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net: phy: remove flag PHY_HAS_INTERRUPT from driver configs
[linux-block.git] / drivers / net / phy / marvell.c
CommitLineData
00db8189
AF		 1/*
2 * drivers/net/phy/marvell.c
3 *
4 * Driver for Marvell PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
3871c387
MS		 10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
11 *
00db8189
AF		 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
00db8189 18#include <linux/kernel.h>
00db8189 19#include <linux/string.h>
0b04680f 20#include <linux/ctype.h>
00db8189
AF		 21#include <linux/errno.h>
22#include <linux/unistd.h>
0b04680f 23#include <linux/hwmon.h>
00db8189
AF		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/skbuff.h>
30#include <linux/spinlock.h>
31#include <linux/mm.h>
32#include <linux/module.h>
00db8189
AF		 33#include <linux/mii.h>
34#include <linux/ethtool.h>
35#include <linux/phy.h>
2f495c39 36#include <linux/marvell_phy.h>
cf41a51d 37#include <linux/of.h>
00db8189 38
eea3b201 39#include <linux/io.h>
00db8189 40#include <asm/irq.h>
eea3b201 41#include <linux/uaccess.h>
00db8189 42
27d916d6 43#define MII_MARVELL_PHY_PAGE 22
52295666
AL		 44#define MII_MARVELL_COPPER_PAGE 0x00
45#define MII_MARVELL_FIBER_PAGE 0x01
46#define MII_MARVELL_MSCR_PAGE 0x02
47#define MII_MARVELL_LED_PAGE 0x03
48#define MII_MARVELL_MISC_TEST_PAGE 0x06
49#define MII_MARVELL_WOL_PAGE 0x11
27d916d6 50
00db8189
AF		 51#define MII_M1011_IEVENT 0x13
52#define MII_M1011_IEVENT_CLEAR 0x0000
53
54#define MII_M1011_IMASK 0x12
55#define MII_M1011_IMASK_INIT 0x6400
56#define MII_M1011_IMASK_CLEAR 0x0000
57
fecd5e91
AL		 58#define MII_M1011_PHY_SCR 0x10
59#define MII_M1011_PHY_SCR_DOWNSHIFT_EN BIT(11)
60#define MII_M1011_PHY_SCR_DOWNSHIFT_SHIFT 12
6ef05eb7 61#define MII_M1011_PHY_SRC_DOWNSHIFT_MASK 0x7800
fecd5e91
AL		 62#define MII_M1011_PHY_SCR_MDI (0x0 << 5)
63#define MII_M1011_PHY_SCR_MDI_X (0x1 << 5)
64#define MII_M1011_PHY_SCR_AUTO_CROSS (0x3 << 5)
76884679 65
76884679
AF		 66#define MII_M1111_PHY_LED_CONTROL 0x18
67#define MII_M1111_PHY_LED_DIRECT 0x4100
68#define MII_M1111_PHY_LED_COMBINE 0x411c
895ee682 69#define MII_M1111_PHY_EXT_CR 0x14
61111598
AL		 70#define MII_M1111_RGMII_RX_DELAY BIT(7)
71#define MII_M1111_RGMII_TX_DELAY BIT(1)
895ee682 72#define MII_M1111_PHY_EXT_SR 0x1b
be937f1f
AS		 73
74#define MII_M1111_HWCFG_MODE_MASK 0xf
be937f1f 75#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
4117b5be 76#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
865b813a 77#define MII_M1111_HWCFG_MODE_RTBI 0x7
5f8cbc13 78#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
865b813a
AL		 79#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
80#define MII_M1111_HWCFG_FIBER_COPPER_RES BIT(13)
81#define MII_M1111_HWCFG_FIBER_COPPER_AUTO BIT(15)
be937f1f 82
c477d044
CC		 83#define MII_88E1121_PHY_MSCR_REG 21
84#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
85#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
424ca4c5 86#define MII_88E1121_PHY_MSCR_DELAY_MASK (BIT(5) | BIT(4))
c477d044 87
0b04680f
AL		 88#define MII_88E1121_MISC_TEST 0x1a
89#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
90#define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
91#define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
92#define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
93#define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
94#define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
95
96#define MII_88E1510_TEMP_SENSOR 0x1b
97#define MII_88E1510_TEMP_SENSOR_MASK 0xff
98
fee2d546
AL		 99#define MII_88E6390_MISC_TEST 0x1b
100#define MII_88E6390_MISC_TEST_SAMPLE_1S 0
101#define MII_88E6390_MISC_TEST_SAMPLE_10MS BIT(14)
102#define MII_88E6390_MISC_TEST_SAMPLE_DISABLE BIT(15)
103#define MII_88E6390_MISC_TEST_SAMPLE_ENABLE 0
104#define MII_88E6390_MISC_TEST_SAMPLE_MASK (0x3 << 14)
105
106#define MII_88E6390_TEMP_SENSOR 0x1c
107#define MII_88E6390_TEMP_SENSOR_MASK 0xff
108#define MII_88E6390_TEMP_SENSOR_SAMPLES 10
109
337ac9d5
CC		 110#define MII_88E1318S_PHY_MSCR1_REG 16
111#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
3ff1c259 112
3871c387 113/* Copper Specific Interrupt Enable Register */
8cf8b87b 114#define MII_88E1318S_PHY_CSIER 0x12
3871c387 115/* WOL Event Interrupt Enable */
8cf8b87b 116#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
3871c387
MS		 117
118/* LED Timer Control Register */
8cf8b87b
AL		 119#define MII_88E1318S_PHY_LED_TCR 0x12
120#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
121#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
122#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
3871c387
MS		 123
124/* Magic Packet MAC address registers */
8cf8b87b
AL		 125#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
126#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
127#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
3871c387 128
8cf8b87b
AL		 129#define MII_88E1318S_PHY_WOL_CTRL 0x10
130#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
131#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
3871c387 132
07777246 133#define MII_PHY_LED_CTRL 16
140bc929 134#define MII_88E1121_PHY_LED_DEF 0x0030
07777246 135#define MII_88E1510_PHY_LED_DEF 0x1177
140bc929 136
be937f1f
AS		 137#define MII_M1011_PHY_STATUS 0x11
138#define MII_M1011_PHY_STATUS_1000 0x8000
139#define MII_M1011_PHY_STATUS_100 0x4000
140#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
141#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
142#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
143#define MII_M1011_PHY_STATUS_LINK 0x0400
144
6b358aed
SH		 145#define MII_88E3016_PHY_SPEC_CTRL 0x10
146#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
147#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
76884679 148
930b37ee
SR		 149#define MII_88E1510_GEN_CTRL_REG_1 0x14
150#define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
151#define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
152#define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
153
6cfb3bcc
CAC		 154#define LPA_FIBER_1000HALF 0x40
155#define LPA_FIBER_1000FULL 0x20
156
8cf8b87b 157#define LPA_PAUSE_FIBER 0x180
6cfb3bcc
CAC		 158#define LPA_PAUSE_ASYM_FIBER 0x100
159
160#define ADVERTISE_FIBER_1000HALF 0x40
161#define ADVERTISE_FIBER_1000FULL 0x20
162
163#define ADVERTISE_PAUSE_FIBER 0x180
164#define ADVERTISE_PAUSE_ASYM_FIBER 0x100
165
166#define REGISTER_LINK_STATUS 0x400
2170fef7 167#define NB_FIBER_STATS 1
6cfb3bcc 168
00db8189
AF		 169MODULE_DESCRIPTION("Marvell PHY driver");
170MODULE_AUTHOR("Andy Fleming");
171MODULE_LICENSE("GPL");
172
d2fa47d9
AL		 173struct marvell_hw_stat {
174 const char *string;
175 u8 page;
176 u8 reg;
177 u8 bits;
178};
179
180static struct marvell_hw_stat marvell_hw_stats[] = {
2170fef7 181 { "phy_receive_errors_copper", 0, 21, 16},
d2fa47d9 182 { "phy_idle_errors", 0, 10, 8 },
2170fef7 183 { "phy_receive_errors_fiber", 1, 21, 16},
d2fa47d9
AL		 184};
185
186struct marvell_priv {
187 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
0b04680f
AL		 188 char *hwmon_name;
189 struct device *hwmon_dev;
d2fa47d9
AL		 190};
191
424ca4c5 192static int marvell_read_page(struct phy_device *phydev)
6427bb2d 193{
424ca4c5 194 return __phy_read(phydev, MII_MARVELL_PHY_PAGE);
6427bb2d
AL		 195}
196
424ca4c5 197static int marvell_write_page(struct phy_device *phydev, int page)
6427bb2d 198{
424ca4c5 199 return __phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
6427bb2d
AL		 200}
201
424ca4c5 202static int marvell_set_page(struct phy_device *phydev, int page)
53798328 203{
424ca4c5 204 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
53798328
AL		 205}
206
00db8189
AF		 207static int marvell_ack_interrupt(struct phy_device *phydev)
208{
209 int err;
210
211 /* Clear the interrupts by reading the reg */
212 err = phy_read(phydev, MII_M1011_IEVENT);
213
214 if (err < 0)
215 return err;
216
217 return 0;
218}
219
220static int marvell_config_intr(struct phy_device *phydev)
221{
222 int err;
223
76884679 224 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
23beb38f
AL		 225 err = phy_write(phydev, MII_M1011_IMASK,
226 MII_M1011_IMASK_INIT);
00db8189 227 else
23beb38f
AL		 228 err = phy_write(phydev, MII_M1011_IMASK,
229 MII_M1011_IMASK_CLEAR);
00db8189
AF		 230
231 return err;
232}
233
239aa55b
DT		 234static int marvell_set_polarity(struct phy_device *phydev, int polarity)
235{
236 int reg;
237 int err;
238 int val;
239
240 /* get the current settings */
241 reg = phy_read(phydev, MII_M1011_PHY_SCR);
242 if (reg < 0)
243 return reg;
244
245 val = reg;
246 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
247 switch (polarity) {
248 case ETH_TP_MDI:
249 val |= MII_M1011_PHY_SCR_MDI;
250 break;
251 case ETH_TP_MDI_X:
252 val |= MII_M1011_PHY_SCR_MDI_X;
253 break;
254 case ETH_TP_MDI_AUTO:
255 case ETH_TP_MDI_INVALID:
256 default:
257 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
258 break;
259 }
260
261 if (val != reg) {
262 /* Set the new polarity value in the register */
263 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
264 if (err)
265 return err;
266 }
267
d6ab9336 268 return val != reg;
239aa55b
DT		 269}
270
6ef05eb7
AL		 271static int marvell_set_downshift(struct phy_device *phydev, bool enable,
272 u8 retries)
273{
274 int reg;
275
276 reg = phy_read(phydev, MII_M1011_PHY_SCR);
277 if (reg < 0)
278 return reg;
279
280 reg &= MII_M1011_PHY_SRC_DOWNSHIFT_MASK;
281 reg |= ((retries - 1) << MII_M1011_PHY_SCR_DOWNSHIFT_SHIFT);
282 if (enable)
283 reg |= MII_M1011_PHY_SCR_DOWNSHIFT_EN;
284
285 return phy_write(phydev, MII_M1011_PHY_SCR, reg);
286}
287
00db8189
AF		 288static int marvell_config_aneg(struct phy_device *phydev)
289{
d6ab9336 290 int changed = 0;
00db8189
AF		 291 int err;
292
4e26c5c3 293 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
76884679
AF		 294 if (err < 0)
295 return err;
296
d6ab9336
FF		 297 changed = err;
298
76884679
AF		 299 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
300 MII_M1111_PHY_LED_DIRECT);
301 if (err < 0)
302 return err;
00db8189
AF		 303
304 err = genphy_config_aneg(phydev);
8ff44985
AV		 305 if (err < 0)
306 return err;
00db8189 307
d6ab9336 308 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
0c3439bc 309 /* A write to speed/duplex bits (that is performed by
8ff44985
AV		 310 * genphy_config_aneg() call above) must be followed by
311 * a software reset. Otherwise, the write has no effect.
312 */
34386344 313 err = genphy_soft_reset(phydev);
8ff44985
AV		 314 if (err < 0)
315 return err;
316 }
317
318 return 0;
00db8189
AF		 319}
320
f2899788
AL		 321static int m88e1101_config_aneg(struct phy_device *phydev)
322{
323 int err;
324
325 /* This Marvell PHY has an errata which requires
326 * that certain registers get written in order
327 * to restart autonegotiation
328 */
34386344 329 err = genphy_soft_reset(phydev);
f2899788
AL		 330 if (err < 0)
331 return err;
332
333 err = phy_write(phydev, 0x1d, 0x1f);
334 if (err < 0)
335 return err;
336
337 err = phy_write(phydev, 0x1e, 0x200c);
338 if (err < 0)
339 return err;
340
341 err = phy_write(phydev, 0x1d, 0x5);
342 if (err < 0)
343 return err;
344
345 err = phy_write(phydev, 0x1e, 0);
346 if (err < 0)
347 return err;
348
349 err = phy_write(phydev, 0x1e, 0x100);
350 if (err < 0)
351 return err;
352
353 return marvell_config_aneg(phydev);
354}
355
cf41a51d 356#ifdef CONFIG_OF_MDIO
0c3439bc 357/* Set and/or override some configuration registers based on the
cf41a51d
DD		 358 * marvell,reg-init property stored in the of_node for the phydev.
359 *
360 * marvell,reg-init = <reg-page reg mask value>,...;
361 *
362 * There may be one or more sets of <reg-page reg mask value>:
363 *
364 * reg-page: which register bank to use.
365 * reg: the register.
366 * mask: if non-zero, ANDed with existing register value.
367 * value: ORed with the masked value and written to the regiser.
368 *
369 */
370static int marvell_of_reg_init(struct phy_device *phydev)
371{
372 const __be32 *paddr;
424ca4c5 373 int len, i, saved_page, current_page, ret = 0;
cf41a51d 374
e5a03bfd 375 if (!phydev->mdio.dev.of_node)
cf41a51d
DD		 376 return 0;
377
e5a03bfd
AL		 378 paddr = of_get_property(phydev->mdio.dev.of_node,
379 "marvell,reg-init", &len);
cf41a51d
DD		 380 if (!paddr || len < (4 * sizeof(*paddr)))
381 return 0;
382
424ca4c5 383 saved_page = phy_save_page(phydev);
cf41a51d 384 if (saved_page < 0)
424ca4c5 385 goto err;
cf41a51d
DD		 386 current_page = saved_page;
387
cf41a51d
DD		 388 len /= sizeof(*paddr);
389 for (i = 0; i < len - 3; i += 4) {
6427bb2d 390 u16 page = be32_to_cpup(paddr + i);
cf41a51d
DD		 391 u16 reg = be32_to_cpup(paddr + i + 1);
392 u16 mask = be32_to_cpup(paddr + i + 2);
393 u16 val_bits = be32_to_cpup(paddr + i + 3);
394 int val;
395
6427bb2d
AL		 396 if (page != current_page) {
397 current_page = page;
424ca4c5 398 ret = marvell_write_page(phydev, page);
cf41a51d
DD		 399 if (ret < 0)
400 goto err;
401 }
402
403 val = 0;
404 if (mask) {
424ca4c5 405 val = __phy_read(phydev, reg);
cf41a51d
DD		 406 if (val < 0) {
407 ret = val;
408 goto err;
409 }
410 val &= mask;
411 }
412 val |= val_bits;
413
424ca4c5 414 ret = __phy_write(phydev, reg, val);
cf41a51d
DD		 415 if (ret < 0)
416 goto err;
cf41a51d
DD		 417 }
418err:
424ca4c5 419 return phy_restore_page(phydev, saved_page, ret);
cf41a51d
DD		 420}
421#else
422static int marvell_of_reg_init(struct phy_device *phydev)
423{
424 return 0;
425}
426#endif /* CONFIG_OF_MDIO */
427
864dc729 428static int m88e1121_config_aneg_rgmii_delays(struct phy_device *phydev)
140bc929 429{
424ca4c5 430 int mscr;
864dc729
AL		 431
432 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
424ca4c5
RK		 433 mscr = MII_88E1121_PHY_MSCR_RX_DELAY |
434 MII_88E1121_PHY_MSCR_TX_DELAY;
864dc729 435 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
424ca4c5 436 mscr = MII_88E1121_PHY_MSCR_RX_DELAY;
864dc729 437 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
424ca4c5
RK		 438 mscr = MII_88E1121_PHY_MSCR_TX_DELAY;
439 else
440 mscr = 0;
140bc929 441
424ca4c5
RK		 442 return phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
443 MII_88E1121_PHY_MSCR_REG,
444 MII_88E1121_PHY_MSCR_DELAY_MASK, mscr);
864dc729
AL		 445}
446
447static int m88e1121_config_aneg(struct phy_device *phydev)
448{
d6ab9336 449 int changed = 0;
864dc729
AL		 450 int err = 0;
451
452 if (phy_interface_is_rgmii(phydev)) {
453 err = m88e1121_config_aneg_rgmii_delays(phydev);
fea23fb5 454 if (err < 0)
864dc729
AL		 455 return err;
456 }
457
d6ab9336 458 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
140bc929
SP		 459 if (err < 0)
460 return err;
461
d6ab9336
FF		 462 changed = err;
463
464 err = genphy_config_aneg(phydev);
140bc929
SP		 465 if (err < 0)
466 return err;
467
4b1bd697 468 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
d6ab9336
FF		 469 /* A software reset is used to ensure a "commit" of the
470 * changes is done.
471 */
472 err = genphy_soft_reset(phydev);
473 if (err < 0)
474 return err;
475 }
476
477 return 0;
140bc929
SP		 478}
479
337ac9d5 480static int m88e1318_config_aneg(struct phy_device *phydev)
3ff1c259 481{
424ca4c5 482 int err;
3ff1c259 483
424ca4c5
RK		 484 err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
485 MII_88E1318S_PHY_MSCR1_REG,
486 0, MII_88E1318S_PHY_MSCR1_PAD_ODD);
3ff1c259
CC		 487 if (err < 0)
488 return err;
489
490 return m88e1121_config_aneg(phydev);
491}
492
78301ebe
CAC		 493/**
494 * ethtool_adv_to_fiber_adv_t
495 * @ethadv: the ethtool advertisement settings
496 *
497 * A small helper function that translates ethtool advertisement
498 * settings to phy autonegotiation advertisements for the
499 * MII_ADV register for fiber link.
500 */
501static inline u32 ethtool_adv_to_fiber_adv_t(u32 ethadv)
502{
503 u32 result = 0;
504
505 if (ethadv & ADVERTISED_1000baseT_Half)
506 result |= ADVERTISE_FIBER_1000HALF;
507 if (ethadv & ADVERTISED_1000baseT_Full)
508 result |= ADVERTISE_FIBER_1000FULL;
509
510 if ((ethadv & ADVERTISE_PAUSE_ASYM) && (ethadv & ADVERTISE_PAUSE_CAP))
511 result |= LPA_PAUSE_ASYM_FIBER;
512 else if (ethadv & ADVERTISE_PAUSE_CAP)
513 result |= (ADVERTISE_PAUSE_FIBER
514 & (~ADVERTISE_PAUSE_ASYM_FIBER));
515
516 return result;
517}
518
519/**
520 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
521 * @phydev: target phy_device struct
522 *
523 * Description: If auto-negotiation is enabled, we configure the
524 * advertising, and then restart auto-negotiation. If it is not
525 * enabled, then we write the BMCR. Adapted for fiber link in
526 * some Marvell's devices.
527 */
528static int marvell_config_aneg_fiber(struct phy_device *phydev)
529{
530 int changed = 0;
531 int err;
532 int adv, oldadv;
533 u32 advertise;
534
535 if (phydev->autoneg != AUTONEG_ENABLE)
536 return genphy_setup_forced(phydev);
537
538 /* Only allow advertising what this PHY supports */
539 phydev->advertising &= phydev->supported;
540 advertise = phydev->advertising;
541
542 /* Setup fiber advertisement */
543 adv = phy_read(phydev, MII_ADVERTISE);
544 if (adv < 0)
545 return adv;
546
547 oldadv = adv;
548 adv &= ~(ADVERTISE_FIBER_1000HALF | ADVERTISE_FIBER_1000FULL
549 | LPA_PAUSE_FIBER);
550 adv |= ethtool_adv_to_fiber_adv_t(advertise);
551
552 if (adv != oldadv) {
553 err = phy_write(phydev, MII_ADVERTISE, adv);
554 if (err < 0)
555 return err;
556
557 changed = 1;
558 }
559
560 if (changed == 0) {
561 /* Advertisement hasn't changed, but maybe aneg was never on to
8cf8b87b 562 * begin with? Or maybe phy was isolated?
78301ebe
CAC		 563 */
564 int ctl = phy_read(phydev, MII_BMCR);
565
566 if (ctl < 0)
567 return ctl;
568
569 if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
570 changed = 1; /* do restart aneg */
571 }
572
573 /* Only restart aneg if we are advertising something different
574 * than we were before.
575 */
576 if (changed > 0)
577 changed = genphy_restart_aneg(phydev);
578
579 return changed;
580}
581
10e24caa
MS		 582static int m88e1510_config_aneg(struct phy_device *phydev)
583{
584 int err;
585
52295666 586 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
78301ebe
CAC		 587 if (err < 0)
588 goto error;
589
590 /* Configure the copper link first */
10e24caa
MS		 591 err = m88e1318_config_aneg(phydev);
592 if (err < 0)
78301ebe 593 goto error;
10e24caa 594
de9c4e06
RK		 595 /* Do not touch the fiber page if we're in copper->sgmii mode */
596 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
597 return 0;
598
78301ebe 599 /* Then the fiber link */
52295666 600 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
78301ebe
CAC		 601 if (err < 0)
602 goto error;
603
604 err = marvell_config_aneg_fiber(phydev);
605 if (err < 0)
606 goto error;
607
52295666 608 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
78301ebe
CAC		 609
610error:
52295666 611 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
78301ebe 612 return err;
79be1a1c
CG		 613}
614
07777246
WD		 615static void marvell_config_led(struct phy_device *phydev)
616{
617 u16 def_config;
618 int err;
619
620 switch (MARVELL_PHY_FAMILY_ID(phydev->phy_id)) {
621 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
622 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1121R):
623 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1318S):
624 def_config = MII_88E1121_PHY_LED_DEF;
625 break;
626 /* Default PHY LED config:
627 * LED[0] .. 1000Mbps Link
628 * LED[1] .. 100Mbps Link
629 * LED[2] .. Blink, Activity
630 */
631 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1510):
632 def_config = MII_88E1510_PHY_LED_DEF;
633 break;
634 default:
635 return;
636 }
637
638 err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, MII_PHY_LED_CTRL,
639 def_config);
640 if (err < 0)
ab2a605f 641 phydev_warn(phydev, "Fail to config marvell phy LED.\n");
07777246
WD		 642}
643
79be1a1c
CG		 644static int marvell_config_init(struct phy_device *phydev)
645{
07777246
WD		 646 /* Set defalut LED */
647 marvell_config_led(phydev);
648
79be1a1c 649 /* Set registers from marvell,reg-init DT property */
10e24caa
MS		 650 return marvell_of_reg_init(phydev);
651}
652
3da09a51
MS		 653static int m88e1116r_config_init(struct phy_device *phydev)
654{
3da09a51
MS		 655 int err;
656
34386344 657 err = genphy_soft_reset(phydev);
3da09a51
MS		 658 if (err < 0)
659 return err;
660
0df125d0 661 msleep(500);
3da09a51 662
52295666 663 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3da09a51
MS		 664 if (err < 0)
665 return err;
666
fecd5e91
AL		 667 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
668 if (err < 0)
669 return err;
670
6ef05eb7 671 err = marvell_set_downshift(phydev, true, 8);
3da09a51
MS		 672 if (err < 0)
673 return err;
674
14fc0aba
AL		 675 if (phy_interface_is_rgmii(phydev)) {
676 err = m88e1121_config_aneg_rgmii_delays(phydev);
677 if (err < 0)
678 return err;
679 }
3da09a51 680
34386344 681 err = genphy_soft_reset(phydev);
3da09a51
MS		 682 if (err < 0)
683 return err;
684
79be1a1c 685 return marvell_config_init(phydev);
3da09a51
MS		 686}
687
6b358aed
SH		 688static int m88e3016_config_init(struct phy_device *phydev)
689{
fea23fb5 690 int ret;
6b358aed
SH		 691
692 /* Enable Scrambler and Auto-Crossover */
fea23fb5 693 ret = phy_modify(phydev, MII_88E3016_PHY_SPEC_CTRL,
f102852f 694 MII_88E3016_DISABLE_SCRAMBLER,
fea23fb5
RK		 695 MII_88E3016_AUTO_MDIX_CROSSOVER);
696 if (ret < 0)
697 return ret;
6b358aed 698
79be1a1c 699 return marvell_config_init(phydev);
6b358aed
SH		 700}
701
865b813a
AL		 702static int m88e1111_config_init_hwcfg_mode(struct phy_device *phydev,
703 u16 mode,
704 int fibre_copper_auto)
705{
865b813a 706 if (fibre_copper_auto)
fea23fb5 707 mode |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
865b813a 708
fea23fb5 709 return phy_modify(phydev, MII_M1111_PHY_EXT_SR,
f102852f
RK		 710 MII_M1111_HWCFG_MODE_MASK |
711 MII_M1111_HWCFG_FIBER_COPPER_AUTO |
712 MII_M1111_HWCFG_FIBER_COPPER_RES,
fea23fb5 713 mode);
865b813a
AL		 714}
715
61111598 716static int m88e1111_config_init_rgmii_delays(struct phy_device *phydev)
895ee682 717{
fea23fb5 718 int delay;
895ee682 719
e1dde8dc 720 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
fea23fb5 721 delay = MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY;
e1dde8dc 722 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
fea23fb5 723 delay = MII_M1111_RGMII_RX_DELAY;
e1dde8dc 724 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
fea23fb5
RK		 725 delay = MII_M1111_RGMII_TX_DELAY;
726 } else {
727 delay = 0;
e1dde8dc 728 }
895ee682 729
fea23fb5 730 return phy_modify(phydev, MII_M1111_PHY_EXT_CR,
f102852f 731 MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY,
fea23fb5 732 delay);
61111598
AL		 733}
734
735static int m88e1111_config_init_rgmii(struct phy_device *phydev)
736{
737 int temp;
738 int err;
739
740 err = m88e1111_config_init_rgmii_delays(phydev);
e1dde8dc
AL		 741 if (err < 0)
742 return err;
9daf5a76 743
e1dde8dc
AL		 744 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
745 if (temp < 0)
746 return temp;
895ee682 747
e1dde8dc 748 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
be937f1f 749
e1dde8dc
AL		 750 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
751 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
752 else
753 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
895ee682 754
e1dde8dc
AL		 755 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
756}
895ee682 757
e1dde8dc
AL		 758static int m88e1111_config_init_sgmii(struct phy_device *phydev)
759{
760 int err;
4117b5be 761
865b813a
AL		 762 err = m88e1111_config_init_hwcfg_mode(
763 phydev,
764 MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
765 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
e1dde8dc
AL		 766 if (err < 0)
767 return err;
07151bc9 768
e1dde8dc 769 /* make sure copper is selected */
52295666 770 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
e1dde8dc 771}
5f8cbc13 772
e1dde8dc
AL		 773static int m88e1111_config_init_rtbi(struct phy_device *phydev)
774{
61111598 775 int err;
e1dde8dc 776
61111598 777 err = m88e1111_config_init_rgmii_delays(phydev);
fea23fb5 778 if (err < 0)
e1dde8dc
AL		 779 return err;
780
865b813a
AL		 781 err = m88e1111_config_init_hwcfg_mode(
782 phydev,
783 MII_M1111_HWCFG_MODE_RTBI,
784 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
e1dde8dc
AL		 785 if (err < 0)
786 return err;
787
788 /* soft reset */
34386344 789 err = genphy_soft_reset(phydev);
e1dde8dc
AL		 790 if (err < 0)
791 return err;
792
865b813a
AL		 793 return m88e1111_config_init_hwcfg_mode(
794 phydev,
795 MII_M1111_HWCFG_MODE_RTBI,
796 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
e1dde8dc
AL		 797}
798
799static int m88e1111_config_init(struct phy_device *phydev)
800{
801 int err;
802
803 if (phy_interface_is_rgmii(phydev)) {
804 err = m88e1111_config_init_rgmii(phydev);
fea23fb5 805 if (err < 0)
5f8cbc13 806 return err;
e1dde8dc 807 }
5f8cbc13 808
e1dde8dc
AL		 809 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
810 err = m88e1111_config_init_sgmii(phydev);
5f8cbc13
LYB		 811 if (err < 0)
812 return err;
e1dde8dc 813 }
5f8cbc13 814
e1dde8dc
AL		 815 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
816 err = m88e1111_config_init_rtbi(phydev);
5f8cbc13
LYB		 817 if (err < 0)
818 return err;
819 }
820
cf41a51d
DD		 821 err = marvell_of_reg_init(phydev);
822 if (err < 0)
823 return err;
5f8cbc13 824
34386344 825 return genphy_soft_reset(phydev);
895ee682
KP		 826}
827
dd9a122a
EH		 828static int m88e1318_config_init(struct phy_device *phydev)
829{
830 if (phy_interrupt_is_valid(phydev)) {
831 int err = phy_modify_paged(
832 phydev, MII_MARVELL_LED_PAGE,
833 MII_88E1318S_PHY_LED_TCR,
834 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
835 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
836 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
837 if (err < 0)
838 return err;
839 }
840
07777246 841 return marvell_config_init(phydev);
dd9a122a
EH		 842}
843
407353ec
CG		 844static int m88e1510_config_init(struct phy_device *phydev)
845{
846 int err;
407353ec
CG		 847
848 /* SGMII-to-Copper mode initialization */
849 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
6623c0fb
RK		 850 u32 pause;
851
407353ec 852 /* Select page 18 */
6427bb2d 853 err = marvell_set_page(phydev, 18);
407353ec
CG		 854 if (err < 0)
855 return err;
856
857 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
fea23fb5 858 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
f102852f 859 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
fea23fb5 860 MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII);
407353ec
CG		 861 if (err < 0)
862 return err;
863
864 /* PHY reset is necessary after changing MODE[2:0] */
fea23fb5
RK		 865 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1, 0,
866 MII_88E1510_GEN_CTRL_REG_1_RESET);
407353ec
CG		 867 if (err < 0)
868 return err;
869
870 /* Reset page selection */
52295666 871 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
407353ec
CG		 872 if (err < 0)
873 return err;
6623c0fb
RK		 874
875 /* There appears to be a bug in the 88e1512 when used in
cc1122b0 876 * SGMII to copper mode, where the AN advertisement register
6623c0fb
RK		 877 * clears the pause bits each time a negotiation occurs.
878 * This means we can never be truely sure what was advertised,
879 * so disable Pause support.
880 */
881 pause = SUPPORTED_Pause | SUPPORTED_Asym_Pause;
882 phydev->supported &= ~pause;
883 phydev->advertising &= ~pause;
407353ec
CG		 884 }
885
dd9a122a 886 return m88e1318_config_init(phydev);
407353ec
CG		 887}
888
605f196e
RM		 889static int m88e1118_config_aneg(struct phy_device *phydev)
890{
891 int err;
892
34386344 893 err = genphy_soft_reset(phydev);
605f196e
RM		 894 if (err < 0)
895 return err;
896
fecd5e91 897 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
605f196e
RM		 898 if (err < 0)
899 return err;
900
901 err = genphy_config_aneg(phydev);
902 return 0;
903}
904
905static int m88e1118_config_init(struct phy_device *phydev)
906{
907 int err;
908
909 /* Change address */
52295666 910 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
605f196e
RM		 911 if (err < 0)
912 return err;
913
914 /* Enable 1000 Mbit */
915 err = phy_write(phydev, 0x15, 0x1070);
916 if (err < 0)
917 return err;
918
919 /* Change address */
52295666 920 err = marvell_set_page(phydev, MII_MARVELL_LED_PAGE);
605f196e
RM		 921 if (err < 0)
922 return err;
923
924 /* Adjust LED Control */
2f495c39
BH		 925 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
926 err = phy_write(phydev, 0x10, 0x1100);
927 else
928 err = phy_write(phydev, 0x10, 0x021e);
605f196e
RM		 929 if (err < 0)
930 return err;
931
cf41a51d
DD		 932 err = marvell_of_reg_init(phydev);
933 if (err < 0)
934 return err;
935
605f196e 936 /* Reset address */
52295666 937 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
605f196e
RM		 938 if (err < 0)
939 return err;
940
34386344 941 return genphy_soft_reset(phydev);
605f196e
RM		 942}
943
90600732
DD		 944static int m88e1149_config_init(struct phy_device *phydev)
945{
946 int err;
947
948 /* Change address */
52295666 949 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
90600732
DD		 950 if (err < 0)
951 return err;
952
953 /* Enable 1000 Mbit */
954 err = phy_write(phydev, 0x15, 0x1048);
955 if (err < 0)
956 return err;
957
cf41a51d
DD		 958 err = marvell_of_reg_init(phydev);
959 if (err < 0)
960 return err;
961
90600732 962 /* Reset address */
52295666 963 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
90600732
DD		 964 if (err < 0)
965 return err;
966
34386344 967 return genphy_soft_reset(phydev);
90600732
DD		 968}
969
e1dde8dc
AL		 970static int m88e1145_config_init_rgmii(struct phy_device *phydev)
971{
972 int err;
e1dde8dc 973
61111598 974 err = m88e1111_config_init_rgmii_delays(phydev);
e1dde8dc
AL		 975 if (err < 0)
976 return err;
977
978 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
979 err = phy_write(phydev, 0x1d, 0x0012);
980 if (err < 0)
981 return err;
982
f102852f 983 err = phy_modify(phydev, 0x1e, 0x0fc0,
fea23fb5
RK		 984 2 << 9 | /* 36 ohm */
985 2 << 6); /* 39 ohm */
e1dde8dc
AL		 986 if (err < 0)
987 return err;
988
989 err = phy_write(phydev, 0x1d, 0x3);
990 if (err < 0)
991 return err;
992
993 err = phy_write(phydev, 0x1e, 0x8000);
994 }
995 return err;
996}
997
998static int m88e1145_config_init_sgmii(struct phy_device *phydev)
999{
865b813a
AL		 1000 return m88e1111_config_init_hwcfg_mode(
1001 phydev, MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
1002 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
e1dde8dc
AL		 1003}
1004
76884679
AF		 1005static int m88e1145_config_init(struct phy_device *phydev)
1006{
1007 int err;
1008
1009 /* Take care of errata E0 & E1 */
1010 err = phy_write(phydev, 0x1d, 0x001b);
1011 if (err < 0)
1012 return err;
1013
1014 err = phy_write(phydev, 0x1e, 0x418f);
1015 if (err < 0)
1016 return err;
1017
1018 err = phy_write(phydev, 0x1d, 0x0016);
1019 if (err < 0)
1020 return err;
1021
1022 err = phy_write(phydev, 0x1e, 0xa2da);
1023 if (err < 0)
1024 return err;
1025
895ee682 1026 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
e1dde8dc 1027 err = m88e1145_config_init_rgmii(phydev);
76884679
AF		 1028 if (err < 0)
1029 return err;
76884679
AF		 1030 }
1031
b0224175 1032 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
e1dde8dc 1033 err = m88e1145_config_init_sgmii(phydev);
b0224175
VND		 1034 if (err < 0)
1035 return err;
1036 }
1037
cf41a51d
DD		 1038 err = marvell_of_reg_init(phydev);
1039 if (err < 0)
1040 return err;
1041
76884679
AF		 1042 return 0;
1043}
00db8189 1044
6cfb3bcc
CAC		 1045/**
1046 * fiber_lpa_to_ethtool_lpa_t
1047 * @lpa: value of the MII_LPA register for fiber link
1048 *
1049 * A small helper function that translates MII_LPA
1050 * bits to ethtool LP advertisement settings.
1051 */
1052static u32 fiber_lpa_to_ethtool_lpa_t(u32 lpa)
1053{
1054 u32 result = 0;
1055
1056 if (lpa & LPA_FIBER_1000HALF)
1057 result |= ADVERTISED_1000baseT_Half;
1058 if (lpa & LPA_FIBER_1000FULL)
1059 result |= ADVERTISED_1000baseT_Full;
1060
1061 return result;
1062}
1063
1064/**
1065 * marvell_update_link - update link status in real time in @phydev
1066 * @phydev: target phy_device struct
1067 *
1068 * Description: Update the value in phydev->link to reflect the
1069 * current link value.
1070 */
1071static int marvell_update_link(struct phy_device *phydev, int fiber)
1072{
1073 int status;
1074
1075 /* Use the generic register for copper link, or specific
0c3439bc
AL		 1076 * register for fiber case
1077 */
6cfb3bcc
CAC		 1078 if (fiber) {
1079 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1080 if (status < 0)
1081 return status;
1082
1083 if ((status & REGISTER_LINK_STATUS) == 0)
1084 phydev->link = 0;
1085 else
1086 phydev->link = 1;
1087 } else {
1088 return genphy_update_link(phydev);
1089 }
1090
1091 return 0;
1092}
1093
e1dde8dc
AL		 1094static int marvell_read_status_page_an(struct phy_device *phydev,
1095 int fiber)
1096{
1097 int status;
1098 int lpa;
1099 int lpagb;
e1dde8dc
AL		 1100
1101 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1102 if (status < 0)
1103 return status;
1104
1105 lpa = phy_read(phydev, MII_LPA);
1106 if (lpa < 0)
1107 return lpa;
1108
1109 lpagb = phy_read(phydev, MII_STAT1000);
1110 if (lpagb < 0)
1111 return lpagb;
1112
e1dde8dc
AL		 1113 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1114 phydev->duplex = DUPLEX_FULL;
1115 else
1116 phydev->duplex = DUPLEX_HALF;
1117
1118 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
1119 phydev->pause = 0;
1120 phydev->asym_pause = 0;
1121
1122 switch (status) {
1123 case MII_M1011_PHY_STATUS_1000:
1124 phydev->speed = SPEED_1000;
1125 break;
1126
1127 case MII_M1011_PHY_STATUS_100:
1128 phydev->speed = SPEED_100;
1129 break;
1130
1131 default:
1132 phydev->speed = SPEED_10;
1133 break;
1134 }
1135
1136 if (!fiber) {
1137 phydev->lp_advertising =
1138 mii_stat1000_to_ethtool_lpa_t(lpagb) |
1139 mii_lpa_to_ethtool_lpa_t(lpa);
1140
1141 if (phydev->duplex == DUPLEX_FULL) {
1142 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
1143 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
1144 }
1145 } else {
1146 /* The fiber link is only 1000M capable */
1147 phydev->lp_advertising = fiber_lpa_to_ethtool_lpa_t(lpa);
1148
1149 if (phydev->duplex == DUPLEX_FULL) {
1150 if (!(lpa & LPA_PAUSE_FIBER)) {
1151 phydev->pause = 0;
1152 phydev->asym_pause = 0;
1153 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1154 phydev->pause = 1;
1155 phydev->asym_pause = 1;
1156 } else {
1157 phydev->pause = 1;
1158 phydev->asym_pause = 0;
1159 }
1160 }
1161 }
1162 return 0;
1163}
1164
1165static int marvell_read_status_page_fixed(struct phy_device *phydev)
1166{
1167 int bmcr = phy_read(phydev, MII_BMCR);
1168
1169 if (bmcr < 0)
1170 return bmcr;
1171
1172 if (bmcr & BMCR_FULLDPLX)
1173 phydev->duplex = DUPLEX_FULL;
1174 else
1175 phydev->duplex = DUPLEX_HALF;
1176
1177 if (bmcr & BMCR_SPEED1000)
1178 phydev->speed = SPEED_1000;
1179 else if (bmcr & BMCR_SPEED100)
1180 phydev->speed = SPEED_100;
1181 else
1182 phydev->speed = SPEED_10;
1183
1184 phydev->pause = 0;
1185 phydev->asym_pause = 0;
1186 phydev->lp_advertising = 0;
1187
1188 return 0;
1189}
1190
6cfb3bcc 1191/* marvell_read_status_page
be937f1f 1192 *
f0c88f9c 1193 * Description:
be937f1f
AS		 1194 * Check the link, then figure out the current state
1195 * by comparing what we advertise with what the link partner
1196 * advertises. Start by checking the gigabit possibilities,
1197 * then move on to 10/100.
1198 */
6cfb3bcc 1199static int marvell_read_status_page(struct phy_device *phydev, int page)
be937f1f 1200{
6cfb3bcc 1201 int fiber;
e1dde8dc 1202 int err;
be937f1f 1203
6cfb3bcc 1204 /* Detect and update the link, but return if there
0c3439bc
AL		 1205 * was an error
1206 */
52295666 1207 if (page == MII_MARVELL_FIBER_PAGE)
6cfb3bcc
CAC		 1208 fiber = 1;
1209 else
1210 fiber = 0;
1211
1212 err = marvell_update_link(phydev, fiber);
be937f1f
AS		 1213 if (err)
1214 return err;
1215
e1dde8dc
AL		 1216 if (phydev->autoneg == AUTONEG_ENABLE)
1217 err = marvell_read_status_page_an(phydev, fiber);
1218 else
1219 err = marvell_read_status_page_fixed(phydev);
be937f1f 1220
e1dde8dc 1221 return err;
be937f1f
AS		 1222}
1223
6cfb3bcc
CAC		 1224/* marvell_read_status
1225 *
1226 * Some Marvell's phys have two modes: fiber and copper.
1227 * Both need status checked.
1228 * Description:
1229 * First, check the fiber link and status.
1230 * If the fiber link is down, check the copper link and status which
1231 * will be the default value if both link are down.
1232 */
1233static int marvell_read_status(struct phy_device *phydev)
1234{
1235 int err;
1236
1237 /* Check the fiber mode first */
a13c0652
RK		 1238 if (phydev->supported & SUPPORTED_FIBRE &&
1239 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
52295666 1240 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
6cfb3bcc
CAC		 1241 if (err < 0)
1242 goto error;
1243
52295666 1244 err = marvell_read_status_page(phydev, MII_MARVELL_FIBER_PAGE);
6cfb3bcc
CAC		 1245 if (err < 0)
1246 goto error;
1247
0c3439bc
AL		 1248 /* If the fiber link is up, it is the selected and
1249 * used link. In this case, we need to stay in the
1250 * fiber page. Please to be careful about that, avoid
1251 * to restore Copper page in other functions which
1252 * could break the behaviour for some fiber phy like
1253 * 88E1512.
1254 */
6cfb3bcc
CAC		 1255 if (phydev->link)
1256 return 0;
1257
1258 /* If fiber link is down, check and save copper mode state */
52295666 1259 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
6cfb3bcc
CAC		 1260 if (err < 0)
1261 goto error;
1262 }
1263
52295666 1264 return marvell_read_status_page(phydev, MII_MARVELL_COPPER_PAGE);
6cfb3bcc
CAC		 1265
1266error:
52295666 1267 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
6cfb3bcc
CAC		 1268 return err;
1269}
3758be3d
CAC		 1270
1271/* marvell_suspend
1272 *
1273 * Some Marvell's phys have two modes: fiber and copper.
1274 * Both need to be suspended
1275 */
1276static int marvell_suspend(struct phy_device *phydev)
1277{
1278 int err;
1279
1280 /* Suspend the fiber mode first */
1281 if (!(phydev->supported & SUPPORTED_FIBRE)) {
52295666 1282 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
3758be3d
CAC		 1283 if (err < 0)
1284 goto error;
1285
1286 /* With the page set, use the generic suspend */
1287 err = genphy_suspend(phydev);
1288 if (err < 0)
1289 goto error;
1290
1291 /* Then, the copper link */
52295666 1292 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3758be3d
CAC		 1293 if (err < 0)
1294 goto error;
1295 }
1296
1297 /* With the page set, use the generic suspend */
1298 return genphy_suspend(phydev);
1299
1300error:
52295666 1301 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3758be3d
CAC		 1302 return err;
1303}
1304
1305/* marvell_resume
1306 *
1307 * Some Marvell's phys have two modes: fiber and copper.
1308 * Both need to be resumed
1309 */
1310static int marvell_resume(struct phy_device *phydev)
1311{
1312 int err;
1313
1314 /* Resume the fiber mode first */
1315 if (!(phydev->supported & SUPPORTED_FIBRE)) {
52295666 1316 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
3758be3d
CAC		 1317 if (err < 0)
1318 goto error;
1319
1320 /* With the page set, use the generic resume */
1321 err = genphy_resume(phydev);
1322 if (err < 0)
1323 goto error;
1324
1325 /* Then, the copper link */
52295666 1326 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3758be3d
CAC		 1327 if (err < 0)
1328 goto error;
1329 }
1330
1331 /* With the page set, use the generic resume */
1332 return genphy_resume(phydev);
1333
1334error:
52295666 1335 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
3758be3d
CAC		 1336 return err;
1337}
1338
6b358aed
SH		 1339static int marvell_aneg_done(struct phy_device *phydev)
1340{
1341 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
e69d9ed4 1342
6b358aed
SH		 1343 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1344}
1345
dcd07be3
AG		 1346static int m88e1121_did_interrupt(struct phy_device *phydev)
1347{
1348 int imask;
1349
1350 imask = phy_read(phydev, MII_M1011_IEVENT);
1351
1352 if (imask & MII_M1011_IMASK_INIT)
1353 return 1;
1354
1355 return 0;
1356}
1357
23beb38f
AL		 1358static void m88e1318_get_wol(struct phy_device *phydev,
1359 struct ethtool_wolinfo *wol)
3871c387 1360{
424ca4c5
RK		 1361 int oldpage, ret = 0;
1362
3871c387
MS		 1363 wol->supported = WAKE_MAGIC;
1364 wol->wolopts = 0;
1365
424ca4c5
RK		 1366 oldpage = phy_select_page(phydev, MII_MARVELL_WOL_PAGE);
1367 if (oldpage < 0)
1368 goto error;
3871c387 1369
424ca4c5
RK		 1370 ret = __phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1371 if (ret & MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
3871c387
MS		 1372 wol->wolopts |= WAKE_MAGIC;
1373
424ca4c5
RK		 1374error:
1375 phy_restore_page(phydev, oldpage, ret);
3871c387
MS		 1376}
1377
23beb38f
AL		 1378static int m88e1318_set_wol(struct phy_device *phydev,
1379 struct ethtool_wolinfo *wol)
3871c387 1380{
424ca4c5 1381 int err = 0, oldpage;
3871c387 1382
424ca4c5
RK		 1383 oldpage = phy_save_page(phydev);
1384 if (oldpage < 0)
1385 goto error;
3871c387
MS		 1386
1387 if (wol->wolopts & WAKE_MAGIC) {
1388 /* Explicitly switch to page 0x00, just to be sure */
424ca4c5 1389 err = marvell_write_page(phydev, MII_MARVELL_COPPER_PAGE);
3871c387 1390 if (err < 0)
424ca4c5 1391 goto error;
3871c387 1392
b6a930fa
JH		 1393 /* If WOL event happened once, the LED[2] interrupt pin
1394 * will not be cleared unless we reading the interrupt status
1395 * register. If interrupts are in use, the normal interrupt
1396 * handling will clear the WOL event. Clear the WOL event
1397 * before enabling it if !phy_interrupt_is_valid()
1398 */
1399 if (!phy_interrupt_is_valid(phydev))
1400 phy_read(phydev, MII_M1011_IEVENT);
1401
3871c387 1402 /* Enable the WOL interrupt */
424ca4c5
RK		 1403 err = __phy_modify(phydev, MII_88E1318S_PHY_CSIER, 0,
1404 MII_88E1318S_PHY_CSIER_WOL_EIE);
3871c387 1405 if (err < 0)
424ca4c5 1406 goto error;
3871c387 1407
424ca4c5 1408 err = marvell_write_page(phydev, MII_MARVELL_LED_PAGE);
3871c387 1409 if (err < 0)
424ca4c5 1410 goto error;
3871c387
MS		 1411
1412 /* Setup LED[2] as interrupt pin (active low) */
424ca4c5 1413 err = __phy_modify(phydev, MII_88E1318S_PHY_LED_TCR,
f102852f 1414 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
424ca4c5
RK		 1415 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1416 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
3871c387 1417 if (err < 0)
424ca4c5 1418 goto error;
3871c387 1419
424ca4c5 1420 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
3871c387 1421 if (err < 0)
424ca4c5 1422 goto error;
3871c387
MS		 1423
1424 /* Store the device address for the magic packet */
424ca4c5 1425 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
3871c387
MS		 1426 ((phydev->attached_dev->dev_addr[5] << 8) |
1427 phydev->attached_dev->dev_addr[4]));
1428 if (err < 0)
424ca4c5
RK		 1429 goto error;
1430 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
3871c387
MS		 1431 ((phydev->attached_dev->dev_addr[3] << 8) |
1432 phydev->attached_dev->dev_addr[2]));
1433 if (err < 0)
424ca4c5
RK		 1434 goto error;
1435 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
3871c387
MS		 1436 ((phydev->attached_dev->dev_addr[1] << 8) |
1437 phydev->attached_dev->dev_addr[0]));
1438 if (err < 0)
424ca4c5 1439 goto error;
3871c387
MS		 1440
1441 /* Clear WOL status and enable magic packet matching */
424ca4c5
RK		 1442 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL, 0,
1443 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1444 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE);
3871c387 1445 if (err < 0)
424ca4c5 1446 goto error;
3871c387 1447 } else {
424ca4c5 1448 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
3871c387 1449 if (err < 0)
424ca4c5 1450 goto error;
3871c387
MS		 1451
1452 /* Clear WOL status and disable magic packet matching */
424ca4c5 1453 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
f102852f 1454 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE,
424ca4c5 1455 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
3871c387 1456 if (err < 0)
424ca4c5 1457 goto error;
3871c387
MS		 1458 }
1459
424ca4c5
RK		 1460error:
1461 return phy_restore_page(phydev, oldpage, err);
3871c387
MS		 1462}
1463
d2fa47d9
AL		 1464static int marvell_get_sset_count(struct phy_device *phydev)
1465{
2170fef7
CAC		 1466 if (phydev->supported & SUPPORTED_FIBRE)
1467 return ARRAY_SIZE(marvell_hw_stats);
1468 else
1469 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
d2fa47d9
AL		 1470}
1471
1472static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1473{
1474 int i;
1475
1476 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) {
98409b2b
FF		 1477 strlcpy(data + i * ETH_GSTRING_LEN,
1478 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
d2fa47d9
AL		 1479 }
1480}
1481
d2fa47d9
AL		 1482static u64 marvell_get_stat(struct phy_device *phydev, int i)
1483{
1484 struct marvell_hw_stat stat = marvell_hw_stats[i];
1485 struct marvell_priv *priv = phydev->priv;
424ca4c5 1486 int val;
321b4d4b 1487 u64 ret;
d2fa47d9 1488
424ca4c5 1489 val = phy_read_paged(phydev, stat.page, stat.reg);
d2fa47d9 1490 if (val < 0) {
6c3442f5 1491 ret = U64_MAX;
d2fa47d9
AL		 1492 } else {
1493 val = val & ((1 << stat.bits) - 1);
1494 priv->stats[i] += val;
321b4d4b 1495 ret = priv->stats[i];
d2fa47d9
AL		 1496 }
1497
321b4d4b 1498 return ret;
d2fa47d9
AL		 1499}
1500
1501static void marvell_get_stats(struct phy_device *phydev,
1502 struct ethtool_stats *stats, u64 *data)
1503{
1504 int i;
1505
1506 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++)
1507 data[i] = marvell_get_stat(phydev, i);
1508}
1509
0b04680f
AL		 1510#ifdef CONFIG_HWMON
1511static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
1512{
975b388c 1513 int oldpage;
424ca4c5 1514 int ret = 0;
0b04680f
AL		 1515 int val;
1516
1517 *temp = 0;
1518
424ca4c5
RK		 1519 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
1520 if (oldpage < 0)
1521 goto error;
975b388c 1522
0b04680f 1523 /* Enable temperature sensor */
424ca4c5 1524 ret = __phy_read(phydev, MII_88E1121_MISC_TEST);
0b04680f
AL		 1525 if (ret < 0)
1526 goto error;
1527
424ca4c5
RK		 1528 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
1529 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
0b04680f
AL		 1530 if (ret < 0)
1531 goto error;
1532
1533 /* Wait for temperature to stabilize */
1534 usleep_range(10000, 12000);
1535
424ca4c5 1536 val = __phy_read(phydev, MII_88E1121_MISC_TEST);
0b04680f
AL		 1537 if (val < 0) {
1538 ret = val;
1539 goto error;
1540 }
1541
1542 /* Disable temperature sensor */
424ca4c5
RK		 1543 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
1544 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
0b04680f
AL		 1545 if (ret < 0)
1546 goto error;
1547
1548 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
1549
1550error:
424ca4c5 1551 return phy_restore_page(phydev, oldpage, ret);
0b04680f
AL		 1552}
1553
1554static int m88e1121_hwmon_read(struct device *dev,
1555 enum hwmon_sensor_types type,
1556 u32 attr, int channel, long *temp)
1557{
1558 struct phy_device *phydev = dev_get_drvdata(dev);
1559 int err;
1560
1561 switch (attr) {
1562 case hwmon_temp_input:
1563 err = m88e1121_get_temp(phydev, temp);
1564 break;
1565 default:
1566 return -EOPNOTSUPP;
1567 }
1568
1569 return err;
1570}
1571
1572static umode_t m88e1121_hwmon_is_visible(const void *data,
1573 enum hwmon_sensor_types type,
1574 u32 attr, int channel)
1575{
1576 if (type != hwmon_temp)
1577 return 0;
1578
1579 switch (attr) {
1580 case hwmon_temp_input:
1581 return 0444;
1582 default:
1583 return 0;
1584 }
1585}
1586
1587static u32 m88e1121_hwmon_chip_config[] = {
1588 HWMON_C_REGISTER_TZ,
1589 0
1590};
1591
1592static const struct hwmon_channel_info m88e1121_hwmon_chip = {
1593 .type = hwmon_chip,
1594 .config = m88e1121_hwmon_chip_config,
1595};
1596
1597static u32 m88e1121_hwmon_temp_config[] = {
1598 HWMON_T_INPUT,
1599 0
1600};
1601
1602static const struct hwmon_channel_info m88e1121_hwmon_temp = {
1603 .type = hwmon_temp,
1604 .config = m88e1121_hwmon_temp_config,
1605};
1606
1607static const struct hwmon_channel_info *m88e1121_hwmon_info[] = {
1608 &m88e1121_hwmon_chip,
1609 &m88e1121_hwmon_temp,
1610 NULL
1611};
1612
1613static const struct hwmon_ops m88e1121_hwmon_hwmon_ops = {
1614 .is_visible = m88e1121_hwmon_is_visible,
1615 .read = m88e1121_hwmon_read,
1616};
1617
1618static const struct hwmon_chip_info m88e1121_hwmon_chip_info = {
1619 .ops = &m88e1121_hwmon_hwmon_ops,
1620 .info = m88e1121_hwmon_info,
1621};
1622
1623static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
1624{
1625 int ret;
1626
1627 *temp = 0;
1628
424ca4c5
RK		 1629 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
1630 MII_88E1510_TEMP_SENSOR);
0b04680f 1631 if (ret < 0)
424ca4c5 1632 return ret;
0b04680f
AL		 1633
1634 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
1635
424ca4c5 1636 return 0;
0b04680f
AL		 1637}
1638
f0a45816 1639static int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
0b04680f
AL		 1640{
1641 int ret;
1642
1643 *temp = 0;
1644
424ca4c5
RK		 1645 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
1646 MII_88E1121_MISC_TEST);
0b04680f 1647 if (ret < 0)
424ca4c5 1648 return ret;
0b04680f
AL		 1649
1650 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
1651 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
1652 /* convert to mC */
1653 *temp *= 1000;
1654
424ca4c5 1655 return 0;
0b04680f
AL		 1656}
1657
f0a45816 1658static int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
0b04680f 1659{
0b04680f
AL		 1660 temp = temp / 1000;
1661 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
0b04680f 1662
424ca4c5
RK		 1663 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
1664 MII_88E1121_MISC_TEST,
1665 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK,
1666 temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT);
0b04680f
AL		 1667}
1668
f0a45816 1669static int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
0b04680f
AL		 1670{
1671 int ret;
1672
1673 *alarm = false;
1674
424ca4c5
RK		 1675 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
1676 MII_88E1121_MISC_TEST);
0b04680f 1677 if (ret < 0)
424ca4c5 1678 return ret;
0b04680f 1679
424ca4c5 1680 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
0b04680f 1681
424ca4c5 1682 return 0;
0b04680f
AL		 1683}
1684
1685static int m88e1510_hwmon_read(struct device *dev,
1686 enum hwmon_sensor_types type,
1687 u32 attr, int channel, long *temp)
1688{
1689 struct phy_device *phydev = dev_get_drvdata(dev);
1690 int err;
1691
1692 switch (attr) {
1693 case hwmon_temp_input:
1694 err = m88e1510_get_temp(phydev, temp);
1695 break;
1696 case hwmon_temp_crit:
1697 err = m88e1510_get_temp_critical(phydev, temp);
1698 break;
1699 case hwmon_temp_max_alarm:
1700 err = m88e1510_get_temp_alarm(phydev, temp);
1701 break;
1702 default:
1703 return -EOPNOTSUPP;
1704 }
1705
1706 return err;
1707}
1708
1709static int m88e1510_hwmon_write(struct device *dev,
1710 enum hwmon_sensor_types type,
1711 u32 attr, int channel, long temp)
1712{
1713 struct phy_device *phydev = dev_get_drvdata(dev);
1714 int err;
1715
1716 switch (attr) {
1717 case hwmon_temp_crit:
1718 err = m88e1510_set_temp_critical(phydev, temp);
1719 break;
1720 default:
1721 return -EOPNOTSUPP;
1722 }
1723 return err;
1724}
1725
1726static umode_t m88e1510_hwmon_is_visible(const void *data,
1727 enum hwmon_sensor_types type,
1728 u32 attr, int channel)
1729{
1730 if (type != hwmon_temp)
1731 return 0;
1732
1733 switch (attr) {
1734 case hwmon_temp_input:
1735 case hwmon_temp_max_alarm:
1736 return 0444;
1737 case hwmon_temp_crit:
1738 return 0644;
1739 default:
1740 return 0;
1741 }
1742}
1743
1744static u32 m88e1510_hwmon_temp_config[] = {
1745 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
1746 0
1747};
1748
1749static const struct hwmon_channel_info m88e1510_hwmon_temp = {
1750 .type = hwmon_temp,
1751 .config = m88e1510_hwmon_temp_config,
1752};
1753
1754static const struct hwmon_channel_info *m88e1510_hwmon_info[] = {
1755 &m88e1121_hwmon_chip,
1756 &m88e1510_hwmon_temp,
1757 NULL
1758};
1759
1760static const struct hwmon_ops m88e1510_hwmon_hwmon_ops = {
1761 .is_visible = m88e1510_hwmon_is_visible,
1762 .read = m88e1510_hwmon_read,
1763 .write = m88e1510_hwmon_write,
1764};
1765
1766static const struct hwmon_chip_info m88e1510_hwmon_chip_info = {
1767 .ops = &m88e1510_hwmon_hwmon_ops,
1768 .info = m88e1510_hwmon_info,
1769};
1770
fee2d546
AL		 1771static int m88e6390_get_temp(struct phy_device *phydev, long *temp)
1772{
1773 int sum = 0;
1774 int oldpage;
1775 int ret = 0;
1776 int i;
1777
1778 *temp = 0;
1779
1780 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
1781 if (oldpage < 0)
1782 goto error;
1783
1784 /* Enable temperature sensor */
1785 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
1786 if (ret < 0)
1787 goto error;
1788
1789 ret = ret & ~MII_88E6390_MISC_TEST_SAMPLE_MASK;
1790 ret |= MII_88E6390_MISC_TEST_SAMPLE_ENABLE |
1791 MII_88E6390_MISC_TEST_SAMPLE_1S;
1792
1793 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
1794 if (ret < 0)
1795 goto error;
1796
1797 /* Wait for temperature to stabilize */
1798 usleep_range(10000, 12000);
1799
1800 /* Reading the temperature sense has an errata. You need to read
1801 * a number of times and take an average.
1802 */
1803 for (i = 0; i < MII_88E6390_TEMP_SENSOR_SAMPLES; i++) {
1804 ret = __phy_read(phydev, MII_88E6390_TEMP_SENSOR);
1805 if (ret < 0)
1806 goto error;
1807 sum += ret & MII_88E6390_TEMP_SENSOR_MASK;
1808 }
1809
1810 sum /= MII_88E6390_TEMP_SENSOR_SAMPLES;
1811 *temp = (sum - 75) * 1000;
1812
1813 /* Disable temperature sensor */
1814 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
1815 if (ret < 0)
1816 goto error;
1817
1818 ret = ret & ~MII_88E6390_MISC_TEST_SAMPLE_MASK;
1819 ret |= MII_88E6390_MISC_TEST_SAMPLE_DISABLE;
1820
1821 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
1822
1823error:
1824 phy_restore_page(phydev, oldpage, ret);
1825
1826 return ret;
1827}
1828
1829static int m88e6390_hwmon_read(struct device *dev,
1830 enum hwmon_sensor_types type,
1831 u32 attr, int channel, long *temp)
1832{
1833 struct phy_device *phydev = dev_get_drvdata(dev);
1834 int err;
1835
1836 switch (attr) {
1837 case hwmon_temp_input:
1838 err = m88e6390_get_temp(phydev, temp);
1839 break;
1840 default:
1841 return -EOPNOTSUPP;
1842 }
1843
1844 return err;
1845}
1846
1847static umode_t m88e6390_hwmon_is_visible(const void *data,
1848 enum hwmon_sensor_types type,
1849 u32 attr, int channel)
1850{
1851 if (type != hwmon_temp)
1852 return 0;
1853
1854 switch (attr) {
1855 case hwmon_temp_input:
1856 return 0444;
1857 default:
1858 return 0;
1859 }
1860}
1861
1862static u32 m88e6390_hwmon_temp_config[] = {
1863 HWMON_T_INPUT,
1864 0
1865};
1866
1867static const struct hwmon_channel_info m88e6390_hwmon_temp = {
1868 .type = hwmon_temp,
1869 .config = m88e6390_hwmon_temp_config,
1870};
1871
1872static const struct hwmon_channel_info *m88e6390_hwmon_info[] = {
1873 &m88e1121_hwmon_chip,
1874 &m88e6390_hwmon_temp,
1875 NULL
1876};
1877
1878static const struct hwmon_ops m88e6390_hwmon_hwmon_ops = {
1879 .is_visible = m88e6390_hwmon_is_visible,
1880 .read = m88e6390_hwmon_read,
1881};
1882
1883static const struct hwmon_chip_info m88e6390_hwmon_chip_info = {
1884 .ops = &m88e6390_hwmon_hwmon_ops,
1885 .info = m88e6390_hwmon_info,
1886};
1887
0b04680f
AL		 1888static int marvell_hwmon_name(struct phy_device *phydev)
1889{
1890 struct marvell_priv *priv = phydev->priv;
1891 struct device *dev = &phydev->mdio.dev;
1892 const char *devname = dev_name(dev);
1893 size_t len = strlen(devname);
1894 int i, j;
1895
1896 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
1897 if (!priv->hwmon_name)
1898 return -ENOMEM;
1899
1900 for (i = j = 0; i < len && devname[i]; i++) {
1901 if (isalnum(devname[i]))
1902 priv->hwmon_name[j++] = devname[i];
1903 }
1904
1905 return 0;
1906}
1907
1908static int marvell_hwmon_probe(struct phy_device *phydev,
1909 const struct hwmon_chip_info *chip)
1910{
1911 struct marvell_priv *priv = phydev->priv;
1912 struct device *dev = &phydev->mdio.dev;
1913 int err;
1914
1915 err = marvell_hwmon_name(phydev);
1916 if (err)
1917 return err;
1918
1919 priv->hwmon_dev = devm_hwmon_device_register_with_info(
1920 dev, priv->hwmon_name, phydev, chip, NULL);
1921
1922 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
1923}
1924
1925static int m88e1121_hwmon_probe(struct phy_device *phydev)
1926{
1927 return marvell_hwmon_probe(phydev, &m88e1121_hwmon_chip_info);
1928}
1929
1930static int m88e1510_hwmon_probe(struct phy_device *phydev)
1931{
1932 return marvell_hwmon_probe(phydev, &m88e1510_hwmon_chip_info);
1933}
fee2d546
AL		 1934
1935static int m88e6390_hwmon_probe(struct phy_device *phydev)
1936{
1937 return marvell_hwmon_probe(phydev, &m88e6390_hwmon_chip_info);
1938}
0b04680f
AL		 1939#else
1940static int m88e1121_hwmon_probe(struct phy_device *phydev)
1941{
1942 return 0;
1943}
1944
1945static int m88e1510_hwmon_probe(struct phy_device *phydev)
1946{
1947 return 0;
1948}
fee2d546
AL		 1949
1950static int m88e6390_hwmon_probe(struct phy_device *phydev)
1951{
1952 return 0;
1953}
0b04680f
AL		 1954#endif
1955
d2fa47d9
AL		 1956static int marvell_probe(struct phy_device *phydev)
1957{
1958 struct marvell_priv *priv;
1959
e5a03bfd 1960 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
d2fa47d9
AL		 1961 if (!priv)
1962 return -ENOMEM;
1963
1964 phydev->priv = priv;
1965
1966 return 0;
1967}
1968
0b04680f
AL		 1969static int m88e1121_probe(struct phy_device *phydev)
1970{
1971 int err;
1972
1973 err = marvell_probe(phydev);
1974 if (err)
1975 return err;
1976
1977 return m88e1121_hwmon_probe(phydev);
1978}
1979
1980static int m88e1510_probe(struct phy_device *phydev)
1981{
1982 int err;
1983
1984 err = marvell_probe(phydev);
1985 if (err)
1986 return err;
1987
1988 return m88e1510_hwmon_probe(phydev);
1989}
1990
fee2d546
AL		 1991static int m88e6390_probe(struct phy_device *phydev)
1992{
1993 int err;
1994
1995 err = marvell_probe(phydev);
1996 if (err)
1997 return err;
1998
1999 return m88e6390_hwmon_probe(phydev);
2000}
2001
e5479239
OJ		 2002static struct phy_driver marvell_drivers[] = {
2003 {
2f495c39
BH		 2004 .phy_id = MARVELL_PHY_ID_88E1101,
2005 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 2006 .name = "Marvell 88E1101",
2007 .features = PHY_GBIT_FEATURES,
18702414 2008 .probe = marvell_probe,
79be1a1c 2009 .config_init = &marvell_config_init,
f2899788 2010 .config_aneg = &m88e1101_config_aneg,
e5479239
OJ		 2011 .ack_interrupt = &marvell_ack_interrupt,
2012 .config_intr = &marvell_config_intr,
0898b448
SH		 2013 .resume = &genphy_resume,
2014 .suspend = &genphy_suspend,
424ca4c5
RK		 2015 .read_page = marvell_read_page,
2016 .write_page = marvell_write_page,
d2fa47d9
AL		 2017 .get_sset_count = marvell_get_sset_count,
2018 .get_strings = marvell_get_strings,
2019 .get_stats = marvell_get_stats,
e5479239 2020 },
85cfb534 2021 {
2f495c39
BH		 2022 .phy_id = MARVELL_PHY_ID_88E1112,
2023 .phy_id_mask = MARVELL_PHY_ID_MASK,
85cfb534
OJ		 2024 .name = "Marvell 88E1112",
2025 .features = PHY_GBIT_FEATURES,
d2fa47d9 2026 .probe = marvell_probe,
85cfb534
OJ		 2027 .config_init = &m88e1111_config_init,
2028 .config_aneg = &marvell_config_aneg,
85cfb534
OJ		 2029 .ack_interrupt = &marvell_ack_interrupt,
2030 .config_intr = &marvell_config_intr,
0898b448
SH		 2031 .resume = &genphy_resume,
2032 .suspend = &genphy_suspend,
424ca4c5
RK		 2033 .read_page = marvell_read_page,
2034 .write_page = marvell_write_page,
d2fa47d9
AL		 2035 .get_sset_count = marvell_get_sset_count,
2036 .get_strings = marvell_get_strings,
2037 .get_stats = marvell_get_stats,
85cfb534 2038 },
e5479239 2039 {
2f495c39
BH		 2040 .phy_id = MARVELL_PHY_ID_88E1111,
2041 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 2042 .name = "Marvell 88E1111",
2043 .features = PHY_GBIT_FEATURES,
d2fa47d9 2044 .probe = marvell_probe,
e5479239 2045 .config_init = &m88e1111_config_init,
d6ab9336 2046 .config_aneg = &marvell_config_aneg,
be937f1f 2047 .read_status = &marvell_read_status,
e5479239
OJ		 2048 .ack_interrupt = &marvell_ack_interrupt,
2049 .config_intr = &marvell_config_intr,
0898b448
SH		 2050 .resume = &genphy_resume,
2051 .suspend = &genphy_suspend,
424ca4c5
RK		 2052 .read_page = marvell_read_page,
2053 .write_page = marvell_write_page,
d2fa47d9
AL		 2054 .get_sset_count = marvell_get_sset_count,
2055 .get_strings = marvell_get_strings,
2056 .get_stats = marvell_get_stats,
e5479239 2057 },
605f196e 2058 {
2f495c39
BH		 2059 .phy_id = MARVELL_PHY_ID_88E1118,
2060 .phy_id_mask = MARVELL_PHY_ID_MASK,
605f196e
RM		 2061 .name = "Marvell 88E1118",
2062 .features = PHY_GBIT_FEATURES,
d2fa47d9 2063 .probe = marvell_probe,
605f196e
RM		 2064 .config_init = &m88e1118_config_init,
2065 .config_aneg = &m88e1118_config_aneg,
605f196e
RM		 2066 .ack_interrupt = &marvell_ack_interrupt,
2067 .config_intr = &marvell_config_intr,
0898b448
SH		 2068 .resume = &genphy_resume,
2069 .suspend = &genphy_suspend,
424ca4c5
RK		 2070 .read_page = marvell_read_page,
2071 .write_page = marvell_write_page,
d2fa47d9
AL		 2072 .get_sset_count = marvell_get_sset_count,
2073 .get_strings = marvell_get_strings,
2074 .get_stats = marvell_get_stats,
605f196e 2075 },
140bc929 2076 {
2f495c39
BH		 2077 .phy_id = MARVELL_PHY_ID_88E1121R,
2078 .phy_id_mask = MARVELL_PHY_ID_MASK,
140bc929
SP		 2079 .name = "Marvell 88E1121R",
2080 .features = PHY_GBIT_FEATURES,
18702414 2081 .probe = &m88e1121_probe,
07777246 2082 .config_init = &marvell_config_init,
140bc929
SP		 2083 .config_aneg = &m88e1121_config_aneg,
2084 .read_status = &marvell_read_status,
2085 .ack_interrupt = &marvell_ack_interrupt,
2086 .config_intr = &marvell_config_intr,
dcd07be3 2087 .did_interrupt = &m88e1121_did_interrupt,
0898b448
SH		 2088 .resume = &genphy_resume,
2089 .suspend = &genphy_suspend,
424ca4c5
RK		 2090 .read_page = marvell_read_page,
2091 .write_page = marvell_write_page,
d2fa47d9
AL		 2092 .get_sset_count = marvell_get_sset_count,
2093 .get_strings = marvell_get_strings,
2094 .get_stats = marvell_get_stats,
140bc929 2095 },
3ff1c259 2096 {
337ac9d5 2097 .phy_id = MARVELL_PHY_ID_88E1318S,
6ba74014 2098 .phy_id_mask = MARVELL_PHY_ID_MASK,
337ac9d5 2099 .name = "Marvell 88E1318S",
3ff1c259 2100 .features = PHY_GBIT_FEATURES,
d2fa47d9 2101 .probe = marvell_probe,
dd9a122a 2102 .config_init = &m88e1318_config_init,
337ac9d5 2103 .config_aneg = &m88e1318_config_aneg,
3ff1c259
CC		 2104 .read_status = &marvell_read_status,
2105 .ack_interrupt = &marvell_ack_interrupt,
2106 .config_intr = &marvell_config_intr,
2107 .did_interrupt = &m88e1121_did_interrupt,
3871c387
MS		 2108 .get_wol = &m88e1318_get_wol,
2109 .set_wol = &m88e1318_set_wol,
0898b448
SH		 2110 .resume = &genphy_resume,
2111 .suspend = &genphy_suspend,
424ca4c5
RK		 2112 .read_page = marvell_read_page,
2113 .write_page = marvell_write_page,
d2fa47d9
AL		 2114 .get_sset_count = marvell_get_sset_count,
2115 .get_strings = marvell_get_strings,
2116 .get_stats = marvell_get_stats,
3ff1c259 2117 },
e5479239 2118 {
2f495c39
BH		 2119 .phy_id = MARVELL_PHY_ID_88E1145,
2120 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 2121 .name = "Marvell 88E1145",
2122 .features = PHY_GBIT_FEATURES,
d2fa47d9 2123 .probe = marvell_probe,
e5479239 2124 .config_init = &m88e1145_config_init,
c505873e 2125 .config_aneg = &m88e1101_config_aneg,
e5479239
OJ		 2126 .read_status = &genphy_read_status,
2127 .ack_interrupt = &marvell_ack_interrupt,
2128 .config_intr = &marvell_config_intr,
0898b448
SH		 2129 .resume = &genphy_resume,
2130 .suspend = &genphy_suspend,
424ca4c5
RK		 2131 .read_page = marvell_read_page,
2132 .write_page = marvell_write_page,
d2fa47d9
AL		 2133 .get_sset_count = marvell_get_sset_count,
2134 .get_strings = marvell_get_strings,
2135 .get_stats = marvell_get_stats,
ac8c635a 2136 },
90600732
DD		 2137 {
2138 .phy_id = MARVELL_PHY_ID_88E1149R,
2139 .phy_id_mask = MARVELL_PHY_ID_MASK,
2140 .name = "Marvell 88E1149R",
2141 .features = PHY_GBIT_FEATURES,
d2fa47d9 2142 .probe = marvell_probe,
90600732
DD		 2143 .config_init = &m88e1149_config_init,
2144 .config_aneg = &m88e1118_config_aneg,
90600732
DD		 2145 .ack_interrupt = &marvell_ack_interrupt,
2146 .config_intr = &marvell_config_intr,
0898b448
SH		 2147 .resume = &genphy_resume,
2148 .suspend = &genphy_suspend,
424ca4c5
RK		 2149 .read_page = marvell_read_page,
2150 .write_page = marvell_write_page,
d2fa47d9
AL		 2151 .get_sset_count = marvell_get_sset_count,
2152 .get_strings = marvell_get_strings,
2153 .get_stats = marvell_get_stats,
90600732 2154 },
ac8c635a 2155 {
2f495c39
BH		 2156 .phy_id = MARVELL_PHY_ID_88E1240,
2157 .phy_id_mask = MARVELL_PHY_ID_MASK,
ac8c635a
OJ		 2158 .name = "Marvell 88E1240",
2159 .features = PHY_GBIT_FEATURES,
d2fa47d9 2160 .probe = marvell_probe,
ac8c635a
OJ		 2161 .config_init = &m88e1111_config_init,
2162 .config_aneg = &marvell_config_aneg,
ac8c635a
OJ		 2163 .ack_interrupt = &marvell_ack_interrupt,
2164 .config_intr = &marvell_config_intr,
0898b448
SH		 2165 .resume = &genphy_resume,
2166 .suspend = &genphy_suspend,
424ca4c5
RK		 2167 .read_page = marvell_read_page,
2168 .write_page = marvell_write_page,
d2fa47d9
AL		 2169 .get_sset_count = marvell_get_sset_count,
2170 .get_strings = marvell_get_strings,
2171 .get_stats = marvell_get_stats,
ac8c635a 2172 },
3da09a51
MS		 2173 {
2174 .phy_id = MARVELL_PHY_ID_88E1116R,
2175 .phy_id_mask = MARVELL_PHY_ID_MASK,
2176 .name = "Marvell 88E1116R",
2177 .features = PHY_GBIT_FEATURES,
d2fa47d9 2178 .probe = marvell_probe,
3da09a51 2179 .config_init = &m88e1116r_config_init,
3da09a51
MS		 2180 .ack_interrupt = &marvell_ack_interrupt,
2181 .config_intr = &marvell_config_intr,
0898b448
SH		 2182 .resume = &genphy_resume,
2183 .suspend = &genphy_suspend,
424ca4c5
RK		 2184 .read_page = marvell_read_page,
2185 .write_page = marvell_write_page,
d2fa47d9
AL		 2186 .get_sset_count = marvell_get_sset_count,
2187 .get_strings = marvell_get_strings,
2188 .get_stats = marvell_get_stats,
3da09a51 2189 },
10e24caa
MS		 2190 {
2191 .phy_id = MARVELL_PHY_ID_88E1510,
2192 .phy_id_mask = MARVELL_PHY_ID_MASK,
2193 .name = "Marvell 88E1510",
719655a1 2194 .features = PHY_GBIT_FIBRE_FEATURES,
0b04680f 2195 .probe = &m88e1510_probe,
930b37ee 2196 .config_init = &m88e1510_config_init,
10e24caa
MS		 2197 .config_aneg = &m88e1510_config_aneg,
2198 .read_status = &marvell_read_status,
2199 .ack_interrupt = &marvell_ack_interrupt,
2200 .config_intr = &marvell_config_intr,
2201 .did_interrupt = &m88e1121_did_interrupt,
f39aac7e
JH		 2202 .get_wol = &m88e1318_get_wol,
2203 .set_wol = &m88e1318_set_wol,
3758be3d
CAC		 2204 .resume = &marvell_resume,
2205 .suspend = &marvell_suspend,
424ca4c5
RK		 2206 .read_page = marvell_read_page,
2207 .write_page = marvell_write_page,
d2fa47d9
AL		 2208 .get_sset_count = marvell_get_sset_count,
2209 .get_strings = marvell_get_strings,
2210 .get_stats = marvell_get_stats,
f0f9b4ed 2211 .set_loopback = genphy_loopback,
10e24caa 2212 },
819ec8e1
AL		 2213 {
2214 .phy_id = MARVELL_PHY_ID_88E1540,
2215 .phy_id_mask = MARVELL_PHY_ID_MASK,
2216 .name = "Marvell 88E1540",
2217 .features = PHY_GBIT_FEATURES,
18702414 2218 .probe = m88e1510_probe,
79be1a1c 2219 .config_init = &marvell_config_init,
819ec8e1
AL		 2220 .config_aneg = &m88e1510_config_aneg,
2221 .read_status = &marvell_read_status,
2222 .ack_interrupt = &marvell_ack_interrupt,
2223 .config_intr = &marvell_config_intr,
2224 .did_interrupt = &m88e1121_did_interrupt,
2225 .resume = &genphy_resume,
2226 .suspend = &genphy_suspend,
424ca4c5
RK		 2227 .read_page = marvell_read_page,
2228 .write_page = marvell_write_page,
d2fa47d9
AL		 2229 .get_sset_count = marvell_get_sset_count,
2230 .get_strings = marvell_get_strings,
2231 .get_stats = marvell_get_stats,
819ec8e1 2232 },
60f06fde
AL		 2233 {
2234 .phy_id = MARVELL_PHY_ID_88E1545,
2235 .phy_id_mask = MARVELL_PHY_ID_MASK,
2236 .name = "Marvell 88E1545",
2237 .probe = m88e1510_probe,
60f06fde 2238 .features = PHY_GBIT_FEATURES,
60f06fde
AL		 2239 .config_init = &marvell_config_init,
2240 .config_aneg = &m88e1510_config_aneg,
2241 .read_status = &marvell_read_status,
2242 .ack_interrupt = &marvell_ack_interrupt,
2243 .config_intr = &marvell_config_intr,
2244 .did_interrupt = &m88e1121_did_interrupt,
2245 .resume = &genphy_resume,
2246 .suspend = &genphy_suspend,
424ca4c5
RK		 2247 .read_page = marvell_read_page,
2248 .write_page = marvell_write_page,
60f06fde
AL		 2249 .get_sset_count = marvell_get_sset_count,
2250 .get_strings = marvell_get_strings,
2251 .get_stats = marvell_get_stats,
2252 },
6b358aed
SH		 2253 {
2254 .phy_id = MARVELL_PHY_ID_88E3016,
2255 .phy_id_mask = MARVELL_PHY_ID_MASK,
2256 .name = "Marvell 88E3016",
2257 .features = PHY_BASIC_FEATURES,
d2fa47d9 2258 .probe = marvell_probe,
6b358aed
SH		 2259 .config_init = &m88e3016_config_init,
2260 .aneg_done = &marvell_aneg_done,
2261 .read_status = &marvell_read_status,
2262 .ack_interrupt = &marvell_ack_interrupt,
2263 .config_intr = &marvell_config_intr,
2264 .did_interrupt = &m88e1121_did_interrupt,
2265 .resume = &genphy_resume,
2266 .suspend = &genphy_suspend,
424ca4c5
RK		 2267 .read_page = marvell_read_page,
2268 .write_page = marvell_write_page,
d2fa47d9
AL		 2269 .get_sset_count = marvell_get_sset_count,
2270 .get_strings = marvell_get_strings,
2271 .get_stats = marvell_get_stats,
6b358aed 2272 },
e4cf8a38
AL		 2273 {
2274 .phy_id = MARVELL_PHY_ID_88E6390,
2275 .phy_id_mask = MARVELL_PHY_ID_MASK,
2276 .name = "Marvell 88E6390",
2277 .features = PHY_GBIT_FEATURES,
fee2d546 2278 .probe = m88e6390_probe,
e4cf8a38
AL		 2279 .config_init = &marvell_config_init,
2280 .config_aneg = &m88e1510_config_aneg,
2281 .read_status = &marvell_read_status,
2282 .ack_interrupt = &marvell_ack_interrupt,
2283 .config_intr = &marvell_config_intr,
2284 .did_interrupt = &m88e1121_did_interrupt,
2285 .resume = &genphy_resume,
2286 .suspend = &genphy_suspend,
424ca4c5
RK		 2287 .read_page = marvell_read_page,
2288 .write_page = marvell_write_page,
e4cf8a38
AL		 2289 .get_sset_count = marvell_get_sset_count,
2290 .get_strings = marvell_get_strings,
2291 .get_stats = marvell_get_stats,
2292 },
00db8189
AF		 2293};
2294
50fd7150 2295module_phy_driver(marvell_drivers);
4e4f10f6 2296
cf93c945 2297static struct mdio_device_id __maybe_unused marvell_tbl[] = {
f5e1cabf
MS		 2298 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
2299 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
2300 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
2301 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
2302 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
2303 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
2304 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
2305 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
2306 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3da09a51 2307 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
10e24caa 2308 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
819ec8e1 2309 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
60f06fde 2310 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
6b358aed 2311 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
e4cf8a38 2312 { MARVELL_PHY_ID_88E6390, MARVELL_PHY_ID_MASK },
4e4f10f6
DW		 2313 { }
2314};
2315
2316MODULE_DEVICE_TABLE(mdio, marvell_tbl);
Linux 6.x block layer and io_uring tree(s)