projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branches 'asoc/fix/rt5677', 'asoc/fix/st', 'asoc/fix/sun4i...
[linux-2.6-block.git] / drivers / net / phy / marvell.c
CommitLineData
00db8189
AF		 1/*
2 * drivers/net/phy/marvell.c
3 *
4 * Driver for Marvell PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
3871c387
MS		 10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
11 *
00db8189
AF		 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
00db8189 18#include <linux/kernel.h>
00db8189
AF		 19#include <linux/string.h>
20#include <linux/errno.h>
21#include <linux/unistd.h>
00db8189
AF		 22#include <linux/interrupt.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/spinlock.h>
29#include <linux/mm.h>
30#include <linux/module.h>
00db8189
AF		 31#include <linux/mii.h>
32#include <linux/ethtool.h>
33#include <linux/phy.h>
2f495c39 34#include <linux/marvell_phy.h>
cf41a51d 35#include <linux/of.h>
00db8189 36
eea3b201 37#include <linux/io.h>
00db8189 38#include <asm/irq.h>
eea3b201 39#include <linux/uaccess.h>
00db8189 40
27d916d6
DD		 41#define MII_MARVELL_PHY_PAGE 22
42
00db8189
AF		 43#define MII_M1011_IEVENT 0x13
44#define MII_M1011_IEVENT_CLEAR 0x0000
45
46#define MII_M1011_IMASK 0x12
47#define MII_M1011_IMASK_INIT 0x6400
48#define MII_M1011_IMASK_CLEAR 0x0000
49
76884679 50#define MII_M1011_PHY_SCR 0x10
239aa55b
DT		 51#define MII_M1011_PHY_SCR_MDI 0x0000
52#define MII_M1011_PHY_SCR_MDI_X 0x0020
76884679
AF		 53#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
54
07151bc9 55#define MII_M1145_PHY_EXT_ADDR_PAGE 0x16
b0224175 56#define MII_M1145_PHY_EXT_SR 0x1b
76884679
AF		 57#define MII_M1145_PHY_EXT_CR 0x14
58#define MII_M1145_RGMII_RX_DELAY 0x0080
59#define MII_M1145_RGMII_TX_DELAY 0x0002
b0224175
VND		 60#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
61#define MII_M1145_HWCFG_MODE_MASK 0xf
62#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
76884679 63
99d881f9
VB		 64#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
65#define MII_M1145_HWCFG_MODE_MASK 0xf
66#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
67
76884679
AF		 68#define MII_M1111_PHY_LED_CONTROL 0x18
69#define MII_M1111_PHY_LED_DIRECT 0x4100
70#define MII_M1111_PHY_LED_COMBINE 0x411c
895ee682
KP		 71#define MII_M1111_PHY_EXT_CR 0x14
72#define MII_M1111_RX_DELAY 0x80
73#define MII_M1111_TX_DELAY 0x2
74#define MII_M1111_PHY_EXT_SR 0x1b
be937f1f
AS		 75
76#define MII_M1111_HWCFG_MODE_MASK 0xf
77#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
78#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
4117b5be 79#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
5f8cbc13 80#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
be937f1f
AS		 81#define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
82#define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
83
84#define MII_M1111_COPPER 0
85#define MII_M1111_FIBER 1
86
c477d044
CC		 87#define MII_88E1121_PHY_MSCR_PAGE 2
88#define MII_88E1121_PHY_MSCR_REG 21
89#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
90#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
91#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
92
337ac9d5
CC		 93#define MII_88E1318S_PHY_MSCR1_REG 16
94#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
3ff1c259 95
3871c387
MS		 96/* Copper Specific Interrupt Enable Register */
97#define MII_88E1318S_PHY_CSIER 0x12
98/* WOL Event Interrupt Enable */
99#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
100
101/* LED Timer Control Register */
102#define MII_88E1318S_PHY_LED_PAGE 0x03
103#define MII_88E1318S_PHY_LED_TCR 0x12
104#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
105#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
106#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
107
108/* Magic Packet MAC address registers */
109#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
110#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
111#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
112
113#define MII_88E1318S_PHY_WOL_PAGE 0x11
114#define MII_88E1318S_PHY_WOL_CTRL 0x10
115#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
116#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
117
140bc929
SP		 118#define MII_88E1121_PHY_LED_CTRL 16
119#define MII_88E1121_PHY_LED_PAGE 3
120#define MII_88E1121_PHY_LED_DEF 0x0030
140bc929 121
be937f1f
AS		 122#define MII_M1011_PHY_STATUS 0x11
123#define MII_M1011_PHY_STATUS_1000 0x8000
124#define MII_M1011_PHY_STATUS_100 0x4000
125#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
126#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
127#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
128#define MII_M1011_PHY_STATUS_LINK 0x0400
129
3da09a51
MS		 130#define MII_M1116R_CONTROL_REG_MAC 21
131
6b358aed
SH		 132#define MII_88E3016_PHY_SPEC_CTRL 0x10
133#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
134#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
76884679 135
00db8189
AF		 136MODULE_DESCRIPTION("Marvell PHY driver");
137MODULE_AUTHOR("Andy Fleming");
138MODULE_LICENSE("GPL");
139
140static int marvell_ack_interrupt(struct phy_device *phydev)
141{
142 int err;
143
144 /* Clear the interrupts by reading the reg */
145 err = phy_read(phydev, MII_M1011_IEVENT);
146
147 if (err < 0)
148 return err;
149
150 return 0;
151}
152
153static int marvell_config_intr(struct phy_device *phydev)
154{
155 int err;
156
76884679 157 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
00db8189
AF		 158 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
159 else
160 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
161
162 return err;
163}
164
239aa55b
DT		 165static int marvell_set_polarity(struct phy_device *phydev, int polarity)
166{
167 int reg;
168 int err;
169 int val;
170
171 /* get the current settings */
172 reg = phy_read(phydev, MII_M1011_PHY_SCR);
173 if (reg < 0)
174 return reg;
175
176 val = reg;
177 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
178 switch (polarity) {
179 case ETH_TP_MDI:
180 val |= MII_M1011_PHY_SCR_MDI;
181 break;
182 case ETH_TP_MDI_X:
183 val |= MII_M1011_PHY_SCR_MDI_X;
184 break;
185 case ETH_TP_MDI_AUTO:
186 case ETH_TP_MDI_INVALID:
187 default:
188 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
189 break;
190 }
191
192 if (val != reg) {
193 /* Set the new polarity value in the register */
194 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
195 if (err)
196 return err;
197 }
198
199 return 0;
200}
201
00db8189
AF		 202static int marvell_config_aneg(struct phy_device *phydev)
203{
204 int err;
205
206 /* The Marvell PHY has an errata which requires
207 * that certain registers get written in order
208 * to restart autonegotiation */
209 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
210
211 if (err < 0)
212 return err;
213
214 err = phy_write(phydev, 0x1d, 0x1f);
215 if (err < 0)
216 return err;
217
218 err = phy_write(phydev, 0x1e, 0x200c);
219 if (err < 0)
220 return err;
221
222 err = phy_write(phydev, 0x1d, 0x5);
223 if (err < 0)
224 return err;
225
226 err = phy_write(phydev, 0x1e, 0);
227 if (err < 0)
228 return err;
229
230 err = phy_write(phydev, 0x1e, 0x100);
231 if (err < 0)
232 return err;
233
239aa55b 234 err = marvell_set_polarity(phydev, phydev->mdix);
76884679
AF		 235 if (err < 0)
236 return err;
237
238 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
239 MII_M1111_PHY_LED_DIRECT);
240 if (err < 0)
241 return err;
00db8189
AF		 242
243 err = genphy_config_aneg(phydev);
8ff44985
AV		 244 if (err < 0)
245 return err;
00db8189 246
8ff44985
AV		 247 if (phydev->autoneg != AUTONEG_ENABLE) {
248 int bmcr;
249
250 /*
251 * A write to speed/duplex bits (that is performed by
252 * genphy_config_aneg() call above) must be followed by
253 * a software reset. Otherwise, the write has no effect.
254 */
255 bmcr = phy_read(phydev, MII_BMCR);
256 if (bmcr < 0)
257 return bmcr;
258
259 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
260 if (err < 0)
261 return err;
262 }
263
264 return 0;
00db8189
AF		 265}
266
cf41a51d
DD		 267#ifdef CONFIG_OF_MDIO
268/*
269 * Set and/or override some configuration registers based on the
270 * marvell,reg-init property stored in the of_node for the phydev.
271 *
272 * marvell,reg-init = <reg-page reg mask value>,...;
273 *
274 * There may be one or more sets of <reg-page reg mask value>:
275 *
276 * reg-page: which register bank to use.
277 * reg: the register.
278 * mask: if non-zero, ANDed with existing register value.
279 * value: ORed with the masked value and written to the regiser.
280 *
281 */
282static int marvell_of_reg_init(struct phy_device *phydev)
283{
284 const __be32 *paddr;
285 int len, i, saved_page, current_page, page_changed, ret;
286
287 if (!phydev->dev.of_node)
288 return 0;
289
290 paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len);
291 if (!paddr || len < (4 * sizeof(*paddr)))
292 return 0;
293
294 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
295 if (saved_page < 0)
296 return saved_page;
297 page_changed = 0;
298 current_page = saved_page;
299
300 ret = 0;
301 len /= sizeof(*paddr);
302 for (i = 0; i < len - 3; i += 4) {
303 u16 reg_page = be32_to_cpup(paddr + i);
304 u16 reg = be32_to_cpup(paddr + i + 1);
305 u16 mask = be32_to_cpup(paddr + i + 2);
306 u16 val_bits = be32_to_cpup(paddr + i + 3);
307 int val;
308
309 if (reg_page != current_page) {
310 current_page = reg_page;
311 page_changed = 1;
312 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
313 if (ret < 0)
314 goto err;
315 }
316
317 val = 0;
318 if (mask) {
319 val = phy_read(phydev, reg);
320 if (val < 0) {
321 ret = val;
322 goto err;
323 }
324 val &= mask;
325 }
326 val |= val_bits;
327
328 ret = phy_write(phydev, reg, val);
329 if (ret < 0)
330 goto err;
331
332 }
333err:
334 if (page_changed) {
335 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
336 if (ret == 0)
337 ret = i;
338 }
339 return ret;
340}
341#else
342static int marvell_of_reg_init(struct phy_device *phydev)
343{
344 return 0;
345}
346#endif /* CONFIG_OF_MDIO */
347
140bc929
SP		 348static int m88e1121_config_aneg(struct phy_device *phydev)
349{
c477d044
CC		 350 int err, oldpage, mscr;
351
27d916d6 352 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
c477d044 353
27d916d6 354 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
c477d044
CC		 355 MII_88E1121_PHY_MSCR_PAGE);
356 if (err < 0)
357 return err;
be8c6480 358
32a64161 359 if (phy_interface_is_rgmii(phydev)) {
be8c6480
AP		 360
361 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
362 MII_88E1121_PHY_MSCR_DELAY_MASK;
363
364 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
365 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
366 MII_88E1121_PHY_MSCR_TX_DELAY);
367 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
368 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
369 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
370 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
371
372 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
373 if (err < 0)
374 return err;
375 }
c477d044 376
27d916d6 377 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
140bc929
SP		 378
379 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
380 if (err < 0)
381 return err;
382
383 err = phy_write(phydev, MII_M1011_PHY_SCR,
384 MII_M1011_PHY_SCR_AUTO_CROSS);
385 if (err < 0)
386 return err;
387
27d916d6 388 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
140bc929 389
27d916d6 390 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
140bc929 391 phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
27d916d6 392 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
140bc929
SP		 393
394 err = genphy_config_aneg(phydev);
395
396 return err;
397}
398
337ac9d5 399static int m88e1318_config_aneg(struct phy_device *phydev)
3ff1c259
CC		 400{
401 int err, oldpage, mscr;
402
27d916d6 403 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
3ff1c259 404
27d916d6 405 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
3ff1c259
CC		 406 MII_88E1121_PHY_MSCR_PAGE);
407 if (err < 0)
408 return err;
409
337ac9d5
CC		 410 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
411 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
3ff1c259 412
337ac9d5 413 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
3ff1c259
CC		 414 if (err < 0)
415 return err;
416
27d916d6 417 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
3ff1c259
CC		 418 if (err < 0)
419 return err;
420
421 return m88e1121_config_aneg(phydev);
422}
423
10e24caa
MS		 424static int m88e1510_config_aneg(struct phy_device *phydev)
425{
426 int err;
427
428 err = m88e1318_config_aneg(phydev);
429 if (err < 0)
430 return err;
431
432 return marvell_of_reg_init(phydev);
433}
434
3da09a51
MS		 435static int m88e1116r_config_init(struct phy_device *phydev)
436{
437 int temp;
438 int err;
439
440 temp = phy_read(phydev, MII_BMCR);
441 temp |= BMCR_RESET;
442 err = phy_write(phydev, MII_BMCR, temp);
443 if (err < 0)
444 return err;
445
446 mdelay(500);
447
448 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
449 if (err < 0)
450 return err;
451
452 temp = phy_read(phydev, MII_M1011_PHY_SCR);
453 temp |= (7 << 12); /* max number of gigabit attempts */
454 temp |= (1 << 11); /* enable downshift */
455 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
456 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
457 if (err < 0)
458 return err;
459
460 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
461 if (err < 0)
462 return err;
463 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
464 temp |= (1 << 5);
465 temp |= (1 << 4);
466 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
467 if (err < 0)
468 return err;
469 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
470 if (err < 0)
471 return err;
472
473 temp = phy_read(phydev, MII_BMCR);
474 temp |= BMCR_RESET;
475 err = phy_write(phydev, MII_BMCR, temp);
476 if (err < 0)
477 return err;
478
479 mdelay(500);
480
481 return 0;
482}
483
6b358aed
SH		 484static int m88e3016_config_init(struct phy_device *phydev)
485{
486 int reg;
487
488 /* Enable Scrambler and Auto-Crossover */
489 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
490 if (reg < 0)
491 return reg;
492
493 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
494 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
495
496 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
497 if (reg < 0)
498 return reg;
499
500 return 0;
501}
502
895ee682
KP		 503static int m88e1111_config_init(struct phy_device *phydev)
504{
505 int err;
be937f1f 506 int temp;
be937f1f 507
32a64161 508 if (phy_interface_is_rgmii(phydev)) {
895ee682 509
9daf5a76
KP		 510 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
511 if (temp < 0)
512 return temp;
895ee682 513
9daf5a76 514 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
895ee682 515 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
9daf5a76
KP		 516 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
517 temp &= ~MII_M1111_TX_DELAY;
518 temp |= MII_M1111_RX_DELAY;
519 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
520 temp &= ~MII_M1111_RX_DELAY;
521 temp |= MII_M1111_TX_DELAY;
895ee682
KP		 522 }
523
9daf5a76
KP		 524 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
525 if (err < 0)
526 return err;
527
895ee682
KP		 528 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
529 if (temp < 0)
530 return temp;
531
532 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
be937f1f 533
7239016d 534 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
be937f1f
AS		 535 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
536 else
537 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
895ee682
KP		 538
539 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
540 if (err < 0)
541 return err;
542 }
543
4117b5be 544 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
4117b5be
KJ		 545 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
546 if (temp < 0)
547 return temp;
548
549 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
550 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
32d0c1e1 551 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
4117b5be
KJ		 552
553 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
554 if (err < 0)
555 return err;
07151bc9
MB		 556
557 /* make sure copper is selected */
558 err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE);
559 if (err < 0)
560 return err;
561
562 err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE,
563 err & (~0xff));
564 if (err < 0)
565 return err;
4117b5be
KJ		 566 }
567
5f8cbc13
LYB		 568 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
569 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
570 if (temp < 0)
571 return temp;
572 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
573 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
574 if (err < 0)
575 return err;
576
577 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
578 if (temp < 0)
579 return temp;
580 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
581 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
582 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
583 if (err < 0)
584 return err;
585
586 /* soft reset */
587 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
588 if (err < 0)
589 return err;
590 do
591 temp = phy_read(phydev, MII_BMCR);
592 while (temp & BMCR_RESET);
593
594 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
595 if (temp < 0)
596 return temp;
597 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
598 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
599 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
600 if (err < 0)
601 return err;
602 }
603
cf41a51d
DD		 604 err = marvell_of_reg_init(phydev);
605 if (err < 0)
606 return err;
5f8cbc13 607
cc90cb3b 608 return phy_write(phydev, MII_BMCR, BMCR_RESET);
895ee682
KP		 609}
610
605f196e
RM		 611static int m88e1118_config_aneg(struct phy_device *phydev)
612{
613 int err;
614
615 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
616 if (err < 0)
617 return err;
618
619 err = phy_write(phydev, MII_M1011_PHY_SCR,
620 MII_M1011_PHY_SCR_AUTO_CROSS);
621 if (err < 0)
622 return err;
623
624 err = genphy_config_aneg(phydev);
625 return 0;
626}
627
628static int m88e1118_config_init(struct phy_device *phydev)
629{
630 int err;
631
632 /* Change address */
27d916d6 633 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
605f196e
RM		 634 if (err < 0)
635 return err;
636
637 /* Enable 1000 Mbit */
638 err = phy_write(phydev, 0x15, 0x1070);
639 if (err < 0)
640 return err;
641
642 /* Change address */
27d916d6 643 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
605f196e
RM		 644 if (err < 0)
645 return err;
646
647 /* Adjust LED Control */
2f495c39
BH		 648 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
649 err = phy_write(phydev, 0x10, 0x1100);
650 else
651 err = phy_write(phydev, 0x10, 0x021e);
605f196e
RM		 652 if (err < 0)
653 return err;
654
cf41a51d
DD		 655 err = marvell_of_reg_init(phydev);
656 if (err < 0)
657 return err;
658
605f196e 659 /* Reset address */
27d916d6 660 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
605f196e
RM		 661 if (err < 0)
662 return err;
663
cc90cb3b 664 return phy_write(phydev, MII_BMCR, BMCR_RESET);
605f196e
RM		 665}
666
90600732
DD		 667static int m88e1149_config_init(struct phy_device *phydev)
668{
669 int err;
670
671 /* Change address */
672 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
673 if (err < 0)
674 return err;
675
676 /* Enable 1000 Mbit */
677 err = phy_write(phydev, 0x15, 0x1048);
678 if (err < 0)
679 return err;
680
cf41a51d
DD		 681 err = marvell_of_reg_init(phydev);
682 if (err < 0)
683 return err;
684
90600732
DD		 685 /* Reset address */
686 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
687 if (err < 0)
688 return err;
689
cc90cb3b 690 return phy_write(phydev, MII_BMCR, BMCR_RESET);
90600732
DD		 691}
692
76884679
AF		 693static int m88e1145_config_init(struct phy_device *phydev)
694{
695 int err;
b0224175 696 int temp;
76884679
AF		 697
698 /* Take care of errata E0 & E1 */
699 err = phy_write(phydev, 0x1d, 0x001b);
700 if (err < 0)
701 return err;
702
703 err = phy_write(phydev, 0x1e, 0x418f);
704 if (err < 0)
705 return err;
706
707 err = phy_write(phydev, 0x1d, 0x0016);
708 if (err < 0)
709 return err;
710
711 err = phy_write(phydev, 0x1e, 0xa2da);
712 if (err < 0)
713 return err;
714
895ee682 715 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
76884679
AF		 716 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
717 if (temp < 0)
718 return temp;
719
720 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
721
722 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
723 if (err < 0)
724 return err;
725
2f495c39 726 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
76884679
AF		 727 err = phy_write(phydev, 0x1d, 0x0012);
728 if (err < 0)
729 return err;
730
731 temp = phy_read(phydev, 0x1e);
732 if (temp < 0)
733 return temp;
734
735 temp &= 0xf03f;
736 temp |= 2 << 9; /* 36 ohm */
737 temp |= 2 << 6; /* 39 ohm */
738
739 err = phy_write(phydev, 0x1e, temp);
740 if (err < 0)
741 return err;
742
743 err = phy_write(phydev, 0x1d, 0x3);
744 if (err < 0)
745 return err;
746
747 err = phy_write(phydev, 0x1e, 0x8000);
748 if (err < 0)
749 return err;
750 }
751 }
752
b0224175
VND		 753 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
754 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
755 if (temp < 0)
756 return temp;
757
99d881f9 758 temp &= ~MII_M1145_HWCFG_MODE_MASK;
b0224175
VND		 759 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
760 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
761
762 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
763 if (err < 0)
764 return err;
765 }
766
cf41a51d
DD		 767 err = marvell_of_reg_init(phydev);
768 if (err < 0)
769 return err;
770
76884679
AF		 771 return 0;
772}
00db8189 773
be937f1f
AS		 774/* marvell_read_status
775 *
776 * Generic status code does not detect Fiber correctly!
f0c88f9c 777 * Description:
be937f1f
AS		 778 * Check the link, then figure out the current state
779 * by comparing what we advertise with what the link partner
780 * advertises. Start by checking the gigabit possibilities,
781 * then move on to 10/100.
782 */
783static int marvell_read_status(struct phy_device *phydev)
784{
785 int adv;
786 int err;
787 int lpa;
357cd64c 788 int lpagb;
be937f1f
AS		 789 int status = 0;
790
791 /* Update the link, but return if there
792 * was an error */
793 err = genphy_update_link(phydev);
794 if (err)
795 return err;
796
797 if (AUTONEG_ENABLE == phydev->autoneg) {
798 status = phy_read(phydev, MII_M1011_PHY_STATUS);
799 if (status < 0)
800 return status;
801
802 lpa = phy_read(phydev, MII_LPA);
803 if (lpa < 0)
804 return lpa;
805
357cd64c
RK		 806 lpagb = phy_read(phydev, MII_STAT1000);
807 if (lpagb < 0)
808 return lpagb;
809
be937f1f
AS		 810 adv = phy_read(phydev, MII_ADVERTISE);
811 if (adv < 0)
812 return adv;
813
357cd64c
RK		 814 phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) |
815 mii_lpa_to_ethtool_lpa_t(lpa);
816
be937f1f
AS		 817 lpa &= adv;
818
819 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
820 phydev->duplex = DUPLEX_FULL;
821 else
822 phydev->duplex = DUPLEX_HALF;
823
824 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
825 phydev->pause = phydev->asym_pause = 0;
826
827 switch (status) {
828 case MII_M1011_PHY_STATUS_1000:
829 phydev->speed = SPEED_1000;
830 break;
831
832 case MII_M1011_PHY_STATUS_100:
833 phydev->speed = SPEED_100;
834 break;
835
836 default:
837 phydev->speed = SPEED_10;
838 break;
839 }
840
841 if (phydev->duplex == DUPLEX_FULL) {
842 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
843 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
844 }
845 } else {
846 int bmcr = phy_read(phydev, MII_BMCR);
847
848 if (bmcr < 0)
849 return bmcr;
850
851 if (bmcr & BMCR_FULLDPLX)
852 phydev->duplex = DUPLEX_FULL;
853 else
854 phydev->duplex = DUPLEX_HALF;
855
856 if (bmcr & BMCR_SPEED1000)
857 phydev->speed = SPEED_1000;
858 else if (bmcr & BMCR_SPEED100)
859 phydev->speed = SPEED_100;
860 else
861 phydev->speed = SPEED_10;
862
863 phydev->pause = phydev->asym_pause = 0;
357cd64c 864 phydev->lp_advertising = 0;
be937f1f
AS		 865 }
866
867 return 0;
868}
869
6b358aed
SH		 870static int marvell_aneg_done(struct phy_device *phydev)
871{
872 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
873 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
874}
875
dcd07be3
AG		 876static int m88e1121_did_interrupt(struct phy_device *phydev)
877{
878 int imask;
879
880 imask = phy_read(phydev, MII_M1011_IEVENT);
881
882 if (imask & MII_M1011_IMASK_INIT)
883 return 1;
884
885 return 0;
886}
887
3871c387
MS		 888static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
889{
890 wol->supported = WAKE_MAGIC;
891 wol->wolopts = 0;
892
893 if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
894 MII_88E1318S_PHY_WOL_PAGE) < 0)
895 return;
896
897 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
898 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
899 wol->wolopts |= WAKE_MAGIC;
900
901 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
902 return;
903}
904
905static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
906{
907 int err, oldpage, temp;
908
909 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
910
911 if (wol->wolopts & WAKE_MAGIC) {
912 /* Explicitly switch to page 0x00, just to be sure */
913 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
914 if (err < 0)
915 return err;
916
917 /* Enable the WOL interrupt */
918 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
919 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
920 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
921 if (err < 0)
922 return err;
923
924 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
925 MII_88E1318S_PHY_LED_PAGE);
926 if (err < 0)
927 return err;
928
929 /* Setup LED[2] as interrupt pin (active low) */
930 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
931 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
932 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
933 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
934 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
935 if (err < 0)
936 return err;
937
938 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
939 MII_88E1318S_PHY_WOL_PAGE);
940 if (err < 0)
941 return err;
942
943 /* Store the device address for the magic packet */
944 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
945 ((phydev->attached_dev->dev_addr[5] << 8) |
946 phydev->attached_dev->dev_addr[4]));
947 if (err < 0)
948 return err;
949 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
950 ((phydev->attached_dev->dev_addr[3] << 8) |
951 phydev->attached_dev->dev_addr[2]));
952 if (err < 0)
953 return err;
954 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
955 ((phydev->attached_dev->dev_addr[1] << 8) |
956 phydev->attached_dev->dev_addr[0]));
957 if (err < 0)
958 return err;
959
960 /* Clear WOL status and enable magic packet matching */
961 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
962 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
963 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
964 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
965 if (err < 0)
966 return err;
967 } else {
968 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
969 MII_88E1318S_PHY_WOL_PAGE);
970 if (err < 0)
971 return err;
972
973 /* Clear WOL status and disable magic packet matching */
974 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
975 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
976 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
977 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
978 if (err < 0)
979 return err;
980 }
981
982 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
983 if (err < 0)
984 return err;
985
986 return 0;
987}
988
e5479239
OJ		 989static struct phy_driver marvell_drivers[] = {
990 {
2f495c39
BH		 991 .phy_id = MARVELL_PHY_ID_88E1101,
992 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 993 .name = "Marvell 88E1101",
994 .features = PHY_GBIT_FEATURES,
995 .flags = PHY_HAS_INTERRUPT,
996 .config_aneg = &marvell_config_aneg,
997 .read_status = &genphy_read_status,
998 .ack_interrupt = &marvell_ack_interrupt,
999 .config_intr = &marvell_config_intr,
0898b448
SH		 1000 .resume = &genphy_resume,
1001 .suspend = &genphy_suspend,
ac8c635a 1002 .driver = { .owner = THIS_MODULE },
e5479239 1003 },
85cfb534 1004 {
2f495c39
BH		 1005 .phy_id = MARVELL_PHY_ID_88E1112,
1006 .phy_id_mask = MARVELL_PHY_ID_MASK,
85cfb534
OJ		 1007 .name = "Marvell 88E1112",
1008 .features = PHY_GBIT_FEATURES,
1009 .flags = PHY_HAS_INTERRUPT,
1010 .config_init = &m88e1111_config_init,
1011 .config_aneg = &marvell_config_aneg,
1012 .read_status = &genphy_read_status,
1013 .ack_interrupt = &marvell_ack_interrupt,
1014 .config_intr = &marvell_config_intr,
0898b448
SH		 1015 .resume = &genphy_resume,
1016 .suspend = &genphy_suspend,
ac8c635a 1017 .driver = { .owner = THIS_MODULE },
85cfb534 1018 },
e5479239 1019 {
2f495c39
BH		 1020 .phy_id = MARVELL_PHY_ID_88E1111,
1021 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1022 .name = "Marvell 88E1111",
1023 .features = PHY_GBIT_FEATURES,
1024 .flags = PHY_HAS_INTERRUPT,
1025 .config_init = &m88e1111_config_init,
1026 .config_aneg = &marvell_config_aneg,
be937f1f 1027 .read_status = &marvell_read_status,
e5479239
OJ		 1028 .ack_interrupt = &marvell_ack_interrupt,
1029 .config_intr = &marvell_config_intr,
0898b448
SH		 1030 .resume = &genphy_resume,
1031 .suspend = &genphy_suspend,
ac8c635a 1032 .driver = { .owner = THIS_MODULE },
e5479239 1033 },
605f196e 1034 {
2f495c39
BH		 1035 .phy_id = MARVELL_PHY_ID_88E1118,
1036 .phy_id_mask = MARVELL_PHY_ID_MASK,
605f196e
RM		 1037 .name = "Marvell 88E1118",
1038 .features = PHY_GBIT_FEATURES,
1039 .flags = PHY_HAS_INTERRUPT,
1040 .config_init = &m88e1118_config_init,
1041 .config_aneg = &m88e1118_config_aneg,
1042 .read_status = &genphy_read_status,
1043 .ack_interrupt = &marvell_ack_interrupt,
1044 .config_intr = &marvell_config_intr,
0898b448
SH		 1045 .resume = &genphy_resume,
1046 .suspend = &genphy_suspend,
605f196e
RM		 1047 .driver = {.owner = THIS_MODULE,},
1048 },
140bc929 1049 {
2f495c39
BH		 1050 .phy_id = MARVELL_PHY_ID_88E1121R,
1051 .phy_id_mask = MARVELL_PHY_ID_MASK,
140bc929
SP		 1052 .name = "Marvell 88E1121R",
1053 .features = PHY_GBIT_FEATURES,
1054 .flags = PHY_HAS_INTERRUPT,
1055 .config_aneg = &m88e1121_config_aneg,
1056 .read_status = &marvell_read_status,
1057 .ack_interrupt = &marvell_ack_interrupt,
1058 .config_intr = &marvell_config_intr,
dcd07be3 1059 .did_interrupt = &m88e1121_did_interrupt,
0898b448
SH		 1060 .resume = &genphy_resume,
1061 .suspend = &genphy_suspend,
140bc929
SP		 1062 .driver = { .owner = THIS_MODULE },
1063 },
3ff1c259 1064 {
337ac9d5 1065 .phy_id = MARVELL_PHY_ID_88E1318S,
6ba74014 1066 .phy_id_mask = MARVELL_PHY_ID_MASK,
337ac9d5 1067 .name = "Marvell 88E1318S",
3ff1c259
CC		 1068 .features = PHY_GBIT_FEATURES,
1069 .flags = PHY_HAS_INTERRUPT,
337ac9d5 1070 .config_aneg = &m88e1318_config_aneg,
3ff1c259
CC		 1071 .read_status = &marvell_read_status,
1072 .ack_interrupt = &marvell_ack_interrupt,
1073 .config_intr = &marvell_config_intr,
1074 .did_interrupt = &m88e1121_did_interrupt,
3871c387
MS		 1075 .get_wol = &m88e1318_get_wol,
1076 .set_wol = &m88e1318_set_wol,
0898b448
SH		 1077 .resume = &genphy_resume,
1078 .suspend = &genphy_suspend,
3ff1c259
CC		 1079 .driver = { .owner = THIS_MODULE },
1080 },
e5479239 1081 {
2f495c39
BH		 1082 .phy_id = MARVELL_PHY_ID_88E1145,
1083 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1084 .name = "Marvell 88E1145",
1085 .features = PHY_GBIT_FEATURES,
1086 .flags = PHY_HAS_INTERRUPT,
1087 .config_init = &m88e1145_config_init,
1088 .config_aneg = &marvell_config_aneg,
1089 .read_status = &genphy_read_status,
1090 .ack_interrupt = &marvell_ack_interrupt,
1091 .config_intr = &marvell_config_intr,
0898b448
SH		 1092 .resume = &genphy_resume,
1093 .suspend = &genphy_suspend,
ac8c635a
OJ		 1094 .driver = { .owner = THIS_MODULE },
1095 },
90600732
DD		 1096 {
1097 .phy_id = MARVELL_PHY_ID_88E1149R,
1098 .phy_id_mask = MARVELL_PHY_ID_MASK,
1099 .name = "Marvell 88E1149R",
1100 .features = PHY_GBIT_FEATURES,
1101 .flags = PHY_HAS_INTERRUPT,
1102 .config_init = &m88e1149_config_init,
1103 .config_aneg = &m88e1118_config_aneg,
1104 .read_status = &genphy_read_status,
1105 .ack_interrupt = &marvell_ack_interrupt,
1106 .config_intr = &marvell_config_intr,
0898b448
SH		 1107 .resume = &genphy_resume,
1108 .suspend = &genphy_suspend,
90600732
DD		 1109 .driver = { .owner = THIS_MODULE },
1110 },
ac8c635a 1111 {
2f495c39
BH		 1112 .phy_id = MARVELL_PHY_ID_88E1240,
1113 .phy_id_mask = MARVELL_PHY_ID_MASK,
ac8c635a
OJ		 1114 .name = "Marvell 88E1240",
1115 .features = PHY_GBIT_FEATURES,
1116 .flags = PHY_HAS_INTERRUPT,
1117 .config_init = &m88e1111_config_init,
1118 .config_aneg = &marvell_config_aneg,
1119 .read_status = &genphy_read_status,
1120 .ack_interrupt = &marvell_ack_interrupt,
1121 .config_intr = &marvell_config_intr,
0898b448
SH		 1122 .resume = &genphy_resume,
1123 .suspend = &genphy_suspend,
ac8c635a
OJ		 1124 .driver = { .owner = THIS_MODULE },
1125 },
3da09a51
MS		 1126 {
1127 .phy_id = MARVELL_PHY_ID_88E1116R,
1128 .phy_id_mask = MARVELL_PHY_ID_MASK,
1129 .name = "Marvell 88E1116R",
1130 .features = PHY_GBIT_FEATURES,
1131 .flags = PHY_HAS_INTERRUPT,
1132 .config_init = &m88e1116r_config_init,
1133 .config_aneg = &genphy_config_aneg,
1134 .read_status = &genphy_read_status,
1135 .ack_interrupt = &marvell_ack_interrupt,
1136 .config_intr = &marvell_config_intr,
0898b448
SH		 1137 .resume = &genphy_resume,
1138 .suspend = &genphy_suspend,
3da09a51
MS		 1139 .driver = { .owner = THIS_MODULE },
1140 },
10e24caa
MS		 1141 {
1142 .phy_id = MARVELL_PHY_ID_88E1510,
1143 .phy_id_mask = MARVELL_PHY_ID_MASK,
1144 .name = "Marvell 88E1510",
1145 .features = PHY_GBIT_FEATURES,
1146 .flags = PHY_HAS_INTERRUPT,
1147 .config_aneg = &m88e1510_config_aneg,
1148 .read_status = &marvell_read_status,
1149 .ack_interrupt = &marvell_ack_interrupt,
1150 .config_intr = &marvell_config_intr,
1151 .did_interrupt = &m88e1121_did_interrupt,
0898b448
SH		 1152 .resume = &genphy_resume,
1153 .suspend = &genphy_suspend,
10e24caa
MS		 1154 .driver = { .owner = THIS_MODULE },
1155 },
819ec8e1
AL		 1156 {
1157 .phy_id = MARVELL_PHY_ID_88E1540,
1158 .phy_id_mask = MARVELL_PHY_ID_MASK,
1159 .name = "Marvell 88E1540",
1160 .features = PHY_GBIT_FEATURES,
1161 .flags = PHY_HAS_INTERRUPT,
1162 .config_aneg = &m88e1510_config_aneg,
1163 .read_status = &marvell_read_status,
1164 .ack_interrupt = &marvell_ack_interrupt,
1165 .config_intr = &marvell_config_intr,
1166 .did_interrupt = &m88e1121_did_interrupt,
1167 .resume = &genphy_resume,
1168 .suspend = &genphy_suspend,
1169 .driver = { .owner = THIS_MODULE },
1170 },
6b358aed
SH		 1171 {
1172 .phy_id = MARVELL_PHY_ID_88E3016,
1173 .phy_id_mask = MARVELL_PHY_ID_MASK,
1174 .name = "Marvell 88E3016",
1175 .features = PHY_BASIC_FEATURES,
1176 .flags = PHY_HAS_INTERRUPT,
1177 .config_aneg = &genphy_config_aneg,
1178 .config_init = &m88e3016_config_init,
1179 .aneg_done = &marvell_aneg_done,
1180 .read_status = &marvell_read_status,
1181 .ack_interrupt = &marvell_ack_interrupt,
1182 .config_intr = &marvell_config_intr,
1183 .did_interrupt = &m88e1121_did_interrupt,
1184 .resume = &genphy_resume,
1185 .suspend = &genphy_suspend,
1186 .driver = { .owner = THIS_MODULE },
1187 },
00db8189
AF		 1188};
1189
50fd7150 1190module_phy_driver(marvell_drivers);
4e4f10f6 1191
cf93c945 1192static struct mdio_device_id __maybe_unused marvell_tbl[] = {
f5e1cabf
MS		 1193 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1194 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1195 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1196 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1197 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1198 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1199 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1200 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1201 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3da09a51 1202 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
10e24caa 1203 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
819ec8e1 1204 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
6b358aed 1205 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
4e4f10f6
DW		 1206 { }
1207};
1208
1209MODULE_DEVICE_TABLE(mdio, marvell_tbl);
Linux 6.x block layer and io_uring tree(s)