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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[linux-2.6-block.git] / drivers / net / phy / marvell.c
CommitLineData
00db8189
AF		 1/*
2 * drivers/net/phy/marvell.c
3 *
4 * Driver for Marvell PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
3871c387
MS		 10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
11 *
00db8189
AF		 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
00db8189 18#include <linux/kernel.h>
00db8189
AF		 19#include <linux/string.h>
20#include <linux/errno.h>
21#include <linux/unistd.h>
00db8189
AF		 22#include <linux/interrupt.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/spinlock.h>
29#include <linux/mm.h>
30#include <linux/module.h>
00db8189
AF		 31#include <linux/mii.h>
32#include <linux/ethtool.h>
33#include <linux/phy.h>
2f495c39 34#include <linux/marvell_phy.h>
cf41a51d 35#include <linux/of.h>
00db8189 36
eea3b201 37#include <linux/io.h>
00db8189 38#include <asm/irq.h>
eea3b201 39#include <linux/uaccess.h>
00db8189 40
27d916d6
DD		 41#define MII_MARVELL_PHY_PAGE 22
42
00db8189
AF		 43#define MII_M1011_IEVENT 0x13
44#define MII_M1011_IEVENT_CLEAR 0x0000
45
46#define MII_M1011_IMASK 0x12
47#define MII_M1011_IMASK_INIT 0x6400
48#define MII_M1011_IMASK_CLEAR 0x0000
49
76884679 50#define MII_M1011_PHY_SCR 0x10
239aa55b
DT		 51#define MII_M1011_PHY_SCR_MDI 0x0000
52#define MII_M1011_PHY_SCR_MDI_X 0x0020
76884679
AF		 53#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
54
b0224175 55#define MII_M1145_PHY_EXT_SR 0x1b
76884679
AF		 56#define MII_M1145_PHY_EXT_CR 0x14
57#define MII_M1145_RGMII_RX_DELAY 0x0080
58#define MII_M1145_RGMII_TX_DELAY 0x0002
b0224175
VND		 59#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
60#define MII_M1145_HWCFG_MODE_MASK 0xf
61#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
76884679 62
99d881f9
VB		 63#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
64#define MII_M1145_HWCFG_MODE_MASK 0xf
65#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
66
76884679
AF		 67#define MII_M1111_PHY_LED_CONTROL 0x18
68#define MII_M1111_PHY_LED_DIRECT 0x4100
69#define MII_M1111_PHY_LED_COMBINE 0x411c
895ee682
KP		 70#define MII_M1111_PHY_EXT_CR 0x14
71#define MII_M1111_RX_DELAY 0x80
72#define MII_M1111_TX_DELAY 0x2
73#define MII_M1111_PHY_EXT_SR 0x1b
be937f1f
AS		 74
75#define MII_M1111_HWCFG_MODE_MASK 0xf
76#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
77#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
4117b5be 78#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
5f8cbc13 79#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
be937f1f
AS		 80#define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
81#define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
82
83#define MII_M1111_COPPER 0
84#define MII_M1111_FIBER 1
85
c477d044
CC		 86#define MII_88E1121_PHY_MSCR_PAGE 2
87#define MII_88E1121_PHY_MSCR_REG 21
88#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
89#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
90#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
91
337ac9d5
CC		 92#define MII_88E1318S_PHY_MSCR1_REG 16
93#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
3ff1c259 94
3871c387
MS		 95/* Copper Specific Interrupt Enable Register */
96#define MII_88E1318S_PHY_CSIER 0x12
97/* WOL Event Interrupt Enable */
98#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
99
100/* LED Timer Control Register */
101#define MII_88E1318S_PHY_LED_PAGE 0x03
102#define MII_88E1318S_PHY_LED_TCR 0x12
103#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
104#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
105#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
106
107/* Magic Packet MAC address registers */
108#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
109#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
110#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
111
112#define MII_88E1318S_PHY_WOL_PAGE 0x11
113#define MII_88E1318S_PHY_WOL_CTRL 0x10
114#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
115#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
116
140bc929
SP		 117#define MII_88E1121_PHY_LED_CTRL 16
118#define MII_88E1121_PHY_LED_PAGE 3
119#define MII_88E1121_PHY_LED_DEF 0x0030
140bc929 120
be937f1f
AS		 121#define MII_M1011_PHY_STATUS 0x11
122#define MII_M1011_PHY_STATUS_1000 0x8000
123#define MII_M1011_PHY_STATUS_100 0x4000
124#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
125#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
126#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
127#define MII_M1011_PHY_STATUS_LINK 0x0400
128
3da09a51
MS		 129#define MII_M1116R_CONTROL_REG_MAC 21
130
6b358aed
SH		 131#define MII_88E3016_PHY_SPEC_CTRL 0x10
132#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
133#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
76884679 134
00db8189
AF		 135MODULE_DESCRIPTION("Marvell PHY driver");
136MODULE_AUTHOR("Andy Fleming");
137MODULE_LICENSE("GPL");
138
139static int marvell_ack_interrupt(struct phy_device *phydev)
140{
141 int err;
142
143 /* Clear the interrupts by reading the reg */
144 err = phy_read(phydev, MII_M1011_IEVENT);
145
146 if (err < 0)
147 return err;
148
149 return 0;
150}
151
152static int marvell_config_intr(struct phy_device *phydev)
153{
154 int err;
155
76884679 156 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
00db8189
AF		 157 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
158 else
159 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
160
161 return err;
162}
163
239aa55b
DT		 164static int marvell_set_polarity(struct phy_device *phydev, int polarity)
165{
166 int reg;
167 int err;
168 int val;
169
170 /* get the current settings */
171 reg = phy_read(phydev, MII_M1011_PHY_SCR);
172 if (reg < 0)
173 return reg;
174
175 val = reg;
176 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
177 switch (polarity) {
178 case ETH_TP_MDI:
179 val |= MII_M1011_PHY_SCR_MDI;
180 break;
181 case ETH_TP_MDI_X:
182 val |= MII_M1011_PHY_SCR_MDI_X;
183 break;
184 case ETH_TP_MDI_AUTO:
185 case ETH_TP_MDI_INVALID:
186 default:
187 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
188 break;
189 }
190
191 if (val != reg) {
192 /* Set the new polarity value in the register */
193 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
194 if (err)
195 return err;
196 }
197
198 return 0;
199}
200
00db8189
AF		 201static int marvell_config_aneg(struct phy_device *phydev)
202{
203 int err;
204
205 /* The Marvell PHY has an errata which requires
206 * that certain registers get written in order
207 * to restart autonegotiation */
208 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
209
210 if (err < 0)
211 return err;
212
213 err = phy_write(phydev, 0x1d, 0x1f);
214 if (err < 0)
215 return err;
216
217 err = phy_write(phydev, 0x1e, 0x200c);
218 if (err < 0)
219 return err;
220
221 err = phy_write(phydev, 0x1d, 0x5);
222 if (err < 0)
223 return err;
224
225 err = phy_write(phydev, 0x1e, 0);
226 if (err < 0)
227 return err;
228
229 err = phy_write(phydev, 0x1e, 0x100);
230 if (err < 0)
231 return err;
232
239aa55b 233 err = marvell_set_polarity(phydev, phydev->mdix);
76884679
AF		 234 if (err < 0)
235 return err;
236
237 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
238 MII_M1111_PHY_LED_DIRECT);
239 if (err < 0)
240 return err;
00db8189
AF		 241
242 err = genphy_config_aneg(phydev);
8ff44985
AV		 243 if (err < 0)
244 return err;
00db8189 245
8ff44985
AV		 246 if (phydev->autoneg != AUTONEG_ENABLE) {
247 int bmcr;
248
249 /*
250 * A write to speed/duplex bits (that is performed by
251 * genphy_config_aneg() call above) must be followed by
252 * a software reset. Otherwise, the write has no effect.
253 */
254 bmcr = phy_read(phydev, MII_BMCR);
255 if (bmcr < 0)
256 return bmcr;
257
258 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
259 if (err < 0)
260 return err;
261 }
262
263 return 0;
00db8189
AF		 264}
265
cf41a51d
DD		 266#ifdef CONFIG_OF_MDIO
267/*
268 * Set and/or override some configuration registers based on the
269 * marvell,reg-init property stored in the of_node for the phydev.
270 *
271 * marvell,reg-init = <reg-page reg mask value>,...;
272 *
273 * There may be one or more sets of <reg-page reg mask value>:
274 *
275 * reg-page: which register bank to use.
276 * reg: the register.
277 * mask: if non-zero, ANDed with existing register value.
278 * value: ORed with the masked value and written to the regiser.
279 *
280 */
281static int marvell_of_reg_init(struct phy_device *phydev)
282{
283 const __be32 *paddr;
284 int len, i, saved_page, current_page, page_changed, ret;
285
286 if (!phydev->dev.of_node)
287 return 0;
288
289 paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len);
290 if (!paddr || len < (4 * sizeof(*paddr)))
291 return 0;
292
293 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
294 if (saved_page < 0)
295 return saved_page;
296 page_changed = 0;
297 current_page = saved_page;
298
299 ret = 0;
300 len /= sizeof(*paddr);
301 for (i = 0; i < len - 3; i += 4) {
302 u16 reg_page = be32_to_cpup(paddr + i);
303 u16 reg = be32_to_cpup(paddr + i + 1);
304 u16 mask = be32_to_cpup(paddr + i + 2);
305 u16 val_bits = be32_to_cpup(paddr + i + 3);
306 int val;
307
308 if (reg_page != current_page) {
309 current_page = reg_page;
310 page_changed = 1;
311 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
312 if (ret < 0)
313 goto err;
314 }
315
316 val = 0;
317 if (mask) {
318 val = phy_read(phydev, reg);
319 if (val < 0) {
320 ret = val;
321 goto err;
322 }
323 val &= mask;
324 }
325 val |= val_bits;
326
327 ret = phy_write(phydev, reg, val);
328 if (ret < 0)
329 goto err;
330
331 }
332err:
333 if (page_changed) {
334 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
335 if (ret == 0)
336 ret = i;
337 }
338 return ret;
339}
340#else
341static int marvell_of_reg_init(struct phy_device *phydev)
342{
343 return 0;
344}
345#endif /* CONFIG_OF_MDIO */
346
140bc929
SP		 347static int m88e1121_config_aneg(struct phy_device *phydev)
348{
c477d044
CC		 349 int err, oldpage, mscr;
350
27d916d6 351 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
c477d044 352
27d916d6 353 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
c477d044
CC		 354 MII_88E1121_PHY_MSCR_PAGE);
355 if (err < 0)
356 return err;
be8c6480 357
32a64161 358 if (phy_interface_is_rgmii(phydev)) {
be8c6480
AP		 359
360 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
361 MII_88E1121_PHY_MSCR_DELAY_MASK;
362
363 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
364 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
365 MII_88E1121_PHY_MSCR_TX_DELAY);
366 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
367 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
368 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
369 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
370
371 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
372 if (err < 0)
373 return err;
374 }
c477d044 375
27d916d6 376 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
140bc929
SP		 377
378 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
379 if (err < 0)
380 return err;
381
382 err = phy_write(phydev, MII_M1011_PHY_SCR,
383 MII_M1011_PHY_SCR_AUTO_CROSS);
384 if (err < 0)
385 return err;
386
27d916d6 387 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
140bc929 388
27d916d6 389 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
140bc929 390 phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
27d916d6 391 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
140bc929
SP		 392
393 err = genphy_config_aneg(phydev);
394
395 return err;
396}
397
337ac9d5 398static int m88e1318_config_aneg(struct phy_device *phydev)
3ff1c259
CC		 399{
400 int err, oldpage, mscr;
401
27d916d6 402 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
3ff1c259 403
27d916d6 404 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
3ff1c259
CC		 405 MII_88E1121_PHY_MSCR_PAGE);
406 if (err < 0)
407 return err;
408
337ac9d5
CC		 409 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
410 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
3ff1c259 411
337ac9d5 412 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
3ff1c259
CC		 413 if (err < 0)
414 return err;
415
27d916d6 416 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
3ff1c259
CC		 417 if (err < 0)
418 return err;
419
420 return m88e1121_config_aneg(phydev);
421}
422
10e24caa
MS		 423static int m88e1510_config_aneg(struct phy_device *phydev)
424{
425 int err;
426
427 err = m88e1318_config_aneg(phydev);
428 if (err < 0)
429 return err;
430
431 return marvell_of_reg_init(phydev);
432}
433
3da09a51
MS		 434static int m88e1116r_config_init(struct phy_device *phydev)
435{
436 int temp;
437 int err;
438
439 temp = phy_read(phydev, MII_BMCR);
440 temp |= BMCR_RESET;
441 err = phy_write(phydev, MII_BMCR, temp);
442 if (err < 0)
443 return err;
444
445 mdelay(500);
446
447 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
448 if (err < 0)
449 return err;
450
451 temp = phy_read(phydev, MII_M1011_PHY_SCR);
452 temp |= (7 << 12); /* max number of gigabit attempts */
453 temp |= (1 << 11); /* enable downshift */
454 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
455 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
456 if (err < 0)
457 return err;
458
459 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
460 if (err < 0)
461 return err;
462 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
463 temp |= (1 << 5);
464 temp |= (1 << 4);
465 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
466 if (err < 0)
467 return err;
468 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
469 if (err < 0)
470 return err;
471
472 temp = phy_read(phydev, MII_BMCR);
473 temp |= BMCR_RESET;
474 err = phy_write(phydev, MII_BMCR, temp);
475 if (err < 0)
476 return err;
477
478 mdelay(500);
479
480 return 0;
481}
482
6b358aed
SH		 483static int m88e3016_config_init(struct phy_device *phydev)
484{
485 int reg;
486
487 /* Enable Scrambler and Auto-Crossover */
488 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
489 if (reg < 0)
490 return reg;
491
492 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
493 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
494
495 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
496 if (reg < 0)
497 return reg;
498
499 return 0;
500}
501
895ee682
KP		 502static int m88e1111_config_init(struct phy_device *phydev)
503{
504 int err;
be937f1f 505 int temp;
be937f1f 506
32a64161 507 if (phy_interface_is_rgmii(phydev)) {
895ee682 508
9daf5a76
KP		 509 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
510 if (temp < 0)
511 return temp;
895ee682 512
9daf5a76 513 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
895ee682 514 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
9daf5a76
KP		 515 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
516 temp &= ~MII_M1111_TX_DELAY;
517 temp |= MII_M1111_RX_DELAY;
518 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
519 temp &= ~MII_M1111_RX_DELAY;
520 temp |= MII_M1111_TX_DELAY;
895ee682
KP		 521 }
522
9daf5a76
KP		 523 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
524 if (err < 0)
525 return err;
526
895ee682
KP		 527 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
528 if (temp < 0)
529 return temp;
530
531 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
be937f1f 532
7239016d 533 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
be937f1f
AS		 534 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
535 else
536 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
895ee682
KP		 537
538 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
539 if (err < 0)
540 return err;
541 }
542
4117b5be 543 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
4117b5be
KJ		 544 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
545 if (temp < 0)
546 return temp;
547
548 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
549 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
32d0c1e1 550 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
4117b5be
KJ		 551
552 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
553 if (err < 0)
554 return err;
555 }
556
5f8cbc13
LYB		 557 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
558 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
559 if (temp < 0)
560 return temp;
561 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
562 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
563 if (err < 0)
564 return err;
565
566 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
567 if (temp < 0)
568 return temp;
569 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
570 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
571 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
572 if (err < 0)
573 return err;
574
575 /* soft reset */
576 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
577 if (err < 0)
578 return err;
579 do
580 temp = phy_read(phydev, MII_BMCR);
581 while (temp & BMCR_RESET);
582
583 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
584 if (temp < 0)
585 return temp;
586 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
587 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
588 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
589 if (err < 0)
590 return err;
591 }
592
cf41a51d
DD		 593 err = marvell_of_reg_init(phydev);
594 if (err < 0)
595 return err;
5f8cbc13 596
cc90cb3b 597 return phy_write(phydev, MII_BMCR, BMCR_RESET);
895ee682
KP		 598}
599
605f196e
RM		 600static int m88e1118_config_aneg(struct phy_device *phydev)
601{
602 int err;
603
604 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
605 if (err < 0)
606 return err;
607
608 err = phy_write(phydev, MII_M1011_PHY_SCR,
609 MII_M1011_PHY_SCR_AUTO_CROSS);
610 if (err < 0)
611 return err;
612
613 err = genphy_config_aneg(phydev);
614 return 0;
615}
616
617static int m88e1118_config_init(struct phy_device *phydev)
618{
619 int err;
620
621 /* Change address */
27d916d6 622 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
605f196e
RM		 623 if (err < 0)
624 return err;
625
626 /* Enable 1000 Mbit */
627 err = phy_write(phydev, 0x15, 0x1070);
628 if (err < 0)
629 return err;
630
631 /* Change address */
27d916d6 632 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
605f196e
RM		 633 if (err < 0)
634 return err;
635
636 /* Adjust LED Control */
2f495c39
BH		 637 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
638 err = phy_write(phydev, 0x10, 0x1100);
639 else
640 err = phy_write(phydev, 0x10, 0x021e);
605f196e
RM		 641 if (err < 0)
642 return err;
643
cf41a51d
DD		 644 err = marvell_of_reg_init(phydev);
645 if (err < 0)
646 return err;
647
605f196e 648 /* Reset address */
27d916d6 649 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
605f196e
RM		 650 if (err < 0)
651 return err;
652
cc90cb3b 653 return phy_write(phydev, MII_BMCR, BMCR_RESET);
605f196e
RM		 654}
655
90600732
DD		 656static int m88e1149_config_init(struct phy_device *phydev)
657{
658 int err;
659
660 /* Change address */
661 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
662 if (err < 0)
663 return err;
664
665 /* Enable 1000 Mbit */
666 err = phy_write(phydev, 0x15, 0x1048);
667 if (err < 0)
668 return err;
669
cf41a51d
DD		 670 err = marvell_of_reg_init(phydev);
671 if (err < 0)
672 return err;
673
90600732
DD		 674 /* Reset address */
675 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
676 if (err < 0)
677 return err;
678
cc90cb3b 679 return phy_write(phydev, MII_BMCR, BMCR_RESET);
90600732
DD		 680}
681
76884679
AF		 682static int m88e1145_config_init(struct phy_device *phydev)
683{
684 int err;
b0224175 685 int temp;
76884679
AF		 686
687 /* Take care of errata E0 & E1 */
688 err = phy_write(phydev, 0x1d, 0x001b);
689 if (err < 0)
690 return err;
691
692 err = phy_write(phydev, 0x1e, 0x418f);
693 if (err < 0)
694 return err;
695
696 err = phy_write(phydev, 0x1d, 0x0016);
697 if (err < 0)
698 return err;
699
700 err = phy_write(phydev, 0x1e, 0xa2da);
701 if (err < 0)
702 return err;
703
895ee682 704 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
76884679
AF		 705 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
706 if (temp < 0)
707 return temp;
708
709 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
710
711 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
712 if (err < 0)
713 return err;
714
2f495c39 715 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
76884679
AF		 716 err = phy_write(phydev, 0x1d, 0x0012);
717 if (err < 0)
718 return err;
719
720 temp = phy_read(phydev, 0x1e);
721 if (temp < 0)
722 return temp;
723
724 temp &= 0xf03f;
725 temp |= 2 << 9; /* 36 ohm */
726 temp |= 2 << 6; /* 39 ohm */
727
728 err = phy_write(phydev, 0x1e, temp);
729 if (err < 0)
730 return err;
731
732 err = phy_write(phydev, 0x1d, 0x3);
733 if (err < 0)
734 return err;
735
736 err = phy_write(phydev, 0x1e, 0x8000);
737 if (err < 0)
738 return err;
739 }
740 }
741
b0224175
VND		 742 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
743 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
744 if (temp < 0)
745 return temp;
746
99d881f9 747 temp &= ~MII_M1145_HWCFG_MODE_MASK;
b0224175
VND		 748 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
749 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
750
751 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
752 if (err < 0)
753 return err;
754 }
755
cf41a51d
DD		 756 err = marvell_of_reg_init(phydev);
757 if (err < 0)
758 return err;
759
76884679
AF		 760 return 0;
761}
00db8189 762
be937f1f
AS		 763/* marvell_read_status
764 *
765 * Generic status code does not detect Fiber correctly!
f0c88f9c 766 * Description:
be937f1f
AS		 767 * Check the link, then figure out the current state
768 * by comparing what we advertise with what the link partner
769 * advertises. Start by checking the gigabit possibilities,
770 * then move on to 10/100.
771 */
772static int marvell_read_status(struct phy_device *phydev)
773{
774 int adv;
775 int err;
776 int lpa;
777 int status = 0;
778
779 /* Update the link, but return if there
780 * was an error */
781 err = genphy_update_link(phydev);
782 if (err)
783 return err;
784
785 if (AUTONEG_ENABLE == phydev->autoneg) {
786 status = phy_read(phydev, MII_M1011_PHY_STATUS);
787 if (status < 0)
788 return status;
789
790 lpa = phy_read(phydev, MII_LPA);
791 if (lpa < 0)
792 return lpa;
793
794 adv = phy_read(phydev, MII_ADVERTISE);
795 if (adv < 0)
796 return adv;
797
798 lpa &= adv;
799
800 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
801 phydev->duplex = DUPLEX_FULL;
802 else
803 phydev->duplex = DUPLEX_HALF;
804
805 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
806 phydev->pause = phydev->asym_pause = 0;
807
808 switch (status) {
809 case MII_M1011_PHY_STATUS_1000:
810 phydev->speed = SPEED_1000;
811 break;
812
813 case MII_M1011_PHY_STATUS_100:
814 phydev->speed = SPEED_100;
815 break;
816
817 default:
818 phydev->speed = SPEED_10;
819 break;
820 }
821
822 if (phydev->duplex == DUPLEX_FULL) {
823 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
824 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
825 }
826 } else {
827 int bmcr = phy_read(phydev, MII_BMCR);
828
829 if (bmcr < 0)
830 return bmcr;
831
832 if (bmcr & BMCR_FULLDPLX)
833 phydev->duplex = DUPLEX_FULL;
834 else
835 phydev->duplex = DUPLEX_HALF;
836
837 if (bmcr & BMCR_SPEED1000)
838 phydev->speed = SPEED_1000;
839 else if (bmcr & BMCR_SPEED100)
840 phydev->speed = SPEED_100;
841 else
842 phydev->speed = SPEED_10;
843
844 phydev->pause = phydev->asym_pause = 0;
845 }
846
847 return 0;
848}
849
6b358aed
SH		 850static int marvell_aneg_done(struct phy_device *phydev)
851{
852 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
853 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
854}
855
dcd07be3
AG		 856static int m88e1121_did_interrupt(struct phy_device *phydev)
857{
858 int imask;
859
860 imask = phy_read(phydev, MII_M1011_IEVENT);
861
862 if (imask & MII_M1011_IMASK_INIT)
863 return 1;
864
865 return 0;
866}
867
3871c387
MS		 868static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
869{
870 wol->supported = WAKE_MAGIC;
871 wol->wolopts = 0;
872
873 if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
874 MII_88E1318S_PHY_WOL_PAGE) < 0)
875 return;
876
877 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
878 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
879 wol->wolopts |= WAKE_MAGIC;
880
881 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
882 return;
883}
884
885static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
886{
887 int err, oldpage, temp;
888
889 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
890
891 if (wol->wolopts & WAKE_MAGIC) {
892 /* Explicitly switch to page 0x00, just to be sure */
893 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
894 if (err < 0)
895 return err;
896
897 /* Enable the WOL interrupt */
898 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
899 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
900 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
901 if (err < 0)
902 return err;
903
904 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
905 MII_88E1318S_PHY_LED_PAGE);
906 if (err < 0)
907 return err;
908
909 /* Setup LED[2] as interrupt pin (active low) */
910 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
911 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
912 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
913 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
914 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
915 if (err < 0)
916 return err;
917
918 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
919 MII_88E1318S_PHY_WOL_PAGE);
920 if (err < 0)
921 return err;
922
923 /* Store the device address for the magic packet */
924 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
925 ((phydev->attached_dev->dev_addr[5] << 8) |
926 phydev->attached_dev->dev_addr[4]));
927 if (err < 0)
928 return err;
929 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
930 ((phydev->attached_dev->dev_addr[3] << 8) |
931 phydev->attached_dev->dev_addr[2]));
932 if (err < 0)
933 return err;
934 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
935 ((phydev->attached_dev->dev_addr[1] << 8) |
936 phydev->attached_dev->dev_addr[0]));
937 if (err < 0)
938 return err;
939
940 /* Clear WOL status and enable magic packet matching */
941 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
942 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
943 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
944 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
945 if (err < 0)
946 return err;
947 } else {
948 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
949 MII_88E1318S_PHY_WOL_PAGE);
950 if (err < 0)
951 return err;
952
953 /* Clear WOL status and disable magic packet matching */
954 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
955 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
956 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
957 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
958 if (err < 0)
959 return err;
960 }
961
962 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
963 if (err < 0)
964 return err;
965
966 return 0;
967}
968
e5479239
OJ		 969static struct phy_driver marvell_drivers[] = {
970 {
2f495c39
BH		 971 .phy_id = MARVELL_PHY_ID_88E1101,
972 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 973 .name = "Marvell 88E1101",
974 .features = PHY_GBIT_FEATURES,
975 .flags = PHY_HAS_INTERRUPT,
976 .config_aneg = &marvell_config_aneg,
977 .read_status = &genphy_read_status,
978 .ack_interrupt = &marvell_ack_interrupt,
979 .config_intr = &marvell_config_intr,
0898b448
SH		 980 .resume = &genphy_resume,
981 .suspend = &genphy_suspend,
ac8c635a 982 .driver = { .owner = THIS_MODULE },
e5479239 983 },
85cfb534 984 {
2f495c39
BH		 985 .phy_id = MARVELL_PHY_ID_88E1112,
986 .phy_id_mask = MARVELL_PHY_ID_MASK,
85cfb534
OJ		 987 .name = "Marvell 88E1112",
988 .features = PHY_GBIT_FEATURES,
989 .flags = PHY_HAS_INTERRUPT,
990 .config_init = &m88e1111_config_init,
991 .config_aneg = &marvell_config_aneg,
992 .read_status = &genphy_read_status,
993 .ack_interrupt = &marvell_ack_interrupt,
994 .config_intr = &marvell_config_intr,
0898b448
SH		 995 .resume = &genphy_resume,
996 .suspend = &genphy_suspend,
ac8c635a 997 .driver = { .owner = THIS_MODULE },
85cfb534 998 },
e5479239 999 {
2f495c39
BH		 1000 .phy_id = MARVELL_PHY_ID_88E1111,
1001 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1002 .name = "Marvell 88E1111",
1003 .features = PHY_GBIT_FEATURES,
1004 .flags = PHY_HAS_INTERRUPT,
1005 .config_init = &m88e1111_config_init,
1006 .config_aneg = &marvell_config_aneg,
be937f1f 1007 .read_status = &marvell_read_status,
e5479239
OJ		 1008 .ack_interrupt = &marvell_ack_interrupt,
1009 .config_intr = &marvell_config_intr,
0898b448
SH		 1010 .resume = &genphy_resume,
1011 .suspend = &genphy_suspend,
ac8c635a 1012 .driver = { .owner = THIS_MODULE },
e5479239 1013 },
605f196e 1014 {
2f495c39
BH		 1015 .phy_id = MARVELL_PHY_ID_88E1118,
1016 .phy_id_mask = MARVELL_PHY_ID_MASK,
605f196e
RM		 1017 .name = "Marvell 88E1118",
1018 .features = PHY_GBIT_FEATURES,
1019 .flags = PHY_HAS_INTERRUPT,
1020 .config_init = &m88e1118_config_init,
1021 .config_aneg = &m88e1118_config_aneg,
1022 .read_status = &genphy_read_status,
1023 .ack_interrupt = &marvell_ack_interrupt,
1024 .config_intr = &marvell_config_intr,
0898b448
SH		 1025 .resume = &genphy_resume,
1026 .suspend = &genphy_suspend,
605f196e
RM		 1027 .driver = {.owner = THIS_MODULE,},
1028 },
140bc929 1029 {
2f495c39
BH		 1030 .phy_id = MARVELL_PHY_ID_88E1121R,
1031 .phy_id_mask = MARVELL_PHY_ID_MASK,
140bc929
SP		 1032 .name = "Marvell 88E1121R",
1033 .features = PHY_GBIT_FEATURES,
1034 .flags = PHY_HAS_INTERRUPT,
1035 .config_aneg = &m88e1121_config_aneg,
1036 .read_status = &marvell_read_status,
1037 .ack_interrupt = &marvell_ack_interrupt,
1038 .config_intr = &marvell_config_intr,
dcd07be3 1039 .did_interrupt = &m88e1121_did_interrupt,
0898b448
SH		 1040 .resume = &genphy_resume,
1041 .suspend = &genphy_suspend,
140bc929
SP		 1042 .driver = { .owner = THIS_MODULE },
1043 },
3ff1c259 1044 {
337ac9d5 1045 .phy_id = MARVELL_PHY_ID_88E1318S,
6ba74014 1046 .phy_id_mask = MARVELL_PHY_ID_MASK,
337ac9d5 1047 .name = "Marvell 88E1318S",
3ff1c259
CC		 1048 .features = PHY_GBIT_FEATURES,
1049 .flags = PHY_HAS_INTERRUPT,
337ac9d5 1050 .config_aneg = &m88e1318_config_aneg,
3ff1c259
CC		 1051 .read_status = &marvell_read_status,
1052 .ack_interrupt = &marvell_ack_interrupt,
1053 .config_intr = &marvell_config_intr,
1054 .did_interrupt = &m88e1121_did_interrupt,
3871c387
MS		 1055 .get_wol = &m88e1318_get_wol,
1056 .set_wol = &m88e1318_set_wol,
0898b448
SH		 1057 .resume = &genphy_resume,
1058 .suspend = &genphy_suspend,
3ff1c259
CC		 1059 .driver = { .owner = THIS_MODULE },
1060 },
e5479239 1061 {
2f495c39
BH		 1062 .phy_id = MARVELL_PHY_ID_88E1145,
1063 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1064 .name = "Marvell 88E1145",
1065 .features = PHY_GBIT_FEATURES,
1066 .flags = PHY_HAS_INTERRUPT,
1067 .config_init = &m88e1145_config_init,
1068 .config_aneg = &marvell_config_aneg,
1069 .read_status = &genphy_read_status,
1070 .ack_interrupt = &marvell_ack_interrupt,
1071 .config_intr = &marvell_config_intr,
0898b448
SH		 1072 .resume = &genphy_resume,
1073 .suspend = &genphy_suspend,
ac8c635a
OJ		 1074 .driver = { .owner = THIS_MODULE },
1075 },
90600732
DD		 1076 {
1077 .phy_id = MARVELL_PHY_ID_88E1149R,
1078 .phy_id_mask = MARVELL_PHY_ID_MASK,
1079 .name = "Marvell 88E1149R",
1080 .features = PHY_GBIT_FEATURES,
1081 .flags = PHY_HAS_INTERRUPT,
1082 .config_init = &m88e1149_config_init,
1083 .config_aneg = &m88e1118_config_aneg,
1084 .read_status = &genphy_read_status,
1085 .ack_interrupt = &marvell_ack_interrupt,
1086 .config_intr = &marvell_config_intr,
0898b448
SH		 1087 .resume = &genphy_resume,
1088 .suspend = &genphy_suspend,
90600732
DD		 1089 .driver = { .owner = THIS_MODULE },
1090 },
ac8c635a 1091 {
2f495c39
BH		 1092 .phy_id = MARVELL_PHY_ID_88E1240,
1093 .phy_id_mask = MARVELL_PHY_ID_MASK,
ac8c635a
OJ		 1094 .name = "Marvell 88E1240",
1095 .features = PHY_GBIT_FEATURES,
1096 .flags = PHY_HAS_INTERRUPT,
1097 .config_init = &m88e1111_config_init,
1098 .config_aneg = &marvell_config_aneg,
1099 .read_status = &genphy_read_status,
1100 .ack_interrupt = &marvell_ack_interrupt,
1101 .config_intr = &marvell_config_intr,
0898b448
SH		 1102 .resume = &genphy_resume,
1103 .suspend = &genphy_suspend,
ac8c635a
OJ		 1104 .driver = { .owner = THIS_MODULE },
1105 },
3da09a51
MS		 1106 {
1107 .phy_id = MARVELL_PHY_ID_88E1116R,
1108 .phy_id_mask = MARVELL_PHY_ID_MASK,
1109 .name = "Marvell 88E1116R",
1110 .features = PHY_GBIT_FEATURES,
1111 .flags = PHY_HAS_INTERRUPT,
1112 .config_init = &m88e1116r_config_init,
1113 .config_aneg = &genphy_config_aneg,
1114 .read_status = &genphy_read_status,
1115 .ack_interrupt = &marvell_ack_interrupt,
1116 .config_intr = &marvell_config_intr,
0898b448
SH		 1117 .resume = &genphy_resume,
1118 .suspend = &genphy_suspend,
3da09a51
MS		 1119 .driver = { .owner = THIS_MODULE },
1120 },
10e24caa
MS		 1121 {
1122 .phy_id = MARVELL_PHY_ID_88E1510,
1123 .phy_id_mask = MARVELL_PHY_ID_MASK,
1124 .name = "Marvell 88E1510",
1125 .features = PHY_GBIT_FEATURES,
1126 .flags = PHY_HAS_INTERRUPT,
1127 .config_aneg = &m88e1510_config_aneg,
1128 .read_status = &marvell_read_status,
1129 .ack_interrupt = &marvell_ack_interrupt,
1130 .config_intr = &marvell_config_intr,
1131 .did_interrupt = &m88e1121_did_interrupt,
0898b448
SH		 1132 .resume = &genphy_resume,
1133 .suspend = &genphy_suspend,
10e24caa
MS		 1134 .driver = { .owner = THIS_MODULE },
1135 },
6b358aed
SH		 1136 {
1137 .phy_id = MARVELL_PHY_ID_88E3016,
1138 .phy_id_mask = MARVELL_PHY_ID_MASK,
1139 .name = "Marvell 88E3016",
1140 .features = PHY_BASIC_FEATURES,
1141 .flags = PHY_HAS_INTERRUPT,
1142 .config_aneg = &genphy_config_aneg,
1143 .config_init = &m88e3016_config_init,
1144 .aneg_done = &marvell_aneg_done,
1145 .read_status = &marvell_read_status,
1146 .ack_interrupt = &marvell_ack_interrupt,
1147 .config_intr = &marvell_config_intr,
1148 .did_interrupt = &m88e1121_did_interrupt,
1149 .resume = &genphy_resume,
1150 .suspend = &genphy_suspend,
1151 .driver = { .owner = THIS_MODULE },
1152 },
00db8189
AF		 1153};
1154
50fd7150 1155module_phy_driver(marvell_drivers);
4e4f10f6 1156
cf93c945 1157static struct mdio_device_id __maybe_unused marvell_tbl[] = {
f5e1cabf
MS		 1158 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1159 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1160 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1161 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1162 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1163 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1164 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1165 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1166 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3da09a51 1167 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
10e24caa 1168 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
6b358aed 1169 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
4e4f10f6
DW		 1170 { }
1171};
1172
1173MODULE_DEVICE_TABLE(mdio, marvell_tbl);
Linux 6.x block layer and io_uring tree(s)