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Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
[linux-block.git] / drivers / net / phy / dp83867.c
CommitLineData
5f857575 1// SPDX-License-Identifier: GPL-2.0
753c66ef 2/* Driver for the Texas Instruments DP83867 PHY
2a10154a
DM		 3 *
4 * Copyright (C) 2015 Texas Instruments Inc.
2a10154a
DM		 5 */
6
7#include <linux/ethtool.h>
8#include <linux/kernel.h>
9#include <linux/mii.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/phy.h>
72a7d452 13#include <linux/delay.h>
caabee5b
TH		 14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
cd26d72d 16#include <linux/bitfield.h>
5c2d0a6a 17#include <linux/nvmem-consumer.h>
2a10154a
DM		 18
19#include <dt-bindings/net/ti-dp83867.h>
20
21#define DP83867_PHY_ID 0x2000a231
22#define DP83867_DEVADDR 0x1f
23
24#define MII_DP83867_PHYCTRL 0x10
cd26d72d 25#define MII_DP83867_PHYSTS 0x11
2a10154a
DM		 26#define MII_DP83867_MICR 0x12
27#define MII_DP83867_ISR 0x13
caabee5b 28#define DP83867_CFG2 0x14
5ca7d1ca 29#define DP83867_CFG3 0x1e
caabee5b 30#define DP83867_CTRL 0x1f
2a10154a
DM		 31
32/* Extended Registers */
749f6f68
GS		 33#define DP83867_FLD_THR_CFG 0x002e
34#define DP83867_CFG4 0x0031
1a97a477
MU		 35#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
36#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
37#define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
38#define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
39#define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
40
2a10154a 41#define DP83867_RGMIICTL 0x0032
ac6e058b 42#define DP83867_STRAP_STS1 0x006E
c11669a2 43#define DP83867_STRAP_STS2 0x006f
2a10154a 44#define DP83867_RGMIIDCTL 0x0086
caabee5b
TH		 45#define DP83867_RXFCFG 0x0134
46#define DP83867_RXFPMD1 0x0136
47#define DP83867_RXFPMD2 0x0137
48#define DP83867_RXFPMD3 0x0138
49#define DP83867_RXFSOP1 0x0139
50#define DP83867_RXFSOP2 0x013A
51#define DP83867_RXFSOP3 0x013B
ed838fe9 52#define DP83867_IO_MUX_CFG 0x0170
507ddd5c 53#define DP83867_SGMIICTL 0x00D3
333061b9
MU		 54#define DP83867_10M_SGMII_CFG 0x016F
55#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
2a10154a
DM		 56
57#define DP83867_SW_RESET BIT(15)
58#define DP83867_SW_RESTART BIT(14)
59
60/* MICR Interrupt bits */
61#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
62#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
63#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
64#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
65#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
66#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
67#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
68#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
69#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
70#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
71#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
72#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
73
74/* RGMIICTL bits */
75#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
76#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
77
507ddd5c
VG		 78/* SGMIICTL bits */
79#define DP83867_SGMII_TYPE BIT(14)
80
caabee5b
TH		 81/* RXFCFG bits*/
82#define DP83867_WOL_MAGIC_EN BIT(0)
83#define DP83867_WOL_BCAST_EN BIT(2)
84#define DP83867_WOL_UCAST_EN BIT(4)
85#define DP83867_WOL_SEC_EN BIT(5)
86#define DP83867_WOL_ENH_MAC BIT(7)
87
ac6e058b
LM		 88/* STRAP_STS1 bits */
89#define DP83867_STRAP_STS1_RESERVED BIT(11)
90
c11669a2
TP		 91/* STRAP_STS2 bits */
92#define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
93#define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
94#define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
95#define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
96#define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
749f6f68 97#define DP83867_STRAP_STS2_STRAP_FLD BIT(10)
c11669a2 98
2a10154a 99/* PHY CTRL bits */
e02d1816
DM		 100#define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14
101#define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT 12
f8bbf417 102#define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
e02d1816
DM		 103#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14)
104#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12)
ac6e058b 105#define DP83867_PHYCR_RESERVED_MASK BIT(11)
86ffe920 106#define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10)
2a10154a
DM		 107
108/* RGMIIDCTL bits */
c11669a2 109#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
2a10154a 110#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
fafc5db2 111#define DP83867_RGMII_TX_CLK_DELAY_INV (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
c11669a2
TP		 112#define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
113#define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
fafc5db2
GS		 114#define DP83867_RGMII_RX_CLK_DELAY_INV (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
115
ed838fe9 116/* IO_MUX_CFG bits */
27708eb5 117#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
ed838fe9
M		 118#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
119#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
13c83cf8 120#define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
9708fb63
WE		 121#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
122#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
ed838fe9 123
cd26d72d
DM		 124/* PHY STS bits */
125#define DP83867_PHYSTS_1000 BIT(15)
126#define DP83867_PHYSTS_100 BIT(14)
127#define DP83867_PHYSTS_DUPLEX BIT(13)
128#define DP83867_PHYSTS_LINK BIT(10)
129
130/* CFG2 bits */
131#define DP83867_DOWNSHIFT_EN (BIT(8) | BIT(9))
132#define DP83867_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11))
133#define DP83867_DOWNSHIFT_1_COUNT_VAL 0
134#define DP83867_DOWNSHIFT_2_COUNT_VAL 1
135#define DP83867_DOWNSHIFT_4_COUNT_VAL 2
136#define DP83867_DOWNSHIFT_8_COUNT_VAL 3
137#define DP83867_DOWNSHIFT_1_COUNT 1
138#define DP83867_DOWNSHIFT_2_COUNT 2
139#define DP83867_DOWNSHIFT_4_COUNT 4
140#define DP83867_DOWNSHIFT_8_COUNT 8
c76acfb7 141#define DP83867_SGMII_AUTONEG_EN BIT(7)
cd26d72d 142
5a7f08c2
GS		 143/* CFG3 bits */
144#define DP83867_CFG3_INT_OE BIT(7)
145#define DP83867_CFG3_ROBUST_AUTO_MDIX BIT(9)
146
fc6d39c3
LM		 147/* CFG4 bits */
148#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
149
749f6f68
GS		 150/* FLD_THR_CFG */
151#define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7
152
fc6d39c3
LM		 153enum {
154 DP83867_PORT_MIRROING_KEEP,
155 DP83867_PORT_MIRROING_EN,
156 DP83867_PORT_MIRROING_DIS,
157};
158
2a10154a 159struct dp83867_private {
1b9b2954
TP		 160 u32 rx_id_delay;
161 u32 tx_id_delay;
e02d1816
DM		 162 u32 tx_fifo_depth;
163 u32 rx_fifo_depth;
ed838fe9 164 int io_impedance;
fc6d39c3 165 int port_mirroring;
37144476 166 bool rxctrl_strap_quirk;
13c83cf8
TP		 167 bool set_clk_output;
168 u32 clk_output_sel;
507ddd5c 169 bool sgmii_ref_clk_en;
2a10154a
DM		 170};
171
172static int dp83867_ack_interrupt(struct phy_device *phydev)
173{
174 int err = phy_read(phydev, MII_DP83867_ISR);
175
176 if (err < 0)
177 return err;
178
179 return 0;
180}
181
caabee5b
TH		 182static int dp83867_set_wol(struct phy_device *phydev,
183 struct ethtool_wolinfo *wol)
184{
185 struct net_device *ndev = phydev->attached_dev;
186 u16 val_rxcfg, val_micr;
86466cbe 187 const u8 *mac;
caabee5b
TH		 188
189 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
190 val_micr = phy_read(phydev, MII_DP83867_MICR);
191
192 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
193 WAKE_BCAST)) {
194 val_rxcfg |= DP83867_WOL_ENH_MAC;
195 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
196
197 if (wol->wolopts & WAKE_MAGIC) {
86466cbe 198 mac = (const u8 *)ndev->dev_addr;
caabee5b
TH		 199
200 if (!is_valid_ether_addr(mac))
201 return -EINVAL;
202
203 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
204 (mac[1] << 8 | mac[0]));
205 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
206 (mac[3] << 8 | mac[2]));
207 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
208 (mac[5] << 8 | mac[4]));
209
210 val_rxcfg |= DP83867_WOL_MAGIC_EN;
211 } else {
212 val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
213 }
214
215 if (wol->wolopts & WAKE_MAGICSECURE) {
216 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
217 (wol->sopass[1] << 8) | wol->sopass[0]);
8b4a11c6 218 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
caabee5b 219 (wol->sopass[3] << 8) | wol->sopass[2]);
8b4a11c6 220 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
caabee5b
TH		 221 (wol->sopass[5] << 8) | wol->sopass[4]);
222
223 val_rxcfg |= DP83867_WOL_SEC_EN;
224 } else {
225 val_rxcfg &= ~DP83867_WOL_SEC_EN;
226 }
227
228 if (wol->wolopts & WAKE_UCAST)
229 val_rxcfg |= DP83867_WOL_UCAST_EN;
230 else
231 val_rxcfg &= ~DP83867_WOL_UCAST_EN;
232
233 if (wol->wolopts & WAKE_BCAST)
234 val_rxcfg |= DP83867_WOL_BCAST_EN;
235 else
236 val_rxcfg &= ~DP83867_WOL_BCAST_EN;
237 } else {
238 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
239 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
240 }
241
242 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
243 phy_write(phydev, MII_DP83867_MICR, val_micr);
244
245 return 0;
246}
247
248static void dp83867_get_wol(struct phy_device *phydev,
249 struct ethtool_wolinfo *wol)
250{
251 u16 value, sopass_val;
252
253 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
254 WAKE_MAGICSECURE);
255 wol->wolopts = 0;
256
257 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
258
259 if (value & DP83867_WOL_UCAST_EN)
260 wol->wolopts |= WAKE_UCAST;
261
262 if (value & DP83867_WOL_BCAST_EN)
263 wol->wolopts |= WAKE_BCAST;
264
265 if (value & DP83867_WOL_MAGIC_EN)
266 wol->wolopts |= WAKE_MAGIC;
267
268 if (value & DP83867_WOL_SEC_EN) {
269 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
270 DP83867_RXFSOP1);
271 wol->sopass[0] = (sopass_val & 0xff);
272 wol->sopass[1] = (sopass_val >> 8);
273
274 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
275 DP83867_RXFSOP2);
276 wol->sopass[2] = (sopass_val & 0xff);
277 wol->sopass[3] = (sopass_val >> 8);
278
279 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
280 DP83867_RXFSOP3);
281 wol->sopass[4] = (sopass_val & 0xff);
282 wol->sopass[5] = (sopass_val >> 8);
283
284 wol->wolopts |= WAKE_MAGICSECURE;
285 }
286
287 if (!(value & DP83867_WOL_ENH_MAC))
288 wol->wolopts = 0;
289}
290
2a10154a
DM		 291static int dp83867_config_intr(struct phy_device *phydev)
292{
aa2d603a 293 int micr_status, err;
2a10154a
DM		 294
295 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
aa2d603a
IC		 296 err = dp83867_ack_interrupt(phydev);
297 if (err)
298 return err;
299
2a10154a
DM		 300 micr_status = phy_read(phydev, MII_DP83867_MICR);
301 if (micr_status < 0)
302 return micr_status;
303
304 micr_status |=
305 (MII_DP83867_MICR_AN_ERR_INT_EN |
306 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
5ca7d1ca
GS		 307 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
308 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
2a10154a
DM		 309 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
310 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
311
aa2d603a
IC		 312 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
313 } else {
314 micr_status = 0x0;
315 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
316 if (err)
317 return err;
318
319 err = dp83867_ack_interrupt(phydev);
2a10154a
DM		 320 }
321
aa2d603a 322 return err;
2a10154a
DM		 323}
324
1d1ae3c6
IC		 325static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev)
326{
327 int irq_status, irq_enabled;
328
329 irq_status = phy_read(phydev, MII_DP83867_ISR);
330 if (irq_status < 0) {
331 phy_error(phydev);
332 return IRQ_NONE;
333 }
334
335 irq_enabled = phy_read(phydev, MII_DP83867_MICR);
336 if (irq_enabled < 0) {
337 phy_error(phydev);
338 return IRQ_NONE;
339 }
340
341 if (!(irq_status & irq_enabled))
342 return IRQ_NONE;
343
344 phy_trigger_machine(phydev);
345
346 return IRQ_HANDLED;
347}
348
cd26d72d
DM		 349static int dp83867_read_status(struct phy_device *phydev)
350{
351 int status = phy_read(phydev, MII_DP83867_PHYSTS);
352 int ret;
353
354 ret = genphy_read_status(phydev);
355 if (ret)
356 return ret;
357
358 if (status < 0)
359 return status;
360
361 if (status & DP83867_PHYSTS_DUPLEX)
362 phydev->duplex = DUPLEX_FULL;
363 else
364 phydev->duplex = DUPLEX_HALF;
365
366 if (status & DP83867_PHYSTS_1000)
367 phydev->speed = SPEED_1000;
368 else if (status & DP83867_PHYSTS_100)
369 phydev->speed = SPEED_100;
370 else
371 phydev->speed = SPEED_10;
372
373 return 0;
374}
375
376static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
377{
378 int val, cnt, enable, count;
379
380 val = phy_read(phydev, DP83867_CFG2);
381 if (val < 0)
382 return val;
383
384 enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
385 cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
386
387 switch (cnt) {
388 case DP83867_DOWNSHIFT_1_COUNT_VAL:
389 count = DP83867_DOWNSHIFT_1_COUNT;
390 break;
391 case DP83867_DOWNSHIFT_2_COUNT_VAL:
392 count = DP83867_DOWNSHIFT_2_COUNT;
393 break;
394 case DP83867_DOWNSHIFT_4_COUNT_VAL:
395 count = DP83867_DOWNSHIFT_4_COUNT;
396 break;
397 case DP83867_DOWNSHIFT_8_COUNT_VAL:
398 count = DP83867_DOWNSHIFT_8_COUNT;
399 break;
400 default:
401 return -EINVAL;
dce38b74 402 }
cd26d72d
DM		 403
404 *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
405
406 return 0;
407}
408
409static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
410{
411 int val, count;
412
413 if (cnt > DP83867_DOWNSHIFT_8_COUNT)
414 return -E2BIG;
415
416 if (!cnt)
417 return phy_clear_bits(phydev, DP83867_CFG2,
418 DP83867_DOWNSHIFT_EN);
419
420 switch (cnt) {
753c66ef
DM		 421 case DP83867_DOWNSHIFT_1_COUNT:
422 count = DP83867_DOWNSHIFT_1_COUNT_VAL;
423 break;
424 case DP83867_DOWNSHIFT_2_COUNT:
425 count = DP83867_DOWNSHIFT_2_COUNT_VAL;
426 break;
427 case DP83867_DOWNSHIFT_4_COUNT:
428 count = DP83867_DOWNSHIFT_4_COUNT_VAL;
429 break;
430 case DP83867_DOWNSHIFT_8_COUNT:
431 count = DP83867_DOWNSHIFT_8_COUNT_VAL;
432 break;
433 default:
434 phydev_err(phydev,
435 "Downshift count must be 1, 2, 4 or 8\n");
436 return -EINVAL;
dce38b74 437 }
cd26d72d
DM		 438
439 val = DP83867_DOWNSHIFT_EN;
440 val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
441
442 return phy_modify(phydev, DP83867_CFG2,
443 DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
444 val);
445}
446
447static int dp83867_get_tunable(struct phy_device *phydev,
753c66ef 448 struct ethtool_tunable *tuna, void *data)
cd26d72d
DM		 449{
450 switch (tuna->id) {
451 case ETHTOOL_PHY_DOWNSHIFT:
452 return dp83867_get_downshift(phydev, data);
453 default:
454 return -EOPNOTSUPP;
455 }
456}
457
458static int dp83867_set_tunable(struct phy_device *phydev,
753c66ef 459 struct ethtool_tunable *tuna, const void *data)
cd26d72d
DM		 460{
461 switch (tuna->id) {
462 case ETHTOOL_PHY_DOWNSHIFT:
463 return dp83867_set_downshift(phydev, *(const u8 *)data);
464 default:
465 return -EOPNOTSUPP;
466 }
467}
468
fc6d39c3
LM		 469static int dp83867_config_port_mirroring(struct phy_device *phydev)
470{
471 struct dp83867_private *dp83867 =
472 (struct dp83867_private *)phydev->priv;
fc6d39c3
LM		 473
474 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
b52c018d
HK		 475 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
476 DP83867_CFG4_PORT_MIRROR_EN);
fc6d39c3 477 else
b52c018d
HK		 478 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
479 DP83867_CFG4_PORT_MIRROR_EN);
fc6d39c3
LM		 480 return 0;
481}
482
fafc5db2
GS		 483static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
484{
485 struct dp83867_private *dp83867 = phydev->priv;
486
487 /* Existing behavior was to use default pin strapping delay in rgmii
488 * mode, but rgmii should have meant no delay. Warn existing users.
489 */
490 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
491 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
492 DP83867_STRAP_STS2);
493 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
494 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
495 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
496 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
497
498 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
499 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
500 phydev_warn(phydev,
501 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
502 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
503 txskew, rxskew);
504 }
505
506 /* RX delay *must* be specified if internal delay of RX is used. */
507 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
508 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
509 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
510 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
511 return -EINVAL;
512 }
513
514 /* TX delay *must* be specified if internal delay of TX is used. */
515 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
516 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
517 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
518 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
519 return -EINVAL;
520 }
521
522 return 0;
523}
524
506de006 525#if IS_ENABLED(CONFIG_OF_MDIO)
5c2d0a6a
RV		 526static int dp83867_of_init_io_impedance(struct phy_device *phydev)
527{
528 struct dp83867_private *dp83867 = phydev->priv;
529 struct device *dev = &phydev->mdio.dev;
530 struct device_node *of_node = dev->of_node;
531 struct nvmem_cell *cell;
532 u8 *buf, val;
533 int ret;
534
535 cell = of_nvmem_cell_get(of_node, "io_impedance_ctrl");
536 if (IS_ERR(cell)) {
537 ret = PTR_ERR(cell);
546b9d3f 538 if (ret != -ENOENT && ret != -EOPNOTSUPP)
5c2d0a6a
RV		 539 return phydev_err_probe(phydev, ret,
540 "failed to get nvmem cell io_impedance_ctrl\n");
541
542 /* If no nvmem cell, check for the boolean properties. */
543 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
544 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
545 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
546 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
547 else
548 dp83867->io_impedance = -1; /* leave at default */
549
550 return 0;
551 }
552
553 buf = nvmem_cell_read(cell, NULL);
554 nvmem_cell_put(cell);
555
556 if (IS_ERR(buf))
557 return PTR_ERR(buf);
558
559 val = *buf;
560 kfree(buf);
561
562 if ((val & DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK) != val) {
563 phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n");
564 return -ERANGE;
565 }
566 dp83867->io_impedance = val;
567
568 return 0;
569}
570
2a10154a
DM		 571static int dp83867_of_init(struct phy_device *phydev)
572{
573 struct dp83867_private *dp83867 = phydev->priv;
e5a03bfd 574 struct device *dev = &phydev->mdio.dev;
2a10154a
DM		 575 struct device_node *of_node = dev->of_node;
576 int ret;
577
7bf9ae01 578 if (!of_node)
2a10154a
DM		 579 return -ENODEV;
580
ed838fe9 581 /* Optional configuration */
9708fb63
WE		 582 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
583 &dp83867->clk_output_sel);
13c83cf8
TP		 584 /* If not set, keep default */
585 if (!ret) {
586 dp83867->set_clk_output = true;
587 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
588 * DP83867_CLK_O_SEL_OFF.
9708fb63 589 */
13c83cf8
TP		 590 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
591 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
592 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
593 dp83867->clk_output_sel);
594 return -EINVAL;
595 }
596 }
9708fb63 597
5c2d0a6a
RV		 598 ret = dp83867_of_init_io_impedance(phydev);
599 if (ret)
600 return ret;
ed838fe9 601
37144476 602 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
753c66ef 603 "ti,dp83867-rxctrl-strap-quirk");
37144476 604
507ddd5c 605 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
753c66ef 606 "ti,sgmii-ref-clock-output-enable");
c11669a2 607
fafc5db2
GS		 608 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
609 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
610 &dp83867->rx_id_delay);
611 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
612 phydev_err(phydev,
613 "ti,rx-internal-delay value of %u out of range\n",
614 dp83867->rx_id_delay);
615 return -EINVAL;
c11669a2
TP		 616 }
617
fafc5db2
GS		 618 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
619 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
620 &dp83867->tx_id_delay);
621 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
622 phydev_err(phydev,
623 "ti,tx-internal-delay value of %u out of range\n",
624 dp83867->tx_id_delay);
625 return -EINVAL;
c11669a2 626 }
2a10154a 627
fc6d39c3
LM		 628 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
629 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
630
631 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
632 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
633
f8bbf417 634 ret = of_property_read_u32(of_node, "ti,fifo-depth",
e02d1816 635 &dp83867->tx_fifo_depth);
f8bbf417 636 if (ret) {
e02d1816
DM		 637 ret = of_property_read_u32(of_node, "tx-fifo-depth",
638 &dp83867->tx_fifo_depth);
639 if (ret)
640 dp83867->tx_fifo_depth =
641 DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
f8bbf417 642 }
e02d1816
DM		 643
644 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
645 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
646 dp83867->tx_fifo_depth);
647 return -EINVAL;
648 }
649
650 ret = of_property_read_u32(of_node, "rx-fifo-depth",
651 &dp83867->rx_fifo_depth);
652 if (ret)
653 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
654
655 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
656 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
657 dp83867->rx_fifo_depth);
f8bbf417
TP		 658 return -EINVAL;
659 }
e02d1816 660
f8bbf417 661 return 0;
2a10154a
DM		 662}
663#else
664static int dp83867_of_init(struct phy_device *phydev)
665{
4dc08dcc
LKL		 666 struct dp83867_private *dp83867 = phydev->priv;
667 u16 delay;
668
669 /* For non-OF device, the RX and TX ID values are either strapped
670 * or take from default value. So, we init RX & TX ID values here
671 * so that the RGMIIDCTL is configured correctly later in
672 * dp83867_config_init();
673 */
674 delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL);
675 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX;
676 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) &
677 DP83867_RGMII_TX_CLK_DELAY_MAX;
678
679 /* Per datasheet, IO impedance is default to 50-ohm, so we set the
680 * same here or else the default '0' means highest IO impedance
681 * which is wrong.
682 */
683 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2;
684
e2a54350
MSWH		 685 /* For non-OF device, the RX and TX FIFO depths are taken from
686 * default value. So, we init RX & TX FIFO depths here
687 * so that it is configured correctly later in dp83867_config_init();
688 */
689 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
690 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
691
2a10154a
DM		 692 return 0;
693}
694#endif /* CONFIG_OF_MDIO */
695
565d9d22 696static int dp83867_probe(struct phy_device *phydev)
2a10154a
DM		 697{
698 struct dp83867_private *dp83867;
565d9d22
TP		 699
700 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
701 GFP_KERNEL);
702 if (!dp83867)
703 return -ENOMEM;
704
705 phydev->priv = dp83867;
706
ef87f7da 707 return dp83867_of_init(phydev);
565d9d22
TP		 708}
709
710static int dp83867_config_init(struct phy_device *phydev)
711{
712 struct dp83867_private *dp83867 = phydev->priv;
ac6e058b 713 int ret, val, bs;
b291c418 714 u16 delay;
2a10154a 715
cd26d72d
DM		 716 /* Force speed optimization for the PHY even if it strapped */
717 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
718 DP83867_DOWNSHIFT_EN);
719 if (ret)
720 return ret;
721
fafc5db2
GS		 722 ret = dp83867_verify_rgmii_cfg(phydev);
723 if (ret)
724 return ret;
725
37144476 726 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
b52c018d
HK		 727 if (dp83867->rxctrl_strap_quirk)
728 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
729 BIT(7));
37144476 730
749f6f68
GS		 731 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
732 if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
733 /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
734 * be set to 0x2. This may causes the PHY link to be unstable -
735 * the default value 0x1 need to be restored.
736 */
737 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
738 DP83867_FLD_THR_CFG,
739 DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
740 0x1);
741 if (ret)
742 return ret;
743 }
744
e02d1816
DM		 745 if (phy_interface_is_rgmii(phydev) ||
746 phydev->interface == PHY_INTERFACE_MODE_SGMII) {
747 val = phy_read(phydev, MII_DP83867_PHYCTRL);
748 if (val < 0)
749 return val;
750
751 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
752 val |= (dp83867->tx_fifo_depth <<
753 DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
754
755 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
756 val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
757 val |= (dp83867->rx_fifo_depth <<
758 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
759 }
760
761 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
762 if (ret)
763 return ret;
764 }
765
2a10154a 766 if (phy_interface_is_rgmii(phydev)) {
b291c418
SH		 767 val = phy_read(phydev, MII_DP83867_PHYCTRL);
768 if (val < 0)
769 return val;
ac6e058b
LM		 770
771 /* The code below checks if "port mirroring" N/A MODE4 has been
772 * enabled during power on bootstrap.
773 *
774 * Such N/A mode enabled by mistake can put PHY IC in some
775 * internal testing mode and disable RGMII transmission.
776 *
777 * In this particular case one needs to check STRAP_STS1
778 * register's bit 11 (marked as RESERVED).
779 */
780
a6d99fcd 781 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
ac6e058b
LM		 782 if (bs & DP83867_STRAP_STS1_RESERVED)
783 val &= ~DP83867_PHYCR_RESERVED_MASK;
784
b291c418 785 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
2a10154a
DM		 786 if (ret)
787 return ret;
2a10154a 788
b4b12b0d
DM		 789 /* If rgmii mode with no internal delay is selected, we do NOT use
790 * aligned mode as one might expect. Instead we use the PHY's default
791 * based on pin strapping. And the "mode 0" default is to *use*
792 * internal delay with a value of 7 (2.00 ns).
793 *
794 * Set up RGMII delays
795 */
a6d99fcd 796 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
2a10154a 797
c11669a2 798 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
2a10154a
DM		 799 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
800 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
801
802 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
803 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
804
805 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
806 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
807
a6d99fcd 808 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
2a10154a 809
fafc5db2
GS		 810 delay = 0;
811 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
812 delay |= dp83867->rx_id_delay;
813 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
814 delay |= dp83867->tx_id_delay <<
815 DP83867_RGMII_TX_CLK_DELAY_SHIFT;
2a10154a 816
a6d99fcd
RK		 817 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
818 delay);
2a10154a
DM		 819 }
820
27708eb5
TP		 821 /* If specified, set io impedance */
822 if (dp83867->io_impedance >= 0)
823 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
824 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
825 dp83867->io_impedance);
826
333061b9
MU		 827 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
828 /* For support SPEED_10 in SGMII mode
829 * DP83867_10M_SGMII_RATE_ADAPT bit
830 * has to be cleared by software. That
831 * does not affect SPEED_100 and
832 * SPEED_1000.
833 */
834 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
835 DP83867_10M_SGMII_CFG,
836 DP83867_10M_SGMII_RATE_ADAPT_MASK,
837 0);
838 if (ret)
839 return ret;
1a97a477
MU		 840
841 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
842 * are 01). That is not enough to finalize autoneg on some
843 * devices. Increase this timer duration to maximum 16ms.
844 */
845 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
846 DP83867_CFG4,
847 DP83867_CFG4_SGMII_ANEG_MASK,
848 DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
849
850 if (ret)
851 return ret;
507ddd5c
VG		 852
853 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
854 /* SGMII type is set to 4-wire mode by default.
855 * If we place appropriate property in dts (see above)
856 * switch on 6-wire mode.
857 */
858 if (dp83867->sgmii_ref_clk_en)
859 val |= DP83867_SGMII_TYPE;
860 else
861 val &= ~DP83867_SGMII_TYPE;
862 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
0c9efbd5
HK		 863
864 /* This is a SW workaround for link instability if RX_CTRL is
865 * not strapped to mode 3 or 4 in HW. This is required for SGMII
866 * in addition to clearing bit 7, handled above.
867 */
868 if (dp83867->rxctrl_strap_quirk)
869 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
870 BIT(8));
333061b9
MU		 871 }
872
5a7f08c2 873 val = phy_read(phydev, DP83867_CFG3);
5ca7d1ca 874 /* Enable Interrupt output INT_OE in CFG3 register */
5a7f08c2
GS		 875 if (phy_interrupt_is_valid(phydev))
876 val |= DP83867_CFG3_INT_OE;
877
878 val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
879 phy_write(phydev, DP83867_CFG3, val);
5ca7d1ca 880
fc6d39c3
LM		 881 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
882 dp83867_config_port_mirroring(phydev);
883
9708fb63 884 /* Clock output selection if muxing property is set */
13c83cf8
TP		 885 if (dp83867->set_clk_output) {
886 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
887
888 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
889 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
890 } else {
891 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
892 val = dp83867->clk_output_sel <<
893 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
894 }
895
b52c018d 896 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
13c83cf8
TP		 897 mask, val);
898 }
9708fb63 899
2a10154a
DM		 900 return 0;
901}
902
903static int dp83867_phy_reset(struct phy_device *phydev)
904{
905 int err;
906
da9ef50f 907 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
2a10154a
DM		 908 if (err < 0)
909 return err;
910
72a7d452
MU		 911 usleep_range(10, 20);
912
86ffe920
MG		 913 return phy_modify(phydev, MII_DP83867_PHYCTRL,
914 DP83867_PHYCR_FORCE_LINK_GOOD, 0);
2a10154a
DM		 915}
916
c76acfb7
TTM		 917static void dp83867_link_change_notify(struct phy_device *phydev)
918{
919 /* There is a limitation in DP83867 PHY device where SGMII AN is
920 * only triggered once after the device is booted up. Even after the
921 * PHY TPI is down and up again, SGMII AN is not triggered and
922 * hence no new in-band message from PHY to MAC side SGMII.
923 * This could cause an issue during power up, when PHY is up prior
924 * to MAC. At this condition, once MAC side SGMII is up, MAC side
925 * SGMII wouldn`t receive new in-band message from TI PHY with
926 * correct link status, speed and duplex info.
927 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg
928 * whenever there is a link change.
929 */
930 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
931 int val = 0;
932
933 val = phy_clear_bits(phydev, DP83867_CFG2,
934 DP83867_SGMII_AUTONEG_EN);
935 if (val < 0)
936 return;
937
938 phy_set_bits(phydev, DP83867_CFG2,
939 DP83867_SGMII_AUTONEG_EN);
940 }
941}
942
13bd8558
TTM		 943static int dp83867_loopback(struct phy_device *phydev, bool enable)
944{
945 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
946 enable ? BMCR_LOOPBACK : 0);
947}
948
2a10154a
DM		 949static struct phy_driver dp83867_driver[] = {
950 {
951 .phy_id = DP83867_PHY_ID,
952 .phy_id_mask = 0xfffffff0,
953 .name = "TI DP83867",
dcdecdcf 954 /* PHY_GBIT_FEATURES */
2a10154a 955
565d9d22 956 .probe = dp83867_probe,
2a10154a
DM		 957 .config_init = dp83867_config_init,
958 .soft_reset = dp83867_phy_reset,
959
cd26d72d
DM		 960 .read_status = dp83867_read_status,
961 .get_tunable = dp83867_get_tunable,
962 .set_tunable = dp83867_set_tunable,
963
caabee5b
TH		 964 .get_wol = dp83867_get_wol,
965 .set_wol = dp83867_set_wol,
966
2a10154a 967 /* IRQ related */
2a10154a 968 .config_intr = dp83867_config_intr,
1d1ae3c6 969 .handle_interrupt = dp83867_handle_interrupt,
2a10154a 970
2a10154a
DM		 971 .suspend = genphy_suspend,
972 .resume = genphy_resume,
c76acfb7
TTM		 973
974 .link_change_notify = dp83867_link_change_notify,
13bd8558 975 .set_loopback = dp83867_loopback,
2a10154a
DM		 976 },
977};
978module_phy_driver(dp83867_driver);
979
980static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
981 { DP83867_PHY_ID, 0xfffffff0 },
982 { }
983};
984
985MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
986
987MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
988MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
5f857575 989MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)