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net: reject PTP periodic output requests with unsupported flags
[linux-2.6-block.git] / drivers / net / phy / dp83640.c
CommitLineData
a2443fd1 1// SPDX-License-Identifier: GPL-2.0+
cb646e2b
RC		 2/*
3 * Driver for the National Semiconductor DP83640 PHYTER
4 *
5 * Copyright (C) 2010 OMICRON electronics GmbH
cb646e2b 6 */
8d242488
JP		 7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
539e44d2 10#include <linux/crc32.h>
cb646e2b
RC		 11#include <linux/ethtool.h>
12#include <linux/kernel.h>
13#include <linux/list.h>
14#include <linux/mii.h>
15#include <linux/module.h>
16#include <linux/net_tstamp.h>
17#include <linux/netdevice.h>
408eccce 18#include <linux/if_vlan.h>
cb646e2b
RC		 19#include <linux/phy.h>
20#include <linux/ptp_classify.h>
21#include <linux/ptp_clock_kernel.h>
22
23#include "dp83640_reg.h"
24
25#define DP83640_PHY_ID 0x20005ce1
26#define PAGESEL 0x13
8028837d 27#define MAX_RXTS 64
49b3fd4a 28#define N_EXT_TS 6
ad01577a 29#define N_PER_OUT 7
cb646e2b
RC		 30#define PSF_PTPVER 2
31#define PSF_EVNT 0x4000
32#define PSF_RX 0x2000
33#define PSF_TX 0x1000
34#define EXT_EVENT 1
49b3fd4a 35#define CAL_EVENT 7
397a253a 36#define CAL_TRIGGER 1
86dd3612 37#define DP83640_N_PINS 12
cb646e2b 38
1642182e
SG		 39#define MII_DP83640_MICR 0x11
40#define MII_DP83640_MISR 0x12
41
42#define MII_DP83640_MICR_OE 0x1
43#define MII_DP83640_MICR_IE 0x2
44
45#define MII_DP83640_MISR_RHF_INT_EN 0x01
46#define MII_DP83640_MISR_FHF_INT_EN 0x02
47#define MII_DP83640_MISR_ANC_INT_EN 0x04
48#define MII_DP83640_MISR_DUP_INT_EN 0x08
49#define MII_DP83640_MISR_SPD_INT_EN 0x10
50#define MII_DP83640_MISR_LINK_INT_EN 0x20
51#define MII_DP83640_MISR_ED_INT_EN 0x40
52#define MII_DP83640_MISR_LQ_INT_EN 0x80
53
cb646e2b
RC		 54/* phyter seems to miss the mark by 16 ns */
55#define ADJTIME_FIX 16
56
4b063258
SS		 57#define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */
58
cb646e2b
RC		 59#if defined(__BIG_ENDIAN)
60#define ENDIAN_FLAG 0
61#elif defined(__LITTLE_ENDIAN)
62#define ENDIAN_FLAG PSF_ENDIAN
63#endif
64
63502b8d
SS		 65struct dp83640_skb_info {
66 int ptp_type;
67 unsigned long tmo;
68};
cb646e2b
RC		 69
70struct phy_rxts {
71 u16 ns_lo; /* ns[15:0] */
72 u16 ns_hi; /* overflow[1:0], ns[29:16] */
73 u16 sec_lo; /* sec[15:0] */
74 u16 sec_hi; /* sec[31:16] */
75 u16 seqid; /* sequenceId[15:0] */
76 u16 msgtype; /* messageType[3:0], hash[11:0] */
77};
78
79struct phy_txts {
80 u16 ns_lo; /* ns[15:0] */
81 u16 ns_hi; /* overflow[1:0], ns[29:16] */
82 u16 sec_lo; /* sec[15:0] */
83 u16 sec_hi; /* sec[31:16] */
84};
85
86struct rxts {
87 struct list_head list;
88 unsigned long tmo;
89 u64 ns;
90 u16 seqid;
91 u8 msgtype;
92 u16 hash;
93};
94
95struct dp83640_clock;
96
97struct dp83640_private {
98 struct list_head list;
99 struct dp83640_clock *clock;
100 struct phy_device *phydev;
4b063258 101 struct delayed_work ts_work;
cb646e2b
RC		 102 int hwts_tx_en;
103 int hwts_rx_en;
104 int layer;
105 int version;
106 /* remember state of cfg0 during calibration */
107 int cfg0;
108 /* remember the last event time stamp */
109 struct phy_txts edata;
110 /* list of rx timestamps */
111 struct list_head rxts;
112 struct list_head rxpool;
113 struct rxts rx_pool_data[MAX_RXTS];
114 /* protects above three fields from concurrent access */
115 spinlock_t rx_lock;
116 /* queues of incoming and outgoing packets */
117 struct sk_buff_head rx_queue;
118 struct sk_buff_head tx_queue;
119};
120
121struct dp83640_clock {
122 /* keeps the instance in the 'phyter_clocks' list */
123 struct list_head list;
124 /* we create one clock instance per MII bus */
125 struct mii_bus *bus;
126 /* protects extended registers from concurrent access */
127 struct mutex extreg_lock;
128 /* remembers which page was last selected */
129 int page;
130 /* our advertised capabilities */
131 struct ptp_clock_info caps;
132 /* protects the three fields below from concurrent access */
133 struct mutex clock_lock;
134 /* the one phyter from which we shall read */
135 struct dp83640_private *chosen;
136 /* list of the other attached phyters, not chosen */
137 struct list_head phylist;
138 /* reference to our PTP hardware clock */
139 struct ptp_clock *ptp_clock;
140};
141
142/* globals */
143
49b3fd4a
RC		 144enum {
145 CALIBRATE_GPIO,
146 PEROUT_GPIO,
147 EXTTS0_GPIO,
148 EXTTS1_GPIO,
149 EXTTS2_GPIO,
150 EXTTS3_GPIO,
151 EXTTS4_GPIO,
152 EXTTS5_GPIO,
153 GPIO_TABLE_SIZE
154};
155
cb646e2b 156static int chosen_phy = -1;
49b3fd4a
RC		 157static ushort gpio_tab[GPIO_TABLE_SIZE] = {
158 1, 2, 3, 4, 8, 9, 10, 11
159};
cb646e2b
RC		 160
161module_param(chosen_phy, int, 0444);
49b3fd4a 162module_param_array(gpio_tab, ushort, NULL, 0444);
cb646e2b
RC		 163
164MODULE_PARM_DESC(chosen_phy, \
165 "The address of the PHY to use for the ancillary clock features");
49b3fd4a
RC		 166MODULE_PARM_DESC(gpio_tab, \
167 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
cb646e2b 168
86dd3612
RC		 169static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
170{
171 int i, index;
172
173 for (i = 0; i < DP83640_N_PINS; i++) {
174 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
175 pd[i].index = i;
176 }
177
178 for (i = 0; i < GPIO_TABLE_SIZE; i++) {
179 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
180 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
181 return;
182 }
183 }
184
185 index = gpio_tab[CALIBRATE_GPIO] - 1;
186 pd[index].func = PTP_PF_PHYSYNC;
187 pd[index].chan = 0;
188
189 index = gpio_tab[PEROUT_GPIO] - 1;
190 pd[index].func = PTP_PF_PEROUT;
191 pd[index].chan = 0;
192
193 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
194 index = gpio_tab[i] - 1;
195 pd[index].func = PTP_PF_EXTTS;
196 pd[index].chan = i - EXTTS0_GPIO;
197 }
198}
199
cb646e2b
RC		 200/* a list of clocks and a mutex to protect it */
201static LIST_HEAD(phyter_clocks);
202static DEFINE_MUTEX(phyter_clocks_lock);
203
204static void rx_timestamp_work(struct work_struct *work);
205
206/* extended register access functions */
207
208#define BROADCAST_ADDR 31
209
e5a03bfd
AL		 210static inline int broadcast_write(struct phy_device *phydev, u32 regnum,
211 u16 val)
cb646e2b 212{
e5a03bfd 213 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val);
cb646e2b
RC		 214}
215
216/* Caller must hold extreg_lock. */
217static int ext_read(struct phy_device *phydev, int page, u32 regnum)
218{
219 struct dp83640_private *dp83640 = phydev->priv;
220 int val;
221
222 if (dp83640->clock->page != page) {
e5a03bfd 223 broadcast_write(phydev, PAGESEL, page);
cb646e2b
RC		 224 dp83640->clock->page = page;
225 }
226 val = phy_read(phydev, regnum);
227
228 return val;
229}
230
231/* Caller must hold extreg_lock. */
232static void ext_write(int broadcast, struct phy_device *phydev,
233 int page, u32 regnum, u16 val)
234{
235 struct dp83640_private *dp83640 = phydev->priv;
236
237 if (dp83640->clock->page != page) {
e5a03bfd 238 broadcast_write(phydev, PAGESEL, page);
cb646e2b
RC		 239 dp83640->clock->page = page;
240 }
241 if (broadcast)
e5a03bfd 242 broadcast_write(phydev, regnum, val);
cb646e2b
RC		 243 else
244 phy_write(phydev, regnum, val);
245}
246
247/* Caller must hold extreg_lock. */
248static int tdr_write(int bc, struct phy_device *dev,
41c2c18f 249 const struct timespec64 *ts, u16 cmd)
cb646e2b
RC		 250{
251 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
252 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
253 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
254 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
255
256 ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
257
258 return 0;
259}
260
261/* convert phy timestamps into driver timestamps */
262
263static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
264{
265 u32 sec;
266
267 sec = p->sec_lo;
268 sec |= p->sec_hi << 16;
269
270 rxts->ns = p->ns_lo;
271 rxts->ns |= (p->ns_hi & 0x3fff) << 16;
272 rxts->ns += ((u64)sec) * 1000000000ULL;
273 rxts->seqid = p->seqid;
274 rxts->msgtype = (p->msgtype >> 12) & 0xf;
275 rxts->hash = p->msgtype & 0x0fff;
4b063258 276 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
cb646e2b
RC		 277}
278
279static u64 phy2txts(struct phy_txts *p)
280{
281 u64 ns;
282 u32 sec;
283
284 sec = p->sec_lo;
285 sec |= p->sec_hi << 16;
286
287 ns = p->ns_lo;
288 ns |= (p->ns_hi & 0x3fff) << 16;
289 ns += ((u64)sec) * 1000000000ULL;
290
291 return ns;
292}
293
621bdecc 294static int periodic_output(struct dp83640_clock *clock,
ad01577a
SS		 295 struct ptp_clock_request *clkreq, bool on,
296 int trigger)
49b3fd4a
RC		 297{
298 struct dp83640_private *dp83640 = clock->chosen;
299 struct phy_device *phydev = dp83640->phydev;
564ca56e 300 u32 sec, nsec, pwidth;
ad01577a 301 u16 gpio, ptp_trig, val;
49b3fd4a 302
621bdecc 303 if (on) {
ad01577a
SS		 304 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
305 trigger);
621bdecc
RC		 306 if (gpio < 1)
307 return -EINVAL;
308 } else {
309 gpio = 0;
310 }
311
49b3fd4a
RC		 312 ptp_trig = TRIG_WR |
313 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
314 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
315 TRIG_PER |
316 TRIG_PULSE;
317
318 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
319
320 if (!on) {
321 val |= TRIG_DIS;
322 mutex_lock(&clock->extreg_lock);
323 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
324 ext_write(0, phydev, PAGE4, PTP_CTL, val);
325 mutex_unlock(&clock->extreg_lock);
621bdecc 326 return 0;
49b3fd4a
RC		 327 }
328
329 sec = clkreq->perout.start.sec;
330 nsec = clkreq->perout.start.nsec;
564ca56e
RC		 331 pwidth = clkreq->perout.period.sec * 1000000000UL;
332 pwidth += clkreq->perout.period.nsec;
333 pwidth /= 2;
49b3fd4a
RC		 334
335 mutex_lock(&clock->extreg_lock);
336
337 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
338
339 /*load trigger*/
340 val |= TRIG_LOAD;
341 ext_write(0, phydev, PAGE4, PTP_CTL, val);
342 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */
343 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */
344 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */
345 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */
564ca56e
RC		 346 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
347 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */
35e872ae
SS		 348 /* Triggers 0 and 1 has programmable pulsewidth2 */
349 if (trigger < 2) {
350 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
351 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
352 }
49b3fd4a
RC		 353
354 /*enable trigger*/
355 val &= ~TRIG_LOAD;
356 val |= TRIG_EN;
357 ext_write(0, phydev, PAGE4, PTP_CTL, val);
358
359 mutex_unlock(&clock->extreg_lock);
621bdecc 360 return 0;
49b3fd4a
RC		 361}
362
cb646e2b
RC		 363/* ptp clock methods */
364
e4788b80 365static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
cb646e2b
RC		 366{
367 struct dp83640_clock *clock =
368 container_of(ptp, struct dp83640_clock, caps);
369 struct phy_device *phydev = clock->chosen->phydev;
370 u64 rate;
371 int neg_adj = 0;
372 u16 hi, lo;
373
e4788b80 374 if (scaled_ppm < 0) {
cb646e2b 375 neg_adj = 1;
e4788b80 376 scaled_ppm = -scaled_ppm;
cb646e2b 377 }
e4788b80
RC		 378 rate = scaled_ppm;
379 rate <<= 13;
380 rate = div_u64(rate, 15625);
cb646e2b
RC		 381
382 hi = (rate >> 16) & PTP_RATE_HI_MASK;
383 if (neg_adj)
384 hi |= PTP_RATE_DIR;
385
386 lo = rate & 0xffff;
387
388 mutex_lock(&clock->extreg_lock);
389
390 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
391 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
392
393 mutex_unlock(&clock->extreg_lock);
394
395 return 0;
396}
397
398static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
399{
400 struct dp83640_clock *clock =
401 container_of(ptp, struct dp83640_clock, caps);
402 struct phy_device *phydev = clock->chosen->phydev;
41c2c18f 403 struct timespec64 ts;
cb646e2b
RC		 404 int err;
405
406 delta += ADJTIME_FIX;
407
41c2c18f 408 ts = ns_to_timespec64(delta);
cb646e2b
RC		 409
410 mutex_lock(&clock->extreg_lock);
411
412 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
413
414 mutex_unlock(&clock->extreg_lock);
415
416 return err;
417}
418
41c2c18f
RC		 419static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,
420 struct timespec64 *ts)
cb646e2b
RC		 421{
422 struct dp83640_clock *clock =
423 container_of(ptp, struct dp83640_clock, caps);
424 struct phy_device *phydev = clock->chosen->phydev;
425 unsigned int val[4];
426
427 mutex_lock(&clock->extreg_lock);
428
429 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
430
431 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
432 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
433 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
434 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
435
436 mutex_unlock(&clock->extreg_lock);
437
438 ts->tv_nsec = val[0] | (val[1] << 16);
439 ts->tv_sec = val[2] | (val[3] << 16);
440
441 return 0;
442}
443
444static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
41c2c18f 445 const struct timespec64 *ts)
cb646e2b
RC		 446{
447 struct dp83640_clock *clock =
448 container_of(ptp, struct dp83640_clock, caps);
449 struct phy_device *phydev = clock->chosen->phydev;
450 int err;
451
452 mutex_lock(&clock->extreg_lock);
453
454 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
455
456 mutex_unlock(&clock->extreg_lock);
457
458 return err;
459}
460
461static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
462 struct ptp_clock_request *rq, int on)
463{
464 struct dp83640_clock *clock =
465 container_of(ptp, struct dp83640_clock, caps);
466 struct phy_device *phydev = clock->chosen->phydev;
fbf4b934 467 unsigned int index;
49b3fd4a 468 u16 evnt, event_num, gpio_num;
cb646e2b
RC		 469
470 switch (rq->type) {
471 case PTP_CLK_REQ_EXTTS:
49b3fd4a 472 index = rq->extts.index;
fbf4b934 473 if (index >= N_EXT_TS)
cb646e2b 474 return -EINVAL;
49b3fd4a
RC		 475 event_num = EXT_EVENT + index;
476 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
cb646e2b 477 if (on) {
faa89716
RC		 478 gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
479 PTP_PF_EXTTS, index);
480 if (gpio_num < 1)
481 return -EINVAL;
49b3fd4a 482 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
80671bd2
SS		 483 if (rq->extts.flags & PTP_FALLING_EDGE)
484 evnt |= EVNT_FALL;
485 else
486 evnt |= EVNT_RISE;
cb646e2b 487 }
a935865c 488 mutex_lock(&clock->extreg_lock);
cb646e2b 489 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
a935865c 490 mutex_unlock(&clock->extreg_lock);
cb646e2b 491 return 0;
49b3fd4a
RC		 492
493 case PTP_CLK_REQ_PEROUT:
7f9048f1
JK		 494 /* Reject requests with unsupported flags */
495 if (rq->perout.flags)
496 return -EOPNOTSUPP;
ad01577a 497 if (rq->perout.index >= N_PER_OUT)
49b3fd4a 498 return -EINVAL;
ad01577a 499 return periodic_output(clock, rq, on, rq->perout.index);
49b3fd4a 500
cb646e2b
RC		 501 default:
502 break;
503 }
504
505 return -EOPNOTSUPP;
506}
507
86dd3612
RC		 508static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
509 enum ptp_pin_function func, unsigned int chan)
510{
6f39eb87
SS		 511 struct dp83640_clock *clock =
512 container_of(ptp, struct dp83640_clock, caps);
513
514 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
515 !list_empty(&clock->phylist))
516 return 1;
517
518 if (func == PTP_PF_PHYSYNC)
519 return 1;
520
86dd3612
RC		 521 return 0;
522}
523
cb646e2b
RC		 524static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
525static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
526
527static void enable_status_frames(struct phy_device *phydev, bool on)
528{
a935865c
RC		 529 struct dp83640_private *dp83640 = phydev->priv;
530 struct dp83640_clock *clock = dp83640->clock;
cb646e2b
RC		 531 u16 cfg0 = 0, ver;
532
533 if (on)
534 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
535
536 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
537
a935865c
RC		 538 mutex_lock(&clock->extreg_lock);
539
cb646e2b
RC		 540 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
541 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
542
a935865c
RC		 543 mutex_unlock(&clock->extreg_lock);
544
cb646e2b 545 if (!phydev->attached_dev) {
ab2a605f
AL		 546 phydev_warn(phydev,
547 "expected to find an attached netdevice\n");
cb646e2b
RC		 548 return;
549 }
550
551 if (on) {
552 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
ab2a605f 553 phydev_warn(phydev, "failed to add mc address\n");
cb646e2b
RC		 554 } else {
555 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
ab2a605f 556 phydev_warn(phydev, "failed to delete mc address\n");
cb646e2b
RC		 557 }
558}
559
560static bool is_status_frame(struct sk_buff *skb, int type)
561{
562 struct ethhdr *h = eth_hdr(skb);
563
564 if (PTP_CLASS_V2_L2 == type &&
565 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
566 return true;
567 else
568 return false;
569}
570
571static int expired(struct rxts *rxts)
572{
573 return time_after(jiffies, rxts->tmo);
574}
575
576/* Caller must hold rx_lock. */
577static void prune_rx_ts(struct dp83640_private *dp83640)
578{
579 struct list_head *this, *next;
580 struct rxts *rxts;
581
582 list_for_each_safe(this, next, &dp83640->rxts) {
583 rxts = list_entry(this, struct rxts, list);
584 if (expired(rxts)) {
585 list_del_init(&rxts->list);
586 list_add(&rxts->list, &dp83640->rxpool);
587 }
588 }
589}
590
591/* synchronize the phyters so they act as one clock */
592
593static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
594{
595 int val;
596 phy_write(phydev, PAGESEL, 0);
597 val = phy_read(phydev, PHYCR2);
598 if (on)
599 val |= BC_WRITE;
600 else
601 val &= ~BC_WRITE;
602 phy_write(phydev, PHYCR2, val);
603 phy_write(phydev, PAGESEL, init_page);
604}
605
606static void recalibrate(struct dp83640_clock *clock)
607{
608 s64 now, diff;
609 struct phy_txts event_ts;
41c2c18f 610 struct timespec64 ts;
cb646e2b
RC		 611 struct list_head *this;
612 struct dp83640_private *tmp;
613 struct phy_device *master = clock->chosen->phydev;
49b3fd4a 614 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
cb646e2b
RC		 615
616 trigger = CAL_TRIGGER;
e0155950
SS		 617 cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
618 if (cal_gpio < 1) {
f42cf8d6 619 pr_err("PHY calibration pin not available - PHY is not calibrated.");
e0155950
SS		 620 return;
621 }
cb646e2b
RC		 622
623 mutex_lock(&clock->extreg_lock);
624
625 /*
626 * enable broadcast, disable status frames, enable ptp clock
627 */
628 list_for_each(this, &clock->phylist) {
629 tmp = list_entry(this, struct dp83640_private, list);
630 enable_broadcast(tmp->phydev, clock->page, 1);
631 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
632 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
633 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
634 }
635 enable_broadcast(master, clock->page, 1);
636 cfg0 = ext_read(master, PAGE5, PSF_CFG0);
637 ext_write(0, master, PAGE5, PSF_CFG0, 0);
638 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
639
640 /*
641 * enable an event timestamp
642 */
643 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
644 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
645 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
646
647 list_for_each(this, &clock->phylist) {
648 tmp = list_entry(this, struct dp83640_private, list);
649 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
650 }
651 ext_write(0, master, PAGE5, PTP_EVNT, evnt);
652
653 /*
654 * configure a trigger
655 */
656 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
657 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
658 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
659 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
660
661 /* load trigger */
662 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
663 val |= TRIG_LOAD;
664 ext_write(0, master, PAGE4, PTP_CTL, val);
665
666 /* enable trigger */
667 val &= ~TRIG_LOAD;
668 val |= TRIG_EN;
669 ext_write(0, master, PAGE4, PTP_CTL, val);
670
671 /* disable trigger */
672 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
673 val |= TRIG_DIS;
674 ext_write(0, master, PAGE4, PTP_CTL, val);
675
676 /*
677 * read out and correct offsets
678 */
679 val = ext_read(master, PAGE4, PTP_STS);
c4fabb8b 680 phydev_info(master, "master PTP_STS 0x%04hx\n", val);
cb646e2b 681 val = ext_read(master, PAGE4, PTP_ESTS);
c4fabb8b 682 phydev_info(master, "master PTP_ESTS 0x%04hx\n", val);
cb646e2b
RC		 683 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
684 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
685 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
686 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
687 now = phy2txts(&event_ts);
688
689 list_for_each(this, &clock->phylist) {
690 tmp = list_entry(this, struct dp83640_private, list);
691 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
c4fabb8b 692 phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val);
cb646e2b 693 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
c4fabb8b 694 phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val);
cb646e2b
RC		 695 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
696 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
697 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
698 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
699 diff = now - (s64) phy2txts(&event_ts);
c4fabb8b
AL		 700 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n",
701 diff);
cb646e2b 702 diff += ADJTIME_FIX;
41c2c18f 703 ts = ns_to_timespec64(diff);
cb646e2b
RC		 704 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
705 }
706
707 /*
708 * restore status frames
709 */
710 list_for_each(this, &clock->phylist) {
711 tmp = list_entry(this, struct dp83640_private, list);
712 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
713 }
714 ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
715
716 mutex_unlock(&clock->extreg_lock);
717}
718
719/* time stamping methods */
720
49b3fd4a
RC		 721static inline u16 exts_chan_to_edata(int ch)
722{
723 return 1 << ((ch + EXT_EVENT) * 2);
724}
725
2331038a 726static int decode_evnt(struct dp83640_private *dp83640,
13322f2e 727 void *data, int len, u16 ests)
cb646e2b 728{
2331038a 729 struct phy_txts *phy_txts;
cb646e2b 730 struct ptp_clock_event event;
49b3fd4a 731 int i, parsed;
cb646e2b 732 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
2331038a
RC		 733 u16 ext_status = 0;
734
13322f2e
CR		 735 /* calculate length of the event timestamp status message */
736 if (ests & MULT_EVNT)
737 parsed = (words + 2) * sizeof(u16);
738 else
739 parsed = (words + 1) * sizeof(u16);
740
741 /* check if enough data is available */
742 if (len < parsed)
743 return len;
744
2331038a
RC		 745 if (ests & MULT_EVNT) {
746 ext_status = *(u16 *) data;
747 data += sizeof(ext_status);
748 }
749
750 phy_txts = data;
cb646e2b 751
d331e758 752 switch (words) {
cb646e2b
RC		 753 case 3:
754 dp83640->edata.sec_hi = phy_txts->sec_hi;
d331e758 755 /* fall through */
cb646e2b
RC		 756 case 2:
757 dp83640->edata.sec_lo = phy_txts->sec_lo;
d331e758 758 /* fall through */
cb646e2b
RC		 759 case 1:
760 dp83640->edata.ns_hi = phy_txts->ns_hi;
d331e758 761 /* fall through */
cb646e2b
RC		 762 case 0:
763 dp83640->edata.ns_lo = phy_txts->ns_lo;
764 }
765
13322f2e 766 if (!ext_status) {
49b3fd4a
RC		 767 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
768 ext_status = exts_chan_to_edata(i);
769 }
770
cb646e2b 771 event.type = PTP_CLOCK_EXTTS;
cb646e2b
RC		 772 event.timestamp = phy2txts(&dp83640->edata);
773
a0077a9f
SS		 774 /* Compensate for input path and synchronization delays */
775 event.timestamp -= 35;
776
49b3fd4a
RC		 777 for (i = 0; i < N_EXT_TS; i++) {
778 if (ext_status & exts_chan_to_edata(i)) {
779 event.index = i;
780 ptp_clock_event(dp83640->clock->ptp_clock, &event);
781 }
782 }
2331038a 783
13322f2e 784 return parsed;
cb646e2b
RC		 785}
786
539e44d2
SS		 787#define DP83640_PACKET_HASH_OFFSET 20
788#define DP83640_PACKET_HASH_LEN 10
789
63502b8d
SS		 790static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
791{
539e44d2 792 u16 *seqid, hash;
63502b8d
SS		 793 unsigned int offset = 0;
794 u8 *msgtype, *data = skb_mac_header(skb);
795
796 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
797
798 if (type & PTP_CLASS_VLAN)
799 offset += VLAN_HLEN;
800
801 switch (type & PTP_CLASS_PMASK) {
802 case PTP_CLASS_IPV4:
cca04b28 803 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
63502b8d
SS		 804 break;
805 case PTP_CLASS_IPV6:
806 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
807 break;
808 case PTP_CLASS_L2:
809 offset += ETH_HLEN;
810 break;
811 default:
812 return 0;
813 }
814
815 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
816 return 0;
817
818 if (unlikely(type & PTP_CLASS_V1))
819 msgtype = data + offset + OFF_PTP_CONTROL;
820 else
821 msgtype = data + offset;
539e44d2
SS		 822 if (rxts->msgtype != (*msgtype & 0xf))
823 return 0;
63502b8d
SS		 824
825 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
539e44d2
SS		 826 if (rxts->seqid != ntohs(*seqid))
827 return 0;
828
829 hash = ether_crc(DP83640_PACKET_HASH_LEN,
830 data + offset + DP83640_PACKET_HASH_OFFSET) >> 20;
831 if (rxts->hash != hash)
832 return 0;
63502b8d 833
539e44d2 834 return 1;
63502b8d
SS		 835}
836
cb646e2b
RC		 837static void decode_rxts(struct dp83640_private *dp83640,
838 struct phy_rxts *phy_rxts)
839{
840 struct rxts *rxts;
63502b8d
SS		 841 struct skb_shared_hwtstamps *shhwtstamps = NULL;
842 struct sk_buff *skb;
cb646e2b 843 unsigned long flags;
81e8f2e9
MR		 844 u8 overflow;
845
846 overflow = (phy_rxts->ns_hi >> 14) & 0x3;
847 if (overflow)
848 pr_debug("rx timestamp queue overflow, count %d\n", overflow);
cb646e2b
RC		 849
850 spin_lock_irqsave(&dp83640->rx_lock, flags);
851
852 prune_rx_ts(dp83640);
853
854 if (list_empty(&dp83640->rxpool)) {
8d242488 855 pr_debug("rx timestamp pool is empty\n");
cb646e2b
RC		 856 goto out;
857 }
858 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
859 list_del_init(&rxts->list);
860 phy2rxts(phy_rxts, rxts);
63502b8d 861
adbe088f 862 spin_lock(&dp83640->rx_queue.lock);
63502b8d
SS		 863 skb_queue_walk(&dp83640->rx_queue, skb) {
864 struct dp83640_skb_info *skb_info;
865
866 skb_info = (struct dp83640_skb_info *)skb->cb;
867 if (match(skb, skb_info->ptp_type, rxts)) {
868 __skb_unlink(skb, &dp83640->rx_queue);
869 shhwtstamps = skb_hwtstamps(skb);
870 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
871 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
63502b8d
SS		 872 list_add(&rxts->list, &dp83640->rxpool);
873 break;
874 }
875 }
adbe088f 876 spin_unlock(&dp83640->rx_queue.lock);
63502b8d
SS		 877
878 if (!shhwtstamps)
879 list_add_tail(&rxts->list, &dp83640->rxts);
cb646e2b
RC		 880out:
881 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
d36b82bc
SS		 882
883 if (shhwtstamps)
884 netif_rx_ni(skb);
cb646e2b
RC		 885}
886
887static void decode_txts(struct dp83640_private *dp83640,
888 struct phy_txts *phy_txts)
889{
890 struct skb_shared_hwtstamps shhwtstamps;
53bc8d2a 891 struct dp83640_skb_info *skb_info;
cb646e2b 892 struct sk_buff *skb;
81e8f2e9 893 u8 overflow;
53bc8d2a 894 u64 ns;
cb646e2b
RC		 895
896 /* We must already have the skb that triggered this. */
53bc8d2a 897again:
cb646e2b 898 skb = skb_dequeue(&dp83640->tx_queue);
cb646e2b 899 if (!skb) {
8d242488 900 pr_debug("have timestamp but tx_queue empty\n");
cb646e2b
RC		 901 return;
902 }
81e8f2e9
MR		 903
904 overflow = (phy_txts->ns_hi >> 14) & 0x3;
905 if (overflow) {
906 pr_debug("tx timestamp queue overflow, count %d\n", overflow);
907 while (skb) {
db9d8b29 908 kfree_skb(skb);
81e8f2e9
MR		 909 skb = skb_dequeue(&dp83640->tx_queue);
910 }
911 return;
912 }
53bc8d2a
SAS		 913 skb_info = (struct dp83640_skb_info *)skb->cb;
914 if (time_after(jiffies, skb_info->tmo)) {
915 kfree_skb(skb);
916 goto again;
917 }
81e8f2e9 918
cb646e2b
RC		 919 ns = phy2txts(phy_txts);
920 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
921 shhwtstamps.hwtstamp = ns_to_ktime(ns);
922 skb_complete_tx_timestamp(skb, &shhwtstamps);
923}
924
925static void decode_status_frame(struct dp83640_private *dp83640,
926 struct sk_buff *skb)
927{
928 struct phy_rxts *phy_rxts;
929 struct phy_txts *phy_txts;
930 u8 *ptr;
931 int len, size;
932 u16 ests, type;
933
934 ptr = skb->data + 2;
935
936 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
937
938 type = *(u16 *)ptr;
939 ests = type & 0x0fff;
940 type = type & 0xf000;
941 len -= sizeof(type);
942 ptr += sizeof(type);
943
944 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
945
946 phy_rxts = (struct phy_rxts *) ptr;
947 decode_rxts(dp83640, phy_rxts);
948 size = sizeof(*phy_rxts);
949
950 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
951
952 phy_txts = (struct phy_txts *) ptr;
953 decode_txts(dp83640, phy_txts);
954 size = sizeof(*phy_txts);
955
13322f2e 956 } else if (PSF_EVNT == type) {
cb646e2b 957
13322f2e 958 size = decode_evnt(dp83640, ptr, len, ests);
cb646e2b
RC		 959
960 } else {
961 size = 0;
962 break;
963 }
964 ptr += size;
965 }
966}
967
dccaa9e0
RC		 968static int is_sync(struct sk_buff *skb, int type)
969{
970 u8 *data = skb->data, *msgtype;
971 unsigned int offset = 0;
972
ae5c6c6d
SS		 973 if (type & PTP_CLASS_VLAN)
974 offset += VLAN_HLEN;
975
976 switch (type & PTP_CLASS_PMASK) {
977 case PTP_CLASS_IPV4:
cca04b28 978 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
dccaa9e0 979 break;
ae5c6c6d
SS		 980 case PTP_CLASS_IPV6:
981 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
dccaa9e0 982 break;
ae5c6c6d
SS		 983 case PTP_CLASS_L2:
984 offset += ETH_HLEN;
dccaa9e0
RC		 985 break;
986 default:
987 return 0;
988 }
989
990 if (type & PTP_CLASS_V1)
991 offset += OFF_PTP_CONTROL;
992
993 if (skb->len < offset + 1)
994 return 0;
995
996 msgtype = data + offset;
997
998 return (*msgtype & 0xf) == 0;
999}
1000
cb646e2b
RC		 1001static void dp83640_free_clocks(void)
1002{
1003 struct dp83640_clock *clock;
1004 struct list_head *this, *next;
1005
1006 mutex_lock(&phyter_clocks_lock);
1007
1008 list_for_each_safe(this, next, &phyter_clocks) {
1009 clock = list_entry(this, struct dp83640_clock, list);
1010 if (!list_empty(&clock->phylist)) {
8d242488 1011 pr_warn("phy list non-empty while unloading\n");
cb646e2b
RC		 1012 BUG();
1013 }
1014 list_del(&clock->list);
1015 mutex_destroy(&clock->extreg_lock);
1016 mutex_destroy(&clock->clock_lock);
1017 put_device(&clock->bus->dev);
86dd3612 1018 kfree(clock->caps.pin_config);
cb646e2b
RC		 1019 kfree(clock);
1020 }
1021
1022 mutex_unlock(&phyter_clocks_lock);
1023}
1024
1025static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
1026{
1027 INIT_LIST_HEAD(&clock->list);
1028 clock->bus = bus;
1029 mutex_init(&clock->extreg_lock);
1030 mutex_init(&clock->clock_lock);
1031 INIT_LIST_HEAD(&clock->phylist);
1032 clock->caps.owner = THIS_MODULE;
1033 sprintf(clock->caps.name, "dp83640 timer");
1034 clock->caps.max_adj = 1953124;
1035 clock->caps.n_alarm = 0;
1036 clock->caps.n_ext_ts = N_EXT_TS;
ad01577a 1037 clock->caps.n_per_out = N_PER_OUT;
86dd3612 1038 clock->caps.n_pins = DP83640_N_PINS;
cb646e2b 1039 clock->caps.pps = 0;
e4788b80 1040 clock->caps.adjfine = ptp_dp83640_adjfine;
cb646e2b 1041 clock->caps.adjtime = ptp_dp83640_adjtime;
41c2c18f
RC		 1042 clock->caps.gettime64 = ptp_dp83640_gettime;
1043 clock->caps.settime64 = ptp_dp83640_settime;
cb646e2b 1044 clock->caps.enable = ptp_dp83640_enable;
86dd3612
RC		 1045 clock->caps.verify = ptp_dp83640_verify;
1046 /*
1047 * Convert the module param defaults into a dynamic pin configuration.
1048 */
1049 dp83640_gpio_defaults(clock->caps.pin_config);
cb646e2b
RC		 1050 /*
1051 * Get a reference to this bus instance.
1052 */
1053 get_device(&bus->dev);
1054}
1055
1056static int choose_this_phy(struct dp83640_clock *clock,
1057 struct phy_device *phydev)
1058{
1059 if (chosen_phy == -1 && !clock->chosen)
1060 return 1;
1061
e5a03bfd 1062 if (chosen_phy == phydev->mdio.addr)
cb646e2b
RC		 1063 return 1;
1064
1065 return 0;
1066}
1067
1068static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
1069{
1070 if (clock)
1071 mutex_lock(&clock->clock_lock);
1072 return clock;
1073}
1074
1075/*
1076 * Look up and lock a clock by bus instance.
1077 * If there is no clock for this bus, then create it first.
1078 */
1079static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
1080{
1081 struct dp83640_clock *clock = NULL, *tmp;
1082 struct list_head *this;
1083
1084 mutex_lock(&phyter_clocks_lock);
1085
1086 list_for_each(this, &phyter_clocks) {
1087 tmp = list_entry(this, struct dp83640_clock, list);
1088 if (tmp->bus == bus) {
1089 clock = tmp;
1090 break;
1091 }
1092 }
1093 if (clock)
1094 goto out;
1095
1096 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1097 if (!clock)
1098 goto out;
1099
6396bb22
KC		 1100 clock->caps.pin_config = kcalloc(DP83640_N_PINS,
1101 sizeof(struct ptp_pin_desc),
1102 GFP_KERNEL);
86dd3612
RC		 1103 if (!clock->caps.pin_config) {
1104 kfree(clock);
1105 clock = NULL;
1106 goto out;
1107 }
cb646e2b
RC		 1108 dp83640_clock_init(clock, bus);
1109 list_add_tail(&phyter_clocks, &clock->list);
1110out:
1111 mutex_unlock(&phyter_clocks_lock);
1112
1113 return dp83640_clock_get(clock);
1114}
1115
1116static void dp83640_clock_put(struct dp83640_clock *clock)
1117{
1118 mutex_unlock(&clock->clock_lock);
1119}
1120
1121static int dp83640_probe(struct phy_device *phydev)
1122{
1123 struct dp83640_clock *clock;
1124 struct dp83640_private *dp83640;
1125 int err = -ENOMEM, i;
1126
e5a03bfd 1127 if (phydev->mdio.addr == BROADCAST_ADDR)
cb646e2b
RC		 1128 return 0;
1129
e5a03bfd 1130 clock = dp83640_clock_get_bus(phydev->mdio.bus);
cb646e2b
RC		 1131 if (!clock)
1132 goto no_clock;
1133
1134 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
1135 if (!dp83640)
1136 goto no_memory;
1137
1138 dp83640->phydev = phydev;
4b063258 1139 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);
cb646e2b
RC		 1140
1141 INIT_LIST_HEAD(&dp83640->rxts);
1142 INIT_LIST_HEAD(&dp83640->rxpool);
1143 for (i = 0; i < MAX_RXTS; i++)
1144 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1145
1146 phydev->priv = dp83640;
1147
1148 spin_lock_init(&dp83640->rx_lock);
1149 skb_queue_head_init(&dp83640->rx_queue);
1150 skb_queue_head_init(&dp83640->tx_queue);
1151
1152 dp83640->clock = clock;
1153
1154 if (choose_this_phy(clock, phydev)) {
1155 clock->chosen = dp83640;
e5a03bfd
AL		 1156 clock->ptp_clock = ptp_clock_register(&clock->caps,
1157 &phydev->mdio.dev);
cb646e2b
RC		 1158 if (IS_ERR(clock->ptp_clock)) {
1159 err = PTR_ERR(clock->ptp_clock);
1160 goto no_register;
1161 }
1162 } else
1163 list_add_tail(&dp83640->list, &clock->phylist);
1164
cb646e2b
RC		 1165 dp83640_clock_put(clock);
1166 return 0;
1167
1168no_register:
1169 clock->chosen = NULL;
1170 kfree(dp83640);
1171no_memory:
1172 dp83640_clock_put(clock);
1173no_clock:
1174 return err;
1175}
1176
1177static void dp83640_remove(struct phy_device *phydev)
1178{
1179 struct dp83640_clock *clock;
1180 struct list_head *this, *next;
1181 struct dp83640_private *tmp, *dp83640 = phydev->priv;
1182
e5a03bfd 1183 if (phydev->mdio.addr == BROADCAST_ADDR)
cb646e2b
RC		 1184 return;
1185
1186 enable_status_frames(phydev, false);
4b063258 1187 cancel_delayed_work_sync(&dp83640->ts_work);
cb646e2b 1188
db91b724
AD		 1189 skb_queue_purge(&dp83640->rx_queue);
1190 skb_queue_purge(&dp83640->tx_queue);
8b3408f8 1191
cb646e2b
RC		 1192 clock = dp83640_clock_get(dp83640->clock);
1193
1194 if (dp83640 == clock->chosen) {
1195 ptp_clock_unregister(clock->ptp_clock);
1196 clock->chosen = NULL;
1197 } else {
1198 list_for_each_safe(this, next, &clock->phylist) {
1199 tmp = list_entry(this, struct dp83640_private, list);
1200 if (tmp == dp83640) {
1201 list_del_init(&tmp->list);
1202 break;
1203 }
1204 }
1205 }
1206
1207 dp83640_clock_put(clock);
1208 kfree(dp83640);
1209}
1210
76327a35
EH		 1211static int dp83640_soft_reset(struct phy_device *phydev)
1212{
1213 int ret;
1214
1215 ret = genphy_soft_reset(phydev);
1216 if (ret < 0)
1217 return ret;
1218
1219 /* From DP83640 datasheet: "Software driver code must wait 3 us
1220 * following a software reset before allowing further serial MII
1221 * operations with the DP83640."
1222 */
1223 udelay(10); /* Taking udelay inaccuracy into account */
1224
1225 return 0;
1226}
1227
62ad9684
SS		 1228static int dp83640_config_init(struct phy_device *phydev)
1229{
602b1099
SS		 1230 struct dp83640_private *dp83640 = phydev->priv;
1231 struct dp83640_clock *clock = dp83640->clock;
1232
1233 if (clock->chosen && !list_empty(&clock->phylist))
1234 recalibrate(clock);
a935865c
RC		 1235 else {
1236 mutex_lock(&clock->extreg_lock);
602b1099 1237 enable_broadcast(phydev, clock->page, 1);
a935865c
RC		 1238 mutex_unlock(&clock->extreg_lock);
1239 }
602b1099 1240
62ad9684 1241 enable_status_frames(phydev, true);
a935865c
RC		 1242
1243 mutex_lock(&clock->extreg_lock);
62ad9684 1244 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
a935865c
RC		 1245 mutex_unlock(&clock->extreg_lock);
1246
62ad9684
SS		 1247 return 0;
1248}
1249
1642182e
SG		 1250static int dp83640_ack_interrupt(struct phy_device *phydev)
1251{
1252 int err = phy_read(phydev, MII_DP83640_MISR);
1253
1254 if (err < 0)
1255 return err;
1256
1257 return 0;
1258}
1259
1260static int dp83640_config_intr(struct phy_device *phydev)
1261{
1262 int micr;
1263 int misr;
1264 int err;
1265
1266 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1267 misr = phy_read(phydev, MII_DP83640_MISR);
1268 if (misr < 0)
1269 return misr;
1270 misr |=
1271 (MII_DP83640_MISR_ANC_INT_EN |
1272 MII_DP83640_MISR_DUP_INT_EN |
1273 MII_DP83640_MISR_SPD_INT_EN |
1274 MII_DP83640_MISR_LINK_INT_EN);
1275 err = phy_write(phydev, MII_DP83640_MISR, misr);
1276 if (err < 0)
1277 return err;
1278
1279 micr = phy_read(phydev, MII_DP83640_MICR);
1280 if (micr < 0)
1281 return micr;
1282 micr |=
1283 (MII_DP83640_MICR_OE |
1284 MII_DP83640_MICR_IE);
1285 return phy_write(phydev, MII_DP83640_MICR, micr);
1286 } else {
1287 micr = phy_read(phydev, MII_DP83640_MICR);
1288 if (micr < 0)
1289 return micr;
1290 micr &=
1291 ~(MII_DP83640_MICR_OE |
1292 MII_DP83640_MICR_IE);
1293 err = phy_write(phydev, MII_DP83640_MICR, micr);
1294 if (err < 0)
1295 return err;
1296
1297 misr = phy_read(phydev, MII_DP83640_MISR);
1298 if (misr < 0)
1299 return misr;
1300 misr &=
1301 ~(MII_DP83640_MISR_ANC_INT_EN |
1302 MII_DP83640_MISR_DUP_INT_EN |
1303 MII_DP83640_MISR_SPD_INT_EN |
1304 MII_DP83640_MISR_LINK_INT_EN);
1305 return phy_write(phydev, MII_DP83640_MISR, misr);
1306 }
1307}
1308
cb646e2b
RC		 1309static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
1310{
1311 struct dp83640_private *dp83640 = phydev->priv;
1312 struct hwtstamp_config cfg;
1313 u16 txcfg0, rxcfg0;
1314
1315 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1316 return -EFAULT;
1317
1318 if (cfg.flags) /* reserved for future extensions */
1319 return -EINVAL;
1320
dccaa9e0 1321 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
cb646e2b 1322 return -ERANGE;
dccaa9e0
RC		 1323
1324 dp83640->hwts_tx_en = cfg.tx_type;
cb646e2b
RC		 1325
1326 switch (cfg.rx_filter) {
1327 case HWTSTAMP_FILTER_NONE:
1328 dp83640->hwts_rx_en = 0;
1329 dp83640->layer = 0;
1330 dp83640->version = 0;
1331 break;
1332 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1333 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1334 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1335 dp83640->hwts_rx_en = 1;
a1f8723f
SS		 1336 dp83640->layer = PTP_CLASS_L4;
1337 dp83640->version = PTP_CLASS_V1;
cb646e2b
RC		 1338 break;
1339 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1340 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1341 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1342 dp83640->hwts_rx_en = 1;
a1f8723f
SS		 1343 dp83640->layer = PTP_CLASS_L4;
1344 dp83640->version = PTP_CLASS_V2;
cb646e2b
RC		 1345 break;
1346 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1347 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1348 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1349 dp83640->hwts_rx_en = 1;
a1f8723f
SS		 1350 dp83640->layer = PTP_CLASS_L2;
1351 dp83640->version = PTP_CLASS_V2;
cb646e2b
RC		 1352 break;
1353 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1354 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1355 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1356 dp83640->hwts_rx_en = 1;
a1f8723f
SS		 1357 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
1358 dp83640->version = PTP_CLASS_V2;
cb646e2b
RC		 1359 break;
1360 default:
1361 return -ERANGE;
1362 }
1363
1364 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1365 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1366
a1f8723f 1367 if (dp83640->layer & PTP_CLASS_L2) {
cb646e2b
RC		 1368 txcfg0 |= TX_L2_EN;
1369 rxcfg0 |= RX_L2_EN;
1370 }
a1f8723f 1371 if (dp83640->layer & PTP_CLASS_L4) {
cb646e2b
RC		 1372 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1373 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1374 }
1375
1376 if (dp83640->hwts_tx_en)
1377 txcfg0 |= TX_TS_EN;
1378
dccaa9e0
RC		 1379 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1380 txcfg0 |= SYNC_1STEP | CHK_1STEP;
1381
cb646e2b
RC		 1382 if (dp83640->hwts_rx_en)
1383 rxcfg0 |= RX_TS_EN;
1384
1385 mutex_lock(&dp83640->clock->extreg_lock);
1386
cb646e2b
RC		 1387 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
1388 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1389
1390 mutex_unlock(&dp83640->clock->extreg_lock);
1391
1392 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1393}
1394
1395static void rx_timestamp_work(struct work_struct *work)
1396{
1397 struct dp83640_private *dp83640 =
4b063258 1398 container_of(work, struct dp83640_private, ts_work.work);
cb646e2b 1399 struct sk_buff *skb;
cb646e2b 1400
63502b8d
SS		 1401 /* Deliver expired packets. */
1402 while ((skb = skb_dequeue(&dp83640->rx_queue))) {
1403 struct dp83640_skb_info *skb_info;
1404
1405 skb_info = (struct dp83640_skb_info *)skb->cb;
1406 if (!time_after(jiffies, skb_info->tmo)) {
1407 skb_queue_head(&dp83640->rx_queue, skb);
1408 break;
cb646e2b 1409 }
63502b8d 1410
72092cc4 1411 netif_rx_ni(skb);
cb646e2b
RC		 1412 }
1413
63502b8d 1414 if (!skb_queue_empty(&dp83640->rx_queue))
4b063258 1415 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
cb646e2b
RC		 1416}
1417
1418static bool dp83640_rxtstamp(struct phy_device *phydev,
1419 struct sk_buff *skb, int type)
1420{
1421 struct dp83640_private *dp83640 = phydev->priv;
63502b8d
SS		 1422 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1423 struct list_head *this, *next;
1424 struct rxts *rxts;
1425 struct skb_shared_hwtstamps *shhwtstamps = NULL;
1426 unsigned long flags;
cb646e2b 1427
cb646e2b
RC		 1428 if (is_status_frame(skb, type)) {
1429 decode_status_frame(dp83640, skb);
ae6e86b7
RC		 1430 kfree_skb(skb);
1431 return true;
cb646e2b
RC		 1432 }
1433
a12f78c5
SS		 1434 if (!dp83640->hwts_rx_en)
1435 return false;
1436
a1f8723f
SS		 1437 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0)
1438 return false;
1439
63502b8d 1440 spin_lock_irqsave(&dp83640->rx_lock, flags);
ccf6ee9a 1441 prune_rx_ts(dp83640);
63502b8d
SS		 1442 list_for_each_safe(this, next, &dp83640->rxts) {
1443 rxts = list_entry(this, struct rxts, list);
1444 if (match(skb, type, rxts)) {
1445 shhwtstamps = skb_hwtstamps(skb);
1446 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1447 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
63502b8d
SS		 1448 list_del_init(&rxts->list);
1449 list_add(&rxts->list, &dp83640->rxpool);
1450 break;
1451 }
1452 }
1453 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1454
1455 if (!shhwtstamps) {
1456 skb_info->ptp_type = type;
4b063258 1457 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
63502b8d 1458 skb_queue_tail(&dp83640->rx_queue, skb);
4b063258 1459 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
d36b82bc
SS		 1460 } else {
1461 netif_rx_ni(skb);
63502b8d 1462 }
cb646e2b
RC		 1463
1464 return true;
1465}
1466
1467static void dp83640_txtstamp(struct phy_device *phydev,
1468 struct sk_buff *skb, int type)
1469{
53bc8d2a 1470 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
cb646e2b
RC		 1471 struct dp83640_private *dp83640 = phydev->priv;
1472
dccaa9e0
RC		 1473 switch (dp83640->hwts_tx_en) {
1474
1475 case HWTSTAMP_TX_ONESTEP_SYNC:
1476 if (is_sync(skb, type)) {
62bccb8c 1477 kfree_skb(skb);
dccaa9e0
RC		 1478 return;
1479 }
1480 /* fall through */
1481 case HWTSTAMP_TX_ON:
e2e2f51d 1482 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
53bc8d2a 1483 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
dccaa9e0 1484 skb_queue_tail(&dp83640->tx_queue, skb);
dccaa9e0
RC		 1485 break;
1486
1487 case HWTSTAMP_TX_OFF:
1488 default:
62bccb8c 1489 kfree_skb(skb);
dccaa9e0 1490 break;
cb646e2b 1491 }
cb646e2b
RC		 1492}
1493
7dff3499
RC		 1494static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info)
1495{
1496 struct dp83640_private *dp83640 = dev->priv;
1497
1498 info->so_timestamping =
1499 SOF_TIMESTAMPING_TX_HARDWARE |
1500 SOF_TIMESTAMPING_RX_HARDWARE |
1501 SOF_TIMESTAMPING_RAW_HARDWARE;
1502 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1503 info->tx_types =
1504 (1 << HWTSTAMP_TX_OFF) |
1505 (1 << HWTSTAMP_TX_ON) |
1506 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1507 info->rx_filters =
1508 (1 << HWTSTAMP_FILTER_NONE) |
1509 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
7dff3499 1510 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
7dff3499 1511 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
11b1544b 1512 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
7dff3499
RC		 1513 return 0;
1514}
1515
cb646e2b
RC		 1516static struct phy_driver dp83640_driver = {
1517 .phy_id = DP83640_PHY_ID,
1518 .phy_id_mask = 0xfffffff0,
1519 .name = "NatSemi DP83640",
dcdecdcf 1520 /* PHY_BASIC_FEATURES */
cb646e2b
RC		 1521 .probe = dp83640_probe,
1522 .remove = dp83640_remove,
76327a35 1523 .soft_reset = dp83640_soft_reset,
62ad9684 1524 .config_init = dp83640_config_init,
1642182e
SG		 1525 .ack_interrupt = dp83640_ack_interrupt,
1526 .config_intr = dp83640_config_intr,
7dff3499 1527 .ts_info = dp83640_ts_info,
cb646e2b
RC		 1528 .hwtstamp = dp83640_hwtstamp,
1529 .rxtstamp = dp83640_rxtstamp,
1530 .txtstamp = dp83640_txtstamp,
cb646e2b
RC		 1531};
1532
1533static int __init dp83640_init(void)
1534{
be01da72 1535 return phy_driver_register(&dp83640_driver, THIS_MODULE);
cb646e2b
RC		 1536}
1537
1538static void __exit dp83640_exit(void)
1539{
1540 dp83640_free_clocks();
1541 phy_driver_unregister(&dp83640_driver);
1542}
1543
1544MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
fbf4b934 1545MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
cb646e2b
RC		 1546MODULE_LICENSE("GPL");
1547
1548module_init(dp83640_init);
1549module_exit(dp83640_exit);
1550
86ff9baa 1551static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
cb646e2b
RC		 1552 { DP83640_PHY_ID, 0xfffffff0 },
1553 { }
1554};
1555
1556MODULE_DEVICE_TABLE(mdio, dp83640_tbl);
Linux 6.x block layer and io_uring tree(s)