[linux-2.6-block.git] / drivers / net / phy / bcm87xx.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2011 - 2012 Cavium, Inc.
 */

#include <linux/module.h>
#include <linux/phy.h>
#include <linux/of.h>

#define PHY_ID_BCM8706	0x0143bdc1
#define PHY_ID_BCM8727	0x0143bff0

#define BCM87XX_PMD_RX_SIGNAL_DETECT	0x000a
#define BCM87XX_10GBASER_PCS_STATUS	0x0020
#define BCM87XX_XGXS_LANE_STATUS	0x0018

#define BCM87XX_LASI_CONTROL		0x9002
#define BCM87XX_LASI_STATUS		0x9005

#if IS_ENABLED(CONFIG_OF_MDIO)
/* Set and/or override some configuration registers based on the
 * broadcom,c45-reg-init property stored in the of_node for the phydev.
 *
 * broadcom,c45-reg-init = <devid reg mask value>,...;
 *
 * There may be one or more sets of <devid reg mask value>:
 *
 * devid: which sub-device to use.
 * reg: the register.
 * mask: if non-zero, ANDed with existing register value.
 * value: ORed with the masked value and written to the regiser.
 *
 */
static int bcm87xx_of_reg_init(struct phy_device *phydev)
{
	const __be32 *paddr;
	const __be32 *paddr_end;
	int len, ret;

	if (!phydev->mdio.dev.of_node)
		return 0;

	paddr = of_get_property(phydev->mdio.dev.of_node,
				"broadcom,c45-reg-init", &len);
	if (!paddr)
		return 0;

	paddr_end = paddr + (len /= sizeof(*paddr));

	ret = 0;

	while (paddr + 3 < paddr_end) {
		u16 devid	= be32_to_cpup(paddr++);
		u16 reg		= be32_to_cpup(paddr++);
		u16 mask	= be32_to_cpup(paddr++);
		u16 val_bits	= be32_to_cpup(paddr++);
		int val = 0;

		if (mask) {
			val = phy_read_mmd(phydev, devid, reg);
			if (val < 0) {
				ret = val;
				goto err;
			}
			val &= mask;
		}
		val |= val_bits;

		ret = phy_write_mmd(phydev, devid, reg, val);
		if (ret < 0)
			goto err;
	}
err:
	return ret;
}
#else
static int bcm87xx_of_reg_init(struct phy_device *phydev)
{
	return 0;
}
#endif /* CONFIG_OF_MDIO */

static int bcm87xx_get_features(struct phy_device *phydev)
{
	linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
			 phydev->supported);
	return 0;
}

static int bcm87xx_config_init(struct phy_device *phydev)
{
	return bcm87xx_of_reg_init(phydev);
}

static int bcm87xx_config_aneg(struct phy_device *phydev)
{
	return -EINVAL;
}

static int bcm87xx_read_status(struct phy_device *phydev)
{
	int rx_signal_detect;
	int pcs_status;
	int xgxs_lane_status;

	rx_signal_detect = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
					BCM87XX_PMD_RX_SIGNAL_DETECT);
	if (rx_signal_detect < 0)
		return rx_signal_detect;

	if ((rx_signal_detect & 1) == 0)
		goto no_link;

	pcs_status = phy_read_mmd(phydev, MDIO_MMD_PCS,
				  BCM87XX_10GBASER_PCS_STATUS);
	if (pcs_status < 0)
		return pcs_status;

	if ((pcs_status & 1) == 0)
		goto no_link;

	xgxs_lane_status = phy_read_mmd(phydev, MDIO_MMD_PHYXS,
					BCM87XX_XGXS_LANE_STATUS);
	if (xgxs_lane_status < 0)
		return xgxs_lane_status;

	if ((xgxs_lane_status & 0x1000) == 0)
		goto no_link;

	phydev->speed = 10000;
	phydev->link = 1;
	phydev->duplex = 1;
	return 0;

no_link:
	phydev->link = 0;
	return 0;
}

static int bcm87xx_config_intr(struct phy_device *phydev)
{
	int reg, err;

	reg = phy_read_mmd(phydev, MDIO_MMD_PCS, BCM87XX_LASI_CONTROL);

	if (reg < 0)
		return reg;

	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
		err = phy_read_mmd(phydev, MDIO_MMD_PCS, BCM87XX_LASI_STATUS);
		if (err)
			return err;

		reg |= 1;
		err = phy_write_mmd(phydev, MDIO_MMD_PCS,
				    BCM87XX_LASI_CONTROL, reg);
	} else {
		reg &= ~1;
		err = phy_write_mmd(phydev, MDIO_MMD_PCS,
				    BCM87XX_LASI_CONTROL, reg);
		if (err)
			return err;

		err = phy_read_mmd(phydev, MDIO_MMD_PCS, BCM87XX_LASI_STATUS);
	}

	return err;
}

static irqreturn_t bcm87xx_handle_interrupt(struct phy_device *phydev)
{
	int irq_status;

	irq_status = phy_read(phydev, BCM87XX_LASI_STATUS);
	if (irq_status < 0) {
		phy_error(phydev);
		return IRQ_NONE;
	}

	if (irq_status == 0)
		return IRQ_NONE;

	phy_trigger_machine(phydev);

	return IRQ_HANDLED;
}

static int bcm8706_match_phy_device(struct phy_device *phydev)
{
	return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8706;
}

static int bcm8727_match_phy_device(struct phy_device *phydev)
{
	return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8727;
}

static struct phy_driver bcm87xx_driver[] = {
{
	.phy_id		= PHY_ID_BCM8706,
	.phy_id_mask	= 0xffffffff,
	.name		= "Broadcom BCM8706",
	.get_features	= bcm87xx_get_features,
	.config_init	= bcm87xx_config_init,
	.config_aneg	= bcm87xx_config_aneg,
	.read_status	= bcm87xx_read_status,
	.config_intr	= bcm87xx_config_intr,
	.handle_interrupt = bcm87xx_handle_interrupt,
	.match_phy_device = bcm8706_match_phy_device,
}, {
	.phy_id		= PHY_ID_BCM8727,
	.phy_id_mask	= 0xffffffff,
	.name		= "Broadcom BCM8727",
	.get_features	= bcm87xx_get_features,
	.config_init	= bcm87xx_config_init,
	.config_aneg	= bcm87xx_config_aneg,
	.read_status	= bcm87xx_read_status,
	.config_intr	= bcm87xx_config_intr,
	.handle_interrupt = bcm87xx_handle_interrupt,
	.match_phy_device = bcm8727_match_phy_device,
} };

module_phy_driver(bcm87xx_driver);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Broadcom BCM87xx PHY driver");
Commit	Line	Data
8bbe833a	1	// SPDX-License-Identifier: GPL-2.0
e9976d7c	2	/*
e9976d7c DD	3	* Copyright (C) 2011 - 2012 Cavium, Inc.
	4	*/
	5
	6	#include <linux/module.h>
	7	#include <linux/phy.h>
	8	#include <linux/of.h>
	9
	10	#define PHY_ID_BCM8706 0x0143bdc1
	11	#define PHY_ID_BCM8727 0x0143bff0
	12
cad75717 AL	13	#define BCM87XX_PMD_RX_SIGNAL_DETECT 0x000a
	14	#define BCM87XX_10GBASER_PCS_STATUS 0x0020
	15	#define BCM87XX_XGXS_LANE_STATUS 0x0018
e9976d7c	16
cad75717 AL	17	#define BCM87XX_LASI_CONTROL 0x9002
cad75717 AL	18	#define BCM87XX_LASI_STATUS 0x9005
e9976d7c DD	19
	20	#if IS_ENABLED(CONFIG_OF_MDIO)
	21	/* Set and/or override some configuration registers based on the
806a0fbe	22	* broadcom,c45-reg-init property stored in the of_node for the phydev.
e9976d7c DD	23	*
	24	* broadcom,c45-reg-init = <devid reg mask value>,...;
	25	*
	26	* There may be one or more sets of <devid reg mask value>:
	27	*
	28	* devid: which sub-device to use.
	29	* reg: the register.
	30	* mask: if non-zero, ANDed with existing register value.
	31	* value: ORed with the masked value and written to the regiser.
	32	*
	33	*/
	34	static int bcm87xx_of_reg_init(struct phy_device *phydev)
	35	{
	36	const __be32 *paddr;
	37	const __be32 *paddr_end;
	38	int len, ret;
	39
e5a03bfd	40	if (!phydev->mdio.dev.of_node)
e9976d7c DD	41	return 0;
e9976d7c DD	42
e5a03bfd	43	paddr = of_get_property(phydev->mdio.dev.of_node,
e9976d7c DD	44	"broadcom,c45-reg-init", &len);
	45	if (!paddr)
	46	return 0;
	47
	48	paddr_end = paddr + (len /= sizeof(*paddr));
	49
	50	ret = 0;
	51
	52	while (paddr + 3 < paddr_end) {
	53	u16 devid = be32_to_cpup(paddr++);
	54	u16 reg = be32_to_cpup(paddr++);
	55	u16 mask = be32_to_cpup(paddr++);
	56	u16 val_bits = be32_to_cpup(paddr++);
775f2547 WL	57	int val = 0;
775f2547 WL	58
e9976d7c	59	if (mask) {
cad75717	60	val = phy_read_mmd(phydev, devid, reg);
e9976d7c DD	61	if (val < 0) {
	62	ret = val;
	63	goto err;
	64	}
	65	val &= mask;
	66	}
	67	val \|= val_bits;
	68
cad75717	69	ret = phy_write_mmd(phydev, devid, reg, val);
e9976d7c DD	70	if (ret < 0)
	71	goto err;
	72	}
	73	err:
	74	return ret;
	75	}
	76	#else
	77	static int bcm87xx_of_reg_init(struct phy_device *phydev)
	78	{
	79	return 0;
	80	}
	81	#endif /* CONFIG_OF_MDIO */
	82
476cc6c9	83	static int bcm87xx_get_features(struct phy_device *phydev)
e9976d7c	84	{
3c1bcc86 AL	85	linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
3c1bcc86 AL	86	phydev->supported);
e9976d7c DD	87	return 0;
	88	}
	89
476cc6c9 HK	90	static int bcm87xx_config_init(struct phy_device *phydev)
	91	{
	92	return bcm87xx_of_reg_init(phydev);
	93	}
	94
e9976d7c DD	95	static int bcm87xx_config_aneg(struct phy_device *phydev)
	96	{
	97	return -EINVAL;
	98	}
	99
	100	static int bcm87xx_read_status(struct phy_device *phydev)
	101	{
	102	int rx_signal_detect;
	103	int pcs_status;
	104	int xgxs_lane_status;
	105
cad75717 AL	106	rx_signal_detect = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
cad75717 AL	107	BCM87XX_PMD_RX_SIGNAL_DETECT);
e9976d7c DD	108	if (rx_signal_detect < 0)
	109	return rx_signal_detect;
	110
	111	if ((rx_signal_detect & 1) == 0)
	112	goto no_link;
	113
cad75717 AL	114	pcs_status = phy_read_mmd(phydev, MDIO_MMD_PCS,
cad75717 AL	115	BCM87XX_10GBASER_PCS_STATUS);
e9976d7c DD	116	if (pcs_status < 0)
	117	return pcs_status;
	118
	119	if ((pcs_status & 1) == 0)
	120	goto no_link;
	121
cad75717 AL	122	xgxs_lane_status = phy_read_mmd(phydev, MDIO_MMD_PHYXS,
cad75717 AL	123	BCM87XX_XGXS_LANE_STATUS);
e9976d7c DD	124	if (xgxs_lane_status < 0)
	125	return xgxs_lane_status;
	126
	127	if ((xgxs_lane_status & 0x1000) == 0)
	128	goto no_link;
	129
	130	phydev->speed = 10000;
	131	phydev->link = 1;
	132	phydev->duplex = 1;
	133	return 0;
	134
	135	no_link:
	136	phydev->link = 0;
	137	return 0;
	138	}
	139
	140	static int bcm87xx_config_intr(struct phy_device *phydev)
	141	{
	142	int reg, err;
	143
cad75717	144	reg = phy_read_mmd(phydev, MDIO_MMD_PCS, BCM87XX_LASI_CONTROL);
e9976d7c DD	145
	146	if (reg < 0)
	147	return reg;
	148
15772e4d	149	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
cad75717	150	err = phy_read_mmd(phydev, MDIO_MMD_PCS, BCM87XX_LASI_STATUS);
15772e4d IC	151	if (err)
	152	return err;
	153
e9976d7c	154	reg \|= 1;
cad75717 AL	155	err = phy_write_mmd(phydev, MDIO_MMD_PCS,
cad75717 AL	156	BCM87XX_LASI_CONTROL, reg);
15772e4d	157	} else {
e9976d7c	158	reg &= ~1;
cad75717 AL	159	err = phy_write_mmd(phydev, MDIO_MMD_PCS,
cad75717 AL	160	BCM87XX_LASI_CONTROL, reg);
15772e4d IC	161	if (err)
	162	return err;
	163
cad75717	164	err = phy_read_mmd(phydev, MDIO_MMD_PCS, BCM87XX_LASI_STATUS);
15772e4d	165	}
e9976d7c	166
e9976d7c DD	167	return err;
	168	}
	169
4567d5c3 IC	170	static irqreturn_t bcm87xx_handle_interrupt(struct phy_device *phydev)
	171	{
	172	int irq_status;
	173
	174	irq_status = phy_read(phydev, BCM87XX_LASI_STATUS);
	175	if (irq_status < 0) {
	176	phy_error(phydev);
	177	return IRQ_NONE;
	178	}
	179
	180	if (irq_status == 0)
	181	return IRQ_NONE;
	182
	183	phy_trigger_machine(phydev);
	184
	185	return IRQ_HANDLED;
	186	}
	187
e9976d7c DD	188	static int bcm8706_match_phy_device(struct phy_device *phydev)
	189	{
	190	return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8706;
	191	}
	192
	193	static int bcm8727_match_phy_device(struct phy_device *phydev)
	194	{
	195	return phydev->c45_ids.device_ids[4] == PHY_ID_BCM8727;
	196	}
	197
d5bf9071 CH	198	static struct phy_driver bcm87xx_driver[] = {
d5bf9071 CH	199	{
e9976d7c DD	200	.phy_id = PHY_ID_BCM8706,
	201	.phy_id_mask = 0xffffffff,
	202	.name = "Broadcom BCM8706",
476cc6c9	203	.get_features = bcm87xx_get_features,
e9976d7c DD	204	.config_init = bcm87xx_config_init,
	205	.config_aneg = bcm87xx_config_aneg,
	206	.read_status = bcm87xx_read_status,
e9976d7c	207	.config_intr = bcm87xx_config_intr,
4567d5c3	208	.handle_interrupt = bcm87xx_handle_interrupt,
e9976d7c	209	.match_phy_device = bcm8706_match_phy_device,
d5bf9071	210	}, {
e9976d7c DD	211	.phy_id = PHY_ID_BCM8727,
	212	.phy_id_mask = 0xffffffff,
	213	.name = "Broadcom BCM8727",
476cc6c9	214	.get_features = bcm87xx_get_features,
e9976d7c DD	215	.config_init = bcm87xx_config_init,
	216	.config_aneg = bcm87xx_config_aneg,
	217	.read_status = bcm87xx_read_status,
e9976d7c	218	.config_intr = bcm87xx_config_intr,
4567d5c3	219	.handle_interrupt = bcm87xx_handle_interrupt,
e9976d7c	220	.match_phy_device = bcm8727_match_phy_device,
d5bf9071	221	} };
e9976d7c	222
50fd7150	223	module_phy_driver(bcm87xx_driver);
9913b8c8	224
8bbe833a	225	MODULE_LICENSE("GPL v2");
dd9d75fc	226	MODULE_DESCRIPTION("Broadcom BCM87xx PHY driver");