Commit | Line | Data |
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a2443fd1 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
09bb9aa0 MB |
2 | /* |
3 | * Driver for Broadcom 63xx SOCs integrated PHYs | |
09bb9aa0 | 4 | */ |
a1cba561 | 5 | #include "bcm-phy-lib.h" |
09bb9aa0 MB |
6 | #include <linux/module.h> |
7 | #include <linux/phy.h> | |
8 | ||
9 | #define MII_BCM63XX_IR 0x1a /* interrupt register */ | |
10 | #define MII_BCM63XX_IR_EN 0x4000 /* global interrupt enable */ | |
11 | #define MII_BCM63XX_IR_DUPLEX 0x0800 /* duplex changed */ | |
12 | #define MII_BCM63XX_IR_SPEED 0x0400 /* speed changed */ | |
13 | #define MII_BCM63XX_IR_LINK 0x0200 /* link changed */ | |
14 | #define MII_BCM63XX_IR_GMASK 0x0100 /* global interrupt mask */ | |
15 | ||
16 | MODULE_DESCRIPTION("Broadcom 63xx internal PHY driver"); | |
17 | MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>"); | |
18 | MODULE_LICENSE("GPL"); | |
19 | ||
cd33b3e0 DGC |
20 | static int bcm63xx_config_intr(struct phy_device *phydev) |
21 | { | |
22 | int reg, err; | |
23 | ||
24 | reg = phy_read(phydev, MII_BCM63XX_IR); | |
25 | if (reg < 0) | |
26 | return reg; | |
27 | ||
15772e4d IC |
28 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { |
29 | err = bcm_phy_ack_intr(phydev); | |
30 | if (err) | |
31 | return err; | |
32 | ||
cd33b3e0 | 33 | reg &= ~MII_BCM63XX_IR_GMASK; |
15772e4d IC |
34 | err = phy_write(phydev, MII_BCM63XX_IR, reg); |
35 | } else { | |
cd33b3e0 | 36 | reg |= MII_BCM63XX_IR_GMASK; |
15772e4d IC |
37 | err = phy_write(phydev, MII_BCM63XX_IR, reg); |
38 | if (err) | |
39 | return err; | |
40 | ||
41 | err = bcm_phy_ack_intr(phydev); | |
42 | } | |
cd33b3e0 | 43 | |
cd33b3e0 DGC |
44 | return err; |
45 | } | |
46 | ||
09bb9aa0 MB |
47 | static int bcm63xx_config_init(struct phy_device *phydev) |
48 | { | |
49 | int reg, err; | |
50 | ||
719655a1 | 51 | /* ASYM_PAUSE bit is marked RO in datasheet, so don't cheat */ |
3c1bcc86 | 52 | linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported); |
719655a1 | 53 | |
09bb9aa0 MB |
54 | reg = phy_read(phydev, MII_BCM63XX_IR); |
55 | if (reg < 0) | |
56 | return reg; | |
57 | ||
58 | /* Mask interrupts globally. */ | |
59 | reg |= MII_BCM63XX_IR_GMASK; | |
60 | err = phy_write(phydev, MII_BCM63XX_IR, reg); | |
61 | if (err < 0) | |
62 | return err; | |
63 | ||
64 | /* Unmask events we are interested in */ | |
65 | reg = ~(MII_BCM63XX_IR_DUPLEX | | |
66 | MII_BCM63XX_IR_SPEED | | |
67 | MII_BCM63XX_IR_LINK) | | |
68 | MII_BCM63XX_IR_EN; | |
a25cc43e | 69 | return phy_write(phydev, MII_BCM63XX_IR, reg); |
09bb9aa0 MB |
70 | } |
71 | ||
d5bf9071 CH |
72 | static struct phy_driver bcm63xx_driver[] = { |
73 | { | |
09bb9aa0 MB |
74 | .phy_id = 0x00406000, |
75 | .phy_id_mask = 0xfffffc00, | |
76 | .name = "Broadcom BCM63XX (1)", | |
dcdecdcf | 77 | /* PHY_BASIC_FEATURES */ |
a4307c0e | 78 | .flags = PHY_IS_INTERNAL, |
09bb9aa0 | 79 | .config_init = bcm63xx_config_init, |
cd33b3e0 | 80 | .config_intr = bcm63xx_config_intr, |
4567d5c3 | 81 | .handle_interrupt = bcm_phy_handle_interrupt, |
d5bf9071 CH |
82 | }, { |
83 | /* same phy as above, with just a different OUI */ | |
09bb9aa0 MB |
84 | .phy_id = 0x002bdc00, |
85 | .phy_id_mask = 0xfffffc00, | |
43de81b0 | 86 | .name = "Broadcom BCM63XX (2)", |
dcdecdcf | 87 | /* PHY_BASIC_FEATURES */ |
a4307c0e | 88 | .flags = PHY_IS_INTERNAL, |
09bb9aa0 | 89 | .config_init = bcm63xx_config_init, |
cd33b3e0 | 90 | .config_intr = bcm63xx_config_intr, |
4567d5c3 | 91 | .handle_interrupt = bcm_phy_handle_interrupt, |
d5bf9071 | 92 | } }; |
09bb9aa0 | 93 | |
50fd7150 | 94 | module_phy_driver(bcm63xx_driver); |
4e4f10f6 | 95 | |
b01b59a4 | 96 | static const struct mdio_device_id __maybe_unused bcm63xx_tbl[] = { |
4e4f10f6 DW |
97 | { 0x00406000, 0xfffffc00 }, |
98 | { 0x002bdc00, 0xfffffc00 }, | |
99 | { } | |
100 | }; | |
101 | ||
0de8655a | 102 | MODULE_DEVICE_TABLE(mdio, bcm63xx_tbl); |