projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| a2443fd1 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 09bb9aa0 MB |
2 | /* |
| 3 | * Driver for Broadcom 63xx SOCs integrated PHYs | |
| 09bb9aa0 | 4 | */ |
| a1cba561 | 5 | #include "bcm-phy-lib.h" |
| 09bb9aa0 MB |
6 | #include <linux/module.h> |
| 7 | #include <linux/phy.h> | |
| 8 | ||
| 9 | #define MII_BCM63XX_IR 0x1a /* interrupt register */ | |
| 10 | #define MII_BCM63XX_IR_EN 0x4000 /* global interrupt enable */ | |
| 11 | #define MII_BCM63XX_IR_DUPLEX 0x0800 /* duplex changed */ | |
| 12 | #define MII_BCM63XX_IR_SPEED 0x0400 /* speed changed */ | |
| 13 | #define MII_BCM63XX_IR_LINK 0x0200 /* link changed */ | |
| 14 | #define MII_BCM63XX_IR_GMASK 0x0100 /* global interrupt mask */ | |
| 15 | ||
| 16 | MODULE_DESCRIPTION("Broadcom 63xx internal PHY driver"); | |
| 17 | MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>"); | |
| 18 | MODULE_LICENSE("GPL"); | |
| 19 | ||
| cd33b3e0 DGC |
20 | static int bcm63xx_config_intr(struct phy_device *phydev) |
| 21 | { | |
| 22 | int reg, err; | |
| 23 | ||
| 24 | reg = phy_read(phydev, MII_BCM63XX_IR); | |
| 25 | if (reg < 0) | |
| 26 | return reg; | |
| 27 | ||
| 28 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) | |
| 29 | reg &= ~MII_BCM63XX_IR_GMASK; | |
| 30 | else | |
| 31 | reg |= MII_BCM63XX_IR_GMASK; | |
| 32 | ||
| 33 | err = phy_write(phydev, MII_BCM63XX_IR, reg); | |
| 34 | return err; | |
| 35 | } | |
| 36 | ||
| 09bb9aa0 MB |
37 | static int bcm63xx_config_init(struct phy_device *phydev) |
| 38 | { | |
| 39 | int reg, err; | |
| 40 | ||
| 719655a1 | 41 | /* ASYM_PAUSE bit is marked RO in datasheet, so don't cheat */ |
| 3c1bcc86 | 42 | linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported); |
| 719655a1 | 43 | |
| 09bb9aa0 MB |
44 | reg = phy_read(phydev, MII_BCM63XX_IR); |
| 45 | if (reg < 0) | |
| 46 | return reg; | |
| 47 | ||
| 48 | /* Mask interrupts globally. */ | |
| 49 | reg |= MII_BCM63XX_IR_GMASK; | |
| 50 | err = phy_write(phydev, MII_BCM63XX_IR, reg); | |
| 51 | if (err < 0) | |
| 52 | return err; | |
| 53 | ||
| 54 | /* Unmask events we are interested in */ | |
| 55 | reg = ~(MII_BCM63XX_IR_DUPLEX | | |
| 56 | MII_BCM63XX_IR_SPEED | | |
| 57 | MII_BCM63XX_IR_LINK) | | |
| 58 | MII_BCM63XX_IR_EN; | |
| a25cc43e | 59 | return phy_write(phydev, MII_BCM63XX_IR, reg); |
| 09bb9aa0 MB |
60 | } |
| 61 | ||
| d5bf9071 CH |
62 | static struct phy_driver bcm63xx_driver[] = { |
| 63 | { | |
| 09bb9aa0 MB |
64 | .phy_id = 0x00406000, |
| 65 | .phy_id_mask = 0xfffffc00, | |
| 66 | .name = "Broadcom BCM63XX (1)", | |
| dcdecdcf | 67 | /* PHY_BASIC_FEATURES */ |
| a4307c0e | 68 | .flags = PHY_IS_INTERNAL, |
| 09bb9aa0 | 69 | .config_init = bcm63xx_config_init, |
| a1cba561 | 70 | .ack_interrupt = bcm_phy_ack_intr, |
| cd33b3e0 | 71 | .config_intr = bcm63xx_config_intr, |
| d5bf9071 CH |
72 | }, { |
| 73 | /* same phy as above, with just a different OUI */ | |
| 09bb9aa0 MB |
74 | .phy_id = 0x002bdc00, |
| 75 | .phy_id_mask = 0xfffffc00, | |
| 43de81b0 | 76 | .name = "Broadcom BCM63XX (2)", |
| dcdecdcf | 77 | /* PHY_BASIC_FEATURES */ |
| a4307c0e | 78 | .flags = PHY_IS_INTERNAL, |
| 09bb9aa0 | 79 | .config_init = bcm63xx_config_init, |
| a1cba561 | 80 | .ack_interrupt = bcm_phy_ack_intr, |
| cd33b3e0 | 81 | .config_intr = bcm63xx_config_intr, |
| d5bf9071 | 82 | } }; |
| 09bb9aa0 | 83 | |
| 50fd7150 | 84 | module_phy_driver(bcm63xx_driver); |
| 4e4f10f6 | 85 | |
| cf93c945 | 86 | static struct mdio_device_id __maybe_unused bcm63xx_tbl[] = { |
| 4e4f10f6 DW |
87 | { 0x00406000, 0xfffffc00 }, |
| 88 | { 0x002bdc00, 0xfffffc00 }, | |
| 89 | { } | |
| 90 | }; | |
| 91 | ||
| 0de8655a | 92 | MODULE_DEVICE_TABLE(mdio, bcm63xx_tbl); |