[linux-2.6-block.git] / drivers / net / phy / at803x.c

/*
 * drivers/net/phy/at803x.c
 *
 * Driver for Atheros 803x PHY
 *
 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/phy.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/of_gpio.h>
#include <linux/gpio/consumer.h>

#define AT803X_INTR_ENABLE			0x12
#define AT803X_INTR_ENABLE_AUTONEG_ERR		BIT(15)
#define AT803X_INTR_ENABLE_SPEED_CHANGED	BIT(14)
#define AT803X_INTR_ENABLE_DUPLEX_CHANGED	BIT(13)
#define AT803X_INTR_ENABLE_PAGE_RECEIVED	BIT(12)
#define AT803X_INTR_ENABLE_LINK_FAIL		BIT(11)
#define AT803X_INTR_ENABLE_LINK_SUCCESS		BIT(10)
#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE	BIT(5)
#define AT803X_INTR_ENABLE_POLARITY_CHANGED	BIT(1)
#define AT803X_INTR_ENABLE_WOL			BIT(0)

#define AT803X_INTR_STATUS			0x13

#define AT803X_SMART_SPEED			0x14
#define AT803X_LED_CONTROL			0x18

#define AT803X_DEVICE_ADDR			0x03
#define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
#define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
#define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
#define AT803X_MMD_ACCESS_CONTROL		0x0D
#define AT803X_MMD_ACCESS_CONTROL_DATA		0x0E
#define AT803X_FUNC_DATA			0x4003
#define AT803X_REG_CHIP_CONFIG			0x1f
#define AT803X_BT_BX_REG_SEL			0x8000

#define AT803X_DEBUG_ADDR			0x1D
#define AT803X_DEBUG_DATA			0x1E

#define AT803X_MODE_CFG_MASK			0x0F
#define AT803X_MODE_CFG_SGMII			0x01

#define AT803X_PSSR			0x11	/*PHY-Specific Status Register*/
#define AT803X_PSSR_MR_AN_COMPLETE	0x0200

#define AT803X_DEBUG_REG_0			0x00
#define AT803X_DEBUG_RX_CLK_DLY_EN		BIT(15)

#define AT803X_DEBUG_REG_5			0x05
#define AT803X_DEBUG_TX_CLK_DLY_EN		BIT(8)

#define ATH8030_PHY_ID 0x004dd076
#define ATH8031_PHY_ID 0x004dd074
#define ATH8035_PHY_ID 0x004dd072
#define AT803X_PHY_ID_MASK			0xffffffef

MODULE_DESCRIPTION("Atheros 803x PHY driver");
MODULE_AUTHOR("Matus Ujhelyi");
MODULE_LICENSE("GPL");

struct at803x_priv {
	bool phy_reset:1;
	struct gpio_desc *gpiod_reset;
};

struct at803x_context {
	u16 bmcr;
	u16 advertise;
	u16 control1000;
	u16 int_enable;
	u16 smart_speed;
	u16 led_control;
};

static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
{
	int ret;

	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
	if (ret < 0)
		return ret;

	return phy_read(phydev, AT803X_DEBUG_DATA);
}

static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
				 u16 clear, u16 set)
{
	u16 val;
	int ret;

	ret = at803x_debug_reg_read(phydev, reg);
	if (ret < 0)
		return ret;

	val = ret & 0xffff;
	val &= ~clear;
	val |= set;

	return phy_write(phydev, AT803X_DEBUG_DATA, val);
}

static inline int at803x_enable_rx_delay(struct phy_device *phydev)
{
	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
					AT803X_DEBUG_RX_CLK_DLY_EN);
}

static inline int at803x_enable_tx_delay(struct phy_device *phydev)
{
	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
					AT803X_DEBUG_TX_CLK_DLY_EN);
}

/* save relevant PHY registers to private copy */
static void at803x_context_save(struct phy_device *phydev,
				struct at803x_context *context)
{
	context->bmcr = phy_read(phydev, MII_BMCR);
	context->advertise = phy_read(phydev, MII_ADVERTISE);
	context->control1000 = phy_read(phydev, MII_CTRL1000);
	context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
	context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
	context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
}

/* restore relevant PHY registers from private copy */
static void at803x_context_restore(struct phy_device *phydev,
				   const struct at803x_context *context)
{
	phy_write(phydev, MII_BMCR, context->bmcr);
	phy_write(phydev, MII_ADVERTISE, context->advertise);
	phy_write(phydev, MII_CTRL1000, context->control1000);
	phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
	phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
	phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
}

static int at803x_set_wol(struct phy_device *phydev,
			  struct ethtool_wolinfo *wol)
{
	struct net_device *ndev = phydev->attached_dev;
	const u8 *mac;
	int ret;
	u32 value;
	unsigned int i, offsets[] = {
		AT803X_LOC_MAC_ADDR_32_47_OFFSET,
		AT803X_LOC_MAC_ADDR_16_31_OFFSET,
		AT803X_LOC_MAC_ADDR_0_15_OFFSET,
	};

	if (!ndev)
		return -ENODEV;

	if (wol->wolopts & WAKE_MAGIC) {
		mac = (const u8 *) ndev->dev_addr;

		if (!is_valid_ether_addr(mac))
			return -EINVAL;

		for (i = 0; i < 3; i++) {
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
				  AT803X_DEVICE_ADDR);
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
				  offsets[i]);
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
				  AT803X_FUNC_DATA);
			phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
				  mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
		}

		value = phy_read(phydev, AT803X_INTR_ENABLE);
		value |= AT803X_INTR_ENABLE_WOL;
		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
		if (ret)
			return ret;
		value = phy_read(phydev, AT803X_INTR_STATUS);
	} else {
		value = phy_read(phydev, AT803X_INTR_ENABLE);
		value &= (~AT803X_INTR_ENABLE_WOL);
		ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
		if (ret)
			return ret;
		value = phy_read(phydev, AT803X_INTR_STATUS);
	}

	return ret;
}

static void at803x_get_wol(struct phy_device *phydev,
			   struct ethtool_wolinfo *wol)
{
	u32 value;

	wol->supported = WAKE_MAGIC;
	wol->wolopts = 0;

	value = phy_read(phydev, AT803X_INTR_ENABLE);
	if (value & AT803X_INTR_ENABLE_WOL)
		wol->wolopts |= WAKE_MAGIC;
}

static int at803x_suspend(struct phy_device *phydev)
{
	int value;
	int wol_enabled;

	mutex_lock(&phydev->lock);

	value = phy_read(phydev, AT803X_INTR_ENABLE);
	wol_enabled = value & AT803X_INTR_ENABLE_WOL;

	value = phy_read(phydev, MII_BMCR);

	if (wol_enabled)
		value |= BMCR_ISOLATE;
	else
		value |= BMCR_PDOWN;

	phy_write(phydev, MII_BMCR, value);

	mutex_unlock(&phydev->lock);

	return 0;
}

static int at803x_resume(struct phy_device *phydev)
{
	int value;

	value = phy_read(phydev, MII_BMCR);
	value &= ~(BMCR_PDOWN | BMCR_ISOLATE);
	phy_write(phydev, MII_BMCR, value);

	return 0;
}

static int at803x_probe(struct phy_device *phydev)
{
	struct device *dev = &phydev->mdio.dev;
	struct at803x_priv *priv;
	struct gpio_desc *gpiod_reset;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	if (phydev->drv->phy_id != ATH8030_PHY_ID)
		goto does_not_require_reset_workaround;

	gpiod_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
	if (IS_ERR(gpiod_reset))
		return PTR_ERR(gpiod_reset);

	priv->gpiod_reset = gpiod_reset;

does_not_require_reset_workaround:
	phydev->priv = priv;

	return 0;
}

static int at803x_config_init(struct phy_device *phydev)
{
	int ret;

	ret = genphy_config_init(phydev);
	if (ret < 0)
		return ret;

	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
		ret = at803x_enable_rx_delay(phydev);
		if (ret < 0)
			return ret;
	}

	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
			phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
		ret = at803x_enable_tx_delay(phydev);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static int at803x_ack_interrupt(struct phy_device *phydev)
{
	int err;

	err = phy_read(phydev, AT803X_INTR_STATUS);

	return (err < 0) ? err : 0;
}

static int at803x_config_intr(struct phy_device *phydev)
{
	int err;
	int value;

	value = phy_read(phydev, AT803X_INTR_ENABLE);

	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
		value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
		value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
		value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
		value |= AT803X_INTR_ENABLE_LINK_FAIL;
		value |= AT803X_INTR_ENABLE_LINK_SUCCESS;

		err = phy_write(phydev, AT803X_INTR_ENABLE, value);
	}
	else
		err = phy_write(phydev, AT803X_INTR_ENABLE, 0);

	return err;
}

static void at803x_link_change_notify(struct phy_device *phydev)
{
	struct at803x_priv *priv = phydev->priv;

	/*
	 * Conduct a hardware reset for AT8030 every time a link loss is
	 * signalled. This is necessary to circumvent a hardware bug that
	 * occurs when the cable is unplugged while TX packets are pending
	 * in the FIFO. In such cases, the FIFO enters an error mode it
	 * cannot recover from by software.
	 */
	if (phydev->state == PHY_NOLINK) {
		if (priv->gpiod_reset && !priv->phy_reset) {
			struct at803x_context context;

			at803x_context_save(phydev, &context);

			gpiod_set_value(priv->gpiod_reset, 1);
			msleep(1);
			gpiod_set_value(priv->gpiod_reset, 0);
			msleep(1);

			at803x_context_restore(phydev, &context);

			phydev_dbg(phydev, "%s(): phy was reset\n",
				   __func__);
			priv->phy_reset = true;
		}
	} else {
		priv->phy_reset = false;
	}
}

static int at803x_aneg_done(struct phy_device *phydev)
{
	int ccr;

	int aneg_done = genphy_aneg_done(phydev);
	if (aneg_done != BMSR_ANEGCOMPLETE)
		return aneg_done;

	/*
	 * in SGMII mode, if copper side autoneg is successful,
	 * also check SGMII side autoneg result
	 */
	ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
	if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII)
		return aneg_done;

	/* switch to SGMII/fiber page */
	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);

	/* check if the SGMII link is OK. */
	if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) {
		pr_warn("803x_aneg_done: SGMII link is not ok\n");
		aneg_done = 0;
	}
	/* switch back to copper page */
	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);

	return aneg_done;
}

static struct phy_driver at803x_driver[] = {
{
	/* ATHEROS 8035 */
	.phy_id			= ATH8035_PHY_ID,
	.name			= "Atheros 8035 ethernet",
	.phy_id_mask		= AT803X_PHY_ID_MASK,
	.probe			= at803x_probe,
	.config_init		= at803x_config_init,
	.set_wol		= at803x_set_wol,
	.get_wol		= at803x_get_wol,
	.suspend		= at803x_suspend,
	.resume			= at803x_resume,
	.features		= PHY_GBIT_FEATURES,
	.flags			= PHY_HAS_INTERRUPT,
	.config_aneg		= genphy_config_aneg,
	.read_status		= genphy_read_status,
	.ack_interrupt		= at803x_ack_interrupt,
	.config_intr		= at803x_config_intr,
}, {
	/* ATHEROS 8030 */
	.phy_id			= ATH8030_PHY_ID,
	.name			= "Atheros 8030 ethernet",
	.phy_id_mask		= AT803X_PHY_ID_MASK,
	.probe			= at803x_probe,
	.config_init		= at803x_config_init,
	.link_change_notify	= at803x_link_change_notify,
	.set_wol		= at803x_set_wol,
	.get_wol		= at803x_get_wol,
	.suspend		= at803x_suspend,
	.resume			= at803x_resume,
	.features		= PHY_BASIC_FEATURES,
	.flags			= PHY_HAS_INTERRUPT,
	.config_aneg		= genphy_config_aneg,
	.read_status		= genphy_read_status,
	.ack_interrupt		= at803x_ack_interrupt,
	.config_intr		= at803x_config_intr,
}, {
	/* ATHEROS 8031 */
	.phy_id			= ATH8031_PHY_ID,
	.name			= "Atheros 8031 ethernet",
	.phy_id_mask		= AT803X_PHY_ID_MASK,
	.probe			= at803x_probe,
	.config_init		= at803x_config_init,
	.set_wol		= at803x_set_wol,
	.get_wol		= at803x_get_wol,
	.suspend		= at803x_suspend,
	.resume			= at803x_resume,
	.features		= PHY_GBIT_FEATURES,
	.flags			= PHY_HAS_INTERRUPT,
	.config_aneg		= genphy_config_aneg,
	.read_status		= genphy_read_status,
	.aneg_done		= at803x_aneg_done,
	.ack_interrupt		= &at803x_ack_interrupt,
	.config_intr		= &at803x_config_intr,
} };

module_phy_driver(at803x_driver);

static struct mdio_device_id __maybe_unused atheros_tbl[] = {
	{ ATH8030_PHY_ID, AT803X_PHY_ID_MASK },
	{ ATH8031_PHY_ID, AT803X_PHY_ID_MASK },
	{ ATH8035_PHY_ID, AT803X_PHY_ID_MASK },
	{ }
};

MODULE_DEVICE_TABLE(mdio, atheros_tbl);
Commit	Line	Data
0ca7111a MU	1	/*
	2	* drivers/net/phy/at803x.c
	3	*
	4	* Driver for Atheros 803x PHY
	5	*
	6	* Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	#include <linux/phy.h>
	15	#include <linux/module.h>
	16	#include <linux/string.h>
	17	#include <linux/netdevice.h>
	18	#include <linux/etherdevice.h>
13a56b44 DM	19	#include <linux/of_gpio.h>
13a56b44 DM	20	#include <linux/gpio/consumer.h>
0ca7111a MU	21
0ca7111a MU	22	#define AT803X_INTR_ENABLE 0x12
e6e4a556 MB	23	#define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
	24	#define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14)
	25	#define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
	26	#define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12)
	27	#define AT803X_INTR_ENABLE_LINK_FAIL BIT(11)
	28	#define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10)
	29	#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5)
	30	#define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1)
	31	#define AT803X_INTR_ENABLE_WOL BIT(0)
	32
0ca7111a	33	#define AT803X_INTR_STATUS 0x13
a46bd63b	34
13a56b44 DM	35	#define AT803X_SMART_SPEED 0x14
13a56b44 DM	36	#define AT803X_LED_CONTROL 0x18
a46bd63b	37
0ca7111a MU	38	#define AT803X_DEVICE_ADDR 0x03
	39	#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
	40	#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
	41	#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
	42	#define AT803X_MMD_ACCESS_CONTROL 0x0D
	43	#define AT803X_MMD_ACCESS_CONTROL_DATA 0x0E
	44	#define AT803X_FUNC_DATA 0x4003
f62265b5 ZK	45	#define AT803X_REG_CHIP_CONFIG 0x1f
f62265b5 ZK	46	#define AT803X_BT_BX_REG_SEL 0x8000
a46bd63b	47
1ca6d1b1 M	48	#define AT803X_DEBUG_ADDR 0x1D
1ca6d1b1 M	49	#define AT803X_DEBUG_DATA 0x1E
a46bd63b	50
f62265b5 ZK	51	#define AT803X_MODE_CFG_MASK 0x0F
	52	#define AT803X_MODE_CFG_SGMII 0x01
	53
	54	#define AT803X_PSSR 0x11 /PHY-Specific Status Register/
	55	#define AT803X_PSSR_MR_AN_COMPLETE 0x0200
	56
2e5f9f28 MB	57	#define AT803X_DEBUG_REG_0 0x00
2e5f9f28 MB	58	#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
a46bd63b	59
2e5f9f28 MB	60	#define AT803X_DEBUG_REG_5 0x05
2e5f9f28 MB	61	#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
0ca7111a	62
bd8ca17f DM	63	#define ATH8030_PHY_ID 0x004dd076
	64	#define ATH8031_PHY_ID 0x004dd074
	65	#define ATH8035_PHY_ID 0x004dd072
58effd71	66	#define AT803X_PHY_ID_MASK 0xffffffef
bd8ca17f	67
0ca7111a MU	68	MODULE_DESCRIPTION("Atheros 803x PHY driver");
	69	MODULE_AUTHOR("Matus Ujhelyi");
	70	MODULE_LICENSE("GPL");
	71
13a56b44 DM	72	struct at803x_priv {
	73	bool phy_reset:1;
	74	struct gpio_desc *gpiod_reset;
	75	};
	76
	77	struct at803x_context {
	78	u16 bmcr;
	79	u16 advertise;
	80	u16 control1000;
	81	u16 int_enable;
	82	u16 smart_speed;
	83	u16 led_control;
	84	};
	85
2e5f9f28 MB	86	static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
	87	{
	88	int ret;
	89
	90	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
	91	if (ret < 0)
	92	return ret;
	93
	94	return phy_read(phydev, AT803X_DEBUG_DATA);
	95	}
	96
	97	static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
	98	u16 clear, u16 set)
	99	{
	100	u16 val;
	101	int ret;
	102
	103	ret = at803x_debug_reg_read(phydev, reg);
	104	if (ret < 0)
	105	return ret;
	106
	107	val = ret & 0xffff;
	108	val &= ~clear;
	109	val \|= set;
	110
	111	return phy_write(phydev, AT803X_DEBUG_DATA, val);
	112	}
	113
	114	static inline int at803x_enable_rx_delay(struct phy_device *phydev)
	115	{
	116	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
	117	AT803X_DEBUG_RX_CLK_DLY_EN);
	118	}
	119
	120	static inline int at803x_enable_tx_delay(struct phy_device *phydev)
	121	{
	122	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
	123	AT803X_DEBUG_TX_CLK_DLY_EN);
	124	}
	125
13a56b44 DM	126	/* save relevant PHY registers to private copy */
	127	static void at803x_context_save(struct phy_device *phydev,
	128	struct at803x_context *context)
	129	{
	130	context->bmcr = phy_read(phydev, MII_BMCR);
	131	context->advertise = phy_read(phydev, MII_ADVERTISE);
	132	context->control1000 = phy_read(phydev, MII_CTRL1000);
	133	context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
	134	context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
	135	context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
	136	}
	137
	138	/* restore relevant PHY registers from private copy */
	139	static void at803x_context_restore(struct phy_device *phydev,
	140	const struct at803x_context *context)
	141	{
	142	phy_write(phydev, MII_BMCR, context->bmcr);
	143	phy_write(phydev, MII_ADVERTISE, context->advertise);
	144	phy_write(phydev, MII_CTRL1000, context->control1000);
	145	phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
	146	phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
	147	phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
	148	}
	149
ea13c9ee M	150	static int at803x_set_wol(struct phy_device *phydev,
ea13c9ee M	151	struct ethtool_wolinfo *wol)
0ca7111a MU	152	{
	153	struct net_device *ndev = phydev->attached_dev;
	154	const u8 *mac;
ea13c9ee M	155	int ret;
ea13c9ee M	156	u32 value;
0ca7111a MU	157	unsigned int i, offsets[] = {
	158	AT803X_LOC_MAC_ADDR_32_47_OFFSET,
	159	AT803X_LOC_MAC_ADDR_16_31_OFFSET,
	160	AT803X_LOC_MAC_ADDR_0_15_OFFSET,
	161	};
	162
	163	if (!ndev)
ea13c9ee	164	return -ENODEV;
0ca7111a	165
ea13c9ee M	166	if (wol->wolopts & WAKE_MAGIC) {
ea13c9ee M	167	mac = (const u8 *) ndev->dev_addr;
0ca7111a	168
ea13c9ee	169	if (!is_valid_ether_addr(mac))
fc755687	170	return -EINVAL;
0ca7111a	171
ea13c9ee M	172	for (i = 0; i < 3; i++) {
ea13c9ee M	173	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
0ca7111a	174	AT803X_DEVICE_ADDR);
ea13c9ee	175	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
0ca7111a	176	offsets[i]);
ea13c9ee	177	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
0ca7111a	178	AT803X_FUNC_DATA);
ea13c9ee	179	phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
0ca7111a	180	mac[(i * 2) + 1] \| (mac[(i * 2)] << 8));
ea13c9ee M	181	}
	182
	183	value = phy_read(phydev, AT803X_INTR_ENABLE);
e6e4a556	184	value \|= AT803X_INTR_ENABLE_WOL;
ea13c9ee M	185	ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
	186	if (ret)
	187	return ret;
	188	value = phy_read(phydev, AT803X_INTR_STATUS);
	189	} else {
	190	value = phy_read(phydev, AT803X_INTR_ENABLE);
e6e4a556	191	value &= (~AT803X_INTR_ENABLE_WOL);
ea13c9ee M	192	ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
	193	if (ret)
	194	return ret;
	195	value = phy_read(phydev, AT803X_INTR_STATUS);
0ca7111a	196	}
ea13c9ee M	197
	198	return ret;
	199	}
	200
	201	static void at803x_get_wol(struct phy_device *phydev,
	202	struct ethtool_wolinfo *wol)
	203	{
	204	u32 value;
	205
	206	wol->supported = WAKE_MAGIC;
	207	wol->wolopts = 0;
	208
	209	value = phy_read(phydev, AT803X_INTR_ENABLE);
e6e4a556	210	if (value & AT803X_INTR_ENABLE_WOL)
ea13c9ee	211	wol->wolopts \|= WAKE_MAGIC;
0ca7111a MU	212	}
0ca7111a MU	213
6229ed1f DM	214	static int at803x_suspend(struct phy_device *phydev)
	215	{
	216	int value;
	217	int wol_enabled;
	218
	219	mutex_lock(&phydev->lock);
	220
	221	value = phy_read(phydev, AT803X_INTR_ENABLE);
e6e4a556	222	wol_enabled = value & AT803X_INTR_ENABLE_WOL;
6229ed1f DM	223
	224	value = phy_read(phydev, MII_BMCR);
	225
	226	if (wol_enabled)
	227	value \|= BMCR_ISOLATE;
	228	else
	229	value \|= BMCR_PDOWN;
	230
	231	phy_write(phydev, MII_BMCR, value);
	232
	233	mutex_unlock(&phydev->lock);
	234
	235	return 0;
	236	}
	237
	238	static int at803x_resume(struct phy_device *phydev)
	239	{
	240	int value;
	241
6229ed1f DM	242	value = phy_read(phydev, MII_BMCR);
	243	value &= ~(BMCR_PDOWN \| BMCR_ISOLATE);
	244	phy_write(phydev, MII_BMCR, value);
	245
6229ed1f DM	246	return 0;
	247	}
	248
13a56b44 DM	249	static int at803x_probe(struct phy_device *phydev)
13a56b44 DM	250	{
e5a03bfd	251	struct device *dev = &phydev->mdio.dev;
13a56b44	252	struct at803x_priv *priv;
687908c2	253	struct gpio_desc *gpiod_reset;
13a56b44	254
8f2877ca	255	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
13a56b44 DM	256	if (!priv)
	257	return -ENOMEM;
	258
9eb13f65 SF	259	if (phydev->drv->phy_id != ATH8030_PHY_ID)
	260	goto does_not_require_reset_workaround;
	261
d57019d1	262	gpiod_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
687908c2 UKK	263	if (IS_ERR(gpiod_reset))
	264	return PTR_ERR(gpiod_reset);
	265
	266	priv->gpiod_reset = gpiod_reset;
13a56b44	267
9eb13f65	268	does_not_require_reset_workaround:
13a56b44 DM	269	phydev->priv = priv;
	270
	271	return 0;
	272	}
	273
0ca7111a MU	274	static int at803x_config_init(struct phy_device *phydev)
0ca7111a MU	275	{
1ca6d1b1	276	int ret;
0ca7111a	277
6ff01dbb DM	278	ret = genphy_config_init(phydev);
	279	if (ret < 0)
	280	return ret;
0ca7111a	281
2e5f9f28 MB	282	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID \|\|
	283	phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
	284	ret = at803x_enable_rx_delay(phydev);
	285	if (ret < 0)
1ca6d1b1	286	return ret;
2e5f9f28 MB	287	}
	288
	289	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID \|\|
	290	phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
	291	ret = at803x_enable_tx_delay(phydev);
	292	if (ret < 0)
1ca6d1b1 M	293	return ret;
	294	}
	295
0ca7111a MU	296	return 0;
	297	}
	298
77a99394 ZQ	299	static int at803x_ack_interrupt(struct phy_device *phydev)
	300	{
	301	int err;
	302
a46bd63b	303	err = phy_read(phydev, AT803X_INTR_STATUS);
77a99394 ZQ	304
	305	return (err < 0) ? err : 0;
	306	}
	307
	308	static int at803x_config_intr(struct phy_device *phydev)
	309	{
	310	int err;
	311	int value;
	312
a46bd63b	313	value = phy_read(phydev, AT803X_INTR_ENABLE);
77a99394	314
e6e4a556 MB	315	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
	316	value \|= AT803X_INTR_ENABLE_AUTONEG_ERR;
	317	value \|= AT803X_INTR_ENABLE_SPEED_CHANGED;
	318	value \|= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
	319	value \|= AT803X_INTR_ENABLE_LINK_FAIL;
	320	value \|= AT803X_INTR_ENABLE_LINK_SUCCESS;
	321
	322	err = phy_write(phydev, AT803X_INTR_ENABLE, value);
	323	}
77a99394	324	else
a46bd63b	325	err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
77a99394 ZQ	326
	327	return err;
	328	}
	329
13a56b44 DM	330	static void at803x_link_change_notify(struct phy_device *phydev)
	331	{
	332	struct at803x_priv *priv = phydev->priv;
	333
	334	/*
	335	* Conduct a hardware reset for AT8030 every time a link loss is
	336	* signalled. This is necessary to circumvent a hardware bug that
	337	* occurs when the cable is unplugged while TX packets are pending
	338	* in the FIFO. In such cases, the FIFO enters an error mode it
	339	* cannot recover from by software.
	340	*/
a05d7dfc TT	341	if (phydev->state == PHY_NOLINK) {
	342	if (priv->gpiod_reset && !priv->phy_reset) {
	343	struct at803x_context context;
	344
	345	at803x_context_save(phydev, &context);
	346
	347	gpiod_set_value(priv->gpiod_reset, 1);
	348	msleep(1);
	349	gpiod_set_value(priv->gpiod_reset, 0);
	350	msleep(1);
	351
	352	at803x_context_restore(phydev, &context);
	353
	354	phydev_dbg(phydev, "%s(): phy was reset\n",
	355	__func__);
	356	priv->phy_reset = true;
13a56b44	357	}
a05d7dfc TT	358	} else {
a05d7dfc TT	359	priv->phy_reset = false;
13a56b44 DM	360	}
	361	}
	362
f62265b5 ZK	363	static int at803x_aneg_done(struct phy_device *phydev)
	364	{
	365	int ccr;
	366
	367	int aneg_done = genphy_aneg_done(phydev);
	368	if (aneg_done != BMSR_ANEGCOMPLETE)
	369	return aneg_done;
	370
	371	/*
	372	* in SGMII mode, if copper side autoneg is successful,
	373	* also check SGMII side autoneg result
	374	*/
	375	ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
	376	if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII)
	377	return aneg_done;
	378
	379	/* switch to SGMII/fiber page */
	380	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
	381
	382	/* check if the SGMII link is OK. */
	383	if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) {
	384	pr_warn("803x_aneg_done: SGMII link is not ok\n");
	385	aneg_done = 0;
	386	}
	387	/* switch back to copper page */
	388	phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr \| AT803X_BT_BX_REG_SEL);
	389
	390	return aneg_done;
	391	}
	392
317420ab M	393	static struct phy_driver at803x_driver[] = {
	394	{
	395	/* ATHEROS 8035 */
13a56b44 DM	396	.phy_id = ATH8035_PHY_ID,
13a56b44 DM	397	.name = "Atheros 8035 ethernet",
58effd71	398	.phy_id_mask = AT803X_PHY_ID_MASK,
13a56b44 DM	399	.probe = at803x_probe,
13a56b44 DM	400	.config_init = at803x_config_init,
13a56b44 DM	401	.set_wol = at803x_set_wol,
	402	.get_wol = at803x_get_wol,
	403	.suspend = at803x_suspend,
	404	.resume = at803x_resume,
	405	.features = PHY_GBIT_FEATURES,
	406	.flags = PHY_HAS_INTERRUPT,
	407	.config_aneg = genphy_config_aneg,
	408	.read_status = genphy_read_status,
0eae5982 MR	409	.ack_interrupt = at803x_ack_interrupt,
0eae5982 MR	410	.config_intr = at803x_config_intr,
317420ab M	411	}, {
317420ab M	412	/* ATHEROS 8030 */
13a56b44 DM	413	.phy_id = ATH8030_PHY_ID,
13a56b44 DM	414	.name = "Atheros 8030 ethernet",
58effd71	415	.phy_id_mask = AT803X_PHY_ID_MASK,
13a56b44 DM	416	.probe = at803x_probe,
	417	.config_init = at803x_config_init,
	418	.link_change_notify = at803x_link_change_notify,
	419	.set_wol = at803x_set_wol,
	420	.get_wol = at803x_get_wol,
	421	.suspend = at803x_suspend,
	422	.resume = at803x_resume,
e15bb4c6	423	.features = PHY_BASIC_FEATURES,
13a56b44 DM	424	.flags = PHY_HAS_INTERRUPT,
	425	.config_aneg = genphy_config_aneg,
	426	.read_status = genphy_read_status,
0eae5982 MR	427	.ack_interrupt = at803x_ack_interrupt,
0eae5982 MR	428	.config_intr = at803x_config_intr,
05d7cce8 M	429	}, {
05d7cce8 M	430	/* ATHEROS 8031 */
13a56b44 DM	431	.phy_id = ATH8031_PHY_ID,
13a56b44 DM	432	.name = "Atheros 8031 ethernet",
58effd71	433	.phy_id_mask = AT803X_PHY_ID_MASK,
13a56b44 DM	434	.probe = at803x_probe,
13a56b44 DM	435	.config_init = at803x_config_init,
13a56b44 DM	436	.set_wol = at803x_set_wol,
	437	.get_wol = at803x_get_wol,
	438	.suspend = at803x_suspend,
	439	.resume = at803x_resume,
	440	.features = PHY_GBIT_FEATURES,
	441	.flags = PHY_HAS_INTERRUPT,
	442	.config_aneg = genphy_config_aneg,
	443	.read_status = genphy_read_status,
f62265b5	444	.aneg_done = at803x_aneg_done,
13a56b44 DM	445	.ack_interrupt = &at803x_ack_interrupt,
13a56b44 DM	446	.config_intr = &at803x_config_intr,
317420ab	447	} };
0ca7111a	448
50fd7150	449	module_phy_driver(at803x_driver);
0ca7111a MU	450
0ca7111a MU	451	static struct mdio_device_id __maybe_unused atheros_tbl[] = {
58effd71 FE	452	{ ATH8030_PHY_ID, AT803X_PHY_ID_MASK },
	453	{ ATH8031_PHY_ID, AT803X_PHY_ID_MASK },
	454	{ ATH8035_PHY_ID, AT803X_PHY_ID_MASK },
0ca7111a MU	455	{ }
	456	};
	457
	458	MODULE_DEVICE_TABLE(mdio, atheros_tbl);