Commit | Line | Data |
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1da177e4 LT |
1 | /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */ |
2 | /* | |
3 | * Copyright 1996-1999 Thomas Bogendoerfer | |
4 | * | |
5 | * Derived from the lance driver written 1993,1994,1995 by Donald Becker. | |
6 | * | |
7 | * Copyright 1993 United States Government as represented by the | |
8 | * Director, National Security Agency. | |
9 | * | |
10 | * This software may be used and distributed according to the terms | |
11 | * of the GNU General Public License, incorporated herein by reference. | |
12 | * | |
13 | * This driver is for PCnet32 and PCnetPCI based ethercards | |
14 | */ | |
15 | /************************************************************************** | |
16 | * 23 Oct, 2000. | |
17 | * Fixed a few bugs, related to running the controller in 32bit mode. | |
18 | * | |
19 | * Carsten Langgaard, carstenl@mips.com | |
20 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | |
21 | * | |
22 | *************************************************************************/ | |
23 | ||
24 | #define DRV_NAME "pcnet32" | |
ac62ef04 DF |
25 | #define DRV_VERSION "1.32" |
26 | #define DRV_RELDATE "18.Mar.2006" | |
1da177e4 LT |
27 | #define PFX DRV_NAME ": " |
28 | ||
4a5e8e29 JG |
29 | static const char *const version = |
30 | DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n"; | |
1da177e4 LT |
31 | |
32 | #include <linux/module.h> | |
33 | #include <linux/kernel.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/errno.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/interrupt.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/init.h> | |
42 | #include <linux/ethtool.h> | |
43 | #include <linux/mii.h> | |
44 | #include <linux/crc32.h> | |
45 | #include <linux/netdevice.h> | |
46 | #include <linux/etherdevice.h> | |
47 | #include <linux/skbuff.h> | |
48 | #include <linux/spinlock.h> | |
49 | #include <linux/moduleparam.h> | |
50 | #include <linux/bitops.h> | |
51 | ||
52 | #include <asm/dma.h> | |
53 | #include <asm/io.h> | |
54 | #include <asm/uaccess.h> | |
55 | #include <asm/irq.h> | |
56 | ||
57 | /* | |
58 | * PCI device identifiers for "new style" Linux PCI Device Drivers | |
59 | */ | |
60 | static struct pci_device_id pcnet32_pci_tbl[] = { | |
4a5e8e29 JG |
61 | { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME, |
62 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
63 | { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, | |
64 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
65 | ||
66 | /* | |
67 | * Adapters that were sold with IBM's RS/6000 or pSeries hardware have | |
68 | * the incorrect vendor id. | |
69 | */ | |
70 | { PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE, | |
71 | PCI_ANY_ID, PCI_ANY_ID, | |
72 | PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, 0}, | |
73 | ||
74 | { } /* terminate list */ | |
1da177e4 LT |
75 | }; |
76 | ||
4a5e8e29 | 77 | MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl); |
1da177e4 LT |
78 | |
79 | static int cards_found; | |
80 | ||
81 | /* | |
82 | * VLB I/O addresses | |
83 | */ | |
84 | static unsigned int pcnet32_portlist[] __initdata = | |
4a5e8e29 | 85 | { 0x300, 0x320, 0x340, 0x360, 0 }; |
1da177e4 LT |
86 | |
87 | static int pcnet32_debug = 0; | |
4a5e8e29 JG |
88 | static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */ |
89 | static int pcnet32vlb; /* check for VLB cards ? */ | |
1da177e4 LT |
90 | |
91 | static struct net_device *pcnet32_dev; | |
92 | ||
93 | static int max_interrupt_work = 2; | |
94 | static int rx_copybreak = 200; | |
95 | ||
96 | #define PCNET32_PORT_AUI 0x00 | |
97 | #define PCNET32_PORT_10BT 0x01 | |
98 | #define PCNET32_PORT_GPSI 0x02 | |
99 | #define PCNET32_PORT_MII 0x03 | |
100 | ||
101 | #define PCNET32_PORT_PORTSEL 0x03 | |
102 | #define PCNET32_PORT_ASEL 0x04 | |
103 | #define PCNET32_PORT_100 0x40 | |
104 | #define PCNET32_PORT_FD 0x80 | |
105 | ||
106 | #define PCNET32_DMA_MASK 0xffffffff | |
107 | ||
108 | #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ)) | |
109 | #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4)) | |
110 | ||
111 | /* | |
112 | * table to translate option values from tulip | |
113 | * to internal options | |
114 | */ | |
f71e1309 | 115 | static const unsigned char options_mapping[] = { |
4a5e8e29 JG |
116 | PCNET32_PORT_ASEL, /* 0 Auto-select */ |
117 | PCNET32_PORT_AUI, /* 1 BNC/AUI */ | |
118 | PCNET32_PORT_AUI, /* 2 AUI/BNC */ | |
119 | PCNET32_PORT_ASEL, /* 3 not supported */ | |
120 | PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */ | |
121 | PCNET32_PORT_ASEL, /* 5 not supported */ | |
122 | PCNET32_PORT_ASEL, /* 6 not supported */ | |
123 | PCNET32_PORT_ASEL, /* 7 not supported */ | |
124 | PCNET32_PORT_ASEL, /* 8 not supported */ | |
125 | PCNET32_PORT_MII, /* 9 MII 10baseT */ | |
126 | PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */ | |
127 | PCNET32_PORT_MII, /* 11 MII (autosel) */ | |
128 | PCNET32_PORT_10BT, /* 12 10BaseT */ | |
129 | PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */ | |
130 | /* 14 MII 100BaseTx-FD */ | |
131 | PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, | |
132 | PCNET32_PORT_ASEL /* 15 not supported */ | |
1da177e4 LT |
133 | }; |
134 | ||
135 | static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = { | |
4a5e8e29 | 136 | "Loopback test (offline)" |
1da177e4 | 137 | }; |
4a5e8e29 | 138 | |
1da177e4 LT |
139 | #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN) |
140 | ||
ac62ef04 | 141 | #define PCNET32_NUM_REGS 136 |
1da177e4 | 142 | |
4a5e8e29 | 143 | #define MAX_UNITS 8 /* More are supported, limit only on options */ |
1da177e4 LT |
144 | static int options[MAX_UNITS]; |
145 | static int full_duplex[MAX_UNITS]; | |
146 | static int homepna[MAX_UNITS]; | |
147 | ||
148 | /* | |
149 | * Theory of Operation | |
150 | * | |
151 | * This driver uses the same software structure as the normal lance | |
152 | * driver. So look for a verbose description in lance.c. The differences | |
153 | * to the normal lance driver is the use of the 32bit mode of PCnet32 | |
154 | * and PCnetPCI chips. Because these chips are 32bit chips, there is no | |
155 | * 16MB limitation and we don't need bounce buffers. | |
156 | */ | |
157 | ||
1da177e4 LT |
158 | /* |
159 | * Set the number of Tx and Rx buffers, using Log_2(# buffers). | |
160 | * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. | |
161 | * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). | |
162 | */ | |
163 | #ifndef PCNET32_LOG_TX_BUFFERS | |
eabf0415 HWL |
164 | #define PCNET32_LOG_TX_BUFFERS 4 |
165 | #define PCNET32_LOG_RX_BUFFERS 5 | |
166 | #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */ | |
167 | #define PCNET32_LOG_MAX_RX_BUFFERS 9 | |
1da177e4 LT |
168 | #endif |
169 | ||
170 | #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS)) | |
eabf0415 | 171 | #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS)) |
1da177e4 LT |
172 | |
173 | #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS)) | |
eabf0415 | 174 | #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS)) |
1da177e4 LT |
175 | |
176 | #define PKT_BUF_SZ 1544 | |
177 | ||
178 | /* Offsets from base I/O address. */ | |
179 | #define PCNET32_WIO_RDP 0x10 | |
180 | #define PCNET32_WIO_RAP 0x12 | |
181 | #define PCNET32_WIO_RESET 0x14 | |
182 | #define PCNET32_WIO_BDP 0x16 | |
183 | ||
184 | #define PCNET32_DWIO_RDP 0x10 | |
185 | #define PCNET32_DWIO_RAP 0x14 | |
186 | #define PCNET32_DWIO_RESET 0x18 | |
187 | #define PCNET32_DWIO_BDP 0x1C | |
188 | ||
189 | #define PCNET32_TOTAL_SIZE 0x20 | |
190 | ||
191 | /* The PCNET32 Rx and Tx ring descriptors. */ | |
192 | struct pcnet32_rx_head { | |
0b5bf225 JG |
193 | u32 base; |
194 | s16 buf_length; | |
195 | s16 status; | |
196 | u32 msg_length; | |
197 | u32 reserved; | |
1da177e4 LT |
198 | }; |
199 | ||
200 | struct pcnet32_tx_head { | |
0b5bf225 JG |
201 | u32 base; |
202 | s16 length; | |
203 | s16 status; | |
204 | u32 misc; | |
205 | u32 reserved; | |
1da177e4 LT |
206 | }; |
207 | ||
208 | /* The PCNET32 32-Bit initialization block, described in databook. */ | |
209 | struct pcnet32_init_block { | |
0b5bf225 JG |
210 | u16 mode; |
211 | u16 tlen_rlen; | |
212 | u8 phys_addr[6]; | |
213 | u16 reserved; | |
214 | u32 filter[2]; | |
4a5e8e29 | 215 | /* Receive and transmit ring base, along with extra bits. */ |
0b5bf225 JG |
216 | u32 rx_ring; |
217 | u32 tx_ring; | |
1da177e4 LT |
218 | }; |
219 | ||
220 | /* PCnet32 access functions */ | |
221 | struct pcnet32_access { | |
4a5e8e29 JG |
222 | u16 (*read_csr) (unsigned long, int); |
223 | void (*write_csr) (unsigned long, int, u16); | |
224 | u16 (*read_bcr) (unsigned long, int); | |
225 | void (*write_bcr) (unsigned long, int, u16); | |
226 | u16 (*read_rap) (unsigned long); | |
227 | void (*write_rap) (unsigned long, u16); | |
228 | void (*reset) (unsigned long); | |
1da177e4 LT |
229 | }; |
230 | ||
231 | /* | |
76209926 HWL |
232 | * The first field of pcnet32_private is read by the ethernet device |
233 | * so the structure should be allocated using pci_alloc_consistent(). | |
1da177e4 LT |
234 | */ |
235 | struct pcnet32_private { | |
4a5e8e29 JG |
236 | struct pcnet32_init_block init_block; |
237 | /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */ | |
0b5bf225 JG |
238 | struct pcnet32_rx_head *rx_ring; |
239 | struct pcnet32_tx_head *tx_ring; | |
240 | dma_addr_t dma_addr;/* DMA address of beginning of this | |
241 | object, returned by pci_alloc_consistent */ | |
242 | struct pci_dev *pci_dev; | |
243 | const char *name; | |
4a5e8e29 | 244 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
0b5bf225 JG |
245 | struct sk_buff **tx_skbuff; |
246 | struct sk_buff **rx_skbuff; | |
247 | dma_addr_t *tx_dma_addr; | |
248 | dma_addr_t *rx_dma_addr; | |
249 | struct pcnet32_access a; | |
250 | spinlock_t lock; /* Guard lock */ | |
251 | unsigned int cur_rx, cur_tx; /* The next free ring entry */ | |
252 | unsigned int rx_ring_size; /* current rx ring size */ | |
253 | unsigned int tx_ring_size; /* current tx ring size */ | |
254 | unsigned int rx_mod_mask; /* rx ring modular mask */ | |
255 | unsigned int tx_mod_mask; /* tx ring modular mask */ | |
256 | unsigned short rx_len_bits; | |
257 | unsigned short tx_len_bits; | |
258 | dma_addr_t rx_ring_dma_addr; | |
259 | dma_addr_t tx_ring_dma_addr; | |
260 | unsigned int dirty_rx, /* ring entries to be freed. */ | |
261 | dirty_tx; | |
262 | ||
263 | struct net_device_stats stats; | |
264 | char tx_full; | |
265 | char phycount; /* number of phys found */ | |
266 | int options; | |
267 | unsigned int shared_irq:1, /* shared irq possible */ | |
268 | dxsuflo:1, /* disable transmit stop on uflo */ | |
269 | mii:1; /* mii port available */ | |
270 | struct net_device *next; | |
271 | struct mii_if_info mii_if; | |
272 | struct timer_list watchdog_timer; | |
273 | struct timer_list blink_timer; | |
274 | u32 msg_enable; /* debug message level */ | |
4a5e8e29 JG |
275 | |
276 | /* each bit indicates an available PHY */ | |
0b5bf225 | 277 | u32 phymask; |
1da177e4 LT |
278 | }; |
279 | ||
280 | static void pcnet32_probe_vlbus(void); | |
4a5e8e29 JG |
281 | static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *); |
282 | static int pcnet32_probe1(unsigned long, int, struct pci_dev *); | |
283 | static int pcnet32_open(struct net_device *); | |
284 | static int pcnet32_init_ring(struct net_device *); | |
285 | static int pcnet32_start_xmit(struct sk_buff *, struct net_device *); | |
286 | static int pcnet32_rx(struct net_device *); | |
287 | static void pcnet32_tx_timeout(struct net_device *dev); | |
1da177e4 | 288 | static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *); |
4a5e8e29 | 289 | static int pcnet32_close(struct net_device *); |
1da177e4 LT |
290 | static struct net_device_stats *pcnet32_get_stats(struct net_device *); |
291 | static void pcnet32_load_multicast(struct net_device *dev); | |
292 | static void pcnet32_set_multicast_list(struct net_device *); | |
4a5e8e29 | 293 | static int pcnet32_ioctl(struct net_device *, struct ifreq *, int); |
1da177e4 LT |
294 | static void pcnet32_watchdog(struct net_device *); |
295 | static int mdio_read(struct net_device *dev, int phy_id, int reg_num); | |
4a5e8e29 JG |
296 | static void mdio_write(struct net_device *dev, int phy_id, int reg_num, |
297 | int val); | |
1da177e4 LT |
298 | static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits); |
299 | static void pcnet32_ethtool_test(struct net_device *dev, | |
4a5e8e29 JG |
300 | struct ethtool_test *eth_test, u64 * data); |
301 | static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1); | |
1da177e4 LT |
302 | static int pcnet32_phys_id(struct net_device *dev, u32 data); |
303 | static void pcnet32_led_blink_callback(struct net_device *dev); | |
304 | static int pcnet32_get_regs_len(struct net_device *dev); | |
305 | static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
4a5e8e29 | 306 | void *ptr); |
1bcd3153 | 307 | static void pcnet32_purge_tx_ring(struct net_device *dev); |
a88c844c | 308 | static int pcnet32_alloc_ring(struct net_device *dev, char *name); |
eabf0415 | 309 | static void pcnet32_free_ring(struct net_device *dev); |
ac62ef04 | 310 | static void pcnet32_check_media(struct net_device *dev, int verbose); |
eabf0415 | 311 | |
1da177e4 | 312 | enum pci_flags_bit { |
4a5e8e29 JG |
313 | PCI_USES_IO = 1, PCI_USES_MEM = 2, PCI_USES_MASTER = 4, |
314 | PCI_ADDR0 = 0x10 << 0, PCI_ADDR1 = 0x10 << 1, PCI_ADDR2 = | |
315 | 0x10 << 2, PCI_ADDR3 = 0x10 << 3, | |
1da177e4 LT |
316 | }; |
317 | ||
4a5e8e29 | 318 | static u16 pcnet32_wio_read_csr(unsigned long addr, int index) |
1da177e4 | 319 | { |
4a5e8e29 JG |
320 | outw(index, addr + PCNET32_WIO_RAP); |
321 | return inw(addr + PCNET32_WIO_RDP); | |
1da177e4 LT |
322 | } |
323 | ||
4a5e8e29 | 324 | static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val) |
1da177e4 | 325 | { |
4a5e8e29 JG |
326 | outw(index, addr + PCNET32_WIO_RAP); |
327 | outw(val, addr + PCNET32_WIO_RDP); | |
1da177e4 LT |
328 | } |
329 | ||
4a5e8e29 | 330 | static u16 pcnet32_wio_read_bcr(unsigned long addr, int index) |
1da177e4 | 331 | { |
4a5e8e29 JG |
332 | outw(index, addr + PCNET32_WIO_RAP); |
333 | return inw(addr + PCNET32_WIO_BDP); | |
1da177e4 LT |
334 | } |
335 | ||
4a5e8e29 | 336 | static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val) |
1da177e4 | 337 | { |
4a5e8e29 JG |
338 | outw(index, addr + PCNET32_WIO_RAP); |
339 | outw(val, addr + PCNET32_WIO_BDP); | |
1da177e4 LT |
340 | } |
341 | ||
4a5e8e29 | 342 | static u16 pcnet32_wio_read_rap(unsigned long addr) |
1da177e4 | 343 | { |
4a5e8e29 | 344 | return inw(addr + PCNET32_WIO_RAP); |
1da177e4 LT |
345 | } |
346 | ||
4a5e8e29 | 347 | static void pcnet32_wio_write_rap(unsigned long addr, u16 val) |
1da177e4 | 348 | { |
4a5e8e29 | 349 | outw(val, addr + PCNET32_WIO_RAP); |
1da177e4 LT |
350 | } |
351 | ||
4a5e8e29 | 352 | static void pcnet32_wio_reset(unsigned long addr) |
1da177e4 | 353 | { |
4a5e8e29 | 354 | inw(addr + PCNET32_WIO_RESET); |
1da177e4 LT |
355 | } |
356 | ||
4a5e8e29 | 357 | static int pcnet32_wio_check(unsigned long addr) |
1da177e4 | 358 | { |
4a5e8e29 JG |
359 | outw(88, addr + PCNET32_WIO_RAP); |
360 | return (inw(addr + PCNET32_WIO_RAP) == 88); | |
1da177e4 LT |
361 | } |
362 | ||
363 | static struct pcnet32_access pcnet32_wio = { | |
4a5e8e29 JG |
364 | .read_csr = pcnet32_wio_read_csr, |
365 | .write_csr = pcnet32_wio_write_csr, | |
366 | .read_bcr = pcnet32_wio_read_bcr, | |
367 | .write_bcr = pcnet32_wio_write_bcr, | |
368 | .read_rap = pcnet32_wio_read_rap, | |
369 | .write_rap = pcnet32_wio_write_rap, | |
370 | .reset = pcnet32_wio_reset | |
1da177e4 LT |
371 | }; |
372 | ||
4a5e8e29 | 373 | static u16 pcnet32_dwio_read_csr(unsigned long addr, int index) |
1da177e4 | 374 | { |
4a5e8e29 JG |
375 | outl(index, addr + PCNET32_DWIO_RAP); |
376 | return (inl(addr + PCNET32_DWIO_RDP) & 0xffff); | |
1da177e4 LT |
377 | } |
378 | ||
4a5e8e29 | 379 | static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val) |
1da177e4 | 380 | { |
4a5e8e29 JG |
381 | outl(index, addr + PCNET32_DWIO_RAP); |
382 | outl(val, addr + PCNET32_DWIO_RDP); | |
1da177e4 LT |
383 | } |
384 | ||
4a5e8e29 | 385 | static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index) |
1da177e4 | 386 | { |
4a5e8e29 JG |
387 | outl(index, addr + PCNET32_DWIO_RAP); |
388 | return (inl(addr + PCNET32_DWIO_BDP) & 0xffff); | |
1da177e4 LT |
389 | } |
390 | ||
4a5e8e29 | 391 | static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val) |
1da177e4 | 392 | { |
4a5e8e29 JG |
393 | outl(index, addr + PCNET32_DWIO_RAP); |
394 | outl(val, addr + PCNET32_DWIO_BDP); | |
1da177e4 LT |
395 | } |
396 | ||
4a5e8e29 | 397 | static u16 pcnet32_dwio_read_rap(unsigned long addr) |
1da177e4 | 398 | { |
4a5e8e29 | 399 | return (inl(addr + PCNET32_DWIO_RAP) & 0xffff); |
1da177e4 LT |
400 | } |
401 | ||
4a5e8e29 | 402 | static void pcnet32_dwio_write_rap(unsigned long addr, u16 val) |
1da177e4 | 403 | { |
4a5e8e29 | 404 | outl(val, addr + PCNET32_DWIO_RAP); |
1da177e4 LT |
405 | } |
406 | ||
4a5e8e29 | 407 | static void pcnet32_dwio_reset(unsigned long addr) |
1da177e4 | 408 | { |
4a5e8e29 | 409 | inl(addr + PCNET32_DWIO_RESET); |
1da177e4 LT |
410 | } |
411 | ||
4a5e8e29 | 412 | static int pcnet32_dwio_check(unsigned long addr) |
1da177e4 | 413 | { |
4a5e8e29 JG |
414 | outl(88, addr + PCNET32_DWIO_RAP); |
415 | return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88); | |
1da177e4 LT |
416 | } |
417 | ||
418 | static struct pcnet32_access pcnet32_dwio = { | |
4a5e8e29 JG |
419 | .read_csr = pcnet32_dwio_read_csr, |
420 | .write_csr = pcnet32_dwio_write_csr, | |
421 | .read_bcr = pcnet32_dwio_read_bcr, | |
422 | .write_bcr = pcnet32_dwio_write_bcr, | |
423 | .read_rap = pcnet32_dwio_read_rap, | |
424 | .write_rap = pcnet32_dwio_write_rap, | |
425 | .reset = pcnet32_dwio_reset | |
1da177e4 LT |
426 | }; |
427 | ||
428 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
429 | static void pcnet32_poll_controller(struct net_device *dev) | |
430 | { | |
4a5e8e29 JG |
431 | disable_irq(dev->irq); |
432 | pcnet32_interrupt(0, dev, NULL); | |
433 | enable_irq(dev->irq); | |
1da177e4 LT |
434 | } |
435 | #endif | |
436 | ||
1da177e4 LT |
437 | static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
438 | { | |
4a5e8e29 JG |
439 | struct pcnet32_private *lp = dev->priv; |
440 | unsigned long flags; | |
441 | int r = -EOPNOTSUPP; | |
1da177e4 | 442 | |
4a5e8e29 JG |
443 | if (lp->mii) { |
444 | spin_lock_irqsave(&lp->lock, flags); | |
445 | mii_ethtool_gset(&lp->mii_if, cmd); | |
446 | spin_unlock_irqrestore(&lp->lock, flags); | |
447 | r = 0; | |
448 | } | |
449 | return r; | |
1da177e4 LT |
450 | } |
451 | ||
452 | static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
453 | { | |
4a5e8e29 JG |
454 | struct pcnet32_private *lp = dev->priv; |
455 | unsigned long flags; | |
456 | int r = -EOPNOTSUPP; | |
1da177e4 | 457 | |
4a5e8e29 JG |
458 | if (lp->mii) { |
459 | spin_lock_irqsave(&lp->lock, flags); | |
460 | r = mii_ethtool_sset(&lp->mii_if, cmd); | |
461 | spin_unlock_irqrestore(&lp->lock, flags); | |
462 | } | |
463 | return r; | |
1da177e4 LT |
464 | } |
465 | ||
4a5e8e29 JG |
466 | static void pcnet32_get_drvinfo(struct net_device *dev, |
467 | struct ethtool_drvinfo *info) | |
1da177e4 | 468 | { |
4a5e8e29 JG |
469 | struct pcnet32_private *lp = dev->priv; |
470 | ||
471 | strcpy(info->driver, DRV_NAME); | |
472 | strcpy(info->version, DRV_VERSION); | |
473 | if (lp->pci_dev) | |
474 | strcpy(info->bus_info, pci_name(lp->pci_dev)); | |
475 | else | |
476 | sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr); | |
1da177e4 LT |
477 | } |
478 | ||
479 | static u32 pcnet32_get_link(struct net_device *dev) | |
480 | { | |
4a5e8e29 JG |
481 | struct pcnet32_private *lp = dev->priv; |
482 | unsigned long flags; | |
483 | int r; | |
1da177e4 | 484 | |
4a5e8e29 JG |
485 | spin_lock_irqsave(&lp->lock, flags); |
486 | if (lp->mii) { | |
487 | r = mii_link_ok(&lp->mii_if); | |
488 | } else { | |
489 | ulong ioaddr = dev->base_addr; /* card base I/O address */ | |
490 | r = (lp->a.read_bcr(ioaddr, 4) != 0xc0); | |
491 | } | |
492 | spin_unlock_irqrestore(&lp->lock, flags); | |
493 | ||
494 | return r; | |
1da177e4 LT |
495 | } |
496 | ||
497 | static u32 pcnet32_get_msglevel(struct net_device *dev) | |
498 | { | |
4a5e8e29 JG |
499 | struct pcnet32_private *lp = dev->priv; |
500 | return lp->msg_enable; | |
1da177e4 LT |
501 | } |
502 | ||
503 | static void pcnet32_set_msglevel(struct net_device *dev, u32 value) | |
504 | { | |
4a5e8e29 JG |
505 | struct pcnet32_private *lp = dev->priv; |
506 | lp->msg_enable = value; | |
1da177e4 LT |
507 | } |
508 | ||
509 | static int pcnet32_nway_reset(struct net_device *dev) | |
510 | { | |
4a5e8e29 JG |
511 | struct pcnet32_private *lp = dev->priv; |
512 | unsigned long flags; | |
513 | int r = -EOPNOTSUPP; | |
1da177e4 | 514 | |
4a5e8e29 JG |
515 | if (lp->mii) { |
516 | spin_lock_irqsave(&lp->lock, flags); | |
517 | r = mii_nway_restart(&lp->mii_if); | |
518 | spin_unlock_irqrestore(&lp->lock, flags); | |
519 | } | |
520 | return r; | |
1da177e4 LT |
521 | } |
522 | ||
4a5e8e29 JG |
523 | static void pcnet32_get_ringparam(struct net_device *dev, |
524 | struct ethtool_ringparam *ering) | |
1da177e4 | 525 | { |
4a5e8e29 | 526 | struct pcnet32_private *lp = dev->priv; |
1da177e4 | 527 | |
4a5e8e29 JG |
528 | ering->tx_max_pending = TX_MAX_RING_SIZE - 1; |
529 | ering->tx_pending = lp->tx_ring_size - 1; | |
530 | ering->rx_max_pending = RX_MAX_RING_SIZE - 1; | |
531 | ering->rx_pending = lp->rx_ring_size - 1; | |
eabf0415 HWL |
532 | } |
533 | ||
4a5e8e29 JG |
534 | static int pcnet32_set_ringparam(struct net_device *dev, |
535 | struct ethtool_ringparam *ering) | |
eabf0415 | 536 | { |
4a5e8e29 JG |
537 | struct pcnet32_private *lp = dev->priv; |
538 | unsigned long flags; | |
539 | int i; | |
540 | ||
541 | if (ering->rx_mini_pending || ering->rx_jumbo_pending) | |
542 | return -EINVAL; | |
543 | ||
544 | if (netif_running(dev)) | |
545 | pcnet32_close(dev); | |
546 | ||
547 | spin_lock_irqsave(&lp->lock, flags); | |
eabf0415 | 548 | pcnet32_free_ring(dev); |
4a5e8e29 JG |
549 | lp->tx_ring_size = |
550 | min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE); | |
551 | lp->rx_ring_size = | |
552 | min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE); | |
553 | ||
554 | /* set the minimum ring size to 4, to allow the loopback test to work | |
555 | * unchanged. | |
556 | */ | |
557 | for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) { | |
558 | if (lp->tx_ring_size <= (1 << i)) | |
559 | break; | |
560 | } | |
561 | lp->tx_ring_size = (1 << i); | |
562 | lp->tx_mod_mask = lp->tx_ring_size - 1; | |
563 | lp->tx_len_bits = (i << 12); | |
eabf0415 | 564 | |
4a5e8e29 JG |
565 | for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) { |
566 | if (lp->rx_ring_size <= (1 << i)) | |
567 | break; | |
568 | } | |
569 | lp->rx_ring_size = (1 << i); | |
570 | lp->rx_mod_mask = lp->rx_ring_size - 1; | |
571 | lp->rx_len_bits = (i << 4); | |
572 | ||
573 | if (pcnet32_alloc_ring(dev, dev->name)) { | |
574 | pcnet32_free_ring(dev); | |
575 | spin_unlock_irqrestore(&lp->lock, flags); | |
576 | return -ENOMEM; | |
577 | } | |
eabf0415 | 578 | |
4a5e8e29 | 579 | spin_unlock_irqrestore(&lp->lock, flags); |
eabf0415 | 580 | |
4a5e8e29 JG |
581 | if (pcnet32_debug & NETIF_MSG_DRV) |
582 | printk(KERN_INFO PFX | |
583 | "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name, | |
584 | lp->rx_ring_size, lp->tx_ring_size); | |
eabf0415 | 585 | |
4a5e8e29 JG |
586 | if (netif_running(dev)) |
587 | pcnet32_open(dev); | |
588 | ||
589 | return 0; | |
1da177e4 LT |
590 | } |
591 | ||
4a5e8e29 JG |
592 | static void pcnet32_get_strings(struct net_device *dev, u32 stringset, |
593 | u8 * data) | |
1da177e4 | 594 | { |
4a5e8e29 | 595 | memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test)); |
1da177e4 LT |
596 | } |
597 | ||
598 | static int pcnet32_self_test_count(struct net_device *dev) | |
599 | { | |
4a5e8e29 | 600 | return PCNET32_TEST_LEN; |
1da177e4 LT |
601 | } |
602 | ||
603 | static void pcnet32_ethtool_test(struct net_device *dev, | |
4a5e8e29 | 604 | struct ethtool_test *test, u64 * data) |
1da177e4 | 605 | { |
4a5e8e29 JG |
606 | struct pcnet32_private *lp = dev->priv; |
607 | int rc; | |
608 | ||
609 | if (test->flags == ETH_TEST_FL_OFFLINE) { | |
610 | rc = pcnet32_loopback_test(dev, data); | |
611 | if (rc) { | |
612 | if (netif_msg_hw(lp)) | |
613 | printk(KERN_DEBUG "%s: Loopback test failed.\n", | |
614 | dev->name); | |
615 | test->flags |= ETH_TEST_FL_FAILED; | |
616 | } else if (netif_msg_hw(lp)) | |
617 | printk(KERN_DEBUG "%s: Loopback test passed.\n", | |
618 | dev->name); | |
1da177e4 | 619 | } else if (netif_msg_hw(lp)) |
4a5e8e29 JG |
620 | printk(KERN_DEBUG |
621 | "%s: No tests to run (specify 'Offline' on ethtool).", | |
622 | dev->name); | |
623 | } /* end pcnet32_ethtool_test */ | |
1da177e4 | 624 | |
4a5e8e29 | 625 | static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1) |
1da177e4 | 626 | { |
4a5e8e29 JG |
627 | struct pcnet32_private *lp = dev->priv; |
628 | struct pcnet32_access *a = &lp->a; /* access to registers */ | |
629 | ulong ioaddr = dev->base_addr; /* card base I/O address */ | |
630 | struct sk_buff *skb; /* sk buff */ | |
631 | int x, i; /* counters */ | |
632 | int numbuffs = 4; /* number of TX/RX buffers and descs */ | |
633 | u16 status = 0x8300; /* TX ring status */ | |
634 | u16 teststatus; /* test of ring status */ | |
635 | int rc; /* return code */ | |
636 | int size; /* size of packets */ | |
637 | unsigned char *packet; /* source packet data */ | |
638 | static const int data_len = 60; /* length of source packets */ | |
639 | unsigned long flags; | |
640 | unsigned long ticks; | |
641 | ||
642 | *data1 = 1; /* status of test, default to fail */ | |
643 | rc = 1; /* default to fail */ | |
644 | ||
645 | if (netif_running(dev)) | |
646 | pcnet32_close(dev); | |
647 | ||
648 | spin_lock_irqsave(&lp->lock, flags); | |
649 | ||
650 | /* Reset the PCNET32 */ | |
651 | lp->a.reset(ioaddr); | |
652 | ||
653 | /* switch pcnet32 to 32bit mode */ | |
654 | lp->a.write_bcr(ioaddr, 20, 2); | |
655 | ||
656 | lp->init_block.mode = | |
657 | le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7); | |
658 | lp->init_block.filter[0] = 0; | |
659 | lp->init_block.filter[1] = 0; | |
660 | ||
661 | /* purge & init rings but don't actually restart */ | |
662 | pcnet32_restart(dev, 0x0000); | |
663 | ||
664 | lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */ | |
665 | ||
666 | /* Initialize Transmit buffers. */ | |
667 | size = data_len + 15; | |
668 | for (x = 0; x < numbuffs; x++) { | |
669 | if (!(skb = dev_alloc_skb(size))) { | |
670 | if (netif_msg_hw(lp)) | |
671 | printk(KERN_DEBUG | |
672 | "%s: Cannot allocate skb at line: %d!\n", | |
673 | dev->name, __LINE__); | |
674 | goto clean_up; | |
675 | } else { | |
676 | packet = skb->data; | |
677 | skb_put(skb, size); /* create space for data */ | |
678 | lp->tx_skbuff[x] = skb; | |
679 | lp->tx_ring[x].length = le16_to_cpu(-skb->len); | |
680 | lp->tx_ring[x].misc = 0; | |
681 | ||
682 | /* put DA and SA into the skb */ | |
683 | for (i = 0; i < 6; i++) | |
684 | *packet++ = dev->dev_addr[i]; | |
685 | for (i = 0; i < 6; i++) | |
686 | *packet++ = dev->dev_addr[i]; | |
687 | /* type */ | |
688 | *packet++ = 0x08; | |
689 | *packet++ = 0x06; | |
690 | /* packet number */ | |
691 | *packet++ = x; | |
692 | /* fill packet with data */ | |
693 | for (i = 0; i < data_len; i++) | |
694 | *packet++ = i; | |
695 | ||
696 | lp->tx_dma_addr[x] = | |
697 | pci_map_single(lp->pci_dev, skb->data, skb->len, | |
698 | PCI_DMA_TODEVICE); | |
699 | lp->tx_ring[x].base = | |
700 | (u32) le32_to_cpu(lp->tx_dma_addr[x]); | |
701 | wmb(); /* Make sure owner changes after all others are visible */ | |
702 | lp->tx_ring[x].status = le16_to_cpu(status); | |
703 | } | |
1da177e4 | 704 | } |
1da177e4 | 705 | |
4a5e8e29 JG |
706 | x = a->read_bcr(ioaddr, 32); /* set internal loopback in BSR32 */ |
707 | x = x | 0x0002; | |
708 | a->write_bcr(ioaddr, 32, x); | |
709 | ||
710 | lp->a.write_csr(ioaddr, 15, 0x0044); /* set int loopback in CSR15 */ | |
711 | ||
712 | teststatus = le16_to_cpu(0x8000); | |
713 | lp->a.write_csr(ioaddr, 0, 0x0002); /* Set STRT bit */ | |
714 | ||
715 | /* Check status of descriptors */ | |
716 | for (x = 0; x < numbuffs; x++) { | |
717 | ticks = 0; | |
718 | rmb(); | |
719 | while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) { | |
720 | spin_unlock_irqrestore(&lp->lock, flags); | |
721 | mdelay(1); | |
722 | spin_lock_irqsave(&lp->lock, flags); | |
723 | rmb(); | |
724 | ticks++; | |
725 | } | |
726 | if (ticks == 200) { | |
727 | if (netif_msg_hw(lp)) | |
728 | printk("%s: Desc %d failed to reset!\n", | |
729 | dev->name, x); | |
730 | break; | |
731 | } | |
732 | } | |
733 | ||
734 | lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */ | |
735 | wmb(); | |
736 | if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) { | |
737 | printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name); | |
738 | ||
739 | for (x = 0; x < numbuffs; x++) { | |
740 | printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x); | |
741 | skb = lp->rx_skbuff[x]; | |
742 | for (i = 0; i < size; i++) { | |
743 | printk("%02x ", *(skb->data + i)); | |
744 | } | |
745 | printk("\n"); | |
746 | } | |
747 | } | |
1da177e4 | 748 | |
4a5e8e29 JG |
749 | x = 0; |
750 | rc = 0; | |
751 | while (x < numbuffs && !rc) { | |
752 | skb = lp->rx_skbuff[x]; | |
753 | packet = lp->tx_skbuff[x]->data; | |
754 | for (i = 0; i < size; i++) { | |
755 | if (*(skb->data + i) != packet[i]) { | |
756 | if (netif_msg_hw(lp)) | |
757 | printk(KERN_DEBUG | |
758 | "%s: Error in compare! %2x - %02x %02x\n", | |
759 | dev->name, i, *(skb->data + i), | |
760 | packet[i]); | |
761 | rc = 1; | |
762 | break; | |
763 | } | |
764 | } | |
765 | x++; | |
766 | } | |
767 | if (!rc) { | |
768 | *data1 = 0; | |
769 | } | |
1da177e4 | 770 | |
4a5e8e29 JG |
771 | clean_up: |
772 | pcnet32_purge_tx_ring(dev); | |
773 | x = a->read_csr(ioaddr, 15) & 0xFFFF; | |
774 | a->write_csr(ioaddr, 15, (x & ~0x0044)); /* reset bits 6 and 2 */ | |
1da177e4 | 775 | |
4a5e8e29 JG |
776 | x = a->read_bcr(ioaddr, 32); /* reset internal loopback */ |
777 | x = x & ~0x0002; | |
778 | a->write_bcr(ioaddr, 32, x); | |
1da177e4 | 779 | |
4a5e8e29 JG |
780 | spin_unlock_irqrestore(&lp->lock, flags); |
781 | ||
782 | if (netif_running(dev)) { | |
783 | pcnet32_open(dev); | |
784 | } else { | |
785 | lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */ | |
786 | } | |
787 | ||
788 | return (rc); | |
789 | } /* end pcnet32_loopback_test */ | |
1da177e4 LT |
790 | |
791 | static void pcnet32_led_blink_callback(struct net_device *dev) | |
792 | { | |
4a5e8e29 JG |
793 | struct pcnet32_private *lp = dev->priv; |
794 | struct pcnet32_access *a = &lp->a; | |
795 | ulong ioaddr = dev->base_addr; | |
796 | unsigned long flags; | |
797 | int i; | |
798 | ||
799 | spin_lock_irqsave(&lp->lock, flags); | |
800 | for (i = 4; i < 8; i++) { | |
801 | a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000); | |
802 | } | |
803 | spin_unlock_irqrestore(&lp->lock, flags); | |
804 | ||
805 | mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT); | |
1da177e4 LT |
806 | } |
807 | ||
808 | static int pcnet32_phys_id(struct net_device *dev, u32 data) | |
809 | { | |
4a5e8e29 JG |
810 | struct pcnet32_private *lp = dev->priv; |
811 | struct pcnet32_access *a = &lp->a; | |
812 | ulong ioaddr = dev->base_addr; | |
813 | unsigned long flags; | |
814 | int i, regs[4]; | |
815 | ||
816 | if (!lp->blink_timer.function) { | |
817 | init_timer(&lp->blink_timer); | |
818 | lp->blink_timer.function = (void *)pcnet32_led_blink_callback; | |
819 | lp->blink_timer.data = (unsigned long)dev; | |
820 | } | |
821 | ||
822 | /* Save the current value of the bcrs */ | |
823 | spin_lock_irqsave(&lp->lock, flags); | |
824 | for (i = 4; i < 8; i++) { | |
825 | regs[i - 4] = a->read_bcr(ioaddr, i); | |
826 | } | |
827 | spin_unlock_irqrestore(&lp->lock, flags); | |
828 | ||
829 | mod_timer(&lp->blink_timer, jiffies); | |
830 | set_current_state(TASK_INTERRUPTIBLE); | |
831 | ||
832 | if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))) | |
833 | data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ); | |
834 | ||
835 | msleep_interruptible(data * 1000); | |
836 | del_timer_sync(&lp->blink_timer); | |
837 | ||
838 | /* Restore the original value of the bcrs */ | |
839 | spin_lock_irqsave(&lp->lock, flags); | |
840 | for (i = 4; i < 8; i++) { | |
841 | a->write_bcr(ioaddr, i, regs[i - 4]); | |
842 | } | |
843 | spin_unlock_irqrestore(&lp->lock, flags); | |
844 | ||
845 | return 0; | |
1da177e4 LT |
846 | } |
847 | ||
ac62ef04 DF |
848 | #define PCNET32_REGS_PER_PHY 32 |
849 | #define PCNET32_MAX_PHYS 32 | |
1da177e4 LT |
850 | static int pcnet32_get_regs_len(struct net_device *dev) |
851 | { | |
4a5e8e29 JG |
852 | struct pcnet32_private *lp = dev->priv; |
853 | int j = lp->phycount * PCNET32_REGS_PER_PHY; | |
ac62ef04 | 854 | |
4a5e8e29 | 855 | return ((PCNET32_NUM_REGS + j) * sizeof(u16)); |
1da177e4 LT |
856 | } |
857 | ||
858 | static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
4a5e8e29 | 859 | void *ptr) |
1da177e4 | 860 | { |
4a5e8e29 JG |
861 | int i, csr0; |
862 | u16 *buff = ptr; | |
863 | struct pcnet32_private *lp = dev->priv; | |
864 | struct pcnet32_access *a = &lp->a; | |
865 | ulong ioaddr = dev->base_addr; | |
866 | int ticks; | |
867 | unsigned long flags; | |
868 | ||
869 | spin_lock_irqsave(&lp->lock, flags); | |
870 | ||
871 | csr0 = a->read_csr(ioaddr, 0); | |
872 | if (!(csr0 & 0x0004)) { /* If not stopped */ | |
873 | /* set SUSPEND (SPND) - CSR5 bit 0 */ | |
874 | a->write_csr(ioaddr, 5, 0x0001); | |
875 | ||
876 | /* poll waiting for bit to be set */ | |
877 | ticks = 0; | |
878 | while (!(a->read_csr(ioaddr, 5) & 0x0001)) { | |
879 | spin_unlock_irqrestore(&lp->lock, flags); | |
880 | mdelay(1); | |
881 | spin_lock_irqsave(&lp->lock, flags); | |
882 | ticks++; | |
883 | if (ticks > 200) { | |
884 | if (netif_msg_hw(lp)) | |
885 | printk(KERN_DEBUG | |
886 | "%s: Error getting into suspend!\n", | |
887 | dev->name); | |
888 | break; | |
889 | } | |
ac62ef04 | 890 | } |
1da177e4 | 891 | } |
1da177e4 | 892 | |
4a5e8e29 JG |
893 | /* read address PROM */ |
894 | for (i = 0; i < 16; i += 2) | |
895 | *buff++ = inw(ioaddr + i); | |
896 | ||
897 | /* read control and status registers */ | |
898 | for (i = 0; i < 90; i++) { | |
899 | *buff++ = a->read_csr(ioaddr, i); | |
900 | } | |
901 | ||
902 | *buff++ = a->read_csr(ioaddr, 112); | |
903 | *buff++ = a->read_csr(ioaddr, 114); | |
1da177e4 | 904 | |
4a5e8e29 JG |
905 | /* read bus configuration registers */ |
906 | for (i = 0; i < 30; i++) { | |
907 | *buff++ = a->read_bcr(ioaddr, i); | |
908 | } | |
909 | *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */ | |
910 | for (i = 31; i < 36; i++) { | |
911 | *buff++ = a->read_bcr(ioaddr, i); | |
912 | } | |
913 | ||
914 | /* read mii phy registers */ | |
915 | if (lp->mii) { | |
916 | int j; | |
917 | for (j = 0; j < PCNET32_MAX_PHYS; j++) { | |
918 | if (lp->phymask & (1 << j)) { | |
919 | for (i = 0; i < PCNET32_REGS_PER_PHY; i++) { | |
920 | lp->a.write_bcr(ioaddr, 33, | |
921 | (j << 5) | i); | |
922 | *buff++ = lp->a.read_bcr(ioaddr, 34); | |
923 | } | |
924 | } | |
925 | } | |
926 | } | |
927 | ||
928 | if (!(csr0 & 0x0004)) { /* If not stopped */ | |
929 | /* clear SUSPEND (SPND) - CSR5 bit 0 */ | |
930 | a->write_csr(ioaddr, 5, 0x0000); | |
931 | } | |
932 | ||
933 | spin_unlock_irqrestore(&lp->lock, flags); | |
1da177e4 LT |
934 | } |
935 | ||
936 | static struct ethtool_ops pcnet32_ethtool_ops = { | |
4a5e8e29 JG |
937 | .get_settings = pcnet32_get_settings, |
938 | .set_settings = pcnet32_set_settings, | |
939 | .get_drvinfo = pcnet32_get_drvinfo, | |
940 | .get_msglevel = pcnet32_get_msglevel, | |
941 | .set_msglevel = pcnet32_set_msglevel, | |
942 | .nway_reset = pcnet32_nway_reset, | |
943 | .get_link = pcnet32_get_link, | |
944 | .get_ringparam = pcnet32_get_ringparam, | |
945 | .set_ringparam = pcnet32_set_ringparam, | |
946 | .get_tx_csum = ethtool_op_get_tx_csum, | |
947 | .get_sg = ethtool_op_get_sg, | |
948 | .get_tso = ethtool_op_get_tso, | |
949 | .get_strings = pcnet32_get_strings, | |
950 | .self_test_count = pcnet32_self_test_count, | |
951 | .self_test = pcnet32_ethtool_test, | |
952 | .phys_id = pcnet32_phys_id, | |
953 | .get_regs_len = pcnet32_get_regs_len, | |
954 | .get_regs = pcnet32_get_regs, | |
955 | .get_perm_addr = ethtool_op_get_perm_addr, | |
1da177e4 LT |
956 | }; |
957 | ||
958 | /* only probes for non-PCI devices, the rest are handled by | |
959 | * pci_register_driver via pcnet32_probe_pci */ | |
960 | ||
4a5e8e29 | 961 | static void __devinit pcnet32_probe_vlbus(void) |
1da177e4 | 962 | { |
4a5e8e29 JG |
963 | unsigned int *port, ioaddr; |
964 | ||
965 | /* search for PCnet32 VLB cards at known addresses */ | |
966 | for (port = pcnet32_portlist; (ioaddr = *port); port++) { | |
967 | if (request_region | |
968 | (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) { | |
969 | /* check if there is really a pcnet chip on that ioaddr */ | |
970 | if ((inb(ioaddr + 14) == 0x57) | |
971 | && (inb(ioaddr + 15) == 0x57)) { | |
972 | pcnet32_probe1(ioaddr, 0, NULL); | |
973 | } else { | |
974 | release_region(ioaddr, PCNET32_TOTAL_SIZE); | |
975 | } | |
976 | } | |
977 | } | |
1da177e4 LT |
978 | } |
979 | ||
1da177e4 LT |
980 | static int __devinit |
981 | pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent) | |
982 | { | |
4a5e8e29 JG |
983 | unsigned long ioaddr; |
984 | int err; | |
985 | ||
986 | err = pci_enable_device(pdev); | |
987 | if (err < 0) { | |
988 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
989 | printk(KERN_ERR PFX | |
990 | "failed to enable device -- err=%d\n", err); | |
991 | return err; | |
992 | } | |
993 | pci_set_master(pdev); | |
994 | ||
995 | ioaddr = pci_resource_start(pdev, 0); | |
996 | if (!ioaddr) { | |
997 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
998 | printk(KERN_ERR PFX | |
999 | "card has no PCI IO resources, aborting\n"); | |
1000 | return -ENODEV; | |
1001 | } | |
1da177e4 | 1002 | |
4a5e8e29 JG |
1003 | if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) { |
1004 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1005 | printk(KERN_ERR PFX | |
1006 | "architecture does not support 32bit PCI busmaster DMA\n"); | |
1007 | return -ENODEV; | |
1008 | } | |
1009 | if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") == | |
1010 | NULL) { | |
1011 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1012 | printk(KERN_ERR PFX | |
1013 | "io address range already allocated\n"); | |
1014 | return -EBUSY; | |
1015 | } | |
1da177e4 | 1016 | |
4a5e8e29 JG |
1017 | err = pcnet32_probe1(ioaddr, 1, pdev); |
1018 | if (err < 0) { | |
1019 | pci_disable_device(pdev); | |
1020 | } | |
1021 | return err; | |
1da177e4 LT |
1022 | } |
1023 | ||
1da177e4 LT |
1024 | /* pcnet32_probe1 |
1025 | * Called from both pcnet32_probe_vlbus and pcnet_probe_pci. | |
1026 | * pdev will be NULL when called from pcnet32_probe_vlbus. | |
1027 | */ | |
1028 | static int __devinit | |
1029 | pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev) | |
1030 | { | |
4a5e8e29 JG |
1031 | struct pcnet32_private *lp; |
1032 | dma_addr_t lp_dma_addr; | |
1033 | int i, media; | |
1034 | int fdx, mii, fset, dxsuflo; | |
1035 | int chip_version; | |
1036 | char *chipname; | |
1037 | struct net_device *dev; | |
1038 | struct pcnet32_access *a = NULL; | |
1039 | u8 promaddr[6]; | |
1040 | int ret = -ENODEV; | |
1041 | ||
1042 | /* reset the chip */ | |
1043 | pcnet32_wio_reset(ioaddr); | |
1044 | ||
1045 | /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */ | |
1046 | if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) { | |
1047 | a = &pcnet32_wio; | |
1048 | } else { | |
1049 | pcnet32_dwio_reset(ioaddr); | |
1050 | if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 | |
1051 | && pcnet32_dwio_check(ioaddr)) { | |
1052 | a = &pcnet32_dwio; | |
1053 | } else | |
1054 | goto err_release_region; | |
1055 | } | |
1056 | ||
1057 | chip_version = | |
1058 | a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16); | |
1059 | if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW)) | |
1060 | printk(KERN_INFO " PCnet chip version is %#x.\n", | |
1061 | chip_version); | |
1062 | if ((chip_version & 0xfff) != 0x003) { | |
1063 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1064 | printk(KERN_INFO PFX "Unsupported chip version.\n"); | |
1065 | goto err_release_region; | |
1066 | } | |
1067 | ||
1068 | /* initialize variables */ | |
1069 | fdx = mii = fset = dxsuflo = 0; | |
1070 | chip_version = (chip_version >> 12) & 0xffff; | |
1071 | ||
1072 | switch (chip_version) { | |
1073 | case 0x2420: | |
1074 | chipname = "PCnet/PCI 79C970"; /* PCI */ | |
1075 | break; | |
1076 | case 0x2430: | |
1077 | if (shared) | |
1078 | chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */ | |
1079 | else | |
1080 | chipname = "PCnet/32 79C965"; /* 486/VL bus */ | |
1081 | break; | |
1082 | case 0x2621: | |
1083 | chipname = "PCnet/PCI II 79C970A"; /* PCI */ | |
1084 | fdx = 1; | |
1085 | break; | |
1086 | case 0x2623: | |
1087 | chipname = "PCnet/FAST 79C971"; /* PCI */ | |
1088 | fdx = 1; | |
1089 | mii = 1; | |
1090 | fset = 1; | |
1091 | break; | |
1092 | case 0x2624: | |
1093 | chipname = "PCnet/FAST+ 79C972"; /* PCI */ | |
1094 | fdx = 1; | |
1095 | mii = 1; | |
1096 | fset = 1; | |
1097 | break; | |
1098 | case 0x2625: | |
1099 | chipname = "PCnet/FAST III 79C973"; /* PCI */ | |
1100 | fdx = 1; | |
1101 | mii = 1; | |
1102 | break; | |
1103 | case 0x2626: | |
1104 | chipname = "PCnet/Home 79C978"; /* PCI */ | |
1105 | fdx = 1; | |
1106 | /* | |
1107 | * This is based on specs published at www.amd.com. This section | |
1108 | * assumes that a card with a 79C978 wants to go into standard | |
1109 | * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode, | |
1110 | * and the module option homepna=1 can select this instead. | |
1111 | */ | |
1112 | media = a->read_bcr(ioaddr, 49); | |
1113 | media &= ~3; /* default to 10Mb ethernet */ | |
1114 | if (cards_found < MAX_UNITS && homepna[cards_found]) | |
1115 | media |= 1; /* switch to home wiring mode */ | |
1116 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1117 | printk(KERN_DEBUG PFX "media set to %sMbit mode.\n", | |
1118 | (media & 1) ? "1" : "10"); | |
1119 | a->write_bcr(ioaddr, 49, media); | |
1120 | break; | |
1121 | case 0x2627: | |
1122 | chipname = "PCnet/FAST III 79C975"; /* PCI */ | |
1123 | fdx = 1; | |
1124 | mii = 1; | |
1125 | break; | |
1126 | case 0x2628: | |
1127 | chipname = "PCnet/PRO 79C976"; | |
1128 | fdx = 1; | |
1129 | mii = 1; | |
1130 | break; | |
1131 | default: | |
1132 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1133 | printk(KERN_INFO PFX | |
1134 | "PCnet version %#x, no PCnet32 chip.\n", | |
1135 | chip_version); | |
1136 | goto err_release_region; | |
1137 | } | |
1138 | ||
1da177e4 | 1139 | /* |
4a5e8e29 JG |
1140 | * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit |
1141 | * starting until the packet is loaded. Strike one for reliability, lose | |
1142 | * one for latency - although on PCI this isnt a big loss. Older chips | |
1143 | * have FIFO's smaller than a packet, so you can't do this. | |
1144 | * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn. | |
1da177e4 | 1145 | */ |
4a5e8e29 JG |
1146 | |
1147 | if (fset) { | |
1148 | a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860)); | |
1149 | a->write_csr(ioaddr, 80, | |
1150 | (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00); | |
1151 | dxsuflo = 1; | |
1152 | } | |
1153 | ||
1154 | dev = alloc_etherdev(0); | |
1155 | if (!dev) { | |
1156 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1157 | printk(KERN_ERR PFX "Memory allocation failed.\n"); | |
1158 | ret = -ENOMEM; | |
1159 | goto err_release_region; | |
1160 | } | |
1161 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1162 | ||
1da177e4 | 1163 | if (pcnet32_debug & NETIF_MSG_PROBE) |
4a5e8e29 JG |
1164 | printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr); |
1165 | ||
1166 | /* In most chips, after a chip reset, the ethernet address is read from the | |
1167 | * station address PROM at the base address and programmed into the | |
1168 | * "Physical Address Registers" CSR12-14. | |
1169 | * As a precautionary measure, we read the PROM values and complain if | |
1170 | * they disagree with the CSRs. Either way, we use the CSR values, and | |
1171 | * double check that they are valid. | |
1172 | */ | |
1173 | for (i = 0; i < 3; i++) { | |
1174 | unsigned int val; | |
1175 | val = a->read_csr(ioaddr, i + 12) & 0x0ffff; | |
1176 | /* There may be endianness issues here. */ | |
1177 | dev->dev_addr[2 * i] = val & 0x0ff; | |
1178 | dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff; | |
1179 | } | |
1180 | ||
1181 | /* read PROM address and compare with CSR address */ | |
1da177e4 | 1182 | for (i = 0; i < 6; i++) |
4a5e8e29 JG |
1183 | promaddr[i] = inb(ioaddr + i); |
1184 | ||
1185 | if (memcmp(promaddr, dev->dev_addr, 6) | |
1186 | || !is_valid_ether_addr(dev->dev_addr)) { | |
1187 | if (is_valid_ether_addr(promaddr)) { | |
1188 | if (pcnet32_debug & NETIF_MSG_PROBE) { | |
1189 | printk(" warning: CSR address invalid,\n"); | |
1190 | printk(KERN_INFO | |
1191 | " using instead PROM address of"); | |
1192 | } | |
1193 | memcpy(dev->dev_addr, promaddr, 6); | |
1194 | } | |
1195 | } | |
1196 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | |
1197 | ||
1198 | /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */ | |
1199 | if (!is_valid_ether_addr(dev->perm_addr)) | |
1200 | memset(dev->dev_addr, 0, sizeof(dev->dev_addr)); | |
1201 | ||
1202 | if (pcnet32_debug & NETIF_MSG_PROBE) { | |
1203 | for (i = 0; i < 6; i++) | |
1204 | printk(" %2.2x", dev->dev_addr[i]); | |
1205 | ||
1206 | /* Version 0x2623 and 0x2624 */ | |
1207 | if (((chip_version + 1) & 0xfffe) == 0x2624) { | |
1208 | i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */ | |
1209 | printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i); | |
1210 | switch (i >> 10) { | |
1211 | case 0: | |
1212 | printk(" 20 bytes,"); | |
1213 | break; | |
1214 | case 1: | |
1215 | printk(" 64 bytes,"); | |
1216 | break; | |
1217 | case 2: | |
1218 | printk(" 128 bytes,"); | |
1219 | break; | |
1220 | case 3: | |
1221 | printk("~220 bytes,"); | |
1222 | break; | |
1223 | } | |
1224 | i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */ | |
1225 | printk(" BCR18(%x):", i & 0xffff); | |
1226 | if (i & (1 << 5)) | |
1227 | printk("BurstWrEn "); | |
1228 | if (i & (1 << 6)) | |
1229 | printk("BurstRdEn "); | |
1230 | if (i & (1 << 7)) | |
1231 | printk("DWordIO "); | |
1232 | if (i & (1 << 11)) | |
1233 | printk("NoUFlow "); | |
1234 | i = a->read_bcr(ioaddr, 25); | |
1235 | printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8); | |
1236 | i = a->read_bcr(ioaddr, 26); | |
1237 | printk(" SRAM_BND=0x%04x,", i << 8); | |
1238 | i = a->read_bcr(ioaddr, 27); | |
1239 | if (i & (1 << 14)) | |
1240 | printk("LowLatRx"); | |
1241 | } | |
1242 | } | |
1243 | ||
1244 | dev->base_addr = ioaddr; | |
1245 | /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */ | |
1246 | if ((lp = | |
1247 | pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) { | |
1248 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1249 | printk(KERN_ERR PFX | |
1250 | "Consistent memory allocation failed.\n"); | |
1251 | ret = -ENOMEM; | |
1252 | goto err_free_netdev; | |
1253 | } | |
1254 | ||
1255 | memset(lp, 0, sizeof(*lp)); | |
1256 | lp->dma_addr = lp_dma_addr; | |
1257 | lp->pci_dev = pdev; | |
1258 | ||
1259 | spin_lock_init(&lp->lock); | |
1260 | ||
1261 | SET_MODULE_OWNER(dev); | |
1262 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1263 | dev->priv = lp; | |
1264 | lp->name = chipname; | |
1265 | lp->shared_irq = shared; | |
1266 | lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */ | |
1267 | lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */ | |
1268 | lp->tx_mod_mask = lp->tx_ring_size - 1; | |
1269 | lp->rx_mod_mask = lp->rx_ring_size - 1; | |
1270 | lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12); | |
1271 | lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4); | |
1272 | lp->mii_if.full_duplex = fdx; | |
1273 | lp->mii_if.phy_id_mask = 0x1f; | |
1274 | lp->mii_if.reg_num_mask = 0x1f; | |
1275 | lp->dxsuflo = dxsuflo; | |
1276 | lp->mii = mii; | |
1277 | lp->msg_enable = pcnet32_debug; | |
1278 | if ((cards_found >= MAX_UNITS) | |
1279 | || (options[cards_found] > sizeof(options_mapping))) | |
1280 | lp->options = PCNET32_PORT_ASEL; | |
1281 | else | |
1282 | lp->options = options_mapping[options[cards_found]]; | |
1283 | lp->mii_if.dev = dev; | |
1284 | lp->mii_if.mdio_read = mdio_read; | |
1285 | lp->mii_if.mdio_write = mdio_write; | |
1286 | ||
1287 | if (fdx && !(lp->options & PCNET32_PORT_ASEL) && | |
1288 | ((cards_found >= MAX_UNITS) || full_duplex[cards_found])) | |
1289 | lp->options |= PCNET32_PORT_FD; | |
1290 | ||
1291 | if (!a) { | |
1292 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1293 | printk(KERN_ERR PFX "No access methods\n"); | |
1294 | ret = -ENODEV; | |
1295 | goto err_free_consistent; | |
1296 | } | |
1297 | lp->a = *a; | |
1298 | ||
1299 | /* prior to register_netdev, dev->name is not yet correct */ | |
1300 | if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) { | |
1301 | ret = -ENOMEM; | |
1302 | goto err_free_ring; | |
1303 | } | |
1304 | /* detect special T1/E1 WAN card by checking for MAC address */ | |
1305 | if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 | |
1da177e4 | 1306 | && dev->dev_addr[2] == 0x75) |
4a5e8e29 | 1307 | lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI; |
1da177e4 | 1308 | |
4a5e8e29 JG |
1309 | lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */ |
1310 | lp->init_block.tlen_rlen = | |
1311 | le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits); | |
1312 | for (i = 0; i < 6; i++) | |
1313 | lp->init_block.phys_addr[i] = dev->dev_addr[i]; | |
1314 | lp->init_block.filter[0] = 0x00000000; | |
1315 | lp->init_block.filter[1] = 0x00000000; | |
1316 | lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr); | |
1317 | lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr); | |
1318 | ||
1319 | /* switch pcnet32 to 32bit mode */ | |
1320 | a->write_bcr(ioaddr, 20, 2); | |
1321 | ||
1322 | a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private, | |
1323 | init_block)) & 0xffff); | |
1324 | a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private, | |
1325 | init_block)) >> 16); | |
1326 | ||
1327 | if (pdev) { /* use the IRQ provided by PCI */ | |
1328 | dev->irq = pdev->irq; | |
1329 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1330 | printk(" assigned IRQ %d.\n", dev->irq); | |
1331 | } else { | |
1332 | unsigned long irq_mask = probe_irq_on(); | |
1333 | ||
1334 | /* | |
1335 | * To auto-IRQ we enable the initialization-done and DMA error | |
1336 | * interrupts. For ISA boards we get a DMA error, but VLB and PCI | |
1337 | * boards will work. | |
1338 | */ | |
1339 | /* Trigger an initialization just for the interrupt. */ | |
1340 | a->write_csr(ioaddr, 0, 0x41); | |
1341 | mdelay(1); | |
1342 | ||
1343 | dev->irq = probe_irq_off(irq_mask); | |
1344 | if (!dev->irq) { | |
1345 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1346 | printk(", failed to detect IRQ line.\n"); | |
1347 | ret = -ENODEV; | |
1348 | goto err_free_ring; | |
1349 | } | |
1350 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1351 | printk(", probed IRQ %d.\n", dev->irq); | |
1352 | } | |
1da177e4 | 1353 | |
4a5e8e29 JG |
1354 | /* Set the mii phy_id so that we can query the link state */ |
1355 | if (lp->mii) { | |
1356 | /* lp->phycount and lp->phymask are set to 0 by memset above */ | |
1357 | ||
1358 | lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f; | |
1359 | /* scan for PHYs */ | |
1360 | for (i = 0; i < PCNET32_MAX_PHYS; i++) { | |
1361 | unsigned short id1, id2; | |
1362 | ||
1363 | id1 = mdio_read(dev, i, MII_PHYSID1); | |
1364 | if (id1 == 0xffff) | |
1365 | continue; | |
1366 | id2 = mdio_read(dev, i, MII_PHYSID2); | |
1367 | if (id2 == 0xffff) | |
1368 | continue; | |
1369 | if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624) | |
1370 | continue; /* 79C971 & 79C972 have phantom phy at id 31 */ | |
1371 | lp->phycount++; | |
1372 | lp->phymask |= (1 << i); | |
1373 | lp->mii_if.phy_id = i; | |
1374 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1375 | printk(KERN_INFO PFX | |
1376 | "Found PHY %04x:%04x at address %d.\n", | |
1377 | id1, id2, i); | |
1378 | } | |
1379 | lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5); | |
1380 | if (lp->phycount > 1) { | |
1381 | lp->options |= PCNET32_PORT_MII; | |
1382 | } | |
1da177e4 | 1383 | } |
4a5e8e29 JG |
1384 | |
1385 | init_timer(&lp->watchdog_timer); | |
1386 | lp->watchdog_timer.data = (unsigned long)dev; | |
1387 | lp->watchdog_timer.function = (void *)&pcnet32_watchdog; | |
1388 | ||
1389 | /* The PCNET32-specific entries in the device structure. */ | |
1390 | dev->open = &pcnet32_open; | |
1391 | dev->hard_start_xmit = &pcnet32_start_xmit; | |
1392 | dev->stop = &pcnet32_close; | |
1393 | dev->get_stats = &pcnet32_get_stats; | |
1394 | dev->set_multicast_list = &pcnet32_set_multicast_list; | |
1395 | dev->do_ioctl = &pcnet32_ioctl; | |
1396 | dev->ethtool_ops = &pcnet32_ethtool_ops; | |
1397 | dev->tx_timeout = pcnet32_tx_timeout; | |
1398 | dev->watchdog_timeo = (5 * HZ); | |
1da177e4 LT |
1399 | |
1400 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
4a5e8e29 | 1401 | dev->poll_controller = pcnet32_poll_controller; |
1da177e4 LT |
1402 | #endif |
1403 | ||
4a5e8e29 JG |
1404 | /* Fill in the generic fields of the device structure. */ |
1405 | if (register_netdev(dev)) | |
1406 | goto err_free_ring; | |
1407 | ||
1408 | if (pdev) { | |
1409 | pci_set_drvdata(pdev, dev); | |
1410 | } else { | |
1411 | lp->next = pcnet32_dev; | |
1412 | pcnet32_dev = dev; | |
1413 | } | |
1414 | ||
1415 | if (pcnet32_debug & NETIF_MSG_PROBE) | |
1416 | printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name); | |
1417 | cards_found++; | |
1418 | ||
1419 | /* enable LED writes */ | |
1420 | a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000); | |
1da177e4 | 1421 | |
4a5e8e29 JG |
1422 | return 0; |
1423 | ||
1424 | err_free_ring: | |
1425 | pcnet32_free_ring(dev); | |
1426 | err_free_consistent: | |
1427 | pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr); | |
1428 | err_free_netdev: | |
1429 | free_netdev(dev); | |
1430 | err_release_region: | |
1431 | release_region(ioaddr, PCNET32_TOTAL_SIZE); | |
1432 | return ret; | |
1433 | } | |
1da177e4 | 1434 | |
a88c844c DF |
1435 | /* if any allocation fails, caller must also call pcnet32_free_ring */ |
1436 | static int pcnet32_alloc_ring(struct net_device *dev, char *name) | |
eabf0415 | 1437 | { |
4a5e8e29 | 1438 | struct pcnet32_private *lp = dev->priv; |
eabf0415 | 1439 | |
4a5e8e29 JG |
1440 | lp->tx_ring = pci_alloc_consistent(lp->pci_dev, |
1441 | sizeof(struct pcnet32_tx_head) * | |
1442 | lp->tx_ring_size, | |
1443 | &lp->tx_ring_dma_addr); | |
1444 | if (lp->tx_ring == NULL) { | |
1445 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1446 | printk("\n" KERN_ERR PFX | |
1447 | "%s: Consistent memory allocation failed.\n", | |
1448 | name); | |
1449 | return -ENOMEM; | |
1450 | } | |
eabf0415 | 1451 | |
4a5e8e29 JG |
1452 | lp->rx_ring = pci_alloc_consistent(lp->pci_dev, |
1453 | sizeof(struct pcnet32_rx_head) * | |
1454 | lp->rx_ring_size, | |
1455 | &lp->rx_ring_dma_addr); | |
1456 | if (lp->rx_ring == NULL) { | |
1457 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1458 | printk("\n" KERN_ERR PFX | |
1459 | "%s: Consistent memory allocation failed.\n", | |
1460 | name); | |
1461 | return -ENOMEM; | |
1462 | } | |
eabf0415 | 1463 | |
4a5e8e29 JG |
1464 | lp->tx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->tx_ring_size, |
1465 | GFP_ATOMIC); | |
1466 | if (!lp->tx_dma_addr) { | |
1467 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1468 | printk("\n" KERN_ERR PFX | |
1469 | "%s: Memory allocation failed.\n", name); | |
1470 | return -ENOMEM; | |
1471 | } | |
1472 | memset(lp->tx_dma_addr, 0, sizeof(dma_addr_t) * lp->tx_ring_size); | |
1473 | ||
1474 | lp->rx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->rx_ring_size, | |
1475 | GFP_ATOMIC); | |
1476 | if (!lp->rx_dma_addr) { | |
1477 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1478 | printk("\n" KERN_ERR PFX | |
1479 | "%s: Memory allocation failed.\n", name); | |
1480 | return -ENOMEM; | |
1481 | } | |
1482 | memset(lp->rx_dma_addr, 0, sizeof(dma_addr_t) * lp->rx_ring_size); | |
1483 | ||
1484 | lp->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->tx_ring_size, | |
1485 | GFP_ATOMIC); | |
1486 | if (!lp->tx_skbuff) { | |
1487 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1488 | printk("\n" KERN_ERR PFX | |
1489 | "%s: Memory allocation failed.\n", name); | |
1490 | return -ENOMEM; | |
1491 | } | |
1492 | memset(lp->tx_skbuff, 0, sizeof(struct sk_buff *) * lp->tx_ring_size); | |
1493 | ||
1494 | lp->rx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->rx_ring_size, | |
1495 | GFP_ATOMIC); | |
1496 | if (!lp->rx_skbuff) { | |
1497 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1498 | printk("\n" KERN_ERR PFX | |
1499 | "%s: Memory allocation failed.\n", name); | |
1500 | return -ENOMEM; | |
1501 | } | |
1502 | memset(lp->rx_skbuff, 0, sizeof(struct sk_buff *) * lp->rx_ring_size); | |
1503 | ||
1504 | return 0; | |
1505 | } | |
eabf0415 HWL |
1506 | |
1507 | static void pcnet32_free_ring(struct net_device *dev) | |
1508 | { | |
4a5e8e29 | 1509 | struct pcnet32_private *lp = dev->priv; |
eabf0415 | 1510 | |
4a5e8e29 JG |
1511 | kfree(lp->tx_skbuff); |
1512 | lp->tx_skbuff = NULL; | |
eabf0415 | 1513 | |
4a5e8e29 JG |
1514 | kfree(lp->rx_skbuff); |
1515 | lp->rx_skbuff = NULL; | |
eabf0415 | 1516 | |
4a5e8e29 JG |
1517 | kfree(lp->tx_dma_addr); |
1518 | lp->tx_dma_addr = NULL; | |
eabf0415 | 1519 | |
4a5e8e29 JG |
1520 | kfree(lp->rx_dma_addr); |
1521 | lp->rx_dma_addr = NULL; | |
eabf0415 | 1522 | |
4a5e8e29 JG |
1523 | if (lp->tx_ring) { |
1524 | pci_free_consistent(lp->pci_dev, | |
1525 | sizeof(struct pcnet32_tx_head) * | |
1526 | lp->tx_ring_size, lp->tx_ring, | |
1527 | lp->tx_ring_dma_addr); | |
1528 | lp->tx_ring = NULL; | |
1529 | } | |
eabf0415 | 1530 | |
4a5e8e29 JG |
1531 | if (lp->rx_ring) { |
1532 | pci_free_consistent(lp->pci_dev, | |
1533 | sizeof(struct pcnet32_rx_head) * | |
1534 | lp->rx_ring_size, lp->rx_ring, | |
1535 | lp->rx_ring_dma_addr); | |
1536 | lp->rx_ring = NULL; | |
1537 | } | |
eabf0415 HWL |
1538 | } |
1539 | ||
4a5e8e29 | 1540 | static int pcnet32_open(struct net_device *dev) |
1da177e4 | 1541 | { |
4a5e8e29 JG |
1542 | struct pcnet32_private *lp = dev->priv; |
1543 | unsigned long ioaddr = dev->base_addr; | |
1544 | u16 val; | |
1545 | int i; | |
1546 | int rc; | |
1547 | unsigned long flags; | |
1548 | ||
1549 | if (request_irq(dev->irq, &pcnet32_interrupt, | |
1550 | lp->shared_irq ? SA_SHIRQ : 0, dev->name, | |
1551 | (void *)dev)) { | |
1552 | return -EAGAIN; | |
1553 | } | |
1554 | ||
1555 | spin_lock_irqsave(&lp->lock, flags); | |
1556 | /* Check for a valid station address */ | |
1557 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
1558 | rc = -EINVAL; | |
1559 | goto err_free_irq; | |
1560 | } | |
1561 | ||
1562 | /* Reset the PCNET32 */ | |
1563 | lp->a.reset(ioaddr); | |
1564 | ||
1565 | /* switch pcnet32 to 32bit mode */ | |
1566 | lp->a.write_bcr(ioaddr, 20, 2); | |
1567 | ||
1568 | if (netif_msg_ifup(lp)) | |
1569 | printk(KERN_DEBUG | |
1570 | "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n", | |
1571 | dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr), | |
1572 | (u32) (lp->rx_ring_dma_addr), | |
1573 | (u32) (lp->dma_addr + | |
1574 | offsetof(struct pcnet32_private, init_block))); | |
1575 | ||
1576 | /* set/reset autoselect bit */ | |
1577 | val = lp->a.read_bcr(ioaddr, 2) & ~2; | |
1578 | if (lp->options & PCNET32_PORT_ASEL) | |
1da177e4 | 1579 | val |= 2; |
4a5e8e29 JG |
1580 | lp->a.write_bcr(ioaddr, 2, val); |
1581 | ||
1582 | /* handle full duplex setting */ | |
1583 | if (lp->mii_if.full_duplex) { | |
1584 | val = lp->a.read_bcr(ioaddr, 9) & ~3; | |
1585 | if (lp->options & PCNET32_PORT_FD) { | |
1586 | val |= 1; | |
1587 | if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI)) | |
1588 | val |= 2; | |
1589 | } else if (lp->options & PCNET32_PORT_ASEL) { | |
1590 | /* workaround of xSeries250, turn on for 79C975 only */ | |
1591 | i = ((lp->a.read_csr(ioaddr, 88) | | |
1592 | (lp->a. | |
1593 | read_csr(ioaddr, 89) << 16)) >> 12) & 0xffff; | |
1594 | if (i == 0x2627) | |
1595 | val |= 3; | |
1596 | } | |
1597 | lp->a.write_bcr(ioaddr, 9, val); | |
1598 | } | |
1599 | ||
1600 | /* set/reset GPSI bit in test register */ | |
1601 | val = lp->a.read_csr(ioaddr, 124) & ~0x10; | |
1602 | if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI) | |
1603 | val |= 0x10; | |
1604 | lp->a.write_csr(ioaddr, 124, val); | |
1605 | ||
1606 | /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */ | |
1607 | if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT && | |
2964bbd7 DF |
1608 | (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX || |
1609 | lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) { | |
ac62ef04 | 1610 | if (lp->options & PCNET32_PORT_ASEL) { |
4a5e8e29 JG |
1611 | lp->options = PCNET32_PORT_FD | PCNET32_PORT_100; |
1612 | if (netif_msg_link(lp)) | |
1613 | printk(KERN_DEBUG | |
1614 | "%s: Setting 100Mb-Full Duplex.\n", | |
1615 | dev->name); | |
1616 | } | |
1617 | } | |
1618 | if (lp->phycount < 2) { | |
1619 | /* | |
1620 | * 24 Jun 2004 according AMD, in order to change the PHY, | |
1621 | * DANAS (or DISPM for 79C976) must be set; then select the speed, | |
1622 | * duplex, and/or enable auto negotiation, and clear DANAS | |
1623 | */ | |
1624 | if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) { | |
1625 | lp->a.write_bcr(ioaddr, 32, | |
1626 | lp->a.read_bcr(ioaddr, 32) | 0x0080); | |
1627 | /* disable Auto Negotiation, set 10Mpbs, HD */ | |
1628 | val = lp->a.read_bcr(ioaddr, 32) & ~0xb8; | |
1629 | if (lp->options & PCNET32_PORT_FD) | |
1630 | val |= 0x10; | |
1631 | if (lp->options & PCNET32_PORT_100) | |
1632 | val |= 0x08; | |
1633 | lp->a.write_bcr(ioaddr, 32, val); | |
1634 | } else { | |
1635 | if (lp->options & PCNET32_PORT_ASEL) { | |
1636 | lp->a.write_bcr(ioaddr, 32, | |
1637 | lp->a.read_bcr(ioaddr, | |
1638 | 32) | 0x0080); | |
1639 | /* enable auto negotiate, setup, disable fd */ | |
1640 | val = lp->a.read_bcr(ioaddr, 32) & ~0x98; | |
1641 | val |= 0x20; | |
1642 | lp->a.write_bcr(ioaddr, 32, val); | |
1643 | } | |
1644 | } | |
1645 | } else { | |
1646 | int first_phy = -1; | |
1647 | u16 bmcr; | |
1648 | u32 bcr9; | |
1649 | struct ethtool_cmd ecmd; | |
1650 | ||
1651 | /* | |
1652 | * There is really no good other way to handle multiple PHYs | |
1653 | * other than turning off all automatics | |
1654 | */ | |
1655 | val = lp->a.read_bcr(ioaddr, 2); | |
1656 | lp->a.write_bcr(ioaddr, 2, val & ~2); | |
1657 | val = lp->a.read_bcr(ioaddr, 32); | |
1658 | lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */ | |
1659 | ||
1660 | if (!(lp->options & PCNET32_PORT_ASEL)) { | |
1661 | /* setup ecmd */ | |
1662 | ecmd.port = PORT_MII; | |
1663 | ecmd.transceiver = XCVR_INTERNAL; | |
1664 | ecmd.autoneg = AUTONEG_DISABLE; | |
1665 | ecmd.speed = | |
1666 | lp-> | |
1667 | options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10; | |
1668 | bcr9 = lp->a.read_bcr(ioaddr, 9); | |
1669 | ||
1670 | if (lp->options & PCNET32_PORT_FD) { | |
1671 | ecmd.duplex = DUPLEX_FULL; | |
1672 | bcr9 |= (1 << 0); | |
1673 | } else { | |
1674 | ecmd.duplex = DUPLEX_HALF; | |
1675 | bcr9 |= ~(1 << 0); | |
1676 | } | |
1677 | lp->a.write_bcr(ioaddr, 9, bcr9); | |
ac62ef04 | 1678 | } |
4a5e8e29 JG |
1679 | |
1680 | for (i = 0; i < PCNET32_MAX_PHYS; i++) { | |
1681 | if (lp->phymask & (1 << i)) { | |
1682 | /* isolate all but the first PHY */ | |
1683 | bmcr = mdio_read(dev, i, MII_BMCR); | |
1684 | if (first_phy == -1) { | |
1685 | first_phy = i; | |
1686 | mdio_write(dev, i, MII_BMCR, | |
1687 | bmcr & ~BMCR_ISOLATE); | |
1688 | } else { | |
1689 | mdio_write(dev, i, MII_BMCR, | |
1690 | bmcr | BMCR_ISOLATE); | |
1691 | } | |
1692 | /* use mii_ethtool_sset to setup PHY */ | |
1693 | lp->mii_if.phy_id = i; | |
1694 | ecmd.phy_address = i; | |
1695 | if (lp->options & PCNET32_PORT_ASEL) { | |
1696 | mii_ethtool_gset(&lp->mii_if, &ecmd); | |
1697 | ecmd.autoneg = AUTONEG_ENABLE; | |
1698 | } | |
1699 | mii_ethtool_sset(&lp->mii_if, &ecmd); | |
1700 | } | |
1701 | } | |
1702 | lp->mii_if.phy_id = first_phy; | |
1703 | if (netif_msg_link(lp)) | |
1704 | printk(KERN_INFO "%s: Using PHY number %d.\n", | |
1705 | dev->name, first_phy); | |
1706 | } | |
1da177e4 LT |
1707 | |
1708 | #ifdef DO_DXSUFLO | |
4a5e8e29 JG |
1709 | if (lp->dxsuflo) { /* Disable transmit stop on underflow */ |
1710 | val = lp->a.read_csr(ioaddr, 3); | |
1711 | val |= 0x40; | |
1712 | lp->a.write_csr(ioaddr, 3, val); | |
1713 | } | |
1da177e4 LT |
1714 | #endif |
1715 | ||
4a5e8e29 JG |
1716 | lp->init_block.mode = |
1717 | le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7); | |
1718 | pcnet32_load_multicast(dev); | |
1719 | ||
1720 | if (pcnet32_init_ring(dev)) { | |
1721 | rc = -ENOMEM; | |
1722 | goto err_free_ring; | |
1723 | } | |
1724 | ||
1725 | /* Re-initialize the PCNET32, and start it when done. */ | |
1726 | lp->a.write_csr(ioaddr, 1, (lp->dma_addr + | |
1727 | offsetof(struct pcnet32_private, | |
1728 | init_block)) & 0xffff); | |
1729 | lp->a.write_csr(ioaddr, 2, | |
1730 | (lp->dma_addr + | |
1731 | offsetof(struct pcnet32_private, init_block)) >> 16); | |
1732 | ||
1733 | lp->a.write_csr(ioaddr, 4, 0x0915); | |
1734 | lp->a.write_csr(ioaddr, 0, 0x0001); | |
1735 | ||
1736 | netif_start_queue(dev); | |
1737 | ||
1738 | /* Print the link status and start the watchdog */ | |
1739 | pcnet32_check_media(dev, 1); | |
1740 | mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT); | |
1741 | ||
1742 | i = 0; | |
1743 | while (i++ < 100) | |
1744 | if (lp->a.read_csr(ioaddr, 0) & 0x0100) | |
1745 | break; | |
1746 | /* | |
1747 | * We used to clear the InitDone bit, 0x0100, here but Mark Stockton | |
1748 | * reports that doing so triggers a bug in the '974. | |
1749 | */ | |
1750 | lp->a.write_csr(ioaddr, 0, 0x0042); | |
1751 | ||
1752 | if (netif_msg_ifup(lp)) | |
1753 | printk(KERN_DEBUG | |
1754 | "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n", | |
1755 | dev->name, i, | |
1756 | (u32) (lp->dma_addr + | |
1757 | offsetof(struct pcnet32_private, init_block)), | |
1758 | lp->a.read_csr(ioaddr, 0)); | |
1759 | ||
1760 | spin_unlock_irqrestore(&lp->lock, flags); | |
1761 | ||
1762 | return 0; /* Always succeed */ | |
1763 | ||
1764 | err_free_ring: | |
1765 | /* free any allocated skbuffs */ | |
1766 | for (i = 0; i < lp->rx_ring_size; i++) { | |
1767 | lp->rx_ring[i].status = 0; | |
1768 | if (lp->rx_skbuff[i]) { | |
1769 | pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], | |
1770 | PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE); | |
1771 | dev_kfree_skb(lp->rx_skbuff[i]); | |
1772 | } | |
1773 | lp->rx_skbuff[i] = NULL; | |
1774 | lp->rx_dma_addr[i] = 0; | |
1775 | } | |
1776 | ||
1777 | pcnet32_free_ring(dev); | |
1778 | ||
1779 | /* | |
1780 | * Switch back to 16bit mode to avoid problems with dumb | |
1781 | * DOS packet driver after a warm reboot | |
1782 | */ | |
1783 | lp->a.write_bcr(ioaddr, 20, 4); | |
1784 | ||
1785 | err_free_irq: | |
1786 | spin_unlock_irqrestore(&lp->lock, flags); | |
1787 | free_irq(dev->irq, dev); | |
1788 | return rc; | |
1da177e4 LT |
1789 | } |
1790 | ||
1791 | /* | |
1792 | * The LANCE has been halted for one reason or another (busmaster memory | |
1793 | * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure, | |
1794 | * etc.). Modern LANCE variants always reload their ring-buffer | |
1795 | * configuration when restarted, so we must reinitialize our ring | |
1796 | * context before restarting. As part of this reinitialization, | |
1797 | * find all packets still on the Tx ring and pretend that they had been | |
1798 | * sent (in effect, drop the packets on the floor) - the higher-level | |
1799 | * protocols will time out and retransmit. It'd be better to shuffle | |
1800 | * these skbs to a temp list and then actually re-Tx them after | |
1801 | * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com | |
1802 | */ | |
1803 | ||
4a5e8e29 | 1804 | static void pcnet32_purge_tx_ring(struct net_device *dev) |
1da177e4 | 1805 | { |
4a5e8e29 JG |
1806 | struct pcnet32_private *lp = dev->priv; |
1807 | int i; | |
1da177e4 | 1808 | |
4a5e8e29 JG |
1809 | for (i = 0; i < lp->tx_ring_size; i++) { |
1810 | lp->tx_ring[i].status = 0; /* CPU owns buffer */ | |
1811 | wmb(); /* Make sure adapter sees owner change */ | |
1812 | if (lp->tx_skbuff[i]) { | |
1813 | pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], | |
1814 | lp->tx_skbuff[i]->len, | |
1815 | PCI_DMA_TODEVICE); | |
1816 | dev_kfree_skb_any(lp->tx_skbuff[i]); | |
1817 | } | |
1818 | lp->tx_skbuff[i] = NULL; | |
1819 | lp->tx_dma_addr[i] = 0; | |
1820 | } | |
1821 | } | |
1da177e4 LT |
1822 | |
1823 | /* Initialize the PCNET32 Rx and Tx rings. */ | |
4a5e8e29 | 1824 | static int pcnet32_init_ring(struct net_device *dev) |
1da177e4 | 1825 | { |
4a5e8e29 JG |
1826 | struct pcnet32_private *lp = dev->priv; |
1827 | int i; | |
1828 | ||
1829 | lp->tx_full = 0; | |
1830 | lp->cur_rx = lp->cur_tx = 0; | |
1831 | lp->dirty_rx = lp->dirty_tx = 0; | |
1832 | ||
1833 | for (i = 0; i < lp->rx_ring_size; i++) { | |
1834 | struct sk_buff *rx_skbuff = lp->rx_skbuff[i]; | |
1835 | if (rx_skbuff == NULL) { | |
1836 | if (! | |
1837 | (rx_skbuff = lp->rx_skbuff[i] = | |
1838 | dev_alloc_skb(PKT_BUF_SZ))) { | |
1839 | /* there is not much, we can do at this point */ | |
1840 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1841 | printk(KERN_ERR | |
1842 | "%s: pcnet32_init_ring dev_alloc_skb failed.\n", | |
1843 | dev->name); | |
1844 | return -1; | |
1845 | } | |
1846 | skb_reserve(rx_skbuff, 2); | |
1847 | } | |
1848 | ||
1849 | rmb(); | |
1850 | if (lp->rx_dma_addr[i] == 0) | |
1851 | lp->rx_dma_addr[i] = | |
1852 | pci_map_single(lp->pci_dev, rx_skbuff->data, | |
1853 | PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE); | |
1854 | lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]); | |
1855 | lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ); | |
1856 | wmb(); /* Make sure owner changes after all others are visible */ | |
1857 | lp->rx_ring[i].status = le16_to_cpu(0x8000); | |
1858 | } | |
1859 | /* The Tx buffer address is filled in as needed, but we do need to clear | |
1860 | * the upper ownership bit. */ | |
1861 | for (i = 0; i < lp->tx_ring_size; i++) { | |
1862 | lp->tx_ring[i].status = 0; /* CPU owns buffer */ | |
1863 | wmb(); /* Make sure adapter sees owner change */ | |
1864 | lp->tx_ring[i].base = 0; | |
1865 | lp->tx_dma_addr[i] = 0; | |
1866 | } | |
1867 | ||
1868 | lp->init_block.tlen_rlen = | |
1869 | le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits); | |
1870 | for (i = 0; i < 6; i++) | |
1871 | lp->init_block.phys_addr[i] = dev->dev_addr[i]; | |
1872 | lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr); | |
1873 | lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr); | |
1874 | wmb(); /* Make sure all changes are visible */ | |
1875 | return 0; | |
1da177e4 LT |
1876 | } |
1877 | ||
1878 | /* the pcnet32 has been issued a stop or reset. Wait for the stop bit | |
1879 | * then flush the pending transmit operations, re-initialize the ring, | |
1880 | * and tell the chip to initialize. | |
1881 | */ | |
4a5e8e29 | 1882 | static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits) |
1da177e4 | 1883 | { |
4a5e8e29 JG |
1884 | struct pcnet32_private *lp = dev->priv; |
1885 | unsigned long ioaddr = dev->base_addr; | |
1886 | int i; | |
1da177e4 | 1887 | |
4a5e8e29 JG |
1888 | /* wait for stop */ |
1889 | for (i = 0; i < 100; i++) | |
1890 | if (lp->a.read_csr(ioaddr, 0) & 0x0004) | |
1891 | break; | |
1da177e4 | 1892 | |
4a5e8e29 JG |
1893 | if (i >= 100 && netif_msg_drv(lp)) |
1894 | printk(KERN_ERR | |
1895 | "%s: pcnet32_restart timed out waiting for stop.\n", | |
1896 | dev->name); | |
1da177e4 | 1897 | |
4a5e8e29 JG |
1898 | pcnet32_purge_tx_ring(dev); |
1899 | if (pcnet32_init_ring(dev)) | |
1900 | return; | |
1da177e4 | 1901 | |
4a5e8e29 JG |
1902 | /* ReInit Ring */ |
1903 | lp->a.write_csr(ioaddr, 0, 1); | |
1904 | i = 0; | |
1905 | while (i++ < 1000) | |
1906 | if (lp->a.read_csr(ioaddr, 0) & 0x0100) | |
1907 | break; | |
1da177e4 | 1908 | |
4a5e8e29 | 1909 | lp->a.write_csr(ioaddr, 0, csr0_bits); |
1da177e4 LT |
1910 | } |
1911 | ||
4a5e8e29 | 1912 | static void pcnet32_tx_timeout(struct net_device *dev) |
1da177e4 | 1913 | { |
4a5e8e29 JG |
1914 | struct pcnet32_private *lp = dev->priv; |
1915 | unsigned long ioaddr = dev->base_addr, flags; | |
1916 | ||
1917 | spin_lock_irqsave(&lp->lock, flags); | |
1918 | /* Transmitter timeout, serious problems. */ | |
1919 | if (pcnet32_debug & NETIF_MSG_DRV) | |
1920 | printk(KERN_ERR | |
1921 | "%s: transmit timed out, status %4.4x, resetting.\n", | |
1922 | dev->name, lp->a.read_csr(ioaddr, 0)); | |
1923 | lp->a.write_csr(ioaddr, 0, 0x0004); | |
1924 | lp->stats.tx_errors++; | |
1925 | if (netif_msg_tx_err(lp)) { | |
1926 | int i; | |
1927 | printk(KERN_DEBUG | |
1928 | " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.", | |
1929 | lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "", | |
1930 | lp->cur_rx); | |
1931 | for (i = 0; i < lp->rx_ring_size; i++) | |
1932 | printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", | |
1933 | le32_to_cpu(lp->rx_ring[i].base), | |
1934 | (-le16_to_cpu(lp->rx_ring[i].buf_length)) & | |
1935 | 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length), | |
1936 | le16_to_cpu(lp->rx_ring[i].status)); | |
1937 | for (i = 0; i < lp->tx_ring_size; i++) | |
1938 | printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", | |
1939 | le32_to_cpu(lp->tx_ring[i].base), | |
1940 | (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff, | |
1941 | le32_to_cpu(lp->tx_ring[i].misc), | |
1942 | le16_to_cpu(lp->tx_ring[i].status)); | |
1943 | printk("\n"); | |
1944 | } | |
1945 | pcnet32_restart(dev, 0x0042); | |
1da177e4 | 1946 | |
4a5e8e29 JG |
1947 | dev->trans_start = jiffies; |
1948 | netif_wake_queue(dev); | |
1da177e4 | 1949 | |
4a5e8e29 JG |
1950 | spin_unlock_irqrestore(&lp->lock, flags); |
1951 | } | |
1952 | ||
1953 | static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1da177e4 | 1954 | { |
4a5e8e29 JG |
1955 | struct pcnet32_private *lp = dev->priv; |
1956 | unsigned long ioaddr = dev->base_addr; | |
1957 | u16 status; | |
1958 | int entry; | |
1959 | unsigned long flags; | |
1da177e4 | 1960 | |
4a5e8e29 | 1961 | spin_lock_irqsave(&lp->lock, flags); |
1da177e4 | 1962 | |
4a5e8e29 JG |
1963 | if (netif_msg_tx_queued(lp)) { |
1964 | printk(KERN_DEBUG | |
1965 | "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n", | |
1966 | dev->name, lp->a.read_csr(ioaddr, 0)); | |
1967 | } | |
1da177e4 | 1968 | |
4a5e8e29 JG |
1969 | /* Default status -- will not enable Successful-TxDone |
1970 | * interrupt when that option is available to us. | |
1971 | */ | |
1972 | status = 0x8300; | |
1da177e4 | 1973 | |
4a5e8e29 | 1974 | /* Fill in a Tx ring entry */ |
1da177e4 | 1975 | |
4a5e8e29 JG |
1976 | /* Mask to ring buffer boundary. */ |
1977 | entry = lp->cur_tx & lp->tx_mod_mask; | |
1da177e4 | 1978 | |
4a5e8e29 JG |
1979 | /* Caution: the write order is important here, set the status |
1980 | * with the "ownership" bits last. */ | |
1da177e4 | 1981 | |
4a5e8e29 | 1982 | lp->tx_ring[entry].length = le16_to_cpu(-skb->len); |
1da177e4 | 1983 | |
4a5e8e29 | 1984 | lp->tx_ring[entry].misc = 0x00000000; |
1da177e4 | 1985 | |
4a5e8e29 JG |
1986 | lp->tx_skbuff[entry] = skb; |
1987 | lp->tx_dma_addr[entry] = | |
1988 | pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); | |
1989 | lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]); | |
1990 | wmb(); /* Make sure owner changes after all others are visible */ | |
1991 | lp->tx_ring[entry].status = le16_to_cpu(status); | |
1da177e4 | 1992 | |
4a5e8e29 JG |
1993 | lp->cur_tx++; |
1994 | lp->stats.tx_bytes += skb->len; | |
1da177e4 | 1995 | |
4a5e8e29 JG |
1996 | /* Trigger an immediate send poll. */ |
1997 | lp->a.write_csr(ioaddr, 0, 0x0048); | |
1da177e4 | 1998 | |
4a5e8e29 | 1999 | dev->trans_start = jiffies; |
1da177e4 | 2000 | |
4a5e8e29 JG |
2001 | if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) { |
2002 | lp->tx_full = 1; | |
2003 | netif_stop_queue(dev); | |
2004 | } | |
2005 | spin_unlock_irqrestore(&lp->lock, flags); | |
2006 | return 0; | |
1da177e4 LT |
2007 | } |
2008 | ||
2009 | /* The PCNET32 interrupt handler. */ | |
2010 | static irqreturn_t | |
4a5e8e29 | 2011 | pcnet32_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
1da177e4 | 2012 | { |
4a5e8e29 JG |
2013 | struct net_device *dev = dev_id; |
2014 | struct pcnet32_private *lp; | |
2015 | unsigned long ioaddr; | |
2016 | u16 csr0, rap; | |
2017 | int boguscnt = max_interrupt_work; | |
2018 | int must_restart; | |
2019 | ||
2020 | if (!dev) { | |
2021 | if (pcnet32_debug & NETIF_MSG_INTR) | |
2022 | printk(KERN_DEBUG "%s(): irq %d for unknown device\n", | |
2023 | __FUNCTION__, irq); | |
2024 | return IRQ_NONE; | |
1da177e4 | 2025 | } |
1da177e4 | 2026 | |
4a5e8e29 JG |
2027 | ioaddr = dev->base_addr; |
2028 | lp = dev->priv; | |
1da177e4 | 2029 | |
4a5e8e29 JG |
2030 | spin_lock(&lp->lock); |
2031 | ||
2032 | rap = lp->a.read_rap(ioaddr); | |
2033 | while ((csr0 = lp->a.read_csr(ioaddr, 0)) & 0x8f00 && --boguscnt >= 0) { | |
2034 | if (csr0 == 0xffff) { | |
2035 | break; /* PCMCIA remove happened */ | |
2036 | } | |
2037 | /* Acknowledge all of the current interrupt sources ASAP. */ | |
2038 | lp->a.write_csr(ioaddr, 0, csr0 & ~0x004f); | |
2039 | ||
2040 | must_restart = 0; | |
2041 | ||
2042 | if (netif_msg_intr(lp)) | |
2043 | printk(KERN_DEBUG | |
2044 | "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n", | |
2045 | dev->name, csr0, lp->a.read_csr(ioaddr, 0)); | |
2046 | ||
2047 | if (csr0 & 0x0400) /* Rx interrupt */ | |
2048 | pcnet32_rx(dev); | |
2049 | ||
2050 | if (csr0 & 0x0200) { /* Tx-done interrupt */ | |
2051 | unsigned int dirty_tx = lp->dirty_tx; | |
2052 | int delta; | |
2053 | ||
2054 | while (dirty_tx != lp->cur_tx) { | |
2055 | int entry = dirty_tx & lp->tx_mod_mask; | |
2056 | int status = | |
2057 | (short)le16_to_cpu(lp->tx_ring[entry]. | |
2058 | status); | |
2059 | ||
2060 | if (status < 0) | |
2061 | break; /* It still hasn't been Txed */ | |
2062 | ||
2063 | lp->tx_ring[entry].base = 0; | |
2064 | ||
2065 | if (status & 0x4000) { | |
2066 | /* There was an major error, log it. */ | |
2067 | int err_status = | |
2068 | le32_to_cpu(lp->tx_ring[entry]. | |
2069 | misc); | |
2070 | lp->stats.tx_errors++; | |
2071 | if (netif_msg_tx_err(lp)) | |
2072 | printk(KERN_ERR | |
2073 | "%s: Tx error status=%04x err_status=%08x\n", | |
2074 | dev->name, status, | |
2075 | err_status); | |
2076 | if (err_status & 0x04000000) | |
2077 | lp->stats.tx_aborted_errors++; | |
2078 | if (err_status & 0x08000000) | |
2079 | lp->stats.tx_carrier_errors++; | |
2080 | if (err_status & 0x10000000) | |
2081 | lp->stats.tx_window_errors++; | |
1da177e4 | 2082 | #ifndef DO_DXSUFLO |
4a5e8e29 JG |
2083 | if (err_status & 0x40000000) { |
2084 | lp->stats.tx_fifo_errors++; | |
2085 | /* Ackk! On FIFO errors the Tx unit is turned off! */ | |
2086 | /* Remove this verbosity later! */ | |
2087 | if (netif_msg_tx_err(lp)) | |
2088 | printk(KERN_ERR | |
2089 | "%s: Tx FIFO error! CSR0=%4.4x\n", | |
2090 | dev->name, csr0); | |
2091 | must_restart = 1; | |
2092 | } | |
1da177e4 | 2093 | #else |
4a5e8e29 JG |
2094 | if (err_status & 0x40000000) { |
2095 | lp->stats.tx_fifo_errors++; | |
2096 | if (!lp->dxsuflo) { /* If controller doesn't recover ... */ | |
2097 | /* Ackk! On FIFO errors the Tx unit is turned off! */ | |
2098 | /* Remove this verbosity later! */ | |
2099 | if (netif_msg_tx_err | |
2100 | (lp)) | |
2101 | printk(KERN_ERR | |
2102 | "%s: Tx FIFO error! CSR0=%4.4x\n", | |
2103 | dev-> | |
2104 | name, | |
2105 | csr0); | |
2106 | must_restart = 1; | |
2107 | } | |
2108 | } | |
1da177e4 | 2109 | #endif |
4a5e8e29 JG |
2110 | } else { |
2111 | if (status & 0x1800) | |
2112 | lp->stats.collisions++; | |
2113 | lp->stats.tx_packets++; | |
2114 | } | |
2115 | ||
2116 | /* We must free the original skb */ | |
2117 | if (lp->tx_skbuff[entry]) { | |
2118 | pci_unmap_single(lp->pci_dev, | |
2119 | lp->tx_dma_addr[entry], | |
2120 | lp->tx_skbuff[entry]-> | |
2121 | len, PCI_DMA_TODEVICE); | |
2122 | dev_kfree_skb_irq(lp->tx_skbuff[entry]); | |
2123 | lp->tx_skbuff[entry] = NULL; | |
2124 | lp->tx_dma_addr[entry] = 0; | |
2125 | } | |
2126 | dirty_tx++; | |
2127 | } | |
2128 | ||
2129 | delta = | |
2130 | (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + | |
2131 | lp->tx_ring_size); | |
2132 | if (delta > lp->tx_ring_size) { | |
2133 | if (netif_msg_drv(lp)) | |
2134 | printk(KERN_ERR | |
2135 | "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n", | |
2136 | dev->name, dirty_tx, lp->cur_tx, | |
2137 | lp->tx_full); | |
2138 | dirty_tx += lp->tx_ring_size; | |
2139 | delta -= lp->tx_ring_size; | |
2140 | } | |
2141 | ||
2142 | if (lp->tx_full && | |
2143 | netif_queue_stopped(dev) && | |
2144 | delta < lp->tx_ring_size - 2) { | |
2145 | /* The ring is no longer full, clear tbusy. */ | |
2146 | lp->tx_full = 0; | |
2147 | netif_wake_queue(dev); | |
2148 | } | |
2149 | lp->dirty_tx = dirty_tx; | |
2150 | } | |
2151 | ||
2152 | /* Log misc errors. */ | |
2153 | if (csr0 & 0x4000) | |
2154 | lp->stats.tx_errors++; /* Tx babble. */ | |
2155 | if (csr0 & 0x1000) { | |
2156 | /* | |
2157 | * this happens when our receive ring is full. This shouldn't | |
2158 | * be a problem as we will see normal rx interrupts for the frames | |
2159 | * in the receive ring. But there are some PCI chipsets (I can | |
2160 | * reproduce this on SP3G with Intel saturn chipset) which have | |
2161 | * sometimes problems and will fill up the receive ring with | |
2162 | * error descriptors. In this situation we don't get a rx | |
2163 | * interrupt, but a missed frame interrupt sooner or later. | |
2164 | * So we try to clean up our receive ring here. | |
2165 | */ | |
2166 | pcnet32_rx(dev); | |
2167 | lp->stats.rx_errors++; /* Missed a Rx frame. */ | |
2168 | } | |
2169 | if (csr0 & 0x0800) { | |
2170 | if (netif_msg_drv(lp)) | |
2171 | printk(KERN_ERR | |
2172 | "%s: Bus master arbitration failure, status %4.4x.\n", | |
2173 | dev->name, csr0); | |
2174 | /* unlike for the lance, there is no restart needed */ | |
1da177e4 LT |
2175 | } |
2176 | ||
4a5e8e29 JG |
2177 | if (must_restart) { |
2178 | /* reset the chip to clear the error condition, then restart */ | |
2179 | lp->a.reset(ioaddr); | |
2180 | lp->a.write_csr(ioaddr, 4, 0x0915); | |
2181 | pcnet32_restart(dev, 0x0002); | |
2182 | netif_wake_queue(dev); | |
1da177e4 | 2183 | } |
4a5e8e29 JG |
2184 | } |
2185 | ||
2186 | /* Set interrupt enable. */ | |
2187 | lp->a.write_csr(ioaddr, 0, 0x0040); | |
2188 | lp->a.write_rap(ioaddr, rap); | |
2189 | ||
2190 | if (netif_msg_intr(lp)) | |
2191 | printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n", | |
2192 | dev->name, lp->a.read_csr(ioaddr, 0)); | |
2193 | ||
2194 | spin_unlock(&lp->lock); | |
2195 | ||
2196 | return IRQ_HANDLED; | |
1da177e4 LT |
2197 | } |
2198 | ||
4a5e8e29 | 2199 | static int pcnet32_rx(struct net_device *dev) |
1da177e4 | 2200 | { |
4a5e8e29 JG |
2201 | struct pcnet32_private *lp = dev->priv; |
2202 | int entry = lp->cur_rx & lp->rx_mod_mask; | |
2203 | int boguscnt = lp->rx_ring_size / 2; | |
2204 | ||
2205 | /* If we own the next entry, it's a new packet. Send it up. */ | |
2206 | while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) { | |
2207 | int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8; | |
2208 | ||
2209 | if (status != 0x03) { /* There was an error. */ | |
2210 | /* | |
2211 | * There is a tricky error noted by John Murphy, | |
2212 | * <murf@perftech.com> to Russ Nelson: Even with full-sized | |
2213 | * buffers it's possible for a jabber packet to use two | |
2214 | * buffers, with only the last correctly noting the error. | |
2215 | */ | |
2216 | if (status & 0x01) /* Only count a general error at the */ | |
2217 | lp->stats.rx_errors++; /* end of a packet. */ | |
2218 | if (status & 0x20) | |
2219 | lp->stats.rx_frame_errors++; | |
2220 | if (status & 0x10) | |
2221 | lp->stats.rx_over_errors++; | |
2222 | if (status & 0x08) | |
2223 | lp->stats.rx_crc_errors++; | |
2224 | if (status & 0x04) | |
2225 | lp->stats.rx_fifo_errors++; | |
2226 | lp->rx_ring[entry].status &= le16_to_cpu(0x03ff); | |
1da177e4 | 2227 | } else { |
4a5e8e29 JG |
2228 | /* Malloc up new buffer, compatible with net-2e. */ |
2229 | short pkt_len = | |
2230 | (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff) | |
2231 | - 4; | |
2232 | struct sk_buff *skb; | |
2233 | ||
2234 | /* Discard oversize frames. */ | |
2235 | if (unlikely(pkt_len > PKT_BUF_SZ - 2)) { | |
2236 | if (netif_msg_drv(lp)) | |
2237 | printk(KERN_ERR | |
2238 | "%s: Impossible packet size %d!\n", | |
2239 | dev->name, pkt_len); | |
2240 | lp->stats.rx_errors++; | |
2241 | } else if (pkt_len < 60) { | |
2242 | if (netif_msg_rx_err(lp)) | |
2243 | printk(KERN_ERR "%s: Runt packet!\n", | |
2244 | dev->name); | |
2245 | lp->stats.rx_errors++; | |
2246 | } else { | |
2247 | int rx_in_place = 0; | |
2248 | ||
2249 | if (pkt_len > rx_copybreak) { | |
2250 | struct sk_buff *newskb; | |
2251 | ||
2252 | if ((newskb = | |
2253 | dev_alloc_skb(PKT_BUF_SZ))) { | |
2254 | skb_reserve(newskb, 2); | |
2255 | skb = lp->rx_skbuff[entry]; | |
2256 | pci_unmap_single(lp->pci_dev, | |
2257 | lp-> | |
2258 | rx_dma_addr | |
2259 | [entry], | |
2260 | PKT_BUF_SZ - 2, | |
2261 | PCI_DMA_FROMDEVICE); | |
2262 | skb_put(skb, pkt_len); | |
2263 | lp->rx_skbuff[entry] = newskb; | |
2264 | newskb->dev = dev; | |
2265 | lp->rx_dma_addr[entry] = | |
2266 | pci_map_single(lp->pci_dev, | |
2267 | newskb->data, | |
2268 | PKT_BUF_SZ - | |
2269 | 2, | |
2270 | PCI_DMA_FROMDEVICE); | |
2271 | lp->rx_ring[entry].base = | |
2272 | le32_to_cpu(lp-> | |
2273 | rx_dma_addr | |
2274 | [entry]); | |
2275 | rx_in_place = 1; | |
2276 | } else | |
2277 | skb = NULL; | |
2278 | } else { | |
2279 | skb = dev_alloc_skb(pkt_len + 2); | |
2280 | } | |
2281 | ||
2282 | if (skb == NULL) { | |
2283 | int i; | |
2284 | if (netif_msg_drv(lp)) | |
2285 | printk(KERN_ERR | |
2286 | "%s: Memory squeeze, deferring packet.\n", | |
2287 | dev->name); | |
2288 | for (i = 0; i < lp->rx_ring_size; i++) | |
2289 | if ((short) | |
2290 | le16_to_cpu(lp-> | |
2291 | rx_ring[(entry + | |
2292 | i) | |
2293 | & lp-> | |
2294 | rx_mod_mask]. | |
2295 | status) < 0) | |
2296 | break; | |
2297 | ||
2298 | if (i > lp->rx_ring_size - 2) { | |
2299 | lp->stats.rx_dropped++; | |
2300 | lp->rx_ring[entry].status |= | |
2301 | le16_to_cpu(0x8000); | |
2302 | wmb(); /* Make sure adapter sees owner change */ | |
2303 | lp->cur_rx++; | |
2304 | } | |
2305 | break; | |
2306 | } | |
2307 | skb->dev = dev; | |
2308 | if (!rx_in_place) { | |
2309 | skb_reserve(skb, 2); /* 16 byte align */ | |
2310 | skb_put(skb, pkt_len); /* Make room */ | |
2311 | pci_dma_sync_single_for_cpu(lp->pci_dev, | |
2312 | lp-> | |
2313 | rx_dma_addr | |
2314 | [entry], | |
2315 | PKT_BUF_SZ - | |
2316 | 2, | |
2317 | PCI_DMA_FROMDEVICE); | |
2318 | eth_copy_and_sum(skb, | |
2319 | (unsigned char *)(lp-> | |
2320 | rx_skbuff | |
2321 | [entry]-> | |
2322 | data), | |
2323 | pkt_len, 0); | |
2324 | pci_dma_sync_single_for_device(lp-> | |
2325 | pci_dev, | |
2326 | lp-> | |
2327 | rx_dma_addr | |
2328 | [entry], | |
2329 | PKT_BUF_SZ | |
2330 | - 2, | |
2331 | PCI_DMA_FROMDEVICE); | |
2332 | } | |
2333 | lp->stats.rx_bytes += skb->len; | |
2334 | skb->protocol = eth_type_trans(skb, dev); | |
2335 | netif_rx(skb); | |
2336 | dev->last_rx = jiffies; | |
2337 | lp->stats.rx_packets++; | |
2338 | } | |
1da177e4 | 2339 | } |
4a5e8e29 JG |
2340 | /* |
2341 | * The docs say that the buffer length isn't touched, but Andrew Boyd | |
2342 | * of QNX reports that some revs of the 79C965 clear it. | |
2343 | */ | |
2344 | lp->rx_ring[entry].buf_length = le16_to_cpu(2 - PKT_BUF_SZ); | |
2345 | wmb(); /* Make sure owner changes after all others are visible */ | |
2346 | lp->rx_ring[entry].status |= le16_to_cpu(0x8000); | |
2347 | entry = (++lp->cur_rx) & lp->rx_mod_mask; | |
2348 | if (--boguscnt <= 0) | |
2349 | break; /* don't stay in loop forever */ | |
1da177e4 | 2350 | } |
4a5e8e29 JG |
2351 | |
2352 | return 0; | |
1da177e4 LT |
2353 | } |
2354 | ||
4a5e8e29 | 2355 | static int pcnet32_close(struct net_device *dev) |
1da177e4 | 2356 | { |
4a5e8e29 JG |
2357 | unsigned long ioaddr = dev->base_addr; |
2358 | struct pcnet32_private *lp = dev->priv; | |
2359 | int i; | |
2360 | unsigned long flags; | |
1da177e4 | 2361 | |
4a5e8e29 | 2362 | del_timer_sync(&lp->watchdog_timer); |
1da177e4 | 2363 | |
4a5e8e29 | 2364 | netif_stop_queue(dev); |
1da177e4 | 2365 | |
4a5e8e29 | 2366 | spin_lock_irqsave(&lp->lock, flags); |
1da177e4 | 2367 | |
4a5e8e29 | 2368 | lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112); |
1da177e4 | 2369 | |
4a5e8e29 JG |
2370 | if (netif_msg_ifdown(lp)) |
2371 | printk(KERN_DEBUG | |
2372 | "%s: Shutting down ethercard, status was %2.2x.\n", | |
2373 | dev->name, lp->a.read_csr(ioaddr, 0)); | |
1da177e4 | 2374 | |
4a5e8e29 JG |
2375 | /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */ |
2376 | lp->a.write_csr(ioaddr, 0, 0x0004); | |
1da177e4 | 2377 | |
4a5e8e29 JG |
2378 | /* |
2379 | * Switch back to 16bit mode to avoid problems with dumb | |
2380 | * DOS packet driver after a warm reboot | |
2381 | */ | |
2382 | lp->a.write_bcr(ioaddr, 20, 4); | |
1da177e4 | 2383 | |
4a5e8e29 | 2384 | spin_unlock_irqrestore(&lp->lock, flags); |
1da177e4 | 2385 | |
4a5e8e29 | 2386 | free_irq(dev->irq, dev); |
1da177e4 | 2387 | |
4a5e8e29 | 2388 | spin_lock_irqsave(&lp->lock, flags); |
1da177e4 | 2389 | |
4a5e8e29 JG |
2390 | /* free all allocated skbuffs */ |
2391 | for (i = 0; i < lp->rx_ring_size; i++) { | |
2392 | lp->rx_ring[i].status = 0; | |
2393 | wmb(); /* Make sure adapter sees owner change */ | |
2394 | if (lp->rx_skbuff[i]) { | |
2395 | pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], | |
2396 | PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE); | |
2397 | dev_kfree_skb(lp->rx_skbuff[i]); | |
2398 | } | |
2399 | lp->rx_skbuff[i] = NULL; | |
2400 | lp->rx_dma_addr[i] = 0; | |
1da177e4 | 2401 | } |
1da177e4 | 2402 | |
4a5e8e29 JG |
2403 | for (i = 0; i < lp->tx_ring_size; i++) { |
2404 | lp->tx_ring[i].status = 0; /* CPU owns buffer */ | |
2405 | wmb(); /* Make sure adapter sees owner change */ | |
2406 | if (lp->tx_skbuff[i]) { | |
2407 | pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], | |
2408 | lp->tx_skbuff[i]->len, | |
2409 | PCI_DMA_TODEVICE); | |
2410 | dev_kfree_skb(lp->tx_skbuff[i]); | |
2411 | } | |
2412 | lp->tx_skbuff[i] = NULL; | |
2413 | lp->tx_dma_addr[i] = 0; | |
1da177e4 | 2414 | } |
1da177e4 | 2415 | |
4a5e8e29 | 2416 | spin_unlock_irqrestore(&lp->lock, flags); |
1da177e4 | 2417 | |
4a5e8e29 | 2418 | return 0; |
1da177e4 LT |
2419 | } |
2420 | ||
4a5e8e29 | 2421 | static struct net_device_stats *pcnet32_get_stats(struct net_device *dev) |
1da177e4 | 2422 | { |
4a5e8e29 JG |
2423 | struct pcnet32_private *lp = dev->priv; |
2424 | unsigned long ioaddr = dev->base_addr; | |
2425 | u16 saved_addr; | |
2426 | unsigned long flags; | |
2427 | ||
2428 | spin_lock_irqsave(&lp->lock, flags); | |
2429 | saved_addr = lp->a.read_rap(ioaddr); | |
2430 | lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112); | |
2431 | lp->a.write_rap(ioaddr, saved_addr); | |
2432 | spin_unlock_irqrestore(&lp->lock, flags); | |
2433 | ||
2434 | return &lp->stats; | |
1da177e4 LT |
2435 | } |
2436 | ||
2437 | /* taken from the sunlance driver, which it took from the depca driver */ | |
4a5e8e29 | 2438 | static void pcnet32_load_multicast(struct net_device *dev) |
1da177e4 | 2439 | { |
4a5e8e29 JG |
2440 | struct pcnet32_private *lp = dev->priv; |
2441 | volatile struct pcnet32_init_block *ib = &lp->init_block; | |
2442 | volatile u16 *mcast_table = (u16 *) & ib->filter; | |
2443 | struct dev_mc_list *dmi = dev->mc_list; | |
2444 | char *addrs; | |
2445 | int i; | |
2446 | u32 crc; | |
2447 | ||
2448 | /* set all multicast bits */ | |
2449 | if (dev->flags & IFF_ALLMULTI) { | |
2450 | ib->filter[0] = 0xffffffff; | |
2451 | ib->filter[1] = 0xffffffff; | |
2452 | return; | |
2453 | } | |
2454 | /* clear the multicast filter */ | |
2455 | ib->filter[0] = 0; | |
2456 | ib->filter[1] = 0; | |
2457 | ||
2458 | /* Add addresses */ | |
2459 | for (i = 0; i < dev->mc_count; i++) { | |
2460 | addrs = dmi->dmi_addr; | |
2461 | dmi = dmi->next; | |
2462 | ||
2463 | /* multicast address? */ | |
2464 | if (!(*addrs & 1)) | |
2465 | continue; | |
2466 | ||
2467 | crc = ether_crc_le(6, addrs); | |
2468 | crc = crc >> 26; | |
2469 | mcast_table[crc >> 4] = | |
2470 | le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) | | |
2471 | (1 << (crc & 0xf))); | |
2472 | } | |
1da177e4 | 2473 | return; |
1da177e4 LT |
2474 | } |
2475 | ||
1da177e4 LT |
2476 | /* |
2477 | * Set or clear the multicast filter for this adaptor. | |
2478 | */ | |
2479 | static void pcnet32_set_multicast_list(struct net_device *dev) | |
2480 | { | |
4a5e8e29 JG |
2481 | unsigned long ioaddr = dev->base_addr, flags; |
2482 | struct pcnet32_private *lp = dev->priv; | |
2483 | ||
2484 | spin_lock_irqsave(&lp->lock, flags); | |
2485 | if (dev->flags & IFF_PROMISC) { | |
2486 | /* Log any net taps. */ | |
2487 | if (netif_msg_hw(lp)) | |
2488 | printk(KERN_INFO "%s: Promiscuous mode enabled.\n", | |
2489 | dev->name); | |
2490 | lp->init_block.mode = | |
2491 | le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << | |
2492 | 7); | |
2493 | } else { | |
2494 | lp->init_block.mode = | |
2495 | le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7); | |
2496 | pcnet32_load_multicast(dev); | |
2497 | } | |
2498 | ||
2499 | lp->a.write_csr(ioaddr, 0, 0x0004); /* Temporarily stop the lance. */ | |
2500 | pcnet32_restart(dev, 0x0042); /* Resume normal operation */ | |
2501 | netif_wake_queue(dev); | |
2502 | ||
2503 | spin_unlock_irqrestore(&lp->lock, flags); | |
1da177e4 LT |
2504 | } |
2505 | ||
2506 | /* This routine assumes that the lp->lock is held */ | |
2507 | static int mdio_read(struct net_device *dev, int phy_id, int reg_num) | |
2508 | { | |
4a5e8e29 JG |
2509 | struct pcnet32_private *lp = dev->priv; |
2510 | unsigned long ioaddr = dev->base_addr; | |
2511 | u16 val_out; | |
1da177e4 | 2512 | |
4a5e8e29 JG |
2513 | if (!lp->mii) |
2514 | return 0; | |
1da177e4 | 2515 | |
4a5e8e29 JG |
2516 | lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); |
2517 | val_out = lp->a.read_bcr(ioaddr, 34); | |
1da177e4 | 2518 | |
4a5e8e29 | 2519 | return val_out; |
1da177e4 LT |
2520 | } |
2521 | ||
2522 | /* This routine assumes that the lp->lock is held */ | |
2523 | static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) | |
2524 | { | |
4a5e8e29 JG |
2525 | struct pcnet32_private *lp = dev->priv; |
2526 | unsigned long ioaddr = dev->base_addr; | |
1da177e4 | 2527 | |
4a5e8e29 JG |
2528 | if (!lp->mii) |
2529 | return; | |
1da177e4 | 2530 | |
4a5e8e29 JG |
2531 | lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); |
2532 | lp->a.write_bcr(ioaddr, 34, val); | |
1da177e4 LT |
2533 | } |
2534 | ||
2535 | static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2536 | { | |
4a5e8e29 JG |
2537 | struct pcnet32_private *lp = dev->priv; |
2538 | int rc; | |
2539 | unsigned long flags; | |
1da177e4 | 2540 | |
4a5e8e29 JG |
2541 | /* SIOC[GS]MIIxxx ioctls */ |
2542 | if (lp->mii) { | |
2543 | spin_lock_irqsave(&lp->lock, flags); | |
2544 | rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL); | |
2545 | spin_unlock_irqrestore(&lp->lock, flags); | |
2546 | } else { | |
2547 | rc = -EOPNOTSUPP; | |
2548 | } | |
1da177e4 | 2549 | |
4a5e8e29 | 2550 | return rc; |
1da177e4 LT |
2551 | } |
2552 | ||
ac62ef04 DF |
2553 | static int pcnet32_check_otherphy(struct net_device *dev) |
2554 | { | |
4a5e8e29 JG |
2555 | struct pcnet32_private *lp = dev->priv; |
2556 | struct mii_if_info mii = lp->mii_if; | |
2557 | u16 bmcr; | |
2558 | int i; | |
ac62ef04 | 2559 | |
4a5e8e29 JG |
2560 | for (i = 0; i < PCNET32_MAX_PHYS; i++) { |
2561 | if (i == lp->mii_if.phy_id) | |
2562 | continue; /* skip active phy */ | |
2563 | if (lp->phymask & (1 << i)) { | |
2564 | mii.phy_id = i; | |
2565 | if (mii_link_ok(&mii)) { | |
2566 | /* found PHY with active link */ | |
2567 | if (netif_msg_link(lp)) | |
2568 | printk(KERN_INFO | |
2569 | "%s: Using PHY number %d.\n", | |
2570 | dev->name, i); | |
2571 | ||
2572 | /* isolate inactive phy */ | |
2573 | bmcr = | |
2574 | mdio_read(dev, lp->mii_if.phy_id, MII_BMCR); | |
2575 | mdio_write(dev, lp->mii_if.phy_id, MII_BMCR, | |
2576 | bmcr | BMCR_ISOLATE); | |
2577 | ||
2578 | /* de-isolate new phy */ | |
2579 | bmcr = mdio_read(dev, i, MII_BMCR); | |
2580 | mdio_write(dev, i, MII_BMCR, | |
2581 | bmcr & ~BMCR_ISOLATE); | |
2582 | ||
2583 | /* set new phy address */ | |
2584 | lp->mii_if.phy_id = i; | |
2585 | return 1; | |
2586 | } | |
2587 | } | |
ac62ef04 | 2588 | } |
4a5e8e29 | 2589 | return 0; |
ac62ef04 DF |
2590 | } |
2591 | ||
2592 | /* | |
2593 | * Show the status of the media. Similar to mii_check_media however it | |
2594 | * correctly shows the link speed for all (tested) pcnet32 variants. | |
2595 | * Devices with no mii just report link state without speed. | |
2596 | * | |
2597 | * Caller is assumed to hold and release the lp->lock. | |
2598 | */ | |
2599 | ||
2600 | static void pcnet32_check_media(struct net_device *dev, int verbose) | |
2601 | { | |
4a5e8e29 JG |
2602 | struct pcnet32_private *lp = dev->priv; |
2603 | int curr_link; | |
2604 | int prev_link = netif_carrier_ok(dev) ? 1 : 0; | |
2605 | u32 bcr9; | |
2606 | ||
ac62ef04 | 2607 | if (lp->mii) { |
4a5e8e29 | 2608 | curr_link = mii_link_ok(&lp->mii_if); |
ac62ef04 | 2609 | } else { |
4a5e8e29 JG |
2610 | ulong ioaddr = dev->base_addr; /* card base I/O address */ |
2611 | curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0); | |
2612 | } | |
2613 | if (!curr_link) { | |
2614 | if (prev_link || verbose) { | |
2615 | netif_carrier_off(dev); | |
2616 | if (netif_msg_link(lp)) | |
2617 | printk(KERN_INFO "%s: link down\n", dev->name); | |
2618 | } | |
2619 | if (lp->phycount > 1) { | |
2620 | curr_link = pcnet32_check_otherphy(dev); | |
2621 | prev_link = 0; | |
2622 | } | |
2623 | } else if (verbose || !prev_link) { | |
2624 | netif_carrier_on(dev); | |
2625 | if (lp->mii) { | |
2626 | if (netif_msg_link(lp)) { | |
2627 | struct ethtool_cmd ecmd; | |
2628 | mii_ethtool_gset(&lp->mii_if, &ecmd); | |
2629 | printk(KERN_INFO | |
2630 | "%s: link up, %sMbps, %s-duplex\n", | |
2631 | dev->name, | |
2632 | (ecmd.speed == SPEED_100) ? "100" : "10", | |
2633 | (ecmd.duplex == | |
2634 | DUPLEX_FULL) ? "full" : "half"); | |
2635 | } | |
2636 | bcr9 = lp->a.read_bcr(dev->base_addr, 9); | |
2637 | if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) { | |
2638 | if (lp->mii_if.full_duplex) | |
2639 | bcr9 |= (1 << 0); | |
2640 | else | |
2641 | bcr9 &= ~(1 << 0); | |
2642 | lp->a.write_bcr(dev->base_addr, 9, bcr9); | |
2643 | } | |
2644 | } else { | |
2645 | if (netif_msg_link(lp)) | |
2646 | printk(KERN_INFO "%s: link up\n", dev->name); | |
2647 | } | |
ac62ef04 | 2648 | } |
ac62ef04 DF |
2649 | } |
2650 | ||
2651 | /* | |
2652 | * Check for loss of link and link establishment. | |
2653 | * Can not use mii_check_media because it does nothing if mode is forced. | |
2654 | */ | |
2655 | ||
1da177e4 LT |
2656 | static void pcnet32_watchdog(struct net_device *dev) |
2657 | { | |
4a5e8e29 JG |
2658 | struct pcnet32_private *lp = dev->priv; |
2659 | unsigned long flags; | |
1da177e4 | 2660 | |
4a5e8e29 JG |
2661 | /* Print the link status if it has changed */ |
2662 | spin_lock_irqsave(&lp->lock, flags); | |
2663 | pcnet32_check_media(dev, 0); | |
2664 | spin_unlock_irqrestore(&lp->lock, flags); | |
1da177e4 | 2665 | |
4a5e8e29 | 2666 | mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT); |
1da177e4 LT |
2667 | } |
2668 | ||
2669 | static void __devexit pcnet32_remove_one(struct pci_dev *pdev) | |
2670 | { | |
4a5e8e29 JG |
2671 | struct net_device *dev = pci_get_drvdata(pdev); |
2672 | ||
2673 | if (dev) { | |
2674 | struct pcnet32_private *lp = dev->priv; | |
2675 | ||
2676 | unregister_netdev(dev); | |
2677 | pcnet32_free_ring(dev); | |
2678 | release_region(dev->base_addr, PCNET32_TOTAL_SIZE); | |
2679 | pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr); | |
2680 | free_netdev(dev); | |
2681 | pci_disable_device(pdev); | |
2682 | pci_set_drvdata(pdev, NULL); | |
2683 | } | |
1da177e4 LT |
2684 | } |
2685 | ||
2686 | static struct pci_driver pcnet32_driver = { | |
4a5e8e29 JG |
2687 | .name = DRV_NAME, |
2688 | .probe = pcnet32_probe_pci, | |
2689 | .remove = __devexit_p(pcnet32_remove_one), | |
2690 | .id_table = pcnet32_pci_tbl, | |
1da177e4 LT |
2691 | }; |
2692 | ||
2693 | /* An additional parameter that may be passed in... */ | |
2694 | static int debug = -1; | |
2695 | static int tx_start_pt = -1; | |
2696 | static int pcnet32_have_pci; | |
2697 | ||
2698 | module_param(debug, int, 0); | |
2699 | MODULE_PARM_DESC(debug, DRV_NAME " debug level"); | |
2700 | module_param(max_interrupt_work, int, 0); | |
4a5e8e29 JG |
2701 | MODULE_PARM_DESC(max_interrupt_work, |
2702 | DRV_NAME " maximum events handled per interrupt"); | |
1da177e4 | 2703 | module_param(rx_copybreak, int, 0); |
4a5e8e29 JG |
2704 | MODULE_PARM_DESC(rx_copybreak, |
2705 | DRV_NAME " copy breakpoint for copy-only-tiny-frames"); | |
1da177e4 LT |
2706 | module_param(tx_start_pt, int, 0); |
2707 | MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)"); | |
2708 | module_param(pcnet32vlb, int, 0); | |
2709 | MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)"); | |
2710 | module_param_array(options, int, NULL, 0); | |
2711 | MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)"); | |
2712 | module_param_array(full_duplex, int, NULL, 0); | |
2713 | MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)"); | |
2714 | /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */ | |
2715 | module_param_array(homepna, int, NULL, 0); | |
4a5e8e29 JG |
2716 | MODULE_PARM_DESC(homepna, |
2717 | DRV_NAME | |
2718 | " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet"); | |
1da177e4 LT |
2719 | |
2720 | MODULE_AUTHOR("Thomas Bogendoerfer"); | |
2721 | MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards"); | |
2722 | MODULE_LICENSE("GPL"); | |
2723 | ||
2724 | #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) | |
2725 | ||
2726 | static int __init pcnet32_init_module(void) | |
2727 | { | |
4a5e8e29 | 2728 | printk(KERN_INFO "%s", version); |
1da177e4 | 2729 | |
4a5e8e29 | 2730 | pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT); |
1da177e4 | 2731 | |
4a5e8e29 JG |
2732 | if ((tx_start_pt >= 0) && (tx_start_pt <= 3)) |
2733 | tx_start = tx_start_pt; | |
1da177e4 | 2734 | |
4a5e8e29 JG |
2735 | /* find the PCI devices */ |
2736 | if (!pci_module_init(&pcnet32_driver)) | |
2737 | pcnet32_have_pci = 1; | |
1da177e4 | 2738 | |
4a5e8e29 JG |
2739 | /* should we find any remaining VLbus devices ? */ |
2740 | if (pcnet32vlb) | |
2741 | pcnet32_probe_vlbus(); | |
1da177e4 | 2742 | |
4a5e8e29 JG |
2743 | if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE)) |
2744 | printk(KERN_INFO PFX "%d cards_found.\n", cards_found); | |
1da177e4 | 2745 | |
4a5e8e29 | 2746 | return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV; |
1da177e4 LT |
2747 | } |
2748 | ||
2749 | static void __exit pcnet32_cleanup_module(void) | |
2750 | { | |
4a5e8e29 JG |
2751 | struct net_device *next_dev; |
2752 | ||
2753 | while (pcnet32_dev) { | |
2754 | struct pcnet32_private *lp = pcnet32_dev->priv; | |
2755 | next_dev = lp->next; | |
2756 | unregister_netdev(pcnet32_dev); | |
2757 | pcnet32_free_ring(pcnet32_dev); | |
2758 | release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE); | |
2759 | pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr); | |
2760 | free_netdev(pcnet32_dev); | |
2761 | pcnet32_dev = next_dev; | |
2762 | } | |
1da177e4 | 2763 | |
4a5e8e29 JG |
2764 | if (pcnet32_have_pci) |
2765 | pci_unregister_driver(&pcnet32_driver); | |
1da177e4 LT |
2766 | } |
2767 | ||
2768 | module_init(pcnet32_init_module); | |
2769 | module_exit(pcnet32_cleanup_module); | |
2770 | ||
2771 | /* | |
2772 | * Local variables: | |
2773 | * c-indent-level: 4 | |
2774 | * tab-width: 8 | |
2775 | * End: | |
2776 | */ |