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Merge branch 'tracing/core' of git://git.kernel.org/pub/scm/linux/kernel/git/frederic...
[linux-2.6-block.git] / drivers / net / netxen / netxen_nic_init.c
CommitLineData
3d396eb1 1/*
5d242f1c 2 * Copyright (C) 2003 - 2009 NetXen, Inc.
13af7a6e 3 * Copyright (C) 2009 - QLogic Corporation.
3d396eb1 4 * All rights reserved.
80922fbc 5 *
3d396eb1
AK		 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
80922fbc 10 *
3d396eb1
AK		 11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
80922fbc 15 *
3d396eb1
AK		 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
80922fbc 20 *
3d396eb1
AK		 21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.
80922fbc 23 *
3d396eb1
AK		 24 */
25
26#include <linux/netdevice.h>
27#include <linux/delay.h>
28#include "netxen_nic.h"
29#include "netxen_nic_hw.h"
3d396eb1
AK		 30
31struct crb_addr_pair {
e0e20a1a
LCMT		 32 u32 addr;
33 u32 data;
3d396eb1
AK		 34};
35
36#define NETXEN_MAX_CRB_XFORM 60
37static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
e0e20a1a 38#define NETXEN_ADDR_ERROR (0xffffffff)
3d396eb1
AK		 39
40#define crb_addr_transform(name) \
41 crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
42 NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
43
cb8011ad
AK		 44#define NETXEN_NIC_XDMA_RESET 0x8000ff
45
becf46a0 46static void
d8b100c5
DP		 47netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
48 struct nx_host_rds_ring *rds_ring);
f50330f9 49static int netxen_p3_has_mn(struct netxen_adapter *adapter);
993fb90c 50
3d396eb1
AK		 51static void crb_addr_transform_setup(void)
52{
53 crb_addr_transform(XDMA);
54 crb_addr_transform(TIMR);
55 crb_addr_transform(SRE);
56 crb_addr_transform(SQN3);
57 crb_addr_transform(SQN2);
58 crb_addr_transform(SQN1);
59 crb_addr_transform(SQN0);
60 crb_addr_transform(SQS3);
61 crb_addr_transform(SQS2);
62 crb_addr_transform(SQS1);
63 crb_addr_transform(SQS0);
64 crb_addr_transform(RPMX7);
65 crb_addr_transform(RPMX6);
66 crb_addr_transform(RPMX5);
67 crb_addr_transform(RPMX4);
68 crb_addr_transform(RPMX3);
69 crb_addr_transform(RPMX2);
70 crb_addr_transform(RPMX1);
71 crb_addr_transform(RPMX0);
72 crb_addr_transform(ROMUSB);
73 crb_addr_transform(SN);
74 crb_addr_transform(QMN);
75 crb_addr_transform(QMS);
76 crb_addr_transform(PGNI);
77 crb_addr_transform(PGND);
78 crb_addr_transform(PGN3);
79 crb_addr_transform(PGN2);
80 crb_addr_transform(PGN1);
81 crb_addr_transform(PGN0);
82 crb_addr_transform(PGSI);
83 crb_addr_transform(PGSD);
84 crb_addr_transform(PGS3);
85 crb_addr_transform(PGS2);
86 crb_addr_transform(PGS1);
87 crb_addr_transform(PGS0);
88 crb_addr_transform(PS);
89 crb_addr_transform(PH);
90 crb_addr_transform(NIU);
91 crb_addr_transform(I2Q);
92 crb_addr_transform(EG);
93 crb_addr_transform(MN);
94 crb_addr_transform(MS);
95 crb_addr_transform(CAS2);
96 crb_addr_transform(CAS1);
97 crb_addr_transform(CAS0);
98 crb_addr_transform(CAM);
99 crb_addr_transform(C2C1);
100 crb_addr_transform(C2C0);
1fcca1a5 101 crb_addr_transform(SMB);
e4c93c81
DP		 102 crb_addr_transform(OCM0);
103 crb_addr_transform(I2C0);
3d396eb1
AK		 104}
105
2956640d 106void netxen_release_rx_buffers(struct netxen_adapter *adapter)
3d396eb1 107{
2956640d 108 struct netxen_recv_context *recv_ctx;
48bfd1e0 109 struct nx_host_rds_ring *rds_ring;
2956640d 110 struct netxen_rx_buffer *rx_buf;
becf46a0
DP		 111 int i, ring;
112
113 recv_ctx = &adapter->recv_ctx;
114 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
115 rds_ring = &recv_ctx->rds_rings[ring];
438627c7 116 for (i = 0; i < rds_ring->num_desc; ++i) {
becf46a0
DP		 117 rx_buf = &(rds_ring->rx_buf_arr[i]);
118 if (rx_buf->state == NETXEN_BUFFER_FREE)
119 continue;
120 pci_unmap_single(adapter->pdev,
121 rx_buf->dma,
122 rds_ring->dma_size,
123 PCI_DMA_FROMDEVICE);
124 if (rx_buf->skb != NULL)
125 dev_kfree_skb_any(rx_buf->skb);
2956640d
DP		 126 }
127 }
128}
129
130void netxen_release_tx_buffers(struct netxen_adapter *adapter)
131{
132 struct netxen_cmd_buffer *cmd_buf;
133 struct netxen_skb_frag *buffrag;
134 int i, j;
4ea528a1 135 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
2956640d 136
d877f1e3
DP		 137 cmd_buf = tx_ring->cmd_buf_arr;
138 for (i = 0; i < tx_ring->num_desc; i++) {
2956640d
DP		 139 buffrag = cmd_buf->frag_array;
140 if (buffrag->dma) {
141 pci_unmap_single(adapter->pdev, buffrag->dma,
142 buffrag->length, PCI_DMA_TODEVICE);
143 buffrag->dma = 0ULL;
144 }
145 for (j = 0; j < cmd_buf->frag_count; j++) {
146 buffrag++;
147 if (buffrag->dma) {
148 pci_unmap_page(adapter->pdev, buffrag->dma,
149 buffrag->length,
150 PCI_DMA_TODEVICE);
151 buffrag->dma = 0ULL;
152 }
153 }
2956640d
DP		 154 if (cmd_buf->skb) {
155 dev_kfree_skb_any(cmd_buf->skb);
156 cmd_buf->skb = NULL;
157 }
158 cmd_buf++;
159 }
160}
161
162void netxen_free_sw_resources(struct netxen_adapter *adapter)
163{
164 struct netxen_recv_context *recv_ctx;
48bfd1e0 165 struct nx_host_rds_ring *rds_ring;
d877f1e3 166 struct nx_host_tx_ring *tx_ring;
becf46a0
DP		 167 int ring;
168
169 recv_ctx = &adapter->recv_ctx;
4ea528a1
DP		 170
171 if (recv_ctx->rds_rings == NULL)
172 goto skip_rds;
173
becf46a0
DP		 174 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
175 rds_ring = &recv_ctx->rds_rings[ring];
f2333a01
F		 176 vfree(rds_ring->rx_buf_arr);
177 rds_ring->rx_buf_arr = NULL;
2956640d 178 }
4ea528a1
DP		 179 kfree(recv_ctx->rds_rings);
180
181skip_rds:
182 if (adapter->tx_ring == NULL)
183 return;
becf46a0 184
4ea528a1 185 tx_ring = adapter->tx_ring;
f2333a01 186 vfree(tx_ring->cmd_buf_arr);
011f4ea0
AKS		 187 kfree(tx_ring);
188 adapter->tx_ring = NULL;
2956640d
DP		 189}
190
191int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
192{
193 struct netxen_recv_context *recv_ctx;
48bfd1e0 194 struct nx_host_rds_ring *rds_ring;
d8b100c5 195 struct nx_host_sds_ring *sds_ring;
4ea528a1 196 struct nx_host_tx_ring *tx_ring;
2956640d 197 struct netxen_rx_buffer *rx_buf;
4ea528a1 198 int ring, i, size;
2956640d
DP		 199
200 struct netxen_cmd_buffer *cmd_buf_arr;
201 struct net_device *netdev = adapter->netdev;
d877f1e3 202 struct pci_dev *pdev = adapter->pdev;
2956640d 203
4ea528a1
DP		 204 size = sizeof(struct nx_host_tx_ring);
205 tx_ring = kzalloc(size, GFP_KERNEL);
206 if (tx_ring == NULL) {
207 dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
208 netdev->name);
209 return -ENOMEM;
210 }
211 adapter->tx_ring = tx_ring;
212
d877f1e3 213 tx_ring->num_desc = adapter->num_txd;
b2af9cb0 214 tx_ring->txq = netdev_get_tx_queue(netdev, 0);
4ea528a1
DP		 215
216 cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
2956640d 217 if (cmd_buf_arr == NULL) {
d877f1e3 218 dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
2956640d
DP		 219 netdev->name);
220 return -ENOMEM;
221 }
d877f1e3
DP		 222 memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
223 tx_ring->cmd_buf_arr = cmd_buf_arr;
2956640d 224
becf46a0 225 recv_ctx = &adapter->recv_ctx;
4ea528a1
DP		 226
227 size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
228 rds_ring = kzalloc(size, GFP_KERNEL);
229 if (rds_ring == NULL) {
230 dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
231 netdev->name);
232 return -ENOMEM;
233 }
234 recv_ctx->rds_rings = rds_ring;
235
becf46a0
DP		 236 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
237 rds_ring = &recv_ctx->rds_rings[ring];
438627c7
DP		 238 switch (ring) {
239 case RCV_RING_NORMAL:
240 rds_ring->num_desc = adapter->num_rxd;
becf46a0
DP		 241 if (adapter->ahw.cut_through) {
242 rds_ring->dma_size =
243 NX_CT_DEFAULT_RX_BUF_LEN;
48bfd1e0 244 rds_ring->skb_size =
becf46a0
DP		 245 NX_CT_DEFAULT_RX_BUF_LEN;
246 } else {
9b08beba
DP		 247 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
248 rds_ring->dma_size =
249 NX_P3_RX_BUF_MAX_LEN;
250 else
251 rds_ring->dma_size =
252 NX_P2_RX_BUF_MAX_LEN;
becf46a0 253 rds_ring->skb_size =
9b08beba 254 rds_ring->dma_size + NET_IP_ALIGN;
becf46a0
DP		 255 }
256 break;
2956640d 257
438627c7
DP		 258 case RCV_RING_JUMBO:
259 rds_ring->num_desc = adapter->num_jumbo_rxd;
becf46a0
DP		 260 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
261 rds_ring->dma_size =
262 NX_P3_RX_JUMBO_BUF_MAX_LEN;
263 else
264 rds_ring->dma_size =
265 NX_P2_RX_JUMBO_BUF_MAX_LEN;
bc75e5bf
DP		 266
267 if (adapter->capabilities & NX_CAP0_HW_LRO)
268 rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
269
becf46a0
DP		 270 rds_ring->skb_size =
271 rds_ring->dma_size + NET_IP_ALIGN;
272 break;
2956640d 273
becf46a0 274 case RCV_RING_LRO:
438627c7 275 rds_ring->num_desc = adapter->num_lro_rxd;
9b08beba
DP		 276 rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
277 rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
becf46a0
DP		 278 break;
279
280 }
281 rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
d8b100c5 282 vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
becf46a0
DP		 283 if (rds_ring->rx_buf_arr == NULL) {
284 printk(KERN_ERR "%s: Failed to allocate "
285 "rx buffer ring %d\n",
286 netdev->name, ring);
287 /* free whatever was already allocated */
288 goto err_out;
289 }
d8b100c5 290 memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
becf46a0
DP		 291 INIT_LIST_HEAD(&rds_ring->free_list);
292 /*
293 * Now go through all of them, set reference handles
294 * and put them in the queues.
295 */
becf46a0 296 rx_buf = rds_ring->rx_buf_arr;
4ea528a1 297 for (i = 0; i < rds_ring->num_desc; i++) {
becf46a0
DP		 298 list_add_tail(&rx_buf->list,
299 &rds_ring->free_list);
300 rx_buf->ref_handle = i;
301 rx_buf->state = NETXEN_BUFFER_FREE;
302 rx_buf++;
3d396eb1 303 }
d8b100c5
DP		 304 spin_lock_init(&rds_ring->lock);
305 }
306
307 for (ring = 0; ring < adapter->max_sds_rings; ring++) {
308 sds_ring = &recv_ctx->sds_rings[ring];
309 sds_ring->irq = adapter->msix_entries[ring].vector;
d8b100c5
DP		 310 sds_ring->adapter = adapter;
311 sds_ring->num_desc = adapter->num_rxd;
312
313 for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
314 INIT_LIST_HEAD(&sds_ring->free_list[i]);
3d396eb1 315 }
2956640d
DP		 316
317 return 0;
318
319err_out:
320 netxen_free_sw_resources(adapter);
321 return -ENOMEM;
3d396eb1
AK		 322}
323
3d396eb1
AK		 324/*
325 * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
326 * address to external PCI CRB address.
327 */
993fb90c 328static u32 netxen_decode_crb_addr(u32 addr)
3d396eb1
AK		 329{
330 int i;
e0e20a1a 331 u32 base_addr, offset, pci_base;
3d396eb1
AK		 332
333 crb_addr_transform_setup();
334
335 pci_base = NETXEN_ADDR_ERROR;
336 base_addr = addr & 0xfff00000;
337 offset = addr & 0x000fffff;
338
339 for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
340 if (crb_addr_xform[i] == base_addr) {
341 pci_base = i << 20;
342 break;
343 }
344 }
345 if (pci_base == NETXEN_ADDR_ERROR)
346 return pci_base;
347 else
348 return (pci_base + offset);
349}
350
c9517e58 351#define NETXEN_MAX_ROM_WAIT_USEC 100
3d396eb1 352
993fb90c 353static int netxen_wait_rom_done(struct netxen_adapter *adapter)
3d396eb1
AK		 354{
355 long timeout = 0;
356 long done = 0;
357
27c915a4
DP		 358 cond_resched();
359
3d396eb1 360 while (done == 0) {
f98a9f69 361 done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
3d396eb1 362 done &= 2;
c9517e58
DP		 363 if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
364 dev_err(&adapter->pdev->dev,
365 "Timeout reached waiting for rom done");
3d396eb1
AK		 366 return -EIO;
367 }
c9517e58 368 udelay(1);
3d396eb1
AK		 369 }
370 return 0;
371}
372
993fb90c
AB		 373static int do_rom_fast_read(struct netxen_adapter *adapter,
374 int addr, int *valp)
3d396eb1 375{
f98a9f69
DP		 376 NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
377 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
378 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
379 NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
3d396eb1
AK		 380 if (netxen_wait_rom_done(adapter)) {
381 printk("Error waiting for rom done\n");
382 return -EIO;
383 }
384 /* reset abyte_cnt and dummy_byte_cnt */
f98a9f69 385 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
27c915a4 386 udelay(10);
f98a9f69 387 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
3d396eb1 388
f98a9f69 389 *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
3d396eb1
AK		 390 return 0;
391}
392
993fb90c
AB		 393static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
394 u8 *bytes, size_t size)
27d2ab54
AK		 395{
396 int addridx;
397 int ret = 0;
398
399 for (addridx = addr; addridx < (addr + size); addridx += 4) {
f305f789
AV		 400 int v;
401 ret = do_rom_fast_read(adapter, addridx, &v);
27d2ab54
AK		 402 if (ret != 0)
403 break;
f305f789 404 *(__le32 *)bytes = cpu_to_le32(v);
27d2ab54
AK		 405 bytes += 4;
406 }
407
408 return ret;
409}
410
411int
4790654c 412netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
27d2ab54
AK		 413 u8 *bytes, size_t size)
414{
415 int ret;
416
c9517e58 417 ret = netxen_rom_lock(adapter);
27d2ab54
AK		 418 if (ret < 0)
419 return ret;
420
421 ret = do_rom_fast_read_words(adapter, addr, bytes, size);
422
423 netxen_rom_unlock(adapter);
424 return ret;
425}
426
3d396eb1
AK		 427int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
428{
429 int ret;
430
c9517e58 431 if (netxen_rom_lock(adapter) != 0)
3d396eb1
AK		 432 return -EIO;
433
434 ret = do_rom_fast_read(adapter, addr, valp);
cb8011ad
AK		 435 netxen_rom_unlock(adapter);
436 return ret;
437}
438
3d396eb1
AK		 439#define NETXEN_BOARDTYPE 0x4008
440#define NETXEN_BOARDNUM 0x400c
441#define NETXEN_CHIPNUM 0x4010
3d396eb1 442
0be367bd 443int netxen_pinit_from_rom(struct netxen_adapter *adapter)
3d396eb1 444{
dcd56fdb 445 int addr, val;
27c915a4 446 int i, n, init_delay = 0;
3d396eb1 447 struct crb_addr_pair *buf;
27c915a4 448 unsigned offset;
e0e20a1a 449 u32 off;
3d396eb1
AK		 450
451 /* resetall */
c9517e58 452 netxen_rom_lock(adapter);
f98a9f69 453 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
27c915a4 454 netxen_rom_unlock(adapter);
3d396eb1 455
2956640d
DP		 456 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
457 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
27c915a4 458 (n != 0xcafecafe) ||
2956640d
DP		 459 netxen_rom_fast_read(adapter, 4, &n) != 0) {
460 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
461 "n: %08x\n", netxen_nic_driver_name, n);
3d396eb1
AK		 462 return -EIO;
463 }
2956640d
DP		 464 offset = n & 0xffffU;
465 n = (n >> 16) & 0xffffU;
466 } else {
467 if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
468 !(n & 0x80000000)) {
469 printk(KERN_ERR "%s: ERROR Reading crb_init area: "
470 "n: %08x\n", netxen_nic_driver_name, n);
471 return -EIO;
3d396eb1 472 }
2956640d
DP		 473 offset = 1;
474 n &= ~0x80000000;
475 }
476
0be367bd 477 if (n >= 1024) {
2956640d
DP		 478 printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
479 " initialized.\n", __func__, n);
480 return -EIO;
481 }
3d396eb1 482
2956640d
DP		 483 buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
484 if (buf == NULL) {
485 printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
486 netxen_nic_driver_name);
487 return -ENOMEM;
488 }
0be367bd 489
2956640d
DP		 490 for (i = 0; i < n; i++) {
491 if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
584dbe94
DM		 492 netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
493 kfree(buf);
2956640d 494 return -EIO;
584dbe94 495 }
2956640d
DP		 496
497 buf[i].addr = addr;
498 buf[i].data = val;
499
2956640d 500 }
0be367bd 501
2956640d
DP		 502 for (i = 0; i < n; i++) {
503
504 off = netxen_decode_crb_addr(buf[i].addr);
505 if (off == NETXEN_ADDR_ERROR) {
506 printk(KERN_ERR"CRB init value out of range %x\n",
1fcca1a5 507 buf[i].addr);
2956640d
DP		 508 continue;
509 }
510 off += NETXEN_PCI_CRBSPACE;
0be367bd
AKS		 511
512 if (off & 1)
513 continue;
514
2956640d
DP		 515 /* skipping cold reboot MAGIC */
516 if (off == NETXEN_CAM_RAM(0x1fc))
517 continue;
518
519 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
8bee0a91
DP		 520 if (off == (NETXEN_CRB_I2C0 + 0x1c))
521 continue;
2956640d
DP		 522 /* do not reset PCI */
523 if (off == (ROMUSB_GLB + 0xbc))
1fcca1a5 524 continue;
27c915a4
DP		 525 if (off == (ROMUSB_GLB + 0xa8))
526 continue;
527 if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
528 continue;
529 if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
530 continue;
531 if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
532 continue;
e7473f12
AKS		 533 if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
534 continue;
0be367bd
AKS		 535 if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
536 !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
2956640d
DP		 537 buf[i].data = 0x1020;
538 /* skip the function enable register */
539 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
3d396eb1 540 continue;
2956640d
DP		 541 if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
542 continue;
543 if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
544 continue;
545 }
3d396eb1 546
27c915a4 547 init_delay = 1;
2956640d
DP		 548 /* After writing this register, HW needs time for CRB */
549 /* to quiet down (else crb_window returns 0xffffffff) */
550 if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
27c915a4 551 init_delay = 1000;
2956640d 552 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
3d396eb1 553 /* hold xdma in reset also */
cb8011ad 554 buf[i].data = NETXEN_NIC_XDMA_RESET;
27c915a4 555 buf[i].data = 0x8000ff;
3d396eb1 556 }
2956640d 557 }
3d396eb1 558
f98a9f69 559 NXWR32(adapter, off, buf[i].data);
3d396eb1 560
27c915a4 561 msleep(init_delay);
2956640d
DP		 562 }
563 kfree(buf);
3d396eb1 564
2956640d 565 /* disable_peg_cache_all */
3d396eb1 566
2956640d
DP		 567 /* unreset_net_cache */
568 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
f98a9f69
DP		 569 val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
570 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
3d396eb1 571 }
2956640d
DP		 572
573 /* p2dn replyCount */
f98a9f69 574 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
2956640d 575 /* disable_peg_cache 0 */
f98a9f69 576 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
2956640d 577 /* disable_peg_cache 1 */
f98a9f69 578 NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
2956640d
DP		 579
580 /* peg_clr_all */
581
582 /* peg_clr 0 */
f98a9f69
DP		 583 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
584 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
2956640d 585 /* peg_clr 1 */
f98a9f69
DP		 586 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
587 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
2956640d 588 /* peg_clr 2 */
f98a9f69
DP		 589 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
590 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
2956640d 591 /* peg_clr 3 */
f98a9f69
DP		 592 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
593 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
3d396eb1
AK		 594 return 0;
595}
596
f50330f9
AKS		 597static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
598{
599 uint32_t i;
600 struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
601 __le32 entries = cpu_to_le32(directory->num_entries);
602
603 for (i = 0; i < entries; i++) {
604
605 __le32 offs = cpu_to_le32(directory->findex) +
606 (i * cpu_to_le32(directory->entry_size));
607 __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
608
609 if (tab_type == section)
610 return (struct uni_table_desc *) &unirom[offs];
611 }
612
613 return NULL;
614}
615
616static int
617nx_set_product_offs(struct netxen_adapter *adapter)
618{
619 struct uni_table_desc *ptab_descr;
620 const u8 *unirom = adapter->fw->data;
621 uint32_t i;
622 __le32 entries;
623
634d7df8
DP		 624 int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
625 1 : netxen_p3_has_mn(adapter);
626
f50330f9
AKS		 627 ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
628 if (ptab_descr == NULL)
629 return -1;
630
631 entries = cpu_to_le32(ptab_descr->num_entries);
632
634d7df8 633nomn:
f50330f9
AKS		 634 for (i = 0; i < entries; i++) {
635
636 __le32 flags, file_chiprev, offs;
637 u8 chiprev = adapter->ahw.revision_id;
f50330f9
AKS		 638 uint32_t flagbit;
639
640 offs = cpu_to_le32(ptab_descr->findex) +
641 (i * cpu_to_le32(ptab_descr->entry_size));
642 flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
643 file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
644 NX_UNI_CHIP_REV_OFF));
645
646 flagbit = mn_present ? 1 : 2;
647
648 if ((chiprev == file_chiprev) &&
649 ((1ULL << flagbit) & flags)) {
650 adapter->file_prd_off = offs;
651 return 0;
652 }
653 }
654
634d7df8
DP		 655 if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
656 mn_present = 0;
657 goto nomn;
658 }
659
f50330f9
AKS		 660 return -1;
661}
662
663
664static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
665 u32 section, u32 idx_offset)
666{
667 const u8 *unirom = adapter->fw->data;
668 int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
669 idx_offset));
670 struct uni_table_desc *tab_desc;
671 __le32 offs;
672
673 tab_desc = nx_get_table_desc(unirom, section);
674
675 if (tab_desc == NULL)
676 return NULL;
677
678 offs = cpu_to_le32(tab_desc->findex) +
679 (cpu_to_le32(tab_desc->entry_size) * idx);
680
681 return (struct uni_data_desc *)&unirom[offs];
682}
683
684static u8 *
685nx_get_bootld_offs(struct netxen_adapter *adapter)
686{
687 u32 offs = NETXEN_BOOTLD_START;
688
689 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
690 offs = cpu_to_le32((nx_get_data_desc(adapter,
691 NX_UNI_DIR_SECT_BOOTLD,
692 NX_UNI_BOOTLD_IDX_OFF))->findex);
693
694 return (u8 *)&adapter->fw->data[offs];
695}
696
697static u8 *
698nx_get_fw_offs(struct netxen_adapter *adapter)
699{
700 u32 offs = NETXEN_IMAGE_START;
701
702 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
703 offs = cpu_to_le32((nx_get_data_desc(adapter,
704 NX_UNI_DIR_SECT_FW,
705 NX_UNI_FIRMWARE_IDX_OFF))->findex);
706
707 return (u8 *)&adapter->fw->data[offs];
708}
709
710static __le32
711nx_get_fw_size(struct netxen_adapter *adapter)
712{
713 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
714 return cpu_to_le32((nx_get_data_desc(adapter,
715 NX_UNI_DIR_SECT_FW,
716 NX_UNI_FIRMWARE_IDX_OFF))->size);
717 else
718 return cpu_to_le32(
719 *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
720}
721
722static __le32
723nx_get_fw_version(struct netxen_adapter *adapter)
724{
725 struct uni_data_desc *fw_data_desc;
726 const struct firmware *fw = adapter->fw;
727 __le32 major, minor, sub;
728 const u8 *ver_str;
729 int i, ret = 0;
730
731 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
732
733 fw_data_desc = nx_get_data_desc(adapter,
734 NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
735 ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
736 cpu_to_le32(fw_data_desc->size) - 17;
737
738 for (i = 0; i < 12; i++) {
739 if (!strncmp(&ver_str[i], "REV=", 4)) {
740 ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
741 &major, &minor, &sub);
742 break;
743 }
744 }
745
746 if (ret != 3)
747 return 0;
748
749 return major + (minor << 8) + (sub << 16);
750
751 } else
752 return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
753}
754
755static __le32
756nx_get_bios_version(struct netxen_adapter *adapter)
757{
758 const struct firmware *fw = adapter->fw;
759 __le32 bios_ver, prd_off = adapter->file_prd_off;
760
761 if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
762 bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
763 + NX_UNI_BIOS_VERSION_OFF));
764 return (bios_ver << 24) + ((bios_ver >> 8) & 0xff00) +
765 (bios_ver >> 24);
766 } else
767 return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
768
769}
770
67c38fc6
DP		 771int
772netxen_need_fw_reset(struct netxen_adapter *adapter)
773{
774 u32 count, old_count;
775 u32 val, version, major, minor, build;
776 int i, timeout;
777 u8 fw_type;
778
779 /* NX2031 firmware doesn't support heartbit */
780 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
781 return 1;
782
783 /* last attempt had failed */
784 if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
785 return 1;
786
581e8ae4 787 old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
67c38fc6
DP		 788
789 for (i = 0; i < 10; i++) {
790
791 timeout = msleep_interruptible(200);
792 if (timeout) {
793 NXWR32(adapter, CRB_CMDPEG_STATE,
794 PHAN_INITIALIZE_FAILED);
795 return -EINTR;
796 }
797
798 count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
799 if (count != old_count)
800 break;
801 }
802
803 /* firmware is dead */
804 if (count == old_count)
805 return 1;
806
807 /* check if we have got newer or different file firmware */
808 if (adapter->fw) {
809
f50330f9 810 val = nx_get_fw_version(adapter);
67c38fc6 811
67c38fc6
DP		 812 version = NETXEN_DECODE_VERSION(val);
813
814 major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
815 minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
816 build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
817
818 if (version > NETXEN_VERSION_CODE(major, minor, build))
819 return 1;
820
f50330f9
AKS		 821 if (version == NETXEN_VERSION_CODE(major, minor, build) &&
822 adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
67c38fc6
DP		 823
824 val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
825 fw_type = (val & 0x4) ?
826 NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
827
828 if (adapter->fw_type != fw_type)
829 return 1;
830 }
831 }
832
833 return 0;
834}
835
836static char *fw_name[] = {
7e8e5d97
DP		 837 NX_P2_MN_ROMIMAGE_NAME,
838 NX_P3_CT_ROMIMAGE_NAME,
839 NX_P3_MN_ROMIMAGE_NAME,
840 NX_UNIFIED_ROMIMAGE_NAME,
841 NX_FLASH_ROMIMAGE_NAME,
67c38fc6
DP		 842};
843
f7185c71
DP		 844int
845netxen_load_firmware(struct netxen_adapter *adapter)
846{
847 u64 *ptr64;
848 u32 i, flashaddr, size;
849 const struct firmware *fw = adapter->fw;
67c38fc6
DP		 850 struct pci_dev *pdev = adapter->pdev;
851
852 dev_info(&pdev->dev, "loading firmware from %s\n",
853 fw_name[adapter->fw_type]);
f7185c71
DP		 854
855 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
856 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
857
858 if (fw) {
859 __le64 data;
860
861 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
862
f50330f9 863 ptr64 = (u64 *)nx_get_bootld_offs(adapter);
f7185c71
DP		 864 flashaddr = NETXEN_BOOTLD_START;
865
866 for (i = 0; i < size; i++) {
867 data = cpu_to_le64(ptr64[i]);
f50330f9
AKS		 868
869 if (adapter->pci_mem_write(adapter, flashaddr, data))
1f5e055d
AKS		 870 return -EIO;
871
f7185c71
DP		 872 flashaddr += 8;
873 }
874
f50330f9 875 size = (__force u32)nx_get_fw_size(adapter) / 8;
f7185c71 876
f50330f9 877 ptr64 = (u64 *)nx_get_fw_offs(adapter);
f7185c71
DP		 878 flashaddr = NETXEN_IMAGE_START;
879
880 for (i = 0; i < size; i++) {
881 data = cpu_to_le64(ptr64[i]);
882
883 if (adapter->pci_mem_write(adapter,
1f5e055d 884 flashaddr, data))
f7185c71
DP		 885 return -EIO;
886
887 flashaddr += 8;
888 }
889 } else {
f78c0850
AKS		 890 u64 data;
891 u32 hi, lo;
f7185c71 892
f78c0850 893 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
f7185c71
DP		 894 flashaddr = NETXEN_BOOTLD_START;
895
896 for (i = 0; i < size; i++) {
897 if (netxen_rom_fast_read(adapter,
1f5e055d 898 flashaddr, (int *)&lo) != 0)
f78c0850
AKS		 899 return -EIO;
900 if (netxen_rom_fast_read(adapter,
1f5e055d 901 flashaddr + 4, (int *)&hi) != 0)
f7185c71
DP		 902 return -EIO;
903
f78c0850
AKS		 904 /* hi, lo are already in host endian byteorder */
905 data = (((u64)hi << 32) | lo);
906
f7185c71 907 if (adapter->pci_mem_write(adapter,
1f5e055d 908 flashaddr, data))
f7185c71
DP		 909 return -EIO;
910
f78c0850 911 flashaddr += 8;
f7185c71
DP		 912 }
913 }
914 msleep(1);
915
0be367bd
AKS		 916 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
917 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
918 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
919 } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
f7185c71
DP		 920 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
921 else {
922 NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
923 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
924 }
925
926 return 0;
927}
928
929static int
f50330f9 930netxen_validate_firmware(struct netxen_adapter *adapter)
f7185c71
DP		 931{
932 __le32 val;
f50330f9 933 u32 ver, min_ver, bios, min_size;
f7185c71
DP		 934 struct pci_dev *pdev = adapter->pdev;
935 const struct firmware *fw = adapter->fw;
f50330f9 936 u8 fw_type = adapter->fw_type;
f7185c71 937
f50330f9
AKS		 938 if (fw_type == NX_UNIFIED_ROMIMAGE) {
939 if (nx_set_product_offs(adapter))
940 return -EINVAL;
941
942 min_size = NX_UNI_FW_MIN_SIZE;
943 } else {
944 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
945 if ((__force u32)val != NETXEN_BDINFO_MAGIC)
946 return -EINVAL;
f7185c71 947
f50330f9
AKS		 948 min_size = NX_FW_MIN_SIZE;
949 }
950
951 if (fw->size < min_size)
f7185c71
DP		 952 return -EINVAL;
953
f50330f9 954 val = nx_get_fw_version(adapter);
f7185c71
DP		 955
956 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
957 min_ver = NETXEN_VERSION_CODE(4, 0, 216);
958 else
959 min_ver = NETXEN_VERSION_CODE(3, 4, 216);
960
98e31bb0 961 ver = NETXEN_DECODE_VERSION(val);
f7185c71 962
98e31bb0 963 if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
f7185c71
DP		 964 dev_err(&pdev->dev,
965 "%s: firmware version %d.%d.%d unsupported\n",
f50330f9 966 fw_name[fw_type], _major(ver), _minor(ver), _build(ver));
f7185c71
DP		 967 return -EINVAL;
968 }
969
f50330f9 970 val = nx_get_bios_version(adapter);
f7185c71
DP		 971 netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
972 if ((__force u32)val != bios) {
973 dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
f50330f9 974 fw_name[fw_type]);
f7185c71
DP		 975 return -EINVAL;
976 }
977
978 /* check if flashed firmware is newer */
979 if (netxen_rom_fast_read(adapter,
980 NX_FW_VERSION_OFFSET, (int *)&val))
981 return -EIO;
98e31bb0
DP		 982 val = NETXEN_DECODE_VERSION(val);
983 if (val > ver) {
984 dev_info(&pdev->dev, "%s: firmware is older than flash\n",
f50330f9 985 fw_name[fw_type]);
f7185c71 986 return -EINVAL;
98e31bb0 987 }
f7185c71
DP		 988
989 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
990 return 0;
991}
992
f50330f9
AKS		 993static void
994nx_get_next_fwtype(struct netxen_adapter *adapter)
995{
996 u8 fw_type;
997
998 switch (adapter->fw_type) {
999 case NX_UNKNOWN_ROMIMAGE:
1000 fw_type = NX_UNIFIED_ROMIMAGE;
1001 break;
1002
1003 case NX_UNIFIED_ROMIMAGE:
1004 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
1005 fw_type = NX_FLASH_ROMIMAGE;
1006 else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1007 fw_type = NX_P2_MN_ROMIMAGE;
1008 else if (netxen_p3_has_mn(adapter))
1009 fw_type = NX_P3_MN_ROMIMAGE;
1010 else
1011 fw_type = NX_P3_CT_ROMIMAGE;
1012 break;
1013
1014 case NX_P3_MN_ROMIMAGE:
1015 fw_type = NX_P3_CT_ROMIMAGE;
1016 break;
1017
1018 case NX_P2_MN_ROMIMAGE:
1019 case NX_P3_CT_ROMIMAGE:
1020 default:
1021 fw_type = NX_FLASH_ROMIMAGE;
1022 break;
1023 }
1024
1025 adapter->fw_type = fw_type;
1026}
1027
6598b169
DP		 1028static int
1029netxen_p3_has_mn(struct netxen_adapter *adapter)
f7185c71
DP		 1030{
1031 u32 capability, flashed_ver;
f7185c71
DP		 1032 capability = 0;
1033
634d7df8
DP		 1034 /* NX2031 always had MN */
1035 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1036 return 1;
1037
f7185c71
DP		 1038 netxen_rom_fast_read(adapter,
1039 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
98e31bb0
DP		 1040 flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
1041
f7185c71 1042 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
6598b169 1043
f7185c71 1044 capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
6598b169
DP		 1045 if (capability & NX_PEG_TUNE_MN_PRESENT)
1046 return 1;
1047 }
1048 return 0;
1049}
1050
1051void netxen_request_firmware(struct netxen_adapter *adapter)
1052{
6598b169
DP		 1053 struct pci_dev *pdev = adapter->pdev;
1054 int rc = 0;
1055
f50330f9 1056 adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
f7185c71 1057
f50330f9
AKS		 1058next:
1059 nx_get_next_fwtype(adapter);
f7185c71 1060
f50330f9 1061 if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
f7185c71 1062 adapter->fw = NULL;
f50330f9
AKS		 1063 } else {
1064 rc = request_firmware(&adapter->fw,
1065 fw_name[adapter->fw_type], &pdev->dev);
1066 if (rc != 0)
1067 goto next;
1068
1069 rc = netxen_validate_firmware(adapter);
1070 if (rc != 0) {
1071 release_firmware(adapter->fw);
f7185c71 1072 msleep(1);
f50330f9 1073 goto next;
f7185c71 1074 }
f7185c71 1075 }
f7185c71
DP		 1076}
1077
1078
1079void
1080netxen_release_firmware(struct netxen_adapter *adapter)
1081{
1082 if (adapter->fw)
1083 release_firmware(adapter->fw);
db4cfd8a 1084 adapter->fw = NULL;
f7185c71
DP		 1085}
1086
83ac51fa 1087int netxen_init_dummy_dma(struct netxen_adapter *adapter)
ed25ffa1 1088{
83ac51fa
DP		 1089 u64 addr;
1090 u32 hi, lo;
ed25ffa1 1091
83ac51fa
DP		 1092 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
1093 return 0;
1094
1095 adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
ed25ffa1
AK		 1096 NETXEN_HOST_DUMMY_DMA_SIZE,
1097 &adapter->dummy_dma.phys_addr);
1098 if (adapter->dummy_dma.addr == NULL) {
83ac51fa
DP		 1099 dev_err(&adapter->pdev->dev,
1100 "ERROR: Could not allocate dummy DMA memory\n");
ed25ffa1
AK		 1101 return -ENOMEM;
1102 }
1103
1104 addr = (uint64_t) adapter->dummy_dma.phys_addr;
1105 hi = (addr >> 32) & 0xffffffff;
1106 lo = addr & 0xffffffff;
1107
f98a9f69
DP		 1108 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
1109 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
ed25ffa1
AK		 1110
1111 return 0;
1112}
1113
83ac51fa
DP		 1114/*
1115 * NetXen DMA watchdog control:
1116 *
1117 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
1118 * Bit 1 : disable_request => 1 req disable dma watchdog
1119 * Bit 2 : enable_request => 1 req enable dma watchdog
1120 * Bit 3-31 : unused
1121 */
1122void netxen_free_dummy_dma(struct netxen_adapter *adapter)
ed25ffa1 1123{
15eef1e1 1124 int i = 100;
83ac51fa
DP		 1125 u32 ctrl;
1126
1127 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
1128 return;
15eef1e1
DP		 1129
1130 if (!adapter->dummy_dma.addr)
1131 return;
439b454e 1132
83ac51fa
DP		 1133 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
1134 if ((ctrl & 0x1) != 0) {
1135 NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
1136
1137 while ((ctrl & 0x1) != 0) {
1138
439b454e 1139 msleep(50);
83ac51fa
DP		 1140
1141 ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
1142
1143 if (--i == 0)
439b454e 1144 break;
83ac51fa 1145 };
15eef1e1 1146 }
439b454e 1147
15eef1e1
DP		 1148 if (i) {
1149 pci_free_consistent(adapter->pdev,
1150 NETXEN_HOST_DUMMY_DMA_SIZE,
1151 adapter->dummy_dma.addr,
1152 adapter->dummy_dma.phys_addr);
1153 adapter->dummy_dma.addr = NULL;
83ac51fa
DP		 1154 } else
1155 dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
ed25ffa1
AK		 1156}
1157
96acb6eb 1158int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
3d396eb1
AK		 1159{
1160 u32 val = 0;
2956640d 1161 int retries = 60;
3d396eb1 1162
96f2ebd2
DP		 1163 if (pegtune_val)
1164 return 0;
1165
1166 do {
1167 val = NXRD32(adapter, CRB_CMDPEG_STATE);
96acb6eb 1168
96f2ebd2
DP		 1169 switch (val) {
1170 case PHAN_INITIALIZE_COMPLETE:
1171 case PHAN_INITIALIZE_ACK:
1172 return 0;
1173 case PHAN_INITIALIZE_FAILED:
1174 goto out_err;
1175 default:
1176 break;
1177 }
96acb6eb 1178
96f2ebd2 1179 msleep(500);
2956640d 1180
96f2ebd2 1181 } while (--retries);
2956640d 1182
96f2ebd2 1183 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
96acb6eb 1184
96f2ebd2
DP		 1185out_err:
1186 dev_warn(&adapter->pdev->dev, "firmware init failed\n");
1187 return -EIO;
3d396eb1
AK		 1188}
1189
56a00787
DP		 1190static int
1191netxen_receive_peg_ready(struct netxen_adapter *adapter)
2956640d
DP		 1192{
1193 u32 val = 0;
1194 int retries = 2000;
1195
1196 do {
f98a9f69 1197 val = NXRD32(adapter, CRB_RCVPEG_STATE);
2956640d
DP		 1198
1199 if (val == PHAN_PEG_RCV_INITIALIZED)
1200 return 0;
1201
1202 msleep(10);
1203
1204 } while (--retries);
1205
1206 if (!retries) {
1207 printk(KERN_ERR "Receive Peg initialization not "
1208 "complete, state: 0x%x.\n", val);
1209 return -EIO;
1210 }
1211
1212 return 0;
1213}
1214
56a00787
DP		 1215int netxen_init_firmware(struct netxen_adapter *adapter)
1216{
1217 int err;
1218
1219 err = netxen_receive_peg_ready(adapter);
1220 if (err)
1221 return err;
1222
f98a9f69
DP		 1223 NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
1224 NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
1225 NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
1226 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
56a00787
DP		 1227
1228 return err;
1229}
1230
3bf26ce3
DP		 1231static void
1232netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
1233{
1234 u32 cable_OUI;
1235 u16 cable_len;
1236 u16 link_speed;
1237 u8 link_status, module, duplex, autoneg;
1238 struct net_device *netdev = adapter->netdev;
1239
1240 adapter->has_link_events = 1;
1241
1242 cable_OUI = msg->body[1] & 0xffffffff;
1243 cable_len = (msg->body[1] >> 32) & 0xffff;
1244 link_speed = (msg->body[1] >> 48) & 0xffff;
1245
1246 link_status = msg->body[2] & 0xff;
1247 duplex = (msg->body[2] >> 16) & 0xff;
1248 autoneg = (msg->body[2] >> 24) & 0xff;
1249
1250 module = (msg->body[2] >> 8) & 0xff;
1251 if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
1252 printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
1253 netdev->name, cable_OUI, cable_len);
1254 } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
1255 printk(KERN_INFO "%s: unsupported cable length %d\n",
1256 netdev->name, cable_len);
1257 }
1258
1259 netxen_advert_link_change(adapter, link_status);
1260
1261 /* update link parameters */
1262 if (duplex == LINKEVENT_FULL_DUPLEX)
1263 adapter->link_duplex = DUPLEX_FULL;
1264 else
1265 adapter->link_duplex = DUPLEX_HALF;
1266 adapter->module_type = module;
1267 adapter->link_autoneg = autoneg;
1268 adapter->link_speed = link_speed;
1269}
1270
1271static void
1272netxen_handle_fw_message(int desc_cnt, int index,
1273 struct nx_host_sds_ring *sds_ring)
1274{
1275 nx_fw_msg_t msg;
1276 struct status_desc *desc;
1277 int i = 0, opcode;
1278
1279 while (desc_cnt > 0 && i < 8) {
1280 desc = &sds_ring->desc_head[index];
1281 msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
1282 msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
1283
1284 index = get_next_index(index, sds_ring->num_desc);
1285 desc_cnt--;
1286 }
1287
1288 opcode = netxen_get_nic_msg_opcode(msg.body[0]);
1289 switch (opcode) {
1290 case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
1291 netxen_handle_linkevent(sds_ring->adapter, &msg);
1292 break;
1293 default:
1294 break;
1295 }
1296}
1297
d8b100c5
DP		 1298static int
1299netxen_alloc_rx_skb(struct netxen_adapter *adapter,
1300 struct nx_host_rds_ring *rds_ring,
1301 struct netxen_rx_buffer *buffer)
1302{
1303 struct sk_buff *skb;
1304 dma_addr_t dma;
1305 struct pci_dev *pdev = adapter->pdev;
1306
1307 buffer->skb = dev_alloc_skb(rds_ring->skb_size);
1308 if (!buffer->skb)
1309 return 1;
1310
1311 skb = buffer->skb;
1312
1313 if (!adapter->ahw.cut_through)
1314 skb_reserve(skb, 2);
1315
1316 dma = pci_map_single(pdev, skb->data,
1317 rds_ring->dma_size, PCI_DMA_FROMDEVICE);
1318
1319 if (pci_dma_mapping_error(pdev, dma)) {
1320 dev_kfree_skb_any(skb);
1321 buffer->skb = NULL;
1322 return 1;
1323 }
1324
1325 buffer->skb = skb;
1326 buffer->dma = dma;
1327 buffer->state = NETXEN_BUFFER_BUSY;
1328
1329 return 0;
1330}
1331
d9e651bc
DP		 1332static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
1333 struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
1334{
1335 struct netxen_rx_buffer *buffer;
1336 struct sk_buff *skb;
1337
1338 buffer = &rds_ring->rx_buf_arr[index];
1339
1340 pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
1341 PCI_DMA_FROMDEVICE);
1342
1343 skb = buffer->skb;
1344 if (!skb)
1345 goto no_skb;
1346
1347 if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
1348 adapter->stats.csummed++;
1349 skb->ip_summed = CHECKSUM_UNNECESSARY;
1350 } else
1351 skb->ip_summed = CHECKSUM_NONE;
1352
1353 skb->dev = adapter->netdev;
1354
1355 buffer->skb = NULL;
d9e651bc
DP		 1356no_skb:
1357 buffer->state = NETXEN_BUFFER_FREE;
d9e651bc
DP		 1358 return skb;
1359}
1360
d8b100c5 1361static struct netxen_rx_buffer *
9b3ef55c 1362netxen_process_rcv(struct netxen_adapter *adapter,
c1c00ab8
DP		 1363 struct nx_host_sds_ring *sds_ring,
1364 int ring, u64 sts_data0)
3d396eb1 1365{
3176ff3e 1366 struct net_device *netdev = adapter->netdev;
becf46a0 1367 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
3d396eb1
AK		 1368 struct netxen_rx_buffer *buffer;
1369 struct sk_buff *skb;
c1c00ab8
DP		 1370 struct nx_host_rds_ring *rds_ring;
1371 int index, length, cksum, pkt_offset;
3d396eb1 1372
c1c00ab8
DP		 1373 if (unlikely(ring >= adapter->max_rds_rings))
1374 return NULL;
1375
1376 rds_ring = &recv_ctx->rds_rings[ring];
1377
1378 index = netxen_get_sts_refhandle(sts_data0);
1379 if (unlikely(index >= rds_ring->num_desc))
d8b100c5 1380 return NULL;
438627c7 1381
48bfd1e0 1382 buffer = &rds_ring->rx_buf_arr[index];
3d396eb1 1383
c1c00ab8
DP		 1384 length = netxen_get_sts_totallength(sts_data0);
1385 cksum = netxen_get_sts_status(sts_data0);
1386 pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
1387
d9e651bc
DP		 1388 skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
1389 if (!skb)
d8b100c5 1390 return buffer;
200eef20 1391
9b3ef55c
DP		 1392 if (length > rds_ring->skb_size)
1393 skb_put(skb, rds_ring->skb_size);
1394 else
1395 skb_put(skb, length);
d9e651bc 1396
9b3ef55c
DP		 1397
1398 if (pkt_offset)
1399 skb_pull(skb, pkt_offset);
ed25ffa1 1400
bc75e5bf 1401 skb->truesize = skb->len + sizeof(struct sk_buff);
3d396eb1
AK		 1402 skb->protocol = eth_type_trans(skb, netdev);
1403
a92e9e65 1404 napi_gro_receive(&sds_ring->napi, skb);
d9e651bc 1405
1bb482f8 1406 adapter->stats.rx_pkts++;
0ddc110c 1407 adapter->stats.rxbytes += length;
d8b100c5
DP		 1408
1409 return buffer;
3d396eb1
AK		 1410}
1411
c1c00ab8
DP		 1412#define TCP_HDR_SIZE 20
1413#define TCP_TS_OPTION_SIZE 12
1414#define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
1415
1416static struct netxen_rx_buffer *
1417netxen_process_lro(struct netxen_adapter *adapter,
1418 struct nx_host_sds_ring *sds_ring,
1419 int ring, u64 sts_data0, u64 sts_data1)
1420{
1421 struct net_device *netdev = adapter->netdev;
1422 struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
1423 struct netxen_rx_buffer *buffer;
1424 struct sk_buff *skb;
1425 struct nx_host_rds_ring *rds_ring;
1426 struct iphdr *iph;
1427 struct tcphdr *th;
1428 bool push, timestamp;
1429 int l2_hdr_offset, l4_hdr_offset;
1430 int index;
1431 u16 lro_length, length, data_offset;
1432 u32 seq_number;
1433
1434 if (unlikely(ring > adapter->max_rds_rings))
1435 return NULL;
1436
1437 rds_ring = &recv_ctx->rds_rings[ring];
1438
1439 index = netxen_get_lro_sts_refhandle(sts_data0);
1440 if (unlikely(index > rds_ring->num_desc))
1441 return NULL;
1442
1443 buffer = &rds_ring->rx_buf_arr[index];
1444
1445 timestamp = netxen_get_lro_sts_timestamp(sts_data0);
1446 lro_length = netxen_get_lro_sts_length(sts_data0);
1447 l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
1448 l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
1449 push = netxen_get_lro_sts_push_flag(sts_data0);
1450 seq_number = netxen_get_lro_sts_seq_number(sts_data1);
1451
1452 skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
1453 if (!skb)
1454 return buffer;
1455
1456 if (timestamp)
1457 data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
1458 else
1459 data_offset = l4_hdr_offset + TCP_HDR_SIZE;
1460
1461 skb_put(skb, lro_length + data_offset);
1462
bc75e5bf 1463 skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
c1c00ab8
DP		 1464
1465 skb_pull(skb, l2_hdr_offset);
1466 skb->protocol = eth_type_trans(skb, netdev);
1467
1468 iph = (struct iphdr *)skb->data;
1469 th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
1470
1471 length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
1472 iph->tot_len = htons(length);
1473 iph->check = 0;
1474 iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
1475 th->psh = push;
1476 th->seq = htonl(seq_number);
1477
1bb482f8
NK		 1478 length = skb->len;
1479
c1c00ab8
DP		 1480 netif_receive_skb(skb);
1481
1bb482f8
NK		 1482 adapter->stats.lro_pkts++;
1483 adapter->stats.rxbytes += length;
1484
c1c00ab8
DP		 1485 return buffer;
1486}
1487
d8b100c5
DP		 1488#define netxen_merge_rx_buffers(list, head) \
1489 do { list_splice_tail_init(list, head); } while (0);
1490
becf46a0 1491int
d8b100c5 1492netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
3d396eb1 1493{
d8b100c5
DP		 1494 struct netxen_adapter *adapter = sds_ring->adapter;
1495
1496 struct list_head *cur;
1497
0ddc110c 1498 struct status_desc *desc;
d8b100c5
DP		 1499 struct netxen_rx_buffer *rxbuf;
1500
1501 u32 consumer = sds_ring->consumer;
1502
9b3ef55c 1503 int count = 0;
c1c00ab8
DP		 1504 u64 sts_data0, sts_data1;
1505 int opcode, ring = 0, desc_cnt;
3d396eb1 1506
3d396eb1 1507 while (count < max) {
d8b100c5 1508 desc = &sds_ring->desc_head[consumer];
c1c00ab8 1509 sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
0ddc110c 1510
c1c00ab8 1511 if (!(sts_data0 & STATUS_OWNER_HOST))
3d396eb1 1512 break;
d9e651bc 1513
c1c00ab8 1514 desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
3bf26ce3 1515
c1c00ab8 1516 opcode = netxen_get_sts_opcode(sts_data0);
d9e651bc 1517
3bf26ce3
DP		 1518 switch (opcode) {
1519 case NETXEN_NIC_RXPKT_DESC:
1520 case NETXEN_OLD_RXPKT_DESC:
6598b169 1521 case NETXEN_NIC_SYN_OFFLOAD:
c1c00ab8
DP		 1522 ring = netxen_get_sts_type(sts_data0);
1523 rxbuf = netxen_process_rcv(adapter, sds_ring,
1524 ring, sts_data0);
1525 break;
1526 case NETXEN_NIC_LRO_DESC:
1527 ring = netxen_get_lro_sts_type(sts_data0);
1528 sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
1529 rxbuf = netxen_process_lro(adapter, sds_ring,
1530 ring, sts_data0, sts_data1);
3bf26ce3
DP		 1531 break;
1532 case NETXEN_NIC_RESPONSE_DESC:
1533 netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
1534 default:
1535 goto skip;
1536 }
1537
1538 WARN_ON(desc_cnt > 1);
1539
d8b100c5
DP		 1540 if (rxbuf)
1541 list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
1542
3bf26ce3
DP		 1543skip:
1544 for (; desc_cnt > 0; desc_cnt--) {
1545 desc = &sds_ring->desc_head[consumer];
1546 desc->status_desc_data[0] =
1547 cpu_to_le64(STATUS_OWNER_PHANTOM);
1548 consumer = get_next_index(consumer, sds_ring->num_desc);
1549 }
3d396eb1
AK		 1550 count++;
1551 }
0ddc110c 1552
d8b100c5
DP		 1553 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1554 struct nx_host_rds_ring *rds_ring =
1555 &adapter->recv_ctx.rds_rings[ring];
1556
1557 if (!list_empty(&sds_ring->free_list[ring])) {
1558 list_for_each(cur, &sds_ring->free_list[ring]) {
1559 rxbuf = list_entry(cur,
1560 struct netxen_rx_buffer, list);
1561 netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
1562 }
1563 spin_lock(&rds_ring->lock);
1564 netxen_merge_rx_buffers(&sds_ring->free_list[ring],
1565 &rds_ring->free_list);
1566 spin_unlock(&rds_ring->lock);
1567 }
1568
1569 netxen_post_rx_buffers_nodb(adapter, rds_ring);
1570 }
3d396eb1 1571
3d396eb1 1572 if (count) {
d8b100c5 1573 sds_ring->consumer = consumer;
195c5f98 1574 NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
3d396eb1
AK		 1575 }
1576
1577 return count;
1578}
1579
1580/* Process Command status ring */
05aaa02d 1581int netxen_process_cmd_ring(struct netxen_adapter *adapter)
3d396eb1 1582{
d877f1e3 1583 u32 sw_consumer, hw_consumer;
ba53e6b4 1584 int count = 0, i;
3d396eb1 1585 struct netxen_cmd_buffer *buffer;
ba53e6b4
DP		 1586 struct pci_dev *pdev = adapter->pdev;
1587 struct net_device *netdev = adapter->netdev;
3d396eb1 1588 struct netxen_skb_frag *frag;
ba53e6b4 1589 int done = 0;
4ea528a1 1590 struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
3d396eb1 1591
d8b100c5
DP		 1592 if (!spin_trylock(&adapter->tx_clean_lock))
1593 return 1;
1594
d877f1e3 1595 sw_consumer = tx_ring->sw_consumer;
d877f1e3 1596 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
3d396eb1 1597
d877f1e3
DP		 1598 while (sw_consumer != hw_consumer) {
1599 buffer = &tx_ring->cmd_buf_arr[sw_consumer];
53a01e00 1600 if (buffer->skb) {
1601 frag = &buffer->frag_array[0];
3d396eb1
AK		 1602 pci_unmap_single(pdev, frag->dma, frag->length,
1603 PCI_DMA_TODEVICE);
96acb6eb 1604 frag->dma = 0ULL;
3d396eb1 1605 for (i = 1; i < buffer->frag_count; i++) {
3d396eb1
AK		 1606 frag++; /* Get the next frag */
1607 pci_unmap_page(pdev, frag->dma, frag->length,
1608 PCI_DMA_TODEVICE);
96acb6eb 1609 frag->dma = 0ULL;
3d396eb1
AK		 1610 }
1611
ba53e6b4 1612 adapter->stats.xmitfinished++;
53a01e00 1613 dev_kfree_skb_any(buffer->skb);
1614 buffer->skb = NULL;
3d396eb1
AK		 1615 }
1616
d877f1e3 1617 sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
ba53e6b4
DP		 1618 if (++count >= MAX_STATUS_HANDLE)
1619 break;
3d396eb1 1620 }
3d396eb1 1621
22527864 1622 if (count && netif_running(netdev)) {
cb2107be
DP		 1623 tx_ring->sw_consumer = sw_consumer;
1624
ba53e6b4 1625 smp_mb();
cb2107be 1626
22527864 1627 if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
b2af9cb0 1628 __netif_tx_lock(tx_ring->txq, smp_processor_id());
74c520da 1629 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) {
cb2107be 1630 netif_wake_queue(netdev);
74c520da
AKS		 1631 adapter->tx_timeo_cnt = 0;
1632 }
b2af9cb0 1633 __netif_tx_unlock(tx_ring->txq);
3d396eb1
AK		 1634 }
1635 }
ed25ffa1
AK		 1636 /*
1637 * If everything is freed up to consumer then check if the ring is full
1638 * If the ring is full then check if more needs to be freed and
1639 * schedule the call back again.
1640 *
1641 * This happens when there are 2 CPUs. One could be freeing and the
1642 * other filling it. If the ring is full when we get out of here and
1643 * the card has already interrupted the host then the host can miss the
1644 * interrupt.
1645 *
1646 * There is still a possible race condition and the host could miss an
1647 * interrupt. The card has to take care of this.
1648 */
d877f1e3
DP		 1649 hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
1650 done = (sw_consumer == hw_consumer);
d8b100c5 1651 spin_unlock(&adapter->tx_clean_lock);
3d396eb1 1652
ed25ffa1 1653 return (done);
3d396eb1
AK		 1654}
1655
becf46a0 1656void
d8b100c5
DP		 1657netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1658 struct nx_host_rds_ring *rds_ring)
3d396eb1 1659{
3d396eb1
AK		 1660 struct rcv_desc *pdesc;
1661 struct netxen_rx_buffer *buffer;
d8b100c5 1662 int producer, count = 0;
ed25ffa1 1663 netxen_ctx_msg msg = 0;
d9e651bc 1664 struct list_head *head;
3d396eb1 1665
48bfd1e0 1666 producer = rds_ring->producer;
d9e651bc 1667
d8b100c5
DP		 1668 spin_lock(&rds_ring->lock);
1669 head = &rds_ring->free_list;
d9e651bc
DP		 1670 while (!list_empty(head)) {
1671
d8b100c5 1672 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
6f703406 1673
d8b100c5
DP		 1674 if (!buffer->skb) {
1675 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1676 break;
6f703406
DP		 1677 }
1678
1679 count++;
d9e651bc
DP		 1680 list_del(&buffer->list);
1681
ed25ffa1 1682 /* make a rcv descriptor */
6f703406 1683 pdesc = &rds_ring->desc_head[producer];
d8b100c5 1684 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
ed33ebe4 1685 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1686 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
6f703406 1687
438627c7 1688 producer = get_next_index(producer, rds_ring->num_desc);
ed25ffa1 1689 }
d8b100c5 1690 spin_unlock(&rds_ring->lock);
9b3ef55c 1691
ed25ffa1 1692 if (count) {
48bfd1e0 1693 rds_ring->producer = producer;
195c5f98 1694 NXWRIO(adapter, rds_ring->crb_rcv_producer,
438627c7 1695 (producer-1) & (rds_ring->num_desc-1));
48bfd1e0 1696
4f96b988 1697 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
ed25ffa1
AK		 1698 /*
1699 * Write a doorbell msg to tell phanmon of change in
1700 * receive ring producer
48bfd1e0 1701 * Only for firmware version < 4.0.0
ed25ffa1
AK		 1702 */
1703 netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
1704 netxen_set_msg_privid(msg);
1705 netxen_set_msg_count(msg,
438627c7
DP		 1706 ((producer - 1) &
1707 (rds_ring->num_desc - 1)));
3176ff3e 1708 netxen_set_msg_ctxid(msg, adapter->portnum);
ed25ffa1 1709 netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
f03b0ebd
DP		 1710 NXWRIO(adapter, DB_NORMALIZE(adapter,
1711 NETXEN_RCV_PRODUCER_OFFSET), msg);
48bfd1e0 1712 }
ed25ffa1
AK		 1713 }
1714}
1715
becf46a0 1716static void
d8b100c5
DP		 1717netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
1718 struct nx_host_rds_ring *rds_ring)
ed25ffa1 1719{
ed25ffa1
AK		 1720 struct rcv_desc *pdesc;
1721 struct netxen_rx_buffer *buffer;
d8b100c5 1722 int producer, count = 0;
d9e651bc 1723 struct list_head *head;
ed25ffa1 1724
48bfd1e0 1725 producer = rds_ring->producer;
d8b100c5
DP		 1726 if (!spin_trylock(&rds_ring->lock))
1727 return;
1728
d9e651bc 1729 head = &rds_ring->free_list;
d9e651bc
DP		 1730 while (!list_empty(head)) {
1731
d8b100c5 1732 buffer = list_entry(head->next, struct netxen_rx_buffer, list);
6f703406 1733
d8b100c5
DP		 1734 if (!buffer->skb) {
1735 if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
1736 break;
6f703406
DP		 1737 }
1738
1739 count++;
d9e651bc
DP		 1740 list_del(&buffer->list);
1741
3d396eb1 1742 /* make a rcv descriptor */
6f703406 1743 pdesc = &rds_ring->desc_head[producer];
ed33ebe4 1744 pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
48bfd1e0 1745 pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
3d396eb1 1746 pdesc->addr_buffer = cpu_to_le64(buffer->dma);
6f703406 1747
438627c7 1748 producer = get_next_index(producer, rds_ring->num_desc);
3d396eb1
AK		 1749 }
1750
3d396eb1 1751 if (count) {
48bfd1e0 1752 rds_ring->producer = producer;
195c5f98 1753 NXWRIO(adapter, rds_ring->crb_rcv_producer,
438627c7 1754 (producer - 1) & (rds_ring->num_desc - 1));
3d396eb1 1755 }
d8b100c5 1756 spin_unlock(&rds_ring->lock);
3d396eb1
AK		 1757}
1758
3d396eb1
AK		 1759void netxen_nic_clear_stats(struct netxen_adapter *adapter)
1760{
3d396eb1 1761 memset(&adapter->stats, 0, sizeof(adapter->stats));
3176ff3e 1762 return;
3d396eb1
AK		 1763}
1764
Linux 6.x block layer and io_uring tree(s)