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Merge branch 'tracing/core' of git://git.kernel.org/pub/scm/linux/kernel/git/frederic...
[linux-2.6-block.git] / drivers / net / netxen / netxen_nic_hw.c
CommitLineData
3d396eb1 1/*
5d242f1c 2 * Copyright (C) 2003 - 2009 NetXen, Inc.
13af7a6e 3 * Copyright (C) 2009 - QLogic Corporation.
3d396eb1 4 * All rights reserved.
80922fbc 5 *
3d396eb1
AK		 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
cb8011ad 10 *
3d396eb1
AK		 11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
cb8011ad 15 *
3d396eb1
AK		 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
80922fbc 20 *
3d396eb1
AK		 21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.
80922fbc 23 *
3d396eb1
AK		 24 */
25
26#include "netxen_nic.h"
27#include "netxen_nic_hw.h"
3d396eb1 28
c9bdd4b5
ACM		 29#include <net/ip.h>
30
3ce06a32
DP		 31#define MASK(n) ((1ULL<<(n))-1)
32#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
33#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
6abb4b83 34#define OCM_WIN_P3P(addr) (addr & 0xffc0000)
3ce06a32
DP		 35#define MS_WIN(addr) (addr & 0x0ffc0000)
36
37#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
38
39#define CRB_BLK(off) ((off >> 20) & 0x3f)
40#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
41#define CRB_WINDOW_2M (0x130060)
42#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
43#define CRB_INDIRECT_2M (0x1e0000UL)
44
f03b0ebd
DP		 45static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
46 void __iomem *addr, u32 data);
47static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
48 void __iomem *addr);
49
e98e3350
DP		 50#ifndef readq
51static inline u64 readq(void __iomem *addr)
52{
53 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
54}
55#endif
56
57#ifndef writeq
58static inline void writeq(u64 val, void __iomem *addr)
59{
60 writel(((u32) (val)), (addr));
61 writel(((u32) (val >> 32)), (addr + 4));
62}
63#endif
64
1fbe6323
DP		 65#define ADDR_IN_RANGE(addr, low, high) \
66 (((addr) < (high)) && ((addr) >= (low)))
67
68#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
69 ((adapter)->ahw.pci_base0 + (off))
70#define PCI_OFFSET_SECOND_RANGE(adapter, off) \
71 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
72#define PCI_OFFSET_THIRD_RANGE(adapter, off) \
73 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
74
75static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
76 unsigned long off)
77{
78 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
79 return PCI_OFFSET_FIRST_RANGE(adapter, off);
80
81 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
82 return PCI_OFFSET_SECOND_RANGE(adapter, off);
83
84 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
85 return PCI_OFFSET_THIRD_RANGE(adapter, off);
86
87 return NULL;
88}
89
ea7eaa39
DP		 90static crb_128M_2M_block_map_t
91crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
3ce06a32
DP		 92 {{{0, 0, 0, 0} } }, /* 0: PCI */
93 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
94 {1, 0x0110000, 0x0120000, 0x130000},
95 {1, 0x0120000, 0x0122000, 0x124000},
96 {1, 0x0130000, 0x0132000, 0x126000},
97 {1, 0x0140000, 0x0142000, 0x128000},
98 {1, 0x0150000, 0x0152000, 0x12a000},
99 {1, 0x0160000, 0x0170000, 0x110000},
100 {1, 0x0170000, 0x0172000, 0x12e000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {1, 0x01e0000, 0x01e0800, 0x122000},
108 {0, 0x0000000, 0x0000000, 0x000000} } },
109 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
110 {{{0, 0, 0, 0} } }, /* 3: */
111 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
112 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
113 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
114 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
115 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {1, 0x08f0000, 0x08f2000, 0x172000} } },
131 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {1, 0x09f0000, 0x09f2000, 0x176000} } },
147 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
163 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
179 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
180 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
181 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
182 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
183 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
184 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
185 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
186 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
187 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
188 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
189 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
190 {{{0, 0, 0, 0} } }, /* 23: */
191 {{{0, 0, 0, 0} } }, /* 24: */
192 {{{0, 0, 0, 0} } }, /* 25: */
193 {{{0, 0, 0, 0} } }, /* 26: */
194 {{{0, 0, 0, 0} } }, /* 27: */
195 {{{0, 0, 0, 0} } }, /* 28: */
196 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
197 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
198 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
199 {{{0} } }, /* 32: PCI */
200 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
201 {1, 0x2110000, 0x2120000, 0x130000},
202 {1, 0x2120000, 0x2122000, 0x124000},
203 {1, 0x2130000, 0x2132000, 0x126000},
204 {1, 0x2140000, 0x2142000, 0x128000},
205 {1, 0x2150000, 0x2152000, 0x12a000},
206 {1, 0x2160000, 0x2170000, 0x110000},
207 {1, 0x2170000, 0x2172000, 0x12e000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000},
213 {0, 0x0000000, 0x0000000, 0x000000},
214 {0, 0x0000000, 0x0000000, 0x000000},
215 {0, 0x0000000, 0x0000000, 0x000000} } },
216 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
217 {{{0} } }, /* 35: */
218 {{{0} } }, /* 36: */
219 {{{0} } }, /* 37: */
220 {{{0} } }, /* 38: */
221 {{{0} } }, /* 39: */
222 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
223 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
224 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
225 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
226 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
227 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
228 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
229 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
230 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
231 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
232 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
233 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
234 {{{0} } }, /* 52: */
235 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
236 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
237 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
238 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
239 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
240 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
241 {{{0} } }, /* 59: I2C0 */
242 {{{0} } }, /* 60: I2C1 */
243 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
244 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
245 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
246};
247
248/*
249 * top 12 bits of crb internal address (hub, agent)
250 */
251static unsigned crb_hub_agt[64] =
252{
253 0,
254 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
255 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
256 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
257 0,
258 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
259 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
260 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
261 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
262 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
263 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
264 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
265 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
266 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
267 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
268 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
269 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
280 0,
281 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
282 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
283 0,
284 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
285 0,
286 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
287 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
288 0,
289 0,
290 0,
291 0,
292 0,
293 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
294 0,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
299 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
301 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
302 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
303 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
304 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
305 0,
306 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
307 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
308 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
309 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
310 0,
311 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
312 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
313 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
314 0,
315 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
316 0,
317};
318
3d396eb1
AK		 319/* PCI Windowing for DDR regions. */
320
3ce06a32 321#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
3d396eb1 322
c9517e58
DP		 323#define NETXEN_PCIE_SEM_TIMEOUT 10000
324
325int
326netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
327{
328 int done = 0, timeout = 0;
329
330 while (!done) {
331 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
332 if (done == 1)
333 break;
334 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
7cecdca1 335 return -EIO;
c9517e58
DP		 336 msleep(1);
337 }
338
339 if (id_reg)
340 NXWR32(adapter, id_reg, adapter->portnum);
341
342 return 0;
343}
344
345void
346netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
347{
581e8ae4 348 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
c9517e58
DP		 349}
350
3ad4467c
DP		 351int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
352{
353 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
354 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
355 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
356 }
357
358 return 0;
359}
360
361/* Disable an XG interface */
362int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
363{
364 __u32 mac_cfg;
365 u32 port = adapter->physical_port;
366
367 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
368 return 0;
369
370 if (port > NETXEN_NIU_MAX_XG_PORTS)
371 return -EINVAL;
372
373 mac_cfg = 0;
374 if (NXWR32(adapter,
375 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
376 return -EIO;
377 return 0;
378}
379
623621b0
DP		 380#define NETXEN_UNICAST_ADDR(port, index) \
381 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
382#define NETXEN_MCAST_ADDR(port, index) \
383 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
384#define MAC_HI(addr) \
385 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
386#define MAC_LO(addr) \
387 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
388
3ad4467c
DP		 389int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
390{
a7483b0a
NK		 391 u32 mac_cfg;
392 u32 cnt = 0;
393 __u32 reg = 0x0200;
3ad4467c 394 u32 port = adapter->physical_port;
a7483b0a 395 u16 board_type = adapter->ahw.board_type;
3ad4467c
DP		 396
397 if (port > NETXEN_NIU_MAX_XG_PORTS)
398 return -EINVAL;
399
a7483b0a
NK		 400 mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port));
401 mac_cfg &= ~0x4;
402 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
3ad4467c 403
a7483b0a
NK		 404 if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) ||
405 (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ))
406 reg = (0x20 << port);
3ad4467c 407
a7483b0a
NK		 408 NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg);
409
410 mdelay(10);
411
412 while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20)
413 mdelay(10);
414
415 if (cnt < 20) {
416
417 reg = NXRD32(adapter,
418 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
419
420 if (mode == NETXEN_NIU_PROMISC_MODE)
421 reg = (reg | 0x2000UL);
422 else
423 reg = (reg & ~0x2000UL);
424
425 if (mode == NETXEN_NIU_ALLMULTI_MODE)
426 reg = (reg | 0x1000UL);
427 else
428 reg = (reg & ~0x1000UL);
429
430 NXWR32(adapter,
431 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
432 }
433
434 mac_cfg |= 0x4;
435 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
3ad4467c
DP		 436
437 return 0;
438}
439
440int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
441{
442 u32 mac_hi, mac_lo;
443 u32 reg_hi, reg_lo;
444
445 u8 phy = adapter->physical_port;
446
447 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
448 return -EINVAL;
449
450 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
451 mac_hi = addr[2] | ((u32)addr[3] << 8) |
452 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
453
454 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
455 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
456
457 /* write twice to flush */
458 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
459 return -EIO;
460 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
461 return -EIO;
462
463 return 0;
464}
465
623621b0
DP		 466static int
467netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
468{
469 u32 val = 0;
470 u16 port = adapter->physical_port;
5d09e534 471 u8 *addr = adapter->mac_addr;
623621b0
DP		 472
473 if (adapter->mc_enabled)
474 return 0;
475
f98a9f69 476 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
623621b0 477 val |= (1UL << (28+port));
f98a9f69 478 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
623621b0
DP		 479
480 /* add broadcast addr to filter */
481 val = 0xffffff;
f98a9f69
DP		 482 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
483 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
623621b0
DP		 484
485 /* add station addr to filter */
486 val = MAC_HI(addr);
f98a9f69 487 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
623621b0 488 val = MAC_LO(addr);
f98a9f69 489 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
623621b0
DP		 490
491 adapter->mc_enabled = 1;
492 return 0;
493}
494
495static int
496netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
497{
498 u32 val = 0;
499 u16 port = adapter->physical_port;
5d09e534 500 u8 *addr = adapter->mac_addr;
623621b0
DP		 501
502 if (!adapter->mc_enabled)
503 return 0;
504
f98a9f69 505 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
623621b0 506 val &= ~(1UL << (28+port));
f98a9f69 507 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
623621b0
DP		 508
509 val = MAC_HI(addr);
f98a9f69 510 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
623621b0 511 val = MAC_LO(addr);
f98a9f69 512 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
623621b0 513
f98a9f69
DP		 514 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
515 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
623621b0
DP		 516
517 adapter->mc_enabled = 0;
518 return 0;
519}
520
521static int
522netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
523 int index, u8 *addr)
524{
525 u32 hi = 0, lo = 0;
526 u16 port = adapter->physical_port;
527
528 lo = MAC_LO(addr);
529 hi = MAC_HI(addr);
530
f98a9f69
DP		 531 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
532 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
623621b0
DP		 533
534 return 0;
535}
536
c9fc891f 537void netxen_p2_nic_set_multi(struct net_device *netdev)
3d396eb1 538{
3176ff3e 539 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1 540 struct dev_mc_list *mc_ptr;
623621b0
DP		 541 u8 null_addr[6];
542 int index = 0;
543
544 memset(null_addr, 0, 6);
3d396eb1 545
3d396eb1 546 if (netdev->flags & IFF_PROMISC) {
623621b0
DP		 547
548 adapter->set_promisc(adapter,
549 NETXEN_NIU_PROMISC_MODE);
550
551 /* Full promiscuous mode */
552 netxen_nic_disable_mcast_filter(adapter);
553
554 return;
555 }
556
557 if (netdev->mc_count == 0) {
558 adapter->set_promisc(adapter,
559 NETXEN_NIU_NON_PROMISC_MODE);
560 netxen_nic_disable_mcast_filter(adapter);
561 return;
562 }
563
564 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
565 if (netdev->flags & IFF_ALLMULTI ||
566 netdev->mc_count > adapter->max_mc_count) {
567 netxen_nic_disable_mcast_filter(adapter);
568 return;
3d396eb1 569 }
623621b0
DP		 570
571 netxen_nic_enable_mcast_filter(adapter);
572
573 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
574 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
575
576 if (index != netdev->mc_count)
577 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
578 netxen_nic_driver_name, netdev->name);
579
580 /* Clear out remaining addresses */
581 for (; index < adapter->max_mc_count; index++)
582 netxen_nic_set_mcast_addr(adapter, index, null_addr);
3d396eb1
AK		 583}
584
c9fc891f
DP		 585static int
586netxen_send_cmd_descs(struct netxen_adapter *adapter,
d877f1e3 587 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
c9fc891f 588{
d877f1e3 589 u32 i, producer, consumer;
c9fc891f
DP		 590 struct netxen_cmd_buffer *pbuf;
591 struct cmd_desc_type0 *cmd_desc;
d877f1e3 592 struct nx_host_tx_ring *tx_ring;
c9fc891f
DP		 593
594 i = 0;
595
db4cfd8a
DP		 596 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
597 return -EIO;
598
4ea528a1 599 tx_ring = adapter->tx_ring;
b2af9cb0 600 __netif_tx_lock_bh(tx_ring->txq);
03e678ee 601
d877f1e3
DP		 602 producer = tx_ring->producer;
603 consumer = tx_ring->sw_consumer;
604
b2af9cb0
DP		 605 if (nr_desc >= netxen_tx_avail(tx_ring)) {
606 netif_tx_stop_queue(tx_ring->txq);
607 __netif_tx_unlock_bh(tx_ring->txq);
d877f1e3
DP		 608 return -EBUSY;
609 }
610
c9fc891f
DP		 611 do {
612 cmd_desc = &cmd_desc_arr[i];
613
d877f1e3 614 pbuf = &tx_ring->cmd_buf_arr[producer];
c9fc891f 615 pbuf->skb = NULL;
c9fc891f 616 pbuf->frag_count = 0;
c9fc891f 617
d877f1e3 618 memcpy(&tx_ring->desc_head[producer],
c9fc891f
DP		 619 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
620
d877f1e3 621 producer = get_next_index(producer, tx_ring->num_desc);
c9fc891f
DP		 622 i++;
623
d877f1e3 624 } while (i != nr_desc);
c9fc891f 625
d877f1e3 626 tx_ring->producer = producer;
c9fc891f 627
cb2107be 628 netxen_nic_update_cmd_producer(adapter, tx_ring);
c9fc891f 629
b2af9cb0 630 __netif_tx_unlock_bh(tx_ring->txq);
03e678ee 631
c9fc891f
DP		 632 return 0;
633}
634
5cf4d323
DP		 635static int
636nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
c9fc891f 637{
c9fc891f 638 nx_nic_req_t req;
2edbb454
DP		 639 nx_mac_req_t *mac_req;
640 u64 word;
c9fc891f
DP		 641
642 memset(&req, 0, sizeof(nx_nic_req_t));
2edbb454
DP		 643 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
644
645 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
646 req.req_hdr = cpu_to_le64(word);
647
648 mac_req = (nx_mac_req_t *)&req.words[0];
649 mac_req->op = op;
650 memcpy(mac_req->mac_addr, addr, 6);
c9fc891f 651
5cf4d323
DP		 652 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
653}
654
655static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
656 u8 *addr, struct list_head *del_list)
657{
658 struct list_head *head;
659 nx_mac_list_t *cur;
660
661 /* look up if already exists */
662 list_for_each(head, del_list) {
663 cur = list_entry(head, nx_mac_list_t, list);
664
665 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
666 list_move_tail(head, &adapter->mac_list);
667 return 0;
668 }
c9fc891f
DP		 669 }
670
5cf4d323
DP		 671 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
672 if (cur == NULL) {
673 printk(KERN_ERR "%s: failed to add mac address filter\n",
674 adapter->netdev->name);
675 return -ENOMEM;
676 }
677 memcpy(cur->mac_addr, addr, ETH_ALEN);
678 list_add_tail(&cur->list, &adapter->mac_list);
679 return nx_p3_sre_macaddr_change(adapter,
680 cur->mac_addr, NETXEN_MAC_ADD);
c9fc891f
DP		 681}
682
683void netxen_p3_nic_set_multi(struct net_device *netdev)
684{
685 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f
DP		 686 struct dev_mc_list *mc_ptr;
687 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
9ad27643 688 u32 mode = VPORT_MISS_MODE_DROP;
5cf4d323
DP		 689 LIST_HEAD(del_list);
690 struct list_head *head;
691 nx_mac_list_t *cur;
c9fc891f 692
d49c9640
AKS		 693 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
694 return;
695
5cf4d323 696 list_splice_tail_init(&adapter->mac_list, &del_list);
c9fc891f 697
5d09e534 698 nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list);
5cf4d323 699 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
9ad27643
DP		 700
701 if (netdev->flags & IFF_PROMISC) {
702 mode = VPORT_MISS_MODE_ACCEPT_ALL;
703 goto send_fw_cmd;
704 }
705
706 if ((netdev->flags & IFF_ALLMULTI) ||
707 (netdev->mc_count > adapter->max_mc_count)) {
708 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
709 goto send_fw_cmd;
710 }
711
c9fc891f 712 if (netdev->mc_count > 0) {
c9fc891f
DP		 713 for (mc_ptr = netdev->mc_list; mc_ptr;
714 mc_ptr = mc_ptr->next) {
5cf4d323 715 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
c9fc891f
DP		 716 }
717 }
9ad27643
DP		 718
719send_fw_cmd:
720 adapter->set_promisc(adapter, mode);
5cf4d323
DP		 721 head = &del_list;
722 while (!list_empty(head)) {
723 cur = list_entry(head->next, nx_mac_list_t, list);
724
725 nx_p3_sre_macaddr_change(adapter,
726 cur->mac_addr, NETXEN_MAC_DEL);
727 list_del(&cur->list);
c9fc891f 728 kfree(cur);
c9fc891f
DP		 729 }
730}
731
9ad27643
DP		 732int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
733{
734 nx_nic_req_t req;
2edbb454 735 u64 word;
9ad27643
DP		 736
737 memset(&req, 0, sizeof(nx_nic_req_t));
738
2edbb454
DP		 739 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
740
741 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
742 ((u64)adapter->portnum << 16);
743 req.req_hdr = cpu_to_le64(word);
744
9ad27643
DP		 745 req.words[0] = cpu_to_le64(mode);
746
747 return netxen_send_cmd_descs(adapter,
748 (struct cmd_desc_type0 *)&req, 1);
749}
750
06e9d9f9
DP		 751void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
752{
5cf4d323
DP		 753 nx_mac_list_t *cur;
754 struct list_head *head = &adapter->mac_list;
755
756 while (!list_empty(head)) {
757 cur = list_entry(head->next, nx_mac_list_t, list);
758 nx_p3_sre_macaddr_change(adapter,
759 cur->mac_addr, NETXEN_MAC_DEL);
760 list_del(&cur->list);
06e9d9f9 761 kfree(cur);
06e9d9f9
DP		 762 }
763}
764
3d0a3cc9
DP		 765int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
766{
767 /* assuming caller has already copied new addr to netdev */
768 netxen_p3_nic_set_multi(adapter->netdev);
769 return 0;
770}
771
cd1f8160
DP		 772#define NETXEN_CONFIG_INTR_COALESCE 3
773
774/*
775 * Send the interrupt coalescing parameter set by ethtool to the card.
776 */
777int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
778{
779 nx_nic_req_t req;
2edbb454 780 u64 word;
cd1f8160
DP		 781 int rv;
782
783 memset(&req, 0, sizeof(nx_nic_req_t));
784
1bb482f8 785 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
2edbb454
DP		 786
787 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
788 req.req_hdr = cpu_to_le64(word);
cd1f8160
DP		 789
790 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
791
792 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
793 if (rv != 0) {
794 printk(KERN_ERR "ERROR. Could not send "
795 "interrupt coalescing parameters\n");
796 }
797
798 return rv;
799}
800
1bb482f8
NK		 801int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
802{
803 nx_nic_req_t req;
804 u64 word;
805 int rv = 0;
806
807 if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable)
808 return 0;
809
810 memset(&req, 0, sizeof(nx_nic_req_t));
811
812 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
813
814 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
815 req.req_hdr = cpu_to_le64(word);
816
817 req.words[0] = cpu_to_le64(enable);
818
819 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
820 if (rv != 0) {
821 printk(KERN_ERR "ERROR. Could not send "
822 "configure hw lro request\n");
823 }
824
825 adapter->flags ^= NETXEN_NIC_LRO_ENABLED;
826
827 return rv;
828}
829
fa3ce355
NK		 830int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
831{
832 nx_nic_req_t req;
833 u64 word;
834 int rv = 0;
835
836 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
837 return rv;
838
839 memset(&req, 0, sizeof(nx_nic_req_t));
840
841 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
842
843 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
844 ((u64)adapter->portnum << 16);
845 req.req_hdr = cpu_to_le64(word);
846
847 req.words[0] = cpu_to_le64(enable);
848
849 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
850 if (rv != 0) {
851 printk(KERN_ERR "ERROR. Could not send "
852 "configure bridge mode request\n");
853 }
854
855 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
856
857 return rv;
858}
859
860
d8b100c5
DP		 861#define RSS_HASHTYPE_IP_TCP 0x3
862
863int netxen_config_rss(struct netxen_adapter *adapter, int enable)
864{
865 nx_nic_req_t req;
866 u64 word;
867 int i, rv;
868
869 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
870 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
871 0x255b0ec26d5a56daULL };
872
873
874 memset(&req, 0, sizeof(nx_nic_req_t));
875 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
876
877 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
878 req.req_hdr = cpu_to_le64(word);
879
880 /*
881 * RSS request:
882 * bits 3-0: hash_method
883 * 5-4: hash_type_ipv4
884 * 7-6: hash_type_ipv6
885 * 8: enable
886 * 9: use indirection table
887 * 47-10: reserved
888 * 63-48: indirection table mask
889 */
890 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
891 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
892 ((u64)(enable & 0x1) << 8) |
893 ((0x7ULL) << 48);
894 req.words[0] = cpu_to_le64(word);
895 for (i = 0; i < 5; i++)
896 req.words[i+1] = cpu_to_le64(key[i]);
897
898
899 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
900 if (rv != 0) {
901 printk(KERN_ERR "%s: could not configure RSS\n",
902 adapter->netdev->name);
903 }
904
905 return rv;
906}
907
6598b169
DP		 908int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
909{
910 nx_nic_req_t req;
911 u64 word;
912 int rv;
913
914 memset(&req, 0, sizeof(nx_nic_req_t));
915 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
916
917 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
918 req.req_hdr = cpu_to_le64(word);
919
920 req.words[0] = cpu_to_le64(cmd);
921 req.words[1] = cpu_to_le64(ip);
922
923 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
924 if (rv != 0) {
925 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
926 adapter->netdev->name,
927 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
928 }
929 return rv;
930}
931
3bf26ce3
DP		 932int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
933{
934 nx_nic_req_t req;
935 u64 word;
936 int rv;
937
938 memset(&req, 0, sizeof(nx_nic_req_t));
939 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
940
941 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
942 req.req_hdr = cpu_to_le64(word);
22527864 943 req.words[0] = cpu_to_le64(enable | (enable << 8));
3bf26ce3
DP		 944
945 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
946 if (rv != 0) {
947 printk(KERN_ERR "%s: could not configure link notification\n",
948 adapter->netdev->name);
949 }
950
951 return rv;
952}
953
1bb482f8
NK		 954int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
955{
956 nx_nic_req_t req;
957 u64 word;
958 int rv;
959
960 memset(&req, 0, sizeof(nx_nic_req_t));
961 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
962
963 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
964 ((u64)adapter->portnum << 16) |
965 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
966
967 req.req_hdr = cpu_to_le64(word);
968
969 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
970 if (rv != 0) {
971 printk(KERN_ERR "%s: could not cleanup lro flows\n",
972 adapter->netdev->name);
973 }
974 return rv;
975}
976
3d396eb1
AK		 977/*
978 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
979 * @returns 0 on success, negative on failure
980 */
c9fc891f
DP		 981
982#define MTU_FUDGE_FACTOR 100
983
3d396eb1
AK		 984int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
985{
3176ff3e 986 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f 987 int max_mtu;
9ad27643 988 int rc = 0;
3d396eb1 989
c9fc891f
DP		 990 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
991 max_mtu = P3_MAX_MTU;
992 else
993 max_mtu = P2_MAX_MTU;
994
995 if (mtu > max_mtu) {
996 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
997 netdev->name, max_mtu);
3d396eb1
AK		 998 return -EINVAL;
999 }
1000
80922fbc 1001 if (adapter->set_mtu)
9ad27643 1002 rc = adapter->set_mtu(adapter, mtu);
3d396eb1 1003
9ad27643
DP		 1004 if (!rc)
1005 netdev->mtu = mtu;
c9fc891f 1006
9ad27643 1007 return rc;
3d396eb1
AK		 1008}
1009
3d396eb1 1010static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
f305f789 1011 int size, __le32 * buf)
3d396eb1 1012{
1e2d0059 1013 int i, v, addr;
f305f789 1014 __le32 *ptr32;
3d396eb1
AK		 1015
1016 addr = base;
1017 ptr32 = buf;
1018 for (i = 0; i < size / sizeof(u32); i++) {
f305f789 1019 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 1020 return -1;
f305f789 1021 *ptr32 = cpu_to_le32(v);
3d396eb1
AK		 1022 ptr32++;
1023 addr += sizeof(u32);
1024 }
1025 if ((char *)buf + size > (char *)ptr32) {
f305f789
AV		 1026 __le32 local;
1027 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 1028 return -1;
f305f789 1029 local = cpu_to_le32(v);
3d396eb1
AK		 1030 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1031 }
1032
1033 return 0;
1034}
1035
9dc28efe 1036int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
3d396eb1 1037{
9dc28efe
DP		 1038 __le32 *pmac = (__le32 *) mac;
1039 u32 offset;
3d396eb1 1040
06db58c0 1041 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
9dc28efe
DP		 1042
1043 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
3d396eb1 1044 return -1;
9dc28efe 1045
f305f789 1046 if (*mac == cpu_to_le64(~0ULL)) {
9dc28efe 1047
06db58c0
DP		 1048 offset = NX_OLD_MAC_ADDR_OFFSET +
1049 (adapter->portnum * sizeof(u64));
9dc28efe 1050
3d396eb1 1051 if (netxen_get_flash_block(adapter,
9dc28efe 1052 offset, sizeof(u64), pmac) == -1)
3d396eb1 1053 return -1;
9dc28efe 1054
f305f789 1055 if (*mac == cpu_to_le64(~0ULL))
3d396eb1
AK		 1056 return -1;
1057 }
1058 return 0;
1059}
1060
9dc28efe
DP		 1061int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
1062{
1063 uint32_t crbaddr, mac_hi, mac_lo;
1064 int pci_func = adapter->ahw.pci_func;
1065
1066 crbaddr = CRB_MAC_BLOCK_START +
1067 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1068
f98a9f69
DP		 1069 mac_lo = NXRD32(adapter, crbaddr);
1070 mac_hi = NXRD32(adapter, crbaddr+4);
9dc28efe 1071
9dc28efe 1072 if (pci_func & 1)
2edbb454 1073 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
9dc28efe 1074 else
2edbb454 1075 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
9dc28efe
DP		 1076
1077 return 0;
1078}
1079
3d396eb1
AK		 1080/*
1081 * Changes the CRB window to the specified window.
1082 */
195c5f98 1083static void
907fa120
DP		 1084netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter,
1085 u32 window)
3d396eb1
AK		 1086{
1087 void __iomem *offset;
907fa120
DP		 1088 int count = 10;
1089 u8 func = adapter->ahw.pci_func;
3d396eb1 1090
907fa120 1091 if (adapter->ahw.crb_win == window)
3d396eb1 1092 return;
907fa120 1093
e4c93c81
DP		 1094 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1095 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
3d396eb1 1096
907fa120
DP		 1097 writel(window, offset);
1098 do {
1099 if (window == readl(offset))
1100 break;
3d396eb1 1101
907fa120
DP		 1102 if (printk_ratelimit())
1103 dev_warn(&adapter->pdev->dev,
1104 "failed to set CRB window to %d\n",
1105 (window == NETXEN_WINDOW_ONE));
1106 udelay(1);
3d396eb1 1107
907fa120 1108 } while (--count > 0);
3d396eb1 1109
907fa120
DP		 1110 if (count > 0)
1111 adapter->ahw.crb_win = window;
3d396eb1
AK		 1112}
1113
3ce06a32 1114/*
7cecdca1 1115 * Returns < 0 if off is not valid,
3ce06a32
DP		 1116 * 1 if window access is needed. 'off' is set to offset from
1117 * CRB space in 128M pci map
1118 * 0 if no window access is needed. 'off' is set to 2M addr
1119 * In: 'off' is offset from base in 128M pci map
1120 */
1121static int
a9ac07de
DP		 1122netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
1123 ulong off, void __iomem **addr)
3ce06a32 1124{
3ce06a32
DP		 1125 crb_128M_2M_sub_block_map_t *m;
1126
1127
a9ac07de 1128 if ((off >= NETXEN_CRB_MAX) || (off < NETXEN_PCI_CRBSPACE))
7cecdca1 1129 return -EINVAL;
3ce06a32 1130
a9ac07de 1131 off -= NETXEN_PCI_CRBSPACE;
3ce06a32
DP		 1132
1133 /*
1134 * Try direct map
1135 */
a9ac07de 1136 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
3ce06a32 1137
a9ac07de
DP		 1138 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1139 *addr = adapter->ahw.pci_base0 + m->start_2M +
1140 (off - m->start_128M);
3ce06a32
DP		 1141 return 0;
1142 }
1143
1144 /*
1145 * Not in direct map, use crb window
1146 */
a9ac07de
DP		 1147 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M +
1148 (off & MASK(16));
3ce06a32
DP		 1149 return 1;
1150}
1151
1152/*
1153 * In: 'off' is offset from CRB space in 128M pci map
1154 * Out: 'off' is 2M pci map addr
1155 * side effect: lock crb window
1156 */
1157static void
a9ac07de 1158netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong off)
3ce06a32 1159{
907fa120
DP		 1160 u32 window;
1161 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
3ce06a32 1162
a9ac07de
DP		 1163 off -= NETXEN_PCI_CRBSPACE;
1164
1165 window = CRB_HI(off);
907fa120
DP		 1166
1167 if (adapter->ahw.crb_win == window)
a9ac07de 1168 return;
907fa120
DP		 1169
1170 writel(window, addr);
1171 if (readl(addr) != window) {
1172 if (printk_ratelimit())
1173 dev_warn(&adapter->pdev->dev,
1174 "failed to set CRB window to %d off 0x%lx\n",
a9ac07de 1175 window, off);
3ce06a32 1176 }
907fa120 1177 adapter->ahw.crb_win = window;
3ce06a32
DP		 1178}
1179
f58dbd73
NK		 1180static void __iomem *
1181netxen_nic_map_indirect_address_128M(struct netxen_adapter *adapter,
1182 ulong win_off, void __iomem **mem_ptr)
1183{
1184 ulong off = win_off;
1185 void __iomem *addr;
1186 resource_size_t mem_base;
1187
1188 if (ADDR_IN_WINDOW1(win_off))
1189 off = NETXEN_CRB_NORMAL(win_off);
1190
1191 addr = pci_base_offset(adapter, off);
1192 if (addr)
1193 return addr;
1194
1195 if (adapter->ahw.pci_len0 == 0)
1196 off -= NETXEN_PCI_CRBSPACE;
1197
1198 mem_base = pci_resource_start(adapter->pdev, 0);
1199 *mem_ptr = ioremap(mem_base + (off & PAGE_MASK), PAGE_SIZE);
1200 if (*mem_ptr)
1201 addr = *mem_ptr + (off & (PAGE_SIZE - 1));
1202
1203 return addr;
1204}
1205
195c5f98 1206static int
1fbe6323 1207netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
3d396eb1 1208{
195c5f98 1209 unsigned long flags;
f58dbd73 1210 void __iomem *addr, *mem_ptr = NULL;
3d396eb1 1211
f58dbd73
NK		 1212 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1213 if (!addr)
1214 return -EIO;
195c5f98 1215
f58dbd73 1216 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
f03b0ebd 1217 netxen_nic_io_write_128M(adapter, addr, data);
f58dbd73 1218 } else { /* Window 0 */
f03b0ebd 1219 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
907fa120 1220 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
195c5f98 1221 writel(data, addr);
907fa120
DP		 1222 netxen_nic_pci_set_crbwindow_128M(adapter,
1223 NETXEN_WINDOW_ONE);
f03b0ebd 1224 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
cb8011ad
AK		 1225 }
1226
f58dbd73
NK		 1227 if (mem_ptr)
1228 iounmap(mem_ptr);
1229
3d396eb1
AK		 1230 return 0;
1231}
1232
195c5f98 1233static u32
1fbe6323 1234netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
3d396eb1 1235{
195c5f98 1236 unsigned long flags;
f58dbd73 1237 void __iomem *addr, *mem_ptr = NULL;
1fbe6323 1238 u32 data;
d8313ce0 1239
f58dbd73
NK		 1240 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1241 if (!addr)
1242 return -EIO;
3d396eb1 1243
f58dbd73 1244 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
f03b0ebd 1245 data = netxen_nic_io_read_128M(adapter, addr);
f58dbd73 1246 } else { /* Window 0 */
f03b0ebd 1247 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
907fa120 1248 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
195c5f98 1249 data = readl(addr);
907fa120
DP		 1250 netxen_nic_pci_set_crbwindow_128M(adapter,
1251 NETXEN_WINDOW_ONE);
f03b0ebd 1252 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
195c5f98 1253 }
3d396eb1 1254
f58dbd73
NK		 1255 if (mem_ptr)
1256 iounmap(mem_ptr);
1257
1fbe6323 1258 return data;
3d396eb1
AK		 1259}
1260
195c5f98 1261static int
1fbe6323 1262netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
3ce06a32 1263{
195c5f98 1264 unsigned long flags;
3ce06a32 1265 int rv;
a9ac07de 1266 void __iomem *addr = NULL;
3d396eb1 1267
a9ac07de 1268 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
3d396eb1 1269
7cecdca1 1270 if (rv == 0) {
a9ac07de 1271 writel(data, addr);
7cecdca1 1272 return 0;
3ce06a32
DP		 1273 }
1274
7cecdca1
DP		 1275 if (rv > 0) {
1276 /* indirect access */
f03b0ebd 1277 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
3ce06a32 1278 crb_win_lock(adapter);
a9ac07de
DP		 1279 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1280 writel(data, addr);
3ce06a32 1281 crb_win_unlock(adapter);
f03b0ebd 1282 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
7cecdca1
DP		 1283 return 0;
1284 }
3ce06a32 1285
7cecdca1
DP		 1286 dev_err(&adapter->pdev->dev,
1287 "%s: invalid offset: 0x%016lx\n", __func__, off);
1288 dump_stack();
1289 return -EIO;
3d396eb1
AK		 1290}
1291
195c5f98 1292static u32
1fbe6323 1293netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
3ce06a32 1294{
195c5f98 1295 unsigned long flags;
3ce06a32 1296 int rv;
1fbe6323 1297 u32 data;
a9ac07de 1298 void __iomem *addr = NULL;
3d396eb1 1299
a9ac07de 1300 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
3ce06a32 1301
7cecdca1 1302 if (rv == 0)
a9ac07de 1303 return readl(addr);
3ce06a32 1304
7cecdca1
DP		 1305 if (rv > 0) {
1306 /* indirect access */
f03b0ebd 1307 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
3ce06a32 1308 crb_win_lock(adapter);
a9ac07de
DP		 1309 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1310 data = readl(addr);
3ce06a32 1311 crb_win_unlock(adapter);
f03b0ebd 1312 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
7cecdca1
DP		 1313 return data;
1314 }
3ce06a32 1315
7cecdca1
DP		 1316 dev_err(&adapter->pdev->dev,
1317 "%s: invalid offset: 0x%016lx\n", __func__, off);
1318 dump_stack();
1319 return -1;
3ce06a32
DP		 1320}
1321
195c5f98
AKS		 1322/* window 1 registers only */
1323static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1324 void __iomem *addr, u32 data)
3ce06a32 1325{
f03b0ebd 1326 read_lock(&adapter->ahw.crb_lock);
195c5f98 1327 writel(data, addr);
f03b0ebd 1328 read_unlock(&adapter->ahw.crb_lock);
195c5f98
AKS		 1329}
1330
1331static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1332 void __iomem *addr)
1333{
1334 u32 val;
1335
f03b0ebd 1336 read_lock(&adapter->ahw.crb_lock);
195c5f98 1337 val = readl(addr);
f03b0ebd 1338 read_unlock(&adapter->ahw.crb_lock);
195c5f98
AKS		 1339
1340 return val;
3ce06a32
DP		 1341}
1342
195c5f98
AKS		 1343static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1344 void __iomem *addr, u32 data)
3ce06a32 1345{
195c5f98
AKS		 1346 writel(data, addr);
1347}
1348
1349static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1350 void __iomem *addr)
1351{
1352 return readl(addr);
1353}
1354
1355void __iomem *
1356netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1357{
a9ac07de 1358 void __iomem *addr = NULL;
195c5f98
AKS		 1359
1360 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
a9ac07de
DP		 1361 if ((offset < NETXEN_CRB_PCIX_HOST2) &&
1362 (offset > NETXEN_CRB_PCIX_HOST))
1363 addr = PCI_OFFSET_SECOND_RANGE(adapter, offset);
1364 else
1365 addr = NETXEN_CRB_NORMALIZE(adapter, offset);
1366 } else {
1367 WARN_ON(netxen_nic_pci_get_crb_addr_2M(adapter,
1368 offset, &addr));
195c5f98
AKS		 1369 }
1370
a9ac07de 1371 return addr;
3ce06a32
DP		 1372}
1373
47abe356
DP		 1374static int
1375netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1376 u64 addr, u32 *start)
3ce06a32 1377{
47abe356
DP		 1378 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1379 *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0);
1380 return 0;
3ce06a32 1381 } else if (ADDR_IN_RANGE(addr,
47abe356
DP		 1382 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1383 *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1);
1384 return 0;
1385 }
3ce06a32 1386
47abe356
DP		 1387 return -EIO;
1388}
3ce06a32 1389
47abe356
DP		 1390static int
1391netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1392 u64 addr, u32 *start)
1393{
6abb4b83 1394 u32 window;
47abe356 1395 struct pci_dev *pdev = adapter->pdev;
3ce06a32 1396
47abe356
DP		 1397 if ((addr & 0x00ff800) == 0xff800) {
1398 if (printk_ratelimit())
1399 dev_warn(&pdev->dev, "QM access not handled\n");
1400 return -EIO;
1401 }
1402
6abb4b83
AKS		 1403 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
1404 window = OCM_WIN_P3P(addr);
1405 else
1406 window = OCM_WIN(addr);
1407
47abe356 1408 writel(window, adapter->ahw.ocm_win_crb);
6abb4b83
AKS		 1409 /* read back to flush */
1410 readl(adapter->ahw.ocm_win_crb);
47abe356
DP		 1411
1412 adapter->ahw.ocm_win = window;
1413 *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
1414 return 0;
3ce06a32 1415}
47abe356
DP		 1416
1417static int
1418netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off,
1419 u64 *data, int op)
1420{
1421 void __iomem *addr, *mem_ptr = NULL;
1422 resource_size_t mem_base;
47abe356
DP		 1423 int ret = -EIO;
1424 u32 start;
1425
f03b0ebd 1426 spin_lock(&adapter->ahw.mem_lock);
47abe356
DP		 1427
1428 ret = adapter->pci_set_window(adapter, off, &start);
1429 if (ret != 0)
1430 goto unlock;
1431
1432 addr = pci_base_offset(adapter, start);
1433 if (addr)
1434 goto noremap;
1435
1436 mem_base = pci_resource_start(adapter->pdev, 0) + (start & PAGE_MASK);
1437
1438 mem_ptr = ioremap(mem_base, PAGE_SIZE);
1439 if (mem_ptr == NULL) {
1440 ret = -EIO;
1441 goto unlock;
3d396eb1 1442 }
47abe356
DP		 1443
1444 addr = mem_ptr + (start & (PAGE_SIZE - 1));
1445
1446noremap:
1447 if (op == 0) /* read */
1448 *data = readq(addr);
1449 else /* write */
1450 writeq(*data, addr);
1451
1452unlock:
f03b0ebd
DP		 1453 spin_unlock(&adapter->ahw.mem_lock);
1454
47abe356
DP		 1455 if (mem_ptr)
1456 iounmap(mem_ptr);
1457 return ret;
3d396eb1
AK		 1458}
1459
3ce06a32
DP		 1460#define MAX_CTL_CHECK 1000
1461
195c5f98 1462static int
3ce06a32 1463netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1f5e055d 1464 u64 off, u64 data)
3ce06a32 1465{
1f5e055d
AKS		 1466 int j, ret;
1467 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
d8313ce0 1468 void __iomem *mem_crb;
3ce06a32 1469
1f5e055d
AKS		 1470 /* Only 64-bit aligned access */
1471 if (off & 7)
ea6828b8
DP		 1472 return -EIO;
1473
1f5e055d 1474 /* P2 has different SIU and MIU test agent base addr */
ea6828b8
DP		 1475 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1476 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1f5e055d
AKS		 1477 mem_crb = pci_base_offset(adapter,
1478 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1479 addr_hi = SIU_TEST_AGT_ADDR_HI;
1480 data_lo = SIU_TEST_AGT_WRDATA_LO;
1481 data_hi = SIU_TEST_AGT_WRDATA_HI;
1482 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1483 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
ea6828b8
DP		 1484 goto correct;
1485 }
3ce06a32 1486
ea6828b8 1487 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1f5e055d
AKS		 1488 mem_crb = pci_base_offset(adapter,
1489 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1490 addr_hi = MIU_TEST_AGT_ADDR_HI;
1491 data_lo = MIU_TEST_AGT_WRDATA_LO;
1492 data_hi = MIU_TEST_AGT_WRDATA_HI;
1493 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1494 off_hi = 0;
ea6828b8
DP		 1495 goto correct;
1496 }
1497
47abe356
DP		 1498 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1499 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1500 if (adapter->ahw.pci_len0 != 0) {
1501 return netxen_nic_pci_mem_access_direct(adapter,
1502 off, &data, 1);
1503 }
1504 }
1505
ea6828b8
DP		 1506 return -EIO;
1507
1508correct:
f03b0ebd 1509 spin_lock(&adapter->ahw.mem_lock);
907fa120 1510 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
3ce06a32 1511
1f5e055d
AKS		 1512 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1513 writel(off_hi, (mem_crb + addr_hi));
1514 writel(data & 0xffffffff, (mem_crb + data_lo));
1515 writel((data >> 32) & 0xffffffff, (mem_crb + data_hi));
1516 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1517 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1518 (mem_crb + TEST_AGT_CTRL));
1519
1520 for (j = 0; j < MAX_CTL_CHECK; j++) {
1521 temp = readl((mem_crb + TEST_AGT_CTRL));
1522 if ((temp & TA_CTL_BUSY) == 0)
3ce06a32 1523 break;
3ce06a32
DP		 1524 }
1525
1f5e055d
AKS		 1526 if (j >= MAX_CTL_CHECK) {
1527 if (printk_ratelimit())
1528 dev_err(&adapter->pdev->dev,
1529 "failed to write through agent\n");
1530 ret = -EIO;
1531 } else
1532 ret = 0;
1533
907fa120 1534 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
f03b0ebd 1535 spin_unlock(&adapter->ahw.mem_lock);
3ce06a32
DP		 1536 return ret;
1537}
1538
195c5f98 1539static int
3ce06a32 1540netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1f5e055d 1541 u64 off, u64 *data)
3ce06a32 1542{
1f5e055d
AKS		 1543 int j, ret;
1544 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1545 u64 val;
d8313ce0 1546 void __iomem *mem_crb;
3ce06a32 1547
1f5e055d
AKS		 1548 /* Only 64-bit aligned access */
1549 if (off & 7)
ea6828b8
DP		 1550 return -EIO;
1551
1f5e055d 1552 /* P2 has different SIU and MIU test agent base addr */
ea6828b8
DP		 1553 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1554 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1f5e055d
AKS		 1555 mem_crb = pci_base_offset(adapter,
1556 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1557 addr_hi = SIU_TEST_AGT_ADDR_HI;
1558 data_lo = SIU_TEST_AGT_RDDATA_LO;
1559 data_hi = SIU_TEST_AGT_RDDATA_HI;
1560 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1561 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
ea6828b8
DP		 1562 goto correct;
1563 }
3ce06a32 1564
ea6828b8 1565 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1f5e055d
AKS		 1566 mem_crb = pci_base_offset(adapter,
1567 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1568 addr_hi = MIU_TEST_AGT_ADDR_HI;
1569 data_lo = MIU_TEST_AGT_RDDATA_LO;
1570 data_hi = MIU_TEST_AGT_RDDATA_HI;
1571 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1572 off_hi = 0;
ea6828b8
DP		 1573 goto correct;
1574 }
1575
47abe356
DP		 1576 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1577 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1578 if (adapter->ahw.pci_len0 != 0) {
1579 return netxen_nic_pci_mem_access_direct(adapter,
1580 off, data, 0);
1581 }
1582 }
1583
ea6828b8 1584 return -EIO;
3ce06a32 1585
ea6828b8 1586correct:
f03b0ebd 1587 spin_lock(&adapter->ahw.mem_lock);
907fa120 1588 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
3ce06a32 1589
1f5e055d
AKS		 1590 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1591 writel(off_hi, (mem_crb + addr_hi));
1592 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1593 writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
3ce06a32 1594
1f5e055d
AKS		 1595 for (j = 0; j < MAX_CTL_CHECK; j++) {
1596 temp = readl(mem_crb + TEST_AGT_CTRL);
1597 if ((temp & TA_CTL_BUSY) == 0)
3ce06a32 1598 break;
1f5e055d 1599 }
3ce06a32 1600
1f5e055d
AKS		 1601 if (j >= MAX_CTL_CHECK) {
1602 if (printk_ratelimit())
1603 dev_err(&adapter->pdev->dev,
1604 "failed to read through agent\n");
1605 ret = -EIO;
1606 } else {
1607
1608 temp = readl(mem_crb + data_hi);
1609 val = ((u64)temp << 32);
1610 val |= readl(mem_crb + data_lo);
1611 *data = val;
1612 ret = 0;
3ce06a32
DP		 1613 }
1614
907fa120 1615 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
f03b0ebd 1616 spin_unlock(&adapter->ahw.mem_lock);
3ce06a32 1617
1f5e055d 1618 return ret;
3ce06a32
DP		 1619}
1620
195c5f98 1621static int
3ce06a32 1622netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1f5e055d 1623 u64 off, u64 data)
3ce06a32 1624{
fb1f6a43 1625 int i, j, ret;
1f5e055d 1626 u32 temp, off8;
fb1f6a43 1627 u64 stride;
ea6828b8 1628 void __iomem *mem_crb;
3ce06a32 1629
1f5e055d
AKS		 1630 /* Only 64-bit aligned access */
1631 if (off & 7)
ea6828b8
DP		 1632 return -EIO;
1633
1f5e055d 1634 /* P3 onward, test agent base for MIU and SIU is same */
ea6828b8
DP		 1635 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1636 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1f5e055d
AKS		 1637 mem_crb = netxen_get_ioaddr(adapter,
1638 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
ea6828b8
DP		 1639 goto correct;
1640 }
1641
1642 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1f5e055d
AKS		 1643 mem_crb = netxen_get_ioaddr(adapter,
1644 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
ea6828b8 1645 goto correct;
3ce06a32
DP		 1646 }
1647
47abe356
DP		 1648 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX))
1649 return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1);
1650
ea6828b8
DP		 1651 return -EIO;
1652
1653correct:
fb1f6a43
AKS		 1654 stride = NX_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
1655
1656 off8 = off & ~(stride-1);
3ce06a32 1657
f03b0ebd 1658 spin_lock(&adapter->ahw.mem_lock);
3ce06a32 1659
1f5e055d
AKS		 1660 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1661 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
fb1f6a43
AKS		 1662
1663 i = 0;
1664 if (stride == 16) {
1665 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1666 writel((TA_CTL_START | TA_CTL_ENABLE),
1667 (mem_crb + TEST_AGT_CTRL));
1668
1669 for (j = 0; j < MAX_CTL_CHECK; j++) {
1670 temp = readl(mem_crb + TEST_AGT_CTRL);
1671 if ((temp & TA_CTL_BUSY) == 0)
1672 break;
1673 }
1674
1675 if (j >= MAX_CTL_CHECK) {
1676 ret = -EIO;
1677 goto done;
1678 }
1679
1680 i = (off & 0xf) ? 0 : 2;
1681 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1682 mem_crb + MIU_TEST_AGT_WRDATA(i));
1683 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1684 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1685 i = (off & 0xf) ? 2 : 0;
1686 }
1687
1688 writel(data & 0xffffffff,
1689 mem_crb + MIU_TEST_AGT_WRDATA(i));
1690 writel((data >> 32) & 0xffffffff,
1691 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1692
1f5e055d
AKS		 1693 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1694 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1695 (mem_crb + TEST_AGT_CTRL));
1696
1697 for (j = 0; j < MAX_CTL_CHECK; j++) {
1698 temp = readl(mem_crb + TEST_AGT_CTRL);
1699 if ((temp & TA_CTL_BUSY) == 0)
1700 break;
3ce06a32
DP		 1701 }
1702
1f5e055d
AKS		 1703 if (j >= MAX_CTL_CHECK) {
1704 if (printk_ratelimit())
1705 dev_err(&adapter->pdev->dev,
39754f44 1706 "failed to write through agent\n");
1f5e055d
AKS		 1707 ret = -EIO;
1708 } else
1709 ret = 0;
1710
fb1f6a43 1711done:
f03b0ebd 1712 spin_unlock(&adapter->ahw.mem_lock);
3ce06a32 1713
3ce06a32
DP		 1714 return ret;
1715}
1716
195c5f98 1717static int
3ce06a32 1718netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1f5e055d 1719 u64 off, u64 *data)
3ce06a32 1720{
1f5e055d
AKS		 1721 int j, ret;
1722 u32 temp, off8;
fb1f6a43 1723 u64 val, stride;
ea6828b8 1724 void __iomem *mem_crb;
3ce06a32 1725
1f5e055d
AKS		 1726 /* Only 64-bit aligned access */
1727 if (off & 7)
ea6828b8 1728 return -EIO;
3ce06a32 1729
1f5e055d 1730 /* P3 onward, test agent base for MIU and SIU is same */
ea6828b8
DP		 1731 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1732 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1f5e055d
AKS		 1733 mem_crb = netxen_get_ioaddr(adapter,
1734 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
ea6828b8 1735 goto correct;
3ce06a32
DP		 1736 }
1737
ea6828b8 1738 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1f5e055d
AKS		 1739 mem_crb = netxen_get_ioaddr(adapter,
1740 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
ea6828b8
DP		 1741 goto correct;
1742 }
1743
907fa120
DP		 1744 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1745 return netxen_nic_pci_mem_access_direct(adapter,
1746 off, data, 0);
1747 }
47abe356 1748
ea6828b8
DP		 1749 return -EIO;
1750
1751correct:
fb1f6a43
AKS		 1752 stride = NX_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
1753
1754 off8 = off & ~(stride-1);
3ce06a32 1755
f03b0ebd 1756 spin_lock(&adapter->ahw.mem_lock);
3ce06a32 1757
1f5e055d
AKS		 1758 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1759 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1760 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1761 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
3ce06a32 1762
1f5e055d
AKS		 1763 for (j = 0; j < MAX_CTL_CHECK; j++) {
1764 temp = readl(mem_crb + TEST_AGT_CTRL);
1765 if ((temp & TA_CTL_BUSY) == 0)
3ce06a32 1766 break;
3ce06a32
DP		 1767 }
1768
1f5e055d
AKS		 1769 if (j >= MAX_CTL_CHECK) {
1770 if (printk_ratelimit())
1771 dev_err(&adapter->pdev->dev,
1772 "failed to read through agent\n");
1773 ret = -EIO;
3ce06a32 1774 } else {
fb1f6a43
AKS		 1775 off8 = MIU_TEST_AGT_RDDATA_LO;
1776 if ((stride == 16) && (off & 0xf))
1777 off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1778
1779 temp = readl(mem_crb + off8 + 4);
1f5e055d 1780 val = (u64)temp << 32;
fb1f6a43 1781 val |= readl(mem_crb + off8);
1f5e055d
AKS		 1782 *data = val;
1783 ret = 0;
3ce06a32
DP		 1784 }
1785
f03b0ebd 1786 spin_unlock(&adapter->ahw.mem_lock);
1f5e055d
AKS		 1787
1788 return ret;
3ce06a32
DP		 1789}
1790
195c5f98
AKS		 1791void
1792netxen_setup_hwops(struct netxen_adapter *adapter)
3ce06a32 1793{
195c5f98
AKS		 1794 adapter->init_port = netxen_niu_xg_init_port;
1795 adapter->stop_port = netxen_niu_disable_xg_port;
3ce06a32 1796
195c5f98
AKS		 1797 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1798 adapter->crb_read = netxen_nic_hw_read_wx_128M,
1799 adapter->crb_write = netxen_nic_hw_write_wx_128M,
1800 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
1801 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
1802 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
1803 adapter->io_read = netxen_nic_io_read_128M,
1804 adapter->io_write = netxen_nic_io_write_128M,
1805
1806 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
1807 adapter->set_multi = netxen_p2_nic_set_multi;
1808 adapter->set_mtu = netxen_nic_set_mtu_xgb;
1809 adapter->set_promisc = netxen_p2_nic_set_promisc;
3ce06a32 1810
195c5f98
AKS		 1811 } else {
1812 adapter->crb_read = netxen_nic_hw_read_wx_2M,
1813 adapter->crb_write = netxen_nic_hw_write_wx_2M,
1814 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
1815 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
1816 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
1817 adapter->io_read = netxen_nic_io_read_2M,
1818 adapter->io_write = netxen_nic_io_write_2M,
1819
1820 adapter->set_mtu = nx_fw_cmd_set_mtu;
1821 adapter->set_promisc = netxen_p3_nic_set_promisc;
1822 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
1823 adapter->set_multi = netxen_p3_nic_set_multi;
1824
1825 adapter->phy_read = nx_fw_cmd_query_phy;
1826 adapter->phy_write = nx_fw_cmd_set_phy;
1827 }
3ce06a32
DP		 1828}
1829
3d396eb1
AK		 1830int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1831{
0dc6d9cb 1832 int offset, board_type, magic;
1e2d0059 1833 struct pci_dev *pdev = adapter->pdev;
3d396eb1 1834
06db58c0 1835 offset = NX_FW_MAGIC_OFFSET;
1e2d0059
DP		 1836 if (netxen_rom_fast_read(adapter, offset, &magic))
1837 return -EIO;
3d396eb1 1838
0dc6d9cb
DP		 1839 if (magic != NETXEN_BDINFO_MAGIC) {
1840 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1841 magic);
1e2d0059 1842 return -EIO;
3d396eb1
AK		 1843 }
1844
06db58c0 1845 offset = NX_BRDTYPE_OFFSET;
1e2d0059
DP		 1846 if (netxen_rom_fast_read(adapter, offset, &board_type))
1847 return -EIO;
1848
1849 adapter->ahw.board_type = board_type;
1850
1851 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
f98a9f69 1852 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
c7860a2a 1853 if ((gpio & 0x8000) == 0)
1e2d0059 1854 board_type = NETXEN_BRDTYPE_P3_10G_TP;
c7860a2a
DP		 1855 }
1856
e98e3350 1857 switch (board_type) {
3d396eb1 1858 case NETXEN_BRDTYPE_P2_SB35_4G:
1e2d0059 1859 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1
AK		 1860 break;
1861 case NETXEN_BRDTYPE_P2_SB31_10G:
1862 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1863 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1864 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
e4c93c81
DP		 1865 case NETXEN_BRDTYPE_P3_HMEZ:
1866 case NETXEN_BRDTYPE_P3_XG_LOM:
1867 case NETXEN_BRDTYPE_P3_10G_CX4:
1868 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1869 case NETXEN_BRDTYPE_P3_IMEZ:
1870 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
a70f9393
DP		 1871 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1872 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
e4c93c81
DP		 1873 case NETXEN_BRDTYPE_P3_10G_XFP:
1874 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1e2d0059 1875 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 1876 break;
1877 case NETXEN_BRDTYPE_P1_BD:
1878 case NETXEN_BRDTYPE_P1_SB:
1879 case NETXEN_BRDTYPE_P1_SMAX:
1880 case NETXEN_BRDTYPE_P1_SOCK:
e4c93c81
DP		 1881 case NETXEN_BRDTYPE_P3_REF_QG:
1882 case NETXEN_BRDTYPE_P3_4_GB:
1883 case NETXEN_BRDTYPE_P3_4_GB_MM:
1e2d0059 1884 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1 1885 break;
c7860a2a 1886 case NETXEN_BRDTYPE_P3_10G_TP:
1e2d0059 1887 adapter->ahw.port_type = (adapter->portnum < 2) ?
c7860a2a
DP		 1888 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1889 break;
3d396eb1 1890 default:
1e2d0059
DP		 1891 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1892 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 1893 break;
1894 }
1895
1e2d0059 1896 return 0;
3d396eb1
AK		 1897}
1898
1899/* NIU access sections */
1900
3176ff3e 1901int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 1902{
9ad27643 1903 new_mtu += MTU_FUDGE_FACTOR;
f98a9f69 1904 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
3276fbad 1905 new_mtu);
3d396eb1
AK		 1906 return 0;
1907}
1908
3176ff3e 1909int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 1910{
9ad27643 1911 new_mtu += MTU_FUDGE_FACTOR;
3276fbad 1912 if (adapter->physical_port == 0)
f98a9f69 1913 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
4790654c 1914 else
f98a9f69 1915 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
3d396eb1
AK		 1916 return 0;
1917}
1918
3176ff3e 1919void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
3d396eb1 1920{
a608ab9c
AV		 1921 __u32 status;
1922 __u32 autoneg;
24a7a455 1923 __u32 port_mode;
3d396eb1 1924
c7860a2a
DP		 1925 if (!netif_carrier_ok(adapter->netdev)) {
1926 adapter->link_speed = 0;
1927 adapter->link_duplex = -1;
1928 adapter->link_autoneg = AUTONEG_ENABLE;
1929 return;
1930 }
24a7a455 1931
1e2d0059 1932 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
f98a9f69 1933 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
24a7a455
DP		 1934 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
1935 adapter->link_speed = SPEED_1000;
1936 adapter->link_duplex = DUPLEX_FULL;
1937 adapter->link_autoneg = AUTONEG_DISABLE;
1938 return;
1939 }
1940
8e95a202
JP		 1941 if (adapter->phy_read &&
1942 adapter->phy_read(adapter,
1943 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1944 &status) == 0) {
3d396eb1
AK		 1945 if (netxen_get_phy_link(status)) {
1946 switch (netxen_get_phy_speed(status)) {
1947 case 0:
3176ff3e 1948 adapter->link_speed = SPEED_10;
3d396eb1
AK		 1949 break;
1950 case 1:
3176ff3e 1951 adapter->link_speed = SPEED_100;
3d396eb1
AK		 1952 break;
1953 case 2:
3176ff3e 1954 adapter->link_speed = SPEED_1000;
3d396eb1
AK		 1955 break;
1956 default:
c7860a2a 1957 adapter->link_speed = 0;
3d396eb1
AK		 1958 break;
1959 }
1960 switch (netxen_get_phy_duplex(status)) {
1961 case 0:
3176ff3e 1962 adapter->link_duplex = DUPLEX_HALF;
3d396eb1
AK		 1963 break;
1964 case 1:
3176ff3e 1965 adapter->link_duplex = DUPLEX_FULL;
3d396eb1
AK		 1966 break;
1967 default:
3176ff3e 1968 adapter->link_duplex = -1;
3d396eb1
AK		 1969 break;
1970 }
8e95a202
JP		 1971 if (adapter->phy_read &&
1972 adapter->phy_read(adapter,
1973 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1974 &autoneg) != 0)
3176ff3e 1975 adapter->link_autoneg = autoneg;
3d396eb1
AK		 1976 } else
1977 goto link_down;
1978 } else {
1979 link_down:
c7860a2a 1980 adapter->link_speed = 0;
3176ff3e 1981 adapter->link_duplex = -1;
3d396eb1
AK		 1982 }
1983 }
1984}
1985
0b72e659
DP		 1986int
1987netxen_nic_wol_supported(struct netxen_adapter *adapter)
1988{
1989 u32 wol_cfg;
1990
1991 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1992 return 0;
1993
f98a9f69 1994 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
0b72e659 1995 if (wol_cfg & (1UL << adapter->portnum)) {
f98a9f69 1996 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
0b72e659
DP		 1997 if (wol_cfg & (1 << adapter->portnum))
1998 return 1;
1999 }
2000
2001 return 0;
2002}
Linux 6.x block layer and io_uring tree(s)