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netxen: fix mac list management
[linux-2.6-block.git] / drivers / net / netxen / netxen_nic_hw.c
CommitLineData
3d396eb1 1/*
5d242f1c 2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3d396eb1 3 * All rights reserved.
80922fbc 4 *
3d396eb1
AK		 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
cb8011ad 9 *
3d396eb1
AK		 10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
cb8011ad 14 *
3d396eb1
AK		 15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
80922fbc 19 *
3d396eb1
AK		 20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
80922fbc 22 *
3d396eb1
AK		 23 * Contact Information:
24 * info@netxen.com
5d242f1c
DP		 25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
3d396eb1
AK		 28 *
29 */
30
31#include "netxen_nic.h"
32#include "netxen_nic_hw.h"
33#include "netxen_nic_phan_reg.h"
34
c9bdd4b5
ACM		 35#include <net/ip.h>
36
3ce06a32
DP		 37#define MASK(n) ((1ULL<<(n))-1)
38#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
39#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
40#define MS_WIN(addr) (addr & 0x0ffc0000)
41
42#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
43
44#define CRB_BLK(off) ((off >> 20) & 0x3f)
45#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
46#define CRB_WINDOW_2M (0x130060)
47#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
48#define CRB_INDIRECT_2M (0x1e0000UL)
49
e98e3350
DP		 50#ifndef readq
51static inline u64 readq(void __iomem *addr)
52{
53 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
54}
55#endif
56
57#ifndef writeq
58static inline void writeq(u64 val, void __iomem *addr)
59{
60 writel(((u32) (val)), (addr));
61 writel(((u32) (val >> 32)), (addr + 4));
62}
63#endif
64
1fbe6323
DP		 65#define ADDR_IN_RANGE(addr, low, high) \
66 (((addr) < (high)) && ((addr) >= (low)))
67
68#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
69 ((adapter)->ahw.pci_base0 + (off))
70#define PCI_OFFSET_SECOND_RANGE(adapter, off) \
71 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
72#define PCI_OFFSET_THIRD_RANGE(adapter, off) \
73 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
74
75static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
76 unsigned long off)
77{
78 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
79 return PCI_OFFSET_FIRST_RANGE(adapter, off);
80
81 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
82 return PCI_OFFSET_SECOND_RANGE(adapter, off);
83
84 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
85 return PCI_OFFSET_THIRD_RANGE(adapter, off);
86
87 return NULL;
88}
89
3ce06a32 90#define CRB_WIN_LOCK_TIMEOUT 100000000
ea7eaa39
DP		 91static crb_128M_2M_block_map_t
92crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
3ce06a32
DP		 93 {{{0, 0, 0, 0} } }, /* 0: PCI */
94 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
95 {1, 0x0110000, 0x0120000, 0x130000},
96 {1, 0x0120000, 0x0122000, 0x124000},
97 {1, 0x0130000, 0x0132000, 0x126000},
98 {1, 0x0140000, 0x0142000, 0x128000},
99 {1, 0x0150000, 0x0152000, 0x12a000},
100 {1, 0x0160000, 0x0170000, 0x110000},
101 {1, 0x0170000, 0x0172000, 0x12e000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {1, 0x01e0000, 0x01e0800, 0x122000},
109 {0, 0x0000000, 0x0000000, 0x000000} } },
110 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
111 {{{0, 0, 0, 0} } }, /* 3: */
112 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
113 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
114 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
115 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
116 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {1, 0x08f0000, 0x08f2000, 0x172000} } },
132 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {1, 0x09f0000, 0x09f2000, 0x176000} } },
148 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
164 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
180 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
181 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
182 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
183 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
184 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
185 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
186 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
187 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
188 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
189 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
190 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
191 {{{0, 0, 0, 0} } }, /* 23: */
192 {{{0, 0, 0, 0} } }, /* 24: */
193 {{{0, 0, 0, 0} } }, /* 25: */
194 {{{0, 0, 0, 0} } }, /* 26: */
195 {{{0, 0, 0, 0} } }, /* 27: */
196 {{{0, 0, 0, 0} } }, /* 28: */
197 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
198 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
199 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
200 {{{0} } }, /* 32: PCI */
201 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
202 {1, 0x2110000, 0x2120000, 0x130000},
203 {1, 0x2120000, 0x2122000, 0x124000},
204 {1, 0x2130000, 0x2132000, 0x126000},
205 {1, 0x2140000, 0x2142000, 0x128000},
206 {1, 0x2150000, 0x2152000, 0x12a000},
207 {1, 0x2160000, 0x2170000, 0x110000},
208 {1, 0x2170000, 0x2172000, 0x12e000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000},
213 {0, 0x0000000, 0x0000000, 0x000000},
214 {0, 0x0000000, 0x0000000, 0x000000},
215 {0, 0x0000000, 0x0000000, 0x000000},
216 {0, 0x0000000, 0x0000000, 0x000000} } },
217 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
218 {{{0} } }, /* 35: */
219 {{{0} } }, /* 36: */
220 {{{0} } }, /* 37: */
221 {{{0} } }, /* 38: */
222 {{{0} } }, /* 39: */
223 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
224 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
225 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
226 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
227 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
228 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
229 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
230 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
231 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
232 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
233 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
234 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
235 {{{0} } }, /* 52: */
236 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
237 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
238 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
239 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
240 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
241 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
242 {{{0} } }, /* 59: I2C0 */
243 {{{0} } }, /* 60: I2C1 */
244 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
245 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
246 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
247};
248
249/*
250 * top 12 bits of crb internal address (hub, agent)
251 */
252static unsigned crb_hub_agt[64] =
253{
254 0,
255 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
256 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
257 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
258 0,
259 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
260 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
261 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
262 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
263 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
264 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
265 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
266 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
267 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
268 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
270 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
277 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
280 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
281 0,
282 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
283 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
284 0,
285 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
286 0,
287 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
288 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
289 0,
290 0,
291 0,
292 0,
293 0,
294 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
295 0,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
299 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
301 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
302 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
303 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
304 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
305 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
306 0,
307 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
308 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
309 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
310 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
311 0,
312 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
313 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
314 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
315 0,
316 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
317 0,
318};
319
3d396eb1
AK		 320/* PCI Windowing for DDR regions. */
321
3ce06a32 322#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
3d396eb1 323
3d396eb1
AK		 324int netxen_nic_set_mac(struct net_device *netdev, void *p)
325{
3176ff3e 326 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1
AK		 327 struct sockaddr *addr = p;
328
329 if (netif_running(netdev))
330 return -EBUSY;
331
332 if (!is_valid_ether_addr(addr->sa_data))
333 return -EADDRNOTAVAIL;
334
3d396eb1
AK		 335 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
336
c9fc891f
DP		 337 /* For P3, MAC addr is not set in NIU */
338 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
339 if (adapter->macaddr_set)
340 adapter->macaddr_set(adapter, addr->sa_data);
3d396eb1
AK		 341
342 return 0;
343}
344
623621b0
DP		 345#define NETXEN_UNICAST_ADDR(port, index) \
346 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
347#define NETXEN_MCAST_ADDR(port, index) \
348 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
349#define MAC_HI(addr) \
350 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
351#define MAC_LO(addr) \
352 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
353
354static int
355netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
356{
357 u32 val = 0;
358 u16 port = adapter->physical_port;
359 u8 *addr = adapter->netdev->dev_addr;
360
361 if (adapter->mc_enabled)
362 return 0;
363
f98a9f69 364 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
623621b0 365 val |= (1UL << (28+port));
f98a9f69 366 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
623621b0
DP		 367
368 /* add broadcast addr to filter */
369 val = 0xffffff;
f98a9f69
DP		 370 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
371 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
623621b0
DP		 372
373 /* add station addr to filter */
374 val = MAC_HI(addr);
f98a9f69 375 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
623621b0 376 val = MAC_LO(addr);
f98a9f69 377 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
623621b0
DP		 378
379 adapter->mc_enabled = 1;
380 return 0;
381}
382
383static int
384netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
385{
386 u32 val = 0;
387 u16 port = adapter->physical_port;
388 u8 *addr = adapter->netdev->dev_addr;
389
390 if (!adapter->mc_enabled)
391 return 0;
392
f98a9f69 393 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
623621b0 394 val &= ~(1UL << (28+port));
f98a9f69 395 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
623621b0
DP		 396
397 val = MAC_HI(addr);
f98a9f69 398 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
623621b0 399 val = MAC_LO(addr);
f98a9f69 400 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
623621b0 401
f98a9f69
DP		 402 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
403 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
623621b0
DP		 404
405 adapter->mc_enabled = 0;
406 return 0;
407}
408
409static int
410netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
411 int index, u8 *addr)
412{
413 u32 hi = 0, lo = 0;
414 u16 port = adapter->physical_port;
415
416 lo = MAC_LO(addr);
417 hi = MAC_HI(addr);
418
f98a9f69
DP		 419 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
420 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
623621b0
DP		 421
422 return 0;
423}
424
c9fc891f 425void netxen_p2_nic_set_multi(struct net_device *netdev)
3d396eb1 426{
3176ff3e 427 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1 428 struct dev_mc_list *mc_ptr;
623621b0
DP		 429 u8 null_addr[6];
430 int index = 0;
431
432 memset(null_addr, 0, 6);
3d396eb1 433
3d396eb1 434 if (netdev->flags & IFF_PROMISC) {
623621b0
DP		 435
436 adapter->set_promisc(adapter,
437 NETXEN_NIU_PROMISC_MODE);
438
439 /* Full promiscuous mode */
440 netxen_nic_disable_mcast_filter(adapter);
441
442 return;
443 }
444
445 if (netdev->mc_count == 0) {
446 adapter->set_promisc(adapter,
447 NETXEN_NIU_NON_PROMISC_MODE);
448 netxen_nic_disable_mcast_filter(adapter);
449 return;
450 }
451
452 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
453 if (netdev->flags & IFF_ALLMULTI ||
454 netdev->mc_count > adapter->max_mc_count) {
455 netxen_nic_disable_mcast_filter(adapter);
456 return;
3d396eb1 457 }
623621b0
DP		 458
459 netxen_nic_enable_mcast_filter(adapter);
460
461 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
462 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
463
464 if (index != netdev->mc_count)
465 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
466 netxen_nic_driver_name, netdev->name);
467
468 /* Clear out remaining addresses */
469 for (; index < adapter->max_mc_count; index++)
470 netxen_nic_set_mcast_addr(adapter, index, null_addr);
3d396eb1
AK		 471}
472
c9fc891f
DP		 473static int
474netxen_send_cmd_descs(struct netxen_adapter *adapter,
d877f1e3 475 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
c9fc891f 476{
d877f1e3 477 u32 i, producer, consumer;
c9fc891f
DP		 478 struct netxen_cmd_buffer *pbuf;
479 struct cmd_desc_type0 *cmd_desc;
d877f1e3 480 struct nx_host_tx_ring *tx_ring;
c9fc891f
DP		 481
482 i = 0;
483
4ea528a1 484 tx_ring = adapter->tx_ring;
03e678ee
DP		 485 netif_tx_lock_bh(adapter->netdev);
486
d877f1e3
DP		 487 producer = tx_ring->producer;
488 consumer = tx_ring->sw_consumer;
489
22527864 490 if (nr_desc >= find_diff_among(producer, consumer, tx_ring->num_desc)) {
d877f1e3
DP		 491 netif_tx_unlock_bh(adapter->netdev);
492 return -EBUSY;
493 }
494
c9fc891f
DP		 495 do {
496 cmd_desc = &cmd_desc_arr[i];
497
d877f1e3 498 pbuf = &tx_ring->cmd_buf_arr[producer];
c9fc891f 499 pbuf->skb = NULL;
c9fc891f 500 pbuf->frag_count = 0;
c9fc891f 501
d877f1e3 502 memcpy(&tx_ring->desc_head[producer],
c9fc891f
DP		 503 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
504
d877f1e3 505 producer = get_next_index(producer, tx_ring->num_desc);
c9fc891f
DP		 506 i++;
507
d877f1e3 508 } while (i != nr_desc);
c9fc891f 509
d877f1e3 510 tx_ring->producer = producer;
c9fc891f 511
d877f1e3 512 netxen_nic_update_cmd_producer(adapter, tx_ring, producer);
c9fc891f 513
03e678ee
DP		 514 netif_tx_unlock_bh(adapter->netdev);
515
c9fc891f
DP		 516 return 0;
517}
518
5cf4d323
DP		 519static int
520nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
c9fc891f 521{
c9fc891f 522 nx_nic_req_t req;
2edbb454
DP		 523 nx_mac_req_t *mac_req;
524 u64 word;
c9fc891f
DP		 525
526 memset(&req, 0, sizeof(nx_nic_req_t));
2edbb454
DP		 527 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
528
529 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
530 req.req_hdr = cpu_to_le64(word);
531
532 mac_req = (nx_mac_req_t *)&req.words[0];
533 mac_req->op = op;
534 memcpy(mac_req->mac_addr, addr, 6);
c9fc891f 535
5cf4d323
DP		 536 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
537}
538
539static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
540 u8 *addr, struct list_head *del_list)
541{
542 struct list_head *head;
543 nx_mac_list_t *cur;
544
545 /* look up if already exists */
546 list_for_each(head, del_list) {
547 cur = list_entry(head, nx_mac_list_t, list);
548
549 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
550 list_move_tail(head, &adapter->mac_list);
551 return 0;
552 }
c9fc891f
DP		 553 }
554
5cf4d323
DP		 555 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
556 if (cur == NULL) {
557 printk(KERN_ERR "%s: failed to add mac address filter\n",
558 adapter->netdev->name);
559 return -ENOMEM;
560 }
561 memcpy(cur->mac_addr, addr, ETH_ALEN);
562 list_add_tail(&cur->list, &adapter->mac_list);
563 return nx_p3_sre_macaddr_change(adapter,
564 cur->mac_addr, NETXEN_MAC_ADD);
c9fc891f
DP		 565}
566
567void netxen_p3_nic_set_multi(struct net_device *netdev)
568{
569 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f
DP		 570 struct dev_mc_list *mc_ptr;
571 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
9ad27643 572 u32 mode = VPORT_MISS_MODE_DROP;
5cf4d323
DP		 573 LIST_HEAD(del_list);
574 struct list_head *head;
575 nx_mac_list_t *cur;
c9fc891f 576
5cf4d323 577 list_splice_tail_init(&adapter->mac_list, &del_list);
c9fc891f 578
5cf4d323
DP		 579 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &del_list);
580 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
9ad27643
DP		 581
582 if (netdev->flags & IFF_PROMISC) {
583 mode = VPORT_MISS_MODE_ACCEPT_ALL;
584 goto send_fw_cmd;
585 }
586
587 if ((netdev->flags & IFF_ALLMULTI) ||
588 (netdev->mc_count > adapter->max_mc_count)) {
589 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
590 goto send_fw_cmd;
591 }
592
c9fc891f 593 if (netdev->mc_count > 0) {
c9fc891f
DP		 594 for (mc_ptr = netdev->mc_list; mc_ptr;
595 mc_ptr = mc_ptr->next) {
5cf4d323 596 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
c9fc891f
DP		 597 }
598 }
9ad27643
DP		 599
600send_fw_cmd:
601 adapter->set_promisc(adapter, mode);
5cf4d323
DP		 602 head = &del_list;
603 while (!list_empty(head)) {
604 cur = list_entry(head->next, nx_mac_list_t, list);
605
606 nx_p3_sre_macaddr_change(adapter,
607 cur->mac_addr, NETXEN_MAC_DEL);
608 list_del(&cur->list);
c9fc891f 609 kfree(cur);
c9fc891f
DP		 610 }
611}
612
9ad27643
DP		 613int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
614{
615 nx_nic_req_t req;
2edbb454 616 u64 word;
9ad27643
DP		 617
618 memset(&req, 0, sizeof(nx_nic_req_t));
619
2edbb454
DP		 620 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
621
622 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
623 ((u64)adapter->portnum << 16);
624 req.req_hdr = cpu_to_le64(word);
625
9ad27643
DP		 626 req.words[0] = cpu_to_le64(mode);
627
628 return netxen_send_cmd_descs(adapter,
629 (struct cmd_desc_type0 *)&req, 1);
630}
631
06e9d9f9
DP		 632void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
633{
5cf4d323
DP		 634 nx_mac_list_t *cur;
635 struct list_head *head = &adapter->mac_list;
636
637 while (!list_empty(head)) {
638 cur = list_entry(head->next, nx_mac_list_t, list);
639 nx_p3_sre_macaddr_change(adapter,
640 cur->mac_addr, NETXEN_MAC_DEL);
641 list_del(&cur->list);
06e9d9f9 642 kfree(cur);
06e9d9f9
DP		 643 }
644}
645
cd1f8160
DP		 646#define NETXEN_CONFIG_INTR_COALESCE 3
647
648/*
649 * Send the interrupt coalescing parameter set by ethtool to the card.
650 */
651int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
652{
653 nx_nic_req_t req;
2edbb454 654 u64 word;
cd1f8160
DP		 655 int rv;
656
657 memset(&req, 0, sizeof(nx_nic_req_t));
658
2edbb454
DP		 659 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
660
661 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
662 req.req_hdr = cpu_to_le64(word);
cd1f8160
DP		 663
664 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
665
666 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
667 if (rv != 0) {
668 printk(KERN_ERR "ERROR. Could not send "
669 "interrupt coalescing parameters\n");
670 }
671
672 return rv;
673}
674
d8b100c5
DP		 675#define RSS_HASHTYPE_IP_TCP 0x3
676
677int netxen_config_rss(struct netxen_adapter *adapter, int enable)
678{
679 nx_nic_req_t req;
680 u64 word;
681 int i, rv;
682
683 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
684 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
685 0x255b0ec26d5a56daULL };
686
687
688 memset(&req, 0, sizeof(nx_nic_req_t));
689 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
690
691 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
692 req.req_hdr = cpu_to_le64(word);
693
694 /*
695 * RSS request:
696 * bits 3-0: hash_method
697 * 5-4: hash_type_ipv4
698 * 7-6: hash_type_ipv6
699 * 8: enable
700 * 9: use indirection table
701 * 47-10: reserved
702 * 63-48: indirection table mask
703 */
704 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
705 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
706 ((u64)(enable & 0x1) << 8) |
707 ((0x7ULL) << 48);
708 req.words[0] = cpu_to_le64(word);
709 for (i = 0; i < 5; i++)
710 req.words[i+1] = cpu_to_le64(key[i]);
711
712
713 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
714 if (rv != 0) {
715 printk(KERN_ERR "%s: could not configure RSS\n",
716 adapter->netdev->name);
717 }
718
719 return rv;
720}
721
3bf26ce3
DP		 722int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
723{
724 nx_nic_req_t req;
725 u64 word;
726 int rv;
727
728 memset(&req, 0, sizeof(nx_nic_req_t));
729 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
730
731 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
732 req.req_hdr = cpu_to_le64(word);
22527864 733 req.words[0] = cpu_to_le64(enable | (enable << 8));
3bf26ce3
DP		 734
735 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
736 if (rv != 0) {
737 printk(KERN_ERR "%s: could not configure link notification\n",
738 adapter->netdev->name);
739 }
740
741 return rv;
742}
743
3d396eb1
AK		 744/*
745 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
746 * @returns 0 on success, negative on failure
747 */
c9fc891f
DP		 748
749#define MTU_FUDGE_FACTOR 100
750
3d396eb1
AK		 751int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
752{
3176ff3e 753 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f 754 int max_mtu;
9ad27643 755 int rc = 0;
3d396eb1 756
c9fc891f
DP		 757 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
758 max_mtu = P3_MAX_MTU;
759 else
760 max_mtu = P2_MAX_MTU;
761
762 if (mtu > max_mtu) {
763 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
764 netdev->name, max_mtu);
3d396eb1
AK		 765 return -EINVAL;
766 }
767
80922fbc 768 if (adapter->set_mtu)
9ad27643 769 rc = adapter->set_mtu(adapter, mtu);
3d396eb1 770
9ad27643
DP		 771 if (!rc)
772 netdev->mtu = mtu;
c9fc891f 773
9ad27643 774 return rc;
3d396eb1
AK		 775}
776
3d396eb1 777static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
f305f789 778 int size, __le32 * buf)
3d396eb1 779{
1e2d0059 780 int i, v, addr;
f305f789 781 __le32 *ptr32;
3d396eb1
AK		 782
783 addr = base;
784 ptr32 = buf;
785 for (i = 0; i < size / sizeof(u32); i++) {
f305f789 786 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 787 return -1;
f305f789 788 *ptr32 = cpu_to_le32(v);
3d396eb1
AK		 789 ptr32++;
790 addr += sizeof(u32);
791 }
792 if ((char *)buf + size > (char *)ptr32) {
f305f789
AV		 793 __le32 local;
794 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 795 return -1;
f305f789 796 local = cpu_to_le32(v);
3d396eb1
AK		 797 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
798 }
799
800 return 0;
801}
802
9dc28efe 803int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
3d396eb1 804{
9dc28efe
DP		 805 __le32 *pmac = (__le32 *) mac;
806 u32 offset;
3d396eb1 807
9dc28efe
DP		 808 offset = NETXEN_USER_START +
809 offsetof(struct netxen_new_user_info, mac_addr) +
810 adapter->portnum * sizeof(u64);
811
812 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
3d396eb1 813 return -1;
9dc28efe 814
f305f789 815 if (*mac == cpu_to_le64(~0ULL)) {
9dc28efe
DP		 816
817 offset = NETXEN_USER_START_OLD +
818 offsetof(struct netxen_user_old_info, mac_addr) +
819 adapter->portnum * sizeof(u64);
820
3d396eb1 821 if (netxen_get_flash_block(adapter,
9dc28efe 822 offset, sizeof(u64), pmac) == -1)
3d396eb1 823 return -1;
9dc28efe 824
f305f789 825 if (*mac == cpu_to_le64(~0ULL))
3d396eb1
AK		 826 return -1;
827 }
828 return 0;
829}
830
9dc28efe
DP		 831int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
832{
833 uint32_t crbaddr, mac_hi, mac_lo;
834 int pci_func = adapter->ahw.pci_func;
835
836 crbaddr = CRB_MAC_BLOCK_START +
837 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
838
f98a9f69
DP		 839 mac_lo = NXRD32(adapter, crbaddr);
840 mac_hi = NXRD32(adapter, crbaddr+4);
9dc28efe 841
9dc28efe 842 if (pci_func & 1)
2edbb454 843 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
9dc28efe 844 else
2edbb454 845 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
9dc28efe
DP		 846
847 return 0;
848}
849
3ce06a32
DP		 850#define CRB_WIN_LOCK_TIMEOUT 100000000
851
852static int crb_win_lock(struct netxen_adapter *adapter)
853{
854 int done = 0, timeout = 0;
855
856 while (!done) {
857 /* acquire semaphore3 from PCI HW block */
f98a9f69 858 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_LOCK));
3ce06a32
DP		 859 if (done == 1)
860 break;
861 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
862 return -1;
863 timeout++;
864 udelay(1);
865 }
f98a9f69 866 NXWR32(adapter, NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
3ce06a32
DP		 867 return 0;
868}
869
870static void crb_win_unlock(struct netxen_adapter *adapter)
871{
872 int val;
873
f98a9f69 874 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK));
3ce06a32
DP		 875}
876
3d396eb1
AK		 877/*
878 * Changes the CRB window to the specified window.
879 */
3ce06a32
DP		 880void
881netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
3d396eb1
AK		 882{
883 void __iomem *offset;
884 u32 tmp;
885 int count = 0;
e4c93c81 886 uint8_t func = adapter->ahw.pci_func;
3d396eb1
AK		 887
888 if (adapter->curr_window == wndw)
889 return;
3d396eb1
AK		 890 /*
891 * Move the CRB window.
892 * We need to write to the "direct access" region of PCI
893 * to avoid a race condition where the window register has
894 * not been successfully written across CRB before the target
895 * register address is received by PCI. The direct region bypasses
896 * the CRB bus.
897 */
e4c93c81
DP		 898 offset = PCI_OFFSET_SECOND_RANGE(adapter,
899 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
3d396eb1
AK		 900
901 if (wndw & 0x1)
902 wndw = NETXEN_WINDOW_ONE;
903
904 writel(wndw, offset);
905
906 /* MUST make sure window is set before we forge on... */
907 while ((tmp = readl(offset)) != wndw) {
908 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
909 "registered properly: 0x%08x.\n",
3ce06a32 910 netxen_nic_driver_name, __func__, tmp);
3d396eb1
AK		 911 mdelay(1);
912 if (count >= 10)
913 break;
914 count++;
915 }
916
6c80b18d
MT		 917 if (wndw == NETXEN_WINDOW_ONE)
918 adapter->curr_window = 1;
919 else
920 adapter->curr_window = 0;
3d396eb1
AK		 921}
922
3ce06a32
DP		 923/*
924 * Return -1 if off is not valid,
925 * 1 if window access is needed. 'off' is set to offset from
926 * CRB space in 128M pci map
927 * 0 if no window access is needed. 'off' is set to 2M addr
928 * In: 'off' is offset from base in 128M pci map
929 */
930static int
931netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
932 ulong *off, int len)
933{
934 unsigned long end = *off + len;
935 crb_128M_2M_sub_block_map_t *m;
936
937
938 if (*off >= NETXEN_CRB_MAX)
939 return -1;
940
941 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
942 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
943 (ulong)adapter->ahw.pci_base0;
944 return 0;
945 }
946
947 if (*off < NETXEN_PCI_CRBSPACE)
948 return -1;
949
950 *off -= NETXEN_PCI_CRBSPACE;
951 end = *off + len;
952
953 /*
954 * Try direct map
955 */
956 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
957
958 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
959 *off = *off + m->start_2M - m->start_128M +
960 (ulong)adapter->ahw.pci_base0;
961 return 0;
962 }
963
964 /*
965 * Not in direct map, use crb window
966 */
967 return 1;
968}
969
970/*
971 * In: 'off' is offset from CRB space in 128M pci map
972 * Out: 'off' is 2M pci map addr
973 * side effect: lock crb window
974 */
975static void
976netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
977{
978 u32 win_read;
979
980 adapter->crb_win = CRB_HI(*off);
d8313ce0 981 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
3ce06a32
DP		 982 /*
983 * Read back value to make sure write has gone through before trying
984 * to use it.
985 */
d8313ce0 986 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
3ce06a32
DP		 987 if (win_read != adapter->crb_win) {
988 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
989 "Read crbwin (0x%x), off=0x%lx\n",
990 __func__, adapter->crb_win, win_read, *off);
991 }
992 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
993 (ulong)adapter->ahw.pci_base0;
994}
995
3d396eb1 996int
1fbe6323 997netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
3d396eb1
AK		 998{
999 void __iomem *addr;
1000
1001 if (ADDR_IN_WINDOW1(off)) {
1002 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1003 } else { /* Window 0 */
cb8011ad 1004 addr = pci_base_offset(adapter, off);
3ce06a32 1005 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
3d396eb1
AK		 1006 }
1007
cb8011ad 1008 if (!addr) {
3ce06a32 1009 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
cb8011ad
AK		 1010 return 1;
1011 }
1012
1fbe6323 1013 writel(data, addr);
3d396eb1 1014
3d396eb1 1015 if (!ADDR_IN_WINDOW1(off))
3ce06a32 1016 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
3d396eb1
AK		 1017
1018 return 0;
1019}
1020
1fbe6323
DP		 1021u32
1022netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
3d396eb1
AK		 1023{
1024 void __iomem *addr;
1fbe6323 1025 u32 data;
d8313ce0 1026
3d396eb1
AK		 1027 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1028 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1029 } else { /* Window 0 */
cb8011ad 1030 addr = pci_base_offset(adapter, off);
3ce06a32 1031 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
3d396eb1
AK		 1032 }
1033
cb8011ad 1034 if (!addr) {
3ce06a32 1035 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
cb8011ad
AK		 1036 return 1;
1037 }
d8313ce0 1038
1fbe6323 1039 data = readl(addr);
3d396eb1
AK		 1040
1041 if (!ADDR_IN_WINDOW1(off))
3ce06a32 1042 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
3d396eb1 1043
1fbe6323 1044 return data;
3d396eb1
AK		 1045}
1046
3ce06a32 1047int
1fbe6323 1048netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
3ce06a32
DP		 1049{
1050 unsigned long flags = 0;
1051 int rv;
3d396eb1 1052
1fbe6323 1053 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, 4);
3d396eb1 1054
3ce06a32
DP		 1055 if (rv == -1) {
1056 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1057 __func__, off);
1058 dump_stack();
1059 return -1;
1060 }
1061
1062 if (rv == 1) {
1063 write_lock_irqsave(&adapter->adapter_lock, flags);
1064 crb_win_lock(adapter);
1065 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1fbe6323 1066 writel(data, (void __iomem *)off);
3ce06a32
DP		 1067 crb_win_unlock(adapter);
1068 write_unlock_irqrestore(&adapter->adapter_lock, flags);
d8313ce0 1069 } else
1fbe6323 1070 writel(data, (void __iomem *)off);
d8313ce0 1071
3ce06a32
DP		 1072
1073 return 0;
3d396eb1
AK		 1074}
1075
1fbe6323
DP		 1076u32
1077netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
3ce06a32
DP		 1078{
1079 unsigned long flags = 0;
1080 int rv;
1fbe6323 1081 u32 data;
3d396eb1 1082
1fbe6323 1083 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, 4);
3ce06a32
DP		 1084
1085 if (rv == -1) {
1086 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1087 __func__, off);
1088 dump_stack();
1089 return -1;
1090 }
1091
1092 if (rv == 1) {
1093 write_lock_irqsave(&adapter->adapter_lock, flags);
1094 crb_win_lock(adapter);
1095 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1fbe6323 1096 data = readl((void __iomem *)off);
3ce06a32
DP		 1097 crb_win_unlock(adapter);
1098 write_unlock_irqrestore(&adapter->adapter_lock, flags);
d8313ce0 1099 } else
1fbe6323 1100 data = readl((void __iomem *)off);
3ce06a32 1101
1fbe6323 1102 return data;
3ce06a32
DP		 1103}
1104
3ce06a32
DP		 1105/*
1106 * check memory access boundary.
1107 * used by test agent. support ddr access only for now
1108 */
1109static unsigned long
1110netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1111 unsigned long long addr, int size)
1112{
1113 if (!ADDR_IN_RANGE(addr,
1114 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1115 !ADDR_IN_RANGE(addr+size-1,
1116 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1117 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1118 return 0;
1119 }
3d396eb1 1120
3ce06a32 1121 return 1;
3d396eb1
AK		 1122}
1123
4790654c 1124static int netxen_pci_set_window_warning_count;
3d396eb1 1125
3ce06a32
DP		 1126unsigned long
1127netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1128 unsigned long long addr)
3d396eb1 1129{
e4c93c81 1130 void __iomem *offset;
3d396eb1 1131 int window;
3ce06a32 1132 unsigned long long qdr_max;
e4c93c81 1133 uint8_t func = adapter->ahw.pci_func;
3d396eb1 1134
3ce06a32
DP		 1135 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1136 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1137 } else {
1138 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1139 }
1140
3d396eb1
AK		 1141 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1142 /* DDR network side */
1143 addr -= NETXEN_ADDR_DDR_NET;
1144 window = (addr >> 25) & 0x3ff;
3ce06a32
DP		 1145 if (adapter->ahw.ddr_mn_window != window) {
1146 adapter->ahw.ddr_mn_window = window;
e4c93c81
DP		 1147 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1148 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1149 writel(window, offset);
3d396eb1 1150 /* MUST make sure window is set before we forge on... */
e4c93c81 1151 readl(offset);
3d396eb1 1152 }
cb8011ad 1153 addr -= (window * NETXEN_WINDOW_ONE);
3d396eb1
AK		 1154 addr += NETXEN_PCI_DDR_NET;
1155 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1156 addr -= NETXEN_ADDR_OCM0;
1157 addr += NETXEN_PCI_OCM0;
1158 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1159 addr -= NETXEN_ADDR_OCM1;
1160 addr += NETXEN_PCI_OCM1;
3ce06a32 1161 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
3d396eb1
AK		 1162 /* QDR network side */
1163 addr -= NETXEN_ADDR_QDR_NET;
1164 window = (addr >> 22) & 0x3f;
3ce06a32
DP		 1165 if (adapter->ahw.qdr_sn_window != window) {
1166 adapter->ahw.qdr_sn_window = window;
e4c93c81
DP		 1167 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1168 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1169 writel((window << 22), offset);
3d396eb1 1170 /* MUST make sure window is set before we forge on... */
e4c93c81 1171 readl(offset);
3d396eb1
AK		 1172 }
1173 addr -= (window * 0x400000);
1174 addr += NETXEN_PCI_QDR_NET;
1175 } else {
1176 /*
1177 * peg gdb frequently accesses memory that doesn't exist,
1178 * this limits the chit chat so debugging isn't slowed down.
1179 */
1180 if ((netxen_pci_set_window_warning_count++ < 8)
1181 || (netxen_pci_set_window_warning_count % 64 == 0))
1182 printk("%s: Warning:netxen_nic_pci_set_window()"
1183 " Unknown address range!\n",
1184 netxen_nic_driver_name);
3ce06a32
DP		 1185 addr = -1UL;
1186 }
1187 return addr;
1188}
1189
1190/*
1191 * Note : only 32-bit writes!
1192 */
1193int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1194 u64 off, u32 data)
1195{
1196 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1197 return 0;
1198}
1199
1200u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1201{
1202 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1203}
1204
3ce06a32
DP		 1205unsigned long
1206netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1207 unsigned long long addr)
1208{
1209 int window;
1210 u32 win_read;
3d396eb1 1211
3ce06a32
DP		 1212 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1213 /* DDR network side */
1214 window = MN_WIN(addr);
1215 adapter->ahw.ddr_mn_window = window;
f98a9f69 1216 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1fbe6323 1217 window);
f98a9f69 1218 win_read = NXRD32(adapter,
1fbe6323 1219 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
3ce06a32
DP		 1220 if ((win_read << 17) != window) {
1221 printk(KERN_INFO "Written MNwin (0x%x) != "
1222 "Read MNwin (0x%x)\n", window, win_read);
1223 }
1224 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1225 } else if (ADDR_IN_RANGE(addr,
1226 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1227 if ((addr & 0x00ff800) == 0xff800) {
1228 printk("%s: QM access not handled.\n", __func__);
1229 addr = -1UL;
1230 }
1231
1232 window = OCM_WIN(addr);
1233 adapter->ahw.ddr_mn_window = window;
f98a9f69 1234 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1fbe6323 1235 window);
f98a9f69 1236 win_read = NXRD32(adapter,
1fbe6323 1237 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
3ce06a32
DP		 1238 if ((win_read >> 7) != window) {
1239 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1240 "Read OCMwin (0x%x)\n",
1241 __func__, window, win_read);
1242 }
1243 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1244
1245 } else if (ADDR_IN_RANGE(addr,
1246 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1247 /* QDR network side */
1248 window = MS_WIN(addr);
1249 adapter->ahw.qdr_sn_window = window;
f98a9f69 1250 NXWR32(adapter, adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1fbe6323 1251 window);
f98a9f69 1252 win_read = NXRD32(adapter,
1fbe6323 1253 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE);
3ce06a32
DP		 1254 if (win_read != window) {
1255 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1256 "Read MSwin (0x%x)\n",
1257 __func__, window, win_read);
1258 }
1259 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1260
1261 } else {
1262 /*
1263 * peg gdb frequently accesses memory that doesn't exist,
1264 * this limits the chit chat so debugging isn't slowed down.
1265 */
1266 if ((netxen_pci_set_window_warning_count++ < 8)
1267 || (netxen_pci_set_window_warning_count%64 == 0)) {
1268 printk("%s: Warning:%s Unknown address range!\n",
1269 __func__, netxen_nic_driver_name);
1270}
1271 addr = -1UL;
3d396eb1
AK		 1272 }
1273 return addr;
1274}
1275
3ce06a32
DP		 1276static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1277 unsigned long long addr)
1278{
1279 int window;
1280 unsigned long long qdr_max;
1281
1282 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1283 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1284 else
1285 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1286
1287 if (ADDR_IN_RANGE(addr,
1288 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1289 /* DDR network side */
1290 BUG(); /* MN access can not come here */
1291 } else if (ADDR_IN_RANGE(addr,
1292 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1293 return 1;
1294 } else if (ADDR_IN_RANGE(addr,
1295 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1296 return 1;
1297 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1298 /* QDR network side */
1299 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1300 if (adapter->ahw.qdr_sn_window == window)
1301 return 1;
1302 }
1303
1304 return 0;
1305}
1306
1307static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1308 u64 off, void *data, int size)
1309{
1310 unsigned long flags;
d8313ce0 1311 void __iomem *addr, *mem_ptr = NULL;
3ce06a32
DP		 1312 int ret = 0;
1313 u64 start;
3ce06a32
DP		 1314 unsigned long mem_base;
1315 unsigned long mem_page;
1316
1317 write_lock_irqsave(&adapter->adapter_lock, flags);
1318
1319 /*
1320 * If attempting to access unknown address or straddle hw windows,
1321 * do not access.
1322 */
1323 start = adapter->pci_set_window(adapter, off);
1324 if ((start == -1UL) ||
1325 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1326 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1327 printk(KERN_ERR "%s out of bound pci memory access. "
11a859e5
AM		 1328 "offset is 0x%llx\n", netxen_nic_driver_name,
1329 (unsigned long long)off);
3ce06a32
DP		 1330 return -1;
1331 }
1332
d8313ce0 1333 addr = pci_base_offset(adapter, start);
3ce06a32
DP		 1334 if (!addr) {
1335 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1336 mem_base = pci_resource_start(adapter->pdev, 0);
1337 mem_page = start & PAGE_MASK;
1338 /* Map two pages whenever user tries to access addresses in two
1339 consecutive pages.
1340 */
1341 if (mem_page != ((start + size - 1) & PAGE_MASK))
1342 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1343 else
1344 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
f8057b7f 1345 if (mem_ptr == NULL) {
3ce06a32
DP		 1346 *(uint8_t *)data = 0;
1347 return -1;
1348 }
1349 addr = mem_ptr;
1350 addr += start & (PAGE_SIZE - 1);
1351 write_lock_irqsave(&adapter->adapter_lock, flags);
1352 }
1353
1354 switch (size) {
1355 case 1:
1356 *(uint8_t *)data = readb(addr);
1357 break;
1358 case 2:
1359 *(uint16_t *)data = readw(addr);
1360 break;
1361 case 4:
1362 *(uint32_t *)data = readl(addr);
1363 break;
1364 case 8:
1365 *(uint64_t *)data = readq(addr);
1366 break;
1367 default:
1368 ret = -1;
1369 break;
1370 }
1371 write_unlock_irqrestore(&adapter->adapter_lock, flags);
3ce06a32
DP		 1372
1373 if (mem_ptr)
1374 iounmap(mem_ptr);
1375 return ret;
1376}
1377
1378static int
1379netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1380 void *data, int size)
1381{
1382 unsigned long flags;
d8313ce0 1383 void __iomem *addr, *mem_ptr = NULL;
3ce06a32
DP		 1384 int ret = 0;
1385 u64 start;
3ce06a32
DP		 1386 unsigned long mem_base;
1387 unsigned long mem_page;
1388
1389 write_lock_irqsave(&adapter->adapter_lock, flags);
1390
1391 /*
1392 * If attempting to access unknown address or straddle hw windows,
1393 * do not access.
1394 */
1395 start = adapter->pci_set_window(adapter, off);
1396 if ((start == -1UL) ||
1397 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1398 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1399 printk(KERN_ERR "%s out of bound pci memory access. "
11a859e5
AM		 1400 "offset is 0x%llx\n", netxen_nic_driver_name,
1401 (unsigned long long)off);
3ce06a32
DP		 1402 return -1;
1403 }
1404
d8313ce0 1405 addr = pci_base_offset(adapter, start);
3ce06a32
DP		 1406 if (!addr) {
1407 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1408 mem_base = pci_resource_start(adapter->pdev, 0);
1409 mem_page = start & PAGE_MASK;
1410 /* Map two pages whenever user tries to access addresses in two
1411 * consecutive pages.
1412 */
1413 if (mem_page != ((start + size - 1) & PAGE_MASK))
1414 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1415 else
1416 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
f8057b7f 1417 if (mem_ptr == NULL)
3ce06a32
DP		 1418 return -1;
1419 addr = mem_ptr;
1420 addr += start & (PAGE_SIZE - 1);
1421 write_lock_irqsave(&adapter->adapter_lock, flags);
1422 }
1423
1424 switch (size) {
1425 case 1:
1426 writeb(*(uint8_t *)data, addr);
1427 break;
1428 case 2:
1429 writew(*(uint16_t *)data, addr);
1430 break;
1431 case 4:
1432 writel(*(uint32_t *)data, addr);
1433 break;
1434 case 8:
1435 writeq(*(uint64_t *)data, addr);
1436 break;
1437 default:
1438 ret = -1;
1439 break;
1440 }
1441 write_unlock_irqrestore(&adapter->adapter_lock, flags);
3ce06a32
DP		 1442 if (mem_ptr)
1443 iounmap(mem_ptr);
1444 return ret;
1445}
1446
1447#define MAX_CTL_CHECK 1000
1448
1449int
1450netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1451 u64 off, void *data, int size)
1452{
d8313ce0 1453 unsigned long flags;
3ce06a32
DP		 1454 int i, j, ret = 0, loop, sz[2], off0;
1455 uint32_t temp;
1456 uint64_t off8, tmpw, word[2] = {0, 0};
d8313ce0 1457 void __iomem *mem_crb;
3ce06a32
DP		 1458
1459 /*
1460 * If not MN, go check for MS or invalid.
1461 */
1462 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1463 return netxen_nic_pci_mem_write_direct(adapter,
1464 off, data, size);
1465
1466 off8 = off & 0xfffffff8;
1467 off0 = off & 0x7;
1468 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1469 sz[1] = size - sz[0];
1470 loop = ((off0 + size - 1) >> 3) + 1;
d8313ce0 1471 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
3ce06a32
DP		 1472
1473 if ((size != 8) || (off0 != 0)) {
1474 for (i = 0; i < loop; i++) {
1475 if (adapter->pci_mem_read(adapter,
1476 off8 + (i << 3), &word[i], 8))
1477 return -1;
1478 }
1479 }
1480
1481 switch (size) {
1482 case 1:
1483 tmpw = *((uint8_t *)data);
1484 break;
1485 case 2:
1486 tmpw = *((uint16_t *)data);
1487 break;
1488 case 4:
1489 tmpw = *((uint32_t *)data);
1490 break;
1491 case 8:
1492 default:
1493 tmpw = *((uint64_t *)data);
1494 break;
1495 }
1496 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1497 word[0] |= tmpw << (off0 * 8);
1498
1499 if (loop == 2) {
1500 word[1] &= ~(~0ULL << (sz[1] * 8));
1501 word[1] |= tmpw >> (sz[0] * 8);
1502 }
1503
1504 write_lock_irqsave(&adapter->adapter_lock, flags);
1505 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1506
1507 for (i = 0; i < loop; i++) {
1508 writel((uint32_t)(off8 + (i << 3)),
d8313ce0 1509 (mem_crb+MIU_TEST_AGT_ADDR_LO));
3ce06a32 1510 writel(0,
d8313ce0 1511 (mem_crb+MIU_TEST_AGT_ADDR_HI));
3ce06a32 1512 writel(word[i] & 0xffffffff,
d8313ce0 1513 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
3ce06a32 1514 writel((word[i] >> 32) & 0xffffffff,
d8313ce0 1515 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
3ce06a32 1516 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
d8313ce0 1517 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32 1518 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
d8313ce0 1519 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1520
1521 for (j = 0; j < MAX_CTL_CHECK; j++) {
1522 temp = readl(
d8313ce0 1523 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1524 if ((temp & MIU_TA_CTL_BUSY) == 0)
1525 break;
1526 }
1527
1528 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1529 if (printk_ratelimit())
1530 dev_err(&adapter->pdev->dev,
1531 "failed to write through agent\n");
3ce06a32
DP		 1532 ret = -1;
1533 break;
1534 }
1535 }
1536
1537 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1538 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1539 return ret;
1540}
1541
1542int
1543netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1544 u64 off, void *data, int size)
1545{
d8313ce0 1546 unsigned long flags;
3ce06a32
DP		 1547 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1548 uint32_t temp;
1549 uint64_t off8, val, word[2] = {0, 0};
d8313ce0 1550 void __iomem *mem_crb;
3ce06a32
DP		 1551
1552
1553 /*
1554 * If not MN, go check for MS or invalid.
1555 */
1556 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1557 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1558
1559 off8 = off & 0xfffffff8;
1560 off0[0] = off & 0x7;
1561 off0[1] = 0;
1562 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1563 sz[1] = size - sz[0];
1564 loop = ((off0[0] + size - 1) >> 3) + 1;
d8313ce0 1565 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
3ce06a32
DP		 1566
1567 write_lock_irqsave(&adapter->adapter_lock, flags);
1568 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1569
1570 for (i = 0; i < loop; i++) {
1571 writel((uint32_t)(off8 + (i << 3)),
d8313ce0 1572 (mem_crb+MIU_TEST_AGT_ADDR_LO));
3ce06a32 1573 writel(0,
d8313ce0 1574 (mem_crb+MIU_TEST_AGT_ADDR_HI));
3ce06a32 1575 writel(MIU_TA_CTL_ENABLE,
d8313ce0 1576 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32 1577 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
d8313ce0 1578 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1579
1580 for (j = 0; j < MAX_CTL_CHECK; j++) {
1581 temp = readl(
d8313ce0 1582 (mem_crb+MIU_TEST_AGT_CTRL));
3ce06a32
DP		 1583 if ((temp & MIU_TA_CTL_BUSY) == 0)
1584 break;
1585 }
1586
1587 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1588 if (printk_ratelimit())
1589 dev_err(&adapter->pdev->dev,
1590 "failed to read through agent\n");
3ce06a32
DP		 1591 break;
1592 }
1593
1594 start = off0[i] >> 2;
1595 end = (off0[i] + sz[i] - 1) >> 2;
1596 for (k = start; k <= end; k++) {
1597 word[i] |= ((uint64_t) readl(
d8313ce0 1598 (mem_crb +
3ce06a32
DP		 1599 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1600 }
1601 }
1602
1603 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1604 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1605
1606 if (j >= MAX_CTL_CHECK)
1607 return -1;
1608
1609 if (sz[0] == 8) {
1610 val = word[0];
1611 } else {
1612 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1613 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1614 }
1615
1616 switch (size) {
1617 case 1:
1618 *(uint8_t *)data = val;
1619 break;
1620 case 2:
1621 *(uint16_t *)data = val;
1622 break;
1623 case 4:
1624 *(uint32_t *)data = val;
1625 break;
1626 case 8:
1627 *(uint64_t *)data = val;
1628 break;
1629 }
3ce06a32
DP		 1630 return 0;
1631}
1632
1633int
1634netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1635 u64 off, void *data, int size)
1636{
1637 int i, j, ret = 0, loop, sz[2], off0;
1638 uint32_t temp;
1639 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1640
1641 /*
1642 * If not MN, go check for MS or invalid.
1643 */
1644 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1645 mem_crb = NETXEN_CRB_QDR_NET;
1646 else {
1647 mem_crb = NETXEN_CRB_DDR_NET;
1648 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1649 return netxen_nic_pci_mem_write_direct(adapter,
1650 off, data, size);
1651 }
1652
1653 off8 = off & 0xfffffff8;
1654 off0 = off & 0x7;
1655 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1656 sz[1] = size - sz[0];
1657 loop = ((off0 + size - 1) >> 3) + 1;
1658
1659 if ((size != 8) || (off0 != 0)) {
1660 for (i = 0; i < loop; i++) {
1661 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1662 &word[i], 8))
1663 return -1;
1664 }
1665 }
1666
1667 switch (size) {
1668 case 1:
1669 tmpw = *((uint8_t *)data);
1670 break;
1671 case 2:
1672 tmpw = *((uint16_t *)data);
1673 break;
1674 case 4:
1675 tmpw = *((uint32_t *)data);
1676 break;
1677 case 8:
1678 default:
1679 tmpw = *((uint64_t *)data);
1680 break;
1681 }
1682
1683 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1684 word[0] |= tmpw << (off0 * 8);
1685
1686 if (loop == 2) {
1687 word[1] &= ~(~0ULL << (sz[1] * 8));
1688 word[1] |= tmpw >> (sz[0] * 8);
1689 }
1690
1691 /*
1692 * don't lock here - write_wx gets the lock if each time
1693 * write_lock_irqsave(&adapter->adapter_lock, flags);
1694 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1695 */
1696
1697 for (i = 0; i < loop; i++) {
1698 temp = off8 + (i << 3);
f98a9f69 1699 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
3ce06a32 1700 temp = 0;
f98a9f69 1701 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
3ce06a32 1702 temp = word[i] & 0xffffffff;
f98a9f69 1703 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
3ce06a32 1704 temp = (word[i] >> 32) & 0xffffffff;
f98a9f69 1705 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
3ce06a32 1706 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
f98a9f69 1707 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
3ce06a32 1708 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
f98a9f69 1709 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
3ce06a32
DP		 1710
1711 for (j = 0; j < MAX_CTL_CHECK; j++) {
f98a9f69 1712 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
3ce06a32
DP		 1713 if ((temp & MIU_TA_CTL_BUSY) == 0)
1714 break;
1715 }
1716
1717 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1718 if (printk_ratelimit())
1719 dev_err(&adapter->pdev->dev,
1720 "failed to write through agent\n");
3ce06a32
DP		 1721 ret = -1;
1722 break;
1723 }
1724 }
1725
1726 /*
1727 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1728 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1729 */
1730 return ret;
1731}
1732
1733int
1734netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1735 u64 off, void *data, int size)
1736{
1737 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1738 uint32_t temp;
1739 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1740
1741 /*
1742 * If not MN, go check for MS or invalid.
1743 */
1744
1745 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1746 mem_crb = NETXEN_CRB_QDR_NET;
1747 else {
1748 mem_crb = NETXEN_CRB_DDR_NET;
1749 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1750 return netxen_nic_pci_mem_read_direct(adapter,
1751 off, data, size);
1752 }
1753
1754 off8 = off & 0xfffffff8;
1755 off0[0] = off & 0x7;
1756 off0[1] = 0;
1757 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1758 sz[1] = size - sz[0];
1759 loop = ((off0[0] + size - 1) >> 3) + 1;
1760
1761 /*
1762 * don't lock here - write_wx gets the lock if each time
1763 * write_lock_irqsave(&adapter->adapter_lock, flags);
1764 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1765 */
1766
1767 for (i = 0; i < loop; i++) {
1768 temp = off8 + (i << 3);
f98a9f69 1769 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
3ce06a32 1770 temp = 0;
f98a9f69 1771 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
3ce06a32 1772 temp = MIU_TA_CTL_ENABLE;
f98a9f69 1773 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
3ce06a32 1774 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
f98a9f69 1775 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
3ce06a32
DP		 1776
1777 for (j = 0; j < MAX_CTL_CHECK; j++) {
f98a9f69 1778 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
3ce06a32
DP		 1779 if ((temp & MIU_TA_CTL_BUSY) == 0)
1780 break;
1781 }
1782
1783 if (j >= MAX_CTL_CHECK) {
39754f44
DP		 1784 if (printk_ratelimit())
1785 dev_err(&adapter->pdev->dev,
1786 "failed to read through agent\n");
3ce06a32
DP		 1787 break;
1788 }
1789
1790 start = off0[i] >> 2;
1791 end = (off0[i] + sz[i] - 1) >> 2;
1792 for (k = start; k <= end; k++) {
f98a9f69 1793 temp = NXRD32(adapter,
1fbe6323 1794 mem_crb + MIU_TEST_AGT_RDDATA(k));
3ce06a32
DP		 1795 word[i] |= ((uint64_t)temp << (32 * k));
1796 }
1797 }
1798
1799 /*
1800 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1801 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1802 */
1803
1804 if (j >= MAX_CTL_CHECK)
1805 return -1;
1806
1807 if (sz[0] == 8) {
1808 val = word[0];
1809 } else {
1810 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1811 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1812 }
1813
1814 switch (size) {
1815 case 1:
1816 *(uint8_t *)data = val;
1817 break;
1818 case 2:
1819 *(uint16_t *)data = val;
1820 break;
1821 case 4:
1822 *(uint32_t *)data = val;
1823 break;
1824 case 8:
1825 *(uint64_t *)data = val;
1826 break;
1827 }
3ce06a32
DP		 1828 return 0;
1829}
1830
1831/*
1832 * Note : only 32-bit writes!
1833 */
1834int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1835 u64 off, u32 data)
1836{
f98a9f69 1837 NXWR32(adapter, off, data);
3ce06a32
DP		 1838
1839 return 0;
1840}
1841
1842u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
1843{
f98a9f69 1844 return NXRD32(adapter, off);
3ce06a32
DP		 1845}
1846
3d396eb1
AK		 1847int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1848{
1e2d0059
DP		 1849 int offset, board_type, magic, header_version;
1850 struct pci_dev *pdev = adapter->pdev;
3d396eb1 1851
1e2d0059
DP		 1852 offset = NETXEN_BRDCFG_START +
1853 offsetof(struct netxen_board_info, magic);
1854 if (netxen_rom_fast_read(adapter, offset, &magic))
1855 return -EIO;
3d396eb1 1856
1e2d0059
DP		 1857 offset = NETXEN_BRDCFG_START +
1858 offsetof(struct netxen_board_info, header_version);
1859 if (netxen_rom_fast_read(adapter, offset, &header_version))
1860 return -EIO;
1861
1862 if (magic != NETXEN_BDINFO_MAGIC ||
1863 header_version != NETXEN_BDINFO_VERSION) {
1864 dev_err(&pdev->dev,
1865 "invalid board config, magic=%08x, version=%08x\n",
1866 magic, header_version);
1867 return -EIO;
3d396eb1
AK		 1868 }
1869
1e2d0059
DP		 1870 offset = NETXEN_BRDCFG_START +
1871 offsetof(struct netxen_board_info, board_type);
1872 if (netxen_rom_fast_read(adapter, offset, &board_type))
1873 return -EIO;
1874
1875 adapter->ahw.board_type = board_type;
1876
1877 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
f98a9f69 1878 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
c7860a2a 1879 if ((gpio & 0x8000) == 0)
1e2d0059 1880 board_type = NETXEN_BRDTYPE_P3_10G_TP;
c7860a2a
DP		 1881 }
1882
e98e3350 1883 switch (board_type) {
3d396eb1 1884 case NETXEN_BRDTYPE_P2_SB35_4G:
1e2d0059 1885 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1
AK		 1886 break;
1887 case NETXEN_BRDTYPE_P2_SB31_10G:
1888 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1889 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1890 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
e4c93c81
DP		 1891 case NETXEN_BRDTYPE_P3_HMEZ:
1892 case NETXEN_BRDTYPE_P3_XG_LOM:
1893 case NETXEN_BRDTYPE_P3_10G_CX4:
1894 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1895 case NETXEN_BRDTYPE_P3_IMEZ:
1896 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
a70f9393
DP		 1897 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1898 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
e4c93c81
DP		 1899 case NETXEN_BRDTYPE_P3_10G_XFP:
1900 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1e2d0059 1901 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 1902 break;
1903 case NETXEN_BRDTYPE_P1_BD:
1904 case NETXEN_BRDTYPE_P1_SB:
1905 case NETXEN_BRDTYPE_P1_SMAX:
1906 case NETXEN_BRDTYPE_P1_SOCK:
e4c93c81
DP		 1907 case NETXEN_BRDTYPE_P3_REF_QG:
1908 case NETXEN_BRDTYPE_P3_4_GB:
1909 case NETXEN_BRDTYPE_P3_4_GB_MM:
1e2d0059 1910 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1 1911 break;
c7860a2a 1912 case NETXEN_BRDTYPE_P3_10G_TP:
1e2d0059 1913 adapter->ahw.port_type = (adapter->portnum < 2) ?
c7860a2a
DP		 1914 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1915 break;
3d396eb1 1916 default:
1e2d0059
DP		 1917 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1918 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 1919 break;
1920 }
1921
1e2d0059 1922 return 0;
3d396eb1
AK		 1923}
1924
1925/* NIU access sections */
1926
3176ff3e 1927int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 1928{
9ad27643 1929 new_mtu += MTU_FUDGE_FACTOR;
f98a9f69 1930 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
3276fbad 1931 new_mtu);
3d396eb1
AK		 1932 return 0;
1933}
1934
3176ff3e 1935int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 1936{
9ad27643 1937 new_mtu += MTU_FUDGE_FACTOR;
3276fbad 1938 if (adapter->physical_port == 0)
f98a9f69 1939 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
4790654c 1940 else
f98a9f69 1941 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
3d396eb1
AK		 1942 return 0;
1943}
1944
3176ff3e 1945void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
3d396eb1 1946{
a608ab9c
AV		 1947 __u32 status;
1948 __u32 autoneg;
24a7a455 1949 __u32 port_mode;
3d396eb1 1950
c7860a2a
DP		 1951 if (!netif_carrier_ok(adapter->netdev)) {
1952 adapter->link_speed = 0;
1953 adapter->link_duplex = -1;
1954 adapter->link_autoneg = AUTONEG_ENABLE;
1955 return;
1956 }
24a7a455 1957
1e2d0059 1958 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
f98a9f69 1959 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
24a7a455
DP		 1960 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
1961 adapter->link_speed = SPEED_1000;
1962 adapter->link_duplex = DUPLEX_FULL;
1963 adapter->link_autoneg = AUTONEG_DISABLE;
1964 return;
1965 }
1966
80922fbc 1967 if (adapter->phy_read
24a7a455 1968 && adapter->phy_read(adapter,
3d396eb1
AK		 1969 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1970 &status) == 0) {
1971 if (netxen_get_phy_link(status)) {
1972 switch (netxen_get_phy_speed(status)) {
1973 case 0:
3176ff3e 1974 adapter->link_speed = SPEED_10;
3d396eb1
AK		 1975 break;
1976 case 1:
3176ff3e 1977 adapter->link_speed = SPEED_100;
3d396eb1
AK		 1978 break;
1979 case 2:
3176ff3e 1980 adapter->link_speed = SPEED_1000;
3d396eb1
AK		 1981 break;
1982 default:
c7860a2a 1983 adapter->link_speed = 0;
3d396eb1
AK		 1984 break;
1985 }
1986 switch (netxen_get_phy_duplex(status)) {
1987 case 0:
3176ff3e 1988 adapter->link_duplex = DUPLEX_HALF;
3d396eb1
AK		 1989 break;
1990 case 1:
3176ff3e 1991 adapter->link_duplex = DUPLEX_FULL;
3d396eb1
AK		 1992 break;
1993 default:
3176ff3e 1994 adapter->link_duplex = -1;
3d396eb1
AK		 1995 break;
1996 }
80922fbc 1997 if (adapter->phy_read
24a7a455 1998 && adapter->phy_read(adapter,
3d396eb1 1999 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
ed25ffa1 2000 &autoneg) != 0)
3176ff3e 2001 adapter->link_autoneg = autoneg;
3d396eb1
AK		 2002 } else
2003 goto link_down;
2004 } else {
2005 link_down:
c7860a2a 2006 adapter->link_speed = 0;
3176ff3e 2007 adapter->link_duplex = -1;
3d396eb1
AK		 2008 }
2009 }
2010}
2011
1e2d0059 2012void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
3d396eb1 2013{
1e2d0059 2014 u32 fw_major, fw_minor, fw_build;
cb8011ad 2015 char brd_name[NETXEN_MAX_SHORT_NAME];
8d74849b 2016 char serial_num[32];
fbb52f22 2017 int i, addr, val;
d8313ce0 2018 int *ptr32;
1e2d0059 2019 struct pci_dev *pdev = adapter->pdev;
dcd56fdb
DP		 2020
2021 adapter->driver_mismatch = 0;
2022
d8313ce0 2023 ptr32 = (int *)&serial_num;
dcd56fdb
DP		 2024 addr = NETXEN_USER_START +
2025 offsetof(struct netxen_new_user_info, serial_num);
2026 for (i = 0; i < 8; i++) {
fbb52f22
DP		 2027 if (netxen_rom_fast_read(adapter, addr, &val) == -1) {
2028 dev_err(&pdev->dev, "error reading board info\n");
dcd56fdb
DP		 2029 adapter->driver_mismatch = 1;
2030 return;
cb8011ad 2031 }
fbb52f22 2032 ptr32[i] = cpu_to_le32(val);
dcd56fdb
DP		 2033 addr += sizeof(u32);
2034 }
2035
f98a9f69
DP		 2036 fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
2037 fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
2038 fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
8d74849b 2039
2956640d 2040 adapter->fw_major = fw_major;
1e2d0059 2041 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build);
2956640d 2042
dcd56fdb 2043 if (adapter->portnum == 0) {
1e2d0059 2044 get_brd_name_by_type(adapter->ahw.board_type, brd_name);
cb8011ad 2045
11d89d63
DP		 2046 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2047 brd_name, serial_num, adapter->ahw.revision_id);
3d396eb1 2048 }
dcd56fdb 2049
1e2d0059 2050 if (adapter->fw_version < NETXEN_VERSION_CODE(3, 4, 216)) {
3d396eb1 2051 adapter->driver_mismatch = 1;
1e2d0059 2052 dev_warn(&pdev->dev, "firmware version %d.%d.%d unsupported\n",
58735567 2053 fw_major, fw_minor, fw_build);
dcd56fdb
DP		 2054 return;
2055 }
1e2d0059
DP		 2056
2057 dev_info(&pdev->dev, "firmware version %d.%d.%d\n",
2058 fw_major, fw_minor, fw_build);
2059
2060 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
f98a9f69 2061 i = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
1e2d0059
DP		 2062 adapter->ahw.cut_through = (i & 0x4) ? 1 : 0;
2063 dev_info(&pdev->dev, "firmware running in %s mode\n",
2064 adapter->ahw.cut_through ? "cut-through" : "legacy");
2065 }
3d396eb1
AK		 2066}
2067
0b72e659
DP		 2068int
2069netxen_nic_wol_supported(struct netxen_adapter *adapter)
2070{
2071 u32 wol_cfg;
2072
2073 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2074 return 0;
2075
f98a9f69 2076 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
0b72e659 2077 if (wol_cfg & (1UL << adapter->portnum)) {
f98a9f69 2078 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
0b72e659
DP		 2079 if (wol_cfg & (1 << adapter->portnum))
2080 return 1;
2081 }
2082
2083 return 0;
2084}
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