Commit | Line | Data |
---|---|---|
a46c30fd | 1 | /* myri_sbus.c: MyriCOM MyriNET SBUS card driver. |
1da177e4 | 2 | * |
a46c30fd | 3 | * Copyright (C) 1996, 1999, 2006 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | */ |
5 | ||
6 | static char version[] = | |
a46c30fd | 7 | "myri_sbus.c:v2.0 June 23, 2006 David S. Miller (davem@davemloft.net)\n"; |
1da177e4 LT |
8 | |
9 | #include <linux/module.h> | |
1da177e4 LT |
10 | #include <linux/errno.h> |
11 | #include <linux/kernel.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/fcntl.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/ioport.h> | |
16 | #include <linux/in.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/netdevice.h> | |
22 | #include <linux/etherdevice.h> | |
23 | #include <linux/skbuff.h> | |
24 | #include <linux/bitops.h> | |
25 | ||
26 | #include <net/dst.h> | |
27 | #include <net/arp.h> | |
28 | #include <net/sock.h> | |
29 | #include <net/ipv6.h> | |
30 | ||
31 | #include <asm/system.h> | |
32 | #include <asm/io.h> | |
33 | #include <asm/dma.h> | |
34 | #include <asm/byteorder.h> | |
35 | #include <asm/idprom.h> | |
36 | #include <asm/sbus.h> | |
37 | #include <asm/openprom.h> | |
38 | #include <asm/oplib.h> | |
39 | #include <asm/auxio.h> | |
40 | #include <asm/pgtable.h> | |
41 | #include <asm/irq.h> | |
42 | #include <asm/checksum.h> | |
43 | ||
44 | #include "myri_sbus.h" | |
45 | #include "myri_code.h" | |
46 | ||
47 | /* #define DEBUG_DETECT */ | |
48 | /* #define DEBUG_IRQ */ | |
49 | /* #define DEBUG_TRANSMIT */ | |
50 | /* #define DEBUG_RECEIVE */ | |
51 | /* #define DEBUG_HEADER */ | |
52 | ||
53 | #ifdef DEBUG_DETECT | |
54 | #define DET(x) printk x | |
55 | #else | |
56 | #define DET(x) | |
57 | #endif | |
58 | ||
59 | #ifdef DEBUG_IRQ | |
60 | #define DIRQ(x) printk x | |
61 | #else | |
62 | #define DIRQ(x) | |
63 | #endif | |
64 | ||
65 | #ifdef DEBUG_TRANSMIT | |
66 | #define DTX(x) printk x | |
67 | #else | |
68 | #define DTX(x) | |
69 | #endif | |
70 | ||
71 | #ifdef DEBUG_RECEIVE | |
72 | #define DRX(x) printk x | |
73 | #else | |
74 | #define DRX(x) | |
75 | #endif | |
76 | ||
77 | #ifdef DEBUG_HEADER | |
78 | #define DHDR(x) printk x | |
79 | #else | |
80 | #define DHDR(x) | |
81 | #endif | |
82 | ||
1da177e4 LT |
83 | static void myri_reset_off(void __iomem *lp, void __iomem *cregs) |
84 | { | |
85 | /* Clear IRQ mask. */ | |
86 | sbus_writel(0, lp + LANAI_EIMASK); | |
87 | ||
88 | /* Turn RESET function off. */ | |
89 | sbus_writel(CONTROL_ROFF, cregs + MYRICTRL_CTRL); | |
90 | } | |
91 | ||
92 | static void myri_reset_on(void __iomem *cregs) | |
93 | { | |
94 | /* Enable RESET function. */ | |
95 | sbus_writel(CONTROL_RON, cregs + MYRICTRL_CTRL); | |
96 | ||
97 | /* Disable IRQ's. */ | |
98 | sbus_writel(CONTROL_DIRQ, cregs + MYRICTRL_CTRL); | |
99 | } | |
100 | ||
101 | static void myri_disable_irq(void __iomem *lp, void __iomem *cregs) | |
102 | { | |
103 | sbus_writel(CONTROL_DIRQ, cregs + MYRICTRL_CTRL); | |
104 | sbus_writel(0, lp + LANAI_EIMASK); | |
105 | sbus_writel(ISTAT_HOST, lp + LANAI_ISTAT); | |
106 | } | |
107 | ||
108 | static void myri_enable_irq(void __iomem *lp, void __iomem *cregs) | |
109 | { | |
110 | sbus_writel(CONTROL_EIRQ, cregs + MYRICTRL_CTRL); | |
111 | sbus_writel(ISTAT_HOST, lp + LANAI_EIMASK); | |
112 | } | |
113 | ||
114 | static inline void bang_the_chip(struct myri_eth *mp) | |
115 | { | |
116 | struct myri_shmem __iomem *shmem = mp->shmem; | |
117 | void __iomem *cregs = mp->cregs; | |
118 | ||
119 | sbus_writel(1, &shmem->send); | |
120 | sbus_writel(CONTROL_WON, cregs + MYRICTRL_CTRL); | |
121 | } | |
122 | ||
123 | static int myri_do_handshake(struct myri_eth *mp) | |
124 | { | |
125 | struct myri_shmem __iomem *shmem = mp->shmem; | |
126 | void __iomem *cregs = mp->cregs; | |
127 | struct myri_channel __iomem *chan = &shmem->channel; | |
128 | int tick = 0; | |
129 | ||
130 | DET(("myri_do_handshake: ")); | |
131 | if (sbus_readl(&chan->state) == STATE_READY) { | |
132 | DET(("Already STATE_READY, failed.\n")); | |
133 | return -1; /* We're hosed... */ | |
134 | } | |
135 | ||
136 | myri_disable_irq(mp->lregs, cregs); | |
137 | ||
138 | while (tick++ <= 25) { | |
139 | u32 softstate; | |
140 | ||
141 | /* Wake it up. */ | |
142 | DET(("shakedown, CONTROL_WON, ")); | |
143 | sbus_writel(1, &shmem->shakedown); | |
144 | sbus_writel(CONTROL_WON, cregs + MYRICTRL_CTRL); | |
145 | ||
146 | softstate = sbus_readl(&chan->state); | |
147 | DET(("chanstate[%08x] ", softstate)); | |
148 | if (softstate == STATE_READY) { | |
149 | DET(("wakeup successful, ")); | |
150 | break; | |
151 | } | |
152 | ||
153 | if (softstate != STATE_WFN) { | |
154 | DET(("not WFN setting that, ")); | |
155 | sbus_writel(STATE_WFN, &chan->state); | |
156 | } | |
157 | ||
158 | udelay(20); | |
159 | } | |
160 | ||
161 | myri_enable_irq(mp->lregs, cregs); | |
162 | ||
163 | if (tick > 25) { | |
164 | DET(("25 ticks we lose, failure.\n")); | |
165 | return -1; | |
166 | } | |
167 | DET(("success\n")); | |
168 | return 0; | |
169 | } | |
170 | ||
171 | static int myri_load_lanai(struct myri_eth *mp) | |
172 | { | |
173 | struct net_device *dev = mp->dev; | |
174 | struct myri_shmem __iomem *shmem = mp->shmem; | |
175 | void __iomem *rptr; | |
176 | int i; | |
177 | ||
178 | myri_disable_irq(mp->lregs, mp->cregs); | |
179 | myri_reset_on(mp->cregs); | |
180 | ||
181 | rptr = mp->lanai; | |
182 | for (i = 0; i < mp->eeprom.ramsz; i++) | |
183 | sbus_writeb(0, rptr + i); | |
184 | ||
185 | if (mp->eeprom.cpuvers >= CPUVERS_3_0) | |
186 | sbus_writel(mp->eeprom.cval, mp->lregs + LANAI_CVAL); | |
187 | ||
188 | /* Load executable code. */ | |
189 | for (i = 0; i < sizeof(lanai4_code); i++) | |
190 | sbus_writeb(lanai4_code[i], rptr + (lanai4_code_off * 2) + i); | |
191 | ||
192 | /* Load data segment. */ | |
193 | for (i = 0; i < sizeof(lanai4_data); i++) | |
194 | sbus_writeb(lanai4_data[i], rptr + (lanai4_data_off * 2) + i); | |
195 | ||
196 | /* Set device address. */ | |
197 | sbus_writeb(0, &shmem->addr[0]); | |
198 | sbus_writeb(0, &shmem->addr[1]); | |
199 | for (i = 0; i < 6; i++) | |
200 | sbus_writeb(dev->dev_addr[i], | |
201 | &shmem->addr[i + 2]); | |
202 | ||
203 | /* Set SBUS bursts and interrupt mask. */ | |
204 | sbus_writel(((mp->myri_bursts & 0xf8) >> 3), &shmem->burst); | |
205 | sbus_writel(SHMEM_IMASK_RX, &shmem->imask); | |
206 | ||
207 | /* Release the LANAI. */ | |
208 | myri_disable_irq(mp->lregs, mp->cregs); | |
209 | myri_reset_off(mp->lregs, mp->cregs); | |
210 | myri_disable_irq(mp->lregs, mp->cregs); | |
211 | ||
212 | /* Wait for the reset to complete. */ | |
213 | for (i = 0; i < 5000; i++) { | |
214 | if (sbus_readl(&shmem->channel.state) != STATE_READY) | |
215 | break; | |
216 | else | |
217 | udelay(10); | |
218 | } | |
219 | ||
220 | if (i == 5000) | |
221 | printk(KERN_ERR "myricom: Chip would not reset after firmware load.\n"); | |
222 | ||
223 | i = myri_do_handshake(mp); | |
224 | if (i) | |
225 | printk(KERN_ERR "myricom: Handshake with LANAI failed.\n"); | |
226 | ||
227 | if (mp->eeprom.cpuvers == CPUVERS_4_0) | |
228 | sbus_writel(0, mp->lregs + LANAI_VERS); | |
229 | ||
230 | return i; | |
231 | } | |
232 | ||
233 | static void myri_clean_rings(struct myri_eth *mp) | |
234 | { | |
235 | struct sendq __iomem *sq = mp->sq; | |
236 | struct recvq __iomem *rq = mp->rq; | |
237 | int i; | |
238 | ||
239 | sbus_writel(0, &rq->tail); | |
240 | sbus_writel(0, &rq->head); | |
241 | for (i = 0; i < (RX_RING_SIZE+1); i++) { | |
242 | if (mp->rx_skbs[i] != NULL) { | |
243 | struct myri_rxd __iomem *rxd = &rq->myri_rxd[i]; | |
244 | u32 dma_addr; | |
245 | ||
246 | dma_addr = sbus_readl(&rxd->myri_scatters[0].addr); | |
247 | sbus_unmap_single(mp->myri_sdev, dma_addr, RX_ALLOC_SIZE, SBUS_DMA_FROMDEVICE); | |
248 | dev_kfree_skb(mp->rx_skbs[i]); | |
249 | mp->rx_skbs[i] = NULL; | |
250 | } | |
251 | } | |
252 | ||
253 | mp->tx_old = 0; | |
254 | sbus_writel(0, &sq->tail); | |
255 | sbus_writel(0, &sq->head); | |
256 | for (i = 0; i < TX_RING_SIZE; i++) { | |
257 | if (mp->tx_skbs[i] != NULL) { | |
258 | struct sk_buff *skb = mp->tx_skbs[i]; | |
259 | struct myri_txd __iomem *txd = &sq->myri_txd[i]; | |
260 | u32 dma_addr; | |
261 | ||
262 | dma_addr = sbus_readl(&txd->myri_gathers[0].addr); | |
263 | sbus_unmap_single(mp->myri_sdev, dma_addr, (skb->len + 3) & ~3, SBUS_DMA_TODEVICE); | |
264 | dev_kfree_skb(mp->tx_skbs[i]); | |
265 | mp->tx_skbs[i] = NULL; | |
266 | } | |
267 | } | |
268 | } | |
269 | ||
270 | static void myri_init_rings(struct myri_eth *mp, int from_irq) | |
271 | { | |
272 | struct recvq __iomem *rq = mp->rq; | |
273 | struct myri_rxd __iomem *rxd = &rq->myri_rxd[0]; | |
274 | struct net_device *dev = mp->dev; | |
9e24974d | 275 | gfp_t gfp_flags = GFP_KERNEL; |
1da177e4 LT |
276 | int i; |
277 | ||
278 | if (from_irq || in_interrupt()) | |
279 | gfp_flags = GFP_ATOMIC; | |
280 | ||
281 | myri_clean_rings(mp); | |
282 | for (i = 0; i < RX_RING_SIZE; i++) { | |
283 | struct sk_buff *skb = myri_alloc_skb(RX_ALLOC_SIZE, gfp_flags); | |
284 | u32 dma_addr; | |
285 | ||
286 | if (!skb) | |
287 | continue; | |
288 | mp->rx_skbs[i] = skb; | |
289 | skb->dev = dev; | |
290 | skb_put(skb, RX_ALLOC_SIZE); | |
291 | ||
292 | dma_addr = sbus_map_single(mp->myri_sdev, skb->data, RX_ALLOC_SIZE, SBUS_DMA_FROMDEVICE); | |
293 | sbus_writel(dma_addr, &rxd[i].myri_scatters[0].addr); | |
294 | sbus_writel(RX_ALLOC_SIZE, &rxd[i].myri_scatters[0].len); | |
295 | sbus_writel(i, &rxd[i].ctx); | |
296 | sbus_writel(1, &rxd[i].num_sg); | |
297 | } | |
298 | sbus_writel(0, &rq->head); | |
299 | sbus_writel(RX_RING_SIZE, &rq->tail); | |
300 | } | |
301 | ||
302 | static int myri_init(struct myri_eth *mp, int from_irq) | |
303 | { | |
304 | myri_init_rings(mp, from_irq); | |
305 | return 0; | |
306 | } | |
307 | ||
308 | static void myri_is_not_so_happy(struct myri_eth *mp) | |
309 | { | |
310 | } | |
311 | ||
312 | #ifdef DEBUG_HEADER | |
313 | static void dump_ehdr(struct ethhdr *ehdr) | |
314 | { | |
315 | printk("ehdr[h_dst(%02x:%02x:%02x:%02x:%02x:%02x)" | |
316 | "h_source(%02x:%02x:%02x:%02x:%02x:%02x)h_proto(%04x)]\n", | |
317 | ehdr->h_dest[0], ehdr->h_dest[1], ehdr->h_dest[2], | |
318 | ehdr->h_dest[3], ehdr->h_dest[4], ehdr->h_dest[4], | |
319 | ehdr->h_source[0], ehdr->h_source[1], ehdr->h_source[2], | |
320 | ehdr->h_source[3], ehdr->h_source[4], ehdr->h_source[4], | |
321 | ehdr->h_proto); | |
322 | } | |
323 | ||
324 | static void dump_ehdr_and_myripad(unsigned char *stuff) | |
325 | { | |
326 | struct ethhdr *ehdr = (struct ethhdr *) (stuff + 2); | |
327 | ||
328 | printk("pad[%02x:%02x]", stuff[0], stuff[1]); | |
329 | printk("ehdr[h_dst(%02x:%02x:%02x:%02x:%02x:%02x)" | |
330 | "h_source(%02x:%02x:%02x:%02x:%02x:%02x)h_proto(%04x)]\n", | |
331 | ehdr->h_dest[0], ehdr->h_dest[1], ehdr->h_dest[2], | |
332 | ehdr->h_dest[3], ehdr->h_dest[4], ehdr->h_dest[4], | |
333 | ehdr->h_source[0], ehdr->h_source[1], ehdr->h_source[2], | |
334 | ehdr->h_source[3], ehdr->h_source[4], ehdr->h_source[4], | |
335 | ehdr->h_proto); | |
336 | } | |
337 | #endif | |
338 | ||
339 | static void myri_tx(struct myri_eth *mp, struct net_device *dev) | |
340 | { | |
341 | struct sendq __iomem *sq= mp->sq; | |
342 | int entry = mp->tx_old; | |
343 | int limit = sbus_readl(&sq->head); | |
344 | ||
345 | DTX(("entry[%d] limit[%d] ", entry, limit)); | |
346 | if (entry == limit) | |
347 | return; | |
348 | while (entry != limit) { | |
349 | struct sk_buff *skb = mp->tx_skbs[entry]; | |
350 | u32 dma_addr; | |
351 | ||
352 | DTX(("SKB[%d] ", entry)); | |
353 | dma_addr = sbus_readl(&sq->myri_txd[entry].myri_gathers[0].addr); | |
354 | sbus_unmap_single(mp->myri_sdev, dma_addr, skb->len, SBUS_DMA_TODEVICE); | |
355 | dev_kfree_skb(skb); | |
356 | mp->tx_skbs[entry] = NULL; | |
357 | mp->enet_stats.tx_packets++; | |
358 | entry = NEXT_TX(entry); | |
359 | } | |
360 | mp->tx_old = entry; | |
361 | } | |
362 | ||
363 | /* Determine the packet's protocol ID. The rule here is that we | |
364 | * assume 802.3 if the type field is short enough to be a length. | |
365 | * This is normal practice and works for any 'now in use' protocol. | |
366 | */ | |
ab611487 | 367 | static __be16 myri_type_trans(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
368 | { |
369 | struct ethhdr *eth; | |
370 | unsigned char *rawp; | |
371 | ||
372 | skb->mac.raw = (((unsigned char *)skb->data) + MYRI_PAD_LEN); | |
373 | skb_pull(skb, dev->hard_header_len); | |
374 | eth = eth_hdr(skb); | |
375 | ||
376 | #ifdef DEBUG_HEADER | |
377 | DHDR(("myri_type_trans: ")); | |
378 | dump_ehdr(eth); | |
379 | #endif | |
380 | if (*eth->h_dest & 1) { | |
381 | if (memcmp(eth->h_dest, dev->broadcast, ETH_ALEN)==0) | |
382 | skb->pkt_type = PACKET_BROADCAST; | |
383 | else | |
384 | skb->pkt_type = PACKET_MULTICAST; | |
385 | } else if (dev->flags & (IFF_PROMISC|IFF_ALLMULTI)) { | |
386 | if (memcmp(eth->h_dest, dev->dev_addr, ETH_ALEN)) | |
387 | skb->pkt_type = PACKET_OTHERHOST; | |
388 | } | |
389 | ||
390 | if (ntohs(eth->h_proto) >= 1536) | |
391 | return eth->h_proto; | |
392 | ||
393 | rawp = skb->data; | |
394 | ||
395 | /* This is a magic hack to spot IPX packets. Older Novell breaks | |
396 | * the protocol design and runs IPX over 802.3 without an 802.2 LLC | |
397 | * layer. We look for FFFF which isn't a used 802.2 SSAP/DSAP. This | |
398 | * won't work for fault tolerant netware but does for the rest. | |
399 | */ | |
400 | if (*(unsigned short *)rawp == 0xFFFF) | |
401 | return htons(ETH_P_802_3); | |
402 | ||
403 | /* Real 802.2 LLC */ | |
404 | return htons(ETH_P_802_2); | |
405 | } | |
406 | ||
407 | static void myri_rx(struct myri_eth *mp, struct net_device *dev) | |
408 | { | |
409 | struct recvq __iomem *rq = mp->rq; | |
410 | struct recvq __iomem *rqa = mp->rqack; | |
411 | int entry = sbus_readl(&rqa->head); | |
412 | int limit = sbus_readl(&rqa->tail); | |
413 | int drops; | |
414 | ||
415 | DRX(("entry[%d] limit[%d] ", entry, limit)); | |
416 | if (entry == limit) | |
417 | return; | |
418 | drops = 0; | |
419 | DRX(("\n")); | |
420 | while (entry != limit) { | |
421 | struct myri_rxd __iomem *rxdack = &rqa->myri_rxd[entry]; | |
422 | u32 csum = sbus_readl(&rxdack->csum); | |
423 | int len = sbus_readl(&rxdack->myri_scatters[0].len); | |
424 | int index = sbus_readl(&rxdack->ctx); | |
425 | struct myri_rxd __iomem *rxd = &rq->myri_rxd[sbus_readl(&rq->tail)]; | |
426 | struct sk_buff *skb = mp->rx_skbs[index]; | |
427 | ||
428 | /* Ack it. */ | |
429 | sbus_writel(NEXT_RX(entry), &rqa->head); | |
430 | ||
431 | /* Check for errors. */ | |
432 | DRX(("rxd[%d]: %p len[%d] csum[%08x] ", entry, rxd, len, csum)); | |
433 | sbus_dma_sync_single_for_cpu(mp->myri_sdev, | |
434 | sbus_readl(&rxd->myri_scatters[0].addr), | |
435 | RX_ALLOC_SIZE, SBUS_DMA_FROMDEVICE); | |
436 | if (len < (ETH_HLEN + MYRI_PAD_LEN) || (skb->data[0] != MYRI_PAD_LEN)) { | |
437 | DRX(("ERROR[")); | |
438 | mp->enet_stats.rx_errors++; | |
439 | if (len < (ETH_HLEN + MYRI_PAD_LEN)) { | |
440 | DRX(("BAD_LENGTH] ")); | |
441 | mp->enet_stats.rx_length_errors++; | |
442 | } else { | |
443 | DRX(("NO_PADDING] ")); | |
444 | mp->enet_stats.rx_frame_errors++; | |
445 | } | |
446 | ||
447 | /* Return it to the LANAI. */ | |
448 | drop_it: | |
449 | drops++; | |
450 | DRX(("DROP ")); | |
451 | mp->enet_stats.rx_dropped++; | |
452 | sbus_dma_sync_single_for_device(mp->myri_sdev, | |
453 | sbus_readl(&rxd->myri_scatters[0].addr), | |
454 | RX_ALLOC_SIZE, | |
455 | SBUS_DMA_FROMDEVICE); | |
456 | sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len); | |
457 | sbus_writel(index, &rxd->ctx); | |
458 | sbus_writel(1, &rxd->num_sg); | |
459 | sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail); | |
460 | goto next; | |
461 | } | |
462 | ||
463 | DRX(("len[%d] ", len)); | |
464 | if (len > RX_COPY_THRESHOLD) { | |
465 | struct sk_buff *new_skb; | |
466 | u32 dma_addr; | |
467 | ||
468 | DRX(("BIGBUFF ")); | |
469 | new_skb = myri_alloc_skb(RX_ALLOC_SIZE, GFP_ATOMIC); | |
470 | if (new_skb == NULL) { | |
471 | DRX(("skb_alloc(FAILED) ")); | |
472 | goto drop_it; | |
473 | } | |
474 | sbus_unmap_single(mp->myri_sdev, | |
475 | sbus_readl(&rxd->myri_scatters[0].addr), | |
476 | RX_ALLOC_SIZE, | |
477 | SBUS_DMA_FROMDEVICE); | |
478 | mp->rx_skbs[index] = new_skb; | |
479 | new_skb->dev = dev; | |
480 | skb_put(new_skb, RX_ALLOC_SIZE); | |
481 | dma_addr = sbus_map_single(mp->myri_sdev, | |
482 | new_skb->data, | |
483 | RX_ALLOC_SIZE, | |
484 | SBUS_DMA_FROMDEVICE); | |
485 | sbus_writel(dma_addr, &rxd->myri_scatters[0].addr); | |
486 | sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len); | |
487 | sbus_writel(index, &rxd->ctx); | |
488 | sbus_writel(1, &rxd->num_sg); | |
489 | sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail); | |
490 | ||
491 | /* Trim the original skb for the netif. */ | |
492 | DRX(("trim(%d) ", len)); | |
493 | skb_trim(skb, len); | |
494 | } else { | |
495 | struct sk_buff *copy_skb = dev_alloc_skb(len); | |
496 | ||
497 | DRX(("SMALLBUFF ")); | |
498 | if (copy_skb == NULL) { | |
499 | DRX(("dev_alloc_skb(FAILED) ")); | |
500 | goto drop_it; | |
501 | } | |
502 | /* DMA sync already done above. */ | |
503 | copy_skb->dev = dev; | |
504 | DRX(("resv_and_put ")); | |
505 | skb_put(copy_skb, len); | |
506 | memcpy(copy_skb->data, skb->data, len); | |
507 | ||
508 | /* Reuse original ring buffer. */ | |
509 | DRX(("reuse ")); | |
510 | sbus_dma_sync_single_for_device(mp->myri_sdev, | |
511 | sbus_readl(&rxd->myri_scatters[0].addr), | |
512 | RX_ALLOC_SIZE, | |
513 | SBUS_DMA_FROMDEVICE); | |
514 | sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len); | |
515 | sbus_writel(index, &rxd->ctx); | |
516 | sbus_writel(1, &rxd->num_sg); | |
517 | sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail); | |
518 | ||
519 | skb = copy_skb; | |
520 | } | |
521 | ||
522 | /* Just like the happy meal we get checksums from this card. */ | |
523 | skb->csum = csum; | |
524 | skb->ip_summed = CHECKSUM_UNNECESSARY; /* XXX */ | |
525 | ||
526 | skb->protocol = myri_type_trans(skb, dev); | |
527 | DRX(("prot[%04x] netif_rx ", skb->protocol)); | |
528 | netif_rx(skb); | |
529 | ||
530 | dev->last_rx = jiffies; | |
531 | mp->enet_stats.rx_packets++; | |
532 | mp->enet_stats.rx_bytes += len; | |
533 | next: | |
534 | DRX(("NEXT\n")); | |
535 | entry = NEXT_RX(entry); | |
536 | } | |
537 | } | |
538 | ||
539 | static irqreturn_t myri_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |
540 | { | |
541 | struct net_device *dev = (struct net_device *) dev_id; | |
542 | struct myri_eth *mp = (struct myri_eth *) dev->priv; | |
543 | void __iomem *lregs = mp->lregs; | |
544 | struct myri_channel __iomem *chan = &mp->shmem->channel; | |
545 | unsigned long flags; | |
546 | u32 status; | |
547 | int handled = 0; | |
548 | ||
549 | spin_lock_irqsave(&mp->irq_lock, flags); | |
550 | ||
551 | status = sbus_readl(lregs + LANAI_ISTAT); | |
552 | DIRQ(("myri_interrupt: status[%08x] ", status)); | |
553 | if (status & ISTAT_HOST) { | |
554 | u32 softstate; | |
555 | ||
556 | handled = 1; | |
557 | DIRQ(("IRQ_DISAB ")); | |
558 | myri_disable_irq(lregs, mp->cregs); | |
559 | softstate = sbus_readl(&chan->state); | |
560 | DIRQ(("state[%08x] ", softstate)); | |
561 | if (softstate != STATE_READY) { | |
562 | DIRQ(("myri_not_so_happy ")); | |
563 | myri_is_not_so_happy(mp); | |
564 | } | |
565 | DIRQ(("\nmyri_rx: ")); | |
566 | myri_rx(mp, dev); | |
567 | DIRQ(("\nistat=ISTAT_HOST ")); | |
568 | sbus_writel(ISTAT_HOST, lregs + LANAI_ISTAT); | |
569 | DIRQ(("IRQ_ENAB ")); | |
570 | myri_enable_irq(lregs, mp->cregs); | |
571 | } | |
572 | DIRQ(("\n")); | |
573 | ||
574 | spin_unlock_irqrestore(&mp->irq_lock, flags); | |
575 | ||
576 | return IRQ_RETVAL(handled); | |
577 | } | |
578 | ||
579 | static int myri_open(struct net_device *dev) | |
580 | { | |
581 | struct myri_eth *mp = (struct myri_eth *) dev->priv; | |
582 | ||
583 | return myri_init(mp, in_interrupt()); | |
584 | } | |
585 | ||
586 | static int myri_close(struct net_device *dev) | |
587 | { | |
588 | struct myri_eth *mp = (struct myri_eth *) dev->priv; | |
589 | ||
590 | myri_clean_rings(mp); | |
591 | return 0; | |
592 | } | |
593 | ||
594 | static void myri_tx_timeout(struct net_device *dev) | |
595 | { | |
596 | struct myri_eth *mp = (struct myri_eth *) dev->priv; | |
597 | ||
598 | printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name); | |
599 | ||
600 | mp->enet_stats.tx_errors++; | |
601 | myri_init(mp, 0); | |
602 | netif_wake_queue(dev); | |
603 | } | |
604 | ||
605 | static int myri_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
606 | { | |
607 | struct myri_eth *mp = (struct myri_eth *) dev->priv; | |
608 | struct sendq __iomem *sq = mp->sq; | |
609 | struct myri_txd __iomem *txd; | |
610 | unsigned long flags; | |
611 | unsigned int head, tail; | |
612 | int len, entry; | |
613 | u32 dma_addr; | |
614 | ||
615 | DTX(("myri_start_xmit: ")); | |
616 | ||
617 | myri_tx(mp, dev); | |
618 | ||
619 | netif_stop_queue(dev); | |
620 | ||
621 | /* This is just to prevent multiple PIO reads for TX_BUFFS_AVAIL. */ | |
622 | head = sbus_readl(&sq->head); | |
623 | tail = sbus_readl(&sq->tail); | |
624 | ||
625 | if (!TX_BUFFS_AVAIL(head, tail)) { | |
626 | DTX(("no buffs available, returning 1\n")); | |
627 | return 1; | |
628 | } | |
629 | ||
630 | spin_lock_irqsave(&mp->irq_lock, flags); | |
631 | ||
632 | DHDR(("xmit[skbdata(%p)]\n", skb->data)); | |
633 | #ifdef DEBUG_HEADER | |
634 | dump_ehdr_and_myripad(((unsigned char *) skb->data)); | |
635 | #endif | |
636 | ||
637 | /* XXX Maybe this can go as well. */ | |
638 | len = skb->len; | |
639 | if (len & 3) { | |
640 | DTX(("len&3 ")); | |
641 | len = (len + 4) & (~3); | |
642 | } | |
643 | ||
644 | entry = sbus_readl(&sq->tail); | |
645 | ||
646 | txd = &sq->myri_txd[entry]; | |
647 | mp->tx_skbs[entry] = skb; | |
648 | ||
649 | /* Must do this before we sbus map it. */ | |
650 | if (skb->data[MYRI_PAD_LEN] & 0x1) { | |
651 | sbus_writew(0xffff, &txd->addr[0]); | |
652 | sbus_writew(0xffff, &txd->addr[1]); | |
653 | sbus_writew(0xffff, &txd->addr[2]); | |
654 | sbus_writew(0xffff, &txd->addr[3]); | |
655 | } else { | |
656 | sbus_writew(0xffff, &txd->addr[0]); | |
657 | sbus_writew((skb->data[0] << 8) | skb->data[1], &txd->addr[1]); | |
658 | sbus_writew((skb->data[2] << 8) | skb->data[3], &txd->addr[2]); | |
659 | sbus_writew((skb->data[4] << 8) | skb->data[5], &txd->addr[3]); | |
660 | } | |
661 | ||
662 | dma_addr = sbus_map_single(mp->myri_sdev, skb->data, len, SBUS_DMA_TODEVICE); | |
663 | sbus_writel(dma_addr, &txd->myri_gathers[0].addr); | |
664 | sbus_writel(len, &txd->myri_gathers[0].len); | |
665 | sbus_writel(1, &txd->num_sg); | |
666 | sbus_writel(KERNEL_CHANNEL, &txd->chan); | |
667 | sbus_writel(len, &txd->len); | |
668 | sbus_writel((u32)-1, &txd->csum_off); | |
669 | sbus_writel(0, &txd->csum_field); | |
670 | ||
671 | sbus_writel(NEXT_TX(entry), &sq->tail); | |
672 | DTX(("BangTheChip ")); | |
673 | bang_the_chip(mp); | |
674 | ||
675 | DTX(("tbusy=0, returning 0\n")); | |
676 | netif_start_queue(dev); | |
677 | spin_unlock_irqrestore(&mp->irq_lock, flags); | |
678 | return 0; | |
679 | } | |
680 | ||
681 | /* Create the MyriNet MAC header for an arbitrary protocol layer | |
682 | * | |
683 | * saddr=NULL means use device source address | |
684 | * daddr=NULL means leave destination address (eg unresolved arp) | |
685 | */ | |
686 | static int myri_header(struct sk_buff *skb, struct net_device *dev, unsigned short type, | |
687 | void *daddr, void *saddr, unsigned len) | |
688 | { | |
689 | struct ethhdr *eth = (struct ethhdr *) skb_push(skb, ETH_HLEN); | |
690 | unsigned char *pad = (unsigned char *) skb_push(skb, MYRI_PAD_LEN); | |
691 | ||
692 | #ifdef DEBUG_HEADER | |
693 | DHDR(("myri_header: pad[%02x,%02x] ", pad[0], pad[1])); | |
694 | dump_ehdr(eth); | |
695 | #endif | |
696 | ||
697 | /* Set the MyriNET padding identifier. */ | |
698 | pad[0] = MYRI_PAD_LEN; | |
699 | pad[1] = 0xab; | |
700 | ||
701 | /* Set the protocol type. For a packet of type ETH_P_802_3 we put the length | |
702 | * in here instead. It is up to the 802.2 layer to carry protocol information. | |
703 | */ | |
704 | if (type != ETH_P_802_3) | |
705 | eth->h_proto = htons(type); | |
706 | else | |
707 | eth->h_proto = htons(len); | |
708 | ||
709 | /* Set the source hardware address. */ | |
710 | if (saddr) | |
711 | memcpy(eth->h_source, saddr, dev->addr_len); | |
712 | else | |
713 | memcpy(eth->h_source, dev->dev_addr, dev->addr_len); | |
714 | ||
715 | /* Anyway, the loopback-device should never use this function... */ | |
716 | if (dev->flags & IFF_LOOPBACK) { | |
717 | int i; | |
718 | for (i = 0; i < dev->addr_len; i++) | |
719 | eth->h_dest[i] = 0; | |
720 | return(dev->hard_header_len); | |
721 | } | |
722 | ||
723 | if (daddr) { | |
724 | memcpy(eth->h_dest, daddr, dev->addr_len); | |
725 | return dev->hard_header_len; | |
726 | } | |
727 | return -dev->hard_header_len; | |
728 | } | |
729 | ||
730 | /* Rebuild the MyriNet MAC header. This is called after an ARP | |
731 | * (or in future other address resolution) has completed on this | |
732 | * sk_buff. We now let ARP fill in the other fields. | |
733 | */ | |
734 | static int myri_rebuild_header(struct sk_buff *skb) | |
735 | { | |
736 | unsigned char *pad = (unsigned char *) skb->data; | |
737 | struct ethhdr *eth = (struct ethhdr *) (pad + MYRI_PAD_LEN); | |
738 | struct net_device *dev = skb->dev; | |
739 | ||
740 | #ifdef DEBUG_HEADER | |
741 | DHDR(("myri_rebuild_header: pad[%02x,%02x] ", pad[0], pad[1])); | |
742 | dump_ehdr(eth); | |
743 | #endif | |
744 | ||
745 | /* Refill MyriNet padding identifiers, this is just being anal. */ | |
746 | pad[0] = MYRI_PAD_LEN; | |
747 | pad[1] = 0xab; | |
748 | ||
749 | switch (eth->h_proto) | |
750 | { | |
751 | #ifdef CONFIG_INET | |
752 | case __constant_htons(ETH_P_IP): | |
753 | return arp_find(eth->h_dest, skb); | |
754 | #endif | |
755 | ||
756 | default: | |
757 | printk(KERN_DEBUG | |
758 | "%s: unable to resolve type %X addresses.\n", | |
759 | dev->name, (int)eth->h_proto); | |
760 | ||
761 | memcpy(eth->h_source, dev->dev_addr, dev->addr_len); | |
762 | return 0; | |
763 | break; | |
764 | } | |
765 | ||
766 | return 0; | |
767 | } | |
768 | ||
769 | int myri_header_cache(struct neighbour *neigh, struct hh_cache *hh) | |
770 | { | |
771 | unsigned short type = hh->hh_type; | |
772 | unsigned char *pad; | |
773 | struct ethhdr *eth; | |
774 | struct net_device *dev = neigh->dev; | |
775 | ||
776 | pad = ((unsigned char *) hh->hh_data) + | |
777 | HH_DATA_OFF(sizeof(*eth) + MYRI_PAD_LEN); | |
778 | eth = (struct ethhdr *) (pad + MYRI_PAD_LEN); | |
779 | ||
780 | if (type == __constant_htons(ETH_P_802_3)) | |
781 | return -1; | |
782 | ||
783 | /* Refill MyriNet padding identifiers, this is just being anal. */ | |
784 | pad[0] = MYRI_PAD_LEN; | |
785 | pad[1] = 0xab; | |
786 | ||
787 | eth->h_proto = type; | |
788 | memcpy(eth->h_source, dev->dev_addr, dev->addr_len); | |
789 | memcpy(eth->h_dest, neigh->ha, dev->addr_len); | |
790 | hh->hh_len = 16; | |
791 | return 0; | |
792 | } | |
793 | ||
794 | ||
795 | /* Called by Address Resolution module to notify changes in address. */ | |
796 | void myri_header_cache_update(struct hh_cache *hh, struct net_device *dev, unsigned char * haddr) | |
797 | { | |
798 | memcpy(((u8*)hh->hh_data) + HH_DATA_OFF(sizeof(struct ethhdr)), | |
799 | haddr, dev->addr_len); | |
800 | } | |
801 | ||
802 | static int myri_change_mtu(struct net_device *dev, int new_mtu) | |
803 | { | |
804 | if ((new_mtu < (ETH_HLEN + MYRI_PAD_LEN)) || (new_mtu > MYRINET_MTU)) | |
805 | return -EINVAL; | |
806 | dev->mtu = new_mtu; | |
807 | return 0; | |
808 | } | |
809 | ||
810 | static struct net_device_stats *myri_get_stats(struct net_device *dev) | |
811 | { return &(((struct myri_eth *)dev->priv)->enet_stats); } | |
812 | ||
813 | static void myri_set_multicast(struct net_device *dev) | |
814 | { | |
815 | /* Do nothing, all MyriCOM nodes transmit multicast frames | |
816 | * as broadcast packets... | |
817 | */ | |
818 | } | |
819 | ||
820 | static inline void set_boardid_from_idprom(struct myri_eth *mp, int num) | |
821 | { | |
822 | mp->eeprom.id[0] = 0; | |
823 | mp->eeprom.id[1] = idprom->id_machtype; | |
824 | mp->eeprom.id[2] = (idprom->id_sernum >> 16) & 0xff; | |
825 | mp->eeprom.id[3] = (idprom->id_sernum >> 8) & 0xff; | |
826 | mp->eeprom.id[4] = (idprom->id_sernum >> 0) & 0xff; | |
827 | mp->eeprom.id[5] = num; | |
828 | } | |
829 | ||
830 | static inline void determine_reg_space_size(struct myri_eth *mp) | |
831 | { | |
832 | switch(mp->eeprom.cpuvers) { | |
833 | case CPUVERS_2_3: | |
834 | case CPUVERS_3_0: | |
835 | case CPUVERS_3_1: | |
836 | case CPUVERS_3_2: | |
837 | mp->reg_size = (3 * 128 * 1024) + 4096; | |
838 | break; | |
839 | ||
840 | case CPUVERS_4_0: | |
841 | case CPUVERS_4_1: | |
842 | mp->reg_size = ((4096<<1) + mp->eeprom.ramsz); | |
843 | break; | |
844 | ||
845 | case CPUVERS_4_2: | |
846 | case CPUVERS_5_0: | |
847 | default: | |
848 | printk("myricom: AIEEE weird cpu version %04x assuming pre4.0\n", | |
849 | mp->eeprom.cpuvers); | |
850 | mp->reg_size = (3 * 128 * 1024) + 4096; | |
851 | }; | |
852 | } | |
853 | ||
854 | #ifdef DEBUG_DETECT | |
855 | static void dump_eeprom(struct myri_eth *mp) | |
856 | { | |
857 | printk("EEPROM: clockval[%08x] cpuvers[%04x] " | |
858 | "id[%02x,%02x,%02x,%02x,%02x,%02x]\n", | |
859 | mp->eeprom.cval, mp->eeprom.cpuvers, | |
860 | mp->eeprom.id[0], mp->eeprom.id[1], mp->eeprom.id[2], | |
861 | mp->eeprom.id[3], mp->eeprom.id[4], mp->eeprom.id[5]); | |
862 | printk("EEPROM: ramsz[%08x]\n", mp->eeprom.ramsz); | |
863 | printk("EEPROM: fvers[%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", | |
864 | mp->eeprom.fvers[0], mp->eeprom.fvers[1], mp->eeprom.fvers[2], | |
865 | mp->eeprom.fvers[3], mp->eeprom.fvers[4], mp->eeprom.fvers[5], | |
866 | mp->eeprom.fvers[6], mp->eeprom.fvers[7]); | |
867 | printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", | |
868 | mp->eeprom.fvers[8], mp->eeprom.fvers[9], mp->eeprom.fvers[10], | |
869 | mp->eeprom.fvers[11], mp->eeprom.fvers[12], mp->eeprom.fvers[13], | |
870 | mp->eeprom.fvers[14], mp->eeprom.fvers[15]); | |
871 | printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", | |
872 | mp->eeprom.fvers[16], mp->eeprom.fvers[17], mp->eeprom.fvers[18], | |
873 | mp->eeprom.fvers[19], mp->eeprom.fvers[20], mp->eeprom.fvers[21], | |
874 | mp->eeprom.fvers[22], mp->eeprom.fvers[23]); | |
875 | printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x]\n", | |
876 | mp->eeprom.fvers[24], mp->eeprom.fvers[25], mp->eeprom.fvers[26], | |
877 | mp->eeprom.fvers[27], mp->eeprom.fvers[28], mp->eeprom.fvers[29], | |
878 | mp->eeprom.fvers[30], mp->eeprom.fvers[31]); | |
879 | printk("EEPROM: mvers[%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n", | |
880 | mp->eeprom.mvers[0], mp->eeprom.mvers[1], mp->eeprom.mvers[2], | |
881 | mp->eeprom.mvers[3], mp->eeprom.mvers[4], mp->eeprom.mvers[5], | |
882 | mp->eeprom.mvers[6], mp->eeprom.mvers[7]); | |
883 | printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x]\n", | |
884 | mp->eeprom.mvers[8], mp->eeprom.mvers[9], mp->eeprom.mvers[10], | |
885 | mp->eeprom.mvers[11], mp->eeprom.mvers[12], mp->eeprom.mvers[13], | |
886 | mp->eeprom.mvers[14], mp->eeprom.mvers[15]); | |
887 | printk("EEPROM: dlval[%04x] brd_type[%04x] bus_type[%04x] prod_code[%04x]\n", | |
888 | mp->eeprom.dlval, mp->eeprom.brd_type, mp->eeprom.bus_type, | |
889 | mp->eeprom.prod_code); | |
890 | printk("EEPROM: serial_num[%08x]\n", mp->eeprom.serial_num); | |
891 | } | |
892 | #endif | |
893 | ||
a46c30fd | 894 | static int __init myri_ether_init(struct sbus_dev *sdev) |
1da177e4 | 895 | { |
a46c30fd | 896 | static int num; |
1da177e4 LT |
897 | static unsigned version_printed; |
898 | struct net_device *dev; | |
899 | struct myri_eth *mp; | |
900 | unsigned char prop_buf[32]; | |
901 | int i; | |
902 | ||
903 | DET(("myri_ether_init(%p,%d):\n", sdev, num)); | |
904 | dev = alloc_etherdev(sizeof(struct myri_eth)); | |
905 | ||
906 | if (!dev) | |
907 | return -ENOMEM; | |
908 | ||
909 | if (version_printed++ == 0) | |
910 | printk(version); | |
911 | ||
a46c30fd DM |
912 | SET_MODULE_OWNER(dev); |
913 | SET_NETDEV_DEV(dev, &sdev->ofdev.dev); | |
914 | ||
1da177e4 LT |
915 | mp = (struct myri_eth *) dev->priv; |
916 | spin_lock_init(&mp->irq_lock); | |
917 | mp->myri_sdev = sdev; | |
918 | ||
919 | /* Clean out skb arrays. */ | |
920 | for (i = 0; i < (RX_RING_SIZE + 1); i++) | |
921 | mp->rx_skbs[i] = NULL; | |
922 | ||
923 | for (i = 0; i < TX_RING_SIZE; i++) | |
924 | mp->tx_skbs[i] = NULL; | |
925 | ||
926 | /* First check for EEPROM information. */ | |
927 | i = prom_getproperty(sdev->prom_node, "myrinet-eeprom-info", | |
928 | (char *)&mp->eeprom, sizeof(struct myri_eeprom)); | |
929 | DET(("prom_getprop(myrinet-eeprom-info) returns %d\n", i)); | |
930 | if (i == 0 || i == -1) { | |
931 | /* No eeprom property, must cook up the values ourselves. */ | |
932 | DET(("No EEPROM: ")); | |
933 | mp->eeprom.bus_type = BUS_TYPE_SBUS; | |
934 | mp->eeprom.cpuvers = prom_getintdefault(sdev->prom_node,"cpu_version",0); | |
935 | mp->eeprom.cval = prom_getintdefault(sdev->prom_node,"clock_value",0); | |
936 | mp->eeprom.ramsz = prom_getintdefault(sdev->prom_node,"sram_size",0); | |
937 | DET(("cpuvers[%d] cval[%d] ramsz[%d]\n", mp->eeprom.cpuvers, | |
938 | mp->eeprom.cval, mp->eeprom.ramsz)); | |
939 | if (mp->eeprom.cpuvers == 0) { | |
940 | DET(("EEPROM: cpuvers was zero, setting to %04x\n",CPUVERS_2_3)); | |
941 | mp->eeprom.cpuvers = CPUVERS_2_3; | |
942 | } | |
943 | if (mp->eeprom.cpuvers < CPUVERS_3_0) { | |
944 | DET(("EEPROM: cpuvers < CPUVERS_3_0, clockval set to zero.\n")); | |
945 | mp->eeprom.cval = 0; | |
946 | } | |
947 | if (mp->eeprom.ramsz == 0) { | |
948 | DET(("EEPROM: ramsz == 0, setting to 128k\n")); | |
949 | mp->eeprom.ramsz = (128 * 1024); | |
950 | } | |
951 | i = prom_getproperty(sdev->prom_node, "myrinet-board-id", | |
952 | &prop_buf[0], 10); | |
953 | DET(("EEPROM: prom_getprop(myrinet-board-id) returns %d\n", i)); | |
954 | if ((i != 0) && (i != -1)) | |
955 | memcpy(&mp->eeprom.id[0], &prop_buf[0], 6); | |
956 | else | |
957 | set_boardid_from_idprom(mp, num); | |
958 | i = prom_getproperty(sdev->prom_node, "fpga_version", | |
959 | &mp->eeprom.fvers[0], 32); | |
960 | DET(("EEPROM: prom_getprop(fpga_version) returns %d\n", i)); | |
961 | if (i == 0 || i == -1) | |
962 | memset(&mp->eeprom.fvers[0], 0, 32); | |
963 | ||
964 | if (mp->eeprom.cpuvers == CPUVERS_4_1) { | |
965 | DET(("EEPROM: cpuvers CPUVERS_4_1, ")); | |
966 | if (mp->eeprom.ramsz == (128 * 1024)) { | |
967 | DET(("ramsize 128k, setting to 256k, ")); | |
968 | mp->eeprom.ramsz = (256 * 1024); | |
969 | } | |
970 | if ((mp->eeprom.cval==0x40414041)||(mp->eeprom.cval==0x90449044)){ | |
971 | DET(("changing cval from %08x to %08x ", | |
972 | mp->eeprom.cval, 0x50e450e4)); | |
973 | mp->eeprom.cval = 0x50e450e4; | |
974 | } | |
975 | DET(("\n")); | |
976 | } | |
977 | } | |
978 | #ifdef DEBUG_DETECT | |
979 | dump_eeprom(mp); | |
980 | #endif | |
981 | ||
982 | for (i = 0; i < 6; i++) | |
983 | dev->dev_addr[i] = mp->eeprom.id[i]; | |
984 | ||
985 | determine_reg_space_size(mp); | |
986 | ||
987 | /* Map in the MyriCOM register/localram set. */ | |
988 | if (mp->eeprom.cpuvers < CPUVERS_4_0) { | |
989 | /* XXX Makes no sense, if control reg is non-existant this | |
990 | * XXX driver cannot function at all... maybe pre-4.0 is | |
991 | * XXX only a valid version for PCI cards? Ask feldy... | |
992 | */ | |
993 | DET(("Mapping regs for cpuvers < CPUVERS_4_0\n")); | |
994 | mp->regs = sbus_ioremap(&sdev->resource[0], 0, | |
995 | mp->reg_size, "MyriCOM Regs"); | |
996 | if (!mp->regs) { | |
997 | printk("MyriCOM: Cannot map MyriCOM registers.\n"); | |
998 | goto err; | |
999 | } | |
1000 | mp->lanai = mp->regs + (256 * 1024); | |
1001 | mp->lregs = mp->lanai + (0x10000 * 2); | |
1002 | } else { | |
1003 | DET(("Mapping regs for cpuvers >= CPUVERS_4_0\n")); | |
1004 | mp->cregs = sbus_ioremap(&sdev->resource[0], 0, | |
1005 | PAGE_SIZE, "MyriCOM Control Regs"); | |
1006 | mp->lregs = sbus_ioremap(&sdev->resource[0], (256 * 1024), | |
1007 | PAGE_SIZE, "MyriCOM LANAI Regs"); | |
1008 | mp->lanai = | |
1009 | sbus_ioremap(&sdev->resource[0], (512 * 1024), | |
1010 | mp->eeprom.ramsz, "MyriCOM SRAM"); | |
1011 | } | |
1012 | DET(("Registers mapped: cregs[%p] lregs[%p] lanai[%p]\n", | |
1013 | mp->cregs, mp->lregs, mp->lanai)); | |
1014 | ||
1015 | if (mp->eeprom.cpuvers >= CPUVERS_4_0) | |
1016 | mp->shmem_base = 0xf000; | |
1017 | else | |
1018 | mp->shmem_base = 0x8000; | |
1019 | ||
1020 | DET(("Shared memory base is %04x, ", mp->shmem_base)); | |
1021 | ||
1022 | mp->shmem = (struct myri_shmem __iomem *) | |
1023 | (mp->lanai + (mp->shmem_base * 2)); | |
1024 | DET(("shmem mapped at %p\n", mp->shmem)); | |
1025 | ||
1026 | mp->rqack = &mp->shmem->channel.recvqa; | |
1027 | mp->rq = &mp->shmem->channel.recvq; | |
1028 | mp->sq = &mp->shmem->channel.sendq; | |
1029 | ||
1030 | /* Reset the board. */ | |
1031 | DET(("Resetting LANAI\n")); | |
1032 | myri_reset_off(mp->lregs, mp->cregs); | |
1033 | myri_reset_on(mp->cregs); | |
1034 | ||
1035 | /* Turn IRQ's off. */ | |
1036 | myri_disable_irq(mp->lregs, mp->cregs); | |
1037 | ||
1038 | /* Reset once more. */ | |
1039 | myri_reset_on(mp->cregs); | |
1040 | ||
1041 | /* Get the supported DVMA burst sizes from our SBUS. */ | |
1042 | mp->myri_bursts = prom_getintdefault(mp->myri_sdev->bus->prom_node, | |
1043 | "burst-sizes", 0x00); | |
1044 | ||
1045 | if (!sbus_can_burst64(sdev)) | |
1046 | mp->myri_bursts &= ~(DMA_BURST64); | |
1047 | ||
1048 | DET(("MYRI bursts %02x\n", mp->myri_bursts)); | |
1049 | ||
1050 | /* Encode SBUS interrupt level in second control register. */ | |
1051 | i = prom_getint(sdev->prom_node, "interrupts"); | |
1052 | if (i == 0) | |
1053 | i = 4; | |
1054 | DET(("prom_getint(interrupts)==%d, irqlvl set to %04x\n", | |
1055 | i, (1 << i))); | |
1056 | ||
1057 | sbus_writel((1 << i), mp->cregs + MYRICTRL_IRQLVL); | |
1058 | ||
1059 | mp->dev = dev; | |
1060 | dev->open = &myri_open; | |
1061 | dev->stop = &myri_close; | |
1062 | dev->hard_start_xmit = &myri_start_xmit; | |
1063 | dev->tx_timeout = &myri_tx_timeout; | |
1064 | dev->watchdog_timeo = 5*HZ; | |
1065 | dev->get_stats = &myri_get_stats; | |
1066 | dev->set_multicast_list = &myri_set_multicast; | |
1067 | dev->irq = sdev->irqs[0]; | |
1068 | ||
1069 | /* Register interrupt handler now. */ | |
1070 | DET(("Requesting MYRIcom IRQ line.\n")); | |
1071 | if (request_irq(dev->irq, &myri_interrupt, | |
1fb9df5d | 1072 | IRQF_SHARED, "MyriCOM Ethernet", (void *) dev)) { |
1da177e4 LT |
1073 | printk("MyriCOM: Cannot register interrupt handler.\n"); |
1074 | goto err; | |
1075 | } | |
1076 | ||
1077 | dev->mtu = MYRINET_MTU; | |
1078 | dev->change_mtu = myri_change_mtu; | |
1079 | dev->hard_header = myri_header; | |
1080 | dev->rebuild_header = myri_rebuild_header; | |
1081 | dev->hard_header_len = (ETH_HLEN + MYRI_PAD_LEN); | |
1082 | dev->hard_header_cache = myri_header_cache; | |
1083 | dev->header_cache_update= myri_header_cache_update; | |
1084 | ||
1085 | /* Load code onto the LANai. */ | |
1086 | DET(("Loading LANAI firmware\n")); | |
1087 | myri_load_lanai(mp); | |
1088 | ||
1089 | if (register_netdev(dev)) { | |
1090 | printk("MyriCOM: Cannot register device.\n"); | |
1091 | goto err_free_irq; | |
1092 | } | |
1093 | ||
a46c30fd DM |
1094 | dev_set_drvdata(&sdev->ofdev.dev, mp); |
1095 | ||
1096 | num++; | |
1da177e4 LT |
1097 | |
1098 | printk("%s: MyriCOM MyriNET Ethernet ", dev->name); | |
1099 | ||
1100 | for (i = 0; i < 6; i++) | |
1101 | printk("%2.2x%c", dev->dev_addr[i], | |
1102 | i == 5 ? ' ' : ':'); | |
1103 | printk("\n"); | |
1104 | ||
1105 | return 0; | |
1106 | ||
1107 | err_free_irq: | |
1108 | free_irq(dev->irq, dev); | |
1109 | err: | |
1110 | /* This will also free the co-allocated 'dev->priv' */ | |
1111 | free_netdev(dev); | |
1112 | return -ENODEV; | |
1113 | } | |
1114 | ||
1da177e4 | 1115 | |
a46c30fd DM |
1116 | static int __devinit myri_sbus_probe(struct of_device *dev, const struct of_device_id *match) |
1117 | { | |
1118 | struct sbus_dev *sdev = to_sbus_device(&dev->dev); | |
1da177e4 | 1119 | |
a46c30fd | 1120 | return myri_ether_init(sdev); |
1da177e4 LT |
1121 | } |
1122 | ||
a46c30fd | 1123 | static int __devexit myri_sbus_remove(struct of_device *dev) |
1da177e4 | 1124 | { |
a46c30fd DM |
1125 | struct myri_eth *mp = dev_get_drvdata(&dev->dev); |
1126 | struct net_device *net_dev = mp->dev; | |
1da177e4 | 1127 | |
a46c30fd | 1128 | unregister_netdevice(net_dev); |
1da177e4 | 1129 | |
a46c30fd DM |
1130 | free_irq(net_dev->irq, net_dev); |
1131 | ||
1132 | if (mp->eeprom.cpuvers < CPUVERS_4_0) { | |
1133 | sbus_iounmap(mp->regs, mp->reg_size); | |
1134 | } else { | |
1135 | sbus_iounmap(mp->cregs, PAGE_SIZE); | |
1136 | sbus_iounmap(mp->lregs, (256 * 1024)); | |
1137 | sbus_iounmap(mp->lanai, (512 * 1024)); | |
1da177e4 | 1138 | } |
a46c30fd DM |
1139 | |
1140 | free_netdev(net_dev); | |
1141 | ||
1142 | dev_set_drvdata(&dev->dev, NULL); | |
1143 | ||
1da177e4 LT |
1144 | return 0; |
1145 | } | |
1146 | ||
a46c30fd DM |
1147 | static struct of_device_id myri_sbus_match[] = { |
1148 | { | |
1149 | .name = "MYRICOM,mlanai", | |
1150 | }, | |
1151 | { | |
1152 | .name = "myri", | |
1153 | }, | |
1154 | {}, | |
1155 | }; | |
1156 | ||
1157 | MODULE_DEVICE_TABLE(of, myri_sbus_match); | |
1158 | ||
1159 | static struct of_platform_driver myri_sbus_driver = { | |
1160 | .name = "myri", | |
1161 | .match_table = myri_sbus_match, | |
1162 | .probe = myri_sbus_probe, | |
1163 | .remove = __devexit_p(myri_sbus_remove), | |
1164 | }; | |
1165 | ||
1166 | static int __init myri_sbus_init(void) | |
1167 | { | |
1168 | return of_register_driver(&myri_sbus_driver, &sbus_bus_type); | |
1169 | } | |
1170 | ||
1171 | static void __exit myri_sbus_exit(void) | |
1da177e4 | 1172 | { |
a46c30fd | 1173 | of_unregister_driver(&myri_sbus_driver); |
1da177e4 LT |
1174 | } |
1175 | ||
a46c30fd DM |
1176 | module_init(myri_sbus_init); |
1177 | module_exit(myri_sbus_exit); | |
1178 | ||
1da177e4 | 1179 | MODULE_LICENSE("GPL"); |