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myri10ge: prevent 4k rdma on SGI TIOCE chipset
[linux-2.6-block.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4a2e612a 4 * Copyright (C) 2005 - 2007 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
51#include <linux/ip.h>
52#include <linux/inet.h>
53#include <linux/in.h>
54#include <linux/ethtool.h>
55#include <linux/firmware.h>
56#include <linux/delay.h>
57#include <linux/version.h>
58#include <linux/timer.h>
59#include <linux/vmalloc.h>
60#include <linux/crc32.h>
61#include <linux/moduleparam.h>
62#include <linux/io.h>
63#include <net/checksum.h>
64#include <asm/byteorder.h>
65#include <asm/io.h>
0da34b6d
BG		 66#include <asm/processor.h>
67#ifdef CONFIG_MTRR
68#include <asm/mtrr.h>
69#endif
70
71#include "myri10ge_mcp.h"
72#include "myri10ge_mcp_gen_header.h"
73
b2db8dd4 74#define MYRI10GE_VERSION_STR "1.2.0"
0da34b6d
BG		 75
76MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77MODULE_AUTHOR("Maintainer: help@myri.com");
78MODULE_VERSION(MYRI10GE_VERSION_STR);
79MODULE_LICENSE("Dual BSD/GPL");
80
81#define MYRI10GE_MAX_ETHER_MTU 9014
82
83#define MYRI10GE_ETH_STOPPED 0
84#define MYRI10GE_ETH_STOPPING 1
85#define MYRI10GE_ETH_STARTING 2
86#define MYRI10GE_ETH_RUNNING 3
87#define MYRI10GE_ETH_OPEN_FAILED 4
88
89#define MYRI10GE_EEPROM_STRINGS_SIZE 256
90#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
91
40f6cff5 92#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 93#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
94
dd50f336
BG		 95#define MYRI10GE_ALLOC_ORDER 0
96#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
97#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
98
0da34b6d 99struct myri10ge_rx_buffer_state {
dd50f336
BG		 100 struct page *page;
101 int page_offset;
0da34b6d
BG		 102 DECLARE_PCI_UNMAP_ADDR(bus)
103 DECLARE_PCI_UNMAP_LEN(len)
104};
105
106struct myri10ge_tx_buffer_state {
107 struct sk_buff *skb;
108 int last;
109 DECLARE_PCI_UNMAP_ADDR(bus)
110 DECLARE_PCI_UNMAP_LEN(len)
111};
112
113struct myri10ge_cmd {
114 u32 data0;
115 u32 data1;
116 u32 data2;
117};
118
119struct myri10ge_rx_buf {
120 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
121 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
122 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
123 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 124 struct page *page;
125 dma_addr_t bus;
126 int page_offset;
0da34b6d 127 int cnt;
dd50f336 128 int fill_cnt;
0da34b6d
BG		 129 int alloc_fail;
130 int mask; /* number of rx slots -1 */
dd50f336 131 int watchdog_needed;
0da34b6d
BG		 132};
133
134struct myri10ge_tx_buf {
135 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
136 u8 __iomem *wc_fifo; /* w/c send fifo address */
137 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
138 char *req_bytes;
139 struct myri10ge_tx_buffer_state *info;
140 int mask; /* number of transmit slots -1 */
141 int boundary; /* boundary transmits cannot cross */
142 int req ____cacheline_aligned; /* transmit slots submitted */
143 int pkt_start; /* packets started */
144 int done ____cacheline_aligned; /* transmit slots completed */
145 int pkt_done; /* packets completed */
146};
147
148struct myri10ge_rx_done {
149 struct mcp_slot *entry;
150 dma_addr_t bus;
151 int cnt;
152 int idx;
153};
154
155struct myri10ge_priv {
156 int running; /* running? */
157 int csum_flag; /* rx_csums? */
158 struct myri10ge_tx_buf tx; /* transmit ring */
159 struct myri10ge_rx_buf rx_small;
160 struct myri10ge_rx_buf rx_big;
161 struct myri10ge_rx_done rx_done;
162 int small_bytes;
dd50f336 163 int big_bytes;
0da34b6d
BG		 164 struct net_device *dev;
165 struct net_device_stats stats;
166 u8 __iomem *sram;
167 int sram_size;
168 unsigned long board_span;
169 unsigned long iomem_base;
40f6cff5
AV		 170 __be32 __iomem *irq_claim;
171 __be32 __iomem *irq_deassert;
0da34b6d
BG		 172 char *mac_addr_string;
173 struct mcp_cmd_response *cmd;
174 dma_addr_t cmd_bus;
175 struct mcp_irq_data *fw_stats;
176 dma_addr_t fw_stats_bus;
177 struct pci_dev *pdev;
178 int msi_enabled;
40f6cff5 179 __be32 link_state;
0da34b6d
BG		 180 unsigned int rdma_tags_available;
181 int intr_coal_delay;
40f6cff5 182 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d
BG		 183 int mtrr;
184 int wake_queue;
185 int stop_queue;
186 int down_cnt;
187 wait_queue_head_t down_wq;
188 struct work_struct watchdog_work;
189 struct timer_list watchdog_timer;
190 int watchdog_tx_done;
c54772e7 191 int watchdog_tx_req;
0da34b6d
BG		 192 int watchdog_resets;
193 int tx_linearized;
194 int pause;
195 char *fw_name;
196 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
197 char fw_version[128];
9dc6f0e7
BG		 198 int fw_ver_major;
199 int fw_ver_minor;
200 int fw_ver_tiny;
201 int adopted_rx_filter_bug;
0da34b6d
BG		 202 u8 mac_addr[6]; /* eeprom mac address */
203 unsigned long serial_number;
204 int vendor_specific_offset;
85a7ea1b 205 int fw_multicast_support;
0da34b6d
BG		 206 u32 read_dma;
207 u32 write_dma;
208 u32 read_write_dma;
c58ac5ca
BG		 209 u32 link_changes;
210 u32 msg_enable;
0da34b6d
BG		 211};
212
213static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
214static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
215
216static char *myri10ge_fw_name = NULL;
217module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
218MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
219
220static int myri10ge_ecrc_enable = 1;
221module_param(myri10ge_ecrc_enable, int, S_IRUGO);
222MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
223
224static int myri10ge_max_intr_slots = 1024;
225module_param(myri10ge_max_intr_slots, int, S_IRUGO);
226MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
227
228static int myri10ge_small_bytes = -1; /* -1 == auto */
229module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
230MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
231
232static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 233module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
0da34b6d
BG		 234MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
235
236static int myri10ge_intr_coal_delay = 25;
237module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
238MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
239
240static int myri10ge_flow_control = 1;
241module_param(myri10ge_flow_control, int, S_IRUGO);
242MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
243
244static int myri10ge_deassert_wait = 1;
245module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
246MODULE_PARM_DESC(myri10ge_deassert_wait,
247 "Wait when deasserting legacy interrupts\n");
248
249static int myri10ge_force_firmware = 0;
250module_param(myri10ge_force_firmware, int, S_IRUGO);
251MODULE_PARM_DESC(myri10ge_force_firmware,
252 "Force firmware to assume aligned completions\n");
253
0da34b6d
BG		 254static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
255module_param(myri10ge_initial_mtu, int, S_IRUGO);
256MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
257
258static int myri10ge_napi_weight = 64;
259module_param(myri10ge_napi_weight, int, S_IRUGO);
260MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
261
262static int myri10ge_watchdog_timeout = 1;
263module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
264MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
265
266static int myri10ge_max_irq_loops = 1048576;
267module_param(myri10ge_max_irq_loops, int, S_IRUGO);
268MODULE_PARM_DESC(myri10ge_max_irq_loops,
269 "Set stuck legacy IRQ detection threshold\n");
270
c58ac5ca
BG		 271#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
272
273static int myri10ge_debug = -1; /* defaults above */
274module_param(myri10ge_debug, int, 0);
275MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
276
dd50f336
BG		 277static int myri10ge_fill_thresh = 256;
278module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
279MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
280
6ebc087a
BG		 281static int myri10ge_wcfifo = 1;
282module_param(myri10ge_wcfifo, int, S_IRUGO);
283MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
284
0da34b6d
BG		 285#define MYRI10GE_FW_OFFSET 1024*1024
286#define MYRI10GE_HIGHPART_TO_U32(X) \
287(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
288#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
289
290#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
291
6250223e 292static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 293{
6250223e 294 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 295}
296
0da34b6d
BG		 297static int
298myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
299 struct myri10ge_cmd *data, int atomic)
300{
301 struct mcp_cmd *buf;
302 char buf_bytes[sizeof(*buf) + 8];
303 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 304 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 305 u32 dma_low, dma_high, result, value;
306 int sleep_total = 0;
307
308 /* ensure buf is aligned to 8 bytes */
309 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
310
311 buf->data0 = htonl(data->data0);
312 buf->data1 = htonl(data->data1);
313 buf->data2 = htonl(data->data2);
314 buf->cmd = htonl(cmd);
315 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
316 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
317
318 buf->response_addr.low = htonl(dma_low);
319 buf->response_addr.high = htonl(dma_high);
40f6cff5 320 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 321 mb();
322 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
323
324 /* wait up to 15ms. Longest command is the DMA benchmark,
325 * which is capped at 5ms, but runs from a timeout handler
326 * that runs every 7.8ms. So a 15ms timeout leaves us with
327 * a 2.2ms margin
328 */
329 if (atomic) {
330 /* if atomic is set, do not sleep,
331 * and try to get the completion quickly
332 * (1ms will be enough for those commands) */
333 for (sleep_total = 0;
334 sleep_total < 1000
40f6cff5 335 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 336 sleep_total += 10)
337 udelay(10);
338 } else {
339 /* use msleep for most command */
340 for (sleep_total = 0;
341 sleep_total < 15
40f6cff5 342 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 343 sleep_total++)
344 msleep(1);
345 }
346
347 result = ntohl(response->result);
348 value = ntohl(response->data);
349 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
350 if (result == 0) {
351 data->data0 = value;
352 return 0;
85a7ea1b
BG		 353 } else if (result == MXGEFW_CMD_UNKNOWN) {
354 return -ENOSYS;
0da34b6d
BG		 355 } else {
356 dev_err(&mgp->pdev->dev,
357 "command %d failed, result = %d\n",
358 cmd, result);
359 return -ENXIO;
360 }
361 }
362
363 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
364 cmd, result);
365 return -EAGAIN;
366}
367
368/*
369 * The eeprom strings on the lanaiX have the format
370 * SN=x\0
371 * MAC=x:x:x:x:x:x\0
372 * PT:ddd mmm xx xx:xx:xx xx\0
373 * PV:ddd mmm xx xx:xx:xx xx\0
374 */
375static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
376{
377 char *ptr, *limit;
378 int i;
379
380 ptr = mgp->eeprom_strings;
381 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
382
383 while (*ptr != '\0' && ptr < limit) {
384 if (memcmp(ptr, "MAC=", 4) == 0) {
385 ptr += 4;
386 mgp->mac_addr_string = ptr;
387 for (i = 0; i < 6; i++) {
388 if ((ptr + 2) > limit)
389 goto abort;
390 mgp->mac_addr[i] =
391 simple_strtoul(ptr, &ptr, 16);
392 ptr += 1;
393 }
394 }
395 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
396 ptr += 3;
397 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
398 }
399 while (ptr < limit && *ptr++) ;
400 }
401
402 return 0;
403
404abort:
405 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
406 return -ENXIO;
407}
408
409/*
410 * Enable or disable periodic RDMAs from the host to make certain
411 * chipsets resend dropped PCIe messages
412 */
413
414static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
415{
416 char __iomem *submit;
40f6cff5 417 __be32 buf[16];
0da34b6d
BG		 418 u32 dma_low, dma_high;
419 int i;
420
421 /* clear confirmation addr */
422 mgp->cmd->data = 0;
423 mb();
424
425 /* send a rdma command to the PCIe engine, and wait for the
426 * response in the confirmation address. The firmware should
427 * write a -1 there to indicate it is alive and well
428 */
429 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
430 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
431
432 buf[0] = htonl(dma_high); /* confirm addr MSW */
433 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 434 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 435 buf[3] = htonl(dma_high); /* dummy addr MSW */
436 buf[4] = htonl(dma_low); /* dummy addr LSW */
437 buf[5] = htonl(enable); /* enable? */
438
e700f9f4 439 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 440
441 myri10ge_pio_copy(submit, &buf, sizeof(buf));
442 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
443 msleep(1);
444 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
445 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
446 (enable ? "enable" : "disable"));
447}
448
449static int
450myri10ge_validate_firmware(struct myri10ge_priv *mgp,
451 struct mcp_gen_header *hdr)
452{
453 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 454
455 /* check firmware type */
456 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
457 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
458 return -EINVAL;
459 }
460
461 /* save firmware version for ethtool */
462 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
463
9dc6f0e7
BG		 464 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
465 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 466
9dc6f0e7
BG		 467 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
468 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 469 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
470 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
471 MXGEFW_VERSION_MINOR);
472 return -EINVAL;
473 }
474 return 0;
475}
476
477static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
478{
479 unsigned crc, reread_crc;
480 const struct firmware *fw;
481 struct device *dev = &mgp->pdev->dev;
482 struct mcp_gen_header *hdr;
483 size_t hdr_offset;
484 int status;
e454358a 485 unsigned i;
0da34b6d
BG		 486
487 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
488 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
489 mgp->fw_name);
490 status = -EINVAL;
491 goto abort_with_nothing;
492 }
493
494 /* check size */
495
496 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
497 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
498 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
499 status = -EINVAL;
500 goto abort_with_fw;
501 }
502
503 /* check id */
40f6cff5 504 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 505 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
506 dev_err(dev, "Bad firmware file\n");
507 status = -EINVAL;
508 goto abort_with_fw;
509 }
510 hdr = (void *)(fw->data + hdr_offset);
511
512 status = myri10ge_validate_firmware(mgp, hdr);
513 if (status != 0)
514 goto abort_with_fw;
515
516 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 517 for (i = 0; i < fw->size; i += 256) {
518 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
519 fw->data + i,
520 min(256U, (unsigned)(fw->size - i)));
521 mb();
522 readb(mgp->sram);
b10c0668 523 }
0da34b6d
BG		 524 /* corruption checking is good for parity recovery and buggy chipset */
525 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
526 reread_crc = crc32(~0, fw->data, fw->size);
527 if (crc != reread_crc) {
528 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
529 (unsigned)fw->size, reread_crc, crc);
530 status = -EIO;
531 goto abort_with_fw;
532 }
533 *size = (u32) fw->size;
534
535abort_with_fw:
536 release_firmware(fw);
537
538abort_with_nothing:
539 return status;
540}
541
542static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
543{
544 struct mcp_gen_header *hdr;
545 struct device *dev = &mgp->pdev->dev;
546 const size_t bytes = sizeof(struct mcp_gen_header);
547 size_t hdr_offset;
548 int status;
549
550 /* find running firmware header */
551 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
552
553 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
554 dev_err(dev, "Running firmware has bad header offset (%d)\n",
555 (int)hdr_offset);
556 return -EIO;
557 }
558
559 /* copy header of running firmware from SRAM to host memory to
560 * validate firmware */
561 hdr = kmalloc(bytes, GFP_KERNEL);
562 if (hdr == NULL) {
563 dev_err(dev, "could not malloc firmware hdr\n");
564 return -ENOMEM;
565 }
566 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
567 status = myri10ge_validate_firmware(mgp, hdr);
568 kfree(hdr);
9dc6f0e7
BG		 569
570 /* check to see if adopted firmware has bug where adopting
571 * it will cause broadcasts to be filtered unless the NIC
572 * is kept in ALLMULTI mode */
573 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
574 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
575 mgp->adopted_rx_filter_bug = 1;
576 dev_warn(dev, "Adopting fw %d.%d.%d: "
577 "working around rx filter bug\n",
578 mgp->fw_ver_major, mgp->fw_ver_minor,
579 mgp->fw_ver_tiny);
580 }
0da34b6d
BG		 581 return status;
582}
583
584static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
585{
586 char __iomem *submit;
40f6cff5 587 __be32 buf[16];
0da34b6d
BG		 588 u32 dma_low, dma_high, size;
589 int status, i;
590
b10c0668 591 size = 0;
0da34b6d
BG		 592 status = myri10ge_load_hotplug_firmware(mgp, &size);
593 if (status) {
594 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
595
596 /* Do not attempt to adopt firmware if there
597 * was a bad crc */
598 if (status == -EIO)
599 return status;
600
601 status = myri10ge_adopt_running_firmware(mgp);
602 if (status != 0) {
603 dev_err(&mgp->pdev->dev,
604 "failed to adopt running firmware\n");
605 return status;
606 }
607 dev_info(&mgp->pdev->dev,
608 "Successfully adopted running firmware\n");
609 if (mgp->tx.boundary == 4096) {
610 dev_warn(&mgp->pdev->dev,
611 "Using firmware currently running on NIC"
612 ". For optimal\n");
613 dev_warn(&mgp->pdev->dev,
614 "performance consider loading optimized "
615 "firmware\n");
616 dev_warn(&mgp->pdev->dev, "via hotplug\n");
617 }
618
619 mgp->fw_name = "adopted";
620 mgp->tx.boundary = 2048;
621 return status;
622 }
623
624 /* clear confirmation addr */
625 mgp->cmd->data = 0;
626 mb();
627
628 /* send a reload command to the bootstrap MCP, and wait for the
629 * response in the confirmation address. The firmware should
630 * write a -1 there to indicate it is alive and well
631 */
632 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
633 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
634
635 buf[0] = htonl(dma_high); /* confirm addr MSW */
636 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 637 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 638
639 /* FIX: All newest firmware should un-protect the bottom of
640 * the sram before handoff. However, the very first interfaces
641 * do not. Therefore the handoff copy must skip the first 8 bytes
642 */
643 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
644 buf[4] = htonl(size - 8); /* length of code */
645 buf[5] = htonl(8); /* where to copy to */
646 buf[6] = htonl(0); /* where to jump to */
647
e700f9f4 648 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 649
650 myri10ge_pio_copy(submit, &buf, sizeof(buf));
651 mb();
652 msleep(1);
653 mb();
654 i = 0;
655 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
656 msleep(1);
657 i++;
658 }
659 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
660 dev_err(&mgp->pdev->dev, "handoff failed\n");
661 return -ENXIO;
662 }
663 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
9a71db72 664 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 665
666 return 0;
667}
668
669static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
670{
671 struct myri10ge_cmd cmd;
672 int status;
673
674 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
675 | (addr[2] << 8) | addr[3]);
676
677 cmd.data1 = ((addr[4] << 8) | (addr[5]));
678
679 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
680 return status;
681}
682
683static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
684{
685 struct myri10ge_cmd cmd;
686 int status, ctl;
687
688 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
689 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
690
691 if (status) {
692 printk(KERN_ERR
693 "myri10ge: %s: Failed to set flow control mode\n",
694 mgp->dev->name);
695 return status;
696 }
697 mgp->pause = pause;
698 return 0;
699}
700
701static void
702myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
703{
704 struct myri10ge_cmd cmd;
705 int status, ctl;
706
707 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
708 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
709 if (status)
710 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
711 mgp->dev->name);
712}
713
714static int myri10ge_reset(struct myri10ge_priv *mgp)
715{
716 struct myri10ge_cmd cmd;
717 int status;
718 size_t bytes;
719 u32 len;
34fdccea
BG		 720 struct page *dmatest_page;
721 dma_addr_t dmatest_bus;
0da34b6d
BG		 722
723 /* try to send a reset command to the card to see if it
724 * is alive */
725 memset(&cmd, 0, sizeof(cmd));
726 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
727 if (status != 0) {
728 dev_err(&mgp->pdev->dev, "failed reset\n");
729 return -ENXIO;
730 }
34fdccea
BG		 731 dmatest_page = alloc_page(GFP_KERNEL);
732 if (!dmatest_page)
733 return -ENOMEM;
734 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
735 DMA_BIDIRECTIONAL);
0da34b6d
BG		 736
737 /* Now exchange information about interrupts */
738
739 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
740 memset(mgp->rx_done.entry, 0, bytes);
741 cmd.data0 = (u32) bytes;
742 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
743 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
744 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
745 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
746
747 status |=
748 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
40f6cff5 749 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
df30a740
BG		 750 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
751 &cmd, 0);
752 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 753
0da34b6d
BG		 754 status |= myri10ge_send_cmd
755 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 756 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 757 if (status != 0) {
758 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
759 return status;
760 }
40f6cff5 761 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 762
763 /* Run a small DMA test.
764 * The magic multipliers to the length tell the firmware
765 * to do DMA read, write, or read+write tests. The
766 * results are returned in cmd.data0. The upper 16
767 * bits or the return is the number of transfers completed.
768 * The lower 16 bits is the time in 0.5us ticks that the
769 * transfers took to complete.
770 */
771
772 len = mgp->tx.boundary;
773
34fdccea
BG		 774 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
775 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
0da34b6d
BG		 776 cmd.data2 = len * 0x10000;
777 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
778 if (status == 0)
779 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) /
780 (cmd.data0 & 0xffff);
781 else
782 dev_warn(&mgp->pdev->dev, "DMA read benchmark failed: %d\n",
783 status);
34fdccea
BG		 784 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
785 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
0da34b6d
BG		 786 cmd.data2 = len * 0x1;
787 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
788 if (status == 0)
789 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) /
790 (cmd.data0 & 0xffff);
791 else
792 dev_warn(&mgp->pdev->dev, "DMA write benchmark failed: %d\n",
793 status);
794
34fdccea
BG		 795 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
796 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
0da34b6d
BG		 797 cmd.data2 = len * 0x10001;
798 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
799 if (status == 0)
800 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
801 (cmd.data0 & 0xffff);
802 else
803 dev_warn(&mgp->pdev->dev,
804 "DMA read/write benchmark failed: %d\n", status);
805
34fdccea
BG		 806 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
807 put_page(dmatest_page);
808
0da34b6d
BG		 809 memset(mgp->rx_done.entry, 0, bytes);
810
811 /* reset mcp/driver shared state back to 0 */
812 mgp->tx.req = 0;
813 mgp->tx.done = 0;
814 mgp->tx.pkt_start = 0;
815 mgp->tx.pkt_done = 0;
816 mgp->rx_big.cnt = 0;
817 mgp->rx_small.cnt = 0;
818 mgp->rx_done.idx = 0;
819 mgp->rx_done.cnt = 0;
c58ac5ca 820 mgp->link_changes = 0;
0da34b6d
BG		 821 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
822 myri10ge_change_promisc(mgp, 0, 0);
823 myri10ge_change_pause(mgp, mgp->pause);
9dc6f0e7
BG		 824 if (mgp->adopted_rx_filter_bug)
825 (void)myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
0da34b6d
BG		 826 return status;
827}
828
829static inline void
830myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
831 struct mcp_kreq_ether_recv *src)
832{
40f6cff5 833 __be32 low;
0da34b6d
BG		 834
835 low = src->addr_low;
40f6cff5 836 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 837 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
838 mb();
839 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 840 mb();
841 src->addr_low = low;
40f6cff5 842 put_be32(low, &dst->addr_low);
0da34b6d
BG		 843 mb();
844}
845
40f6cff5 846static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 847{
848 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
849
40f6cff5 850 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 851 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
852 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
853 skb->csum = hw_csum;
84fa7933 854 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 855 }
856}
857
dd50f336
BG		 858static inline void
859myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
860 struct skb_frag_struct *rx_frags, int len, int hlen)
861{
862 struct skb_frag_struct *skb_frags;
863
864 skb->len = skb->data_len = len;
865 skb->truesize = len + sizeof(struct sk_buff);
866 /* attach the page(s) */
867
868 skb_frags = skb_shinfo(skb)->frags;
869 while (len > 0) {
870 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
871 len -= rx_frags->size;
872 skb_frags++;
873 rx_frags++;
874 skb_shinfo(skb)->nr_frags++;
875 }
876
877 /* pskb_may_pull is not available in irq context, but
878 * skb_pull() (for ether_pad and eth_type_trans()) requires
879 * the beginning of the packet in skb_headlen(), move it
880 * manually */
881 memcpy(skb->data, va, hlen);
882 skb_shinfo(skb)->frags[0].page_offset += hlen;
883 skb_shinfo(skb)->frags[0].size -= hlen;
884 skb->data_len -= hlen;
885 skb->tail += hlen;
886 skb_pull(skb, MXGEFW_PAD);
887}
888
889static void
890myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
891 int bytes, int watchdog)
892{
893 struct page *page;
894 int idx;
895
896 if (unlikely(rx->watchdog_needed && !watchdog))
897 return;
898
899 /* try to refill entire ring */
900 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
901 idx = rx->fill_cnt & rx->mask;
902
903 if ((bytes < MYRI10GE_ALLOC_SIZE / 2) &&
904 (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE)) {
905 /* we can use part of previous page */
906 get_page(rx->page);
907 } else {
908 /* we need a new page */
909 page =
910 alloc_pages(GFP_ATOMIC | __GFP_COMP,
911 MYRI10GE_ALLOC_ORDER);
912 if (unlikely(page == NULL)) {
913 if (rx->fill_cnt - rx->cnt < 16)
914 rx->watchdog_needed = 1;
915 return;
916 }
917 rx->page = page;
918 rx->page_offset = 0;
919 rx->bus = pci_map_page(mgp->pdev, page, 0,
920 MYRI10GE_ALLOC_SIZE,
921 PCI_DMA_FROMDEVICE);
922 }
923 rx->info[idx].page = rx->page;
924 rx->info[idx].page_offset = rx->page_offset;
925 /* note that this is the address of the start of the
926 * page */
927 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
928 rx->shadow[idx].addr_low =
929 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
930 rx->shadow[idx].addr_high =
931 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
932
933 /* start next packet on a cacheline boundary */
934 rx->page_offset += SKB_DATA_ALIGN(bytes);
935 rx->fill_cnt++;
936
937 /* copy 8 descriptors to the firmware at a time */
938 if ((idx & 7) == 7) {
939 if (rx->wc_fifo == NULL)
940 myri10ge_submit_8rx(&rx->lanai[idx - 7],
941 &rx->shadow[idx - 7]);
942 else {
943 mb();
944 myri10ge_pio_copy(rx->wc_fifo,
945 &rx->shadow[idx - 7], 64);
946 }
947 }
948 }
949}
950
951static inline void
952myri10ge_unmap_rx_page(struct pci_dev *pdev,
953 struct myri10ge_rx_buffer_state *info, int bytes)
954{
955 /* unmap the recvd page if we're the only or last user of it */
956 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
957 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
958 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
959 & ~(MYRI10GE_ALLOC_SIZE - 1)),
960 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
961 }
962}
963
964#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
965 * page into an skb */
966
967static inline int
52ea6fb3
BG		 968myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
969 int bytes, int len, __wsum csum)
dd50f336
BG		 970{
971 struct sk_buff *skb;
972 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
973 int i, idx, hlen, remainder;
974 struct pci_dev *pdev = mgp->pdev;
975 struct net_device *dev = mgp->dev;
976 u8 *va;
977
978 len += MXGEFW_PAD;
979 idx = rx->cnt & rx->mask;
980 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
981 prefetch(va);
982 /* Fill skb_frag_struct(s) with data from our receive */
983 for (i = 0, remainder = len; remainder > 0; i++) {
984 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
985 rx_frags[i].page = rx->info[idx].page;
986 rx_frags[i].page_offset = rx->info[idx].page_offset;
987 if (remainder < MYRI10GE_ALLOC_SIZE)
988 rx_frags[i].size = remainder;
989 else
990 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
991 rx->cnt++;
992 idx = rx->cnt & rx->mask;
993 remainder -= MYRI10GE_ALLOC_SIZE;
994 }
995
996 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
997
998 /* allocate an skb to attach the page(s) to. */
999
1000 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1001 if (unlikely(skb == NULL)) {
1002 mgp->stats.rx_dropped++;
1003 do {
1004 i--;
1005 put_page(rx_frags[i].page);
1006 } while (i != 0);
1007 return 0;
1008 }
1009
1010 /* Attach the pages to the skb, and trim off any padding */
1011 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1012 if (skb_shinfo(skb)->frags[0].size <= 0) {
1013 put_page(skb_shinfo(skb)->frags[0].page);
1014 skb_shinfo(skb)->nr_frags = 0;
1015 }
1016 skb->protocol = eth_type_trans(skb, dev);
1017 skb->dev = dev;
1018
1019 if (mgp->csum_flag) {
1020 if ((skb->protocol == htons(ETH_P_IP)) ||
1021 (skb->protocol == htons(ETH_P_IPV6))) {
1022 skb->csum = csum;
1023 skb->ip_summed = CHECKSUM_COMPLETE;
1024 } else
1025 myri10ge_vlan_ip_csum(skb, csum);
1026 }
1027 netif_receive_skb(skb);
1028 dev->last_rx = jiffies;
1029 return 1;
1030}
1031
0da34b6d
BG		 1032static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1033{
1034 struct pci_dev *pdev = mgp->pdev;
1035 struct myri10ge_tx_buf *tx = &mgp->tx;
1036 struct sk_buff *skb;
1037 int idx, len;
1038 int limit = 0;
1039
1040 while (tx->pkt_done != mcp_index) {
1041 idx = tx->done & tx->mask;
1042 skb = tx->info[idx].skb;
1043
1044 /* Mark as free */
1045 tx->info[idx].skb = NULL;
1046 if (tx->info[idx].last) {
1047 tx->pkt_done++;
1048 tx->info[idx].last = 0;
1049 }
1050 tx->done++;
1051 len = pci_unmap_len(&tx->info[idx], len);
1052 pci_unmap_len_set(&tx->info[idx], len, 0);
1053 if (skb) {
1054 mgp->stats.tx_bytes += skb->len;
1055 mgp->stats.tx_packets++;
1056 dev_kfree_skb_irq(skb);
1057 if (len)
1058 pci_unmap_single(pdev,
1059 pci_unmap_addr(&tx->info[idx],
1060 bus), len,
1061 PCI_DMA_TODEVICE);
1062 } else {
1063 if (len)
1064 pci_unmap_page(pdev,
1065 pci_unmap_addr(&tx->info[idx],
1066 bus), len,
1067 PCI_DMA_TODEVICE);
1068 }
1069
1070 /* limit potential for livelock by only handling
1071 * 2 full tx rings per call */
1072 if (unlikely(++limit > 2 * tx->mask))
1073 break;
1074 }
1075 /* start the queue if we've stopped it */
1076 if (netif_queue_stopped(mgp->dev)
1077 && tx->req - tx->done < (tx->mask >> 1)) {
1078 mgp->wake_queue++;
1079 netif_wake_queue(mgp->dev);
1080 }
1081}
1082
1083static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1084{
1085 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1086 unsigned long rx_bytes = 0;
1087 unsigned long rx_packets = 0;
1088 unsigned long rx_ok;
1089
1090 int idx = rx_done->idx;
1091 int cnt = rx_done->cnt;
1092 u16 length;
40f6cff5 1093 __wsum checksum;
0da34b6d
BG		 1094
1095 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1096 length = ntohs(rx_done->entry[idx].length);
1097 rx_done->entry[idx].length = 0;
40f6cff5 1098 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1099 if (length <= mgp->small_bytes)
52ea6fb3
BG		 1100 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1101 mgp->small_bytes,
1102 length, checksum);
0da34b6d 1103 else
52ea6fb3
BG		 1104 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1105 mgp->big_bytes,
1106 length, checksum);
0da34b6d
BG		 1107 rx_packets += rx_ok;
1108 rx_bytes += rx_ok * (unsigned long)length;
1109 cnt++;
1110 idx = cnt & (myri10ge_max_intr_slots - 1);
1111
1112 /* limit potential for livelock by only handling a
1113 * limited number of frames. */
1114 (*limit)--;
1115 }
1116 rx_done->idx = idx;
1117 rx_done->cnt = cnt;
1118 mgp->stats.rx_packets += rx_packets;
1119 mgp->stats.rx_bytes += rx_bytes;
c7dab99b
BG		 1120
1121 /* restock receive rings if needed */
1122 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1123 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1124 mgp->small_bytes + MXGEFW_PAD, 0);
1125 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1126 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1127
0da34b6d
BG		 1128}
1129
1130static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1131{
1132 struct mcp_irq_data *stats = mgp->fw_stats;
1133
1134 if (unlikely(stats->stats_updated)) {
1135 if (mgp->link_state != stats->link_up) {
1136 mgp->link_state = stats->link_up;
1137 if (mgp->link_state) {
c58ac5ca
BG		 1138 if (netif_msg_link(mgp))
1139 printk(KERN_INFO
1140 "myri10ge: %s: link up\n",
1141 mgp->dev->name);
0da34b6d 1142 netif_carrier_on(mgp->dev);
c58ac5ca 1143 mgp->link_changes++;
0da34b6d 1144 } else {
c58ac5ca
BG		 1145 if (netif_msg_link(mgp))
1146 printk(KERN_INFO
1147 "myri10ge: %s: link down\n",
1148 mgp->dev->name);
0da34b6d 1149 netif_carrier_off(mgp->dev);
c58ac5ca 1150 mgp->link_changes++;
0da34b6d
BG		 1151 }
1152 }
1153 if (mgp->rdma_tags_available !=
1154 ntohl(mgp->fw_stats->rdma_tags_available)) {
1155 mgp->rdma_tags_available =
1156 ntohl(mgp->fw_stats->rdma_tags_available);
1157 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1158 "%d tags left\n", mgp->dev->name,
1159 mgp->rdma_tags_available);
1160 }
1161 mgp->down_cnt += stats->link_down;
1162 if (stats->link_down)
1163 wake_up(&mgp->down_wq);
1164 }
1165}
1166
1167static int myri10ge_poll(struct net_device *netdev, int *budget)
1168{
1169 struct myri10ge_priv *mgp = netdev_priv(netdev);
1170 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1171 int limit, orig_limit, work_done;
1172
1173 /* process as many rx events as NAPI will allow */
1174 limit = min(*budget, netdev->quota);
1175 orig_limit = limit;
1176 myri10ge_clean_rx_done(mgp, &limit);
1177 work_done = orig_limit - limit;
1178 *budget -= work_done;
1179 netdev->quota -= work_done;
1180
1181 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1182 netif_rx_complete(netdev);
40f6cff5 1183 put_be32(htonl(3), mgp->irq_claim);
0da34b6d
BG		 1184 return 0;
1185 }
1186 return 1;
1187}
1188
7d12e780 1189static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d
BG		 1190{
1191 struct myri10ge_priv *mgp = arg;
1192 struct mcp_irq_data *stats = mgp->fw_stats;
1193 struct myri10ge_tx_buf *tx = &mgp->tx;
1194 u32 send_done_count;
1195 int i;
1196
1197 /* make sure it is our IRQ, and that the DMA has finished */
1198 if (unlikely(!stats->valid))
1199 return (IRQ_NONE);
1200
1201 /* low bit indicates receives are present, so schedule
1202 * napi poll handler */
1203 if (stats->valid & 1)
1204 netif_rx_schedule(mgp->dev);
1205
1206 if (!mgp->msi_enabled) {
40f6cff5 1207 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1208 if (!myri10ge_deassert_wait)
1209 stats->valid = 0;
1210 mb();
1211 } else
1212 stats->valid = 0;
1213
1214 /* Wait for IRQ line to go low, if using INTx */
1215 i = 0;
1216 while (1) {
1217 i++;
1218 /* check for transmit completes and receives */
1219 send_done_count = ntohl(stats->send_done_count);
1220 if (send_done_count != tx->pkt_done)
1221 myri10ge_tx_done(mgp, (int)send_done_count);
1222 if (unlikely(i > myri10ge_max_irq_loops)) {
1223 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1224 mgp->dev->name);
1225 stats->valid = 0;
1226 schedule_work(&mgp->watchdog_work);
1227 }
1228 if (likely(stats->valid == 0))
1229 break;
1230 cpu_relax();
1231 barrier();
1232 }
1233
1234 myri10ge_check_statblock(mgp);
1235
40f6cff5 1236 put_be32(htonl(3), mgp->irq_claim + 1);
0da34b6d
BG		 1237 return (IRQ_HANDLED);
1238}
1239
1240static int
1241myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1242{
1243 cmd->autoneg = AUTONEG_DISABLE;
1244 cmd->speed = SPEED_10000;
1245 cmd->duplex = DUPLEX_FULL;
1246 return 0;
1247}
1248
1249static void
1250myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1251{
1252 struct myri10ge_priv *mgp = netdev_priv(netdev);
1253
1254 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1255 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1256 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1257 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1258}
1259
1260static int
1261myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1262{
1263 struct myri10ge_priv *mgp = netdev_priv(netdev);
1264 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1265 return 0;
1266}
1267
1268static int
1269myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1270{
1271 struct myri10ge_priv *mgp = netdev_priv(netdev);
1272
1273 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1274 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1275 return 0;
1276}
1277
1278static void
1279myri10ge_get_pauseparam(struct net_device *netdev,
1280 struct ethtool_pauseparam *pause)
1281{
1282 struct myri10ge_priv *mgp = netdev_priv(netdev);
1283
1284 pause->autoneg = 0;
1285 pause->rx_pause = mgp->pause;
1286 pause->tx_pause = mgp->pause;
1287}
1288
1289static int
1290myri10ge_set_pauseparam(struct net_device *netdev,
1291 struct ethtool_pauseparam *pause)
1292{
1293 struct myri10ge_priv *mgp = netdev_priv(netdev);
1294
1295 if (pause->tx_pause != mgp->pause)
1296 return myri10ge_change_pause(mgp, pause->tx_pause);
1297 if (pause->rx_pause != mgp->pause)
1298 return myri10ge_change_pause(mgp, pause->tx_pause);
1299 if (pause->autoneg != 0)
1300 return -EINVAL;
1301 return 0;
1302}
1303
1304static void
1305myri10ge_get_ringparam(struct net_device *netdev,
1306 struct ethtool_ringparam *ring)
1307{
1308 struct myri10ge_priv *mgp = netdev_priv(netdev);
1309
1310 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1311 ring->rx_max_pending = mgp->rx_big.mask + 1;
1312 ring->rx_jumbo_max_pending = 0;
1313 ring->tx_max_pending = mgp->rx_small.mask + 1;
1314 ring->rx_mini_pending = ring->rx_mini_max_pending;
1315 ring->rx_pending = ring->rx_max_pending;
1316 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1317 ring->tx_pending = ring->tx_max_pending;
1318}
1319
1320static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1321{
1322 struct myri10ge_priv *mgp = netdev_priv(netdev);
1323 if (mgp->csum_flag)
1324 return 1;
1325 else
1326 return 0;
1327}
1328
1329static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1330{
1331 struct myri10ge_priv *mgp = netdev_priv(netdev);
1332 if (csum_enabled)
1333 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1334 else
1335 mgp->csum_flag = 0;
1336 return 0;
1337}
1338
1339static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1340 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1341 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1342 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1343 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1344 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1345 "tx_heartbeat_errors", "tx_window_errors",
1346 /* device-specific stats */
2c1a1088 1347 "tx_boundary", "WC", "irq", "MSI",
0da34b6d
BG		 1348 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1349 "serial_number", "tx_pkt_start", "tx_pkt_done",
1350 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1351 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
c58ac5ca 1352 "link_changes", "link_up", "dropped_link_overflow",
85a7ea1b 1353 "dropped_link_error_or_filtered", "dropped_multicast_filtered",
0da34b6d
BG		 1354 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1355 "dropped_no_big_buffer"
1356};
1357
1358#define MYRI10GE_NET_STATS_LEN 21
1359#define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1360
1361static void
1362myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1363{
1364 switch (stringset) {
1365 case ETH_SS_STATS:
1366 memcpy(data, *myri10ge_gstrings_stats,
1367 sizeof(myri10ge_gstrings_stats));
1368 break;
1369 }
1370}
1371
1372static int myri10ge_get_stats_count(struct net_device *netdev)
1373{
1374 return MYRI10GE_STATS_LEN;
1375}
1376
1377static void
1378myri10ge_get_ethtool_stats(struct net_device *netdev,
1379 struct ethtool_stats *stats, u64 * data)
1380{
1381 struct myri10ge_priv *mgp = netdev_priv(netdev);
1382 int i;
1383
1384 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1385 data[i] = ((unsigned long *)&mgp->stats)[i];
1386
2c1a1088
BG		 1387 data[i++] = (unsigned int)mgp->tx.boundary;
1388 data[i++] = (unsigned int)(mgp->mtrr >= 0);
1389 data[i++] = (unsigned int)mgp->pdev->irq;
1390 data[i++] = (unsigned int)mgp->msi_enabled;
0da34b6d
BG		 1391 data[i++] = (unsigned int)mgp->read_dma;
1392 data[i++] = (unsigned int)mgp->write_dma;
1393 data[i++] = (unsigned int)mgp->read_write_dma;
1394 data[i++] = (unsigned int)mgp->serial_number;
1395 data[i++] = (unsigned int)mgp->tx.pkt_start;
1396 data[i++] = (unsigned int)mgp->tx.pkt_done;
1397 data[i++] = (unsigned int)mgp->tx.req;
1398 data[i++] = (unsigned int)mgp->tx.done;
1399 data[i++] = (unsigned int)mgp->rx_small.cnt;
1400 data[i++] = (unsigned int)mgp->rx_big.cnt;
1401 data[i++] = (unsigned int)mgp->wake_queue;
1402 data[i++] = (unsigned int)mgp->stop_queue;
1403 data[i++] = (unsigned int)mgp->watchdog_resets;
1404 data[i++] = (unsigned int)mgp->tx_linearized;
c58ac5ca 1405 data[i++] = (unsigned int)mgp->link_changes;
0da34b6d
BG		 1406 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1407 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1408 data[i++] =
1409 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
85a7ea1b
BG		 1410 data[i++] =
1411 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
0da34b6d
BG		 1412 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1413 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1414 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1415 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1416}
1417
c58ac5ca
BG		 1418static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1419{
1420 struct myri10ge_priv *mgp = netdev_priv(netdev);
1421 mgp->msg_enable = value;
1422}
1423
1424static u32 myri10ge_get_msglevel(struct net_device *netdev)
1425{
1426 struct myri10ge_priv *mgp = netdev_priv(netdev);
1427 return mgp->msg_enable;
1428}
1429
7282d491 1430static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1431 .get_settings = myri10ge_get_settings,
1432 .get_drvinfo = myri10ge_get_drvinfo,
1433 .get_coalesce = myri10ge_get_coalesce,
1434 .set_coalesce = myri10ge_set_coalesce,
1435 .get_pauseparam = myri10ge_get_pauseparam,
1436 .set_pauseparam = myri10ge_set_pauseparam,
1437 .get_ringparam = myri10ge_get_ringparam,
1438 .get_rx_csum = myri10ge_get_rx_csum,
1439 .set_rx_csum = myri10ge_set_rx_csum,
1440 .get_tx_csum = ethtool_op_get_tx_csum,
b10c0668 1441 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d
BG		 1442 .get_sg = ethtool_op_get_sg,
1443 .set_sg = ethtool_op_set_sg,
0da34b6d
BG		 1444 .get_tso = ethtool_op_get_tso,
1445 .set_tso = ethtool_op_set_tso,
0da34b6d
BG		 1446 .get_strings = myri10ge_get_strings,
1447 .get_stats_count = myri10ge_get_stats_count,
c58ac5ca
BG		 1448 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1449 .set_msglevel = myri10ge_set_msglevel,
1450 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1451};
1452
1453static int myri10ge_allocate_rings(struct net_device *dev)
1454{
1455 struct myri10ge_priv *mgp;
1456 struct myri10ge_cmd cmd;
1457 int tx_ring_size, rx_ring_size;
1458 int tx_ring_entries, rx_ring_entries;
1459 int i, status;
1460 size_t bytes;
1461
1462 mgp = netdev_priv(dev);
1463
1464 /* get ring sizes */
1465
1466 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1467 tx_ring_size = cmd.data0;
1468 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1469 if (status != 0)
1470 return status;
0da34b6d
BG		 1471 rx_ring_size = cmd.data0;
1472
1473 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1474 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1475 mgp->tx.mask = tx_ring_entries - 1;
1476 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1477
355c7265
BG		 1478 status = -ENOMEM;
1479
0da34b6d
BG		 1480 /* allocate the host shadow rings */
1481
1482 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1483 * sizeof(*mgp->tx.req_list);
1484 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1485 if (mgp->tx.req_bytes == NULL)
1486 goto abort_with_nothing;
1487
1488 /* ensure req_list entries are aligned to 8 bytes */
1489 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1490 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1491
1492 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1493 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1494 if (mgp->rx_small.shadow == NULL)
1495 goto abort_with_tx_req_bytes;
1496
1497 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1498 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1499 if (mgp->rx_big.shadow == NULL)
1500 goto abort_with_rx_small_shadow;
1501
1502 /* allocate the host info rings */
1503
1504 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1505 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1506 if (mgp->tx.info == NULL)
1507 goto abort_with_rx_big_shadow;
1508
1509 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1510 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1511 if (mgp->rx_small.info == NULL)
1512 goto abort_with_tx_info;
1513
1514 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1515 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1516 if (mgp->rx_big.info == NULL)
1517 goto abort_with_rx_small_info;
1518
1519 /* Fill the receive rings */
c7dab99b
BG		 1520 mgp->rx_big.cnt = 0;
1521 mgp->rx_small.cnt = 0;
1522 mgp->rx_big.fill_cnt = 0;
1523 mgp->rx_small.fill_cnt = 0;
1524 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1525 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1526 mgp->rx_small.watchdog_needed = 0;
1527 mgp->rx_big.watchdog_needed = 0;
1528 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1529 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1530
c7dab99b
BG		 1531 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1532 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1533 dev->name, mgp->rx_small.fill_cnt);
1534 goto abort_with_rx_small_ring;
0da34b6d
BG		 1535 }
1536
c7dab99b
BG		 1537 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1538 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1539 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1540 dev->name, mgp->rx_big.fill_cnt);
1541 goto abort_with_rx_big_ring;
0da34b6d
BG		 1542 }
1543
1544 return 0;
1545
1546abort_with_rx_big_ring:
c7dab99b
BG		 1547 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1548 int idx = i & mgp->rx_big.mask;
1549 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1550 mgp->big_bytes);
1551 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1552 }
1553
1554abort_with_rx_small_ring:
c7dab99b
BG		 1555 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1556 int idx = i & mgp->rx_small.mask;
1557 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1558 mgp->small_bytes + MXGEFW_PAD);
1559 put_page(mgp->rx_small.info[idx].page);
0da34b6d 1560 }
c7dab99b 1561
0da34b6d
BG		 1562 kfree(mgp->rx_big.info);
1563
1564abort_with_rx_small_info:
1565 kfree(mgp->rx_small.info);
1566
1567abort_with_tx_info:
1568 kfree(mgp->tx.info);
1569
1570abort_with_rx_big_shadow:
1571 kfree(mgp->rx_big.shadow);
1572
1573abort_with_rx_small_shadow:
1574 kfree(mgp->rx_small.shadow);
1575
1576abort_with_tx_req_bytes:
1577 kfree(mgp->tx.req_bytes);
1578 mgp->tx.req_bytes = NULL;
1579 mgp->tx.req_list = NULL;
1580
1581abort_with_nothing:
1582 return status;
1583}
1584
1585static void myri10ge_free_rings(struct net_device *dev)
1586{
1587 struct myri10ge_priv *mgp;
1588 struct sk_buff *skb;
1589 struct myri10ge_tx_buf *tx;
1590 int i, len, idx;
1591
1592 mgp = netdev_priv(dev);
1593
c7dab99b
BG		 1594 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1595 idx = i & mgp->rx_big.mask;
1596 if (i == mgp->rx_big.fill_cnt - 1)
1597 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1598 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1599 mgp->big_bytes);
1600 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1601 }
1602
c7dab99b
BG		 1603 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1604 idx = i & mgp->rx_small.mask;
1605 if (i == mgp->rx_small.fill_cnt - 1)
1606 mgp->rx_small.info[idx].page_offset =
1607 MYRI10GE_ALLOC_SIZE;
1608 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1609 mgp->small_bytes + MXGEFW_PAD);
1610 put_page(mgp->rx_small.info[idx].page);
1611 }
0da34b6d
BG		 1612 tx = &mgp->tx;
1613 while (tx->done != tx->req) {
1614 idx = tx->done & tx->mask;
1615 skb = tx->info[idx].skb;
1616
1617 /* Mark as free */
1618 tx->info[idx].skb = NULL;
1619 tx->done++;
1620 len = pci_unmap_len(&tx->info[idx], len);
1621 pci_unmap_len_set(&tx->info[idx], len, 0);
1622 if (skb) {
1623 mgp->stats.tx_dropped++;
1624 dev_kfree_skb_any(skb);
1625 if (len)
1626 pci_unmap_single(mgp->pdev,
1627 pci_unmap_addr(&tx->info[idx],
1628 bus), len,
1629 PCI_DMA_TODEVICE);
1630 } else {
1631 if (len)
1632 pci_unmap_page(mgp->pdev,
1633 pci_unmap_addr(&tx->info[idx],
1634 bus), len,
1635 PCI_DMA_TODEVICE);
1636 }
1637 }
1638 kfree(mgp->rx_big.info);
1639
1640 kfree(mgp->rx_small.info);
1641
1642 kfree(mgp->tx.info);
1643
1644 kfree(mgp->rx_big.shadow);
1645
1646 kfree(mgp->rx_small.shadow);
1647
1648 kfree(mgp->tx.req_bytes);
1649 mgp->tx.req_bytes = NULL;
1650 mgp->tx.req_list = NULL;
1651}
1652
df30a740
BG		 1653static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1654{
1655 struct pci_dev *pdev = mgp->pdev;
1656 int status;
1657
1658 if (myri10ge_msi) {
1659 status = pci_enable_msi(pdev);
1660 if (status != 0)
1661 dev_err(&pdev->dev,
1662 "Error %d setting up MSI; falling back to xPIC\n",
1663 status);
1664 else
1665 mgp->msi_enabled = 1;
1666 } else {
1667 mgp->msi_enabled = 0;
1668 }
1669 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1670 mgp->dev->name, mgp);
1671 if (status != 0) {
1672 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1673 if (mgp->msi_enabled)
1674 pci_disable_msi(pdev);
1675 }
1676 return status;
1677}
1678
1679static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1680{
1681 struct pci_dev *pdev = mgp->pdev;
1682
1683 free_irq(pdev->irq, mgp);
1684 if (mgp->msi_enabled)
1685 pci_disable_msi(pdev);
1686}
1687
0da34b6d
BG		 1688static int myri10ge_open(struct net_device *dev)
1689{
1690 struct myri10ge_priv *mgp;
1691 struct myri10ge_cmd cmd;
1692 int status, big_pow2;
1693
1694 mgp = netdev_priv(dev);
1695
1696 if (mgp->running != MYRI10GE_ETH_STOPPED)
1697 return -EBUSY;
1698
1699 mgp->running = MYRI10GE_ETH_STARTING;
1700 status = myri10ge_reset(mgp);
1701 if (status != 0) {
1702 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 1703 goto abort_with_nothing;
0da34b6d
BG		 1704 }
1705
df30a740
BG		 1706 status = myri10ge_request_irq(mgp);
1707 if (status != 0)
1708 goto abort_with_nothing;
1709
0da34b6d
BG		 1710 /* decide what small buffer size to use. For good TCP rx
1711 * performance, it is important to not receive 1514 byte
1712 * frames into jumbo buffers, as it confuses the socket buffer
1713 * accounting code, leading to drops and erratic performance.
1714 */
1715
1716 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 1717 /* enough for a TCP header */
1718 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1719 ? (128 - MXGEFW_PAD)
1720 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 1721 else
de3c4507
BG		 1722 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1723 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 1724
1725 /* Override the small buffer size? */
1726 if (myri10ge_small_bytes > 0)
1727 mgp->small_bytes = myri10ge_small_bytes;
1728
0da34b6d
BG		 1729 /* get the lanai pointers to the send and receive rings */
1730
1731 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1732 mgp->tx.lanai =
1733 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1734
1735 status |=
1736 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1737 mgp->rx_small.lanai =
1738 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1739
1740 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1741 mgp->rx_big.lanai =
1742 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1743
1744 if (status != 0) {
1745 printk(KERN_ERR
1746 "myri10ge: %s: failed to get ring sizes or locations\n",
1747 dev->name);
1748 mgp->running = MYRI10GE_ETH_STOPPED;
df30a740 1749 goto abort_with_irq;
0da34b6d
BG		 1750 }
1751
6ebc087a 1752 if (myri10ge_wcfifo && mgp->mtrr >= 0) {
e700f9f4
BG		 1753 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1754 mgp->rx_small.wc_fifo =
1755 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1756 mgp->rx_big.wc_fifo =
1757 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
0da34b6d
BG		 1758 } else {
1759 mgp->tx.wc_fifo = NULL;
1760 mgp->rx_small.wc_fifo = NULL;
1761 mgp->rx_big.wc_fifo = NULL;
1762 }
1763
0da34b6d
BG		 1764 /* Firmware needs the big buff size as a power of 2. Lie and
1765 * tell him the buffer is larger, because we only use 1
1766 * buffer/pkt, and the mtu will prevent overruns.
1767 */
13348bee 1768 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1769 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
1770 while ((big_pow2 & (big_pow2 - 1)) != 0)
1771 big_pow2++;
13348bee 1772 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1773 } else {
1774 big_pow2 = MYRI10GE_ALLOC_SIZE;
1775 mgp->big_bytes = big_pow2;
1776 }
1777
1778 status = myri10ge_allocate_rings(dev);
1779 if (status != 0)
df30a740 1780 goto abort_with_irq;
0da34b6d
BG		 1781
1782 /* now give firmware buffers sizes, and MTU */
1783 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1784 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1785 cmd.data0 = mgp->small_bytes;
1786 status |=
1787 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1788 cmd.data0 = big_pow2;
1789 status |=
1790 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1791 if (status) {
1792 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1793 dev->name);
1794 goto abort_with_rings;
1795 }
1796
1797 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1798 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
85a7ea1b
BG		 1799 cmd.data2 = sizeof(struct mcp_irq_data);
1800 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1801 if (status == -ENOSYS) {
1802 dma_addr_t bus = mgp->fw_stats_bus;
1803 bus += offsetof(struct mcp_irq_data, send_done_count);
1804 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1805 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1806 status = myri10ge_send_cmd(mgp,
1807 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1808 &cmd, 0);
1809 /* Firmware cannot support multicast without STATS_DMA_V2 */
1810 mgp->fw_multicast_support = 0;
1811 } else {
1812 mgp->fw_multicast_support = 1;
1813 }
0da34b6d
BG		 1814 if (status) {
1815 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1816 dev->name);
1817 goto abort_with_rings;
1818 }
1819
40f6cff5 1820 mgp->link_state = htonl(~0U);
0da34b6d
BG		 1821 mgp->rdma_tags_available = 15;
1822
1823 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1824
1825 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1826 if (status) {
1827 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1828 dev->name);
1829 goto abort_with_rings;
1830 }
1831
1832 mgp->wake_queue = 0;
1833 mgp->stop_queue = 0;
1834 mgp->running = MYRI10GE_ETH_RUNNING;
1835 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1836 add_timer(&mgp->watchdog_timer);
1837 netif_wake_queue(dev);
1838 return 0;
1839
1840abort_with_rings:
1841 myri10ge_free_rings(dev);
1842
df30a740
BG		 1843abort_with_irq:
1844 myri10ge_free_irq(mgp);
1845
0da34b6d
BG		 1846abort_with_nothing:
1847 mgp->running = MYRI10GE_ETH_STOPPED;
1848 return -ENOMEM;
1849}
1850
1851static int myri10ge_close(struct net_device *dev)
1852{
1853 struct myri10ge_priv *mgp;
1854 struct myri10ge_cmd cmd;
1855 int status, old_down_cnt;
1856
1857 mgp = netdev_priv(dev);
1858
1859 if (mgp->running != MYRI10GE_ETH_RUNNING)
1860 return 0;
1861
1862 if (mgp->tx.req_bytes == NULL)
1863 return 0;
1864
1865 del_timer_sync(&mgp->watchdog_timer);
1866 mgp->running = MYRI10GE_ETH_STOPPING;
1867 netif_poll_disable(mgp->dev);
1868 netif_carrier_off(dev);
1869 netif_stop_queue(dev);
1870 old_down_cnt = mgp->down_cnt;
1871 mb();
1872 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1873 if (status)
1874 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1875 dev->name);
1876
1877 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1878 if (old_down_cnt == mgp->down_cnt)
1879 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1880
1881 netif_tx_disable(dev);
df30a740 1882 myri10ge_free_irq(mgp);
0da34b6d
BG		 1883 myri10ge_free_rings(dev);
1884
1885 mgp->running = MYRI10GE_ETH_STOPPED;
1886 return 0;
1887}
1888
1889/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1890 * backwards one at a time and handle ring wraps */
1891
1892static inline void
1893myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1894 struct mcp_kreq_ether_send *src, int cnt)
1895{
1896 int idx, starting_slot;
1897 starting_slot = tx->req;
1898 while (cnt > 1) {
1899 cnt--;
1900 idx = (starting_slot + cnt) & tx->mask;
1901 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1902 mb();
1903 }
1904}
1905
1906/*
1907 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1908 * at most 32 bytes at a time, so as to avoid involving the software
1909 * pio handler in the nic. We re-write the first segment's flags
1910 * to mark them valid only after writing the entire chain.
1911 */
1912
1913static inline void
1914myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1915 int cnt)
1916{
1917 int idx, i;
1918 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1919 struct mcp_kreq_ether_send *srcp;
1920 u8 last_flags;
1921
1922 idx = tx->req & tx->mask;
1923
1924 last_flags = src->flags;
1925 src->flags = 0;
1926 mb();
1927 dst = dstp = &tx->lanai[idx];
1928 srcp = src;
1929
1930 if ((idx + cnt) < tx->mask) {
1931 for (i = 0; i < (cnt - 1); i += 2) {
1932 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1933 mb(); /* force write every 32 bytes */
1934 srcp += 2;
1935 dstp += 2;
1936 }
1937 } else {
1938 /* submit all but the first request, and ensure
1939 * that it is submitted below */
1940 myri10ge_submit_req_backwards(tx, src, cnt);
1941 i = 0;
1942 }
1943 if (i < cnt) {
1944 /* submit the first request */
1945 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1946 mb(); /* barrier before setting valid flag */
1947 }
1948
1949 /* re-write the last 32-bits with the valid flags */
1950 src->flags = last_flags;
40f6cff5 1951 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 1952 tx->req += cnt;
1953 mb();
1954}
1955
1956static inline void
1957myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1958 struct mcp_kreq_ether_send *src, int cnt)
1959{
1960 tx->req += cnt;
1961 mb();
1962 while (cnt >= 4) {
1963 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1964 mb();
1965 src += 4;
1966 cnt -= 4;
1967 }
1968 if (cnt > 0) {
1969 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1970 * needs to be so that we don't overrun it */
e700f9f4
BG		 1971 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
1972 src, 64);
0da34b6d
BG		 1973 mb();
1974 }
1975}
1976
1977/*
1978 * Transmit a packet. We need to split the packet so that a single
1979 * segment does not cross myri10ge->tx.boundary, so this makes segment
1980 * counting tricky. So rather than try to count segments up front, we
1981 * just give up if there are too few segments to hold a reasonably
1982 * fragmented packet currently available. If we run
1983 * out of segments while preparing a packet for DMA, we just linearize
1984 * it and try again.
1985 */
1986
1987static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
1988{
1989 struct myri10ge_priv *mgp = netdev_priv(dev);
1990 struct mcp_kreq_ether_send *req;
1991 struct myri10ge_tx_buf *tx = &mgp->tx;
1992 struct skb_frag_struct *frag;
1993 dma_addr_t bus;
40f6cff5
AV		 1994 u32 low;
1995 __be32 high_swapped;
0da34b6d
BG		 1996 unsigned int len;
1997 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
1998 u16 pseudo_hdr_offset, cksum_offset;
1999 int cum_len, seglen, boundary, rdma_count;
2000 u8 flags, odd_flag;
2001
2002again:
2003 req = tx->req_list;
2004 avail = tx->mask - 1 - (tx->req - tx->done);
2005
2006 mss = 0;
2007 max_segments = MXGEFW_MAX_SEND_DESC;
2008
0da34b6d 2009 if (skb->len > (dev->mtu + ETH_HLEN)) {
7967168c 2010 mss = skb_shinfo(skb)->gso_size;
0da34b6d
BG		 2011 if (mss != 0)
2012 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2013 }
0da34b6d
BG		 2014
2015 if ((unlikely(avail < max_segments))) {
2016 /* we are out of transmit resources */
2017 mgp->stop_queue++;
2018 netif_stop_queue(dev);
2019 return 1;
2020 }
2021
2022 /* Setup checksum offloading, if needed */
2023 cksum_offset = 0;
2024 pseudo_hdr_offset = 0;
2025 odd_flag = 0;
2026 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2027 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
0da34b6d 2028 cksum_offset = (skb->h.raw - skb->data);
ff1dcadb 2029 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2030 /* If the headers are excessively large, then we must
2031 * fall back to a software checksum */
2032 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
84fa7933 2033 if (skb_checksum_help(skb))
0da34b6d
BG		 2034 goto drop;
2035 cksum_offset = 0;
2036 pseudo_hdr_offset = 0;
2037 } else {
0da34b6d
BG		 2038 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2039 flags |= MXGEFW_FLAGS_CKSUM;
2040 }
2041 }
2042
2043 cum_len = 0;
2044
0da34b6d
BG		 2045 if (mss) { /* TSO */
2046 /* this removes any CKSUM flag from before */
2047 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2048
2049 /* negative cum_len signifies to the
2050 * send loop that we are still in the
2051 * header portion of the TSO packet.
2052 * TSO header must be at most 134 bytes long */
2053 cum_len = -((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2054
2055 /* for TSO, pseudo_hdr_offset holds mss.
2056 * The firmware figures out where to put
2057 * the checksum by parsing the header. */
40f6cff5 2058 pseudo_hdr_offset = mss;
0da34b6d 2059 } else
0da34b6d
BG		 2060 /* Mark small packets, and pad out tiny packets */
2061 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2062 flags |= MXGEFW_FLAGS_SMALL;
2063
2064 /* pad frames to at least ETH_ZLEN bytes */
2065 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2066 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2067 /* The packet is gone, so we must
2068 * return 0 */
2069 mgp->stats.tx_dropped += 1;
2070 return 0;
2071 }
2072 /* adjust the len to account for the zero pad
2073 * so that the nic can know how long it is */
2074 skb->len = ETH_ZLEN;
2075 }
2076 }
2077
2078 /* map the skb for DMA */
2079 len = skb->len - skb->data_len;
2080 idx = tx->req & tx->mask;
2081 tx->info[idx].skb = skb;
2082 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2083 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2084 pci_unmap_len_set(&tx->info[idx], len, len);
2085
2086 frag_cnt = skb_shinfo(skb)->nr_frags;
2087 frag_idx = 0;
2088 count = 0;
2089 rdma_count = 0;
2090
2091 /* "rdma_count" is the number of RDMAs belonging to the
2092 * current packet BEFORE the current send request. For
2093 * non-TSO packets, this is equal to "count".
2094 * For TSO packets, rdma_count needs to be reset
2095 * to 0 after a segment cut.
2096 *
2097 * The rdma_count field of the send request is
2098 * the number of RDMAs of the packet starting at
2099 * that request. For TSO send requests with one ore more cuts
2100 * in the middle, this is the number of RDMAs starting
2101 * after the last cut in the request. All previous
2102 * segments before the last cut implicitly have 1 RDMA.
2103 *
2104 * Since the number of RDMAs is not known beforehand,
2105 * it must be filled-in retroactively - after each
2106 * segmentation cut or at the end of the entire packet.
2107 */
2108
2109 while (1) {
2110 /* Break the SKB or Fragment up into pieces which
2111 * do not cross mgp->tx.boundary */
2112 low = MYRI10GE_LOWPART_TO_U32(bus);
2113 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2114 while (len) {
2115 u8 flags_next;
2116 int cum_len_next;
2117
2118 if (unlikely(count == max_segments))
2119 goto abort_linearize;
2120
2121 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2122 seglen = boundary - low;
2123 if (seglen > len)
2124 seglen = len;
2125 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2126 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2127 if (mss) { /* TSO */
2128 (req - rdma_count)->rdma_count = rdma_count + 1;
2129
2130 if (likely(cum_len >= 0)) { /* payload */
2131 int next_is_first, chop;
2132
2133 chop = (cum_len_next > mss);
2134 cum_len_next = cum_len_next % mss;
2135 next_is_first = (cum_len_next == 0);
2136 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2137 flags_next |= next_is_first *
2138 MXGEFW_FLAGS_FIRST;
2139 rdma_count |= -(chop | next_is_first);
2140 rdma_count += chop & !next_is_first;
2141 } else if (likely(cum_len_next >= 0)) { /* header ends */
2142 int small;
2143
2144 rdma_count = -1;
2145 cum_len_next = 0;
2146 seglen = -cum_len;
2147 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2148 flags_next = MXGEFW_FLAGS_TSO_PLD |
2149 MXGEFW_FLAGS_FIRST |
2150 (small * MXGEFW_FLAGS_SMALL);
2151 }
2152 }
0da34b6d
BG		 2153 req->addr_high = high_swapped;
2154 req->addr_low = htonl(low);
40f6cff5 2155 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2156 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2157 req->rdma_count = 1;
2158 req->length = htons(seglen);
2159 req->cksum_offset = cksum_offset;
2160 req->flags = flags | ((cum_len & 1) * odd_flag);
2161
2162 low += seglen;
2163 len -= seglen;
2164 cum_len = cum_len_next;
2165 flags = flags_next;
2166 req++;
2167 count++;
2168 rdma_count++;
2169 if (unlikely(cksum_offset > seglen))
2170 cksum_offset -= seglen;
2171 else
2172 cksum_offset = 0;
2173 }
2174 if (frag_idx == frag_cnt)
2175 break;
2176
2177 /* map next fragment for DMA */
2178 idx = (count + tx->req) & tx->mask;
2179 frag = &skb_shinfo(skb)->frags[frag_idx];
2180 frag_idx++;
2181 len = frag->size;
2182 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2183 len, PCI_DMA_TODEVICE);
2184 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2185 pci_unmap_len_set(&tx->info[idx], len, len);
2186 }
2187
2188 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2189 if (mss)
2190 do {
2191 req--;
2192 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2193 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2194 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2195 idx = ((count - 1) + tx->req) & tx->mask;
2196 tx->info[idx].last = 1;
2197 if (tx->wc_fifo == NULL)
2198 myri10ge_submit_req(tx, tx->req_list, count);
2199 else
2200 myri10ge_submit_req_wc(tx, tx->req_list, count);
2201 tx->pkt_start++;
2202 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2203 mgp->stop_queue++;
2204 netif_stop_queue(dev);
2205 }
2206 dev->trans_start = jiffies;
2207 return 0;
2208
2209abort_linearize:
2210 /* Free any DMA resources we've alloced and clear out the skb
2211 * slot so as to not trip up assertions, and to avoid a
2212 * double-free if linearizing fails */
2213
2214 last_idx = (idx + 1) & tx->mask;
2215 idx = tx->req & tx->mask;
2216 tx->info[idx].skb = NULL;
2217 do {
2218 len = pci_unmap_len(&tx->info[idx], len);
2219 if (len) {
2220 if (tx->info[idx].skb != NULL)
2221 pci_unmap_single(mgp->pdev,
2222 pci_unmap_addr(&tx->info[idx],
2223 bus), len,
2224 PCI_DMA_TODEVICE);
2225 else
2226 pci_unmap_page(mgp->pdev,
2227 pci_unmap_addr(&tx->info[idx],
2228 bus), len,
2229 PCI_DMA_TODEVICE);
2230 pci_unmap_len_set(&tx->info[idx], len, 0);
2231 tx->info[idx].skb = NULL;
2232 }
2233 idx = (idx + 1) & tx->mask;
2234 } while (idx != last_idx);
89114afd 2235 if (skb_is_gso(skb)) {
0da34b6d
BG		 2236 printk(KERN_ERR
2237 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2238 mgp->dev->name);
2239 goto drop;
2240 }
2241
bec0e859 2242 if (skb_linearize(skb))
0da34b6d
BG		 2243 goto drop;
2244
2245 mgp->tx_linearized++;
2246 goto again;
2247
2248drop:
2249 dev_kfree_skb_any(skb);
2250 mgp->stats.tx_dropped += 1;
2251 return 0;
2252
2253}
2254
2255static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2256{
2257 struct myri10ge_priv *mgp = netdev_priv(dev);
2258 return &mgp->stats;
2259}
2260
2261static void myri10ge_set_multicast_list(struct net_device *dev)
2262{
85a7ea1b
BG		 2263 struct myri10ge_cmd cmd;
2264 struct myri10ge_priv *mgp;
2265 struct dev_mc_list *mc_list;
6250223e 2266 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 2267 int err;
2268
2269 mgp = netdev_priv(dev);
0da34b6d
BG		 2270 /* can be called from atomic contexts,
2271 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2272 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2273
2274 /* This firmware is known to not support multicast */
9dc6f0e7 2275 if (!mgp->fw_multicast_support || mgp->adopted_rx_filter_bug)
85a7ea1b
BG		 2276 return;
2277
2278 /* Disable multicast filtering */
2279
2280 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2281 if (err != 0) {
2282 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2283 " error status: %d\n", dev->name, err);
2284 goto abort;
2285 }
2286
2287 if (dev->flags & IFF_ALLMULTI) {
2288 /* request to disable multicast filtering, so quit here */
2289 return;
2290 }
2291
2292 /* Flush the filters */
2293
2294 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2295 &cmd, 1);
2296 if (err != 0) {
2297 printk(KERN_ERR
2298 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2299 ", error status: %d\n", dev->name, err);
2300 goto abort;
2301 }
2302
2303 /* Walk the multicast list, and add each address */
2304 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2305 memcpy(data, &mc_list->dmi_addr, 6);
2306 cmd.data0 = ntohl(data[0]);
2307 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2308 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2309 &cmd, 1);
2310
2311 if (err != 0) {
2312 printk(KERN_ERR "myri10ge: %s: Failed "
2313 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2314 "%d\t", dev->name, err);
2315 printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
2316 ((unsigned char *)&mc_list->dmi_addr)[0],
2317 ((unsigned char *)&mc_list->dmi_addr)[1],
2318 ((unsigned char *)&mc_list->dmi_addr)[2],
2319 ((unsigned char *)&mc_list->dmi_addr)[3],
2320 ((unsigned char *)&mc_list->dmi_addr)[4],
2321 ((unsigned char *)&mc_list->dmi_addr)[5]
2322 );
2323 goto abort;
2324 }
2325 }
2326 /* Enable multicast filtering */
2327 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2328 if (err != 0) {
2329 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2330 "error status: %d\n", dev->name, err);
2331 goto abort;
2332 }
2333
2334 return;
2335
2336abort:
2337 return;
0da34b6d
BG		 2338}
2339
2340static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2341{
2342 struct sockaddr *sa = addr;
2343 struct myri10ge_priv *mgp = netdev_priv(dev);
2344 int status;
2345
2346 if (!is_valid_ether_addr(sa->sa_data))
2347 return -EADDRNOTAVAIL;
2348
2349 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2350 if (status != 0) {
2351 printk(KERN_ERR
2352 "myri10ge: %s: changing mac address failed with %d\n",
2353 dev->name, status);
2354 return status;
2355 }
2356
2357 /* change the dev structure */
2358 memcpy(dev->dev_addr, sa->sa_data, 6);
2359 return 0;
2360}
2361
2362static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2363{
2364 struct myri10ge_priv *mgp = netdev_priv(dev);
2365 int error = 0;
2366
2367 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2368 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2369 dev->name, new_mtu);
2370 return -EINVAL;
2371 }
2372 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2373 dev->name, dev->mtu, new_mtu);
2374 if (mgp->running) {
2375 /* if we change the mtu on an active device, we must
2376 * reset the device so the firmware sees the change */
2377 myri10ge_close(dev);
2378 dev->mtu = new_mtu;
2379 myri10ge_open(dev);
2380 } else
2381 dev->mtu = new_mtu;
2382
2383 return error;
2384}
2385
2386/*
2387 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2388 * Only do it if the bridge is a root port since we don't want to disturb
2389 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2390 */
2391
0da34b6d
BG		 2392static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2393{
2394 struct pci_dev *bridge = mgp->pdev->bus->self;
2395 struct device *dev = &mgp->pdev->dev;
2396 unsigned cap;
2397 unsigned err_cap;
2398 u16 val;
2399 u8 ext_type;
2400 int ret;
2401
2402 if (!myri10ge_ecrc_enable || !bridge)
2403 return;
2404
2405 /* check that the bridge is a root port */
2406 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2407 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2408 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2409 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2410 if (myri10ge_ecrc_enable > 1) {
2411 struct pci_dev *old_bridge = bridge;
2412
2413 /* Walk the hierarchy up to the root port
2414 * where ECRC has to be enabled */
2415 do {
2416 bridge = bridge->bus->self;
2417 if (!bridge) {
2418 dev_err(dev,
2419 "Failed to find root port"
2420 " to force ECRC\n");
2421 return;
2422 }
2423 cap =
2424 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2425 pci_read_config_word(bridge,
2426 cap + PCI_CAP_FLAGS, &val);
2427 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2428 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2429
2430 dev_info(dev,
2431 "Forcing ECRC on non-root port %s"
2432 " (enabling on root port %s)\n",
2433 pci_name(old_bridge), pci_name(bridge));
2434 } else {
2435 dev_err(dev,
2436 "Not enabling ECRC on non-root port %s\n",
2437 pci_name(bridge));
2438 return;
2439 }
2440 }
2441
2442 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 2443 if (!cap)
2444 return;
2445
2446 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2447 if (ret) {
2448 dev_err(dev, "failed reading ext-conf-space of %s\n",
2449 pci_name(bridge));
2450 dev_err(dev, "\t pci=nommconf in use? "
2451 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2452 return;
2453 }
2454 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2455 return;
2456
2457 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2458 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2459 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2460 mgp->tx.boundary = 4096;
2461 mgp->fw_name = myri10ge_fw_aligned;
2462}
2463
2464/*
2465 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2466 * when the PCI-E Completion packets are aligned on an 8-byte
2467 * boundary. Some PCI-E chip sets always align Completion packets; on
2468 * the ones that do not, the alignment can be enforced by enabling
2469 * ECRC generation (if supported).
2470 *
2471 * When PCI-E Completion packets are not aligned, it is actually more
2472 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2473 *
2474 * If the driver can neither enable ECRC nor verify that it has
2475 * already been enabled, then it must use a firmware image which works
2476 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2477 * should also ensure that it never gives the device a Read-DMA which is
2478 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2479 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2480 * firmware image, and set tx.boundary to 4KB.
2481 */
2482
ce7f9368
BG		 2483#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
2484#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
0da34b6d
BG		 2485
2486static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2487{
2488 struct pci_dev *bridge = mgp->pdev->bus->self;
2489
2490 mgp->tx.boundary = 2048;
2491 mgp->fw_name = myri10ge_fw_unaligned;
2492
2493 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 2494 int link_width, exp_cap;
2495 u16 lnk;
2496
2497 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2498 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2499 link_width = (lnk >> 4) & 0x3f;
2500
0da34b6d
BG		 2501 myri10ge_enable_ecrc(mgp);
2502
ce7f9368
BG		 2503 /* Check to see if Link is less than 8 or if the
2504 * upstream bridge is known to provide aligned
2505 * completions */
2506 if (link_width < 8) {
2507 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2508 link_width);
2509 mgp->tx.boundary = 4096;
2510 mgp->fw_name = myri10ge_fw_aligned;
2511 } else if (bridge &&
2512 /* ServerWorks HT2000/HT1000 */
2513 ((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2514 && bridge->device ==
2515 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE)
2516 /* All Intel E5000 PCIE ports */
2517 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2518 && bridge->device >=
2519 PCI_DEVICE_ID_INTEL_E5000_PCIE23
2520 && bridge->device <=
2521 PCI_DEVICE_ID_INTEL_E5000_PCIE47))) {
0da34b6d
BG		 2522 dev_info(&mgp->pdev->dev,
2523 "Assuming aligned completions (0x%x:0x%x)\n",
2524 bridge->vendor, bridge->device);
2525 mgp->tx.boundary = 4096;
2526 mgp->fw_name = myri10ge_fw_aligned;
4c882dd8
BG		 2527 } else if (bridge &&
2528 bridge->vendor == PCI_VENDOR_ID_SGI &&
2529 bridge->device == 0x4002 /* TIOCE pcie-port */ ) {
2530 /* this pcie bridge does not support 4K rdma request */
2531 mgp->tx.boundary = 2048;
2532 mgp->fw_name = myri10ge_fw_aligned;
0da34b6d
BG		 2533 }
2534 } else {
2535 if (myri10ge_force_firmware == 1) {
2536 dev_info(&mgp->pdev->dev,
2537 "Assuming aligned completions (forced)\n");
2538 mgp->tx.boundary = 4096;
2539 mgp->fw_name = myri10ge_fw_aligned;
2540 } else {
2541 dev_info(&mgp->pdev->dev,
2542 "Assuming unaligned completions (forced)\n");
2543 mgp->tx.boundary = 2048;
2544 mgp->fw_name = myri10ge_fw_unaligned;
2545 }
2546 }
2547 if (myri10ge_fw_name != NULL) {
2548 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2549 myri10ge_fw_name);
2550 mgp->fw_name = myri10ge_fw_name;
2551 }
2552}
2553
0da34b6d
BG		 2554#ifdef CONFIG_PM
2555
2556static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2557{
2558 struct myri10ge_priv *mgp;
2559 struct net_device *netdev;
2560
2561 mgp = pci_get_drvdata(pdev);
2562 if (mgp == NULL)
2563 return -EINVAL;
2564 netdev = mgp->dev;
2565
2566 netif_device_detach(netdev);
2567 if (netif_running(netdev)) {
2568 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2569 rtnl_lock();
2570 myri10ge_close(netdev);
2571 rtnl_unlock();
2572 }
2573 myri10ge_dummy_rdma(mgp, 0);
83f6e152 2574 pci_save_state(pdev);
0da34b6d 2575 pci_disable_device(pdev);
1a63e846
BG		 2576
2577 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 2578}
2579
2580static int myri10ge_resume(struct pci_dev *pdev)
2581{
2582 struct myri10ge_priv *mgp;
2583 struct net_device *netdev;
2584 int status;
2585 u16 vendor;
2586
2587 mgp = pci_get_drvdata(pdev);
2588 if (mgp == NULL)
2589 return -EINVAL;
2590 netdev = mgp->dev;
2591 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2592 msleep(5); /* give card time to respond */
2593 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2594 if (vendor == 0xffff) {
2595 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2596 mgp->dev->name);
2597 return -EIO;
2598 }
83f6e152 2599
1a63e846
BG		 2600 status = pci_restore_state(pdev);
2601 if (status)
2602 return status;
4c2248cc
BG		 2603
2604 status = pci_enable_device(pdev);
1a63e846 2605 if (status) {
4c2248cc 2606 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 2607 return status;
4c2248cc
BG		 2608 }
2609
0da34b6d
BG		 2610 pci_set_master(pdev);
2611
0da34b6d 2612 myri10ge_reset(mgp);
013b68bf 2613 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 2614
2615 /* Save configuration space to be restored if the
2616 * nic resets due to a parity error */
83f6e152 2617 pci_save_state(pdev);
0da34b6d
BG		 2618
2619 if (netif_running(netdev)) {
2620 rtnl_lock();
df30a740 2621 status = myri10ge_open(netdev);
0da34b6d 2622 rtnl_unlock();
df30a740
BG		 2623 if (status != 0)
2624 goto abort_with_enabled;
2625
0da34b6d
BG		 2626 }
2627 netif_device_attach(netdev);
2628
2629 return 0;
2630
4c2248cc
BG		 2631abort_with_enabled:
2632 pci_disable_device(pdev);
0da34b6d
BG		 2633 return -EIO;
2634
2635}
2636
2637#endif /* CONFIG_PM */
2638
2639static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2640{
2641 struct pci_dev *pdev = mgp->pdev;
2642 int vs = mgp->vendor_specific_offset;
2643 u32 reboot;
2644
2645 /*enter read32 mode */
2646 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2647
2648 /*read REBOOT_STATUS (0xfffffff0) */
2649 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2650 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2651 return reboot;
2652}
2653
2654/*
2655 * This watchdog is used to check whether the board has suffered
2656 * from a parity error and needs to be recovered.
2657 */
c4028958 2658static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 2659{
c4028958 2660 struct myri10ge_priv *mgp =
6250223e 2661 container_of(work, struct myri10ge_priv, watchdog_work);
0da34b6d
BG		 2662 u32 reboot;
2663 int status;
2664 u16 cmd, vendor;
2665
2666 mgp->watchdog_resets++;
2667 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2668 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2669 /* Bus master DMA disabled? Check to see
2670 * if the card rebooted due to a parity error
2671 * For now, just report it */
2672 reboot = myri10ge_read_reboot(mgp);
2673 printk(KERN_ERR
2674 "myri10ge: %s: NIC rebooted (0x%x), resetting\n",
2675 mgp->dev->name, reboot);
2676 /*
2677 * A rebooted nic will come back with config space as
2678 * it was after power was applied to PCIe bus.
2679 * Attempt to restore config space which was saved
2680 * when the driver was loaded, or the last time the
2681 * nic was resumed from power saving mode.
2682 */
83f6e152 2683 pci_restore_state(mgp->pdev);
7adda30c
BG		 2684
2685 /* save state again for accounting reasons */
83f6e152 2686 pci_save_state(mgp->pdev);
7adda30c 2687
0da34b6d
BG		 2688 } else {
2689 /* if we get back -1's from our slot, perhaps somebody
2690 * powered off our card. Don't try to reset it in
2691 * this case */
2692 if (cmd == 0xffff) {
2693 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2694 if (vendor == 0xffff) {
2695 printk(KERN_ERR
2696 "myri10ge: %s: device disappeared!\n",
2697 mgp->dev->name);
2698 return;
2699 }
2700 }
2701 /* Perhaps it is a software error. Try to reset */
2702
2703 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2704 mgp->dev->name);
2705 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2706 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2707 mgp->tx.pkt_start, mgp->tx.pkt_done,
2708 (int)ntohl(mgp->fw_stats->send_done_count));
2709 msleep(2000);
2710 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2711 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2712 mgp->tx.pkt_start, mgp->tx.pkt_done,
2713 (int)ntohl(mgp->fw_stats->send_done_count));
2714 }
2715 rtnl_lock();
2716 myri10ge_close(mgp->dev);
2717 status = myri10ge_load_firmware(mgp);
2718 if (status != 0)
2719 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2720 mgp->dev->name);
2721 else
2722 myri10ge_open(mgp->dev);
2723 rtnl_unlock();
2724}
2725
2726/*
2727 * We use our own timer routine rather than relying upon
2728 * netdev->tx_timeout because we have a very large hardware transmit
2729 * queue. Due to the large queue, the netdev->tx_timeout function
2730 * cannot detect a NIC with a parity error in a timely fashion if the
2731 * NIC is lightly loaded.
2732 */
2733static void myri10ge_watchdog_timer(unsigned long arg)
2734{
2735 struct myri10ge_priv *mgp;
2736
2737 mgp = (struct myri10ge_priv *)arg;
c7dab99b
BG		 2738
2739 if (mgp->rx_small.watchdog_needed) {
2740 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2741 mgp->small_bytes + MXGEFW_PAD, 1);
2742 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2743 myri10ge_fill_thresh)
2744 mgp->rx_small.watchdog_needed = 0;
2745 }
2746 if (mgp->rx_big.watchdog_needed) {
2747 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2748 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2749 myri10ge_fill_thresh)
2750 mgp->rx_big.watchdog_needed = 0;
2751 }
2752
0da34b6d 2753 if (mgp->tx.req != mgp->tx.done &&
c54772e7
BG		 2754 mgp->tx.done == mgp->watchdog_tx_done &&
2755 mgp->watchdog_tx_req != mgp->watchdog_tx_done)
0da34b6d
BG		 2756 /* nic seems like it might be stuck.. */
2757 schedule_work(&mgp->watchdog_work);
2758 else
2759 /* rearm timer */
2760 mod_timer(&mgp->watchdog_timer,
2761 jiffies + myri10ge_watchdog_timeout * HZ);
2762
2763 mgp->watchdog_tx_done = mgp->tx.done;
c54772e7 2764 mgp->watchdog_tx_req = mgp->tx.req;
0da34b6d
BG		 2765}
2766
2767static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2768{
2769 struct net_device *netdev;
2770 struct myri10ge_priv *mgp;
2771 struct device *dev = &pdev->dev;
2772 size_t bytes;
2773 int i;
2774 int status = -ENXIO;
2775 int cap;
2776 int dac_enabled;
2777 u16 val;
2778
2779 netdev = alloc_etherdev(sizeof(*mgp));
2780 if (netdev == NULL) {
2781 dev_err(dev, "Could not allocate ethernet device\n");
2782 return -ENOMEM;
2783 }
2784
2785 mgp = netdev_priv(netdev);
2786 memset(mgp, 0, sizeof(*mgp));
2787 mgp->dev = netdev;
2788 mgp->pdev = pdev;
2789 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2790 mgp->pause = myri10ge_flow_control;
2791 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 2792 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 2793 init_waitqueue_head(&mgp->down_wq);
2794
2795 if (pci_enable_device(pdev)) {
2796 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2797 status = -ENODEV;
2798 goto abort_with_netdev;
2799 }
2800 myri10ge_select_firmware(mgp);
2801
2802 /* Find the vendor-specific cap so we can check
2803 * the reboot register later on */
2804 mgp->vendor_specific_offset
2805 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2806
2807 /* Set our max read request to 4KB */
2808 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2809 if (cap < 64) {
2810 dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2811 goto abort_with_netdev;
2812 }
2813 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2814 if (status != 0) {
2815 dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n",
2816 status);
2817 goto abort_with_netdev;
2818 }
2819 val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
2820 status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val);
2821 if (status != 0) {
2822 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2823 status);
2824 goto abort_with_netdev;
2825 }
2826
2827 pci_set_master(pdev);
2828 dac_enabled = 1;
2829 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2830 if (status != 0) {
2831 dac_enabled = 0;
2832 dev_err(&pdev->dev,
2833 "64-bit pci address mask was refused, trying 32-bit");
2834 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2835 }
2836 if (status != 0) {
2837 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2838 goto abort_with_netdev;
2839 }
b10c0668
BG		 2840 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2841 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 2842 if (mgp->cmd == NULL)
2843 goto abort_with_netdev;
2844
b10c0668
BG		 2845 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2846 &mgp->fw_stats_bus, GFP_KERNEL);
0da34b6d
BG		 2847 if (mgp->fw_stats == NULL)
2848 goto abort_with_cmd;
2849
2850 mgp->board_span = pci_resource_len(pdev, 0);
2851 mgp->iomem_base = pci_resource_start(pdev, 0);
2852 mgp->mtrr = -1;
2853#ifdef CONFIG_MTRR
2854 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2855 MTRR_TYPE_WRCOMB, 1);
2856#endif
2857 /* Hack. need to get rid of these magic numbers */
2858 mgp->sram_size =
2859 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2860 if (mgp->sram_size > mgp->board_span) {
2861 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2862 mgp->board_span);
2863 goto abort_with_wc;
2864 }
2865 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2866 if (mgp->sram == NULL) {
2867 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2868 mgp->board_span, mgp->iomem_base);
2869 status = -ENXIO;
2870 goto abort_with_wc;
2871 }
2872 memcpy_fromio(mgp->eeprom_strings,
2873 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2874 MYRI10GE_EEPROM_STRINGS_SIZE);
2875 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2876 status = myri10ge_read_mac_addr(mgp);
2877 if (status)
2878 goto abort_with_ioremap;
2879
2880 for (i = 0; i < ETH_ALEN; i++)
2881 netdev->dev_addr[i] = mgp->mac_addr[i];
2882
2883 /* allocate rx done ring */
2884 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2885 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2886 &mgp->rx_done.bus, GFP_KERNEL);
0da34b6d
BG		 2887 if (mgp->rx_done.entry == NULL)
2888 goto abort_with_ioremap;
2889 memset(mgp->rx_done.entry, 0, bytes);
2890
2891 status = myri10ge_load_firmware(mgp);
2892 if (status != 0) {
2893 dev_err(&pdev->dev, "failed to load firmware\n");
2894 goto abort_with_rx_done;
2895 }
2896
2897 status = myri10ge_reset(mgp);
2898 if (status != 0) {
2899 dev_err(&pdev->dev, "failed reset\n");
2900 goto abort_with_firmware;
2901 }
2902
0da34b6d
BG		 2903 pci_set_drvdata(pdev, mgp);
2904 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2905 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2906 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2907 myri10ge_initial_mtu = 68;
2908 netdev->mtu = myri10ge_initial_mtu;
2909 netdev->open = myri10ge_open;
2910 netdev->stop = myri10ge_close;
2911 netdev->hard_start_xmit = myri10ge_xmit;
2912 netdev->get_stats = myri10ge_get_stats;
2913 netdev->base_addr = mgp->iomem_base;
0da34b6d
BG		 2914 netdev->change_mtu = myri10ge_change_mtu;
2915 netdev->set_multicast_list = myri10ge_set_multicast_list;
2916 netdev->set_mac_address = myri10ge_set_mac_address;
2917 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2918 if (dac_enabled)
2919 netdev->features |= NETIF_F_HIGHDMA;
2920 netdev->poll = myri10ge_poll;
2921 netdev->weight = myri10ge_napi_weight;
2922
21d05db1
BG		 2923 /* make sure we can get an irq, and that MSI can be
2924 * setup (if available). Also ensure netdev->irq
2925 * is set to correct value if MSI is enabled */
2926 status = myri10ge_request_irq(mgp);
2927 if (status != 0)
2928 goto abort_with_firmware;
2929 netdev->irq = pdev->irq;
2930 myri10ge_free_irq(mgp);
2931
0da34b6d
BG		 2932 /* Save configuration space to be restored if the
2933 * nic resets due to a parity error */
83f6e152 2934 pci_save_state(pdev);
0da34b6d
BG		 2935
2936 /* Setup the watchdog timer */
2937 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
2938 (unsigned long)mgp);
2939
2940 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 2941 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 2942 status = register_netdev(netdev);
2943 if (status != 0) {
2944 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 2945 goto abort_with_state;
0da34b6d 2946 }
21d05db1
BG		 2947 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
2948 (mgp->msi_enabled ? "MSI" : "xPIC"),
2949 netdev->irq, mgp->tx.boundary, mgp->fw_name,
d6020787 2950 (mgp->mtrr >= 0 ? "Enabled" : "Disabled"));
0da34b6d
BG		 2951
2952 return 0;
2953
7adda30c 2954abort_with_state:
83f6e152 2955 pci_restore_state(pdev);
0da34b6d
BG		 2956
2957abort_with_firmware:
2958 myri10ge_dummy_rdma(mgp, 0);
2959
2960abort_with_rx_done:
2961 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 2962 dma_free_coherent(&pdev->dev, bytes,
2963 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 2964
2965abort_with_ioremap:
2966 iounmap(mgp->sram);
2967
2968abort_with_wc:
2969#ifdef CONFIG_MTRR
2970 if (mgp->mtrr >= 0)
2971 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2972#endif
b10c0668
BG		 2973 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2974 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d
BG		 2975
2976abort_with_cmd:
b10c0668
BG		 2977 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2978 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 2979
2980abort_with_netdev:
2981
2982 free_netdev(netdev);
2983 return status;
2984}
2985
2986/*
2987 * myri10ge_remove
2988 *
2989 * Does what is necessary to shutdown one Myrinet device. Called
2990 * once for each Myrinet card by the kernel when a module is
2991 * unloaded.
2992 */
2993static void myri10ge_remove(struct pci_dev *pdev)
2994{
2995 struct myri10ge_priv *mgp;
2996 struct net_device *netdev;
2997 size_t bytes;
2998
2999 mgp = pci_get_drvdata(pdev);
3000 if (mgp == NULL)
3001 return;
3002
3003 flush_scheduled_work();
3004 netdev = mgp->dev;
3005 unregister_netdev(netdev);
0da34b6d
BG		 3006
3007 myri10ge_dummy_rdma(mgp, 0);
3008
7adda30c 3009 /* avoid a memory leak */
83f6e152 3010 pci_restore_state(pdev);
7adda30c 3011
0da34b6d 3012 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3013 dma_free_coherent(&pdev->dev, bytes,
3014 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3015
3016 iounmap(mgp->sram);
3017
3018#ifdef CONFIG_MTRR
3019 if (mgp->mtrr >= 0)
3020 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3021#endif
b10c0668
BG		 3022 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3023 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d 3024
b10c0668
BG		 3025 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3026 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3027
3028 free_netdev(netdev);
3029 pci_set_drvdata(pdev, NULL);
3030}
3031
b10c0668 3032#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
0da34b6d
BG		 3033
3034static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3035 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
0da34b6d
BG		 3036 {0},
3037};
3038
3039static struct pci_driver myri10ge_driver = {
3040 .name = "myri10ge",
3041 .probe = myri10ge_probe,
3042 .remove = myri10ge_remove,
3043 .id_table = myri10ge_pci_tbl,
3044#ifdef CONFIG_PM
3045 .suspend = myri10ge_suspend,
3046 .resume = myri10ge_resume,
3047#endif
3048};
3049
3050static __init int myri10ge_init_module(void)
3051{
3052 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3053 MYRI10GE_VERSION_STR);
3054 return pci_register_driver(&myri10ge_driver);
3055}
3056
3057module_init(myri10ge_init_module);
3058
3059static __exit void myri10ge_cleanup_module(void)
3060{
3061 pci_unregister_driver(&myri10ge_driver);
3062}
3063
3064module_exit(myri10ge_cleanup_module);
Linux 6.x block layer and io_uring tree(s)