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Merge branches 'core/debug', 'core/futexes', 'core/locking', 'core/rcu', 'core/signal...
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
c3efab8e 41#include <linux/ip.h>
1da177e4
LT		 42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/etherdevice.h>
1da177e4
LT		 45#include <linux/delay.h>
46#include <linux/ethtool.h>
d052d1be 47#include <linux/platform_device.h>
fbd6a754
LB		 48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/spinlock.h>
51#include <linux/workqueue.h>
ed94493f 52#include <linux/phy.h>
fbd6a754 53#include <linux/mv643xx_eth.h>
1da177e4
LT		 54#include <asm/io.h>
55#include <asm/types.h>
1da177e4 56#include <asm/system.h>
fbd6a754 57
e5371493 58static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 59static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 60
fbd6a754 61
fbd6a754
LB		 62/*
63 * Registers shared between all ports.
64 */
3cb4667c
LB		 65#define PHY_ADDR 0x0000
66#define SMI_REG 0x0004
45c5d3bc
LB		 67#define SMI_BUSY 0x10000000
68#define SMI_READ_VALID 0x08000000
69#define SMI_OPCODE_READ 0x04000000
70#define SMI_OPCODE_WRITE 0x00000000
71#define ERR_INT_CAUSE 0x0080
72#define ERR_INT_SMI_DONE 0x00000010
73#define ERR_INT_MASK 0x0084
3cb4667c
LB		 74#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77#define WINDOW_BAR_ENABLE 0x0290
78#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 79
80/*
81 * Per-port registers.
82 */
3cb4667c 83#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 84#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 85#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
86#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
87#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
88#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
89#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
90#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 91#define TX_FIFO_EMPTY 0x00000400
ae9ae064 92#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 93#define PORT_SPEED_MASK 0x00000030
94#define PORT_SPEED_1000 0x00000010
95#define PORT_SPEED_100 0x00000020
96#define PORT_SPEED_10 0x00000000
97#define FLOW_CONTROL_ENABLED 0x00000008
98#define FULL_DUPLEX 0x00000004
81600eea 99#define LINK_UP 0x00000002
3cb4667c 100#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 101#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
102#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 103#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 104#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 105#define INT_CAUSE(p) (0x0460 + ((p) << 10))
226bb6b7 106#define INT_TX_END 0x07f80000
befefe21 107#define INT_RX 0x000003fc
073a345c 108#define INT_EXT 0x00000002
3cb4667c 109#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
befefe21
LB		 110#define INT_EXT_LINK_PHY 0x00110000
111#define INT_EXT_TX 0x000000ff
3cb4667c
LB		 112#define INT_MASK(p) (0x0468 + ((p) << 10))
113#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
114#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
1e881592
LB		 115#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
116#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
117#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
118#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
64da80a2 119#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 120#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 121#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
122#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
123#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
124#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 125#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
126#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
127#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
128#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 129
2679a550
LB		 130
131/*
132 * SDMA configuration register.
133 */
cd4ccf76 134#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 135#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 136#define BLM_TX_NO_SWAP (1 << 5)
cd4ccf76 137#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 138
139#if defined(__BIG_ENDIAN)
140#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76
LB		 141 RX_BURST_SIZE_16_64BIT | \
142 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 143#elif defined(__LITTLE_ENDIAN)
144#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76 145 RX_BURST_SIZE_16_64BIT | \
fbd6a754
LB		 146 BLM_RX_NO_SWAP | \
147 BLM_TX_NO_SWAP | \
cd4ccf76 148 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 149#else
150#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
151#endif
152
2beff77b
LB		 153
154/*
155 * Port serial control register.
156 */
157#define SET_MII_SPEED_TO_100 (1 << 24)
158#define SET_GMII_SPEED_TO_1000 (1 << 23)
159#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 160#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 161#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
162#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
163#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
164#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
165#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
166#define FORCE_LINK_PASS (1 << 1)
167#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 168
2b4a624d
LB		 169#define DEFAULT_RX_QUEUE_SIZE 128
170#define DEFAULT_TX_QUEUE_SIZE 256
fbd6a754 171
fbd6a754 172
7ca72a3b
LB		 173/*
174 * RX/TX descriptors.
fbd6a754
LB		 175 */
176#if defined(__BIG_ENDIAN)
cc9754b3 177struct rx_desc {
fbd6a754
LB		 178 u16 byte_cnt; /* Descriptor buffer byte count */
179 u16 buf_size; /* Buffer size */
180 u32 cmd_sts; /* Descriptor command status */
181 u32 next_desc_ptr; /* Next descriptor pointer */
182 u32 buf_ptr; /* Descriptor buffer pointer */
183};
184
cc9754b3 185struct tx_desc {
fbd6a754
LB		 186 u16 byte_cnt; /* buffer byte count */
187 u16 l4i_chk; /* CPU provided TCP checksum */
188 u32 cmd_sts; /* Command/status field */
189 u32 next_desc_ptr; /* Pointer to next descriptor */
190 u32 buf_ptr; /* pointer to buffer for this descriptor*/
191};
192#elif defined(__LITTLE_ENDIAN)
cc9754b3 193struct rx_desc {
fbd6a754
LB		 194 u32 cmd_sts; /* Descriptor command status */
195 u16 buf_size; /* Buffer size */
196 u16 byte_cnt; /* Descriptor buffer byte count */
197 u32 buf_ptr; /* Descriptor buffer pointer */
198 u32 next_desc_ptr; /* Next descriptor pointer */
199};
200
cc9754b3 201struct tx_desc {
fbd6a754
LB		 202 u32 cmd_sts; /* Command/status field */
203 u16 l4i_chk; /* CPU provided TCP checksum */
204 u16 byte_cnt; /* buffer byte count */
205 u32 buf_ptr; /* pointer to buffer for this descriptor*/
206 u32 next_desc_ptr; /* Pointer to next descriptor */
207};
208#else
209#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
210#endif
211
7ca72a3b 212/* RX & TX descriptor command */
cc9754b3 213#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 214
215/* RX & TX descriptor status */
cc9754b3 216#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 217
218/* RX descriptor status */
cc9754b3
LB		 219#define LAYER_4_CHECKSUM_OK 0x40000000
220#define RX_ENABLE_INTERRUPT 0x20000000
221#define RX_FIRST_DESC 0x08000000
222#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 223
224/* TX descriptor command */
cc9754b3
LB		 225#define TX_ENABLE_INTERRUPT 0x00800000
226#define GEN_CRC 0x00400000
227#define TX_FIRST_DESC 0x00200000
228#define TX_LAST_DESC 0x00100000
229#define ZERO_PADDING 0x00080000
230#define GEN_IP_V4_CHECKSUM 0x00040000
231#define GEN_TCP_UDP_CHECKSUM 0x00020000
232#define UDP_FRAME 0x00010000
e32b6617
LB		 233#define MAC_HDR_EXTRA_4_BYTES 0x00008000
234#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 235
cc9754b3 236#define TX_IHL_SHIFT 11
7ca72a3b
LB		 237
238
c9df406f 239/* global *******************************************************************/
e5371493 240struct mv643xx_eth_shared_private {
fc32b0e2
LB		 241 /*
242 * Ethernet controller base address.
243 */
cc9754b3 244 void __iomem *base;
c9df406f 245
fc0eb9f2
LB		 246 /*
247 * Points at the right SMI instance to use.
248 */
249 struct mv643xx_eth_shared_private *smi;
250
fc32b0e2 251 /*
ed94493f 252 * Provides access to local SMI interface.
fc32b0e2 253 */
298cf9be 254 struct mii_bus *smi_bus;
c9df406f 255
45c5d3bc
LB		 256 /*
257 * If we have access to the error interrupt pin (which is
258 * somewhat misnamed as it not only reflects internal errors
259 * but also reflects SMI completion), use that to wait for
260 * SMI access completion instead of polling the SMI busy bit.
261 */
262 int err_interrupt;
263 wait_queue_head_t smi_busy_wait;
264
fc32b0e2
LB		 265 /*
266 * Per-port MBUS window access register value.
267 */
c9df406f
LB		 268 u32 win_protect;
269
fc32b0e2
LB		 270 /*
271 * Hardware-specific parameters.
272 */
c9df406f 273 unsigned int t_clk;
773fc3ee 274 int extended_rx_coal_limit;
457b1d5a 275 int tx_bw_control;
c9df406f
LB		 276};
277
457b1d5a
LB		 278#define TX_BW_CONTROL_ABSENT 0
279#define TX_BW_CONTROL_OLD_LAYOUT 1
280#define TX_BW_CONTROL_NEW_LAYOUT 2
281
c9df406f
LB		 282
283/* per-port *****************************************************************/
e5371493 284struct mib_counters {
fbd6a754
LB		 285 u64 good_octets_received;
286 u32 bad_octets_received;
287 u32 internal_mac_transmit_err;
288 u32 good_frames_received;
289 u32 bad_frames_received;
290 u32 broadcast_frames_received;
291 u32 multicast_frames_received;
292 u32 frames_64_octets;
293 u32 frames_65_to_127_octets;
294 u32 frames_128_to_255_octets;
295 u32 frames_256_to_511_octets;
296 u32 frames_512_to_1023_octets;
297 u32 frames_1024_to_max_octets;
298 u64 good_octets_sent;
299 u32 good_frames_sent;
300 u32 excessive_collision;
301 u32 multicast_frames_sent;
302 u32 broadcast_frames_sent;
303 u32 unrec_mac_control_received;
304 u32 fc_sent;
305 u32 good_fc_received;
306 u32 bad_fc_received;
307 u32 undersize_received;
308 u32 fragments_received;
309 u32 oversize_received;
310 u32 jabber_received;
311 u32 mac_receive_error;
312 u32 bad_crc_event;
313 u32 collision;
314 u32 late_collision;
315};
316
8a578111 317struct rx_queue {
64da80a2
LB		 318 int index;
319
8a578111
LB		 320 int rx_ring_size;
321
322 int rx_desc_count;
323 int rx_curr_desc;
324 int rx_used_desc;
325
326 struct rx_desc *rx_desc_area;
327 dma_addr_t rx_desc_dma;
328 int rx_desc_area_size;
329 struct sk_buff **rx_skb;
8a578111
LB		 330};
331
13d64285 332struct tx_queue {
3d6b35bc
LB		 333 int index;
334
13d64285 335 int tx_ring_size;
fbd6a754 336
13d64285
LB		 337 int tx_desc_count;
338 int tx_curr_desc;
339 int tx_used_desc;
fbd6a754 340
5daffe94 341 struct tx_desc *tx_desc_area;
fbd6a754
LB		 342 dma_addr_t tx_desc_dma;
343 int tx_desc_area_size;
99ab08e0
LB		 344
345 struct sk_buff_head tx_skb;
8fd89211
LB		 346
347 unsigned long tx_packets;
348 unsigned long tx_bytes;
349 unsigned long tx_dropped;
13d64285
LB		 350};
351
352struct mv643xx_eth_private {
353 struct mv643xx_eth_shared_private *shared;
fc32b0e2 354 int port_num;
13d64285 355
fc32b0e2 356 struct net_device *dev;
fbd6a754 357
ed94493f 358 struct phy_device *phy;
fbd6a754 359
4ff3495a
LB		 360 struct timer_list mib_counters_timer;
361 spinlock_t mib_counters_lock;
fc32b0e2 362 struct mib_counters mib_counters;
4ff3495a 363
fc32b0e2 364 struct work_struct tx_timeout_task;
8a578111 365
1fa38c58
LB		 366 struct napi_struct napi;
367 u8 work_link;
368 u8 work_tx;
369 u8 work_tx_end;
370 u8 work_rx;
371 u8 work_rx_refill;
372 u8 work_rx_oom;
373
2bcb4b0f
LB		 374 int skb_size;
375 struct sk_buff_head rx_recycle;
376
8a578111
LB		 377 /*
378 * RX state.
379 */
380 int default_rx_ring_size;
381 unsigned long rx_desc_sram_addr;
382 int rx_desc_sram_size;
f7981c1c 383 int rxq_count;
2257e05c 384 struct timer_list rx_oom;
64da80a2 385 struct rx_queue rxq[8];
13d64285
LB		 386
387 /*
388 * TX state.
389 */
390 int default_tx_ring_size;
391 unsigned long tx_desc_sram_addr;
392 int tx_desc_sram_size;
f7981c1c 393 int txq_count;
3d6b35bc 394 struct tx_queue txq[8];
fbd6a754 395};
1da177e4 396
fbd6a754 397
c9df406f 398/* port register accessors **************************************************/
e5371493 399static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 400{
cc9754b3 401 return readl(mp->shared->base + offset);
c9df406f 402}
fbd6a754 403
e5371493 404static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 405{
cc9754b3 406 writel(data, mp->shared->base + offset);
c9df406f 407}
fbd6a754 408
fbd6a754 409
c9df406f 410/* rxq/txq helper functions *************************************************/
8a578111 411static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 412{
64da80a2 413 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 414}
fbd6a754 415
13d64285
LB		 416static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
417{
3d6b35bc 418 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 419}
420
8a578111 421static void rxq_enable(struct rx_queue *rxq)
c9df406f 422{
8a578111 423 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 424 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 425}
1da177e4 426
8a578111
LB		 427static void rxq_disable(struct rx_queue *rxq)
428{
429 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 430 u8 mask = 1 << rxq->index;
1da177e4 431
8a578111
LB		 432 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
433 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
434 udelay(10);
c9df406f
LB		 435}
436
6b368f68
LB		 437static void txq_reset_hw_ptr(struct tx_queue *txq)
438{
439 struct mv643xx_eth_private *mp = txq_to_mp(txq);
440 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
441 u32 addr;
442
443 addr = (u32)txq->tx_desc_dma;
444 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
445 wrl(mp, off, addr);
446}
447
13d64285 448static void txq_enable(struct tx_queue *txq)
1da177e4 449{
13d64285 450 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 451 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 452}
453
13d64285 454static void txq_disable(struct tx_queue *txq)
1da177e4 455{
13d64285 456 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 457 u8 mask = 1 << txq->index;
c9df406f 458
13d64285
LB		 459 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
460 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
461 udelay(10);
462}
463
1fa38c58 464static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 465{
466 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 467 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 468
8fd89211
LB		 469 if (netif_tx_queue_stopped(nq)) {
470 __netif_tx_lock(nq, smp_processor_id());
471 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
472 netif_tx_wake_queue(nq);
473 __netif_tx_unlock(nq);
474 }
1da177e4
LT		 475}
476
c9df406f 477
1fa38c58 478/* rx napi ******************************************************************/
8a578111 479static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 480{
8a578111
LB		 481 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
482 struct net_device_stats *stats = &mp->dev->stats;
483 int rx;
1da177e4 484
8a578111 485 rx = 0;
9e1f3772 486 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 487 struct rx_desc *rx_desc;
96587661 488 unsigned int cmd_sts;
fc32b0e2 489 struct sk_buff *skb;
6b8f90c2 490 u16 byte_cnt;
ff561eef 491
8a578111 492 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 493
96587661 494 cmd_sts = rx_desc->cmd_sts;
2257e05c 495 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 496 break;
96587661 497 rmb();
1da177e4 498
8a578111
LB		 499 skb = rxq->rx_skb[rxq->rx_curr_desc];
500 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 501
9da78745
LB		 502 rxq->rx_curr_desc++;
503 if (rxq->rx_curr_desc == rxq->rx_ring_size)
504 rxq->rx_curr_desc = 0;
ff561eef 505
3a499481 506 dma_unmap_single(NULL, rx_desc->buf_ptr,
abe78717 507 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 508 rxq->rx_desc_count--;
509 rx++;
b1dd9ca1 510
1fa38c58
LB		 511 mp->work_rx_refill |= 1 << rxq->index;
512
6b8f90c2
LB		 513 byte_cnt = rx_desc->byte_cnt;
514
468d09f8
DF		 515 /*
516 * Update statistics.
fc32b0e2
LB		 517 *
518 * Note that the descriptor byte count includes 2 dummy
519 * bytes automatically inserted by the hardware at the
520 * start of the packet (which we don't count), and a 4
521 * byte CRC at the end of the packet (which we do count).
468d09f8 522 */
1da177e4 523 stats->rx_packets++;
6b8f90c2 524 stats->rx_bytes += byte_cnt - 2;
96587661 525
1da177e4 526 /*
fc32b0e2
LB		 527 * In case we received a packet without first / last bits
528 * on, or the error summary bit is set, the packet needs
529 * to be dropped.
1da177e4 530 */
96587661 531 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 532 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 533 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 534 stats->rx_dropped++;
fc32b0e2 535
96587661 536 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 537 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 538 if (net_ratelimit())
fc32b0e2
LB		 539 dev_printk(KERN_ERR, &mp->dev->dev,
540 "received packet spanning "
541 "multiple descriptors\n");
1da177e4 542 }
fc32b0e2 543
96587661 544 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 545 stats->rx_errors++;
546
78fff83b 547 dev_kfree_skb(skb);
1da177e4
LT		 548 } else {
549 /*
550 * The -4 is for the CRC in the trailer of the
551 * received packet
552 */
6b8f90c2 553 skb_put(skb, byte_cnt - 2 - 4);
1da177e4 554
170e7108 555 if (cmd_sts & LAYER_4_CHECKSUM_OK)
1da177e4 556 skb->ip_summed = CHECKSUM_UNNECESSARY;
8a578111 557 skb->protocol = eth_type_trans(skb, mp->dev);
1da177e4 558 netif_receive_skb(skb);
1da177e4 559 }
fc32b0e2 560
8a578111 561 mp->dev->last_rx = jiffies;
1da177e4 562 }
fc32b0e2 563
1fa38c58
LB		 564 if (rx < budget)
565 mp->work_rx &= ~(1 << rxq->index);
566
8a578111 567 return rx;
1da177e4
LT		 568}
569
1fa38c58 570static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 571{
1fa38c58 572 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 573 int refilled;
8a578111 574
1fa38c58
LB		 575 refilled = 0;
576 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
577 struct sk_buff *skb;
578 int unaligned;
579 int rx;
d0412d96 580
2bcb4b0f
LB		 581 skb = __skb_dequeue(&mp->rx_recycle);
582 if (skb == NULL)
583 skb = dev_alloc_skb(mp->skb_size +
584 dma_get_cache_alignment() - 1);
585
1fa38c58
LB		 586 if (skb == NULL) {
587 mp->work_rx_oom |= 1 << rxq->index;
588 goto oom;
589 }
d0412d96 590
1fa38c58
LB		 591 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
592 if (unaligned)
593 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
2257e05c 594
1fa38c58
LB		 595 refilled++;
596 rxq->rx_desc_count++;
c9df406f 597
1fa38c58
LB		 598 rx = rxq->rx_used_desc++;
599 if (rxq->rx_used_desc == rxq->rx_ring_size)
600 rxq->rx_used_desc = 0;
2257e05c 601
1fa38c58 602 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
2bcb4b0f
LB		 603 mp->skb_size, DMA_FROM_DEVICE);
604 rxq->rx_desc_area[rx].buf_size = mp->skb_size;
1fa38c58
LB		 605 rxq->rx_skb[rx] = skb;
606 wmb();
607 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
608 RX_ENABLE_INTERRUPT;
609 wmb();
2257e05c 610
1fa38c58
LB		 611 /*
612 * The hardware automatically prepends 2 bytes of
613 * dummy data to each received packet, so that the
614 * IP header ends up 16-byte aligned.
615 */
616 skb_reserve(skb, 2);
617 }
618
619 if (refilled < budget)
620 mp->work_rx_refill &= ~(1 << rxq->index);
621
622oom:
623 return refilled;
d0412d96
JC		 624}
625
c9df406f
LB		 626
627/* tx ***********************************************************************/
c9df406f 628static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 629{
13d64285 630 int frag;
1da177e4 631
c9df406f 632 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 633 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
634 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 635 return 1;
1da177e4 636 }
13d64285 637
c9df406f
LB		 638 return 0;
639}
7303fde8 640
13d64285 641static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 642{
643 int tx_desc_curr;
d0412d96 644
13d64285 645 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 646
9da78745
LB		 647 tx_desc_curr = txq->tx_curr_desc++;
648 if (txq->tx_curr_desc == txq->tx_ring_size)
649 txq->tx_curr_desc = 0;
e4d00fa9 650
13d64285 651 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 652
c9df406f
LB		 653 return tx_desc_curr;
654}
468d09f8 655
13d64285 656static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 657{
13d64285 658 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 659 int frag;
1da177e4 660
13d64285
LB		 661 for (frag = 0; frag < nr_frags; frag++) {
662 skb_frag_t *this_frag;
663 int tx_index;
664 struct tx_desc *desc;
665
666 this_frag = &skb_shinfo(skb)->frags[frag];
667 tx_index = txq_alloc_desc_index(txq);
668 desc = &txq->tx_desc_area[tx_index];
669
670 /*
671 * The last fragment will generate an interrupt
672 * which will free the skb on TX completion.
673 */
674 if (frag == nr_frags - 1) {
675 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
676 ZERO_PADDING | TX_LAST_DESC |
677 TX_ENABLE_INTERRUPT;
13d64285
LB		 678 } else {
679 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 680 }
681
c9df406f
LB		 682 desc->l4i_chk = 0;
683 desc->byte_cnt = this_frag->size;
684 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
685 this_frag->page_offset,
686 this_frag->size,
687 DMA_TO_DEVICE);
688 }
1da177e4
LT		 689}
690
c9df406f
LB		 691static inline __be16 sum16_as_be(__sum16 sum)
692{
693 return (__force __be16)sum;
694}
1da177e4 695
4df89bd5 696static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 697{
8fa89bf5 698 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 699 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 700 int tx_index;
cc9754b3 701 struct tx_desc *desc;
c9df406f 702 u32 cmd_sts;
4df89bd5 703 u16 l4i_chk;
c9df406f 704 int length;
1da177e4 705
cc9754b3 706 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 707 l4i_chk = 0;
c9df406f
LB		 708
709 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4df89bd5 710 int tag_bytes;
e32b6617
LB		 711
712 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
713 skb->protocol != htons(ETH_P_8021Q));
c9df406f 714
4df89bd5
LB		 715 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
716 if (unlikely(tag_bytes & ~12)) {
717 if (skb_checksum_help(skb) == 0)
718 goto no_csum;
719 kfree_skb(skb);
720 return 1;
721 }
c9df406f 722
4df89bd5 723 if (tag_bytes & 4)
e32b6617 724 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 725 if (tag_bytes & 8)
e32b6617 726 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 727
728 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
729 GEN_IP_V4_CHECKSUM |
730 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 731
c9df406f
LB		 732 switch (ip_hdr(skb)->protocol) {
733 case IPPROTO_UDP:
cc9754b3 734 cmd_sts |= UDP_FRAME;
4df89bd5 735 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 736 break;
737 case IPPROTO_TCP:
4df89bd5 738 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 739 break;
740 default:
741 BUG();
742 }
743 } else {
4df89bd5 744no_csum:
c9df406f 745 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 746 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 747 }
748
4df89bd5
LB		 749 tx_index = txq_alloc_desc_index(txq);
750 desc = &txq->tx_desc_area[tx_index];
751
752 if (nr_frags) {
753 txq_submit_frag_skb(txq, skb);
754 length = skb_headlen(skb);
755 } else {
756 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
757 length = skb->len;
758 }
759
760 desc->l4i_chk = l4i_chk;
761 desc->byte_cnt = length;
762 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
763
99ab08e0
LB		 764 __skb_queue_tail(&txq->tx_skb, skb);
765
c9df406f
LB		 766 /* ensure all other descriptors are written before first cmd_sts */
767 wmb();
768 desc->cmd_sts = cmd_sts;
769
1fa38c58
LB		 770 /* clear TX_END status */
771 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 772
c9df406f
LB		 773 /* ensure all descriptors are written before poking hardware */
774 wmb();
13d64285 775 txq_enable(txq);
c9df406f 776
13d64285 777 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 778
779 return 0;
1da177e4 780}
1da177e4 781
fc32b0e2 782static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 783{
e5371493 784 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 785 int queue;
13d64285 786 struct tx_queue *txq;
e5ef1de1 787 struct netdev_queue *nq;
afdb57a2 788
8fd89211
LB		 789 queue = skb_get_queue_mapping(skb);
790 txq = mp->txq + queue;
791 nq = netdev_get_tx_queue(dev, queue);
792
c9df406f 793 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 794 txq->tx_dropped++;
fc32b0e2
LB		 795 dev_printk(KERN_DEBUG, &dev->dev,
796 "failed to linearize skb with tiny "
797 "unaligned fragment\n");
c9df406f
LB		 798 return NETDEV_TX_BUSY;
799 }
800
17cd0a59 801 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 802 if (net_ratelimit())
803 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 804 kfree_skb(skb);
805 return NETDEV_TX_OK;
c9df406f
LB		 806 }
807
4df89bd5
LB		 808 if (!txq_submit_skb(txq, skb)) {
809 int entries_left;
810
811 txq->tx_bytes += skb->len;
812 txq->tx_packets++;
813 dev->trans_start = jiffies;
c9df406f 814
4df89bd5
LB		 815 entries_left = txq->tx_ring_size - txq->tx_desc_count;
816 if (entries_left < MAX_SKB_FRAGS + 1)
817 netif_tx_stop_queue(nq);
818 }
c9df406f 819
c9df406f 820 return NETDEV_TX_OK;
1da177e4
LT		 821}
822
c9df406f 823
1fa38c58
LB		 824/* tx napi ******************************************************************/
825static void txq_kick(struct tx_queue *txq)
826{
827 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 828 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 829 u32 hw_desc_ptr;
830 u32 expected_ptr;
831
8fd89211 832 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 833
834 if (rdl(mp, TXQ_COMMAND(mp->port_num)) & (1 << txq->index))
835 goto out;
836
837 hw_desc_ptr = rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index));
838 expected_ptr = (u32)txq->tx_desc_dma +
839 txq->tx_curr_desc * sizeof(struct tx_desc);
840
841 if (hw_desc_ptr != expected_ptr)
842 txq_enable(txq);
843
844out:
8fd89211 845 __netif_tx_unlock(nq);
1fa38c58
LB		 846
847 mp->work_tx_end &= ~(1 << txq->index);
848}
849
850static int txq_reclaim(struct tx_queue *txq, int budget, int force)
851{
852 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 853 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 854 int reclaimed;
855
8fd89211 856 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 857
858 reclaimed = 0;
859 while (reclaimed < budget && txq->tx_desc_count > 0) {
860 int tx_index;
861 struct tx_desc *desc;
862 u32 cmd_sts;
863 struct sk_buff *skb;
1fa38c58
LB		 864
865 tx_index = txq->tx_used_desc;
866 desc = &txq->tx_desc_area[tx_index];
867 cmd_sts = desc->cmd_sts;
868
869 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
870 if (!force)
871 break;
872 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
873 }
874
875 txq->tx_used_desc = tx_index + 1;
876 if (txq->tx_used_desc == txq->tx_ring_size)
877 txq->tx_used_desc = 0;
878
879 reclaimed++;
880 txq->tx_desc_count--;
881
99ab08e0
LB		 882 skb = NULL;
883 if (cmd_sts & TX_LAST_DESC)
884 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 885
886 if (cmd_sts & ERROR_SUMMARY) {
887 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
888 mp->dev->stats.tx_errors++;
889 }
890
a418950c
LB		 891 if (cmd_sts & TX_FIRST_DESC) {
892 dma_unmap_single(NULL, desc->buf_ptr,
893 desc->byte_cnt, DMA_TO_DEVICE);
894 } else {
895 dma_unmap_page(NULL, desc->buf_ptr,
896 desc->byte_cnt, DMA_TO_DEVICE);
897 }
1fa38c58 898
2bcb4b0f
LB		 899 if (skb != NULL) {
900 if (skb_queue_len(&mp->rx_recycle) <
901 mp->default_rx_ring_size &&
11b4aa03
LB		 902 skb_recycle_check(skb, mp->skb_size +
903 dma_get_cache_alignment() - 1))
2bcb4b0f
LB		 904 __skb_queue_head(&mp->rx_recycle, skb);
905 else
906 dev_kfree_skb(skb);
907 }
1fa38c58
LB		 908 }
909
8fd89211
LB		 910 __netif_tx_unlock(nq);
911
1fa38c58
LB		 912 if (reclaimed < budget)
913 mp->work_tx &= ~(1 << txq->index);
914
1fa38c58
LB		 915 return reclaimed;
916}
917
918
89df5fdc
LB		 919/* tx rate control **********************************************************/
920/*
921 * Set total maximum TX rate (shared by all TX queues for this port)
922 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
923 */
924static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
925{
926 int token_rate;
927 int mtu;
928 int bucket_size;
929
930 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
931 if (token_rate > 1023)
932 token_rate = 1023;
933
934 mtu = (mp->dev->mtu + 255) >> 8;
935 if (mtu > 63)
936 mtu = 63;
937
938 bucket_size = (burst + 255) >> 8;
939 if (bucket_size > 65535)
940 bucket_size = 65535;
941
457b1d5a
LB		 942 switch (mp->shared->tx_bw_control) {
943 case TX_BW_CONTROL_OLD_LAYOUT:
1e881592
LB		 944 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
945 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
946 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
457b1d5a
LB		 947 break;
948 case TX_BW_CONTROL_NEW_LAYOUT:
949 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
950 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
951 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
952 break;
1e881592 953 }
89df5fdc
LB		 954}
955
956static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
957{
958 struct mv643xx_eth_private *mp = txq_to_mp(txq);
959 int token_rate;
960 int bucket_size;
961
962 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
963 if (token_rate > 1023)
964 token_rate = 1023;
965
966 bucket_size = (burst + 255) >> 8;
967 if (bucket_size > 65535)
968 bucket_size = 65535;
969
3d6b35bc
LB		 970 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
971 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 972 (bucket_size << 10) | token_rate);
973}
974
975static void txq_set_fixed_prio_mode(struct tx_queue *txq)
976{
977 struct mv643xx_eth_private *mp = txq_to_mp(txq);
978 int off;
979 u32 val;
980
981 /*
982 * Turn on fixed priority mode.
983 */
457b1d5a
LB		 984 off = 0;
985 switch (mp->shared->tx_bw_control) {
986 case TX_BW_CONTROL_OLD_LAYOUT:
1e881592 987 off = TXQ_FIX_PRIO_CONF(mp->port_num);
457b1d5a
LB		 988 break;
989 case TX_BW_CONTROL_NEW_LAYOUT:
990 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
991 break;
992 }
89df5fdc 993
457b1d5a
LB		 994 if (off) {
995 val = rdl(mp, off);
996 val |= 1 << txq->index;
997 wrl(mp, off, val);
998 }
89df5fdc
LB		 999}
1000
1001static void txq_set_wrr(struct tx_queue *txq, int weight)
1002{
1003 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1004 int off;
1005 u32 val;
1006
1007 /*
1008 * Turn off fixed priority mode.
1009 */
457b1d5a
LB		 1010 off = 0;
1011 switch (mp->shared->tx_bw_control) {
1012 case TX_BW_CONTROL_OLD_LAYOUT:
1e881592 1013 off = TXQ_FIX_PRIO_CONF(mp->port_num);
457b1d5a
LB		 1014 break;
1015 case TX_BW_CONTROL_NEW_LAYOUT:
1016 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
1017 break;
1018 }
89df5fdc 1019
457b1d5a
LB		 1020 if (off) {
1021 val = rdl(mp, off);
1022 val &= ~(1 << txq->index);
1023 wrl(mp, off, val);
89df5fdc 1024
457b1d5a
LB		 1025 /*
1026 * Configure WRR weight for this queue.
1027 */
1028 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc 1029
457b1d5a
LB		 1030 val = rdl(mp, off);
1031 val = (val & ~0xff) | (weight & 0xff);
1032 wrl(mp, off, val);
1033 }
89df5fdc
LB		 1034}
1035
1036
c9df406f 1037/* mii management interface *************************************************/
45c5d3bc
LB		 1038static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1039{
1040 struct mv643xx_eth_shared_private *msp = dev_id;
1041
1042 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1043 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1044 wake_up(&msp->smi_busy_wait);
1045 return IRQ_HANDLED;
1046 }
1047
1048 return IRQ_NONE;
1049}
c9df406f 1050
45c5d3bc 1051static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1052{
45c5d3bc
LB		 1053 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1054}
1da177e4 1055
45c5d3bc
LB		 1056static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1057{
1058 if (msp->err_interrupt == NO_IRQ) {
1059 int i;
c9df406f 1060
45c5d3bc
LB		 1061 for (i = 0; !smi_is_done(msp); i++) {
1062 if (i == 10)
1063 return -ETIMEDOUT;
1064 msleep(10);
c9df406f 1065 }
45c5d3bc
LB		 1066
1067 return 0;
1068 }
1069
ee04448d
LB		 1070 if (!smi_is_done(msp)) {
1071 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1072 msecs_to_jiffies(100));
1073 if (!smi_is_done(msp))
1074 return -ETIMEDOUT;
1075 }
45c5d3bc
LB		 1076
1077 return 0;
1078}
1079
ed94493f 1080static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1081{
ed94493f 1082 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1083 void __iomem *smi_reg = msp->base + SMI_REG;
1084 int ret;
1085
45c5d3bc 1086 if (smi_wait_ready(msp)) {
ed94493f
LB		 1087 printk("mv643xx_eth: SMI bus busy timeout\n");
1088 return -ETIMEDOUT;
1da177e4
LT		 1089 }
1090
fc32b0e2 1091 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1092
45c5d3bc 1093 if (smi_wait_ready(msp)) {
ed94493f
LB		 1094 printk("mv643xx_eth: SMI bus busy timeout\n");
1095 return -ETIMEDOUT;
45c5d3bc
LB		 1096 }
1097
1098 ret = readl(smi_reg);
1099 if (!(ret & SMI_READ_VALID)) {
ed94493f
LB		 1100 printk("mv643xx_eth: SMI bus read not valid\n");
1101 return -ENODEV;
c9df406f
LB		 1102 }
1103
ed94493f 1104 return ret & 0xffff;
1da177e4
LT		 1105}
1106
ed94493f 1107static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1108{
ed94493f 1109 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1110 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1111
45c5d3bc 1112 if (smi_wait_ready(msp)) {
ed94493f 1113 printk("mv643xx_eth: SMI bus busy timeout\n");
45c5d3bc 1114 return -ETIMEDOUT;
1da177e4
LT		 1115 }
1116
fc32b0e2 1117 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1118 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1119
ed94493f
LB		 1120 if (smi_wait_ready(msp)) {
1121 printk("mv643xx_eth: SMI bus busy timeout\n");
1122 return -ETIMEDOUT;
1123 }
45c5d3bc
LB		 1124
1125 return 0;
c9df406f 1126}
1da177e4 1127
c9df406f 1128
8fd89211
LB		 1129/* statistics ***************************************************************/
1130static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1131{
1132 struct mv643xx_eth_private *mp = netdev_priv(dev);
1133 struct net_device_stats *stats = &dev->stats;
1134 unsigned long tx_packets = 0;
1135 unsigned long tx_bytes = 0;
1136 unsigned long tx_dropped = 0;
1137 int i;
1138
1139 for (i = 0; i < mp->txq_count; i++) {
1140 struct tx_queue *txq = mp->txq + i;
1141
1142 tx_packets += txq->tx_packets;
1143 tx_bytes += txq->tx_bytes;
1144 tx_dropped += txq->tx_dropped;
1145 }
1146
1147 stats->tx_packets = tx_packets;
1148 stats->tx_bytes = tx_bytes;
1149 stats->tx_dropped = tx_dropped;
1150
1151 return stats;
1152}
1153
fc32b0e2 1154static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1155{
fc32b0e2 1156 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1157}
1158
fc32b0e2 1159static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1160{
fc32b0e2
LB		 1161 int i;
1162
1163 for (i = 0; i < 0x80; i += 4)
1164 mib_read(mp, i);
c9df406f 1165}
d0412d96 1166
fc32b0e2 1167static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1168{
e5371493 1169 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1170
4ff3495a 1171 spin_lock(&mp->mib_counters_lock);
fc32b0e2
LB		 1172 p->good_octets_received += mib_read(mp, 0x00);
1173 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1174 p->bad_octets_received += mib_read(mp, 0x08);
1175 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1176 p->good_frames_received += mib_read(mp, 0x10);
1177 p->bad_frames_received += mib_read(mp, 0x14);
1178 p->broadcast_frames_received += mib_read(mp, 0x18);
1179 p->multicast_frames_received += mib_read(mp, 0x1c);
1180 p->frames_64_octets += mib_read(mp, 0x20);
1181 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1182 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1183 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1184 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1185 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1186 p->good_octets_sent += mib_read(mp, 0x38);
1187 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1188 p->good_frames_sent += mib_read(mp, 0x40);
1189 p->excessive_collision += mib_read(mp, 0x44);
1190 p->multicast_frames_sent += mib_read(mp, 0x48);
1191 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1192 p->unrec_mac_control_received += mib_read(mp, 0x50);
1193 p->fc_sent += mib_read(mp, 0x54);
1194 p->good_fc_received += mib_read(mp, 0x58);
1195 p->bad_fc_received += mib_read(mp, 0x5c);
1196 p->undersize_received += mib_read(mp, 0x60);
1197 p->fragments_received += mib_read(mp, 0x64);
1198 p->oversize_received += mib_read(mp, 0x68);
1199 p->jabber_received += mib_read(mp, 0x6c);
1200 p->mac_receive_error += mib_read(mp, 0x70);
1201 p->bad_crc_event += mib_read(mp, 0x74);
1202 p->collision += mib_read(mp, 0x78);
1203 p->late_collision += mib_read(mp, 0x7c);
4ff3495a
LB		 1204 spin_unlock(&mp->mib_counters_lock);
1205
1206 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1207}
1208
1209static void mib_counters_timer_wrapper(unsigned long _mp)
1210{
1211 struct mv643xx_eth_private *mp = (void *)_mp;
1212
1213 mib_counters_update(mp);
d0412d96
JC		 1214}
1215
c9df406f
LB		 1216
1217/* ethtool ******************************************************************/
e5371493 1218struct mv643xx_eth_stats {
c9df406f
LB		 1219 char stat_string[ETH_GSTRING_LEN];
1220 int sizeof_stat;
16820054
LB		 1221 int netdev_off;
1222 int mp_off;
c9df406f
LB		 1223};
1224
16820054
LB		 1225#define SSTAT(m) \
1226 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1227 offsetof(struct net_device, stats.m), -1 }
1228
1229#define MIBSTAT(m) \
1230 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1231 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1232
1233static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1234 SSTAT(rx_packets),
1235 SSTAT(tx_packets),
1236 SSTAT(rx_bytes),
1237 SSTAT(tx_bytes),
1238 SSTAT(rx_errors),
1239 SSTAT(tx_errors),
1240 SSTAT(rx_dropped),
1241 SSTAT(tx_dropped),
1242 MIBSTAT(good_octets_received),
1243 MIBSTAT(bad_octets_received),
1244 MIBSTAT(internal_mac_transmit_err),
1245 MIBSTAT(good_frames_received),
1246 MIBSTAT(bad_frames_received),
1247 MIBSTAT(broadcast_frames_received),
1248 MIBSTAT(multicast_frames_received),
1249 MIBSTAT(frames_64_octets),
1250 MIBSTAT(frames_65_to_127_octets),
1251 MIBSTAT(frames_128_to_255_octets),
1252 MIBSTAT(frames_256_to_511_octets),
1253 MIBSTAT(frames_512_to_1023_octets),
1254 MIBSTAT(frames_1024_to_max_octets),
1255 MIBSTAT(good_octets_sent),
1256 MIBSTAT(good_frames_sent),
1257 MIBSTAT(excessive_collision),
1258 MIBSTAT(multicast_frames_sent),
1259 MIBSTAT(broadcast_frames_sent),
1260 MIBSTAT(unrec_mac_control_received),
1261 MIBSTAT(fc_sent),
1262 MIBSTAT(good_fc_received),
1263 MIBSTAT(bad_fc_received),
1264 MIBSTAT(undersize_received),
1265 MIBSTAT(fragments_received),
1266 MIBSTAT(oversize_received),
1267 MIBSTAT(jabber_received),
1268 MIBSTAT(mac_receive_error),
1269 MIBSTAT(bad_crc_event),
1270 MIBSTAT(collision),
1271 MIBSTAT(late_collision),
c9df406f
LB		 1272};
1273
e5371493 1274static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1275{
e5371493 1276 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1277 int err;
1278
ed94493f
LB		 1279 err = phy_read_status(mp->phy);
1280 if (err == 0)
1281 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1282
fc32b0e2
LB		 1283 /*
1284 * The MAC does not support 1000baseT_Half.
1285 */
d0412d96
JC		 1286 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1287 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1288
1289 return err;
1290}
1291
bedfe324
LB		 1292static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1293{
81600eea
LB		 1294 struct mv643xx_eth_private *mp = netdev_priv(dev);
1295 u32 port_status;
1296
1297 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1298
bedfe324
LB		 1299 cmd->supported = SUPPORTED_MII;
1300 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1301 switch (port_status & PORT_SPEED_MASK) {
1302 case PORT_SPEED_10:
1303 cmd->speed = SPEED_10;
1304 break;
1305 case PORT_SPEED_100:
1306 cmd->speed = SPEED_100;
1307 break;
1308 case PORT_SPEED_1000:
1309 cmd->speed = SPEED_1000;
1310 break;
1311 default:
1312 cmd->speed = -1;
1313 break;
1314 }
1315 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1316 cmd->port = PORT_MII;
1317 cmd->phy_address = 0;
1318 cmd->transceiver = XCVR_INTERNAL;
1319 cmd->autoneg = AUTONEG_DISABLE;
1320 cmd->maxtxpkt = 1;
1321 cmd->maxrxpkt = 1;
1322
1323 return 0;
1324}
1325
e5371493 1326static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1327{
e5371493 1328 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1329
fc32b0e2
LB		 1330 /*
1331 * The MAC does not support 1000baseT_Half.
1332 */
1333 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1334
ed94493f 1335 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1336}
1da177e4 1337
bedfe324
LB		 1338static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1339{
1340 return -EINVAL;
1341}
1342
fc32b0e2
LB		 1343static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1344 struct ethtool_drvinfo *drvinfo)
c9df406f 1345{
e5371493
LB		 1346 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1347 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1348 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1349 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1350 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1351}
1da177e4 1352
fc32b0e2 1353static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1354{
e5371493 1355 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1356
ed94493f 1357 return genphy_restart_aneg(mp->phy);
c9df406f 1358}
1da177e4 1359
bedfe324
LB		 1360static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1361{
1362 return -EINVAL;
1363}
1364
c9df406f
LB		 1365static u32 mv643xx_eth_get_link(struct net_device *dev)
1366{
ed94493f 1367 return !!netif_carrier_ok(dev);
bedfe324
LB		 1368}
1369
fc32b0e2
LB		 1370static void mv643xx_eth_get_strings(struct net_device *dev,
1371 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1372{
1373 int i;
1da177e4 1374
fc32b0e2
LB		 1375 if (stringset == ETH_SS_STATS) {
1376 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1377 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1378 mv643xx_eth_stats[i].stat_string,
e5371493 1379 ETH_GSTRING_LEN);
c9df406f 1380 }
c9df406f
LB		 1381 }
1382}
1da177e4 1383
fc32b0e2
LB		 1384static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1385 struct ethtool_stats *stats,
1386 uint64_t *data)
c9df406f 1387{
b9873841 1388 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1389 int i;
1da177e4 1390
8fd89211 1391 mv643xx_eth_get_stats(dev);
fc32b0e2 1392 mib_counters_update(mp);
1da177e4 1393
16820054
LB		 1394 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1395 const struct mv643xx_eth_stats *stat;
1396 void *p;
1397
1398 stat = mv643xx_eth_stats + i;
1399
1400 if (stat->netdev_off >= 0)
1401 p = ((void *)mp->dev) + stat->netdev_off;
1402 else
1403 p = ((void *)mp) + stat->mp_off;
1404
1405 data[i] = (stat->sizeof_stat == 8) ?
1406 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1407 }
c9df406f 1408}
1da177e4 1409
fc32b0e2 1410static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1411{
fc32b0e2 1412 if (sset == ETH_SS_STATS)
16820054 1413 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1414
1415 return -EOPNOTSUPP;
c9df406f 1416}
1da177e4 1417
e5371493 1418static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1419 .get_settings = mv643xx_eth_get_settings,
1420 .set_settings = mv643xx_eth_set_settings,
1421 .get_drvinfo = mv643xx_eth_get_drvinfo,
1422 .nway_reset = mv643xx_eth_nway_reset,
1423 .get_link = mv643xx_eth_get_link,
c9df406f 1424 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1425 .get_strings = mv643xx_eth_get_strings,
1426 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1427 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1428};
1da177e4 1429
bedfe324
LB		 1430static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1431 .get_settings = mv643xx_eth_get_settings_phyless,
1432 .set_settings = mv643xx_eth_set_settings_phyless,
1433 .get_drvinfo = mv643xx_eth_get_drvinfo,
1434 .nway_reset = mv643xx_eth_nway_reset_phyless,
ed94493f 1435 .get_link = mv643xx_eth_get_link,
bedfe324
LB		 1436 .set_sg = ethtool_op_set_sg,
1437 .get_strings = mv643xx_eth_get_strings,
1438 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1439 .get_sset_count = mv643xx_eth_get_sset_count,
1440};
1441
bea3348e 1442
c9df406f 1443/* address handling *********************************************************/
5daffe94 1444static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1445{
c9df406f
LB		 1446 unsigned int mac_h;
1447 unsigned int mac_l;
1da177e4 1448
fc32b0e2
LB		 1449 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1450 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1451
5daffe94
LB		 1452 addr[0] = (mac_h >> 24) & 0xff;
1453 addr[1] = (mac_h >> 16) & 0xff;
1454 addr[2] = (mac_h >> 8) & 0xff;
1455 addr[3] = mac_h & 0xff;
1456 addr[4] = (mac_l >> 8) & 0xff;
1457 addr[5] = mac_l & 0xff;
c9df406f 1458}
1da177e4 1459
e5371493 1460static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1461{
fc32b0e2 1462 int i;
1da177e4 1463
fc32b0e2
LB		 1464 for (i = 0; i < 0x100; i += 4) {
1465 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1466 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1467 }
fc32b0e2
LB		 1468
1469 for (i = 0; i < 0x10; i += 4)
1470 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1471}
d0412d96 1472
e5371493 1473static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1474 int table, unsigned char entry)
c9df406f
LB		 1475{
1476 unsigned int table_reg;
ab4384a6 1477
c9df406f 1478 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1479 table_reg = rdl(mp, table + (entry & 0xfc));
1480 table_reg |= 0x01 << (8 * (entry & 3));
1481 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1482}
1483
5daffe94 1484static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1485{
c9df406f
LB		 1486 unsigned int mac_h;
1487 unsigned int mac_l;
1488 int table;
1da177e4 1489
fc32b0e2
LB		 1490 mac_l = (addr[4] << 8) | addr[5];
1491 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1492
fc32b0e2
LB		 1493 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1494 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1495
fc32b0e2 1496 table = UNICAST_TABLE(mp->port_num);
5daffe94 1497 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1498}
1499
fc32b0e2 1500static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1501{
e5371493 1502 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1503
fc32b0e2
LB		 1504 /* +2 is for the offset of the HW addr type */
1505 memcpy(dev->dev_addr, addr + 2, 6);
1506
cc9754b3
LB		 1507 init_mac_tables(mp);
1508 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1509
1510 return 0;
1511}
1512
69876569
LB		 1513static int addr_crc(unsigned char *addr)
1514{
1515 int crc = 0;
1516 int i;
1517
1518 for (i = 0; i < 6; i++) {
1519 int j;
1520
1521 crc = (crc ^ addr[i]) << 8;
1522 for (j = 7; j >= 0; j--) {
1523 if (crc & (0x100 << j))
1524 crc ^= 0x107 << j;
1525 }
1526 }
1527
1528 return crc;
1529}
1530
fc32b0e2 1531static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1532{
fc32b0e2
LB		 1533 struct mv643xx_eth_private *mp = netdev_priv(dev);
1534 u32 port_config;
1535 struct dev_addr_list *addr;
1536 int i;
c8aaea25 1537
fc32b0e2
LB		 1538 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1539 if (dev->flags & IFF_PROMISC)
1540 port_config |= UNICAST_PROMISCUOUS_MODE;
1541 else
1542 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1543 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1544
fc32b0e2
LB		 1545 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1546 int port_num = mp->port_num;
1547 u32 accept = 0x01010101;
c8aaea25 1548
fc32b0e2
LB		 1549 for (i = 0; i < 0x100; i += 4) {
1550 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1551 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1552 }
1553 return;
1554 }
c8aaea25 1555
fc32b0e2
LB		 1556 for (i = 0; i < 0x100; i += 4) {
1557 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1558 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1559 }
1560
fc32b0e2
LB		 1561 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1562 u8 *a = addr->da_addr;
1563 int table;
324ff2c1 1564
fc32b0e2
LB		 1565 if (addr->da_addrlen != 6)
1566 continue;
1da177e4 1567
fc32b0e2
LB		 1568 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1569 table = SPECIAL_MCAST_TABLE(mp->port_num);
1570 set_filter_table_entry(mp, table, a[5]);
1571 } else {
1572 int crc = addr_crc(a);
1da177e4 1573
fc32b0e2
LB		 1574 table = OTHER_MCAST_TABLE(mp->port_num);
1575 set_filter_table_entry(mp, table, crc);
1576 }
1577 }
c9df406f 1578}
c8aaea25 1579
c8aaea25 1580
c9df406f 1581/* rx/tx queue initialisation ***********************************************/
64da80a2 1582static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1583{
64da80a2 1584 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1585 struct rx_desc *rx_desc;
1586 int size;
c9df406f
LB		 1587 int i;
1588
64da80a2
LB		 1589 rxq->index = index;
1590
8a578111
LB		 1591 rxq->rx_ring_size = mp->default_rx_ring_size;
1592
1593 rxq->rx_desc_count = 0;
1594 rxq->rx_curr_desc = 0;
1595 rxq->rx_used_desc = 0;
1596
1597 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1598
f7981c1c 1599 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1600 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1601 mp->rx_desc_sram_size);
1602 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1603 } else {
1604 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1605 &rxq->rx_desc_dma,
1606 GFP_KERNEL);
f7ea3337
PJ		 1607 }
1608
8a578111
LB		 1609 if (rxq->rx_desc_area == NULL) {
1610 dev_printk(KERN_ERR, &mp->dev->dev,
1611 "can't allocate rx ring (%d bytes)\n", size);
1612 goto out;
1613 }
1614 memset(rxq->rx_desc_area, 0, size);
1da177e4 1615
8a578111
LB		 1616 rxq->rx_desc_area_size = size;
1617 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1618 GFP_KERNEL);
1619 if (rxq->rx_skb == NULL) {
1620 dev_printk(KERN_ERR, &mp->dev->dev,
1621 "can't allocate rx skb ring\n");
1622 goto out_free;
1623 }
1624
1625 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1626 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1627 int nexti;
1628
1629 nexti = i + 1;
1630 if (nexti == rxq->rx_ring_size)
1631 nexti = 0;
1632
8a578111
LB		 1633 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1634 nexti * sizeof(struct rx_desc);
1635 }
1636
8a578111
LB		 1637 return 0;
1638
1639
1640out_free:
f7981c1c 1641 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1642 iounmap(rxq->rx_desc_area);
1643 else
1644 dma_free_coherent(NULL, size,
1645 rxq->rx_desc_area,
1646 rxq->rx_desc_dma);
1647
1648out:
1649 return -ENOMEM;
c9df406f 1650}
c8aaea25 1651
8a578111 1652static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1653{
8a578111
LB		 1654 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1655 int i;
1656
1657 rxq_disable(rxq);
c8aaea25 1658
8a578111
LB		 1659 for (i = 0; i < rxq->rx_ring_size; i++) {
1660 if (rxq->rx_skb[i]) {
1661 dev_kfree_skb(rxq->rx_skb[i]);
1662 rxq->rx_desc_count--;
1da177e4 1663 }
c8aaea25 1664 }
1da177e4 1665
8a578111
LB		 1666 if (rxq->rx_desc_count) {
1667 dev_printk(KERN_ERR, &mp->dev->dev,
1668 "error freeing rx ring -- %d skbs stuck\n",
1669 rxq->rx_desc_count);
1670 }
1671
f7981c1c 1672 if (rxq->index == 0 &&
64da80a2 1673 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1674 iounmap(rxq->rx_desc_area);
c9df406f 1675 else
8a578111
LB		 1676 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1677 rxq->rx_desc_area, rxq->rx_desc_dma);
1678
1679 kfree(rxq->rx_skb);
c9df406f 1680}
1da177e4 1681
3d6b35bc 1682static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1683{
3d6b35bc 1684 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1685 struct tx_desc *tx_desc;
1686 int size;
c9df406f 1687 int i;
1da177e4 1688
3d6b35bc
LB		 1689 txq->index = index;
1690
13d64285
LB		 1691 txq->tx_ring_size = mp->default_tx_ring_size;
1692
1693 txq->tx_desc_count = 0;
1694 txq->tx_curr_desc = 0;
1695 txq->tx_used_desc = 0;
1696
1697 size = txq->tx_ring_size * sizeof(struct tx_desc);
1698
f7981c1c 1699 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1700 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1701 mp->tx_desc_sram_size);
1702 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1703 } else {
1704 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1705 &txq->tx_desc_dma,
1706 GFP_KERNEL);
1707 }
1708
1709 if (txq->tx_desc_area == NULL) {
1710 dev_printk(KERN_ERR, &mp->dev->dev,
1711 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1712 return -ENOMEM;
c9df406f 1713 }
13d64285
LB		 1714 memset(txq->tx_desc_area, 0, size);
1715
1716 txq->tx_desc_area_size = size;
13d64285
LB		 1717
1718 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1719 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1720 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1721 int nexti;
1722
1723 nexti = i + 1;
1724 if (nexti == txq->tx_ring_size)
1725 nexti = 0;
6b368f68
LB		 1726
1727 txd->cmd_sts = 0;
1728 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1729 nexti * sizeof(struct tx_desc);
1730 }
1731
99ab08e0 1732 skb_queue_head_init(&txq->tx_skb);
c9df406f 1733
99ab08e0 1734 return 0;
c8aaea25 1735}
1da177e4 1736
13d64285 1737static void txq_deinit(struct tx_queue *txq)
c9df406f 1738{
13d64285 1739 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1740
13d64285 1741 txq_disable(txq);
1fa38c58 1742 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 1743
13d64285 1744 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1745
f7981c1c 1746 if (txq->index == 0 &&
3d6b35bc 1747 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1748 iounmap(txq->tx_desc_area);
c9df406f 1749 else
13d64285
LB		 1750 dma_free_coherent(NULL, txq->tx_desc_area_size,
1751 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 1752}
1da177e4 1753
1da177e4 1754
c9df406f 1755/* netdev ops and related ***************************************************/
1fa38c58
LB		 1756static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1757{
1758 u32 int_cause;
1759 u32 int_cause_ext;
1760
1761 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1762 (INT_TX_END | INT_RX | INT_EXT);
1763 if (int_cause == 0)
1764 return 0;
1765
1766 int_cause_ext = 0;
1767 if (int_cause & INT_EXT)
1768 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num));
1769
1770 int_cause &= INT_TX_END | INT_RX;
1771 if (int_cause) {
1772 wrl(mp, INT_CAUSE(mp->port_num), ~int_cause);
1773 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1774 ~(rdl(mp, TXQ_COMMAND(mp->port_num)) & 0xff);
1775 mp->work_rx |= (int_cause & INT_RX) >> 2;
1776 }
1777
1778 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1779 if (int_cause_ext) {
1780 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1781 if (int_cause_ext & INT_EXT_LINK_PHY)
1782 mp->work_link = 1;
1783 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1784 }
1785
1786 return 1;
1787}
1788
1789static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1790{
1791 struct net_device *dev = (struct net_device *)dev_id;
1792 struct mv643xx_eth_private *mp = netdev_priv(dev);
1793
1794 if (unlikely(!mv643xx_eth_collect_events(mp)))
1795 return IRQ_NONE;
1796
1797 wrl(mp, INT_MASK(mp->port_num), 0);
1798 napi_schedule(&mp->napi);
1799
1800 return IRQ_HANDLED;
1801}
1802
2f7eb47a
LB		 1803static void handle_link_event(struct mv643xx_eth_private *mp)
1804{
1805 struct net_device *dev = mp->dev;
1806 u32 port_status;
1807 int speed;
1808 int duplex;
1809 int fc;
1810
1811 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1812 if (!(port_status & LINK_UP)) {
1813 if (netif_carrier_ok(dev)) {
1814 int i;
1815
1816 printk(KERN_INFO "%s: link down\n", dev->name);
1817
1818 netif_carrier_off(dev);
2f7eb47a 1819
f7981c1c 1820 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 1821 struct tx_queue *txq = mp->txq + i;
1822
1fa38c58 1823 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 1824 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 1825 }
1826 }
1827 return;
1828 }
1829
1830 switch (port_status & PORT_SPEED_MASK) {
1831 case PORT_SPEED_10:
1832 speed = 10;
1833 break;
1834 case PORT_SPEED_100:
1835 speed = 100;
1836 break;
1837 case PORT_SPEED_1000:
1838 speed = 1000;
1839 break;
1840 default:
1841 speed = -1;
1842 break;
1843 }
1844 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1845 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1846
1847 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1848 "flow control %sabled\n", dev->name,
1849 speed, duplex ? "full" : "half",
1850 fc ? "en" : "dis");
1851
4fdeca3f 1852 if (!netif_carrier_ok(dev))
2f7eb47a 1853 netif_carrier_on(dev);
2f7eb47a
LB		 1854}
1855
1fa38c58 1856static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 1857{
1fa38c58
LB		 1858 struct mv643xx_eth_private *mp;
1859 int work_done;
ce4e2e45 1860
1fa38c58 1861 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 1862
1fa38c58
LB		 1863 mp->work_rx_refill |= mp->work_rx_oom;
1864 mp->work_rx_oom = 0;
1da177e4 1865
1fa38c58
LB		 1866 work_done = 0;
1867 while (work_done < budget) {
1868 u8 queue_mask;
1869 int queue;
1870 int work_tbd;
1871
1872 if (mp->work_link) {
1873 mp->work_link = 0;
1874 handle_link_event(mp);
1875 continue;
1876 }
1da177e4 1877
1fa38c58
LB		 1878 queue_mask = mp->work_tx | mp->work_tx_end |
1879 mp->work_rx | mp->work_rx_refill;
1880 if (!queue_mask) {
1881 if (mv643xx_eth_collect_events(mp))
1882 continue;
1883 break;
1884 }
1da177e4 1885
1fa38c58
LB		 1886 queue = fls(queue_mask) - 1;
1887 queue_mask = 1 << queue;
1888
1889 work_tbd = budget - work_done;
1890 if (work_tbd > 16)
1891 work_tbd = 16;
1892
1893 if (mp->work_tx_end & queue_mask) {
1894 txq_kick(mp->txq + queue);
1895 } else if (mp->work_tx & queue_mask) {
1896 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1897 txq_maybe_wake(mp->txq + queue);
1898 } else if (mp->work_rx & queue_mask) {
1899 work_done += rxq_process(mp->rxq + queue, work_tbd);
1900 } else if (mp->work_rx_refill & queue_mask) {
1901 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1902 } else {
1903 BUG();
1904 }
84dd619e 1905 }
fc32b0e2 1906
1fa38c58
LB		 1907 if (work_done < budget) {
1908 if (mp->work_rx_oom)
1909 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1910 napi_complete(napi);
1911 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
226bb6b7 1912 }
3d6b35bc 1913
1fa38c58
LB		 1914 return work_done;
1915}
8fa89bf5 1916
1fa38c58
LB		 1917static inline void oom_timer_wrapper(unsigned long data)
1918{
1919 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 1920
1fa38c58 1921 napi_schedule(&mp->napi);
1da177e4
LT		 1922}
1923
e5371493 1924static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1925{
45c5d3bc
LB		 1926 int data;
1927
ed94493f 1928 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 1929 if (data < 0)
1930 return;
1da177e4 1931
7f106c1d 1932 data |= BMCR_RESET;
ed94493f 1933 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 1934 return;
1da177e4 1935
c9df406f 1936 do {
ed94493f 1937 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 1938 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 1939}
1940
fc32b0e2 1941static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1942{
d0412d96 1943 u32 pscr;
8a578111 1944 int i;
1da177e4 1945
bedfe324
LB		 1946 /*
1947 * Perform PHY reset, if there is a PHY.
1948 */
ed94493f 1949 if (mp->phy != NULL) {
bedfe324
LB		 1950 struct ethtool_cmd cmd;
1951
1952 mv643xx_eth_get_settings(mp->dev, &cmd);
1953 phy_reset(mp);
1954 mv643xx_eth_set_settings(mp->dev, &cmd);
1955 }
1da177e4 1956
81600eea
LB		 1957 /*
1958 * Configure basic link parameters.
1959 */
1960 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1961
1962 pscr |= SERIAL_PORT_ENABLE;
1963 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1964
1965 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 1966 if (mp->phy == NULL)
81600eea
LB		 1967 pscr |= FORCE_LINK_PASS;
1968 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1969
1970 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1971
13d64285
LB		 1972 /*
1973 * Configure TX path and queues.
1974 */
89df5fdc 1975 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 1976 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 1977 struct tx_queue *txq = mp->txq + i;
13d64285 1978
6b368f68 1979 txq_reset_hw_ptr(txq);
89df5fdc
LB		 1980 txq_set_rate(txq, 1000000000, 16777216);
1981 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1982 }
1983
fc32b0e2
LB		 1984 /*
1985 * Add configured unicast address to address filter table.
1986 */
1987 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1988
d9a073ea
LB		 1989 /*
1990 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 1991 * frames to RX queue #0, and include the pseudo-header when
1992 * calculating receive checksums.
d9a073ea 1993 */
170e7108 1994 wrl(mp, PORT_CONFIG(mp->port_num), 0x02000000);
01999873 1995
376489a2
LB		 1996 /*
1997 * Treat BPDUs as normal multicasts, and disable partition mode.
1998 */
8a578111 1999 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 2000
8a578111 2001 /*
64da80a2 2002 * Enable the receive queues.
8a578111 2003 */
f7981c1c 2004 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2005 struct rx_queue *rxq = mp->rxq + i;
2006 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 2007 u32 addr;
1da177e4 2008
8a578111
LB		 2009 addr = (u32)rxq->rx_desc_dma;
2010 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2011 wrl(mp, off, addr);
1da177e4 2012
8a578111
LB		 2013 rxq_enable(rxq);
2014 }
1da177e4
LT		 2015}
2016
ffd86bbe 2017static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2018{
c9df406f 2019 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 2020 u32 val;
1da177e4 2021
773fc3ee
LB		 2022 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2023 if (mp->shared->extended_rx_coal_limit) {
2024 if (coal > 0xffff)
2025 coal = 0xffff;
2026 val &= ~0x023fff80;
2027 val |= (coal & 0x8000) << 10;
2028 val |= (coal & 0x7fff) << 7;
2029 } else {
2030 if (coal > 0x3fff)
2031 coal = 0x3fff;
2032 val &= ~0x003fff00;
2033 val |= (coal & 0x3fff) << 8;
2034 }
2035 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1da177e4
LT		 2036}
2037
ffd86bbe 2038static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 2039{
c9df406f 2040 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 2041
fc32b0e2
LB		 2042 if (coal > 0x3fff)
2043 coal = 0x3fff;
2044 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 2045}
2046
2bcb4b0f
LB		 2047static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2048{
2049 int skb_size;
2050
2051 /*
2052 * Reserve 2+14 bytes for an ethernet header (the hardware
2053 * automatically prepends 2 bytes of dummy data to each
2054 * received packet), 16 bytes for up to four VLAN tags, and
2055 * 4 bytes for the trailing FCS -- 36 bytes total.
2056 */
2057 skb_size = mp->dev->mtu + 36;
2058
2059 /*
2060 * Make sure that the skb size is a multiple of 8 bytes, as
2061 * the lower three bits of the receive descriptor's buffer
2062 * size field are ignored by the hardware.
2063 */
2064 mp->skb_size = (skb_size + 7) & ~7;
2065}
2066
c9df406f 2067static int mv643xx_eth_open(struct net_device *dev)
16e03018 2068{
e5371493 2069 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2070 int err;
64da80a2 2071 int i;
16e03018 2072
fc32b0e2
LB		 2073 wrl(mp, INT_CAUSE(mp->port_num), 0);
2074 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2075 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 2076
fc32b0e2 2077 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2078 IRQF_SHARED, dev->name, dev);
c9df406f 2079 if (err) {
fc32b0e2 2080 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2081 return -EAGAIN;
16e03018
DF		 2082 }
2083
fc32b0e2 2084 init_mac_tables(mp);
16e03018 2085
2bcb4b0f
LB		 2086 mv643xx_eth_recalc_skb_size(mp);
2087
2257e05c
LB		 2088 napi_enable(&mp->napi);
2089
2bcb4b0f
LB		 2090 skb_queue_head_init(&mp->rx_recycle);
2091
f7981c1c 2092 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2093 err = rxq_init(mp, i);
2094 if (err) {
2095 while (--i >= 0)
f7981c1c 2096 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2097 goto out;
2098 }
2099
1fa38c58 2100 rxq_refill(mp->rxq + i, INT_MAX);
2257e05c
LB		 2101 }
2102
1fa38c58 2103 if (mp->work_rx_oom) {
2257e05c
LB		 2104 mp->rx_oom.expires = jiffies + (HZ / 10);
2105 add_timer(&mp->rx_oom);
64da80a2 2106 }
8a578111 2107
f7981c1c 2108 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2109 err = txq_init(mp, i);
2110 if (err) {
2111 while (--i >= 0)
f7981c1c 2112 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2113 goto out_free;
2114 }
2115 }
16e03018 2116
2f7eb47a 2117 netif_carrier_off(dev);
2f7eb47a 2118
fc32b0e2 2119 port_start(mp);
16e03018 2120
ffd86bbe
LB		 2121 set_rx_coal(mp, 0);
2122 set_tx_coal(mp, 0);
16e03018 2123
befefe21 2124 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
226bb6b7 2125 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16e03018 2126
c9df406f
LB		 2127 return 0;
2128
13d64285 2129
fc32b0e2 2130out_free:
f7981c1c
LB		 2131 for (i = 0; i < mp->rxq_count; i++)
2132 rxq_deinit(mp->rxq + i);
fc32b0e2 2133out:
c9df406f
LB		 2134 free_irq(dev->irq, dev);
2135
2136 return err;
16e03018
DF		 2137}
2138
e5371493 2139static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2140{
fc32b0e2 2141 unsigned int data;
64da80a2 2142 int i;
1da177e4 2143
f7981c1c
LB		 2144 for (i = 0; i < mp->rxq_count; i++)
2145 rxq_disable(mp->rxq + i);
2146 for (i = 0; i < mp->txq_count; i++)
2147 txq_disable(mp->txq + i);
ae9ae064
LB		 2148
2149 while (1) {
2150 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2151
2152 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2153 break;
13d64285 2154 udelay(10);
ae9ae064 2155 }
1da177e4 2156
c9df406f 2157 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 2158 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2159 data &= ~(SERIAL_PORT_ENABLE |
2160 DO_NOT_FORCE_LINK_FAIL |
2161 FORCE_LINK_PASS);
2162 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 2163}
2164
c9df406f 2165static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2166{
e5371493 2167 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2168 int i;
1da177e4 2169
fc32b0e2
LB		 2170 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2171 rdl(mp, INT_MASK(mp->port_num));
1da177e4 2172
4ff3495a
LB		 2173 del_timer_sync(&mp->mib_counters_timer);
2174
c9df406f 2175 napi_disable(&mp->napi);
78fff83b 2176
2257e05c
LB		 2177 del_timer_sync(&mp->rx_oom);
2178
c9df406f 2179 netif_carrier_off(dev);
1da177e4 2180
fc32b0e2
LB		 2181 free_irq(dev->irq, dev);
2182
cc9754b3 2183 port_reset(mp);
8fd89211 2184 mv643xx_eth_get_stats(dev);
fc32b0e2 2185 mib_counters_update(mp);
1da177e4 2186
2bcb4b0f
LB		 2187 skb_queue_purge(&mp->rx_recycle);
2188
f7981c1c
LB		 2189 for (i = 0; i < mp->rxq_count; i++)
2190 rxq_deinit(mp->rxq + i);
2191 for (i = 0; i < mp->txq_count; i++)
2192 txq_deinit(mp->txq + i);
1da177e4 2193
c9df406f 2194 return 0;
1da177e4
LT		 2195}
2196
fc32b0e2 2197static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2198{
e5371493 2199 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2200
ed94493f
LB		 2201 if (mp->phy != NULL)
2202 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
bedfe324
LB		 2203
2204 return -EOPNOTSUPP;
1da177e4
LT		 2205}
2206
c9df406f 2207static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2208{
89df5fdc
LB		 2209 struct mv643xx_eth_private *mp = netdev_priv(dev);
2210
fc32b0e2 2211 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2212 return -EINVAL;
1da177e4 2213
c9df406f 2214 dev->mtu = new_mtu;
2bcb4b0f 2215 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2216 tx_set_rate(mp, 1000000000, 16777216);
2217
c9df406f
LB		 2218 if (!netif_running(dev))
2219 return 0;
1da177e4 2220
c9df406f
LB		 2221 /*
2222 * Stop and then re-open the interface. This will allocate RX
2223 * skbs of the new MTU.
2224 * There is a possible danger that the open will not succeed,
fc32b0e2 2225 * due to memory being full.
c9df406f
LB		 2226 */
2227 mv643xx_eth_stop(dev);
2228 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2229 dev_printk(KERN_ERR, &dev->dev,
2230 "fatal error on re-opening device after "
2231 "MTU change\n");
c9df406f
LB		 2232 }
2233
2234 return 0;
1da177e4
LT		 2235}
2236
fc32b0e2 2237static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2238{
fc32b0e2 2239 struct mv643xx_eth_private *mp;
1da177e4 2240
fc32b0e2
LB		 2241 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2242 if (netif_running(mp->dev)) {
e5ef1de1 2243 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2244 port_reset(mp);
2245 port_start(mp);
e5ef1de1 2246 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2247 }
c9df406f
LB		 2248}
2249
c9df406f 2250static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2251{
e5371493 2252 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2253
fc32b0e2 2254 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2255
c9df406f 2256 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2257}
2258
c9df406f 2259#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2260static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2261{
fc32b0e2 2262 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2263
fc32b0e2
LB		 2264 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2265 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2266
fc32b0e2 2267 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2268
f2ca60f2 2269 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2270}
c9df406f 2271#endif
9f8dd319 2272
9f8dd319 2273
c9df406f 2274/* platform glue ************************************************************/
e5371493
LB		 2275static void
2276mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2277 struct mbus_dram_target_info *dram)
c9df406f 2278{
cc9754b3 2279 void __iomem *base = msp->base;
c9df406f
LB		 2280 u32 win_enable;
2281 u32 win_protect;
2282 int i;
9f8dd319 2283
c9df406f
LB		 2284 for (i = 0; i < 6; i++) {
2285 writel(0, base + WINDOW_BASE(i));
2286 writel(0, base + WINDOW_SIZE(i));
2287 if (i < 4)
2288 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2289 }
2290
c9df406f
LB		 2291 win_enable = 0x3f;
2292 win_protect = 0;
2293
2294 for (i = 0; i < dram->num_cs; i++) {
2295 struct mbus_dram_window *cs = dram->cs + i;
2296
2297 writel((cs->base & 0xffff0000) |
2298 (cs->mbus_attr << 8) |
2299 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2300 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2301
2302 win_enable &= ~(1 << i);
2303 win_protect |= 3 << (2 * i);
2304 }
2305
2306 writel(win_enable, base + WINDOW_BAR_ENABLE);
2307 msp->win_protect = win_protect;
9f8dd319
DF		 2308}
2309
773fc3ee
LB		 2310static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2311{
2312 /*
2313 * Check whether we have a 14-bit coal limit field in bits
2314 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2315 * SDMA config register.
2316 */
2317 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2318 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2319 msp->extended_rx_coal_limit = 1;
2320 else
2321 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2322
2323 /*
457b1d5a
LB		 2324 * Check whether the MAC supports TX rate control, and if
2325 * yes, whether its associated registers are in the old or
2326 * the new place.
1e881592
LB		 2327 */
2328 writel(1, msp->base + TX_BW_MTU_MOVED(0));
457b1d5a
LB		 2329 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1) {
2330 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2331 } else {
2332 writel(7, msp->base + TX_BW_RATE(0));
2333 if (readl(msp->base + TX_BW_RATE(0)) & 7)
2334 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2335 else
2336 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2337 }
773fc3ee
LB		 2338}
2339
c9df406f 2340static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2341{
e5371493 2342 static int mv643xx_eth_version_printed = 0;
c9df406f 2343 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2344 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2345 struct resource *res;
2346 int ret;
9f8dd319 2347
e5371493 2348 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2349 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2350 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2351
c9df406f
LB		 2352 ret = -EINVAL;
2353 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2354 if (res == NULL)
2355 goto out;
9f8dd319 2356
c9df406f
LB		 2357 ret = -ENOMEM;
2358 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2359 if (msp == NULL)
2360 goto out;
2361 memset(msp, 0, sizeof(*msp));
2362
cc9754b3
LB		 2363 msp->base = ioremap(res->start, res->end - res->start + 1);
2364 if (msp->base == NULL)
c9df406f
LB		 2365 goto out_free;
2366
ed94493f
LB		 2367 /*
2368 * Set up and register SMI bus.
2369 */
2370 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2371 msp->smi_bus = mdiobus_alloc();
2372 if (msp->smi_bus == NULL)
ed94493f 2373 goto out_unmap;
298cf9be
LB		 2374
2375 msp->smi_bus->priv = msp;
2376 msp->smi_bus->name = "mv643xx_eth smi";
2377 msp->smi_bus->read = smi_bus_read;
2378 msp->smi_bus->write = smi_bus_write,
2379 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2380 msp->smi_bus->parent = &pdev->dev;
2381 msp->smi_bus->phy_mask = 0xffffffff;
2382 if (mdiobus_register(msp->smi_bus) < 0)
2383 goto out_free_mii_bus;
ed94493f
LB		 2384 msp->smi = msp;
2385 } else {
fc0eb9f2 2386 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2387 }
c9df406f 2388
45c5d3bc
LB		 2389 msp->err_interrupt = NO_IRQ;
2390 init_waitqueue_head(&msp->smi_busy_wait);
2391
2392 /*
2393 * Check whether the error interrupt is hooked up.
2394 */
2395 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2396 if (res != NULL) {
2397 int err;
2398
2399 err = request_irq(res->start, mv643xx_eth_err_irq,
2400 IRQF_SHARED, "mv643xx_eth", msp);
2401 if (!err) {
2402 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2403 msp->err_interrupt = res->start;
2404 }
2405 }
2406
c9df406f
LB		 2407 /*
2408 * (Re-)program MBUS remapping windows if we are asked to.
2409 */
2410 if (pd != NULL && pd->dram != NULL)
2411 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2412
fc32b0e2
LB		 2413 /*
2414 * Detect hardware parameters.
2415 */
2416 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2417 infer_hw_params(msp);
fc32b0e2
LB		 2418
2419 platform_set_drvdata(pdev, msp);
2420
c9df406f
LB		 2421 return 0;
2422
298cf9be
LB		 2423out_free_mii_bus:
2424 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2425out_unmap:
2426 iounmap(msp->base);
c9df406f
LB		 2427out_free:
2428 kfree(msp);
2429out:
2430 return ret;
2431}
2432
2433static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2434{
e5371493 2435 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2436 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2437
298cf9be 2438 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be 2439 mdiobus_unregister(msp->smi_bus);
bcb3336c 2440 mdiobus_free(msp->smi_bus);
298cf9be 2441 }
45c5d3bc
LB		 2442 if (msp->err_interrupt != NO_IRQ)
2443 free_irq(msp->err_interrupt, msp);
cc9754b3 2444 iounmap(msp->base);
c9df406f
LB		 2445 kfree(msp);
2446
2447 return 0;
9f8dd319
DF		 2448}
2449
c9df406f 2450static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2451 .probe = mv643xx_eth_shared_probe,
2452 .remove = mv643xx_eth_shared_remove,
c9df406f 2453 .driver = {
fc32b0e2 2454 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2455 .owner = THIS_MODULE,
2456 },
2457};
2458
e5371493 2459static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2460{
c9df406f 2461 int addr_shift = 5 * mp->port_num;
fc32b0e2 2462 u32 data;
1da177e4 2463
fc32b0e2
LB		 2464 data = rdl(mp, PHY_ADDR);
2465 data &= ~(0x1f << addr_shift);
2466 data |= (phy_addr & 0x1f) << addr_shift;
2467 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2468}
2469
e5371493 2470static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2471{
fc32b0e2
LB		 2472 unsigned int data;
2473
2474 data = rdl(mp, PHY_ADDR);
2475
2476 return (data >> (5 * mp->port_num)) & 0x1f;
2477}
2478
2479static void set_params(struct mv643xx_eth_private *mp,
2480 struct mv643xx_eth_platform_data *pd)
2481{
2482 struct net_device *dev = mp->dev;
2483
2484 if (is_valid_ether_addr(pd->mac_addr))
2485 memcpy(dev->dev_addr, pd->mac_addr, 6);
2486 else
2487 uc_addr_get(mp, dev->dev_addr);
2488
fc32b0e2
LB		 2489 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2490 if (pd->rx_queue_size)
2491 mp->default_rx_ring_size = pd->rx_queue_size;
2492 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2493 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2494
f7981c1c 2495 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2496
fc32b0e2
LB		 2497 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2498 if (pd->tx_queue_size)
2499 mp->default_tx_ring_size = pd->tx_queue_size;
2500 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2501 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2502
f7981c1c 2503 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2504}
2505
ed94493f
LB		 2506static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2507 int phy_addr)
1da177e4 2508{
298cf9be 2509 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2510 struct phy_device *phydev;
2511 int start;
2512 int num;
2513 int i;
45c5d3bc 2514
ed94493f
LB		 2515 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2516 start = phy_addr_get(mp) & 0x1f;
2517 num = 32;
2518 } else {
2519 start = phy_addr & 0x1f;
2520 num = 1;
2521 }
45c5d3bc 2522
ed94493f
LB		 2523 phydev = NULL;
2524 for (i = 0; i < num; i++) {
2525 int addr = (start + i) & 0x1f;
fc32b0e2 2526
ed94493f
LB		 2527 if (bus->phy_map[addr] == NULL)
2528 mdiobus_scan(bus, addr);
1da177e4 2529
ed94493f
LB		 2530 if (phydev == NULL) {
2531 phydev = bus->phy_map[addr];
2532 if (phydev != NULL)
2533 phy_addr_set(mp, addr);
2534 }
2535 }
1da177e4 2536
ed94493f 2537 return phydev;
1da177e4
LT		 2538}
2539
ed94493f 2540static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2541{
ed94493f 2542 struct phy_device *phy = mp->phy;
c28a4f89 2543
fc32b0e2
LB		 2544 phy_reset(mp);
2545
ed94493f
LB		 2546 phy_attach(mp->dev, phy->dev.bus_id, 0, PHY_INTERFACE_MODE_GMII);
2547
2548 if (speed == 0) {
2549 phy->autoneg = AUTONEG_ENABLE;
2550 phy->speed = 0;
2551 phy->duplex = 0;
2552 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2553 } else {
ed94493f
LB		 2554 phy->autoneg = AUTONEG_DISABLE;
2555 phy->advertising = 0;
2556 phy->speed = speed;
2557 phy->duplex = duplex;
c9df406f 2558 }
ed94493f 2559 phy_start_aneg(phy);
c28a4f89
JC		 2560}
2561
81600eea
LB		 2562static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2563{
2564 u32 pscr;
2565
2566 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2567 if (pscr & SERIAL_PORT_ENABLE) {
2568 pscr &= ~SERIAL_PORT_ENABLE;
2569 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2570 }
2571
2572 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2573 if (mp->phy == NULL) {
81600eea
LB		 2574 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2575 if (speed == SPEED_1000)
2576 pscr |= SET_GMII_SPEED_TO_1000;
2577 else if (speed == SPEED_100)
2578 pscr |= SET_MII_SPEED_TO_100;
2579
2580 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2581
2582 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2583 if (duplex == DUPLEX_FULL)
2584 pscr |= SET_FULL_DUPLEX_MODE;
2585 }
2586
2587 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2588}
2589
c9df406f 2590static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2591{
c9df406f 2592 struct mv643xx_eth_platform_data *pd;
e5371493 2593 struct mv643xx_eth_private *mp;
c9df406f 2594 struct net_device *dev;
c9df406f 2595 struct resource *res;
c9df406f 2596 DECLARE_MAC_BUF(mac);
fc32b0e2 2597 int err;
1da177e4 2598
c9df406f
LB		 2599 pd = pdev->dev.platform_data;
2600 if (pd == NULL) {
fc32b0e2
LB		 2601 dev_printk(KERN_ERR, &pdev->dev,
2602 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2603 return -ENODEV;
2604 }
1da177e4 2605
c9df406f 2606 if (pd->shared == NULL) {
fc32b0e2
LB		 2607 dev_printk(KERN_ERR, &pdev->dev,
2608 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2609 return -ENODEV;
2610 }
8f518703 2611
e5ef1de1 2612 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2613 if (!dev)
2614 return -ENOMEM;
1da177e4 2615
c9df406f 2616 mp = netdev_priv(dev);
fc32b0e2
LB		 2617 platform_set_drvdata(pdev, mp);
2618
2619 mp->shared = platform_get_drvdata(pd->shared);
2620 mp->port_num = pd->port_number;
2621
c9df406f 2622 mp->dev = dev;
78fff83b 2623
fc32b0e2 2624 set_params(mp, pd);
e5ef1de1 2625 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2626
ed94493f
LB		 2627 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2628 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2629
ed94493f
LB		 2630 if (mp->phy != NULL) {
2631 phy_init(mp, pd->speed, pd->duplex);
bedfe324
LB		 2632 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2633 } else {
2634 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2635 }
ed94493f 2636
81600eea 2637 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2638
4ff3495a
LB		 2639
2640 mib_counters_clear(mp);
2641
2642 init_timer(&mp->mib_counters_timer);
2643 mp->mib_counters_timer.data = (unsigned long)mp;
2644 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2645 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2646 add_timer(&mp->mib_counters_timer);
2647
2648 spin_lock_init(&mp->mib_counters_lock);
2649
2650 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2651
2257e05c
LB		 2652 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2653
2654 init_timer(&mp->rx_oom);
2655 mp->rx_oom.data = (unsigned long)mp;
2656 mp->rx_oom.function = oom_timer_wrapper;
2657
fc32b0e2 2658
c9df406f
LB		 2659 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2660 BUG_ON(!res);
2661 dev->irq = res->start;
1da177e4 2662
8fd89211 2663 dev->get_stats = mv643xx_eth_get_stats;
fc32b0e2 2664 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2665 dev->open = mv643xx_eth_open;
2666 dev->stop = mv643xx_eth_stop;
c9df406f 2667 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2668 dev->set_mac_address = mv643xx_eth_set_mac_address;
2669 dev->do_ioctl = mv643xx_eth_ioctl;
2670 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2671 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2672#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2673 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2674#endif
c9df406f
LB		 2675 dev->watchdog_timeo = 2 * HZ;
2676 dev->base_addr = 0;
1da177e4 2677
c9df406f 2678 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2679 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2680
fc32b0e2 2681 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2682
c9df406f 2683 if (mp->shared->win_protect)
fc32b0e2 2684 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2685
c9df406f
LB		 2686 err = register_netdev(dev);
2687 if (err)
2688 goto out;
1da177e4 2689
fc32b0e2
LB		 2690 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2691 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2692
13d64285 2693 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2694 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2695
c9df406f 2696 return 0;
1da177e4 2697
c9df406f
LB		 2698out:
2699 free_netdev(dev);
1da177e4 2700
c9df406f 2701 return err;
1da177e4
LT		 2702}
2703
c9df406f 2704static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2705{
fc32b0e2 2706 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2707
fc32b0e2 2708 unregister_netdev(mp->dev);
ed94493f
LB		 2709 if (mp->phy != NULL)
2710 phy_detach(mp->phy);
c9df406f 2711 flush_scheduled_work();
fc32b0e2 2712 free_netdev(mp->dev);
c9df406f 2713
c9df406f 2714 platform_set_drvdata(pdev, NULL);
fc32b0e2 2715
c9df406f 2716 return 0;
1da177e4
LT		 2717}
2718
c9df406f 2719static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2720{
fc32b0e2 2721 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2722
c9df406f 2723 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2724 wrl(mp, INT_MASK(mp->port_num), 0);
2725 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2726
fc32b0e2
LB		 2727 if (netif_running(mp->dev))
2728 port_reset(mp);
d0412d96
JC		 2729}
2730
c9df406f 2731static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2732 .probe = mv643xx_eth_probe,
2733 .remove = mv643xx_eth_remove,
2734 .shutdown = mv643xx_eth_shutdown,
c9df406f 2735 .driver = {
fc32b0e2 2736 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2737 .owner = THIS_MODULE,
2738 },
2739};
2740
e5371493 2741static int __init mv643xx_eth_init_module(void)
d0412d96 2742{
c9df406f 2743 int rc;
d0412d96 2744
c9df406f
LB		 2745 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2746 if (!rc) {
2747 rc = platform_driver_register(&mv643xx_eth_driver);
2748 if (rc)
2749 platform_driver_unregister(&mv643xx_eth_shared_driver);
2750 }
fc32b0e2 2751
c9df406f 2752 return rc;
d0412d96 2753}
fc32b0e2 2754module_init(mv643xx_eth_init_module);
d0412d96 2755
e5371493 2756static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2757{
c9df406f
LB		 2758 platform_driver_unregister(&mv643xx_eth_driver);
2759 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2760}
e5371493 2761module_exit(mv643xx_eth_cleanup_module);
1da177e4 2762
45675bc6
LB		 2763MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2764 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2765MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2766MODULE_LICENSE("GPL");
c9df406f 2767MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2768MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux 6.x block layer and io_uring tree(s)