projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for_3.0/pm-fixes' of ssh://master.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
7542db8b
JP		 38#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
39
1da177e4
LT		 40#include <linux/init.h>
41#include <linux/dma-mapping.h>
b6298c22 42#include <linux/in.h>
c3efab8e 43#include <linux/ip.h>
1da177e4
LT		 44#include <linux/tcp.h>
45#include <linux/udp.h>
46#include <linux/etherdevice.h>
1da177e4
LT		 47#include <linux/delay.h>
48#include <linux/ethtool.h>
d052d1be 49#include <linux/platform_device.h>
fbd6a754
LB		 50#include <linux/module.h>
51#include <linux/kernel.h>
52#include <linux/spinlock.h>
53#include <linux/workqueue.h>
ed94493f 54#include <linux/phy.h>
fbd6a754 55#include <linux/mv643xx_eth.h>
10a9948d
LB		 56#include <linux/io.h>
57#include <linux/types.h>
eaf5d590 58#include <linux/inet_lro.h>
5a0e3ad6 59#include <linux/slab.h>
1da177e4 60#include <asm/system.h>
fbd6a754 61
e5371493 62static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 63static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 64
fbd6a754 65
fbd6a754
LB		 66/*
67 * Registers shared between all ports.
68 */
3cb4667c
LB		 69#define PHY_ADDR 0x0000
70#define SMI_REG 0x0004
45c5d3bc
LB		 71#define SMI_BUSY 0x10000000
72#define SMI_READ_VALID 0x08000000
73#define SMI_OPCODE_READ 0x04000000
74#define SMI_OPCODE_WRITE 0x00000000
75#define ERR_INT_CAUSE 0x0080
76#define ERR_INT_SMI_DONE 0x00000010
77#define ERR_INT_MASK 0x0084
3cb4667c
LB		 78#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
79#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
80#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
81#define WINDOW_BAR_ENABLE 0x0290
82#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 83
84/*
37a6084f
LB		 85 * Main per-port registers. These live at offset 0x0400 for
86 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 87 */
37a6084f 88#define PORT_CONFIG 0x0000
d9a073ea 89#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 90#define PORT_CONFIG_EXT 0x0004
91#define MAC_ADDR_LOW 0x0014
92#define MAC_ADDR_HIGH 0x0018
93#define SDMA_CONFIG 0x001c
becfad97
LB		 94#define TX_BURST_SIZE_16_64BIT 0x01000000
95#define TX_BURST_SIZE_4_64BIT 0x00800000
96#define BLM_TX_NO_SWAP 0x00000020
97#define BLM_RX_NO_SWAP 0x00000010
98#define RX_BURST_SIZE_16_64BIT 0x00000008
99#define RX_BURST_SIZE_4_64BIT 0x00000004
37a6084f 100#define PORT_SERIAL_CONTROL 0x003c
becfad97
LB		 101#define SET_MII_SPEED_TO_100 0x01000000
102#define SET_GMII_SPEED_TO_1000 0x00800000
103#define SET_FULL_DUPLEX_MODE 0x00200000
104#define MAX_RX_PACKET_9700BYTE 0x000a0000
105#define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
106#define DO_NOT_FORCE_LINK_FAIL 0x00000400
107#define SERIAL_PORT_CONTROL_RESERVED 0x00000200
108#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
109#define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
110#define FORCE_LINK_PASS 0x00000002
111#define SERIAL_PORT_ENABLE 0x00000001
37a6084f 112#define PORT_STATUS 0x0044
a2a41689 113#define TX_FIFO_EMPTY 0x00000400
ae9ae064 114#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 115#define PORT_SPEED_MASK 0x00000030
116#define PORT_SPEED_1000 0x00000010
117#define PORT_SPEED_100 0x00000020
118#define PORT_SPEED_10 0x00000000
119#define FLOW_CONTROL_ENABLED 0x00000008
120#define FULL_DUPLEX 0x00000004
81600eea 121#define LINK_UP 0x00000002
37a6084f
LB		 122#define TXQ_COMMAND 0x0048
123#define TXQ_FIX_PRIO_CONF 0x004c
124#define TX_BW_RATE 0x0050
125#define TX_BW_MTU 0x0058
126#define TX_BW_BURST 0x005c
127#define INT_CAUSE 0x0060
226bb6b7 128#define INT_TX_END 0x07f80000
e0ca8410 129#define INT_TX_END_0 0x00080000
befefe21 130#define INT_RX 0x000003fc
e0ca8410 131#define INT_RX_0 0x00000004
073a345c 132#define INT_EXT 0x00000002
37a6084f 133#define INT_CAUSE_EXT 0x0064
befefe21
LB		 134#define INT_EXT_LINK_PHY 0x00110000
135#define INT_EXT_TX 0x000000ff
37a6084f
LB		 136#define INT_MASK 0x0068
137#define INT_MASK_EXT 0x006c
138#define TX_FIFO_URGENT_THRESHOLD 0x0074
139#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
140#define TX_BW_RATE_MOVED 0x00e0
141#define TX_BW_MTU_MOVED 0x00e8
142#define TX_BW_BURST_MOVED 0x00ec
143#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
144#define RXQ_COMMAND 0x0280
145#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
146#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
147#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
148#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
149
150/*
151 * Misc per-port registers.
152 */
3cb4667c
LB		 153#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
154#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
155#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
156#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 157
2679a550
LB		 158
159/*
becfad97 160 * SDMA configuration register default value.
2679a550 161 */
fbd6a754
LB		 162#if defined(__BIG_ENDIAN)
163#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 164 (RX_BURST_SIZE_4_64BIT | \
165 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 166#elif defined(__LITTLE_ENDIAN)
167#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 168 (RX_BURST_SIZE_4_64BIT | \
169 BLM_RX_NO_SWAP | \
170 BLM_TX_NO_SWAP | \
171 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 172#else
173#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
174#endif
175
2beff77b
LB		 176
177/*
becfad97 178 * Misc definitions.
2beff77b 179 */
becfad97
LB		 180#define DEFAULT_RX_QUEUE_SIZE 128
181#define DEFAULT_TX_QUEUE_SIZE 256
7fd96ce4 182#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
fbd6a754 183
fbd6a754 184
7ca72a3b
LB		 185/*
186 * RX/TX descriptors.
fbd6a754
LB		 187 */
188#if defined(__BIG_ENDIAN)
cc9754b3 189struct rx_desc {
fbd6a754
LB		 190 u16 byte_cnt; /* Descriptor buffer byte count */
191 u16 buf_size; /* Buffer size */
192 u32 cmd_sts; /* Descriptor command status */
193 u32 next_desc_ptr; /* Next descriptor pointer */
194 u32 buf_ptr; /* Descriptor buffer pointer */
195};
196
cc9754b3 197struct tx_desc {
fbd6a754
LB		 198 u16 byte_cnt; /* buffer byte count */
199 u16 l4i_chk; /* CPU provided TCP checksum */
200 u32 cmd_sts; /* Command/status field */
201 u32 next_desc_ptr; /* Pointer to next descriptor */
202 u32 buf_ptr; /* pointer to buffer for this descriptor*/
203};
204#elif defined(__LITTLE_ENDIAN)
cc9754b3 205struct rx_desc {
fbd6a754
LB		 206 u32 cmd_sts; /* Descriptor command status */
207 u16 buf_size; /* Buffer size */
208 u16 byte_cnt; /* Descriptor buffer byte count */
209 u32 buf_ptr; /* Descriptor buffer pointer */
210 u32 next_desc_ptr; /* Next descriptor pointer */
211};
212
cc9754b3 213struct tx_desc {
fbd6a754
LB		 214 u32 cmd_sts; /* Command/status field */
215 u16 l4i_chk; /* CPU provided TCP checksum */
216 u16 byte_cnt; /* buffer byte count */
217 u32 buf_ptr; /* pointer to buffer for this descriptor*/
218 u32 next_desc_ptr; /* Pointer to next descriptor */
219};
220#else
221#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
222#endif
223
7ca72a3b 224/* RX & TX descriptor command */
cc9754b3 225#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 226
227/* RX & TX descriptor status */
cc9754b3 228#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 229
230/* RX descriptor status */
cc9754b3
LB		 231#define LAYER_4_CHECKSUM_OK 0x40000000
232#define RX_ENABLE_INTERRUPT 0x20000000
233#define RX_FIRST_DESC 0x08000000
234#define RX_LAST_DESC 0x04000000
eaf5d590
LB		 235#define RX_IP_HDR_OK 0x02000000
236#define RX_PKT_IS_IPV4 0x01000000
237#define RX_PKT_IS_ETHERNETV2 0x00800000
238#define RX_PKT_LAYER4_TYPE_MASK 0x00600000
239#define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
240#define RX_PKT_IS_VLAN_TAGGED 0x00080000
7ca72a3b
LB		 241
242/* TX descriptor command */
cc9754b3
LB		 243#define TX_ENABLE_INTERRUPT 0x00800000
244#define GEN_CRC 0x00400000
245#define TX_FIRST_DESC 0x00200000
246#define TX_LAST_DESC 0x00100000
247#define ZERO_PADDING 0x00080000
248#define GEN_IP_V4_CHECKSUM 0x00040000
249#define GEN_TCP_UDP_CHECKSUM 0x00020000
250#define UDP_FRAME 0x00010000
e32b6617
LB		 251#define MAC_HDR_EXTRA_4_BYTES 0x00008000
252#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 253
cc9754b3 254#define TX_IHL_SHIFT 11
7ca72a3b
LB		 255
256
c9df406f 257/* global *******************************************************************/
e5371493 258struct mv643xx_eth_shared_private {
fc32b0e2
LB		 259 /*
260 * Ethernet controller base address.
261 */
cc9754b3 262 void __iomem *base;
c9df406f 263
fc0eb9f2
LB		 264 /*
265 * Points at the right SMI instance to use.
266 */
267 struct mv643xx_eth_shared_private *smi;
268
fc32b0e2 269 /*
ed94493f 270 * Provides access to local SMI interface.
fc32b0e2 271 */
298cf9be 272 struct mii_bus *smi_bus;
c9df406f 273
45c5d3bc
LB		 274 /*
275 * If we have access to the error interrupt pin (which is
276 * somewhat misnamed as it not only reflects internal errors
277 * but also reflects SMI completion), use that to wait for
278 * SMI access completion instead of polling the SMI busy bit.
279 */
280 int err_interrupt;
281 wait_queue_head_t smi_busy_wait;
282
fc32b0e2
LB		 283 /*
284 * Per-port MBUS window access register value.
285 */
c9df406f
LB		 286 u32 win_protect;
287
fc32b0e2
LB		 288 /*
289 * Hardware-specific parameters.
290 */
c9df406f 291 unsigned int t_clk;
773fc3ee 292 int extended_rx_coal_limit;
457b1d5a 293 int tx_bw_control;
9b2c2ff7 294 int tx_csum_limit;
c9df406f
LB		 295};
296
457b1d5a
LB		 297#define TX_BW_CONTROL_ABSENT 0
298#define TX_BW_CONTROL_OLD_LAYOUT 1
299#define TX_BW_CONTROL_NEW_LAYOUT 2
300
e7d2f4db
LB		 301static int mv643xx_eth_open(struct net_device *dev);
302static int mv643xx_eth_stop(struct net_device *dev);
303
c9df406f
LB		 304
305/* per-port *****************************************************************/
e5371493 306struct mib_counters {
fbd6a754
LB		 307 u64 good_octets_received;
308 u32 bad_octets_received;
309 u32 internal_mac_transmit_err;
310 u32 good_frames_received;
311 u32 bad_frames_received;
312 u32 broadcast_frames_received;
313 u32 multicast_frames_received;
314 u32 frames_64_octets;
315 u32 frames_65_to_127_octets;
316 u32 frames_128_to_255_octets;
317 u32 frames_256_to_511_octets;
318 u32 frames_512_to_1023_octets;
319 u32 frames_1024_to_max_octets;
320 u64 good_octets_sent;
321 u32 good_frames_sent;
322 u32 excessive_collision;
323 u32 multicast_frames_sent;
324 u32 broadcast_frames_sent;
325 u32 unrec_mac_control_received;
326 u32 fc_sent;
327 u32 good_fc_received;
328 u32 bad_fc_received;
329 u32 undersize_received;
330 u32 fragments_received;
331 u32 oversize_received;
332 u32 jabber_received;
333 u32 mac_receive_error;
334 u32 bad_crc_event;
335 u32 collision;
336 u32 late_collision;
337};
338
eaf5d590
LB		 339struct lro_counters {
340 u32 lro_aggregated;
341 u32 lro_flushed;
342 u32 lro_no_desc;
343};
344
8a578111 345struct rx_queue {
64da80a2
LB		 346 int index;
347
8a578111
LB		 348 int rx_ring_size;
349
350 int rx_desc_count;
351 int rx_curr_desc;
352 int rx_used_desc;
353
354 struct rx_desc *rx_desc_area;
355 dma_addr_t rx_desc_dma;
356 int rx_desc_area_size;
357 struct sk_buff **rx_skb;
eaf5d590 358
eaf5d590
LB		 359 struct net_lro_mgr lro_mgr;
360 struct net_lro_desc lro_arr[8];
8a578111
LB		 361};
362
13d64285 363struct tx_queue {
3d6b35bc
LB		 364 int index;
365
13d64285 366 int tx_ring_size;
fbd6a754 367
13d64285
LB		 368 int tx_desc_count;
369 int tx_curr_desc;
370 int tx_used_desc;
fbd6a754 371
5daffe94 372 struct tx_desc *tx_desc_area;
fbd6a754
LB		 373 dma_addr_t tx_desc_dma;
374 int tx_desc_area_size;
99ab08e0
LB		 375
376 struct sk_buff_head tx_skb;
8fd89211
LB		 377
378 unsigned long tx_packets;
379 unsigned long tx_bytes;
380 unsigned long tx_dropped;
13d64285
LB		 381};
382
383struct mv643xx_eth_private {
384 struct mv643xx_eth_shared_private *shared;
37a6084f 385 void __iomem *base;
fc32b0e2 386 int port_num;
13d64285 387
fc32b0e2 388 struct net_device *dev;
fbd6a754 389
ed94493f 390 struct phy_device *phy;
fbd6a754 391
4ff3495a
LB		 392 struct timer_list mib_counters_timer;
393 spinlock_t mib_counters_lock;
fc32b0e2 394 struct mib_counters mib_counters;
4ff3495a 395
eaf5d590
LB		 396 struct lro_counters lro_counters;
397
fc32b0e2 398 struct work_struct tx_timeout_task;
8a578111 399
1fa38c58 400 struct napi_struct napi;
e0ca8410 401 u32 int_mask;
1319ebad 402 u8 oom;
1fa38c58
LB		 403 u8 work_link;
404 u8 work_tx;
405 u8 work_tx_end;
406 u8 work_rx;
407 u8 work_rx_refill;
1fa38c58 408
2bcb4b0f
LB		 409 int skb_size;
410 struct sk_buff_head rx_recycle;
411
8a578111
LB		 412 /*
413 * RX state.
414 */
e7d2f4db 415 int rx_ring_size;
8a578111
LB		 416 unsigned long rx_desc_sram_addr;
417 int rx_desc_sram_size;
f7981c1c 418 int rxq_count;
2257e05c 419 struct timer_list rx_oom;
64da80a2 420 struct rx_queue rxq[8];
13d64285
LB		 421
422 /*
423 * TX state.
424 */
e7d2f4db 425 int tx_ring_size;
13d64285
LB		 426 unsigned long tx_desc_sram_addr;
427 int tx_desc_sram_size;
f7981c1c 428 int txq_count;
3d6b35bc 429 struct tx_queue txq[8];
fbd6a754 430};
1da177e4 431
fbd6a754 432
c9df406f 433/* port register accessors **************************************************/
e5371493 434static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 435{
cc9754b3 436 return readl(mp->shared->base + offset);
c9df406f 437}
fbd6a754 438
37a6084f
LB		 439static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
440{
441 return readl(mp->base + offset);
442}
443
e5371493 444static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 445{
cc9754b3 446 writel(data, mp->shared->base + offset);
c9df406f 447}
fbd6a754 448
37a6084f
LB		 449static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
450{
451 writel(data, mp->base + offset);
452}
453
fbd6a754 454
c9df406f 455/* rxq/txq helper functions *************************************************/
8a578111 456static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 457{
64da80a2 458 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 459}
fbd6a754 460
13d64285
LB		 461static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
462{
3d6b35bc 463 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 464}
465
8a578111 466static void rxq_enable(struct rx_queue *rxq)
c9df406f 467{
8a578111 468 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 469 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 470}
1da177e4 471
8a578111
LB		 472static void rxq_disable(struct rx_queue *rxq)
473{
474 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 475 u8 mask = 1 << rxq->index;
1da177e4 476
37a6084f
LB		 477 wrlp(mp, RXQ_COMMAND, mask << 8);
478 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 479 udelay(10);
c9df406f
LB		 480}
481
6b368f68
LB		 482static void txq_reset_hw_ptr(struct tx_queue *txq)
483{
484 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 485 u32 addr;
486
487 addr = (u32)txq->tx_desc_dma;
488 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 489 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 490}
491
13d64285 492static void txq_enable(struct tx_queue *txq)
1da177e4 493{
13d64285 494 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 495 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 496}
497
13d64285 498static void txq_disable(struct tx_queue *txq)
1da177e4 499{
13d64285 500 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 501 u8 mask = 1 << txq->index;
c9df406f 502
37a6084f
LB		 503 wrlp(mp, TXQ_COMMAND, mask << 8);
504 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 505 udelay(10);
506}
507
1fa38c58 508static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 509{
510 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 511 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 512
8fd89211
LB		 513 if (netif_tx_queue_stopped(nq)) {
514 __netif_tx_lock(nq, smp_processor_id());
515 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
516 netif_tx_wake_queue(nq);
517 __netif_tx_unlock(nq);
518 }
1da177e4
LT		 519}
520
c9df406f 521
1fa38c58 522/* rx napi ******************************************************************/
eaf5d590
LB		 523static int
524mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
525 u64 *hdr_flags, void *priv)
526{
527 unsigned long cmd_sts = (unsigned long)priv;
528
529 /*
530 * Make sure that this packet is Ethernet II, is not VLAN
531 * tagged, is IPv4, has a valid IP header, and is TCP.
532 */
533 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
534 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
535 RX_PKT_IS_VLAN_TAGGED)) !=
536 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
537 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
538 return -1;
539
540 skb_reset_network_header(skb);
541 skb_set_transport_header(skb, ip_hdrlen(skb));
542 *iphdr = ip_hdr(skb);
543 *tcph = tcp_hdr(skb);
544 *hdr_flags = LRO_IPV4 | LRO_TCP;
545
546 return 0;
547}
eaf5d590 548
8a578111 549static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 550{
8a578111
LB		 551 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
552 struct net_device_stats *stats = &mp->dev->stats;
eaf5d590 553 int lro_flush_needed;
8a578111 554 int rx;
1da177e4 555
eaf5d590 556 lro_flush_needed = 0;
8a578111 557 rx = 0;
9e1f3772 558 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 559 struct rx_desc *rx_desc;
96587661 560 unsigned int cmd_sts;
fc32b0e2 561 struct sk_buff *skb;
6b8f90c2 562 u16 byte_cnt;
ff561eef 563
8a578111 564 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 565
96587661 566 cmd_sts = rx_desc->cmd_sts;
2257e05c 567 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 568 break;
96587661 569 rmb();
1da177e4 570
8a578111
LB		 571 skb = rxq->rx_skb[rxq->rx_curr_desc];
572 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 573
9da78745
LB		 574 rxq->rx_curr_desc++;
575 if (rxq->rx_curr_desc == rxq->rx_ring_size)
576 rxq->rx_curr_desc = 0;
ff561eef 577
eb0519b5 578 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
abe78717 579 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 580 rxq->rx_desc_count--;
581 rx++;
b1dd9ca1 582
1fa38c58
LB		 583 mp->work_rx_refill |= 1 << rxq->index;
584
6b8f90c2
LB		 585 byte_cnt = rx_desc->byte_cnt;
586
468d09f8
DF		 587 /*
588 * Update statistics.
fc32b0e2
LB		 589 *
590 * Note that the descriptor byte count includes 2 dummy
591 * bytes automatically inserted by the hardware at the
592 * start of the packet (which we don't count), and a 4
593 * byte CRC at the end of the packet (which we do count).
468d09f8 594 */
1da177e4 595 stats->rx_packets++;
6b8f90c2 596 stats->rx_bytes += byte_cnt - 2;
96587661 597
1da177e4 598 /*
fc32b0e2
LB		 599 * In case we received a packet without first / last bits
600 * on, or the error summary bit is set, the packet needs
601 * to be dropped.
1da177e4 602 */
f61e5547
LB		 603 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
604 != (RX_FIRST_DESC | RX_LAST_DESC))
605 goto err;
606
607 /*
608 * The -4 is for the CRC in the trailer of the
609 * received packet
610 */
611 skb_put(skb, byte_cnt - 2 - 4);
612
613 if (cmd_sts & LAYER_4_CHECKSUM_OK)
614 skb->ip_summed = CHECKSUM_UNNECESSARY;
615 skb->protocol = eth_type_trans(skb, mp->dev);
eaf5d590 616
eaf5d590
LB		 617 if (skb->dev->features & NETIF_F_LRO &&
618 skb->ip_summed == CHECKSUM_UNNECESSARY) {
619 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
620 lro_flush_needed = 1;
621 } else
eaf5d590 622 netif_receive_skb(skb);
f61e5547
LB		 623
624 continue;
625
626err:
627 stats->rx_dropped++;
628
629 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
630 (RX_FIRST_DESC | RX_LAST_DESC)) {
631 if (net_ratelimit())
7542db8b
JP		 632 netdev_err(mp->dev,
633 "received packet spanning multiple descriptors\n");
1da177e4 634 }
f61e5547
LB		 635
636 if (cmd_sts & ERROR_SUMMARY)
637 stats->rx_errors++;
638
639 dev_kfree_skb(skb);
1da177e4 640 }
fc32b0e2 641
eaf5d590
LB		 642 if (lro_flush_needed)
643 lro_flush_all(&rxq->lro_mgr);
eaf5d590 644
1fa38c58
LB		 645 if (rx < budget)
646 mp->work_rx &= ~(1 << rxq->index);
647
8a578111 648 return rx;
1da177e4
LT		 649}
650
1fa38c58 651static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 652{
1fa38c58 653 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 654 int refilled;
8a578111 655
1fa38c58
LB		 656 refilled = 0;
657 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
658 struct sk_buff *skb;
1fa38c58 659 int rx;
53771522 660 struct rx_desc *rx_desc;
530e557a 661 int size;
d0412d96 662
2bcb4b0f
LB		 663 skb = __skb_dequeue(&mp->rx_recycle);
664 if (skb == NULL)
7fd96ce4 665 skb = dev_alloc_skb(mp->skb_size);
2bcb4b0f 666
1fa38c58 667 if (skb == NULL) {
1319ebad 668 mp->oom = 1;
1fa38c58
LB		 669 goto oom;
670 }
d0412d96 671
7fd96ce4
LB		 672 if (SKB_DMA_REALIGN)
673 skb_reserve(skb, SKB_DMA_REALIGN);
2257e05c 674
1fa38c58
LB		 675 refilled++;
676 rxq->rx_desc_count++;
c9df406f 677
1fa38c58
LB		 678 rx = rxq->rx_used_desc++;
679 if (rxq->rx_used_desc == rxq->rx_ring_size)
680 rxq->rx_used_desc = 0;
2257e05c 681
53771522
LB		 682 rx_desc = rxq->rx_desc_area + rx;
683
530e557a 684 size = skb->end - skb->data;
eb0519b5 685 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
530e557a 686 skb->data, size,
eb0519b5 687 DMA_FROM_DEVICE);
530e557a 688 rx_desc->buf_size = size;
1fa38c58
LB		 689 rxq->rx_skb[rx] = skb;
690 wmb();
53771522 691 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
1fa38c58 692 wmb();
2257e05c 693
1fa38c58
LB		 694 /*
695 * The hardware automatically prepends 2 bytes of
696 * dummy data to each received packet, so that the
697 * IP header ends up 16-byte aligned.
698 */
699 skb_reserve(skb, 2);
700 }
701
702 if (refilled < budget)
703 mp->work_rx_refill &= ~(1 << rxq->index);
704
705oom:
706 return refilled;
d0412d96
JC		 707}
708
c9df406f
LB		 709
710/* tx ***********************************************************************/
c9df406f 711static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 712{
13d64285 713 int frag;
1da177e4 714
c9df406f 715 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 716 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
717 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 718 return 1;
1da177e4 719 }
13d64285 720
c9df406f
LB		 721 return 0;
722}
7303fde8 723
13d64285 724static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 725{
eb0519b5 726 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 727 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 728 int frag;
1da177e4 729
13d64285
LB		 730 for (frag = 0; frag < nr_frags; frag++) {
731 skb_frag_t *this_frag;
732 int tx_index;
733 struct tx_desc *desc;
734
735 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 736 tx_index = txq->tx_curr_desc++;
737 if (txq->tx_curr_desc == txq->tx_ring_size)
738 txq->tx_curr_desc = 0;
13d64285
LB		 739 desc = &txq->tx_desc_area[tx_index];
740
741 /*
742 * The last fragment will generate an interrupt
743 * which will free the skb on TX completion.
744 */
745 if (frag == nr_frags - 1) {
746 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
747 ZERO_PADDING | TX_LAST_DESC |
748 TX_ENABLE_INTERRUPT;
13d64285
LB		 749 } else {
750 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 751 }
752
c9df406f
LB		 753 desc->l4i_chk = 0;
754 desc->byte_cnt = this_frag->size;
eb0519b5
GP		 755 desc->buf_ptr = dma_map_page(mp->dev->dev.parent,
756 this_frag->page,
757 this_frag->page_offset,
758 this_frag->size, DMA_TO_DEVICE);
c9df406f 759 }
1da177e4
LT		 760}
761
c9df406f
LB		 762static inline __be16 sum16_as_be(__sum16 sum)
763{
764 return (__force __be16)sum;
765}
1da177e4 766
4df89bd5 767static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 768{
8fa89bf5 769 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 770 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 771 int tx_index;
cc9754b3 772 struct tx_desc *desc;
c9df406f 773 u32 cmd_sts;
4df89bd5 774 u16 l4i_chk;
c9df406f 775 int length;
1da177e4 776
cc9754b3 777 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 778 l4i_chk = 0;
c9df406f
LB		 779
780 if (skb->ip_summed == CHECKSUM_PARTIAL) {
9b2c2ff7 781 int hdr_len;
4df89bd5 782 int tag_bytes;
e32b6617
LB		 783
784 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
785 skb->protocol != htons(ETH_P_8021Q));
c9df406f 786
9b2c2ff7
SB		 787 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
788 tag_bytes = hdr_len - ETH_HLEN;
789 if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
790 unlikely(tag_bytes & ~12)) {
4df89bd5
LB		 791 if (skb_checksum_help(skb) == 0)
792 goto no_csum;
793 kfree_skb(skb);
794 return 1;
795 }
c9df406f 796
4df89bd5 797 if (tag_bytes & 4)
e32b6617 798 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 799 if (tag_bytes & 8)
e32b6617 800 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 801
802 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
803 GEN_IP_V4_CHECKSUM |
804 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 805
c9df406f
LB		 806 switch (ip_hdr(skb)->protocol) {
807 case IPPROTO_UDP:
cc9754b3 808 cmd_sts |= UDP_FRAME;
4df89bd5 809 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 810 break;
811 case IPPROTO_TCP:
4df89bd5 812 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 813 break;
814 default:
815 BUG();
816 }
817 } else {
4df89bd5 818no_csum:
c9df406f 819 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 820 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 821 }
822
66823b92
LB		 823 tx_index = txq->tx_curr_desc++;
824 if (txq->tx_curr_desc == txq->tx_ring_size)
825 txq->tx_curr_desc = 0;
4df89bd5
LB		 826 desc = &txq->tx_desc_area[tx_index];
827
828 if (nr_frags) {
829 txq_submit_frag_skb(txq, skb);
830 length = skb_headlen(skb);
831 } else {
832 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
833 length = skb->len;
834 }
835
836 desc->l4i_chk = l4i_chk;
837 desc->byte_cnt = length;
eb0519b5
GP		 838 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
839 length, DMA_TO_DEVICE);
4df89bd5 840
99ab08e0
LB		 841 __skb_queue_tail(&txq->tx_skb, skb);
842
c9df406f
LB		 843 /* ensure all other descriptors are written before first cmd_sts */
844 wmb();
845 desc->cmd_sts = cmd_sts;
846
1fa38c58
LB		 847 /* clear TX_END status */
848 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 849
c9df406f
LB		 850 /* ensure all descriptors are written before poking hardware */
851 wmb();
13d64285 852 txq_enable(txq);
c9df406f 853
13d64285 854 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 855
856 return 0;
1da177e4 857}
1da177e4 858
0ccfe64d 859static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 860{
e5371493 861 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 862 int queue;
13d64285 863 struct tx_queue *txq;
e5ef1de1 864 struct netdev_queue *nq;
afdb57a2 865
8fd89211
LB		 866 queue = skb_get_queue_mapping(skb);
867 txq = mp->txq + queue;
868 nq = netdev_get_tx_queue(dev, queue);
869
c9df406f 870 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 871 txq->tx_dropped++;
7542db8b
JP		 872 netdev_printk(KERN_DEBUG, dev,
873 "failed to linearize skb with tiny unaligned fragment\n");
c9df406f
LB		 874 return NETDEV_TX_BUSY;
875 }
876
17cd0a59 877 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1 878 if (net_ratelimit())
7542db8b 879 netdev_err(dev, "tx queue full?!\n");
3d6b35bc
LB		 880 kfree_skb(skb);
881 return NETDEV_TX_OK;
c9df406f
LB		 882 }
883
4df89bd5
LB		 884 if (!txq_submit_skb(txq, skb)) {
885 int entries_left;
886
887 txq->tx_bytes += skb->len;
888 txq->tx_packets++;
c9df406f 889
4df89bd5
LB		 890 entries_left = txq->tx_ring_size - txq->tx_desc_count;
891 if (entries_left < MAX_SKB_FRAGS + 1)
892 netif_tx_stop_queue(nq);
893 }
c9df406f 894
c9df406f 895 return NETDEV_TX_OK;
1da177e4
LT		 896}
897
c9df406f 898
1fa38c58
LB		 899/* tx napi ******************************************************************/
900static void txq_kick(struct tx_queue *txq)
901{
902 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 903 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 904 u32 hw_desc_ptr;
905 u32 expected_ptr;
906
8fd89211 907 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 908
37a6084f 909 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 910 goto out;
911
37a6084f 912 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 913 expected_ptr = (u32)txq->tx_desc_dma +
914 txq->tx_curr_desc * sizeof(struct tx_desc);
915
916 if (hw_desc_ptr != expected_ptr)
917 txq_enable(txq);
918
919out:
8fd89211 920 __netif_tx_unlock(nq);
1fa38c58
LB		 921
922 mp->work_tx_end &= ~(1 << txq->index);
923}
924
925static int txq_reclaim(struct tx_queue *txq, int budget, int force)
926{
927 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 928 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 929 int reclaimed;
930
8fd89211 931 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 932
933 reclaimed = 0;
934 while (reclaimed < budget && txq->tx_desc_count > 0) {
935 int tx_index;
936 struct tx_desc *desc;
937 u32 cmd_sts;
938 struct sk_buff *skb;
1fa38c58
LB		 939
940 tx_index = txq->tx_used_desc;
941 desc = &txq->tx_desc_area[tx_index];
942 cmd_sts = desc->cmd_sts;
943
944 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
945 if (!force)
946 break;
947 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
948 }
949
950 txq->tx_used_desc = tx_index + 1;
951 if (txq->tx_used_desc == txq->tx_ring_size)
952 txq->tx_used_desc = 0;
953
954 reclaimed++;
955 txq->tx_desc_count--;
956
99ab08e0
LB		 957 skb = NULL;
958 if (cmd_sts & TX_LAST_DESC)
959 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 960
961 if (cmd_sts & ERROR_SUMMARY) {
7542db8b 962 netdev_info(mp->dev, "tx error\n");
1fa38c58
LB		 963 mp->dev->stats.tx_errors++;
964 }
965
a418950c 966 if (cmd_sts & TX_FIRST_DESC) {
eb0519b5 967 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 968 desc->byte_cnt, DMA_TO_DEVICE);
969 } else {
eb0519b5 970 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 971 desc->byte_cnt, DMA_TO_DEVICE);
972 }
1fa38c58 973
2bcb4b0f
LB		 974 if (skb != NULL) {
975 if (skb_queue_len(&mp->rx_recycle) <
e7d2f4db 976 mp->rx_ring_size &&
7fd96ce4 977 skb_recycle_check(skb, mp->skb_size))
2bcb4b0f
LB		 978 __skb_queue_head(&mp->rx_recycle, skb);
979 else
980 dev_kfree_skb(skb);
981 }
1fa38c58
LB		 982 }
983
8fd89211
LB		 984 __netif_tx_unlock(nq);
985
1fa38c58
LB		 986 if (reclaimed < budget)
987 mp->work_tx &= ~(1 << txq->index);
988
1fa38c58
LB		 989 return reclaimed;
990}
991
992
89df5fdc
LB		 993/* tx rate control **********************************************************/
994/*
995 * Set total maximum TX rate (shared by all TX queues for this port)
996 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
997 */
998static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
999{
1000 int token_rate;
1001 int mtu;
1002 int bucket_size;
1003
1004 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1005 if (token_rate > 1023)
1006 token_rate = 1023;
1007
1008 mtu = (mp->dev->mtu + 255) >> 8;
1009 if (mtu > 63)
1010 mtu = 63;
1011
1012 bucket_size = (burst + 255) >> 8;
1013 if (bucket_size > 65535)
1014 bucket_size = 65535;
1015
457b1d5a
LB		 1016 switch (mp->shared->tx_bw_control) {
1017 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 1018 wrlp(mp, TX_BW_RATE, token_rate);
1019 wrlp(mp, TX_BW_MTU, mtu);
1020 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 1021 break;
1022 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 1023 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1024 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1025 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 1026 break;
1e881592 1027 }
89df5fdc
LB		 1028}
1029
1030static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1031{
1032 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1033 int token_rate;
1034 int bucket_size;
1035
1036 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1037 if (token_rate > 1023)
1038 token_rate = 1023;
1039
1040 bucket_size = (burst + 255) >> 8;
1041 if (bucket_size > 65535)
1042 bucket_size = 65535;
1043
37a6084f
LB		 1044 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1045 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 1046}
1047
1048static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1049{
1050 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1051 int off;
1052 u32 val;
1053
1054 /*
1055 * Turn on fixed priority mode.
1056 */
457b1d5a
LB		 1057 off = 0;
1058 switch (mp->shared->tx_bw_control) {
1059 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1060 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1061 break;
1062 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1063 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1064 break;
1065 }
89df5fdc 1066
457b1d5a 1067 if (off) {
37a6084f 1068 val = rdlp(mp, off);
457b1d5a 1069 val |= 1 << txq->index;
37a6084f 1070 wrlp(mp, off, val);
457b1d5a 1071 }
89df5fdc
LB		 1072}
1073
89df5fdc 1074
c9df406f 1075/* mii management interface *************************************************/
45c5d3bc
LB		 1076static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1077{
1078 struct mv643xx_eth_shared_private *msp = dev_id;
1079
1080 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1081 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1082 wake_up(&msp->smi_busy_wait);
1083 return IRQ_HANDLED;
1084 }
1085
1086 return IRQ_NONE;
1087}
c9df406f 1088
45c5d3bc 1089static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1090{
45c5d3bc
LB		 1091 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1092}
1da177e4 1093
45c5d3bc
LB		 1094static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1095{
1096 if (msp->err_interrupt == NO_IRQ) {
1097 int i;
c9df406f 1098
45c5d3bc
LB		 1099 for (i = 0; !smi_is_done(msp); i++) {
1100 if (i == 10)
1101 return -ETIMEDOUT;
1102 msleep(10);
c9df406f 1103 }
45c5d3bc
LB		 1104
1105 return 0;
1106 }
1107
ee04448d
LB		 1108 if (!smi_is_done(msp)) {
1109 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1110 msecs_to_jiffies(100));
1111 if (!smi_is_done(msp))
1112 return -ETIMEDOUT;
1113 }
45c5d3bc
LB		 1114
1115 return 0;
1116}
1117
ed94493f 1118static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1119{
ed94493f 1120 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1121 void __iomem *smi_reg = msp->base + SMI_REG;
1122 int ret;
1123
45c5d3bc 1124 if (smi_wait_ready(msp)) {
7542db8b 1125 pr_warn("SMI bus busy timeout\n");
ed94493f 1126 return -ETIMEDOUT;
1da177e4
LT		 1127 }
1128
fc32b0e2 1129 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1130
45c5d3bc 1131 if (smi_wait_ready(msp)) {
7542db8b 1132 pr_warn("SMI bus busy timeout\n");
ed94493f 1133 return -ETIMEDOUT;
45c5d3bc
LB		 1134 }
1135
1136 ret = readl(smi_reg);
1137 if (!(ret & SMI_READ_VALID)) {
7542db8b 1138 pr_warn("SMI bus read not valid\n");
ed94493f 1139 return -ENODEV;
c9df406f
LB		 1140 }
1141
ed94493f 1142 return ret & 0xffff;
1da177e4
LT		 1143}
1144
ed94493f 1145static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1146{
ed94493f 1147 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1148 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1149
45c5d3bc 1150 if (smi_wait_ready(msp)) {
7542db8b 1151 pr_warn("SMI bus busy timeout\n");
45c5d3bc 1152 return -ETIMEDOUT;
1da177e4
LT		 1153 }
1154
fc32b0e2 1155 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1156 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1157
ed94493f 1158 if (smi_wait_ready(msp)) {
7542db8b 1159 pr_warn("SMI bus busy timeout\n");
ed94493f
LB		 1160 return -ETIMEDOUT;
1161 }
45c5d3bc
LB		 1162
1163 return 0;
c9df406f 1164}
1da177e4 1165
c9df406f 1166
8fd89211
LB		 1167/* statistics ***************************************************************/
1168static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1169{
1170 struct mv643xx_eth_private *mp = netdev_priv(dev);
1171 struct net_device_stats *stats = &dev->stats;
1172 unsigned long tx_packets = 0;
1173 unsigned long tx_bytes = 0;
1174 unsigned long tx_dropped = 0;
1175 int i;
1176
1177 for (i = 0; i < mp->txq_count; i++) {
1178 struct tx_queue *txq = mp->txq + i;
1179
1180 tx_packets += txq->tx_packets;
1181 tx_bytes += txq->tx_bytes;
1182 tx_dropped += txq->tx_dropped;
1183 }
1184
1185 stats->tx_packets = tx_packets;
1186 stats->tx_bytes = tx_bytes;
1187 stats->tx_dropped = tx_dropped;
1188
1189 return stats;
1190}
1191
eaf5d590
LB		 1192static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1193{
1194 u32 lro_aggregated = 0;
1195 u32 lro_flushed = 0;
1196 u32 lro_no_desc = 0;
1197 int i;
1198
eaf5d590
LB		 1199 for (i = 0; i < mp->rxq_count; i++) {
1200 struct rx_queue *rxq = mp->rxq + i;
1201
1202 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1203 lro_flushed += rxq->lro_mgr.stats.flushed;
1204 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1205 }
eaf5d590
LB		 1206
1207 mp->lro_counters.lro_aggregated = lro_aggregated;
1208 mp->lro_counters.lro_flushed = lro_flushed;
1209 mp->lro_counters.lro_no_desc = lro_no_desc;
1210}
1211
fc32b0e2 1212static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1213{
fc32b0e2 1214 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1215}
1216
fc32b0e2 1217static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1218{
fc32b0e2
LB		 1219 int i;
1220
1221 for (i = 0; i < 0x80; i += 4)
1222 mib_read(mp, i);
c9df406f 1223}
d0412d96 1224
fc32b0e2 1225static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1226{
e5371493 1227 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1228
57e8f26a 1229 spin_lock_bh(&mp->mib_counters_lock);
fc32b0e2 1230 p->good_octets_received += mib_read(mp, 0x00);
fc32b0e2
LB		 1231 p->bad_octets_received += mib_read(mp, 0x08);
1232 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1233 p->good_frames_received += mib_read(mp, 0x10);
1234 p->bad_frames_received += mib_read(mp, 0x14);
1235 p->broadcast_frames_received += mib_read(mp, 0x18);
1236 p->multicast_frames_received += mib_read(mp, 0x1c);
1237 p->frames_64_octets += mib_read(mp, 0x20);
1238 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1239 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1240 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1241 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1242 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1243 p->good_octets_sent += mib_read(mp, 0x38);
fc32b0e2
LB		 1244 p->good_frames_sent += mib_read(mp, 0x40);
1245 p->excessive_collision += mib_read(mp, 0x44);
1246 p->multicast_frames_sent += mib_read(mp, 0x48);
1247 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1248 p->unrec_mac_control_received += mib_read(mp, 0x50);
1249 p->fc_sent += mib_read(mp, 0x54);
1250 p->good_fc_received += mib_read(mp, 0x58);
1251 p->bad_fc_received += mib_read(mp, 0x5c);
1252 p->undersize_received += mib_read(mp, 0x60);
1253 p->fragments_received += mib_read(mp, 0x64);
1254 p->oversize_received += mib_read(mp, 0x68);
1255 p->jabber_received += mib_read(mp, 0x6c);
1256 p->mac_receive_error += mib_read(mp, 0x70);
1257 p->bad_crc_event += mib_read(mp, 0x74);
1258 p->collision += mib_read(mp, 0x78);
1259 p->late_collision += mib_read(mp, 0x7c);
57e8f26a 1260 spin_unlock_bh(&mp->mib_counters_lock);
4ff3495a
LB		 1261
1262 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1263}
1264
1265static void mib_counters_timer_wrapper(unsigned long _mp)
1266{
1267 struct mv643xx_eth_private *mp = (void *)_mp;
1268
1269 mib_counters_update(mp);
d0412d96
JC		 1270}
1271
c9df406f 1272
3e508034
LB		 1273/* interrupt coalescing *****************************************************/
1274/*
1275 * Hardware coalescing parameters are set in units of 64 t_clk
1276 * cycles. I.e.:
1277 *
1278 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1279 *
1280 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1281 *
1282 * In the ->set*() methods, we round the computed register value
1283 * to the nearest integer.
1284 */
1285static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1286{
1287 u32 val = rdlp(mp, SDMA_CONFIG);
1288 u64 temp;
1289
1290 if (mp->shared->extended_rx_coal_limit)
1291 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1292 else
1293 temp = (val & 0x003fff00) >> 8;
1294
1295 temp *= 64000000;
1296 do_div(temp, mp->shared->t_clk);
1297
1298 return (unsigned int)temp;
1299}
1300
1301static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1302{
1303 u64 temp;
1304 u32 val;
1305
1306 temp = (u64)usec * mp->shared->t_clk;
1307 temp += 31999999;
1308 do_div(temp, 64000000);
1309
1310 val = rdlp(mp, SDMA_CONFIG);
1311 if (mp->shared->extended_rx_coal_limit) {
1312 if (temp > 0xffff)
1313 temp = 0xffff;
1314 val &= ~0x023fff80;
1315 val |= (temp & 0x8000) << 10;
1316 val |= (temp & 0x7fff) << 7;
1317 } else {
1318 if (temp > 0x3fff)
1319 temp = 0x3fff;
1320 val &= ~0x003fff00;
1321 val |= (temp & 0x3fff) << 8;
1322 }
1323 wrlp(mp, SDMA_CONFIG, val);
1324}
1325
1326static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1327{
1328 u64 temp;
1329
1330 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1331 temp *= 64000000;
1332 do_div(temp, mp->shared->t_clk);
1333
1334 return (unsigned int)temp;
1335}
1336
1337static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1338{
1339 u64 temp;
1340
1341 temp = (u64)usec * mp->shared->t_clk;
1342 temp += 31999999;
1343 do_div(temp, 64000000);
1344
1345 if (temp > 0x3fff)
1346 temp = 0x3fff;
1347
1348 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1349}
1350
1351
c9df406f 1352/* ethtool ******************************************************************/
e5371493 1353struct mv643xx_eth_stats {
c9df406f
LB		 1354 char stat_string[ETH_GSTRING_LEN];
1355 int sizeof_stat;
16820054
LB		 1356 int netdev_off;
1357 int mp_off;
c9df406f
LB		 1358};
1359
16820054
LB		 1360#define SSTAT(m) \
1361 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1362 offsetof(struct net_device, stats.m), -1 }
1363
1364#define MIBSTAT(m) \
1365 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1366 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1367
eaf5d590
LB		 1368#define LROSTAT(m) \
1369 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1370 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1371
16820054
LB		 1372static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1373 SSTAT(rx_packets),
1374 SSTAT(tx_packets),
1375 SSTAT(rx_bytes),
1376 SSTAT(tx_bytes),
1377 SSTAT(rx_errors),
1378 SSTAT(tx_errors),
1379 SSTAT(rx_dropped),
1380 SSTAT(tx_dropped),
1381 MIBSTAT(good_octets_received),
1382 MIBSTAT(bad_octets_received),
1383 MIBSTAT(internal_mac_transmit_err),
1384 MIBSTAT(good_frames_received),
1385 MIBSTAT(bad_frames_received),
1386 MIBSTAT(broadcast_frames_received),
1387 MIBSTAT(multicast_frames_received),
1388 MIBSTAT(frames_64_octets),
1389 MIBSTAT(frames_65_to_127_octets),
1390 MIBSTAT(frames_128_to_255_octets),
1391 MIBSTAT(frames_256_to_511_octets),
1392 MIBSTAT(frames_512_to_1023_octets),
1393 MIBSTAT(frames_1024_to_max_octets),
1394 MIBSTAT(good_octets_sent),
1395 MIBSTAT(good_frames_sent),
1396 MIBSTAT(excessive_collision),
1397 MIBSTAT(multicast_frames_sent),
1398 MIBSTAT(broadcast_frames_sent),
1399 MIBSTAT(unrec_mac_control_received),
1400 MIBSTAT(fc_sent),
1401 MIBSTAT(good_fc_received),
1402 MIBSTAT(bad_fc_received),
1403 MIBSTAT(undersize_received),
1404 MIBSTAT(fragments_received),
1405 MIBSTAT(oversize_received),
1406 MIBSTAT(jabber_received),
1407 MIBSTAT(mac_receive_error),
1408 MIBSTAT(bad_crc_event),
1409 MIBSTAT(collision),
1410 MIBSTAT(late_collision),
eaf5d590
LB		 1411 LROSTAT(lro_aggregated),
1412 LROSTAT(lro_flushed),
1413 LROSTAT(lro_no_desc),
c9df406f
LB		 1414};
1415
10a9948d 1416static int
6bdf576e
LB		 1417mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1418 struct ethtool_cmd *cmd)
d0412d96 1419{
d0412d96
JC		 1420 int err;
1421
ed94493f
LB		 1422 err = phy_read_status(mp->phy);
1423 if (err == 0)
1424 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1425
fc32b0e2
LB		 1426 /*
1427 * The MAC does not support 1000baseT_Half.
1428 */
d0412d96
JC		 1429 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1430 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1431
1432 return err;
1433}
1434
10a9948d 1435static int
6bdf576e 1436mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
10a9948d 1437 struct ethtool_cmd *cmd)
bedfe324 1438{
81600eea
LB		 1439 u32 port_status;
1440
37a6084f 1441 port_status = rdlp(mp, PORT_STATUS);
81600eea 1442
bedfe324
LB		 1443 cmd->supported = SUPPORTED_MII;
1444 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1445 switch (port_status & PORT_SPEED_MASK) {
1446 case PORT_SPEED_10:
70739497 1447 ethtool_cmd_speed_set(cmd, SPEED_10);
81600eea
LB		 1448 break;
1449 case PORT_SPEED_100:
70739497 1450 ethtool_cmd_speed_set(cmd, SPEED_100);
81600eea
LB		 1451 break;
1452 case PORT_SPEED_1000:
70739497 1453 ethtool_cmd_speed_set(cmd, SPEED_1000);
81600eea
LB		 1454 break;
1455 default:
1456 cmd->speed = -1;
1457 break;
1458 }
1459 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1460 cmd->port = PORT_MII;
1461 cmd->phy_address = 0;
1462 cmd->transceiver = XCVR_INTERNAL;
1463 cmd->autoneg = AUTONEG_DISABLE;
1464 cmd->maxtxpkt = 1;
1465 cmd->maxrxpkt = 1;
1466
1467 return 0;
1468}
1469
6bdf576e
LB		 1470static int
1471mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1472{
1473 struct mv643xx_eth_private *mp = netdev_priv(dev);
1474
1475 if (mp->phy != NULL)
1476 return mv643xx_eth_get_settings_phy(mp, cmd);
1477 else
1478 return mv643xx_eth_get_settings_phyless(mp, cmd);
1479}
1480
10a9948d
LB		 1481static int
1482mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1483{
e5371493 1484 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1485
6bdf576e
LB		 1486 if (mp->phy == NULL)
1487 return -EINVAL;
1488
fc32b0e2
LB		 1489 /*
1490 * The MAC does not support 1000baseT_Half.
1491 */
1492 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1493
ed94493f 1494 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1495}
1da177e4 1496
fc32b0e2
LB		 1497static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1498 struct ethtool_drvinfo *drvinfo)
c9df406f 1499{
e5371493
LB		 1500 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1501 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1502 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1503 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1504 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1505}
1da177e4 1506
fc32b0e2 1507static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1508{
e5371493 1509 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1510
6bdf576e
LB		 1511 if (mp->phy == NULL)
1512 return -EINVAL;
1da177e4 1513
6bdf576e 1514 return genphy_restart_aneg(mp->phy);
bedfe324
LB		 1515}
1516
3e508034
LB		 1517static int
1518mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1519{
1520 struct mv643xx_eth_private *mp = netdev_priv(dev);
1521
1522 ec->rx_coalesce_usecs = get_rx_coal(mp);
1523 ec->tx_coalesce_usecs = get_tx_coal(mp);
1524
1525 return 0;
1526}
1527
1528static int
1529mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1530{
1531 struct mv643xx_eth_private *mp = netdev_priv(dev);
1532
1533 set_rx_coal(mp, ec->rx_coalesce_usecs);
1534 set_tx_coal(mp, ec->tx_coalesce_usecs);
1535
1536 return 0;
1537}
1538
e7d2f4db
LB		 1539static void
1540mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1541{
1542 struct mv643xx_eth_private *mp = netdev_priv(dev);
1543
1544 er->rx_max_pending = 4096;
1545 er->tx_max_pending = 4096;
1546 er->rx_mini_max_pending = 0;
1547 er->rx_jumbo_max_pending = 0;
1548
1549 er->rx_pending = mp->rx_ring_size;
1550 er->tx_pending = mp->tx_ring_size;
1551 er->rx_mini_pending = 0;
1552 er->rx_jumbo_pending = 0;
1553}
1554
1555static int
1556mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1557{
1558 struct mv643xx_eth_private *mp = netdev_priv(dev);
1559
1560 if (er->rx_mini_pending || er->rx_jumbo_pending)
1561 return -EINVAL;
1562
1563 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1564 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1565
1566 if (netif_running(dev)) {
1567 mv643xx_eth_stop(dev);
1568 if (mv643xx_eth_open(dev)) {
7542db8b
JP		 1569 netdev_err(dev,
1570 "fatal error on re-opening device after ring param change\n");
e7d2f4db
LB		 1571 return -ENOMEM;
1572 }
1573 }
1574
1575 return 0;
1576}
1577
d888b373
LB		 1578
1579static int
aad59c43 1580mv643xx_eth_set_features(struct net_device *dev, u32 features)
d888b373
LB		 1581{
1582 struct mv643xx_eth_private *mp = netdev_priv(dev);
aad59c43 1583 u32 rx_csum = features & NETIF_F_RXCSUM;
d888b373
LB		 1584
1585 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1586
1587 return 0;
1588}
1589
fc32b0e2
LB		 1590static void mv643xx_eth_get_strings(struct net_device *dev,
1591 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1592{
1593 int i;
1da177e4 1594
fc32b0e2
LB		 1595 if (stringset == ETH_SS_STATS) {
1596 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1597 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1598 mv643xx_eth_stats[i].stat_string,
e5371493 1599 ETH_GSTRING_LEN);
c9df406f 1600 }
c9df406f
LB		 1601 }
1602}
1da177e4 1603
fc32b0e2
LB		 1604static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1605 struct ethtool_stats *stats,
1606 uint64_t *data)
c9df406f 1607{
b9873841 1608 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1609 int i;
1da177e4 1610
8fd89211 1611 mv643xx_eth_get_stats(dev);
fc32b0e2 1612 mib_counters_update(mp);
eaf5d590 1613 mv643xx_eth_grab_lro_stats(mp);
1da177e4 1614
16820054
LB		 1615 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1616 const struct mv643xx_eth_stats *stat;
1617 void *p;
1618
1619 stat = mv643xx_eth_stats + i;
1620
1621 if (stat->netdev_off >= 0)
1622 p = ((void *)mp->dev) + stat->netdev_off;
1623 else
1624 p = ((void *)mp) + stat->mp_off;
1625
1626 data[i] = (stat->sizeof_stat == 8) ?
1627 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1628 }
c9df406f 1629}
1da177e4 1630
fc32b0e2 1631static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1632{
fc32b0e2 1633 if (sset == ETH_SS_STATS)
16820054 1634 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1635
1636 return -EOPNOTSUPP;
c9df406f 1637}
1da177e4 1638
e5371493 1639static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1640 .get_settings = mv643xx_eth_get_settings,
1641 .set_settings = mv643xx_eth_set_settings,
1642 .get_drvinfo = mv643xx_eth_get_drvinfo,
1643 .nway_reset = mv643xx_eth_nway_reset,
ed4ba4b5 1644 .get_link = ethtool_op_get_link,
3e508034
LB		 1645 .get_coalesce = mv643xx_eth_get_coalesce,
1646 .set_coalesce = mv643xx_eth_set_coalesce,
e7d2f4db
LB		 1647 .get_ringparam = mv643xx_eth_get_ringparam,
1648 .set_ringparam = mv643xx_eth_set_ringparam,
fc32b0e2
LB		 1649 .get_strings = mv643xx_eth_get_strings,
1650 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1651 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1652};
1da177e4 1653
bea3348e 1654
c9df406f 1655/* address handling *********************************************************/
5daffe94 1656static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1657{
66e63ffb
LB		 1658 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1659 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1660
5daffe94
LB		 1661 addr[0] = (mac_h >> 24) & 0xff;
1662 addr[1] = (mac_h >> 16) & 0xff;
1663 addr[2] = (mac_h >> 8) & 0xff;
1664 addr[3] = mac_h & 0xff;
1665 addr[4] = (mac_l >> 8) & 0xff;
1666 addr[5] = mac_l & 0xff;
c9df406f 1667}
1da177e4 1668
66e63ffb 1669static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1670{
66e63ffb
LB		 1671 wrlp(mp, MAC_ADDR_HIGH,
1672 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1673 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
c9df406f 1674}
d0412d96 1675
66e63ffb 1676static u32 uc_addr_filter_mask(struct net_device *dev)
c9df406f 1677{
ccffad25 1678 struct netdev_hw_addr *ha;
66e63ffb 1679 u32 nibbles;
1da177e4 1680
66e63ffb
LB		 1681 if (dev->flags & IFF_PROMISC)
1682 return 0;
1da177e4 1683
66e63ffb 1684 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
32e7bfc4 1685 netdev_for_each_uc_addr(ha, dev) {
ccffad25 1686 if (memcmp(dev->dev_addr, ha->addr, 5))
66e63ffb 1687 return 0;
ccffad25 1688 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
66e63ffb 1689 return 0;
ff561eef 1690
ccffad25 1691 nibbles |= 1 << (ha->addr[5] & 0x0f);
66e63ffb 1692 }
1da177e4 1693
66e63ffb 1694 return nibbles;
1da177e4
LT		 1695}
1696
66e63ffb 1697static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1da177e4 1698{
e5371493 1699 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1700 u32 port_config;
1701 u32 nibbles;
1702 int i;
1da177e4 1703
cc9754b3 1704 uc_addr_set(mp, dev->dev_addr);
1da177e4 1705
6877f54e
PS		 1706 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1707
66e63ffb
LB		 1708 nibbles = uc_addr_filter_mask(dev);
1709 if (!nibbles) {
1710 port_config |= UNICAST_PROMISCUOUS_MODE;
6877f54e 1711 nibbles = 0xffff;
66e63ffb
LB		 1712 }
1713
1714 for (i = 0; i < 16; i += 4) {
1715 int off = UNICAST_TABLE(mp->port_num) + i;
1716 u32 v;
1717
1718 v = 0;
1719 if (nibbles & 1)
1720 v |= 0x00000001;
1721 if (nibbles & 2)
1722 v |= 0x00000100;
1723 if (nibbles & 4)
1724 v |= 0x00010000;
1725 if (nibbles & 8)
1726 v |= 0x01000000;
1727 nibbles >>= 4;
1728
1729 wrl(mp, off, v);
1730 }
1731
66e63ffb 1732 wrlp(mp, PORT_CONFIG, port_config);
1da177e4
LT		 1733}
1734
69876569
LB		 1735static int addr_crc(unsigned char *addr)
1736{
1737 int crc = 0;
1738 int i;
1739
1740 for (i = 0; i < 6; i++) {
1741 int j;
1742
1743 crc = (crc ^ addr[i]) << 8;
1744 for (j = 7; j >= 0; j--) {
1745 if (crc & (0x100 << j))
1746 crc ^= 0x107 << j;
1747 }
1748 }
1749
1750 return crc;
1751}
1752
66e63ffb 1753static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1da177e4 1754{
fc32b0e2 1755 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1756 u32 *mc_spec;
1757 u32 *mc_other;
22bedad3 1758 struct netdev_hw_addr *ha;
fc32b0e2 1759 int i;
c8aaea25 1760
fc32b0e2 1761 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
66e63ffb
LB		 1762 int port_num;
1763 u32 accept;
c8aaea25 1764
66e63ffb
LB		 1765oom:
1766 port_num = mp->port_num;
1767 accept = 0x01010101;
fc32b0e2
LB		 1768 for (i = 0; i < 0x100; i += 4) {
1769 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1770 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1771 }
1772 return;
1773 }
c8aaea25 1774
82a5bd6a 1775 mc_spec = kmalloc(0x200, GFP_ATOMIC);
66e63ffb
LB		 1776 if (mc_spec == NULL)
1777 goto oom;
1778 mc_other = mc_spec + (0x100 >> 2);
1779
1780 memset(mc_spec, 0, 0x100);
1781 memset(mc_other, 0, 0x100);
1da177e4 1782
22bedad3
JP		 1783 netdev_for_each_mc_addr(ha, dev) {
1784 u8 *a = ha->addr;
66e63ffb
LB		 1785 u32 *table;
1786 int entry;
1da177e4 1787
fc32b0e2 1788 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
66e63ffb
LB		 1789 table = mc_spec;
1790 entry = a[5];
fc32b0e2 1791 } else {
66e63ffb
LB		 1792 table = mc_other;
1793 entry = addr_crc(a);
fc32b0e2 1794 }
66e63ffb 1795
2b448334 1796 table[entry >> 2] |= 1 << (8 * (entry & 3));
fc32b0e2 1797 }
66e63ffb
LB		 1798
1799 for (i = 0; i < 0x100; i += 4) {
1800 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1801 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1802 }
1803
1804 kfree(mc_spec);
1805}
1806
1807static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1808{
1809 mv643xx_eth_program_unicast_filter(dev);
1810 mv643xx_eth_program_multicast_filter(dev);
1811}
1812
1813static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1814{
1815 struct sockaddr *sa = addr;
1816
a29ec08a
DK		 1817 if (!is_valid_ether_addr(sa->sa_data))
1818 return -EINVAL;
1819
66e63ffb
LB		 1820 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1821
1822 netif_addr_lock_bh(dev);
1823 mv643xx_eth_program_unicast_filter(dev);
1824 netif_addr_unlock_bh(dev);
1825
1826 return 0;
c9df406f 1827}
c8aaea25 1828
c8aaea25 1829
c9df406f 1830/* rx/tx queue initialisation ***********************************************/
64da80a2 1831static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1832{
64da80a2 1833 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1834 struct rx_desc *rx_desc;
1835 int size;
c9df406f
LB		 1836 int i;
1837
64da80a2
LB		 1838 rxq->index = index;
1839
e7d2f4db 1840 rxq->rx_ring_size = mp->rx_ring_size;
8a578111
LB		 1841
1842 rxq->rx_desc_count = 0;
1843 rxq->rx_curr_desc = 0;
1844 rxq->rx_used_desc = 0;
1845
1846 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1847
f7981c1c 1848 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1849 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1850 mp->rx_desc_sram_size);
1851 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1852 } else {
eb0519b5
GP		 1853 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1854 size, &rxq->rx_desc_dma,
1855 GFP_KERNEL);
f7ea3337
PJ		 1856 }
1857
8a578111 1858 if (rxq->rx_desc_area == NULL) {
7542db8b 1859 netdev_err(mp->dev,
8a578111
LB		 1860 "can't allocate rx ring (%d bytes)\n", size);
1861 goto out;
1862 }
1863 memset(rxq->rx_desc_area, 0, size);
1da177e4 1864
8a578111
LB		 1865 rxq->rx_desc_area_size = size;
1866 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1867 GFP_KERNEL);
1868 if (rxq->rx_skb == NULL) {
7542db8b 1869 netdev_err(mp->dev, "can't allocate rx skb ring\n");
8a578111
LB		 1870 goto out_free;
1871 }
1872
1873 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1874 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1875 int nexti;
1876
1877 nexti = i + 1;
1878 if (nexti == rxq->rx_ring_size)
1879 nexti = 0;
1880
8a578111
LB		 1881 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1882 nexti * sizeof(struct rx_desc);
1883 }
1884
eaf5d590
LB		 1885 rxq->lro_mgr.dev = mp->dev;
1886 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1887 rxq->lro_mgr.features = LRO_F_NAPI;
1888 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1889 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1890 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1891 rxq->lro_mgr.max_aggr = 32;
1892 rxq->lro_mgr.frag_align_pad = 0;
1893 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1894 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1895
1896 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
eaf5d590 1897
8a578111
LB		 1898 return 0;
1899
1900
1901out_free:
f7981c1c 1902 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1903 iounmap(rxq->rx_desc_area);
1904 else
eb0519b5 1905 dma_free_coherent(mp->dev->dev.parent, size,
8a578111
LB		 1906 rxq->rx_desc_area,
1907 rxq->rx_desc_dma);
1908
1909out:
1910 return -ENOMEM;
c9df406f 1911}
c8aaea25 1912
8a578111 1913static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1914{
8a578111
LB		 1915 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1916 int i;
1917
1918 rxq_disable(rxq);
c8aaea25 1919
8a578111
LB		 1920 for (i = 0; i < rxq->rx_ring_size; i++) {
1921 if (rxq->rx_skb[i]) {
1922 dev_kfree_skb(rxq->rx_skb[i]);
1923 rxq->rx_desc_count--;
1da177e4 1924 }
c8aaea25 1925 }
1da177e4 1926
8a578111 1927 if (rxq->rx_desc_count) {
7542db8b 1928 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
8a578111
LB		 1929 rxq->rx_desc_count);
1930 }
1931
f7981c1c 1932 if (rxq->index == 0 &&
64da80a2 1933 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1934 iounmap(rxq->rx_desc_area);
c9df406f 1935 else
eb0519b5 1936 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
8a578111
LB		 1937 rxq->rx_desc_area, rxq->rx_desc_dma);
1938
1939 kfree(rxq->rx_skb);
c9df406f 1940}
1da177e4 1941
3d6b35bc 1942static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1943{
3d6b35bc 1944 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1945 struct tx_desc *tx_desc;
1946 int size;
c9df406f 1947 int i;
1da177e4 1948
3d6b35bc
LB		 1949 txq->index = index;
1950
e7d2f4db 1951 txq->tx_ring_size = mp->tx_ring_size;
13d64285
LB		 1952
1953 txq->tx_desc_count = 0;
1954 txq->tx_curr_desc = 0;
1955 txq->tx_used_desc = 0;
1956
1957 size = txq->tx_ring_size * sizeof(struct tx_desc);
1958
f7981c1c 1959 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1960 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1961 mp->tx_desc_sram_size);
1962 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1963 } else {
eb0519b5
GP		 1964 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1965 size, &txq->tx_desc_dma,
1966 GFP_KERNEL);
13d64285
LB		 1967 }
1968
1969 if (txq->tx_desc_area == NULL) {
7542db8b 1970 netdev_err(mp->dev,
13d64285 1971 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1972 return -ENOMEM;
c9df406f 1973 }
13d64285
LB		 1974 memset(txq->tx_desc_area, 0, size);
1975
1976 txq->tx_desc_area_size = size;
13d64285
LB		 1977
1978 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1979 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1980 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 1981 int nexti;
1982
1983 nexti = i + 1;
1984 if (nexti == txq->tx_ring_size)
1985 nexti = 0;
6b368f68
LB		 1986
1987 txd->cmd_sts = 0;
1988 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1989 nexti * sizeof(struct tx_desc);
1990 }
1991
99ab08e0 1992 skb_queue_head_init(&txq->tx_skb);
c9df406f 1993
99ab08e0 1994 return 0;
c8aaea25 1995}
1da177e4 1996
13d64285 1997static void txq_deinit(struct tx_queue *txq)
c9df406f 1998{
13d64285 1999 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 2000
13d64285 2001 txq_disable(txq);
1fa38c58 2002 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 2003
13d64285 2004 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 2005
f7981c1c 2006 if (txq->index == 0 &&
3d6b35bc 2007 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 2008 iounmap(txq->tx_desc_area);
c9df406f 2009 else
eb0519b5 2010 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
13d64285 2011 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 2012}
1da177e4 2013
1da177e4 2014
c9df406f 2015/* netdev ops and related ***************************************************/
1fa38c58
LB		 2016static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2017{
2018 u32 int_cause;
2019 u32 int_cause_ext;
2020
e0ca8410 2021 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1fa38c58
LB		 2022 if (int_cause == 0)
2023 return 0;
2024
2025 int_cause_ext = 0;
e0ca8410
SB		 2026 if (int_cause & INT_EXT) {
2027 int_cause &= ~INT_EXT;
37a6084f 2028 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
e0ca8410 2029 }
1fa38c58 2030
1fa38c58 2031 if (int_cause) {
37a6084f 2032 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 2033 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 2034 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 2035 mp->work_rx |= (int_cause & INT_RX) >> 2;
2036 }
2037
2038 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2039 if (int_cause_ext) {
37a6084f 2040 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 2041 if (int_cause_ext & INT_EXT_LINK_PHY)
2042 mp->work_link = 1;
2043 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2044 }
2045
2046 return 1;
2047}
2048
2049static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2050{
2051 struct net_device *dev = (struct net_device *)dev_id;
2052 struct mv643xx_eth_private *mp = netdev_priv(dev);
2053
2054 if (unlikely(!mv643xx_eth_collect_events(mp)))
2055 return IRQ_NONE;
2056
37a6084f 2057 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 2058 napi_schedule(&mp->napi);
2059
2060 return IRQ_HANDLED;
2061}
2062
2f7eb47a
LB		 2063static void handle_link_event(struct mv643xx_eth_private *mp)
2064{
2065 struct net_device *dev = mp->dev;
2066 u32 port_status;
2067 int speed;
2068 int duplex;
2069 int fc;
2070
37a6084f 2071 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 2072 if (!(port_status & LINK_UP)) {
2073 if (netif_carrier_ok(dev)) {
2074 int i;
2075
7542db8b 2076 netdev_info(dev, "link down\n");
2f7eb47a
LB		 2077
2078 netif_carrier_off(dev);
2f7eb47a 2079
f7981c1c 2080 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 2081 struct tx_queue *txq = mp->txq + i;
2082
1fa38c58 2083 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 2084 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 2085 }
2086 }
2087 return;
2088 }
2089
2090 switch (port_status & PORT_SPEED_MASK) {
2091 case PORT_SPEED_10:
2092 speed = 10;
2093 break;
2094 case PORT_SPEED_100:
2095 speed = 100;
2096 break;
2097 case PORT_SPEED_1000:
2098 speed = 1000;
2099 break;
2100 default:
2101 speed = -1;
2102 break;
2103 }
2104 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2105 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2106
7542db8b
JP		 2107 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2108 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2f7eb47a 2109
4fdeca3f 2110 if (!netif_carrier_ok(dev))
2f7eb47a 2111 netif_carrier_on(dev);
2f7eb47a
LB		 2112}
2113
1fa38c58 2114static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 2115{
1fa38c58
LB		 2116 struct mv643xx_eth_private *mp;
2117 int work_done;
ce4e2e45 2118
1fa38c58 2119 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 2120
1319ebad
LB		 2121 if (unlikely(mp->oom)) {
2122 mp->oom = 0;
2123 del_timer(&mp->rx_oom);
2124 }
1da177e4 2125
1fa38c58
LB		 2126 work_done = 0;
2127 while (work_done < budget) {
2128 u8 queue_mask;
2129 int queue;
2130 int work_tbd;
2131
2132 if (mp->work_link) {
2133 mp->work_link = 0;
2134 handle_link_event(mp);
26ef1f17 2135 work_done++;
1fa38c58
LB		 2136 continue;
2137 }
1da177e4 2138
1319ebad
LB		 2139 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2140 if (likely(!mp->oom))
2141 queue_mask |= mp->work_rx_refill;
2142
1fa38c58
LB		 2143 if (!queue_mask) {
2144 if (mv643xx_eth_collect_events(mp))
2145 continue;
2146 break;
2147 }
1da177e4 2148
1fa38c58
LB		 2149 queue = fls(queue_mask) - 1;
2150 queue_mask = 1 << queue;
2151
2152 work_tbd = budget - work_done;
2153 if (work_tbd > 16)
2154 work_tbd = 16;
2155
2156 if (mp->work_tx_end & queue_mask) {
2157 txq_kick(mp->txq + queue);
2158 } else if (mp->work_tx & queue_mask) {
2159 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2160 txq_maybe_wake(mp->txq + queue);
2161 } else if (mp->work_rx & queue_mask) {
2162 work_done += rxq_process(mp->rxq + queue, work_tbd);
1319ebad 2163 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
1fa38c58
LB		 2164 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2165 } else {
2166 BUG();
2167 }
84dd619e 2168 }
fc32b0e2 2169
1fa38c58 2170 if (work_done < budget) {
1319ebad 2171 if (mp->oom)
1fa38c58
LB		 2172 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2173 napi_complete(napi);
e0ca8410 2174 wrlp(mp, INT_MASK, mp->int_mask);
226bb6b7 2175 }
3d6b35bc 2176
1fa38c58
LB		 2177 return work_done;
2178}
8fa89bf5 2179
1fa38c58
LB		 2180static inline void oom_timer_wrapper(unsigned long data)
2181{
2182 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 2183
1fa38c58 2184 napi_schedule(&mp->napi);
1da177e4
LT		 2185}
2186
e5371493 2187static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 2188{
45c5d3bc
LB		 2189 int data;
2190
ed94493f 2191 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 2192 if (data < 0)
2193 return;
1da177e4 2194
7f106c1d 2195 data |= BMCR_RESET;
ed94493f 2196 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 2197 return;
1da177e4 2198
c9df406f 2199 do {
ed94493f 2200 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 2201 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 2202}
2203
fc32b0e2 2204static void port_start(struct mv643xx_eth_private *mp)
1da177e4 2205{
d0412d96 2206 u32 pscr;
8a578111 2207 int i;
1da177e4 2208
bedfe324
LB		 2209 /*
2210 * Perform PHY reset, if there is a PHY.
2211 */
ed94493f 2212 if (mp->phy != NULL) {
bedfe324
LB		 2213 struct ethtool_cmd cmd;
2214
2215 mv643xx_eth_get_settings(mp->dev, &cmd);
2216 phy_reset(mp);
2217 mv643xx_eth_set_settings(mp->dev, &cmd);
2218 }
1da177e4 2219
81600eea
LB		 2220 /*
2221 * Configure basic link parameters.
2222 */
37a6084f 2223 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2224
2225 pscr |= SERIAL_PORT_ENABLE;
37a6084f 2226 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2227
2228 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 2229 if (mp->phy == NULL)
81600eea 2230 pscr |= FORCE_LINK_PASS;
37a6084f 2231 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 2232
13d64285
LB		 2233 /*
2234 * Configure TX path and queues.
2235 */
89df5fdc 2236 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 2237 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 2238 struct tx_queue *txq = mp->txq + i;
13d64285 2239
6b368f68 2240 txq_reset_hw_ptr(txq);
89df5fdc
LB		 2241 txq_set_rate(txq, 1000000000, 16777216);
2242 txq_set_fixed_prio_mode(txq);
13d64285
LB		 2243 }
2244
d9a073ea
LB		 2245 /*
2246 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2247 * frames to RX queue #0, and include the pseudo-header when
2248 * calculating receive checksums.
d9a073ea 2249 */
e138f96b 2250 mv643xx_eth_set_features(mp->dev, mp->dev->features);
01999873 2251
376489a2
LB		 2252 /*
2253 * Treat BPDUs as normal multicasts, and disable partition mode.
2254 */
37a6084f 2255 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2256
5a893922
LB		 2257 /*
2258 * Add configured unicast addresses to address filter table.
2259 */
2260 mv643xx_eth_program_unicast_filter(mp->dev);
2261
8a578111 2262 /*
64da80a2 2263 * Enable the receive queues.
8a578111 2264 */
f7981c1c 2265 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2266 struct rx_queue *rxq = mp->rxq + i;
8a578111 2267 u32 addr;
1da177e4 2268
8a578111
LB		 2269 addr = (u32)rxq->rx_desc_dma;
2270 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2271 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2272
8a578111
LB		 2273 rxq_enable(rxq);
2274 }
1da177e4
LT		 2275}
2276
2bcb4b0f
LB		 2277static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2278{
2279 int skb_size;
2280
2281 /*
2282 * Reserve 2+14 bytes for an ethernet header (the hardware
2283 * automatically prepends 2 bytes of dummy data to each
2284 * received packet), 16 bytes for up to four VLAN tags, and
2285 * 4 bytes for the trailing FCS -- 36 bytes total.
2286 */
2287 skb_size = mp->dev->mtu + 36;
2288
2289 /*
2290 * Make sure that the skb size is a multiple of 8 bytes, as
2291 * the lower three bits of the receive descriptor's buffer
2292 * size field are ignored by the hardware.
2293 */
2294 mp->skb_size = (skb_size + 7) & ~7;
7fd96ce4
LB		 2295
2296 /*
2297 * If NET_SKB_PAD is smaller than a cache line,
2298 * netdev_alloc_skb() will cause skb->data to be misaligned
2299 * to a cache line boundary. If this is the case, include
2300 * some extra space to allow re-aligning the data area.
2301 */
2302 mp->skb_size += SKB_DMA_REALIGN;
2bcb4b0f
LB		 2303}
2304
c9df406f 2305static int mv643xx_eth_open(struct net_device *dev)
16e03018 2306{
e5371493 2307 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2308 int err;
64da80a2 2309 int i;
16e03018 2310
37a6084f
LB		 2311 wrlp(mp, INT_CAUSE, 0);
2312 wrlp(mp, INT_CAUSE_EXT, 0);
2313 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2314
fc32b0e2 2315 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2316 IRQF_SHARED, dev->name, dev);
c9df406f 2317 if (err) {
7542db8b 2318 netdev_err(dev, "can't assign irq\n");
c9df406f 2319 return -EAGAIN;
16e03018
DF		 2320 }
2321
2bcb4b0f
LB		 2322 mv643xx_eth_recalc_skb_size(mp);
2323
2257e05c
LB		 2324 napi_enable(&mp->napi);
2325
2bcb4b0f
LB		 2326 skb_queue_head_init(&mp->rx_recycle);
2327
e0ca8410
SB		 2328 mp->int_mask = INT_EXT;
2329
f7981c1c 2330 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2331 err = rxq_init(mp, i);
2332 if (err) {
2333 while (--i >= 0)
f7981c1c 2334 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2335 goto out;
2336 }
2337
1fa38c58 2338 rxq_refill(mp->rxq + i, INT_MAX);
e0ca8410 2339 mp->int_mask |= INT_RX_0 << i;
2257e05c
LB		 2340 }
2341
1319ebad 2342 if (mp->oom) {
2257e05c
LB		 2343 mp->rx_oom.expires = jiffies + (HZ / 10);
2344 add_timer(&mp->rx_oom);
64da80a2 2345 }
8a578111 2346
f7981c1c 2347 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2348 err = txq_init(mp, i);
2349 if (err) {
2350 while (--i >= 0)
f7981c1c 2351 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2352 goto out_free;
2353 }
e0ca8410 2354 mp->int_mask |= INT_TX_END_0 << i;
3d6b35bc 2355 }
16e03018 2356
fc32b0e2 2357 port_start(mp);
16e03018 2358
37a6084f 2359 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
e0ca8410 2360 wrlp(mp, INT_MASK, mp->int_mask);
16e03018 2361
c9df406f
LB		 2362 return 0;
2363
13d64285 2364
fc32b0e2 2365out_free:
f7981c1c
LB		 2366 for (i = 0; i < mp->rxq_count; i++)
2367 rxq_deinit(mp->rxq + i);
fc32b0e2 2368out:
c9df406f
LB		 2369 free_irq(dev->irq, dev);
2370
2371 return err;
16e03018
DF		 2372}
2373
e5371493 2374static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2375{
fc32b0e2 2376 unsigned int data;
64da80a2 2377 int i;
1da177e4 2378
f7981c1c
LB		 2379 for (i = 0; i < mp->rxq_count; i++)
2380 rxq_disable(mp->rxq + i);
2381 for (i = 0; i < mp->txq_count; i++)
2382 txq_disable(mp->txq + i);
ae9ae064
LB		 2383
2384 while (1) {
37a6084f 2385 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2386
2387 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2388 break;
13d64285 2389 udelay(10);
ae9ae064 2390 }
1da177e4 2391
c9df406f 2392 /* Reset the Enable bit in the Configuration Register */
37a6084f 2393 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2394 data &= ~(SERIAL_PORT_ENABLE |
2395 DO_NOT_FORCE_LINK_FAIL |
2396 FORCE_LINK_PASS);
37a6084f 2397 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2398}
2399
c9df406f 2400static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2401{
e5371493 2402 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2403 int i;
1da177e4 2404
fe65e704 2405 wrlp(mp, INT_MASK_EXT, 0x00000000);
37a6084f
LB		 2406 wrlp(mp, INT_MASK, 0x00000000);
2407 rdlp(mp, INT_MASK);
1da177e4 2408
c9df406f 2409 napi_disable(&mp->napi);
78fff83b 2410
2257e05c
LB		 2411 del_timer_sync(&mp->rx_oom);
2412
c9df406f 2413 netif_carrier_off(dev);
1da177e4 2414
fc32b0e2
LB		 2415 free_irq(dev->irq, dev);
2416
cc9754b3 2417 port_reset(mp);
8fd89211 2418 mv643xx_eth_get_stats(dev);
fc32b0e2 2419 mib_counters_update(mp);
57e8f26a 2420 del_timer_sync(&mp->mib_counters_timer);
1da177e4 2421
2bcb4b0f
LB		 2422 skb_queue_purge(&mp->rx_recycle);
2423
f7981c1c
LB		 2424 for (i = 0; i < mp->rxq_count; i++)
2425 rxq_deinit(mp->rxq + i);
2426 for (i = 0; i < mp->txq_count; i++)
2427 txq_deinit(mp->txq + i);
1da177e4 2428
c9df406f 2429 return 0;
1da177e4
LT		 2430}
2431
fc32b0e2 2432static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2433{
e5371493 2434 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2435
ed94493f 2436 if (mp->phy != NULL)
28b04113 2437 return phy_mii_ioctl(mp->phy, ifr, cmd);
bedfe324
LB		 2438
2439 return -EOPNOTSUPP;
1da177e4
LT		 2440}
2441
c9df406f 2442static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2443{
89df5fdc
LB		 2444 struct mv643xx_eth_private *mp = netdev_priv(dev);
2445
fc32b0e2 2446 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2447 return -EINVAL;
1da177e4 2448
c9df406f 2449 dev->mtu = new_mtu;
2bcb4b0f 2450 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2451 tx_set_rate(mp, 1000000000, 16777216);
2452
c9df406f
LB		 2453 if (!netif_running(dev))
2454 return 0;
1da177e4 2455
c9df406f
LB		 2456 /*
2457 * Stop and then re-open the interface. This will allocate RX
2458 * skbs of the new MTU.
2459 * There is a possible danger that the open will not succeed,
fc32b0e2 2460 * due to memory being full.
c9df406f
LB		 2461 */
2462 mv643xx_eth_stop(dev);
2463 if (mv643xx_eth_open(dev)) {
7542db8b
JP		 2464 netdev_err(dev,
2465 "fatal error on re-opening device after MTU change\n");
c9df406f
LB		 2466 }
2467
2468 return 0;
1da177e4
LT		 2469}
2470
fc32b0e2 2471static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2472{
fc32b0e2 2473 struct mv643xx_eth_private *mp;
1da177e4 2474
fc32b0e2
LB		 2475 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2476 if (netif_running(mp->dev)) {
e5ef1de1 2477 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2478 port_reset(mp);
2479 port_start(mp);
e5ef1de1 2480 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2481 }
c9df406f
LB		 2482}
2483
c9df406f 2484static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2485{
e5371493 2486 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2487
7542db8b 2488 netdev_info(dev, "tx timeout\n");
d0412d96 2489
c9df406f 2490 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2491}
2492
c9df406f 2493#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2494static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2495{
fc32b0e2 2496 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2497
37a6084f
LB		 2498 wrlp(mp, INT_MASK, 0x00000000);
2499 rdlp(mp, INT_MASK);
c9df406f 2500
fc32b0e2 2501 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2502
e0ca8410 2503 wrlp(mp, INT_MASK, mp->int_mask);
9f8dd319 2504}
c9df406f 2505#endif
9f8dd319 2506
9f8dd319 2507
c9df406f 2508/* platform glue ************************************************************/
e5371493
LB		 2509static void
2510mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2511 struct mbus_dram_target_info *dram)
c9df406f 2512{
cc9754b3 2513 void __iomem *base = msp->base;
c9df406f
LB		 2514 u32 win_enable;
2515 u32 win_protect;
2516 int i;
9f8dd319 2517
c9df406f
LB		 2518 for (i = 0; i < 6; i++) {
2519 writel(0, base + WINDOW_BASE(i));
2520 writel(0, base + WINDOW_SIZE(i));
2521 if (i < 4)
2522 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2523 }
2524
c9df406f
LB		 2525 win_enable = 0x3f;
2526 win_protect = 0;
2527
2528 for (i = 0; i < dram->num_cs; i++) {
2529 struct mbus_dram_window *cs = dram->cs + i;
2530
2531 writel((cs->base & 0xffff0000) |
2532 (cs->mbus_attr << 8) |
2533 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2534 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2535
2536 win_enable &= ~(1 << i);
2537 win_protect |= 3 << (2 * i);
2538 }
2539
2540 writel(win_enable, base + WINDOW_BAR_ENABLE);
2541 msp->win_protect = win_protect;
9f8dd319
DF		 2542}
2543
773fc3ee
LB		 2544static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2545{
2546 /*
2547 * Check whether we have a 14-bit coal limit field in bits
2548 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2549 * SDMA config register.
2550 */
37a6084f
LB		 2551 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2552 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2553 msp->extended_rx_coal_limit = 1;
2554 else
2555 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2556
2557 /*
457b1d5a
LB		 2558 * Check whether the MAC supports TX rate control, and if
2559 * yes, whether its associated registers are in the old or
2560 * the new place.
1e881592 2561 */
37a6084f
LB		 2562 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2563 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2564 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2565 } else {
37a6084f
LB		 2566 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2567 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2568 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2569 else
2570 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2571 }
773fc3ee
LB		 2572}
2573
c9df406f 2574static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2575{
10a9948d 2576 static int mv643xx_eth_version_printed;
c9df406f 2577 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2578 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2579 struct resource *res;
2580 int ret;
9f8dd319 2581
e5371493 2582 if (!mv643xx_eth_version_printed++)
7542db8b
JP		 2583 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2584 mv643xx_eth_driver_version);
9f8dd319 2585
c9df406f
LB		 2586 ret = -EINVAL;
2587 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2588 if (res == NULL)
2589 goto out;
9f8dd319 2590
c9df406f 2591 ret = -ENOMEM;
beae22e6 2592 msp = kzalloc(sizeof(*msp), GFP_KERNEL);
c9df406f
LB		 2593 if (msp == NULL)
2594 goto out;
c9df406f 2595
cc9754b3
LB		 2596 msp->base = ioremap(res->start, res->end - res->start + 1);
2597 if (msp->base == NULL)
c9df406f
LB		 2598 goto out_free;
2599
ed94493f
LB		 2600 /*
2601 * Set up and register SMI bus.
2602 */
2603 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2604 msp->smi_bus = mdiobus_alloc();
2605 if (msp->smi_bus == NULL)
ed94493f 2606 goto out_unmap;
298cf9be
LB		 2607
2608 msp->smi_bus->priv = msp;
2609 msp->smi_bus->name = "mv643xx_eth smi";
2610 msp->smi_bus->read = smi_bus_read;
2611 msp->smi_bus->write = smi_bus_write,
2612 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2613 msp->smi_bus->parent = &pdev->dev;
2614 msp->smi_bus->phy_mask = 0xffffffff;
2615 if (mdiobus_register(msp->smi_bus) < 0)
2616 goto out_free_mii_bus;
ed94493f
LB		 2617 msp->smi = msp;
2618 } else {
fc0eb9f2 2619 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2620 }
c9df406f 2621
45c5d3bc
LB		 2622 msp->err_interrupt = NO_IRQ;
2623 init_waitqueue_head(&msp->smi_busy_wait);
2624
2625 /*
2626 * Check whether the error interrupt is hooked up.
2627 */
2628 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2629 if (res != NULL) {
2630 int err;
2631
2632 err = request_irq(res->start, mv643xx_eth_err_irq,
2633 IRQF_SHARED, "mv643xx_eth", msp);
2634 if (!err) {
2635 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2636 msp->err_interrupt = res->start;
2637 }
2638 }
2639
c9df406f
LB		 2640 /*
2641 * (Re-)program MBUS remapping windows if we are asked to.
2642 */
2643 if (pd != NULL && pd->dram != NULL)
2644 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2645
fc32b0e2
LB		 2646 /*
2647 * Detect hardware parameters.
2648 */
2649 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
50a749c1
DC		 2650 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2651 pd->tx_csum_limit : 9 * 1024;
773fc3ee 2652 infer_hw_params(msp);
fc32b0e2
LB		 2653
2654 platform_set_drvdata(pdev, msp);
2655
c9df406f
LB		 2656 return 0;
2657
298cf9be
LB		 2658out_free_mii_bus:
2659 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2660out_unmap:
2661 iounmap(msp->base);
c9df406f
LB		 2662out_free:
2663 kfree(msp);
2664out:
2665 return ret;
2666}
2667
2668static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2669{
e5371493 2670 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2671 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2672
298cf9be 2673 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be 2674 mdiobus_unregister(msp->smi_bus);
bcb3336c 2675 mdiobus_free(msp->smi_bus);
298cf9be 2676 }
45c5d3bc
LB		 2677 if (msp->err_interrupt != NO_IRQ)
2678 free_irq(msp->err_interrupt, msp);
cc9754b3 2679 iounmap(msp->base);
c9df406f
LB		 2680 kfree(msp);
2681
2682 return 0;
9f8dd319
DF		 2683}
2684
c9df406f 2685static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2686 .probe = mv643xx_eth_shared_probe,
2687 .remove = mv643xx_eth_shared_remove,
c9df406f 2688 .driver = {
fc32b0e2 2689 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2690 .owner = THIS_MODULE,
2691 },
2692};
2693
e5371493 2694static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2695{
c9df406f 2696 int addr_shift = 5 * mp->port_num;
fc32b0e2 2697 u32 data;
1da177e4 2698
fc32b0e2
LB		 2699 data = rdl(mp, PHY_ADDR);
2700 data &= ~(0x1f << addr_shift);
2701 data |= (phy_addr & 0x1f) << addr_shift;
2702 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2703}
2704
e5371493 2705static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2706{
fc32b0e2
LB		 2707 unsigned int data;
2708
2709 data = rdl(mp, PHY_ADDR);
2710
2711 return (data >> (5 * mp->port_num)) & 0x1f;
2712}
2713
2714static void set_params(struct mv643xx_eth_private *mp,
2715 struct mv643xx_eth_platform_data *pd)
2716{
2717 struct net_device *dev = mp->dev;
2718
2719 if (is_valid_ether_addr(pd->mac_addr))
2720 memcpy(dev->dev_addr, pd->mac_addr, 6);
2721 else
2722 uc_addr_get(mp, dev->dev_addr);
2723
e7d2f4db 2724 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
fc32b0e2 2725 if (pd->rx_queue_size)
e7d2f4db 2726 mp->rx_ring_size = pd->rx_queue_size;
fc32b0e2
LB		 2727 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2728 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2729
f7981c1c 2730 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2731
e7d2f4db 2732 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
fc32b0e2 2733 if (pd->tx_queue_size)
e7d2f4db 2734 mp->tx_ring_size = pd->tx_queue_size;
fc32b0e2
LB		 2735 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2736 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2737
f7981c1c 2738 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2739}
2740
ed94493f
LB		 2741static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2742 int phy_addr)
1da177e4 2743{
298cf9be 2744 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2745 struct phy_device *phydev;
2746 int start;
2747 int num;
2748 int i;
45c5d3bc 2749
ed94493f
LB		 2750 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2751 start = phy_addr_get(mp) & 0x1f;
2752 num = 32;
2753 } else {
2754 start = phy_addr & 0x1f;
2755 num = 1;
2756 }
45c5d3bc 2757
ed94493f
LB		 2758 phydev = NULL;
2759 for (i = 0; i < num; i++) {
2760 int addr = (start + i) & 0x1f;
fc32b0e2 2761
ed94493f
LB		 2762 if (bus->phy_map[addr] == NULL)
2763 mdiobus_scan(bus, addr);
1da177e4 2764
ed94493f
LB		 2765 if (phydev == NULL) {
2766 phydev = bus->phy_map[addr];
2767 if (phydev != NULL)
2768 phy_addr_set(mp, addr);
2769 }
2770 }
1da177e4 2771
ed94493f 2772 return phydev;
1da177e4
LT		 2773}
2774
ed94493f 2775static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2776{
ed94493f 2777 struct phy_device *phy = mp->phy;
c28a4f89 2778
fc32b0e2
LB		 2779 phy_reset(mp);
2780
db1d7bf7 2781 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
ed94493f
LB		 2782
2783 if (speed == 0) {
2784 phy->autoneg = AUTONEG_ENABLE;
2785 phy->speed = 0;
2786 phy->duplex = 0;
2787 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2788 } else {
ed94493f
LB		 2789 phy->autoneg = AUTONEG_DISABLE;
2790 phy->advertising = 0;
2791 phy->speed = speed;
2792 phy->duplex = duplex;
c9df406f 2793 }
ed94493f 2794 phy_start_aneg(phy);
c28a4f89
JC		 2795}
2796
81600eea
LB		 2797static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2798{
2799 u32 pscr;
2800
37a6084f 2801 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2802 if (pscr & SERIAL_PORT_ENABLE) {
2803 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2804 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2805 }
2806
2807 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2808 if (mp->phy == NULL) {
81600eea
LB		 2809 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2810 if (speed == SPEED_1000)
2811 pscr |= SET_GMII_SPEED_TO_1000;
2812 else if (speed == SPEED_100)
2813 pscr |= SET_MII_SPEED_TO_100;
2814
2815 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2816
2817 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2818 if (duplex == DUPLEX_FULL)
2819 pscr |= SET_FULL_DUPLEX_MODE;
2820 }
2821
37a6084f 2822 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2823}
2824
ea8a8642
LB		 2825static const struct net_device_ops mv643xx_eth_netdev_ops = {
2826 .ndo_open = mv643xx_eth_open,
2827 .ndo_stop = mv643xx_eth_stop,
2828 .ndo_start_xmit = mv643xx_eth_xmit,
2829 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2830 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
1d4bd947 2831 .ndo_validate_addr = eth_validate_addr,
ea8a8642
LB		 2832 .ndo_do_ioctl = mv643xx_eth_ioctl,
2833 .ndo_change_mtu = mv643xx_eth_change_mtu,
aad59c43 2834 .ndo_set_features = mv643xx_eth_set_features,
ea8a8642
LB		 2835 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2836 .ndo_get_stats = mv643xx_eth_get_stats,
2837#ifdef CONFIG_NET_POLL_CONTROLLER
2838 .ndo_poll_controller = mv643xx_eth_netpoll,
2839#endif
2840};
2841
c9df406f 2842static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2843{
c9df406f 2844 struct mv643xx_eth_platform_data *pd;
e5371493 2845 struct mv643xx_eth_private *mp;
c9df406f 2846 struct net_device *dev;
c9df406f 2847 struct resource *res;
fc32b0e2 2848 int err;
1da177e4 2849
c9df406f
LB		 2850 pd = pdev->dev.platform_data;
2851 if (pd == NULL) {
7542db8b 2852 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2853 return -ENODEV;
2854 }
1da177e4 2855
c9df406f 2856 if (pd->shared == NULL) {
7542db8b 2857 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2858 return -ENODEV;
2859 }
8f518703 2860
e5ef1de1 2861 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2862 if (!dev)
2863 return -ENOMEM;
1da177e4 2864
c9df406f 2865 mp = netdev_priv(dev);
fc32b0e2
LB		 2866 platform_set_drvdata(pdev, mp);
2867
2868 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2869 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2870 mp->port_num = pd->port_number;
2871
c9df406f 2872 mp->dev = dev;
78fff83b 2873
fc32b0e2 2874 set_params(mp, pd);
206d6b32
BH		 2875 netif_set_real_num_tx_queues(dev, mp->txq_count);
2876 netif_set_real_num_rx_queues(dev, mp->rxq_count);
fc32b0e2 2877
ed94493f
LB		 2878 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2879 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2880
6bdf576e 2881 if (mp->phy != NULL)
ed94493f 2882 phy_init(mp, pd->speed, pd->duplex);
6bdf576e
LB		 2883
2884 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
ed94493f 2885
81600eea 2886 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2887
4ff3495a
LB		 2888
2889 mib_counters_clear(mp);
2890
2891 init_timer(&mp->mib_counters_timer);
2892 mp->mib_counters_timer.data = (unsigned long)mp;
2893 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2894 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2895 add_timer(&mp->mib_counters_timer);
2896
2897 spin_lock_init(&mp->mib_counters_lock);
2898
2899 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2900
2257e05c
LB		 2901 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2902
2903 init_timer(&mp->rx_oom);
2904 mp->rx_oom.data = (unsigned long)mp;
2905 mp->rx_oom.function = oom_timer_wrapper;
2906
fc32b0e2 2907
c9df406f
LB		 2908 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2909 BUG_ON(!res);
2910 dev->irq = res->start;
1da177e4 2911
ea8a8642
LB		 2912 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2913
c9df406f
LB		 2914 dev->watchdog_timeo = 2 * HZ;
2915 dev->base_addr = 0;
1da177e4 2916
aad59c43
MM		 2917 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
2918 NETIF_F_RXCSUM | NETIF_F_LRO;
2919 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
e32b6617 2920 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2921
fc32b0e2 2922 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2923
c9df406f 2924 if (mp->shared->win_protect)
fc32b0e2 2925 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2926
a5fe3616
LB		 2927 netif_carrier_off(dev);
2928
b5e86db4
LB		 2929 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2930
4fb0a54a 2931 set_rx_coal(mp, 250);
a5fe3616
LB		 2932 set_tx_coal(mp, 0);
2933
c9df406f
LB		 2934 err = register_netdev(dev);
2935 if (err)
2936 goto out;
1da177e4 2937
7542db8b
JP		 2938 netdev_notice(dev, "port %d with MAC address %pM\n",
2939 mp->port_num, dev->dev_addr);
1da177e4 2940
13d64285 2941 if (mp->tx_desc_sram_size > 0)
7542db8b 2942 netdev_notice(dev, "configured with sram\n");
1da177e4 2943
c9df406f 2944 return 0;
1da177e4 2945
c9df406f
LB		 2946out:
2947 free_netdev(dev);
1da177e4 2948
c9df406f 2949 return err;
1da177e4
LT		 2950}
2951
c9df406f 2952static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2953{
fc32b0e2 2954 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2955
fc32b0e2 2956 unregister_netdev(mp->dev);
ed94493f
LB		 2957 if (mp->phy != NULL)
2958 phy_detach(mp->phy);
23f333a2 2959 cancel_work_sync(&mp->tx_timeout_task);
fc32b0e2 2960 free_netdev(mp->dev);
c9df406f 2961
c9df406f 2962 platform_set_drvdata(pdev, NULL);
fc32b0e2 2963
c9df406f 2964 return 0;
1da177e4
LT		 2965}
2966
c9df406f 2967static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2968{
fc32b0e2 2969 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2970
c9df406f 2971 /* Mask all interrupts on ethernet port */
37a6084f
LB		 2972 wrlp(mp, INT_MASK, 0);
2973 rdlp(mp, INT_MASK);
c9df406f 2974
fc32b0e2
LB		 2975 if (netif_running(mp->dev))
2976 port_reset(mp);
d0412d96
JC		 2977}
2978
c9df406f 2979static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2980 .probe = mv643xx_eth_probe,
2981 .remove = mv643xx_eth_remove,
2982 .shutdown = mv643xx_eth_shutdown,
c9df406f 2983 .driver = {
fc32b0e2 2984 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2985 .owner = THIS_MODULE,
2986 },
2987};
2988
e5371493 2989static int __init mv643xx_eth_init_module(void)
d0412d96 2990{
c9df406f 2991 int rc;
d0412d96 2992
c9df406f
LB		 2993 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2994 if (!rc) {
2995 rc = platform_driver_register(&mv643xx_eth_driver);
2996 if (rc)
2997 platform_driver_unregister(&mv643xx_eth_shared_driver);
2998 }
fc32b0e2 2999
c9df406f 3000 return rc;
d0412d96 3001}
fc32b0e2 3002module_init(mv643xx_eth_init_module);
d0412d96 3003
e5371493 3004static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 3005{
c9df406f
LB		 3006 platform_driver_unregister(&mv643xx_eth_driver);
3007 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 3008}
e5371493 3009module_exit(mv643xx_eth_cleanup_module);
1da177e4 3010
45675bc6
LB		 3011MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3012 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 3013MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 3014MODULE_LICENSE("GPL");
c9df406f 3015MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 3016MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux 6.x block layer and io_uring tree(s)