[linux-2.6-block.git] / drivers / net / mlx4 / mlx4_en.h

/*
 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

#ifndef _MLX4_EN_H_
#define _MLX4_EN_H_

#include <linux/compiler.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/netdevice.h>
#include <linux/inet_lro.h>

#include <linux/mlx4/device.h>
#include <linux/mlx4/qp.h>
#include <linux/mlx4/cq.h>
#include <linux/mlx4/srq.h>
#include <linux/mlx4/doorbell.h>

#include "en_port.h"

#define DRV_NAME	"mlx4_en"
#define DRV_VERSION	"1.4.1.1"
#define DRV_RELDATE	"June 2009"

#define MLX4_EN_MSG_LEVEL	(NETIF_MSG_LINK | NETIF_MSG_IFDOWN)

/*
 * Device constants
 */


#define MLX4_EN_PAGE_SHIFT	12
#define MLX4_EN_PAGE_SIZE	(1 << MLX4_EN_PAGE_SHIFT)
#define MAX_TX_RINGS		16
#define MAX_RX_RINGS		16
#define TXBB_SIZE		64
#define HEADROOM		(2048 / TXBB_SIZE + 1)
#define STAMP_STRIDE		64
#define STAMP_DWORDS		(STAMP_STRIDE / 4)
#define STAMP_SHIFT		31
#define STAMP_VAL		0x7fffffff
#define STATS_DELAY		(HZ / 4)

/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
#define MAX_DESC_SIZE		512
#define MAX_DESC_TXBBS		(MAX_DESC_SIZE / TXBB_SIZE)

/*
 * OS related constants and tunables
 */

#define MLX4_EN_WATCHDOG_TIMEOUT	(15 * HZ)

#define MLX4_EN_ALLOC_ORDER	2
#define MLX4_EN_ALLOC_SIZE	(PAGE_SIZE << MLX4_EN_ALLOC_ORDER)

#define MLX4_EN_MAX_LRO_DESCRIPTORS	32

/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
 * and 4K allocations) */
enum {
	FRAG_SZ0 = 512 - NET_IP_ALIGN,
	FRAG_SZ1 = 1024,
	FRAG_SZ2 = 4096,
	FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
};
#define MLX4_EN_MAX_RX_FRAGS	4

/* Maximum ring sizes */
#define MLX4_EN_MAX_TX_SIZE	8192
#define MLX4_EN_MAX_RX_SIZE	8192

/* Minimum ring size for our page-allocation sceme to work */
#define MLX4_EN_MIN_RX_SIZE	(MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
#define MLX4_EN_MIN_TX_SIZE	(4096 / TXBB_SIZE)

#define MLX4_EN_SMALL_PKT_SIZE		64
#define MLX4_EN_NUM_TX_RINGS		8
#define MLX4_EN_NUM_PPP_RINGS		8
#define MLX4_EN_DEF_TX_RING_SIZE	512
#define MLX4_EN_DEF_RX_RING_SIZE  	1024

/* Target number of packets to coalesce with interrupt moderation */
#define MLX4_EN_RX_COAL_TARGET	44
#define MLX4_EN_RX_COAL_TIME	0x10

#define MLX4_EN_TX_COAL_PKTS	5
#define MLX4_EN_TX_COAL_TIME	0x80

#define MLX4_EN_RX_RATE_LOW		400000
#define MLX4_EN_RX_COAL_TIME_LOW	0
#define MLX4_EN_RX_RATE_HIGH		450000
#define MLX4_EN_RX_COAL_TIME_HIGH	128
#define MLX4_EN_RX_SIZE_THRESH		1024
#define MLX4_EN_RX_RATE_THRESH		(1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
#define MLX4_EN_SAMPLE_INTERVAL		0

#define MLX4_EN_AUTO_CONF	0xffff

#define MLX4_EN_DEF_RX_PAUSE	1
#define MLX4_EN_DEF_TX_PAUSE	1

/* Interval between successive polls in the Tx routine when polling is used
   instead of interrupts (in per-core Tx rings) - should be power of 2 */
#define MLX4_EN_TX_POLL_MODER	16
#define MLX4_EN_TX_POLL_TIMEOUT	(HZ / 4)

#define ETH_LLC_SNAP_SIZE	8

#define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
#define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)

#define MLX4_EN_MIN_MTU		46
#define ETH_BCAST		0xffffffffffffULL

#ifdef MLX4_EN_PERF_STAT
/* Number of samples to 'average' */
#define AVG_SIZE			128
#define AVG_FACTOR			1024
#define NUM_PERF_STATS			NUM_PERF_COUNTERS

#define INC_PERF_COUNTER(cnt)		(++(cnt))
#define ADD_PERF_COUNTER(cnt, add)	((cnt) += (add))
#define AVG_PERF_COUNTER(cnt, sample) \
	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
#define GET_PERF_COUNTER(cnt)		(cnt)
#define GET_AVG_PERF_COUNTER(cnt)	((cnt) / AVG_FACTOR)

#else

#define NUM_PERF_STATS			0
#define INC_PERF_COUNTER(cnt)		do {} while (0)
#define ADD_PERF_COUNTER(cnt, add)	do {} while (0)
#define AVG_PERF_COUNTER(cnt, sample)	do {} while (0)
#define GET_PERF_COUNTER(cnt)		(0)
#define GET_AVG_PERF_COUNTER(cnt)	(0)
#endif /* MLX4_EN_PERF_STAT */

/*
 * Configurables
 */

enum cq_type {
	RX = 0,
	TX = 1,
};


/*
 * Useful macros
 */
#define ROUNDUP_LOG2(x)		ilog2(roundup_pow_of_two(x))
#define XNOR(x, y)		(!(x) == !(y))
#define ILLEGAL_MAC(addr)	(addr == 0xffffffffffffULL || addr == 0x0)


struct mlx4_en_tx_info {
	struct sk_buff *skb;
	u32 nr_txbb;
	u8 linear;
	u8 data_offset;
	u8 inl;
};


#define MLX4_EN_BIT_DESC_OWN	0x80000000
#define CTRL_SIZE	sizeof(struct mlx4_wqe_ctrl_seg)
#define MLX4_EN_MEMTYPE_PAD	0x100
#define DS_SIZE		sizeof(struct mlx4_wqe_data_seg)


struct mlx4_en_tx_desc {
	struct mlx4_wqe_ctrl_seg ctrl;
	union {
		struct mlx4_wqe_data_seg data; /* at least one data segment */
		struct mlx4_wqe_lso_seg lso;
		struct mlx4_wqe_inline_seg inl;
	};
};

#define MLX4_EN_USE_SRQ		0x01000000

struct mlx4_en_rx_alloc {
	struct page *page;
	u16 offset;
};

struct mlx4_en_tx_ring {
	struct mlx4_hwq_resources wqres;
	u32 size ; /* number of TXBBs */
	u32 size_mask;
	u16 stride;
	u16 cqn;	/* index of port CQ associated with this ring */
	u32 prod;
	u32 cons;
	u32 buf_size;
	u32 doorbell_qpn;
	void *buf;
	u16 poll_cnt;
	int blocked;
	struct mlx4_en_tx_info *tx_info;
	u8 *bounce_buf;
	u32 last_nr_txbb;
	struct mlx4_qp qp;
	struct mlx4_qp_context context;
	int qpn;
	enum mlx4_qp_state qp_state;
	struct mlx4_srq dummy;
	unsigned long bytes;
	unsigned long packets;
	spinlock_t comp_lock;
};

struct mlx4_en_rx_desc {
	/* actual number of entries depends on rx ring stride */
	struct mlx4_wqe_data_seg data[0];
};

struct mlx4_en_rx_ring {
	struct mlx4_hwq_resources wqres;
	struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
	struct net_lro_mgr lro;
	u32 size ;	/* number of Rx descs*/
	u32 actual_size;
	u32 size_mask;
	u16 stride;
	u16 log_stride;
	u16 cqn;	/* index of port CQ associated with this ring */
	u32 prod;
	u32 cons;
	u32 buf_size;
	void *buf;
	void *rx_info;
	unsigned long bytes;
	unsigned long packets;
};


static inline int mlx4_en_can_lro(__be16 status)
{
	return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4	|
				     MLX4_CQE_STATUS_IPV4F	|
				     MLX4_CQE_STATUS_IPV6	|
				     MLX4_CQE_STATUS_IPV4OPT	|
				     MLX4_CQE_STATUS_TCP	|
				     MLX4_CQE_STATUS_UDP	|
				     MLX4_CQE_STATUS_IPOK)) ==
		cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
			    MLX4_CQE_STATUS_IPOK |
			    MLX4_CQE_STATUS_TCP);
}

struct mlx4_en_cq {
	struct mlx4_cq          mcq;
	struct mlx4_hwq_resources wqres;
	int                     ring;
	spinlock_t              lock;
	struct net_device      *dev;
	struct napi_struct	napi;
	/* Per-core Tx cq processing support */
	struct timer_list timer;
	int size;
	int buf_size;
	unsigned vector;
	enum cq_type is_tx;
	u16 moder_time;
	u16 moder_cnt;
	struct mlx4_cqe *buf;
#define MLX4_EN_OPCODE_ERROR	0x1e
};

struct mlx4_en_port_profile {
	u32 flags;
	u32 tx_ring_num;
	u32 rx_ring_num;
	u32 tx_ring_size;
	u32 rx_ring_size;
	u8 rx_pause;
	u8 rx_ppp;
	u8 tx_pause;
	u8 tx_ppp;
};

struct mlx4_en_profile {
	int rss_xor;
	int num_lro;
	u8 rss_mask;
	u32 active_ports;
	u32 small_pkt_int;
	u8 no_reset;
	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
};

struct mlx4_en_dev {
	struct mlx4_dev         *dev;
	struct pci_dev		*pdev;
	struct mutex		state_lock;
	struct net_device       *pndev[MLX4_MAX_PORTS + 1];
	u32                     port_cnt;
	bool			device_up;
	struct mlx4_en_profile  profile;
	u32			LSO_support;
	struct workqueue_struct *workqueue;
	struct device           *dma_device;
	void __iomem            *uar_map;
	struct mlx4_uar         priv_uar;
	struct mlx4_mr		mr;
	u32                     priv_pdn;
	spinlock_t              uar_lock;
};


struct mlx4_en_rss_map {
	int base_qpn;
	struct mlx4_qp qps[MAX_RX_RINGS];
	enum mlx4_qp_state state[MAX_RX_RINGS];
	struct mlx4_qp indir_qp;
	enum mlx4_qp_state indir_state;
};

struct mlx4_en_rss_context {
	__be32 base_qpn;
	__be32 default_qpn;
	u16 reserved;
	u8 hash_fn;
	u8 flags;
	__be32 rss_key[10];
};

struct mlx4_en_pkt_stats {
	unsigned long broadcast;
	unsigned long rx_prio[8];
	unsigned long tx_prio[8];
#define NUM_PKT_STATS		17
};

struct mlx4_en_port_stats {
	unsigned long lro_aggregated;
	unsigned long lro_flushed;
	unsigned long lro_no_desc;
	unsigned long tso_packets;
	unsigned long queue_stopped;
	unsigned long wake_queue;
	unsigned long tx_timeout;
	unsigned long rx_alloc_failed;
	unsigned long rx_chksum_good;
	unsigned long rx_chksum_none;
	unsigned long tx_chksum_offload;
#define NUM_PORT_STATS		11
};

struct mlx4_en_perf_stats {
	u32 tx_poll;
	u64 tx_pktsz_avg;
	u32 inflight_avg;
	u16 tx_coal_avg;
	u16 rx_coal_avg;
	u32 napi_quota;
#define NUM_PERF_COUNTERS		6
};

struct mlx4_en_frag_info {
	u16 frag_size;
	u16 frag_prefix_size;
	u16 frag_stride;
	u16 frag_align;
	u16 last_offset;

};

struct mlx4_en_priv {
	struct mlx4_en_dev *mdev;
	struct mlx4_en_port_profile *prof;
	struct net_device *dev;
	struct vlan_group *vlgrp;
	struct net_device_stats stats;
	struct net_device_stats ret_stats;
	spinlock_t stats_lock;

	unsigned long last_moder_packets;
	unsigned long last_moder_tx_packets;
	unsigned long last_moder_bytes;
	unsigned long last_moder_jiffies;
	int last_moder_time;
	u16 rx_usecs;
	u16 rx_frames;
	u16 tx_usecs;
	u16 tx_frames;
	u32 pkt_rate_low;
	u16 rx_usecs_low;
	u32 pkt_rate_high;
	u16 rx_usecs_high;
	u16 sample_interval;
	u16 adaptive_rx_coal;
	u32 msg_enable;

	struct mlx4_hwq_resources res;
	int link_state;
	int last_link_state;
	bool port_up;
	int port;
	int registered;
	int allocated;
	int stride;
	int rx_csum;
	u64 mac;
	int mac_index;
	unsigned max_mtu;
	int base_qpn;

	struct mlx4_en_rss_map rss_map;
	u32 flags;
#define MLX4_EN_FLAG_PROMISC	0x1
	u32 tx_ring_num;
	u32 rx_ring_num;
	u32 rx_skb_size;
	struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
	u16 num_frags;
	u16 log_rx_info;

	struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
	struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
	struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
	struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
	struct work_struct mcast_task;
	struct work_struct mac_task;
	struct work_struct watchdog_task;
	struct work_struct linkstate_task;
	struct delayed_work stats_task;
	struct mlx4_en_perf_stats pstats;
	struct mlx4_en_pkt_stats pkstats;
	struct mlx4_en_port_stats port_stats;
	char *mc_addrs;
	int mc_addrs_cnt;
	struct mlx4_en_stat_out_mbox hw_stats;
	int vids[128];
};


void mlx4_en_destroy_netdev(struct net_device *dev);
int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
			struct mlx4_en_port_profile *prof);

int mlx4_en_start_port(struct net_device *dev);
void mlx4_en_stop_port(struct net_device *dev);

void mlx4_en_free_resources(struct mlx4_en_priv *priv);
int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);

int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
		      int entries, int ring, enum cq_type mode);
void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);

void mlx4_en_poll_tx_cq(unsigned long data);
void mlx4_en_tx_irq(struct mlx4_cq *mcq);
u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);

int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
			   u32 size, u16 stride);
void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
			     struct mlx4_en_tx_ring *ring,
			     int cq);
void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
				struct mlx4_en_tx_ring *ring);

int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
			   struct mlx4_en_rx_ring *ring,
			   u32 size, u16 stride);
void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
			     struct mlx4_en_rx_ring *ring);
int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
				struct mlx4_en_rx_ring *ring);
int mlx4_en_process_rx_cq(struct net_device *dev,
			  struct mlx4_en_cq *cq,
			  int budget);
int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
			     int is_tx, int rss, int qpn, int cqn,
			     struct mlx4_qp_context *context);
void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
int mlx4_en_map_buffer(struct mlx4_buf *buf);
void mlx4_en_unmap_buffer(struct mlx4_buf *buf);

void mlx4_en_calc_rx_buf(struct net_device *dev);
int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
void mlx4_en_rx_irq(struct mlx4_cq *mcq);

int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp);
int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
			  u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
			   u8 promisc);

int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);

/*
 * Globals
 */
extern const struct ethtool_ops mlx4_en_ethtool_ops;


/*
 * printk / logging functions
 */

int en_print(const char *level, const struct mlx4_en_priv *priv,
	     const char *format, ...) __attribute__ ((format (printf, 3, 4)));

#define en_dbg(mlevel, priv, format, arg...)			\
do {								\
	if (NETIF_MSG_##mlevel & priv->msg_enable)		\
		en_print(KERN_DEBUG, priv, format, ##arg);	\
} while (0)
#define en_warn(priv, format, arg...)			\
	en_print(KERN_WARNING, priv, format, ##arg)
#define en_err(priv, format, arg...)			\
	en_print(KERN_ERR, priv, format, ##arg)

#define mlx4_err(mdev, format, arg...)			\
	pr_err("%s %s: " format, DRV_NAME,		\
	       dev_name(&mdev->pdev->dev), ##arg)
#define mlx4_info(mdev, format, arg...)			\
	pr_info("%s %s: " format, DRV_NAME,		\
		dev_name(&mdev->pdev->dev), ##arg)
#define mlx4_warn(mdev, format, arg...)			\
	pr_warning("%s %s: " format, DRV_NAME,		\
		   dev_name(&mdev->pdev->dev), ##arg)

#endif
Commit	Line	Data
c27a02cd YP	1	/*
	2	* Copyright (c) 2007 Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*
	32	*/
	33
	34	#ifndef _MLX4_EN_H_
	35	#define _MLX4_EN_H_
	36
	37	#include <linux/compiler.h>
	38	#include <linux/list.h>
	39	#include <linux/mutex.h>
	40	#include <linux/netdevice.h>
	41	#include <linux/inet_lro.h>
	42
	43	#include <linux/mlx4/device.h>
	44	#include <linux/mlx4/qp.h>
	45	#include <linux/mlx4/cq.h>
	46	#include <linux/mlx4/srq.h>
	47	#include <linux/mlx4/doorbell.h>
	48
	49	#include "en_port.h"
	50
	51	#define DRV_NAME "mlx4_en"
d455e5b1 YP	52	#define DRV_VERSION "1.4.1.1"
d455e5b1 YP	53	#define DRV_RELDATE "June 2009"
c27a02cd	54
c27a02cd YP	55	#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK \| NETIF_MSG_IFDOWN)
c27a02cd YP	56
c27a02cd YP	57	/*
	58	* Device constants
	59	*/
	60
	61
	62	#define MLX4_EN_PAGE_SHIFT 12
	63	#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
	64	#define MAX_TX_RINGS 16
	65	#define MAX_RX_RINGS 16
c27a02cd YP	66	#define TXBB_SIZE 64
c27a02cd YP	67	#define HEADROOM (2048 / TXBB_SIZE + 1)
c27a02cd YP	68	#define STAMP_STRIDE 64
	69	#define STAMP_DWORDS (STAMP_STRIDE / 4)
	70	#define STAMP_SHIFT 31
	71	#define STAMP_VAL 0x7fffffff
	72	#define STATS_DELAY (HZ / 4)
	73
	74	/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
	75	#define MAX_DESC_SIZE 512
	76	#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
	77
	78	/*
	79	* OS related constants and tunables
	80	*/
	81
	82	#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
	83
	84	#define MLX4_EN_ALLOC_ORDER 2
	85	#define MLX4_EN_ALLOC_SIZE (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
	86
	87	#define MLX4_EN_MAX_LRO_DESCRIPTORS 32
	88
	89	/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
	90	* and 4K allocations) */
	91	enum {
	92	FRAG_SZ0 = 512 - NET_IP_ALIGN,
	93	FRAG_SZ1 = 1024,
	94	FRAG_SZ2 = 4096,
	95	FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
	96	};
	97	#define MLX4_EN_MAX_RX_FRAGS 4
	98
bd531e36 YP	99	/* Maximum ring sizes */
	100	#define MLX4_EN_MAX_TX_SIZE 8192
	101	#define MLX4_EN_MAX_RX_SIZE 8192
	102
c27a02cd YP	103	/* Minimum ring size for our page-allocation sceme to work */
	104	#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
	105	#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
	106
f813cad8 YP	107	#define MLX4_EN_SMALL_PKT_SIZE 64
	108	#define MLX4_EN_NUM_TX_RINGS 8
	109	#define MLX4_EN_NUM_PPP_RINGS 8
	110	#define MLX4_EN_DEF_TX_RING_SIZE 512
c27a02cd YP	111	#define MLX4_EN_DEF_RX_RING_SIZE 1024
c27a02cd YP	112
3db36fb2 YP	113	/* Target number of packets to coalesce with interrupt moderation */
3db36fb2 YP	114	#define MLX4_EN_RX_COAL_TARGET 44
c27a02cd YP	115	#define MLX4_EN_RX_COAL_TIME 0x10
	116
	117	#define MLX4_EN_TX_COAL_PKTS 5
	118	#define MLX4_EN_TX_COAL_TIME 0x80
	119
	120	#define MLX4_EN_RX_RATE_LOW 400000
	121	#define MLX4_EN_RX_COAL_TIME_LOW 0
	122	#define MLX4_EN_RX_RATE_HIGH 450000
	123	#define MLX4_EN_RX_COAL_TIME_HIGH 128
	124	#define MLX4_EN_RX_SIZE_THRESH 1024
	125	#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
	126	#define MLX4_EN_SAMPLE_INTERVAL 0
	127
	128	#define MLX4_EN_AUTO_CONF 0xffff
	129
	130	#define MLX4_EN_DEF_RX_PAUSE 1
	131	#define MLX4_EN_DEF_TX_PAUSE 1
	132
af901ca1	133	/* Interval between successive polls in the Tx routine when polling is used
c27a02cd YP	134	instead of interrupts (in per-core Tx rings) - should be power of 2 */
	135	#define MLX4_EN_TX_POLL_MODER 16
	136	#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
	137
	138	#define ETH_LLC_SNAP_SIZE 8
	139
	140	#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
	141	#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
	142
	143	#define MLX4_EN_MIN_MTU 46
	144	#define ETH_BCAST 0xffffffffffffULL
	145
	146	#ifdef MLX4_EN_PERF_STAT
	147	/* Number of samples to 'average' */
	148	#define AVG_SIZE 128
	149	#define AVG_FACTOR 1024
	150	#define NUM_PERF_STATS NUM_PERF_COUNTERS
	151
	152	#define INC_PERF_COUNTER(cnt) (++(cnt))
	153	#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
	154	#define AVG_PERF_COUNTER(cnt, sample) \
	155	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
	156	#define GET_PERF_COUNTER(cnt) (cnt)
	157	#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
	158
	159	#else
	160
	161	#define NUM_PERF_STATS 0
	162	#define INC_PERF_COUNTER(cnt) do {} while (0)
	163	#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
	164	#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
	165	#define GET_PERF_COUNTER(cnt) (0)
	166	#define GET_AVG_PERF_COUNTER(cnt) (0)
	167	#endif /* MLX4_EN_PERF_STAT */
	168
	169	/*
	170	* Configurables
	171	*/
	172
	173	enum cq_type {
	174	RX = 0,
	175	TX = 1,
	176	};
	177
	178
	179	/*
	180	* Useful macros
	181	*/
	182	#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
	183	#define XNOR(x, y) (!(x) == !(y))
	184	#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL \|\| addr == 0x0)
	185
	186
	187	struct mlx4_en_tx_info {
	188	struct sk_buff *skb;
	189	u32 nr_txbb;
	190	u8 linear;
	191	u8 data_offset;
41efea5a	192	u8 inl;
c27a02cd YP	193	};
	194
	195
	196	#define MLX4_EN_BIT_DESC_OWN 0x80000000
	197	#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
	198	#define MLX4_EN_MEMTYPE_PAD 0x100
	199	#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
	200
	201
	202	struct mlx4_en_tx_desc {
	203	struct mlx4_wqe_ctrl_seg ctrl;
	204	union {
	205	struct mlx4_wqe_data_seg data; /* at least one data segment */
	206	struct mlx4_wqe_lso_seg lso;
	207	struct mlx4_wqe_inline_seg inl;
	208	};
	209	};
	210
	211	#define MLX4_EN_USE_SRQ 0x01000000
	212
	213	struct mlx4_en_rx_alloc {
	214	struct page *page;
	215	u16 offset;
	216	};
	217
	218	struct mlx4_en_tx_ring {
	219	struct mlx4_hwq_resources wqres;
	220	u32 size ; /* number of TXBBs */
	221	u32 size_mask;
	222	u16 stride;
	223	u16 cqn; /* index of port CQ associated with this ring */
	224	u32 prod;
	225	u32 cons;
	226	u32 buf_size;
	227	u32 doorbell_qpn;
	228	void *buf;
	229	u16 poll_cnt;
	230	int blocked;
	231	struct mlx4_en_tx_info *tx_info;
	232	u8 *bounce_buf;
	233	u32 last_nr_txbb;
	234	struct mlx4_qp qp;
	235	struct mlx4_qp_context context;
	236	int qpn;
	237	enum mlx4_qp_state qp_state;
	238	struct mlx4_srq dummy;
	239	unsigned long bytes;
	240	unsigned long packets;
	241	spinlock_t comp_lock;
	242	};
	243
	244	struct mlx4_en_rx_desc {
c27a02cd YP	245	/* actual number of entries depends on rx ring stride */
	246	struct mlx4_wqe_data_seg data[0];
	247	};
	248
	249	struct mlx4_en_rx_ring {
c27a02cd YP	250	struct mlx4_hwq_resources wqres;
	251	struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
	252	struct net_lro_mgr lro;
	253	u32 size ; /* number of Rx descs*/
	254	u32 actual_size;
	255	u32 size_mask;
	256	u16 stride;
	257	u16 log_stride;
	258	u16 cqn; /* index of port CQ associated with this ring */
	259	u32 prod;
	260	u32 cons;
	261	u32 buf_size;
c27a02cd YP	262	void *buf;
	263	void *rx_info;
	264	unsigned long bytes;
	265	unsigned long packets;
	266	};
	267
	268
	269	static inline int mlx4_en_can_lro(__be16 status)
	270	{
	271	return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 \|
	272	MLX4_CQE_STATUS_IPV4F \|
	273	MLX4_CQE_STATUS_IPV6 \|
	274	MLX4_CQE_STATUS_IPV4OPT \|
	275	MLX4_CQE_STATUS_TCP \|
	276	MLX4_CQE_STATUS_UDP \|
	277	MLX4_CQE_STATUS_IPOK)) ==
	278	cpu_to_be16(MLX4_CQE_STATUS_IPV4 \|
	279	MLX4_CQE_STATUS_IPOK \|
	280	MLX4_CQE_STATUS_TCP);
	281	}
	282
	283	struct mlx4_en_cq {
	284	struct mlx4_cq mcq;
	285	struct mlx4_hwq_resources wqres;
	286	int ring;
	287	spinlock_t lock;
	288	struct net_device *dev;
	289	struct napi_struct napi;
	290	/* Per-core Tx cq processing support */
	291	struct timer_list timer;
	292	int size;
	293	int buf_size;
	294	unsigned vector;
	295	enum cq_type is_tx;
	296	u16 moder_time;
	297	u16 moder_cnt;
c27a02cd YP	298	struct mlx4_cqe *buf;
	299	#define MLX4_EN_OPCODE_ERROR 0x1e
	300	};
	301
	302	struct mlx4_en_port_profile {
	303	u32 flags;
	304	u32 tx_ring_num;
	305	u32 rx_ring_num;
	306	u32 tx_ring_size;
	307	u32 rx_ring_size;
d53b93f2 YP	308	u8 rx_pause;
	309	u8 rx_ppp;
	310	u8 tx_pause;
	311	u8 tx_ppp;
c27a02cd YP	312	};
	313
	314	struct mlx4_en_profile {
	315	int rss_xor;
	316	int num_lro;
	317	u8 rss_mask;
	318	u32 active_ports;
	319	u32 small_pkt_int;
c27a02cd YP	320	u8 no_reset;
	321	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
	322	};
	323
	324	struct mlx4_en_dev {
	325	struct mlx4_dev *dev;
	326	struct pci_dev *pdev;
	327	struct mutex state_lock;
	328	struct net_device *pndev[MLX4_MAX_PORTS + 1];
	329	u32 port_cnt;
	330	bool device_up;
	331	struct mlx4_en_profile profile;
	332	u32 LSO_support;
	333	struct workqueue_struct *workqueue;
	334	struct device *dma_device;
	335	void __iomem *uar_map;
	336	struct mlx4_uar priv_uar;
	337	struct mlx4_mr mr;
	338	u32 priv_pdn;
	339	spinlock_t uar_lock;
	340	};
	341
	342
	343	struct mlx4_en_rss_map {
c27a02cd	344	int base_qpn;
b6b912e0 YP	345	struct mlx4_qp qps[MAX_RX_RINGS];
b6b912e0 YP	346	enum mlx4_qp_state state[MAX_RX_RINGS];
c27a02cd YP	347	struct mlx4_qp indir_qp;
	348	enum mlx4_qp_state indir_state;
	349	};
	350
	351	struct mlx4_en_rss_context {
	352	__be32 base_qpn;
	353	__be32 default_qpn;
	354	u16 reserved;
	355	u8 hash_fn;
	356	u8 flags;
	357	__be32 rss_key[10];
	358	};
	359
	360	struct mlx4_en_pkt_stats {
	361	unsigned long broadcast;
	362	unsigned long rx_prio[8];
	363	unsigned long tx_prio[8];
	364	#define NUM_PKT_STATS 17
	365	};
	366
	367	struct mlx4_en_port_stats {
	368	unsigned long lro_aggregated;
	369	unsigned long lro_flushed;
	370	unsigned long lro_no_desc;
	371	unsigned long tso_packets;
	372	unsigned long queue_stopped;
	373	unsigned long wake_queue;
	374	unsigned long tx_timeout;
	375	unsigned long rx_alloc_failed;
	376	unsigned long rx_chksum_good;
	377	unsigned long rx_chksum_none;
	378	unsigned long tx_chksum_offload;
	379	#define NUM_PORT_STATS 11
	380	};
	381
	382	struct mlx4_en_perf_stats {
	383	u32 tx_poll;
	384	u64 tx_pktsz_avg;
	385	u32 inflight_avg;
	386	u16 tx_coal_avg;
	387	u16 rx_coal_avg;
	388	u32 napi_quota;
	389	#define NUM_PERF_COUNTERS 6
	390	};
	391
	392	struct mlx4_en_frag_info {
	393	u16 frag_size;
	394	u16 frag_prefix_size;
	395	u16 frag_stride;
	396	u16 frag_align;
	397	u16 last_offset;
	398
	399	};
	400
	401	struct mlx4_en_priv {
	402	struct mlx4_en_dev *mdev;
	403	struct mlx4_en_port_profile *prof;
	404	struct net_device *dev;
	405	struct vlan_group *vlgrp;
	406	struct net_device_stats stats;
	407	struct net_device_stats ret_stats;
	408	spinlock_t stats_lock;
	409
	410	unsigned long last_moder_packets;
411	unsigned long last_moder_tx_packets;
412	unsigned long last_moder_bytes;
413	unsigned long last_moder_jiffies;
414	int last_moder_time;
415	u16 rx_usecs;
416	u16 rx_frames;
417	u16 tx_usecs;
418	u16 tx_frames;
419	u32 pkt_rate_low;
420	u16 rx_usecs_low;
421	u32 pkt_rate_high;
422	u16 rx_usecs_high;
423	u16 sample_interval;
424	u16 adaptive_rx_coal;
425	u32 msg_enable;
426
427	struct mlx4_hwq_resources res;
428	int link_state;
429	int last_link_state;
430	bool port_up;
431	int port;
432	int registered;
433	int allocated;
434	int stride;
435	int rx_csum;
436	u64 mac;
437	int mac_index;
438	unsigned max_mtu;
439	int base_qpn;
440
441	struct mlx4_en_rss_map rss_map;
c27a02cd YP	442	u32 flags;
	443	#define MLX4_EN_FLAG_PROMISC 0x1
	444	u32 tx_ring_num;
	445	u32 rx_ring_num;
	446	u32 rx_skb_size;
	447	struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
	448	u16 num_frags;
	449	u16 log_rx_info;
	450
	451	struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
	452	struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
	453	struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
	454	struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
	455	struct work_struct mcast_task;
	456	struct work_struct mac_task;
c27a02cd YP	457	struct work_struct watchdog_task;
	458	struct work_struct linkstate_task;
	459	struct delayed_work stats_task;
	460	struct mlx4_en_perf_stats pstats;
	461	struct mlx4_en_pkt_stats pkstats;
	462	struct mlx4_en_port_stats port_stats;
ff6e2163 JP	463	char *mc_addrs;
ff6e2163 JP	464	int mc_addrs_cnt;
c27a02cd	465	struct mlx4_en_stat_out_mbox hw_stats;
4c3eb3ca	466	int vids[128];
c27a02cd YP	467	};
	468
	469
	470	void mlx4_en_destroy_netdev(struct net_device *dev);
	471	int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
	472	struct mlx4_en_port_profile *prof);
	473
18cc42a3 YP	474	int mlx4_en_start_port(struct net_device *dev);
	475	void mlx4_en_stop_port(struct net_device *dev);
	476
	477	void mlx4_en_free_resources(struct mlx4_en_priv *priv);
	478	int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
	479
c27a02cd YP	480	int mlx4_en_create_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq,
	481	int entries, int ring, enum cq_type mode);
	482	void mlx4_en_destroy_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	483	int mlx4_en_activate_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	484	void mlx4_en_deactivate_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	485	int mlx4_en_set_cq_moder(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	486	int mlx4_en_arm_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	487
	488	void mlx4_en_poll_tx_cq(unsigned long data);
	489	void mlx4_en_tx_irq(struct mlx4_cq *mcq);
f813cad8	490	u16 mlx4_en_select_queue(struct net_device dev, struct sk_buff skb);
61357325	491	netdev_tx_t mlx4_en_xmit(struct sk_buff skb, struct net_device dev);
c27a02cd YP	492
	493	int mlx4_en_create_tx_ring(struct mlx4_en_priv priv, struct mlx4_en_tx_ring ring,
	494	u32 size, u16 stride);
	495	void mlx4_en_destroy_tx_ring(struct mlx4_en_priv priv, struct mlx4_en_tx_ring ring);
	496	int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
	497	struct mlx4_en_tx_ring *ring,
9f519f68	498	int cq);
c27a02cd YP	499	void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
	500	struct mlx4_en_tx_ring *ring);
	501
	502	int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
	503	struct mlx4_en_rx_ring *ring,
	504	u32 size, u16 stride);
	505	void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
	506	struct mlx4_en_rx_ring *ring);
	507	int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
	508	void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
	509	struct mlx4_en_rx_ring *ring);
	510	int mlx4_en_process_rx_cq(struct net_device *dev,
	511	struct mlx4_en_cq *cq,
	512	int budget);
	513	int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
	514	void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
9f519f68	515	int is_tx, int rss, int qpn, int cqn,
c27a02cd	516	struct mlx4_qp_context *context);
966508f7	517	void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
c27a02cd YP	518	int mlx4_en_map_buffer(struct mlx4_buf *buf);
	519	void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
	520
	521	void mlx4_en_calc_rx_buf(struct net_device *dev);
c27a02cd YP	522	int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
	523	void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
	524	int mlx4_en_free_tx_buf(struct net_device dev, struct mlx4_en_tx_ring ring);
c27a02cd YP	525	void mlx4_en_rx_irq(struct mlx4_cq *mcq);
	526
	527	int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
	528	int mlx4_SET_VLAN_FLTR(struct mlx4_dev dev, u8 port, struct vlan_group grp);
	529	int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
	530	u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
	531	int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
	532	u8 promisc);
	533
	534	int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
	535
	536	/*
	537	* Globals
	538	*/
	539	extern const struct ethtool_ops mlx4_en_ethtool_ops;
0a645e80 JP	540
	541
	542
	543	/*
	544	* printk / logging functions
	545	*/
	546
	547	int en_print(const char level, const struct mlx4_en_priv priv,
	548	const char *format, ...) __attribute__ ((format (printf, 3, 4)));
	549
	550	#define en_dbg(mlevel, priv, format, arg...) \
	551	do { \
	552	if (NETIF_MSG_##mlevel & priv->msg_enable) \
	553	en_print(KERN_DEBUG, priv, format, ##arg); \
	554	} while (0)
	555	#define en_warn(priv, format, arg...) \
	556	en_print(KERN_WARNING, priv, format, ##arg)
	557	#define en_err(priv, format, arg...) \
	558	en_print(KERN_ERR, priv, format, ##arg)
	559
	560	#define mlx4_err(mdev, format, arg...) \
	561	pr_err("%s %s: " format, DRV_NAME, \
	562	dev_name(&mdev->pdev->dev), ##arg)
	563	#define mlx4_info(mdev, format, arg...) \
	564	pr_info("%s %s: " format, DRV_NAME, \
	565	dev_name(&mdev->pdev->dev), ##arg)
	566	#define mlx4_warn(mdev, format, arg...) \
	567	pr_warning("%s %s: " format, DRV_NAME, \
	568	dev_name(&mdev->pdev->dev), ##arg)
	569
c27a02cd	570	#endif