[linux-2.6-block.git] / drivers / net / mlx4 / mlx4_en.h

/*
 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

#ifndef _MLX4_EN_H_
#define _MLX4_EN_H_

#include <linux/compiler.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/netdevice.h>
#include <linux/inet_lro.h>

#include <linux/mlx4/device.h>
#include <linux/mlx4/qp.h>
#include <linux/mlx4/cq.h>
#include <linux/mlx4/srq.h>
#include <linux/mlx4/doorbell.h>

#include "en_port.h"

#define DRV_NAME	"mlx4_en"
#define DRV_VERSION	"1.4.1.1"
#define DRV_RELDATE	"June 2009"


#define MLX4_EN_MSG_LEVEL	(NETIF_MSG_LINK | NETIF_MSG_IFDOWN)

#define en_print(level, priv, format, arg...)			\
	{							\
	if ((priv)->registered)					\
		printk(level "%s: %s: " format, DRV_NAME,	\
			(priv->dev)->name, ## arg);		\
	else							\
		printk(level "%s: %s: Port %d: " format,	\
			DRV_NAME, dev_name(&priv->mdev->pdev->dev), \
			(priv)->port, ## arg);			\
	}

#define en_dbg(mlevel, priv, format, arg...)			\
	{							\
	if (NETIF_MSG_##mlevel & priv->msg_enable)		\
		en_print(KERN_DEBUG, priv, format, ## arg)	\
	}
#define en_warn(priv, format, arg...)				\
	en_print(KERN_WARNING, priv, format, ## arg)
#define en_err(priv, format, arg...)				\
	en_print(KERN_ERR, priv, format, ## arg)

#define mlx4_err(mdev, format, arg...) \
	printk(KERN_ERR "%s %s: " format , DRV_NAME ,\
		dev_name(&mdev->pdev->dev) , ## arg)
#define mlx4_info(mdev, format, arg...) \
	printk(KERN_INFO "%s %s: " format , DRV_NAME ,\
		dev_name(&mdev->pdev->dev) , ## arg)
#define mlx4_warn(mdev, format, arg...) \
	printk(KERN_WARNING "%s %s: " format , DRV_NAME ,\
		dev_name(&mdev->pdev->dev) , ## arg)

/*
 * Device constants
 */


#define MLX4_EN_PAGE_SHIFT	12
#define MLX4_EN_PAGE_SIZE	(1 << MLX4_EN_PAGE_SHIFT)
#define MAX_TX_RINGS		16
#define MAX_RX_RINGS		16
#define MAX_RSS_MAP_SIZE	64
#define RSS_FACTOR		2
#define TXBB_SIZE		64
#define HEADROOM		(2048 / TXBB_SIZE + 1)
#define STAMP_STRIDE		64
#define STAMP_DWORDS		(STAMP_STRIDE / 4)
#define STAMP_SHIFT		31
#define STAMP_VAL		0x7fffffff
#define STATS_DELAY		(HZ / 4)

/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
#define MAX_DESC_SIZE		512
#define MAX_DESC_TXBBS		(MAX_DESC_SIZE / TXBB_SIZE)

/*
 * OS related constants and tunables
 */

#define MLX4_EN_WATCHDOG_TIMEOUT	(15 * HZ)

#define MLX4_EN_ALLOC_ORDER	2
#define MLX4_EN_ALLOC_SIZE	(PAGE_SIZE << MLX4_EN_ALLOC_ORDER)

#define MLX4_EN_MAX_LRO_DESCRIPTORS	32

/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
 * and 4K allocations) */
enum {
	FRAG_SZ0 = 512 - NET_IP_ALIGN,
	FRAG_SZ1 = 1024,
	FRAG_SZ2 = 4096,
	FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
};
#define MLX4_EN_MAX_RX_FRAGS	4

/* Maximum ring sizes */
#define MLX4_EN_MAX_TX_SIZE	8192
#define MLX4_EN_MAX_RX_SIZE	8192

/* Minimum ring size for our page-allocation sceme to work */
#define MLX4_EN_MIN_RX_SIZE	(MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
#define MLX4_EN_MIN_TX_SIZE	(4096 / TXBB_SIZE)

#define MLX4_EN_SMALL_PKT_SIZE		64
#define MLX4_EN_NUM_TX_RINGS		8
#define MLX4_EN_NUM_PPP_RINGS		8
#define MLX4_EN_DEF_TX_RING_SIZE	512
#define MLX4_EN_DEF_RX_RING_SIZE  	1024

/* Target number of packets to coalesce with interrupt moderation */
#define MLX4_EN_RX_COAL_TARGET	44
#define MLX4_EN_RX_COAL_TIME	0x10

#define MLX4_EN_TX_COAL_PKTS	5
#define MLX4_EN_TX_COAL_TIME	0x80

#define MLX4_EN_RX_RATE_LOW		400000
#define MLX4_EN_RX_COAL_TIME_LOW	0
#define MLX4_EN_RX_RATE_HIGH		450000
#define MLX4_EN_RX_COAL_TIME_HIGH	128
#define MLX4_EN_RX_SIZE_THRESH		1024
#define MLX4_EN_RX_RATE_THRESH		(1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
#define MLX4_EN_SAMPLE_INTERVAL		0

#define MLX4_EN_AUTO_CONF	0xffff

#define MLX4_EN_DEF_RX_PAUSE	1
#define MLX4_EN_DEF_TX_PAUSE	1

/* Interval between sucessive polls in the Tx routine when polling is used
   instead of interrupts (in per-core Tx rings) - should be power of 2 */
#define MLX4_EN_TX_POLL_MODER	16
#define MLX4_EN_TX_POLL_TIMEOUT	(HZ / 4)

#define ETH_LLC_SNAP_SIZE	8

#define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
#define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)

#define MLX4_EN_MIN_MTU		46
#define ETH_BCAST		0xffffffffffffULL

#ifdef MLX4_EN_PERF_STAT
/* Number of samples to 'average' */
#define AVG_SIZE			128
#define AVG_FACTOR			1024
#define NUM_PERF_STATS			NUM_PERF_COUNTERS

#define INC_PERF_COUNTER(cnt)		(++(cnt))
#define ADD_PERF_COUNTER(cnt, add)	((cnt) += (add))
#define AVG_PERF_COUNTER(cnt, sample) \
	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
#define GET_PERF_COUNTER(cnt)		(cnt)
#define GET_AVG_PERF_COUNTER(cnt)	((cnt) / AVG_FACTOR)

#else

#define NUM_PERF_STATS			0
#define INC_PERF_COUNTER(cnt)		do {} while (0)
#define ADD_PERF_COUNTER(cnt, add)	do {} while (0)
#define AVG_PERF_COUNTER(cnt, sample)	do {} while (0)
#define GET_PERF_COUNTER(cnt)		(0)
#define GET_AVG_PERF_COUNTER(cnt)	(0)
#endif /* MLX4_EN_PERF_STAT */

/*
 * Configurables
 */

enum cq_type {
	RX = 0,
	TX = 1,
};


/*
 * Useful macros
 */
#define ROUNDUP_LOG2(x)		ilog2(roundup_pow_of_two(x))
#define XNOR(x, y)		(!(x) == !(y))
#define ILLEGAL_MAC(addr)	(addr == 0xffffffffffffULL || addr == 0x0)


struct mlx4_en_tx_info {
	struct sk_buff *skb;
	u32 nr_txbb;
	u8 linear;
	u8 data_offset;
	u8 inl;
};


#define MLX4_EN_BIT_DESC_OWN	0x80000000
#define CTRL_SIZE	sizeof(struct mlx4_wqe_ctrl_seg)
#define MLX4_EN_MEMTYPE_PAD	0x100
#define DS_SIZE		sizeof(struct mlx4_wqe_data_seg)


struct mlx4_en_tx_desc {
	struct mlx4_wqe_ctrl_seg ctrl;
	union {
		struct mlx4_wqe_data_seg data; /* at least one data segment */
		struct mlx4_wqe_lso_seg lso;
		struct mlx4_wqe_inline_seg inl;
	};
};

#define MLX4_EN_USE_SRQ		0x01000000

struct mlx4_en_rx_alloc {
	struct page *page;
	u16 offset;
};

struct mlx4_en_tx_ring {
	struct mlx4_hwq_resources wqres;
	u32 size ; /* number of TXBBs */
	u32 size_mask;
	u16 stride;
	u16 cqn;	/* index of port CQ associated with this ring */
	u32 prod;
	u32 cons;
	u32 buf_size;
	u32 doorbell_qpn;
	void *buf;
	u16 poll_cnt;
	int blocked;
	struct mlx4_en_tx_info *tx_info;
	u8 *bounce_buf;
	u32 last_nr_txbb;
	struct mlx4_qp qp;
	struct mlx4_qp_context context;
	int qpn;
	enum mlx4_qp_state qp_state;
	struct mlx4_srq dummy;
	unsigned long bytes;
	unsigned long packets;
	spinlock_t comp_lock;
};

struct mlx4_en_rx_desc {
	struct mlx4_wqe_srq_next_seg next;
	/* actual number of entries depends on rx ring stride */
	struct mlx4_wqe_data_seg data[0];
};

struct mlx4_en_rx_ring {
	struct mlx4_srq srq;
	struct mlx4_hwq_resources wqres;
	struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
	struct net_lro_mgr lro;
	u32 size ;	/* number of Rx descs*/
	u32 actual_size;
	u32 size_mask;
	u16 stride;
	u16 log_stride;
	u16 cqn;	/* index of port CQ associated with this ring */
	u32 prod;
	u32 cons;
	u32 buf_size;
	void *buf;
	void *rx_info;
	unsigned long bytes;
	unsigned long packets;
};


static inline int mlx4_en_can_lro(__be16 status)
{
	return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4	|
				     MLX4_CQE_STATUS_IPV4F	|
				     MLX4_CQE_STATUS_IPV6	|
				     MLX4_CQE_STATUS_IPV4OPT	|
				     MLX4_CQE_STATUS_TCP	|
				     MLX4_CQE_STATUS_UDP	|
				     MLX4_CQE_STATUS_IPOK)) ==
		cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
			    MLX4_CQE_STATUS_IPOK |
			    MLX4_CQE_STATUS_TCP);
}

struct mlx4_en_cq {
	struct mlx4_cq          mcq;
	struct mlx4_hwq_resources wqres;
	int                     ring;
	spinlock_t              lock;
	struct net_device      *dev;
	struct napi_struct	napi;
	/* Per-core Tx cq processing support */
	struct timer_list timer;
	int size;
	int buf_size;
	unsigned vector;
	enum cq_type is_tx;
	u16 moder_time;
	u16 moder_cnt;
	struct mlx4_cqe *buf;
#define MLX4_EN_OPCODE_ERROR	0x1e
};

struct mlx4_en_port_profile {
	u32 flags;
	u32 tx_ring_num;
	u32 rx_ring_num;
	u32 tx_ring_size;
	u32 rx_ring_size;
	u8 rx_pause;
	u8 rx_ppp;
	u8 tx_pause;
	u8 tx_ppp;
};

struct mlx4_en_profile {
	int rss_xor;
	int num_lro;
	u8 rss_mask;
	u32 active_ports;
	u32 small_pkt_int;
	u8 no_reset;
	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
};

struct mlx4_en_dev {
	struct mlx4_dev         *dev;
	struct pci_dev		*pdev;
	struct mutex		state_lock;
	struct net_device       *pndev[MLX4_MAX_PORTS + 1];
	u32                     port_cnt;
	bool			device_up;
	struct mlx4_en_profile  profile;
	u32			LSO_support;
	struct workqueue_struct *workqueue;
	struct device           *dma_device;
	void __iomem            *uar_map;
	struct mlx4_uar         priv_uar;
	struct mlx4_mr		mr;
	u32                     priv_pdn;
	spinlock_t              uar_lock;
};


struct mlx4_en_rss_map {
	int size;
	int base_qpn;
	u16 map[MAX_RSS_MAP_SIZE];
	struct mlx4_qp qps[MAX_RSS_MAP_SIZE];
	enum mlx4_qp_state state[MAX_RSS_MAP_SIZE];
	struct mlx4_qp indir_qp;
	enum mlx4_qp_state indir_state;
};

struct mlx4_en_rss_context {
	__be32 base_qpn;
	__be32 default_qpn;
	u16 reserved;
	u8 hash_fn;
	u8 flags;
	__be32 rss_key[10];
};

struct mlx4_en_pkt_stats {
	unsigned long broadcast;
	unsigned long rx_prio[8];
	unsigned long tx_prio[8];
#define NUM_PKT_STATS		17
};

struct mlx4_en_port_stats {
	unsigned long lro_aggregated;
	unsigned long lro_flushed;
	unsigned long lro_no_desc;
	unsigned long tso_packets;
	unsigned long queue_stopped;
	unsigned long wake_queue;
	unsigned long tx_timeout;
	unsigned long rx_alloc_failed;
	unsigned long rx_chksum_good;
	unsigned long rx_chksum_none;
	unsigned long tx_chksum_offload;
#define NUM_PORT_STATS		11
};

struct mlx4_en_perf_stats {
	u32 tx_poll;
	u64 tx_pktsz_avg;
	u32 inflight_avg;
	u16 tx_coal_avg;
	u16 rx_coal_avg;
	u32 napi_quota;
#define NUM_PERF_COUNTERS		6
};

struct mlx4_en_frag_info {
	u16 frag_size;
	u16 frag_prefix_size;
	u16 frag_stride;
	u16 frag_align;
	u16 last_offset;

};

struct mlx4_en_priv {
	struct mlx4_en_dev *mdev;
	struct mlx4_en_port_profile *prof;
	struct net_device *dev;
	struct vlan_group *vlgrp;
	struct net_device_stats stats;
	struct net_device_stats ret_stats;
	spinlock_t stats_lock;

	unsigned long last_moder_packets;
	unsigned long last_moder_tx_packets;
	unsigned long last_moder_bytes;
	unsigned long last_moder_jiffies;
	int last_moder_time;
	u16 rx_usecs;
	u16 rx_frames;
	u16 tx_usecs;
	u16 tx_frames;
	u32 pkt_rate_low;
	u16 rx_usecs_low;
	u32 pkt_rate_high;
	u16 rx_usecs_high;
	u16 sample_interval;
	u16 adaptive_rx_coal;
	u32 msg_enable;

	struct mlx4_hwq_resources res;
	int link_state;
	int last_link_state;
	bool port_up;
	int port;
	int registered;
	int allocated;
	int stride;
	int rx_csum;
	u64 mac;
	int mac_index;
	unsigned max_mtu;
	int base_qpn;

	struct mlx4_en_rss_map rss_map;
	u32 flags;
#define MLX4_EN_FLAG_PROMISC	0x1
	u32 tx_ring_num;
	u32 rx_ring_num;
	u32 rx_skb_size;
	struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
	u16 num_frags;
	u16 log_rx_info;

	struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
	struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
	struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
	struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
	struct work_struct mcast_task;
	struct work_struct mac_task;
	struct work_struct watchdog_task;
	struct work_struct linkstate_task;
	struct delayed_work stats_task;
	struct mlx4_en_perf_stats pstats;
	struct mlx4_en_pkt_stats pkstats;
	struct mlx4_en_port_stats port_stats;
	struct dev_mc_list *mc_list;
	struct mlx4_en_stat_out_mbox hw_stats;
};


void mlx4_en_destroy_netdev(struct net_device *dev);
int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
			struct mlx4_en_port_profile *prof);

int mlx4_en_start_port(struct net_device *dev);
void mlx4_en_stop_port(struct net_device *dev);

void mlx4_en_free_resources(struct mlx4_en_priv *priv);
int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);

int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
		      int entries, int ring, enum cq_type mode);
void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);

void mlx4_en_poll_tx_cq(unsigned long data);
void mlx4_en_tx_irq(struct mlx4_cq *mcq);
u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
int mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);

int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
			   u32 size, u16 stride);
void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
			     struct mlx4_en_tx_ring *ring,
			     int cq, int srqn);
void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
				struct mlx4_en_tx_ring *ring);

int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
			   struct mlx4_en_rx_ring *ring,
			   u32 size, u16 stride);
void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
			     struct mlx4_en_rx_ring *ring);
int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
				struct mlx4_en_rx_ring *ring);
int mlx4_en_process_rx_cq(struct net_device *dev,
			  struct mlx4_en_cq *cq,
			  int budget);
int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
			     int is_tx, int rss, int qpn, int cqn, int srqn,
			     struct mlx4_qp_context *context);
void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
int mlx4_en_map_buffer(struct mlx4_buf *buf);
void mlx4_en_unmap_buffer(struct mlx4_buf *buf);

void mlx4_en_calc_rx_buf(struct net_device *dev);
void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv,
				 struct mlx4_en_rss_map *rss_map,
				 int num_entries, int num_rings);
int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
void mlx4_en_rx_irq(struct mlx4_cq *mcq);

int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp);
int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
			  u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
			   u8 promisc);

int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);

/*
 * Globals
 */
extern const struct ethtool_ops mlx4_en_ethtool_ops;
#endif
Commit	Line	Data
c27a02cd YP	1	/*
	2	* Copyright (c) 2007 Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*
	32	*/
	33
	34	#ifndef _MLX4_EN_H_
	35	#define _MLX4_EN_H_
	36
	37	#include <linux/compiler.h>
	38	#include <linux/list.h>
	39	#include <linux/mutex.h>
	40	#include <linux/netdevice.h>
	41	#include <linux/inet_lro.h>
	42
	43	#include <linux/mlx4/device.h>
	44	#include <linux/mlx4/qp.h>
	45	#include <linux/mlx4/cq.h>
	46	#include <linux/mlx4/srq.h>
	47	#include <linux/mlx4/doorbell.h>
	48
	49	#include "en_port.h"
	50
	51	#define DRV_NAME "mlx4_en"
d455e5b1 YP	52	#define DRV_VERSION "1.4.1.1"
d455e5b1 YP	53	#define DRV_RELDATE "June 2009"
c27a02cd YP	54
	55
	56	#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK \| NETIF_MSG_IFDOWN)
	57
453a6082 YP	58	#define en_print(level, priv, format, arg...) \
	59	{ \
	60	if ((priv)->registered) \
	61	printk(level "%s: %s: " format, DRV_NAME, \
	62	(priv->dev)->name, ## arg); \
	63	else \
	64	printk(level "%s: %s: Port %d: " format, \
	65	DRV_NAME, dev_name(&priv->mdev->pdev->dev), \
	66	(priv)->port, ## arg); \
	67	}
	68
	69	#define en_dbg(mlevel, priv, format, arg...) \
	70	{ \
	71	if (NETIF_MSG_##mlevel & priv->msg_enable) \
	72	en_print(KERN_DEBUG, priv, format, ## arg) \
	73	}
	74	#define en_warn(priv, format, arg...) \
	75	en_print(KERN_WARNING, priv, format, ## arg)
	76	#define en_err(priv, format, arg...) \
	77	en_print(KERN_ERR, priv, format, ## arg)
c27a02cd YP	78
	79	#define mlx4_err(mdev, format, arg...) \
	80	printk(KERN_ERR "%s %s: " format , DRV_NAME ,\
453a6082	81	dev_name(&mdev->pdev->dev) , ## arg)
c27a02cd YP	82	#define mlx4_info(mdev, format, arg...) \
c27a02cd YP	83	printk(KERN_INFO "%s %s: " format , DRV_NAME ,\
453a6082	84	dev_name(&mdev->pdev->dev) , ## arg)
c27a02cd YP	85	#define mlx4_warn(mdev, format, arg...) \
c27a02cd YP	86	printk(KERN_WARNING "%s %s: " format , DRV_NAME ,\
453a6082	87	dev_name(&mdev->pdev->dev) , ## arg)
c27a02cd YP	88
	89	/*
	90	* Device constants
	91	*/
	92
	93
	94	#define MLX4_EN_PAGE_SHIFT 12
	95	#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
	96	#define MAX_TX_RINGS 16
	97	#define MAX_RX_RINGS 16
	98	#define MAX_RSS_MAP_SIZE 64
	99	#define RSS_FACTOR 2
	100	#define TXBB_SIZE 64
	101	#define HEADROOM (2048 / TXBB_SIZE + 1)
c27a02cd YP	102	#define STAMP_STRIDE 64
	103	#define STAMP_DWORDS (STAMP_STRIDE / 4)
	104	#define STAMP_SHIFT 31
	105	#define STAMP_VAL 0x7fffffff
	106	#define STATS_DELAY (HZ / 4)
	107
	108	/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
	109	#define MAX_DESC_SIZE 512
	110	#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
	111
	112	/*
	113	* OS related constants and tunables
	114	*/
	115
	116	#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
	117
	118	#define MLX4_EN_ALLOC_ORDER 2
	119	#define MLX4_EN_ALLOC_SIZE (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
	120
	121	#define MLX4_EN_MAX_LRO_DESCRIPTORS 32
	122
	123	/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
	124	* and 4K allocations) */
	125	enum {
	126	FRAG_SZ0 = 512 - NET_IP_ALIGN,
	127	FRAG_SZ1 = 1024,
	128	FRAG_SZ2 = 4096,
	129	FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
	130	};
	131	#define MLX4_EN_MAX_RX_FRAGS 4
	132
bd531e36 YP	133	/* Maximum ring sizes */
	134	#define MLX4_EN_MAX_TX_SIZE 8192
	135	#define MLX4_EN_MAX_RX_SIZE 8192
	136
c27a02cd YP	137	/* Minimum ring size for our page-allocation sceme to work */
	138	#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
	139	#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
	140
f813cad8 YP	141	#define MLX4_EN_SMALL_PKT_SIZE 64
	142	#define MLX4_EN_NUM_TX_RINGS 8
	143	#define MLX4_EN_NUM_PPP_RINGS 8
	144	#define MLX4_EN_DEF_TX_RING_SIZE 512
c27a02cd YP	145	#define MLX4_EN_DEF_RX_RING_SIZE 1024
c27a02cd YP	146
3db36fb2 YP	147	/* Target number of packets to coalesce with interrupt moderation */
3db36fb2 YP	148	#define MLX4_EN_RX_COAL_TARGET 44
c27a02cd YP	149	#define MLX4_EN_RX_COAL_TIME 0x10
	150
	151	#define MLX4_EN_TX_COAL_PKTS 5
	152	#define MLX4_EN_TX_COAL_TIME 0x80
	153
	154	#define MLX4_EN_RX_RATE_LOW 400000
	155	#define MLX4_EN_RX_COAL_TIME_LOW 0
	156	#define MLX4_EN_RX_RATE_HIGH 450000
	157	#define MLX4_EN_RX_COAL_TIME_HIGH 128
	158	#define MLX4_EN_RX_SIZE_THRESH 1024
	159	#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
	160	#define MLX4_EN_SAMPLE_INTERVAL 0
	161
	162	#define MLX4_EN_AUTO_CONF 0xffff
	163
	164	#define MLX4_EN_DEF_RX_PAUSE 1
	165	#define MLX4_EN_DEF_TX_PAUSE 1
	166
	167	/* Interval between sucessive polls in the Tx routine when polling is used
	168	instead of interrupts (in per-core Tx rings) - should be power of 2 */
	169	#define MLX4_EN_TX_POLL_MODER 16
	170	#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
	171
	172	#define ETH_LLC_SNAP_SIZE 8
	173
	174	#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
	175	#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
	176
	177	#define MLX4_EN_MIN_MTU 46
	178	#define ETH_BCAST 0xffffffffffffULL
	179
	180	#ifdef MLX4_EN_PERF_STAT
	181	/* Number of samples to 'average' */
	182	#define AVG_SIZE 128
	183	#define AVG_FACTOR 1024
	184	#define NUM_PERF_STATS NUM_PERF_COUNTERS
	185
	186	#define INC_PERF_COUNTER(cnt) (++(cnt))
	187	#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
	188	#define AVG_PERF_COUNTER(cnt, sample) \
	189	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
	190	#define GET_PERF_COUNTER(cnt) (cnt)
	191	#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
	192
	193	#else
	194
	195	#define NUM_PERF_STATS 0
	196	#define INC_PERF_COUNTER(cnt) do {} while (0)
	197	#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
	198	#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
	199	#define GET_PERF_COUNTER(cnt) (0)
	200	#define GET_AVG_PERF_COUNTER(cnt) (0)
	201	#endif /* MLX4_EN_PERF_STAT */
	202
	203	/*
	204	* Configurables
	205	*/
	206
	207	enum cq_type {
	208	RX = 0,
	209	TX = 1,
	210	};
	211
	212
213	/*
214	* Useful macros
215	*/
216	#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
217	#define XNOR(x, y) (!(x) == !(y))
218	#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL \|\| addr == 0x0)
219
220
221	struct mlx4_en_tx_info {
222	struct sk_buff *skb;
223	u32 nr_txbb;
224	u8 linear;
225	u8 data_offset;
41efea5a	226	u8 inl;
c27a02cd YP	227	};
	228
	229
	230	#define MLX4_EN_BIT_DESC_OWN 0x80000000
	231	#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
	232	#define MLX4_EN_MEMTYPE_PAD 0x100
	233	#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
	234
	235
	236	struct mlx4_en_tx_desc {
	237	struct mlx4_wqe_ctrl_seg ctrl;
	238	union {
	239	struct mlx4_wqe_data_seg data; /* at least one data segment */
	240	struct mlx4_wqe_lso_seg lso;
	241	struct mlx4_wqe_inline_seg inl;
	242	};
	243	};
	244
	245	#define MLX4_EN_USE_SRQ 0x01000000
	246
	247	struct mlx4_en_rx_alloc {
	248	struct page *page;
	249	u16 offset;
	250	};
	251
	252	struct mlx4_en_tx_ring {
	253	struct mlx4_hwq_resources wqres;
	254	u32 size ; /* number of TXBBs */
	255	u32 size_mask;
	256	u16 stride;
	257	u16 cqn; /* index of port CQ associated with this ring */
	258	u32 prod;
	259	u32 cons;
	260	u32 buf_size;
	261	u32 doorbell_qpn;
	262	void *buf;
	263	u16 poll_cnt;
	264	int blocked;
	265	struct mlx4_en_tx_info *tx_info;
	266	u8 *bounce_buf;
	267	u32 last_nr_txbb;
	268	struct mlx4_qp qp;
	269	struct mlx4_qp_context context;
	270	int qpn;
	271	enum mlx4_qp_state qp_state;
	272	struct mlx4_srq dummy;
	273	unsigned long bytes;
	274	unsigned long packets;
	275	spinlock_t comp_lock;
	276	};
	277
	278	struct mlx4_en_rx_desc {
	279	struct mlx4_wqe_srq_next_seg next;
	280	/* actual number of entries depends on rx ring stride */
	281	struct mlx4_wqe_data_seg data[0];
	282	};
	283
	284	struct mlx4_en_rx_ring {
	285	struct mlx4_srq srq;
	286	struct mlx4_hwq_resources wqres;
	287	struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
	288	struct net_lro_mgr lro;
	289	u32 size ; /* number of Rx descs*/
	290	u32 actual_size;
291	u32 size_mask;
292	u16 stride;
293	u16 log_stride;
294	u16 cqn; /* index of port CQ associated with this ring */
295	u32 prod;
296	u32 cons;
297	u32 buf_size;
c27a02cd YP	298	void *buf;
	299	void *rx_info;
	300	unsigned long bytes;
	301	unsigned long packets;
	302	};
	303
	304
	305	static inline int mlx4_en_can_lro(__be16 status)
	306	{
	307	return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 \|
	308	MLX4_CQE_STATUS_IPV4F \|
	309	MLX4_CQE_STATUS_IPV6 \|
	310	MLX4_CQE_STATUS_IPV4OPT \|
	311	MLX4_CQE_STATUS_TCP \|
	312	MLX4_CQE_STATUS_UDP \|
	313	MLX4_CQE_STATUS_IPOK)) ==
	314	cpu_to_be16(MLX4_CQE_STATUS_IPV4 \|
	315	MLX4_CQE_STATUS_IPOK \|
	316	MLX4_CQE_STATUS_TCP);
	317	}
	318
	319	struct mlx4_en_cq {
	320	struct mlx4_cq mcq;
	321	struct mlx4_hwq_resources wqres;
	322	int ring;
	323	spinlock_t lock;
	324	struct net_device *dev;
	325	struct napi_struct napi;
	326	/* Per-core Tx cq processing support */
	327	struct timer_list timer;
	328	int size;
	329	int buf_size;
	330	unsigned vector;
	331	enum cq_type is_tx;
	332	u16 moder_time;
	333	u16 moder_cnt;
c27a02cd YP	334	struct mlx4_cqe *buf;
	335	#define MLX4_EN_OPCODE_ERROR 0x1e
	336	};
	337
	338	struct mlx4_en_port_profile {
	339	u32 flags;
	340	u32 tx_ring_num;
	341	u32 rx_ring_num;
	342	u32 tx_ring_size;
	343	u32 rx_ring_size;
d53b93f2 YP	344	u8 rx_pause;
	345	u8 rx_ppp;
	346	u8 tx_pause;
	347	u8 tx_ppp;
c27a02cd YP	348	};
	349
	350	struct mlx4_en_profile {
	351	int rss_xor;
	352	int num_lro;
	353	u8 rss_mask;
	354	u32 active_ports;
	355	u32 small_pkt_int;
c27a02cd YP	356	u8 no_reset;
	357	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
	358	};
	359
	360	struct mlx4_en_dev {
	361	struct mlx4_dev *dev;
	362	struct pci_dev *pdev;
	363	struct mutex state_lock;
	364	struct net_device *pndev[MLX4_MAX_PORTS + 1];
	365	u32 port_cnt;
	366	bool device_up;
	367	struct mlx4_en_profile profile;
	368	u32 LSO_support;
	369	struct workqueue_struct *workqueue;
	370	struct device *dma_device;
	371	void __iomem *uar_map;
	372	struct mlx4_uar priv_uar;
	373	struct mlx4_mr mr;
	374	u32 priv_pdn;
	375	spinlock_t uar_lock;
	376	};
	377
	378
	379	struct mlx4_en_rss_map {
	380	int size;
	381	int base_qpn;
	382	u16 map[MAX_RSS_MAP_SIZE];
	383	struct mlx4_qp qps[MAX_RSS_MAP_SIZE];
	384	enum mlx4_qp_state state[MAX_RSS_MAP_SIZE];
	385	struct mlx4_qp indir_qp;
	386	enum mlx4_qp_state indir_state;
	387	};
	388
	389	struct mlx4_en_rss_context {
	390	__be32 base_qpn;
	391	__be32 default_qpn;
	392	u16 reserved;
	393	u8 hash_fn;
	394	u8 flags;
	395	__be32 rss_key[10];
	396	};
	397
	398	struct mlx4_en_pkt_stats {
	399	unsigned long broadcast;
	400	unsigned long rx_prio[8];
	401	unsigned long tx_prio[8];
	402	#define NUM_PKT_STATS 17
	403	};
	404
	405	struct mlx4_en_port_stats {
	406	unsigned long lro_aggregated;
	407	unsigned long lro_flushed;
	408	unsigned long lro_no_desc;
	409	unsigned long tso_packets;
	410	unsigned long queue_stopped;
	411	unsigned long wake_queue;
	412	unsigned long tx_timeout;
	413	unsigned long rx_alloc_failed;
	414	unsigned long rx_chksum_good;
	415	unsigned long rx_chksum_none;
	416	unsigned long tx_chksum_offload;
	417	#define NUM_PORT_STATS 11
	418	};
	419
420	struct mlx4_en_perf_stats {
421	u32 tx_poll;
422	u64 tx_pktsz_avg;
423	u32 inflight_avg;
424	u16 tx_coal_avg;
425	u16 rx_coal_avg;
426	u32 napi_quota;
427	#define NUM_PERF_COUNTERS 6
428	};
429
430	struct mlx4_en_frag_info {
431	u16 frag_size;
432	u16 frag_prefix_size;
433	u16 frag_stride;
434	u16 frag_align;
435	u16 last_offset;
436
437	};
438
439	struct mlx4_en_priv {
440	struct mlx4_en_dev *mdev;
441	struct mlx4_en_port_profile *prof;
442	struct net_device *dev;
443	struct vlan_group *vlgrp;
444	struct net_device_stats stats;
445	struct net_device_stats ret_stats;
446	spinlock_t stats_lock;
447
448	unsigned long last_moder_packets;
449	unsigned long last_moder_tx_packets;
450	unsigned long last_moder_bytes;
451	unsigned long last_moder_jiffies;
452	int last_moder_time;
453	u16 rx_usecs;
454	u16 rx_frames;
455	u16 tx_usecs;
456	u16 tx_frames;
457	u32 pkt_rate_low;
458	u16 rx_usecs_low;
459	u32 pkt_rate_high;
460	u16 rx_usecs_high;
461	u16 sample_interval;
462	u16 adaptive_rx_coal;
463	u32 msg_enable;
464
465	struct mlx4_hwq_resources res;
466	int link_state;
467	int last_link_state;
468	bool port_up;
469	int port;
470	int registered;
471	int allocated;
472	int stride;
473	int rx_csum;
474	u64 mac;
475	int mac_index;
476	unsigned max_mtu;
477	int base_qpn;
478
479	struct mlx4_en_rss_map rss_map;
c27a02cd YP	480	u32 flags;
	481	#define MLX4_EN_FLAG_PROMISC 0x1
	482	u32 tx_ring_num;
	483	u32 rx_ring_num;
	484	u32 rx_skb_size;
	485	struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
	486	u16 num_frags;
	487	u16 log_rx_info;
	488
	489	struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
	490	struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
	491	struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
	492	struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
	493	struct work_struct mcast_task;
	494	struct work_struct mac_task;
c27a02cd YP	495	struct work_struct watchdog_task;
	496	struct work_struct linkstate_task;
	497	struct delayed_work stats_task;
	498	struct mlx4_en_perf_stats pstats;
	499	struct mlx4_en_pkt_stats pkstats;
	500	struct mlx4_en_port_stats port_stats;
	501	struct dev_mc_list *mc_list;
	502	struct mlx4_en_stat_out_mbox hw_stats;
	503	};
	504
	505
	506	void mlx4_en_destroy_netdev(struct net_device *dev);
	507	int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
	508	struct mlx4_en_port_profile *prof);
	509
18cc42a3 YP	510	int mlx4_en_start_port(struct net_device *dev);
	511	void mlx4_en_stop_port(struct net_device *dev);
	512
	513	void mlx4_en_free_resources(struct mlx4_en_priv *priv);
	514	int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
	515
c27a02cd YP	516	int mlx4_en_create_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq,
	517	int entries, int ring, enum cq_type mode);
	518	void mlx4_en_destroy_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	519	int mlx4_en_activate_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	520	void mlx4_en_deactivate_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	521	int mlx4_en_set_cq_moder(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	522	int mlx4_en_arm_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	523
	524	void mlx4_en_poll_tx_cq(unsigned long data);
	525	void mlx4_en_tx_irq(struct mlx4_cq *mcq);
f813cad8	526	u16 mlx4_en_select_queue(struct net_device dev, struct sk_buff skb);
c27a02cd YP	527	int mlx4_en_xmit(struct sk_buff skb, struct net_device dev);
	528
	529	int mlx4_en_create_tx_ring(struct mlx4_en_priv priv, struct mlx4_en_tx_ring ring,
	530	u32 size, u16 stride);
	531	void mlx4_en_destroy_tx_ring(struct mlx4_en_priv priv, struct mlx4_en_tx_ring ring);
	532	int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
	533	struct mlx4_en_tx_ring *ring,
	534	int cq, int srqn);
	535	void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
	536	struct mlx4_en_tx_ring *ring);
	537
	538	int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
	539	struct mlx4_en_rx_ring *ring,
	540	u32 size, u16 stride);
	541	void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
	542	struct mlx4_en_rx_ring *ring);
	543	int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
	544	void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
	545	struct mlx4_en_rx_ring *ring);
	546	int mlx4_en_process_rx_cq(struct net_device *dev,
	547	struct mlx4_en_cq *cq,
	548	int budget);
	549	int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
	550	void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
	551	int is_tx, int rss, int qpn, int cqn, int srqn,
	552	struct mlx4_qp_context *context);
966508f7	553	void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
c27a02cd YP	554	int mlx4_en_map_buffer(struct mlx4_buf *buf);
	555	void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
	556
	557	void mlx4_en_calc_rx_buf(struct net_device *dev);
	558	void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv,
	559	struct mlx4_en_rss_map *rss_map,
	560	int num_entries, int num_rings);
c27a02cd YP	561	int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
	562	void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
	563	int mlx4_en_free_tx_buf(struct net_device dev, struct mlx4_en_tx_ring ring);
c27a02cd YP	564	void mlx4_en_rx_irq(struct mlx4_cq *mcq);
	565
	566	int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
	567	int mlx4_SET_VLAN_FLTR(struct mlx4_dev dev, u8 port, struct vlan_group grp);
	568	int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
	569	u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
	570	int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
	571	u8 promisc);
	572
	573	int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
	574
	575	/*
	576	* Globals
	577	*/
	578	extern const struct ethtool_ops mlx4_en_ethtool_ops;
	579	#endif