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1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
3 | * Copyright (c) 2005 Mellanox Technologies. All rights reserved. | |
4 | * Copyright (c) 2006, 2007 Cisco Systems. All rights reserved. | |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #ifndef MLX4_FW_H | |
36 | #define MLX4_FW_H | |
37 | ||
38 | #include "mlx4.h" | |
39 | #include "icm.h" | |
40 | ||
41 | struct mlx4_dev_cap { | |
42 | int max_srq_sz; | |
43 | int max_qp_sz; | |
44 | int reserved_qps; | |
45 | int max_qps; | |
46 | int reserved_srqs; | |
47 | int max_srqs; | |
48 | int max_cq_sz; | |
49 | int reserved_cqs; | |
50 | int max_cqs; | |
51 | int max_mpts; | |
52 | int reserved_eqs; | |
53 | int max_eqs; | |
54 | int reserved_mtts; | |
55 | int max_mrw_sz; | |
56 | int reserved_mrws; | |
57 | int max_mtt_seg; | |
58 | int max_requester_per_qp; | |
59 | int max_responder_per_qp; | |
60 | int max_rdma_global; | |
61 | int local_ca_ack_delay; | |
225c7b1f | 62 | int num_ports; |
149983af | 63 | u32 max_msg_sz; |
5ae2a7a8 RD |
64 | int max_mtu[MLX4_MAX_PORTS + 1]; |
65 | int max_port_width[MLX4_MAX_PORTS + 1]; | |
66 | int max_vl[MLX4_MAX_PORTS + 1]; | |
67 | int max_gids[MLX4_MAX_PORTS + 1]; | |
68 | int max_pkeys[MLX4_MAX_PORTS + 1]; | |
225c7b1f | 69 | u16 stat_rate_support; |
225c7b1f RD |
70 | u32 flags; |
71 | int reserved_uars; | |
72 | int uar_size; | |
73 | int min_page_sz; | |
74 | int bf_reg_size; | |
75 | int bf_regs_per_page; | |
76 | int max_sq_sg; | |
77 | int max_sq_desc_sz; | |
78 | int max_rq_sg; | |
79 | int max_rq_desc_sz; | |
80 | int max_qp_per_mcg; | |
81 | int reserved_mgms; | |
82 | int max_mcgs; | |
83 | int reserved_pds; | |
84 | int max_pds; | |
85 | int qpc_entry_sz; | |
86 | int rdmarc_entry_sz; | |
87 | int altc_entry_sz; | |
88 | int aux_entry_sz; | |
89 | int srq_entry_sz; | |
90 | int cqc_entry_sz; | |
91 | int eqc_entry_sz; | |
92 | int dmpt_entry_sz; | |
93 | int cmpt_entry_sz; | |
94 | int mtt_entry_sz; | |
95 | int resize_srq; | |
96 | u8 bmme_flags; | |
97 | u32 reserved_lkey; | |
98 | u64 max_icm_sz; | |
b832be1e | 99 | int max_gso_sz; |
225c7b1f RD |
100 | }; |
101 | ||
102 | struct mlx4_adapter { | |
225c7b1f RD |
103 | char board_id[MLX4_BOARD_ID_LEN]; |
104 | u8 inta_pin; | |
105 | }; | |
106 | ||
107 | struct mlx4_init_hca_param { | |
108 | u64 qpc_base; | |
109 | u64 rdmarc_base; | |
110 | u64 auxc_base; | |
111 | u64 altc_base; | |
112 | u64 srqc_base; | |
113 | u64 cqc_base; | |
114 | u64 eqc_base; | |
115 | u64 mc_base; | |
116 | u64 dmpt_base; | |
117 | u64 cmpt_base; | |
118 | u64 mtt_base; | |
119 | u16 log_mc_entry_sz; | |
120 | u16 log_mc_hash_sz; | |
121 | u8 log_num_qps; | |
122 | u8 log_num_srqs; | |
123 | u8 log_num_cqs; | |
124 | u8 log_num_eqs; | |
125 | u8 log_rd_per_qp; | |
126 | u8 log_mc_table_sz; | |
127 | u8 log_mpt_sz; | |
128 | u8 log_uar_sz; | |
129 | }; | |
130 | ||
131 | struct mlx4_init_ib_param { | |
132 | int port_width; | |
133 | int vl_cap; | |
134 | int mtu_cap; | |
135 | u16 gid_cap; | |
136 | u16 pkey_cap; | |
137 | int set_guid0; | |
138 | u64 guid0; | |
139 | int set_node_guid; | |
140 | u64 node_guid; | |
141 | int set_si_guid; | |
142 | u64 si_guid; | |
143 | }; | |
144 | ||
145 | struct mlx4_set_ib_param { | |
146 | int set_si_guid; | |
147 | int reset_qkey_viol; | |
148 | u64 si_guid; | |
149 | u32 cap_mask; | |
150 | }; | |
151 | ||
152 | int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap); | |
153 | int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm); | |
154 | int mlx4_UNMAP_FA(struct mlx4_dev *dev); | |
155 | int mlx4_RUN_FW(struct mlx4_dev *dev); | |
156 | int mlx4_QUERY_FW(struct mlx4_dev *dev); | |
157 | int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter); | |
158 | int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param); | |
159 | int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic); | |
160 | int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt); | |
161 | int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages); | |
162 | int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm); | |
163 | int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev); | |
164 | int mlx4_NOP(struct mlx4_dev *dev); | |
165 | ||
166 | #endif /* MLX4_FW_H */ |