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[linux-2.6-block.git] / drivers / net / mlx4 / fw.c
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225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/mlx4/cmd.h>
36
37#include "fw.h"
38#include "icm.h"
39
fe40900f 40enum {
5ae2a7a8
RD		 41 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
42 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
43 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 44};
45
225c7b1f
RD		 46extern void __buggy_use_of_MLX4_GET(void);
47extern void __buggy_use_of_MLX4_PUT(void);
48
49#define MLX4_GET(dest, source, offset) \
50 do { \
51 void *__p = (char *) (source) + (offset); \
52 switch (sizeof (dest)) { \
53 case 1: (dest) = *(u8 *) __p; break; \
54 case 2: (dest) = be16_to_cpup(__p); break; \
55 case 4: (dest) = be32_to_cpup(__p); break; \
56 case 8: (dest) = be64_to_cpup(__p); break; \
57 default: __buggy_use_of_MLX4_GET(); \
58 } \
59 } while (0)
60
61#define MLX4_PUT(dest, source, offset) \
62 do { \
63 void *__d = ((char *) (dest) + (offset)); \
64 switch (sizeof(source)) { \
65 case 1: *(u8 *) __d = (source); break; \
66 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
67 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
68 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
69 default: __buggy_use_of_MLX4_PUT(); \
70 } \
71 } while (0)
72
73static void dump_dev_cap_flags(struct mlx4_dev *dev, u32 flags)
74{
75 static const char *fname[] = {
76 [ 0] = "RC transport",
77 [ 1] = "UC transport",
78 [ 2] = "UD transport",
79 [ 3] = "SRC transport",
80 [ 4] = "reliable multicast",
81 [ 5] = "FCoIB support",
82 [ 6] = "SRQ support",
83 [ 7] = "IPoIB checksum offload",
84 [ 8] = "P_Key violation counter",
85 [ 9] = "Q_Key violation counter",
86 [10] = "VMM",
87 [16] = "MW support",
88 [17] = "APM support",
89 [18] = "Atomic ops support",
90 [19] = "Raw multicast support",
91 [20] = "Address vector port checking support",
92 [21] = "UD multicast support",
93 [24] = "Demand paging support",
94 [25] = "Router support"
95 };
96 int i;
97
98 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 99 for (i = 0; i < ARRAY_SIZE(fname); ++i)
225c7b1f
RD		 100 if (fname[i] && (flags & (1 << i)))
101 mlx4_dbg(dev, " %s\n", fname[i]);
102}
103
104int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
105{
106 struct mlx4_cmd_mailbox *mailbox;
107 u32 *outbox;
108 u8 field;
109 u16 size;
110 u16 stat_rate;
111 int err;
5ae2a7a8 112 int i;
225c7b1f
RD		 113
114#define QUERY_DEV_CAP_OUT_SIZE 0x100
115#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
116#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
117#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
118#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
119#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
120#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
121#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
122#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
123#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
124#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
125#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
126#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
127#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
128#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
129#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
130#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
131#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
132#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
133#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
134#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
135#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
136#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
137#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
138#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
139#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
140#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
141#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
142#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
143#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
144#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
145#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
146#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
147#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
148#define QUERY_DEV_CAP_BF_OFFSET 0x4c
149#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
150#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
151#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
152#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
153#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
154#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
155#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
156#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
157#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
158#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
159#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
160#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
161#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
162#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
163#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
164#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
165#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
166#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
167#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
168#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
169#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
170#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
171#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x97
172#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
173#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
174
175 mailbox = mlx4_alloc_cmd_mailbox(dev);
176 if (IS_ERR(mailbox))
177 return PTR_ERR(mailbox);
178 outbox = mailbox->buf;
179
180 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
181 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 182 if (err)
183 goto out;
184
185 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
186 dev_cap->reserved_qps = 1 << (field & 0xf);
187 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
188 dev_cap->max_qps = 1 << (field & 0x1f);
189 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
190 dev_cap->reserved_srqs = 1 << (field >> 4);
191 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
192 dev_cap->max_srqs = 1 << (field & 0x1f);
193 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
194 dev_cap->max_cq_sz = 1 << field;
195 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
196 dev_cap->reserved_cqs = 1 << (field & 0xf);
197 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
198 dev_cap->max_cqs = 1 << (field & 0x1f);
199 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
200 dev_cap->max_mpts = 1 << (field & 0x3f);
201 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
202 dev_cap->reserved_eqs = 1 << (field & 0xf);
203 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
204 dev_cap->max_eqs = 1 << (field & 0x7);
205 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
206 dev_cap->reserved_mtts = 1 << (field >> 4);
207 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
208 dev_cap->max_mrw_sz = 1 << field;
209 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
210 dev_cap->reserved_mrws = 1 << (field & 0xf);
211 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
212 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
213 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
214 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
215 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
216 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
217 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
218 dev_cap->max_rdma_global = 1 << (field & 0x3f);
219 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
220 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 221 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 222 dev_cap->num_ports = field & 0xf;
225c7b1f
RD		 223 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
224 dev_cap->stat_rate_support = stat_rate;
225c7b1f
RD		 225 MLX4_GET(dev_cap->flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
226 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
227 dev_cap->reserved_uars = field >> 4;
228 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
229 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
230 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
231 dev_cap->min_page_sz = 1 << field;
232
233 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
234 if (field & 0x80) {
235 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
236 dev_cap->bf_reg_size = 1 << (field & 0x1f);
237 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
238 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
239 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
240 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
241 } else {
242 dev_cap->bf_reg_size = 0;
243 mlx4_dbg(dev, "BlueFlame not available\n");
244 }
245
246 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
247 dev_cap->max_sq_sg = field;
248 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
249 dev_cap->max_sq_desc_sz = size;
250
251 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
252 dev_cap->max_qp_per_mcg = 1 << field;
253 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
254 dev_cap->reserved_mgms = field & 0xf;
255 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
256 dev_cap->max_mcgs = 1 << field;
257 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
258 dev_cap->reserved_pds = field >> 4;
259 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
260 dev_cap->max_pds = 1 << (field & 0x3f);
261
262 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
263 dev_cap->rdmarc_entry_sz = size;
264 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
265 dev_cap->qpc_entry_sz = size;
266 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
267 dev_cap->aux_entry_sz = size;
268 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
269 dev_cap->altc_entry_sz = size;
270 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
271 dev_cap->eqc_entry_sz = size;
272 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
273 dev_cap->cqc_entry_sz = size;
274 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
275 dev_cap->srq_entry_sz = size;
276 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
277 dev_cap->cmpt_entry_sz = size;
278 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
279 dev_cap->mtt_entry_sz = size;
280 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
281 dev_cap->dmpt_entry_sz = size;
282
283 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
284 dev_cap->max_srq_sz = 1 << field;
285 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
286 dev_cap->max_qp_sz = 1 << field;
287 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
288 dev_cap->resize_srq = field & 1;
289 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
290 dev_cap->max_rq_sg = field;
291 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
292 dev_cap->max_rq_desc_sz = size;
293
294 MLX4_GET(dev_cap->bmme_flags, outbox,
295 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
296 MLX4_GET(dev_cap->reserved_lkey, outbox,
297 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
298 MLX4_GET(dev_cap->max_icm_sz, outbox,
299 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
300
5ae2a7a8
RD		 301 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
302 for (i = 1; i <= dev_cap->num_ports; ++i) {
303 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
304 dev_cap->max_vl[i] = field >> 4;
305 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
306 dev_cap->max_mtu[i] = field >> 4;
307 dev_cap->max_port_width[i] = field & 0xf;
308 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
309 dev_cap->max_gids[i] = 1 << (field & 0xf);
310 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
311 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
312 }
313 } else {
314#define QUERY_PORT_MTU_OFFSET 0x01
315#define QUERY_PORT_WIDTH_OFFSET 0x06
316#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
317#define QUERY_PORT_MAX_VL_OFFSET 0x0b
318
319 for (i = 1; i <= dev_cap->num_ports; ++i) {
320 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
321 MLX4_CMD_TIME_CLASS_B);
322 if (err)
323 goto out;
324
325 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
326 dev_cap->max_mtu[i] = field & 0xf;
327 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
328 dev_cap->max_port_width[i] = field & 0xf;
329 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
330 dev_cap->max_gids[i] = 1 << (field >> 4);
331 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
332 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
333 dev_cap->max_vl[i] = field & 0xf;
334 }
335 }
336
225c7b1f
RD		 337 if (dev_cap->bmme_flags & 1)
338 mlx4_dbg(dev, "Base MM extensions: yes "
339 "(flags %d, rsvd L_Key %08x)\n",
340 dev_cap->bmme_flags, dev_cap->reserved_lkey);
341 else
342 mlx4_dbg(dev, "Base MM extensions: no\n");
343
344 /*
345 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
346 * we can't use any EQs whose doorbell falls on that page,
347 * even if the EQ itself isn't reserved.
348 */
349 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
350 dev_cap->reserved_eqs);
351
352 mlx4_dbg(dev, "Max ICM size %lld MB\n",
353 (unsigned long long) dev_cap->max_icm_sz >> 20);
354 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
355 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
356 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
357 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
358 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
359 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
360 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
361 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
362 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
363 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
364 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
365 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
366 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
367 dev_cap->max_pds, dev_cap->reserved_mgms);
368 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
369 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
370 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
5ae2a7a8
RD		 371 dev_cap->local_ca_ack_delay, 128 << dev_cap->max_mtu[1],
372 dev_cap->max_port_width[1]);
225c7b1f
RD		 373 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
374 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
375 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
376 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
377
378 dump_dev_cap_flags(dev, dev_cap->flags);
379
380out:
381 mlx4_free_cmd_mailbox(dev, mailbox);
382 return err;
383}
384
385int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
386{
387 struct mlx4_cmd_mailbox *mailbox;
388 struct mlx4_icm_iter iter;
389 __be64 *pages;
390 int lg;
391 int nent = 0;
392 int i;
393 int err = 0;
394 int ts = 0, tc = 0;
395
396 mailbox = mlx4_alloc_cmd_mailbox(dev);
397 if (IS_ERR(mailbox))
398 return PTR_ERR(mailbox);
399 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
400 pages = mailbox->buf;
401
402 for (mlx4_icm_first(icm, &iter);
403 !mlx4_icm_last(&iter);
404 mlx4_icm_next(&iter)) {
405 /*
406 * We have to pass pages that are aligned to their
407 * size, so find the least significant 1 in the
408 * address or size and use that as our log2 size.
409 */
410 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
411 if (lg < MLX4_ICM_PAGE_SHIFT) {
412 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
413 MLX4_ICM_PAGE_SIZE,
414 (unsigned long long) mlx4_icm_addr(&iter),
415 mlx4_icm_size(&iter));
416 err = -EINVAL;
417 goto out;
418 }
419
420 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
421 if (virt != -1) {
422 pages[nent * 2] = cpu_to_be64(virt);
423 virt += 1 << lg;
424 }
425
426 pages[nent * 2 + 1] =
427 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
428 (lg - MLX4_ICM_PAGE_SHIFT));
429 ts += 1 << (lg - 10);
430 ++tc;
431
432 if (++nent == MLX4_MAILBOX_SIZE / 16) {
433 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
434 MLX4_CMD_TIME_CLASS_B);
435 if (err)
436 goto out;
437 nent = 0;
438 }
439 }
440 }
441
442 if (nent)
443 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
444 if (err)
445 goto out;
446
447 switch (op) {
448 case MLX4_CMD_MAP_FA:
449 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
450 break;
451 case MLX4_CMD_MAP_ICM_AUX:
452 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
453 break;
454 case MLX4_CMD_MAP_ICM:
455 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
456 tc, ts, (unsigned long long) virt - (ts << 10));
457 break;
458 }
459
460out:
461 mlx4_free_cmd_mailbox(dev, mailbox);
462 return err;
463}
464
465int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
466{
467 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
468}
469
470int mlx4_UNMAP_FA(struct mlx4_dev *dev)
471{
472 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
473}
474
475
476int mlx4_RUN_FW(struct mlx4_dev *dev)
477{
478 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
479}
480
481int mlx4_QUERY_FW(struct mlx4_dev *dev)
482{
483 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
484 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
485 struct mlx4_cmd_mailbox *mailbox;
486 u32 *outbox;
487 int err = 0;
488 u64 fw_ver;
fe40900f 489 u16 cmd_if_rev;
225c7b1f
RD		 490 u8 lg;
491
492#define QUERY_FW_OUT_SIZE 0x100
493#define QUERY_FW_VER_OFFSET 0x00
fe40900f 494#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 495#define QUERY_FW_MAX_CMD_OFFSET 0x0f
496#define QUERY_FW_ERR_START_OFFSET 0x30
497#define QUERY_FW_ERR_SIZE_OFFSET 0x38
498#define QUERY_FW_ERR_BAR_OFFSET 0x3c
499
500#define QUERY_FW_SIZE_OFFSET 0x00
501#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
502#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
503
504 mailbox = mlx4_alloc_cmd_mailbox(dev);
505 if (IS_ERR(mailbox))
506 return PTR_ERR(mailbox);
507 outbox = mailbox->buf;
508
509 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
510 MLX4_CMD_TIME_CLASS_A);
511 if (err)
512 goto out;
513
514 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
515 /*
3e1db334 516 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 517 * version, so swap here.
518 */
519 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
520 ((fw_ver & 0xffff0000ull) >> 16) |
521 ((fw_ver & 0x0000ffffull) << 16);
522
fe40900f 523 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 524 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
525 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 526 mlx4_err(dev, "Installed FW has unsupported "
527 "command interface revision %d.\n",
528 cmd_if_rev);
529 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
530 (int) (dev->caps.fw_ver >> 32),
531 (int) (dev->caps.fw_ver >> 16) & 0xffff,
532 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 533 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
534 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 535 err = -ENODEV;
536 goto out;
537 }
538
5ae2a7a8
RD		 539 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
540 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
541
225c7b1f
RD		 542 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
543 cmd->max_cmds = 1 << lg;
544
fe40900f 545 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 546 (int) (dev->caps.fw_ver >> 32),
547 (int) (dev->caps.fw_ver >> 16) & 0xffff,
548 (int) dev->caps.fw_ver & 0xffff,
fe40900f 549 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 550
551 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
552 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
553 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
554 fw->catas_bar = (fw->catas_bar >> 6) * 2;
555
556 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
557 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
558
559 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
560 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
561 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
562 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
563
564 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
565
566 /*
567 * Round up number of system pages needed in case
568 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
569 */
570 fw->fw_pages =
571 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
572 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
573
574 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
575 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
576
577out:
578 mlx4_free_cmd_mailbox(dev, mailbox);
579 return err;
580}
581
582static void get_board_id(void *vsd, char *board_id)
583{
584 int i;
585
586#define VSD_OFFSET_SIG1 0x00
587#define VSD_OFFSET_SIG2 0xde
588#define VSD_OFFSET_MLX_BOARD_ID 0xd0
589#define VSD_OFFSET_TS_BOARD_ID 0x20
590
591#define VSD_SIGNATURE_TOPSPIN 0x5ad
592
593 memset(board_id, 0, MLX4_BOARD_ID_LEN);
594
595 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
596 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
597 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
598 } else {
599 /*
600 * The board ID is a string but the firmware byte
601 * swaps each 4-byte word before passing it back to
602 * us. Therefore we need to swab it before printing.
603 */
604 for (i = 0; i < 4; ++i)
605 ((u32 *) board_id)[i] =
606 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
607 }
608}
609
610int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
611{
612 struct mlx4_cmd_mailbox *mailbox;
613 u32 *outbox;
614 int err;
615
616#define QUERY_ADAPTER_OUT_SIZE 0x100
617#define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00
618#define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04
619#define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08
620#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
621#define QUERY_ADAPTER_VSD_OFFSET 0x20
622
623 mailbox = mlx4_alloc_cmd_mailbox(dev);
624 if (IS_ERR(mailbox))
625 return PTR_ERR(mailbox);
626 outbox = mailbox->buf;
627
628 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
629 MLX4_CMD_TIME_CLASS_A);
630 if (err)
631 goto out;
632
633 MLX4_GET(adapter->vendor_id, outbox, QUERY_ADAPTER_VENDOR_ID_OFFSET);
634 MLX4_GET(adapter->device_id, outbox, QUERY_ADAPTER_DEVICE_ID_OFFSET);
635 MLX4_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET);
636 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
637
638 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
639 adapter->board_id);
640
641out:
642 mlx4_free_cmd_mailbox(dev, mailbox);
643 return err;
644}
645
646int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
647{
648 struct mlx4_cmd_mailbox *mailbox;
649 __be32 *inbox;
650 int err;
651
652#define INIT_HCA_IN_SIZE 0x200
653#define INIT_HCA_VERSION_OFFSET 0x000
654#define INIT_HCA_VERSION 2
655#define INIT_HCA_FLAGS_OFFSET 0x014
656#define INIT_HCA_QPC_OFFSET 0x020
657#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
658#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
659#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
660#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
661#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
662#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
663#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
664#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
665#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
666#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
667#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
668#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
669#define INIT_HCA_MCAST_OFFSET 0x0c0
670#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
671#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
672#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
673#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
674#define INIT_HCA_TPT_OFFSET 0x0f0
675#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
676#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
677#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
678#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
679#define INIT_HCA_UAR_OFFSET 0x120
680#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
681#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
682
683 mailbox = mlx4_alloc_cmd_mailbox(dev);
684 if (IS_ERR(mailbox))
685 return PTR_ERR(mailbox);
686 inbox = mailbox->buf;
687
688 memset(inbox, 0, INIT_HCA_IN_SIZE);
689
690 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
691
692#if defined(__LITTLE_ENDIAN)
693 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
694#elif defined(__BIG_ENDIAN)
695 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
696#else
697#error Host endianness not defined
698#endif
699 /* Check port for UD address vector: */
700 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
701
702 /* QPC/EEC/CQC/EQC/RDMARC attributes */
703
704 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
705 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
706 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
707 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
708 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
709 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
710 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
711 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
712 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
713 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
714 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
715 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
716
717 /* multicast attributes */
718
719 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
720 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
721 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
722 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
723
724 /* TPT attributes */
725
726 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
727 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
728 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
729 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
730
731 /* UAR attributes */
732
733 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
734 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
735
736 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 1000);
737
738 if (err)
739 mlx4_err(dev, "INIT_HCA returns %d\n", err);
740
741 mlx4_free_cmd_mailbox(dev, mailbox);
742 return err;
743}
744
5ae2a7a8 745int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 746{
747 struct mlx4_cmd_mailbox *mailbox;
748 u32 *inbox;
749 int err;
750 u32 flags;
5ae2a7a8 751 u16 field;
225c7b1f 752
5ae2a7a8 753 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 754#define INIT_PORT_IN_SIZE 256
755#define INIT_PORT_FLAGS_OFFSET 0x00
756#define INIT_PORT_FLAG_SIG (1 << 18)
757#define INIT_PORT_FLAG_NG (1 << 17)
758#define INIT_PORT_FLAG_G0 (1 << 16)
759#define INIT_PORT_VL_SHIFT 4
760#define INIT_PORT_PORT_WIDTH_SHIFT 8
761#define INIT_PORT_MTU_OFFSET 0x04
762#define INIT_PORT_MAX_GID_OFFSET 0x06
763#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
764#define INIT_PORT_GUID0_OFFSET 0x10
765#define INIT_PORT_NODE_GUID_OFFSET 0x18
766#define INIT_PORT_SI_GUID_OFFSET 0x20
767
5ae2a7a8
RD		 768 mailbox = mlx4_alloc_cmd_mailbox(dev);
769 if (IS_ERR(mailbox))
770 return PTR_ERR(mailbox);
771 inbox = mailbox->buf;
225c7b1f 772
5ae2a7a8 773 memset(inbox, 0, INIT_PORT_IN_SIZE);
225c7b1f 774
5ae2a7a8
RD		 775 flags = 0;
776 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
777 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
778 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 779
5ae2a7a8
RD		 780 field = 128 << dev->caps.mtu_cap[port];
781 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
782 field = dev->caps.gid_table_len[port];
783 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
784 field = dev->caps.pkey_table_len[port];
785 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 786
5ae2a7a8
RD		 787 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
788 MLX4_CMD_TIME_CLASS_A);
225c7b1f 789
5ae2a7a8
RD		 790 mlx4_free_cmd_mailbox(dev, mailbox);
791 } else
792 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
793 MLX4_CMD_TIME_CLASS_A);
225c7b1f
RD		 794
795 return err;
796}
797EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
798
799int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
800{
801 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
802}
803EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
804
805int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
806{
807 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
808}
809
810int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
811{
812 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
813 MLX4_CMD_SET_ICM_SIZE,
814 MLX4_CMD_TIME_CLASS_A);
815 if (ret)
816 return ret;
817
818 /*
819 * Round up number of system pages needed in case
820 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
821 */
822 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
823 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
824
825 return 0;
826}
827
828int mlx4_NOP(struct mlx4_dev *dev)
829{
830 /* Input modifier of 0x1f means "finish as soon as possible." */
831 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
832}
Linux 6.x block layer and io_uring tree(s)