Commit | Line | Data |
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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <asm/page.h> | |
35 | #include <linux/mlx4/cq.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/if_vlan.h> | |
40 | #include <linux/vmalloc.h> | |
fa37a958 | 41 | #include <linux/tcp.h> |
c27a02cd YP |
42 | |
43 | #include "mlx4_en.h" | |
44 | ||
45 | enum { | |
46 | MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ | |
87a5c389 | 47 | MAX_BF = 256, |
c27a02cd YP |
48 | }; |
49 | ||
50 | static int inline_thold __read_mostly = MAX_INLINE; | |
51 | ||
52 | module_param_named(inline_thold, inline_thold, int, 0444); | |
af901ca1 | 53 | MODULE_PARM_DESC(inline_thold, "threshold for using inline data"); |
c27a02cd YP |
54 | |
55 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, | |
87a5c389 | 56 | struct mlx4_en_tx_ring *ring, int qpn, u32 size, |
c27a02cd YP |
57 | u16 stride) |
58 | { | |
59 | struct mlx4_en_dev *mdev = priv->mdev; | |
60 | int tmp; | |
61 | int err; | |
62 | ||
63 | ring->size = size; | |
64 | ring->size_mask = size - 1; | |
65 | ring->stride = stride; | |
66 | ||
67 | inline_thold = min(inline_thold, MAX_INLINE); | |
68 | ||
69 | spin_lock_init(&ring->comp_lock); | |
70 | ||
71 | tmp = size * sizeof(struct mlx4_en_tx_info); | |
72 | ring->tx_info = vmalloc(tmp); | |
73 | if (!ring->tx_info) { | |
453a6082 | 74 | en_err(priv, "Failed allocating tx_info ring\n"); |
c27a02cd YP |
75 | return -ENOMEM; |
76 | } | |
453a6082 | 77 | en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
78 | ring->tx_info, tmp); |
79 | ||
80 | ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); | |
81 | if (!ring->bounce_buf) { | |
453a6082 | 82 | en_err(priv, "Failed allocating bounce buffer\n"); |
c27a02cd YP |
83 | err = -ENOMEM; |
84 | goto err_tx; | |
85 | } | |
86 | ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); | |
87 | ||
88 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, | |
89 | 2 * PAGE_SIZE); | |
90 | if (err) { | |
453a6082 | 91 | en_err(priv, "Failed allocating hwq resources\n"); |
c27a02cd YP |
92 | goto err_bounce; |
93 | } | |
94 | ||
95 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
96 | if (err) { | |
453a6082 | 97 | en_err(priv, "Failed to map TX buffer\n"); |
c27a02cd YP |
98 | goto err_hwq_res; |
99 | } | |
100 | ||
101 | ring->buf = ring->wqres.buf.direct.buf; | |
102 | ||
453a6082 YP |
103 | en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d " |
104 | "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size, | |
105 | ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map); | |
c27a02cd | 106 | |
87a5c389 | 107 | ring->qpn = qpn; |
c27a02cd YP |
108 | err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp); |
109 | if (err) { | |
453a6082 | 110 | en_err(priv, "Failed allocating qp %d\n", ring->qpn); |
87a5c389 | 111 | goto err_map; |
c27a02cd | 112 | } |
966508f7 | 113 | ring->qp.event = mlx4_en_sqp_event; |
c27a02cd | 114 | |
87a5c389 YP |
115 | err = mlx4_bf_alloc(mdev->dev, &ring->bf); |
116 | if (err) { | |
117 | en_dbg(DRV, priv, "working without blueflame (%d)", err); | |
118 | ring->bf.uar = &mdev->priv_uar; | |
119 | ring->bf.uar->map = mdev->uar_map; | |
120 | ring->bf_enabled = false; | |
121 | } else | |
122 | ring->bf_enabled = true; | |
123 | ||
c27a02cd YP |
124 | return 0; |
125 | ||
c27a02cd YP |
126 | err_map: |
127 | mlx4_en_unmap_buffer(&ring->wqres.buf); | |
128 | err_hwq_res: | |
129 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
130 | err_bounce: | |
131 | kfree(ring->bounce_buf); | |
132 | ring->bounce_buf = NULL; | |
133 | err_tx: | |
134 | vfree(ring->tx_info); | |
135 | ring->tx_info = NULL; | |
136 | return err; | |
137 | } | |
138 | ||
139 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, | |
140 | struct mlx4_en_tx_ring *ring) | |
141 | { | |
142 | struct mlx4_en_dev *mdev = priv->mdev; | |
453a6082 | 143 | en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); |
c27a02cd | 144 | |
87a5c389 YP |
145 | if (ring->bf_enabled) |
146 | mlx4_bf_free(mdev->dev, &ring->bf); | |
c27a02cd YP |
147 | mlx4_qp_remove(mdev->dev, &ring->qp); |
148 | mlx4_qp_free(mdev->dev, &ring->qp); | |
149 | mlx4_qp_release_range(mdev->dev, ring->qpn, 1); | |
150 | mlx4_en_unmap_buffer(&ring->wqres.buf); | |
151 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
152 | kfree(ring->bounce_buf); | |
153 | ring->bounce_buf = NULL; | |
154 | vfree(ring->tx_info); | |
155 | ring->tx_info = NULL; | |
156 | } | |
157 | ||
158 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, | |
159 | struct mlx4_en_tx_ring *ring, | |
9f519f68 | 160 | int cq) |
c27a02cd YP |
161 | { |
162 | struct mlx4_en_dev *mdev = priv->mdev; | |
163 | int err; | |
164 | ||
165 | ring->cqn = cq; | |
166 | ring->prod = 0; | |
167 | ring->cons = 0xffffffff; | |
168 | ring->last_nr_txbb = 1; | |
169 | ring->poll_cnt = 0; | |
170 | ring->blocked = 0; | |
171 | memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); | |
172 | memset(ring->buf, 0, ring->buf_size); | |
173 | ||
174 | ring->qp_state = MLX4_QP_STATE_RST; | |
175 | ring->doorbell_qpn = swab32(ring->qp.qpn << 8); | |
176 | ||
177 | mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, | |
9f519f68 | 178 | ring->cqn, &ring->context); |
87a5c389 YP |
179 | if (ring->bf_enabled) |
180 | ring->context.usr_page = cpu_to_be32(ring->bf.uar->index); | |
c27a02cd YP |
181 | |
182 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, | |
183 | &ring->qp, &ring->qp_state); | |
184 | ||
185 | return err; | |
186 | } | |
187 | ||
188 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, | |
189 | struct mlx4_en_tx_ring *ring) | |
190 | { | |
191 | struct mlx4_en_dev *mdev = priv->mdev; | |
192 | ||
193 | mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, | |
194 | MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); | |
195 | } | |
196 | ||
197 | ||
198 | static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, | |
199 | struct mlx4_en_tx_ring *ring, | |
200 | int index, u8 owner) | |
201 | { | |
202 | struct mlx4_en_dev *mdev = priv->mdev; | |
203 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; | |
204 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; | |
205 | struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; | |
206 | struct sk_buff *skb = tx_info->skb; | |
207 | struct skb_frag_struct *frag; | |
208 | void *end = ring->buf + ring->buf_size; | |
209 | int frags = skb_shinfo(skb)->nr_frags; | |
210 | int i; | |
211 | __be32 *ptr = (__be32 *)tx_desc; | |
212 | __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); | |
213 | ||
214 | /* Optimize the common case when there are no wraparounds */ | |
215 | if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { | |
41efea5a YP |
216 | if (!tx_info->inl) { |
217 | if (tx_info->linear) { | |
218 | pci_unmap_single(mdev->pdev, | |
219 | (dma_addr_t) be64_to_cpu(data->addr), | |
c27a02cd YP |
220 | be32_to_cpu(data->byte_count), |
221 | PCI_DMA_TODEVICE); | |
41efea5a YP |
222 | ++data; |
223 | } | |
c27a02cd | 224 | |
41efea5a YP |
225 | for (i = 0; i < frags; i++) { |
226 | frag = &skb_shinfo(skb)->frags[i]; | |
227 | pci_unmap_page(mdev->pdev, | |
228 | (dma_addr_t) be64_to_cpu(data[i].addr), | |
229 | frag->size, PCI_DMA_TODEVICE); | |
230 | } | |
c27a02cd YP |
231 | } |
232 | /* Stamp the freed descriptor */ | |
233 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) { | |
234 | *ptr = stamp; | |
235 | ptr += STAMP_DWORDS; | |
236 | } | |
237 | ||
238 | } else { | |
41efea5a YP |
239 | if (!tx_info->inl) { |
240 | if ((void *) data >= end) { | |
241 | data = (struct mlx4_wqe_data_seg *) | |
242 | (ring->buf + ((void *) data - end)); | |
243 | } | |
c27a02cd | 244 | |
41efea5a YP |
245 | if (tx_info->linear) { |
246 | pci_unmap_single(mdev->pdev, | |
247 | (dma_addr_t) be64_to_cpu(data->addr), | |
c27a02cd YP |
248 | be32_to_cpu(data->byte_count), |
249 | PCI_DMA_TODEVICE); | |
41efea5a YP |
250 | ++data; |
251 | } | |
c27a02cd | 252 | |
41efea5a YP |
253 | for (i = 0; i < frags; i++) { |
254 | /* Check for wraparound before unmapping */ | |
255 | if ((void *) data >= end) | |
256 | data = (struct mlx4_wqe_data_seg *) ring->buf; | |
257 | frag = &skb_shinfo(skb)->frags[i]; | |
258 | pci_unmap_page(mdev->pdev, | |
c27a02cd YP |
259 | (dma_addr_t) be64_to_cpu(data->addr), |
260 | frag->size, PCI_DMA_TODEVICE); | |
eb4ad826 | 261 | ++data; |
41efea5a | 262 | } |
c27a02cd YP |
263 | } |
264 | /* Stamp the freed descriptor */ | |
265 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) { | |
266 | *ptr = stamp; | |
267 | ptr += STAMP_DWORDS; | |
268 | if ((void *) ptr >= end) { | |
269 | ptr = ring->buf; | |
270 | stamp ^= cpu_to_be32(0x80000000); | |
271 | } | |
272 | } | |
273 | ||
274 | } | |
275 | dev_kfree_skb_any(skb); | |
276 | return tx_info->nr_txbb; | |
277 | } | |
278 | ||
279 | ||
280 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) | |
281 | { | |
282 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
283 | int cnt = 0; | |
284 | ||
285 | /* Skip last polled descriptor */ | |
286 | ring->cons += ring->last_nr_txbb; | |
453a6082 | 287 | en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", |
c27a02cd YP |
288 | ring->cons, ring->prod); |
289 | ||
290 | if ((u32) (ring->prod - ring->cons) > ring->size) { | |
291 | if (netif_msg_tx_err(priv)) | |
453a6082 | 292 | en_warn(priv, "Tx consumer passed producer!\n"); |
c27a02cd YP |
293 | return 0; |
294 | } | |
295 | ||
296 | while (ring->cons != ring->prod) { | |
297 | ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, | |
298 | ring->cons & ring->size_mask, | |
299 | !!(ring->cons & ring->size)); | |
300 | ring->cons += ring->last_nr_txbb; | |
301 | cnt++; | |
302 | } | |
303 | ||
304 | if (cnt) | |
453a6082 | 305 | en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); |
c27a02cd YP |
306 | |
307 | return cnt; | |
308 | } | |
309 | ||
c27a02cd YP |
310 | |
311 | static void mlx4_en_process_tx_cq(struct net_device *dev, struct mlx4_en_cq *cq) | |
312 | { | |
313 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
314 | struct mlx4_cq *mcq = &cq->mcq; | |
315 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; | |
316 | struct mlx4_cqe *cqe = cq->buf; | |
317 | u16 index; | |
318 | u16 new_index; | |
319 | u32 txbbs_skipped = 0; | |
320 | u32 cq_last_sav; | |
321 | ||
322 | /* index always points to the first TXBB of the last polled descriptor */ | |
323 | index = ring->cons & ring->size_mask; | |
324 | new_index = be16_to_cpu(cqe->wqe_index) & ring->size_mask; | |
325 | if (index == new_index) | |
326 | return; | |
327 | ||
328 | if (!priv->port_up) | |
329 | return; | |
330 | ||
331 | /* | |
332 | * We use a two-stage loop: | |
333 | * - the first samples the HW-updated CQE | |
334 | * - the second frees TXBBs until the last sample | |
335 | * This lets us amortize CQE cache misses, while still polling the CQ | |
336 | * until is quiescent. | |
337 | */ | |
338 | cq_last_sav = mcq->cons_index; | |
339 | do { | |
340 | do { | |
341 | /* Skip over last polled CQE */ | |
342 | index = (index + ring->last_nr_txbb) & ring->size_mask; | |
343 | txbbs_skipped += ring->last_nr_txbb; | |
344 | ||
345 | /* Poll next CQE */ | |
346 | ring->last_nr_txbb = mlx4_en_free_tx_desc( | |
347 | priv, ring, index, | |
348 | !!((ring->cons + txbbs_skipped) & | |
349 | ring->size)); | |
350 | ++mcq->cons_index; | |
351 | ||
352 | } while (index != new_index); | |
353 | ||
354 | new_index = be16_to_cpu(cqe->wqe_index) & ring->size_mask; | |
355 | } while (index != new_index); | |
356 | AVG_PERF_COUNTER(priv->pstats.tx_coal_avg, | |
357 | (u32) (mcq->cons_index - cq_last_sav)); | |
358 | ||
359 | /* | |
360 | * To prevent CQ overflow we first update CQ consumer and only then | |
361 | * the ring consumer. | |
362 | */ | |
363 | mlx4_cq_set_ci(mcq); | |
364 | wmb(); | |
365 | ring->cons += txbbs_skipped; | |
366 | ||
367 | /* Wakeup Tx queue if this ring stopped it */ | |
368 | if (unlikely(ring->blocked)) { | |
c03ea21f YP |
369 | if ((u32) (ring->prod - ring->cons) <= |
370 | ring->size - HEADROOM - MAX_DESC_TXBBS) { | |
c27a02cd | 371 | ring->blocked = 0; |
f813cad8 | 372 | netif_tx_wake_queue(netdev_get_tx_queue(dev, cq->ring)); |
c27a02cd YP |
373 | priv->port_stats.wake_queue++; |
374 | } | |
375 | } | |
376 | } | |
377 | ||
378 | void mlx4_en_tx_irq(struct mlx4_cq *mcq) | |
379 | { | |
380 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
381 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
382 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; | |
383 | ||
48374ddc YP |
384 | if (!spin_trylock(&ring->comp_lock)) |
385 | return; | |
c27a02cd | 386 | mlx4_en_process_tx_cq(cq->dev, cq); |
48374ddc YP |
387 | mod_timer(&cq->timer, jiffies + 1); |
388 | spin_unlock(&ring->comp_lock); | |
c27a02cd YP |
389 | } |
390 | ||
391 | ||
392 | void mlx4_en_poll_tx_cq(unsigned long data) | |
393 | { | |
394 | struct mlx4_en_cq *cq = (struct mlx4_en_cq *) data; | |
395 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
396 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[cq->ring]; | |
397 | u32 inflight; | |
398 | ||
399 | INC_PERF_COUNTER(priv->pstats.tx_poll); | |
400 | ||
465440d2 | 401 | if (!spin_trylock_irq(&ring->comp_lock)) { |
48374ddc YP |
402 | mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); |
403 | return; | |
404 | } | |
c27a02cd YP |
405 | mlx4_en_process_tx_cq(cq->dev, cq); |
406 | inflight = (u32) (ring->prod - ring->cons - ring->last_nr_txbb); | |
407 | ||
408 | /* If there are still packets in flight and the timer has not already | |
409 | * been scheduled by the Tx routine then schedule it here to guarantee | |
410 | * completion processing of these packets */ | |
411 | if (inflight && priv->port_up) | |
412 | mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); | |
413 | ||
465440d2 | 414 | spin_unlock_irq(&ring->comp_lock); |
c27a02cd YP |
415 | } |
416 | ||
417 | static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, | |
418 | struct mlx4_en_tx_ring *ring, | |
419 | u32 index, | |
420 | unsigned int desc_size) | |
421 | { | |
422 | u32 copy = (ring->size - index) * TXBB_SIZE; | |
423 | int i; | |
424 | ||
425 | for (i = desc_size - copy - 4; i >= 0; i -= 4) { | |
426 | if ((i & (TXBB_SIZE - 1)) == 0) | |
427 | wmb(); | |
428 | ||
429 | *((u32 *) (ring->buf + i)) = | |
430 | *((u32 *) (ring->bounce_buf + copy + i)); | |
431 | } | |
432 | ||
433 | for (i = copy - 4; i >= 4 ; i -= 4) { | |
434 | if ((i & (TXBB_SIZE - 1)) == 0) | |
435 | wmb(); | |
436 | ||
437 | *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = | |
438 | *((u32 *) (ring->bounce_buf + i)); | |
439 | } | |
440 | ||
441 | /* Return real descriptor location */ | |
442 | return ring->buf + index * TXBB_SIZE; | |
443 | } | |
444 | ||
445 | static inline void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind) | |
446 | { | |
447 | struct mlx4_en_cq *cq = &priv->tx_cq[tx_ind]; | |
448 | struct mlx4_en_tx_ring *ring = &priv->tx_ring[tx_ind]; | |
4871953c | 449 | unsigned long flags; |
c27a02cd YP |
450 | |
451 | /* If we don't have a pending timer, set one up to catch our recent | |
452 | post in case the interface becomes idle */ | |
453 | if (!timer_pending(&cq->timer)) | |
454 | mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT); | |
455 | ||
456 | /* Poll the CQ every mlx4_en_TX_MODER_POLL packets */ | |
457 | if ((++ring->poll_cnt & (MLX4_EN_TX_POLL_MODER - 1)) == 0) | |
4871953c | 458 | if (spin_trylock_irqsave(&ring->comp_lock, flags)) { |
48374ddc | 459 | mlx4_en_process_tx_cq(priv->dev, cq); |
4871953c | 460 | spin_unlock_irqrestore(&ring->comp_lock, flags); |
48374ddc | 461 | } |
c27a02cd YP |
462 | } |
463 | ||
464 | static void *get_frag_ptr(struct sk_buff *skb) | |
465 | { | |
466 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
467 | struct page *page = frag->page; | |
468 | void *ptr; | |
469 | ||
470 | ptr = page_address(page); | |
471 | if (unlikely(!ptr)) | |
472 | return NULL; | |
473 | ||
474 | return ptr + frag->page_offset; | |
475 | } | |
476 | ||
477 | static int is_inline(struct sk_buff *skb, void **pfrag) | |
478 | { | |
479 | void *ptr; | |
480 | ||
481 | if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) { | |
482 | if (skb_shinfo(skb)->nr_frags == 1) { | |
483 | ptr = get_frag_ptr(skb); | |
484 | if (unlikely(!ptr)) | |
485 | return 0; | |
486 | ||
487 | if (pfrag) | |
488 | *pfrag = ptr; | |
489 | ||
490 | return 1; | |
491 | } else if (unlikely(skb_shinfo(skb)->nr_frags)) | |
492 | return 0; | |
493 | else | |
494 | return 1; | |
495 | } | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
500 | static int inline_size(struct sk_buff *skb) | |
501 | { | |
502 | if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) | |
503 | <= MLX4_INLINE_ALIGN) | |
504 | return ALIGN(skb->len + CTRL_SIZE + | |
505 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
506 | else | |
507 | return ALIGN(skb->len + CTRL_SIZE + 2 * | |
508 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
509 | } | |
510 | ||
511 | static int get_real_size(struct sk_buff *skb, struct net_device *dev, | |
512 | int *lso_header_size) | |
513 | { | |
514 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
515 | int real_size; |
516 | ||
517 | if (skb_is_gso(skb)) { | |
518 | *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
519 | real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE + | |
520 | ALIGN(*lso_header_size + 4, DS_SIZE); | |
521 | if (unlikely(*lso_header_size != skb_headlen(skb))) { | |
522 | /* We add a segment for the skb linear buffer only if | |
523 | * it contains data */ | |
524 | if (*lso_header_size < skb_headlen(skb)) | |
525 | real_size += DS_SIZE; | |
526 | else { | |
527 | if (netif_msg_tx_err(priv)) | |
453a6082 | 528 | en_warn(priv, "Non-linear headers\n"); |
c27a02cd YP |
529 | return 0; |
530 | } | |
531 | } | |
c27a02cd YP |
532 | } else { |
533 | *lso_header_size = 0; | |
534 | if (!is_inline(skb, NULL)) | |
535 | real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE; | |
536 | else | |
537 | real_size = inline_size(skb); | |
538 | } | |
539 | ||
540 | return real_size; | |
541 | } | |
542 | ||
543 | static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb, | |
544 | int real_size, u16 *vlan_tag, int tx_ind, void *fragptr) | |
545 | { | |
546 | struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; | |
547 | int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; | |
548 | ||
549 | if (skb->len <= spc) { | |
550 | inl->byte_count = cpu_to_be32(1 << 31 | skb->len); | |
551 | skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); | |
552 | if (skb_shinfo(skb)->nr_frags) | |
553 | memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr, | |
554 | skb_shinfo(skb)->frags[0].size); | |
555 | ||
556 | } else { | |
557 | inl->byte_count = cpu_to_be32(1 << 31 | spc); | |
558 | if (skb_headlen(skb) <= spc) { | |
559 | skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); | |
560 | if (skb_headlen(skb) < spc) { | |
561 | memcpy(((void *)(inl + 1)) + skb_headlen(skb), | |
562 | fragptr, spc - skb_headlen(skb)); | |
563 | fragptr += spc - skb_headlen(skb); | |
564 | } | |
565 | inl = (void *) (inl + 1) + spc; | |
566 | memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); | |
567 | } else { | |
568 | skb_copy_from_linear_data(skb, inl + 1, spc); | |
569 | inl = (void *) (inl + 1) + spc; | |
570 | skb_copy_from_linear_data_offset(skb, spc, inl + 1, | |
571 | skb_headlen(skb) - spc); | |
572 | if (skb_shinfo(skb)->nr_frags) | |
573 | memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc, | |
574 | fragptr, skb_shinfo(skb)->frags[0].size); | |
575 | } | |
576 | ||
577 | wmb(); | |
578 | inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); | |
579 | } | |
580 | tx_desc->ctrl.vlan_tag = cpu_to_be16(*vlan_tag); | |
581 | tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * !!(*vlan_tag); | |
582 | tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; | |
583 | } | |
584 | ||
f813cad8 | 585 | u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb) |
c27a02cd | 586 | { |
f813cad8 YP |
587 | struct mlx4_en_priv *priv = netdev_priv(dev); |
588 | u16 vlan_tag = 0; | |
c27a02cd | 589 | |
f813cad8 YP |
590 | /* If we support per priority flow control and the packet contains |
591 | * a vlan tag, send the packet to the TX ring assigned to that priority | |
592 | */ | |
eab6d18d | 593 | if (priv->prof->rx_ppp && vlan_tx_tag_present(skb)) { |
f813cad8 YP |
594 | vlan_tag = vlan_tx_tag_get(skb); |
595 | return MLX4_EN_NUM_TX_RINGS + (vlan_tag >> 13); | |
c27a02cd | 596 | } |
f813cad8 YP |
597 | |
598 | return skb_tx_hash(dev, skb); | |
c27a02cd YP |
599 | } |
600 | ||
87a5c389 YP |
601 | static void mlx4_bf_copy(unsigned long *dst, unsigned long *src, unsigned bytecnt) |
602 | { | |
603 | __iowrite64_copy(dst, src, bytecnt / 8); | |
604 | } | |
605 | ||
61357325 | 606 | netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) |
c27a02cd YP |
607 | { |
608 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
609 | struct mlx4_en_dev *mdev = priv->mdev; | |
610 | struct mlx4_en_tx_ring *ring; | |
611 | struct mlx4_en_cq *cq; | |
612 | struct mlx4_en_tx_desc *tx_desc; | |
613 | struct mlx4_wqe_data_seg *data; | |
614 | struct skb_frag_struct *frag; | |
615 | struct mlx4_en_tx_info *tx_info; | |
e7c1c2c4 YP |
616 | struct ethhdr *ethh; |
617 | u64 mac; | |
618 | u32 mac_l, mac_h; | |
c27a02cd YP |
619 | int tx_ind = 0; |
620 | int nr_txbb; | |
621 | int desc_size; | |
622 | int real_size; | |
623 | dma_addr_t dma; | |
87a5c389 | 624 | u32 index, bf_index; |
c27a02cd | 625 | __be32 op_own; |
f813cad8 | 626 | u16 vlan_tag = 0; |
c27a02cd YP |
627 | int i; |
628 | int lso_header_size; | |
629 | void *fragptr; | |
87a5c389 | 630 | bool bounce = false; |
c27a02cd | 631 | |
3005ad40 YP |
632 | if (!priv->port_up) |
633 | goto tx_drop; | |
634 | ||
c27a02cd YP |
635 | real_size = get_real_size(skb, dev, &lso_header_size); |
636 | if (unlikely(!real_size)) | |
7e230913 | 637 | goto tx_drop; |
c27a02cd | 638 | |
25985edc | 639 | /* Align descriptor to TXBB size */ |
c27a02cd YP |
640 | desc_size = ALIGN(real_size, TXBB_SIZE); |
641 | nr_txbb = desc_size / TXBB_SIZE; | |
642 | if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { | |
643 | if (netif_msg_tx_err(priv)) | |
453a6082 | 644 | en_warn(priv, "Oversized header or SG list\n"); |
7e230913 | 645 | goto tx_drop; |
c27a02cd YP |
646 | } |
647 | ||
f813cad8 | 648 | tx_ind = skb->queue_mapping; |
c27a02cd | 649 | ring = &priv->tx_ring[tx_ind]; |
eab6d18d | 650 | if (vlan_tx_tag_present(skb)) |
f813cad8 | 651 | vlan_tag = vlan_tx_tag_get(skb); |
c27a02cd YP |
652 | |
653 | /* Check available TXBBs And 2K spare for prefetch */ | |
654 | if (unlikely(((int)(ring->prod - ring->cons)) > | |
655 | ring->size - HEADROOM - MAX_DESC_TXBBS)) { | |
f813cad8 YP |
656 | /* every full Tx ring stops queue */ |
657 | netif_tx_stop_queue(netdev_get_tx_queue(dev, tx_ind)); | |
c27a02cd YP |
658 | ring->blocked = 1; |
659 | priv->port_stats.queue_stopped++; | |
660 | ||
661 | /* Use interrupts to find out when queue opened */ | |
662 | cq = &priv->tx_cq[tx_ind]; | |
663 | mlx4_en_arm_cq(priv, cq); | |
664 | return NETDEV_TX_BUSY; | |
665 | } | |
666 | ||
c27a02cd YP |
667 | /* Track current inflight packets for performance analysis */ |
668 | AVG_PERF_COUNTER(priv->pstats.inflight_avg, | |
669 | (u32) (ring->prod - ring->cons - 1)); | |
670 | ||
671 | /* Packet is good - grab an index and transmit it */ | |
672 | index = ring->prod & ring->size_mask; | |
87a5c389 | 673 | bf_index = ring->prod; |
c27a02cd YP |
674 | |
675 | /* See if we have enough space for whole descriptor TXBB for setting | |
676 | * SW ownership on next descriptor; if not, use a bounce buffer. */ | |
677 | if (likely(index + nr_txbb <= ring->size)) | |
678 | tx_desc = ring->buf + index * TXBB_SIZE; | |
87a5c389 | 679 | else { |
c27a02cd | 680 | tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; |
87a5c389 YP |
681 | bounce = true; |
682 | } | |
c27a02cd YP |
683 | |
684 | /* Save skb in tx_info ring */ | |
685 | tx_info = &ring->tx_info[index]; | |
686 | tx_info->skb = skb; | |
687 | tx_info->nr_txbb = nr_txbb; | |
688 | ||
689 | /* Prepare ctrl segement apart opcode+ownership, which depends on | |
690 | * whether LSO is used */ | |
691 | tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); | |
692 | tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * !!vlan_tag; | |
693 | tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; | |
694 | tx_desc->ctrl.srcrb_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE | | |
695 | MLX4_WQE_CTRL_SOLICITED); | |
696 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { | |
697 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | | |
698 | MLX4_WQE_CTRL_TCP_UDP_CSUM); | |
699 | priv->port_stats.tx_chksum_offload++; | |
700 | } | |
701 | ||
e7c1c2c4 YP |
702 | if (unlikely(priv->validate_loopback)) { |
703 | /* Copy dst mac address to wqe */ | |
704 | skb_reset_mac_header(skb); | |
705 | ethh = eth_hdr(skb); | |
706 | if (ethh && ethh->h_dest) { | |
707 | mac = mlx4_en_mac_to_u64(ethh->h_dest); | |
708 | mac_h = (u32) ((mac & 0xffff00000000ULL) >> 16); | |
709 | mac_l = (u32) (mac & 0xffffffff); | |
710 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(mac_h); | |
711 | tx_desc->ctrl.imm = cpu_to_be32(mac_l); | |
712 | } | |
713 | } | |
714 | ||
c27a02cd YP |
715 | /* Handle LSO (TSO) packets */ |
716 | if (lso_header_size) { | |
717 | /* Mark opcode as LSO */ | |
718 | op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | | |
719 | ((ring->prod & ring->size) ? | |
720 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
721 | ||
722 | /* Fill in the LSO prefix */ | |
723 | tx_desc->lso.mss_hdr_size = cpu_to_be32( | |
724 | skb_shinfo(skb)->gso_size << 16 | lso_header_size); | |
725 | ||
726 | /* Copy headers; | |
727 | * note that we already verified that it is linear */ | |
728 | memcpy(tx_desc->lso.header, skb->data, lso_header_size); | |
729 | data = ((void *) &tx_desc->lso + | |
730 | ALIGN(lso_header_size + 4, DS_SIZE)); | |
731 | ||
732 | priv->port_stats.tso_packets++; | |
733 | i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) + | |
734 | !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size); | |
735 | ring->bytes += skb->len + (i - 1) * lso_header_size; | |
736 | ring->packets += i; | |
737 | } else { | |
738 | /* Normal (Non LSO) packet */ | |
739 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
740 | ((ring->prod & ring->size) ? | |
741 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
742 | data = &tx_desc->data; | |
743 | ring->bytes += max(skb->len, (unsigned int) ETH_ZLEN); | |
744 | ring->packets++; | |
745 | ||
746 | } | |
747 | AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); | |
748 | ||
749 | ||
750 | /* valid only for none inline segments */ | |
751 | tx_info->data_offset = (void *) data - (void *) tx_desc; | |
752 | ||
753 | tx_info->linear = (lso_header_size < skb_headlen(skb) && !is_inline(skb, NULL)) ? 1 : 0; | |
754 | data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1; | |
755 | ||
756 | if (!is_inline(skb, &fragptr)) { | |
757 | /* Map fragments */ | |
758 | for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) { | |
759 | frag = &skb_shinfo(skb)->frags[i]; | |
760 | dma = pci_map_page(mdev->dev->pdev, frag->page, frag->page_offset, | |
761 | frag->size, PCI_DMA_TODEVICE); | |
762 | data->addr = cpu_to_be64(dma); | |
763 | data->lkey = cpu_to_be32(mdev->mr.key); | |
764 | wmb(); | |
765 | data->byte_count = cpu_to_be32(frag->size); | |
766 | --data; | |
767 | } | |
768 | ||
769 | /* Map linear part */ | |
770 | if (tx_info->linear) { | |
771 | dma = pci_map_single(mdev->dev->pdev, skb->data + lso_header_size, | |
772 | skb_headlen(skb) - lso_header_size, PCI_DMA_TODEVICE); | |
773 | data->addr = cpu_to_be64(dma); | |
774 | data->lkey = cpu_to_be32(mdev->mr.key); | |
775 | wmb(); | |
776 | data->byte_count = cpu_to_be32(skb_headlen(skb) - lso_header_size); | |
777 | } | |
41efea5a YP |
778 | tx_info->inl = 0; |
779 | } else { | |
c27a02cd | 780 | build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr); |
41efea5a YP |
781 | tx_info->inl = 1; |
782 | } | |
c27a02cd YP |
783 | |
784 | ring->prod += nr_txbb; | |
785 | ||
786 | /* If we used a bounce buffer then copy descriptor back into place */ | |
87a5c389 | 787 | if (bounce) |
c27a02cd YP |
788 | tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); |
789 | ||
790 | /* Run destructor before passing skb to HW */ | |
791 | if (likely(!skb_shared(skb))) | |
792 | skb_orphan(skb); | |
793 | ||
87a5c389 YP |
794 | if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && !vlan_tag) { |
795 | *(u32 *) (&tx_desc->ctrl.vlan_tag) |= ring->doorbell_qpn; | |
796 | op_own |= htonl((bf_index & 0xffff) << 8); | |
797 | /* Ensure new descirptor hits memory | |
798 | * before setting ownership of this descriptor to HW */ | |
799 | wmb(); | |
800 | tx_desc->ctrl.owner_opcode = op_own; | |
c27a02cd | 801 | |
87a5c389 YP |
802 | wmb(); |
803 | ||
804 | mlx4_bf_copy(ring->bf.reg + ring->bf.offset, (unsigned long *) &tx_desc->ctrl, | |
805 | desc_size); | |
806 | ||
807 | wmb(); | |
808 | ||
809 | ring->bf.offset ^= ring->bf.buf_size; | |
810 | } else { | |
811 | /* Ensure new descirptor hits memory | |
812 | * before setting ownership of this descriptor to HW */ | |
813 | wmb(); | |
814 | tx_desc->ctrl.owner_opcode = op_own; | |
815 | wmb(); | |
816 | writel(ring->doorbell_qpn, ring->bf.uar->map + MLX4_SEND_DOORBELL); | |
817 | } | |
c27a02cd YP |
818 | |
819 | /* Poll CQ here */ | |
820 | mlx4_en_xmit_poll(priv, tx_ind); | |
821 | ||
ec634fe3 | 822 | return NETDEV_TX_OK; |
7e230913 YP |
823 | |
824 | tx_drop: | |
825 | dev_kfree_skb_any(skb); | |
826 | priv->stats.tx_dropped++; | |
827 | return NETDEV_TX_OK; | |
c27a02cd YP |
828 | } |
829 |