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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
b4617240 | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
37 | #include <linux/ipv6.h> | |
38 | #include <net/checksum.h> | |
39 | #include <net/ip6_checksum.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/if_vlan.h> | |
42 | ||
43 | #include "ixgbe.h" | |
44 | #include "ixgbe_common.h" | |
45 | ||
46 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 47 | static const char ixgbe_driver_string[] = |
b4617240 | 48 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 49 | |
51ac6445 | 50 | #define DRV_VERSION "1.3.30-k2" |
9c8eb720 | 51 | const char ixgbe_driver_version[] = DRV_VERSION; |
b4617240 | 52 | static char ixgbe_copyright[] = "Copyright (c) 1999-2007 Intel Corporation."; |
9a799d71 AK |
53 | |
54 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 55 | [board_82598] = &ixgbe_82598_info, |
9a799d71 AK |
56 | }; |
57 | ||
58 | /* ixgbe_pci_tbl - PCI Device ID Table | |
59 | * | |
60 | * Wildcard entries (PCI_ANY_ID) should come last | |
61 | * Last entry must be all 0s | |
62 | * | |
63 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
64 | * Class, Class Mask, private data (not used) } | |
65 | */ | |
66 | static struct pci_device_id ixgbe_pci_tbl[] = { | |
67 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), | |
3957d63d | 68 | board_82598 }, |
9a799d71 | 69 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 70 | board_82598 }, |
9a799d71 | 71 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 72 | board_82598 }, |
8d792cd9 JB |
73 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
74 | board_82598 }, | |
b95f5fcb JB |
75 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
76 | board_82598 }, | |
9a799d71 AK |
77 | |
78 | /* required last entry */ | |
79 | {0, } | |
80 | }; | |
81 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
82 | ||
5dd2d332 | 83 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 84 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
b4617240 | 85 | void *p); |
bd0362dd JC |
86 | static struct notifier_block dca_notifier = { |
87 | .notifier_call = ixgbe_notify_dca, | |
88 | .next = NULL, | |
89 | .priority = 0 | |
90 | }; | |
91 | #endif | |
92 | ||
9a799d71 AK |
93 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
94 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
95 | MODULE_LICENSE("GPL"); | |
96 | MODULE_VERSION(DRV_VERSION); | |
97 | ||
98 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
99 | ||
5eba3699 AV |
100 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
101 | { | |
102 | u32 ctrl_ext; | |
103 | ||
104 | /* Let firmware take over control of h/w */ | |
105 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
106 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 107 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
108 | } |
109 | ||
110 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
111 | { | |
112 | u32 ctrl_ext; | |
113 | ||
114 | /* Let firmware know the driver has taken over */ | |
115 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
116 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 117 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 118 | } |
9a799d71 | 119 | |
9a799d71 | 120 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry, |
b4617240 | 121 | u8 msix_vector) |
9a799d71 AK |
122 | { |
123 | u32 ivar, index; | |
124 | ||
125 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
126 | index = (int_alloc_entry >> 2) & 0x1F; | |
127 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index)); | |
128 | ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3))); | |
129 | ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3))); | |
130 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar); | |
131 | } | |
132 | ||
133 | static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, | |
b4617240 PW |
134 | struct ixgbe_tx_buffer |
135 | *tx_buffer_info) | |
9a799d71 AK |
136 | { |
137 | if (tx_buffer_info->dma) { | |
e01c31a5 | 138 | pci_unmap_page(adapter->pdev, tx_buffer_info->dma, |
b4617240 | 139 | tx_buffer_info->length, PCI_DMA_TODEVICE); |
9a799d71 AK |
140 | tx_buffer_info->dma = 0; |
141 | } | |
142 | if (tx_buffer_info->skb) { | |
143 | dev_kfree_skb_any(tx_buffer_info->skb); | |
144 | tx_buffer_info->skb = NULL; | |
145 | } | |
146 | /* tx_buffer_info must be completely set up in the transmit path */ | |
147 | } | |
148 | ||
149 | static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter, | |
b4617240 PW |
150 | struct ixgbe_ring *tx_ring, |
151 | unsigned int eop) | |
9a799d71 | 152 | { |
e01c31a5 JB |
153 | struct ixgbe_hw *hw = &adapter->hw; |
154 | u32 head, tail; | |
155 | ||
9a799d71 | 156 | /* Detect a transmit hang in hardware, this serializes the |
e01c31a5 JB |
157 | * check with the clearing of time_stamp and movement of eop */ |
158 | head = IXGBE_READ_REG(hw, tx_ring->head); | |
159 | tail = IXGBE_READ_REG(hw, tx_ring->tail); | |
9a799d71 | 160 | adapter->detect_tx_hung = false; |
e01c31a5 JB |
161 | if ((head != tail) && |
162 | tx_ring->tx_buffer_info[eop].time_stamp && | |
9a799d71 AK |
163 | time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) && |
164 | !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) { | |
165 | /* detected Tx unit hang */ | |
e01c31a5 JB |
166 | union ixgbe_adv_tx_desc *tx_desc; |
167 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
9a799d71 | 168 | DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" |
e01c31a5 JB |
169 | " Tx Queue <%d>\n" |
170 | " TDH, TDT <%x>, <%x>\n" | |
9a799d71 AK |
171 | " next_to_use <%x>\n" |
172 | " next_to_clean <%x>\n" | |
173 | "tx_buffer_info[next_to_clean]\n" | |
174 | " time_stamp <%lx>\n" | |
e01c31a5 JB |
175 | " jiffies <%lx>\n", |
176 | tx_ring->queue_index, | |
177 | head, tail, | |
178 | tx_ring->next_to_use, eop, | |
179 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
9a799d71 AK |
180 | return true; |
181 | } | |
182 | ||
183 | return false; | |
184 | } | |
185 | ||
b4617240 PW |
186 | #define IXGBE_MAX_TXD_PWR 14 |
187 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
188 | |
189 | /* Tx Descriptors needed, worst case */ | |
190 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
191 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
192 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 193 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 194 | |
e01c31a5 JB |
195 | #define GET_TX_HEAD_FROM_RING(ring) (\ |
196 | *(volatile u32 *) \ | |
197 | ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count)) | |
198 | static void ixgbe_tx_timeout(struct net_device *netdev); | |
199 | ||
9a799d71 AK |
200 | /** |
201 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
202 | * @adapter: board private structure | |
e01c31a5 | 203 | * @tx_ring: tx ring to clean |
9a799d71 AK |
204 | **/ |
205 | static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter, | |
e01c31a5 | 206 | struct ixgbe_ring *tx_ring) |
9a799d71 | 207 | { |
e01c31a5 | 208 | union ixgbe_adv_tx_desc *tx_desc; |
9a799d71 | 209 | struct ixgbe_tx_buffer *tx_buffer_info; |
e01c31a5 JB |
210 | struct net_device *netdev = adapter->netdev; |
211 | struct sk_buff *skb; | |
212 | unsigned int i; | |
213 | u32 head, oldhead; | |
214 | unsigned int count = 0; | |
215 | unsigned int total_bytes = 0, total_packets = 0; | |
9a799d71 | 216 | |
e01c31a5 JB |
217 | rmb(); |
218 | head = GET_TX_HEAD_FROM_RING(tx_ring); | |
219 | head = le32_to_cpu(head); | |
9a799d71 | 220 | i = tx_ring->next_to_clean; |
e01c31a5 JB |
221 | while (1) { |
222 | while (i != head) { | |
9a799d71 AK |
223 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); |
224 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
e01c31a5 | 225 | skb = tx_buffer_info->skb; |
9a799d71 | 226 | |
e01c31a5 | 227 | if (skb) { |
e092be60 | 228 | unsigned int segs, bytecount; |
e01c31a5 JB |
229 | |
230 | /* gso_segs is currently only valid for tcp */ | |
e092be60 AV |
231 | segs = skb_shinfo(skb)->gso_segs ?: 1; |
232 | /* multiply data chunks by size of headers */ | |
233 | bytecount = ((segs - 1) * skb_headlen(skb)) + | |
e01c31a5 JB |
234 | skb->len; |
235 | total_packets += segs; | |
236 | total_bytes += bytecount; | |
e092be60 | 237 | } |
e01c31a5 | 238 | |
9a799d71 | 239 | ixgbe_unmap_and_free_tx_resource(adapter, |
e01c31a5 | 240 | tx_buffer_info); |
9a799d71 AK |
241 | |
242 | i++; | |
243 | if (i == tx_ring->count) | |
244 | i = 0; | |
9a799d71 | 245 | |
e01c31a5 JB |
246 | count++; |
247 | if (count == tx_ring->count) | |
248 | goto done_cleaning; | |
249 | } | |
250 | oldhead = head; | |
251 | rmb(); | |
252 | head = GET_TX_HEAD_FROM_RING(tx_ring); | |
253 | head = le32_to_cpu(head); | |
254 | if (head == oldhead) | |
255 | goto done_cleaning; | |
256 | } /* while (1) */ | |
257 | ||
258 | done_cleaning: | |
9a799d71 AK |
259 | tx_ring->next_to_clean = i; |
260 | ||
e092be60 | 261 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
e01c31a5 JB |
262 | if (unlikely(count && netif_carrier_ok(netdev) && |
263 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
e092be60 AV |
264 | /* Make sure that anybody stopping the queue after this |
265 | * sees the new next_to_clean. | |
266 | */ | |
267 | smp_mb(); | |
30eba97a AV |
268 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
269 | !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
270 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
e01c31a5 | 271 | ++adapter->restart_queue; |
30eba97a | 272 | } |
e092be60 | 273 | } |
9a799d71 | 274 | |
e01c31a5 JB |
275 | if (adapter->detect_tx_hung) { |
276 | if (ixgbe_check_tx_hang(adapter, tx_ring, i)) { | |
277 | /* schedule immediate reset if we believe we hung */ | |
278 | DPRINTK(PROBE, INFO, | |
279 | "tx hang %d detected, resetting adapter\n", | |
280 | adapter->tx_timeout_count + 1); | |
281 | ixgbe_tx_timeout(adapter->netdev); | |
282 | } | |
283 | } | |
9a799d71 | 284 | |
e01c31a5 JB |
285 | /* re-arm the interrupt */ |
286 | if ((total_packets >= tx_ring->work_limit) || | |
287 | (count == tx_ring->count)) | |
288 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx); | |
9a799d71 | 289 | |
e01c31a5 JB |
290 | tx_ring->total_bytes += total_bytes; |
291 | tx_ring->total_packets += total_packets; | |
292 | tx_ring->stats.bytes += total_bytes; | |
293 | tx_ring->stats.packets += total_packets; | |
294 | adapter->net_stats.tx_bytes += total_bytes; | |
295 | adapter->net_stats.tx_packets += total_packets; | |
296 | return (total_packets ? true : false); | |
9a799d71 AK |
297 | } |
298 | ||
5dd2d332 | 299 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 300 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
b4617240 | 301 | struct ixgbe_ring *rx_ring) |
bd0362dd JC |
302 | { |
303 | u32 rxctrl; | |
304 | int cpu = get_cpu(); | |
3a581073 | 305 | int q = rx_ring - adapter->rx_ring; |
bd0362dd | 306 | |
3a581073 | 307 | if (rx_ring->cpu != cpu) { |
bd0362dd JC |
308 | rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); |
309 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
96b0e0f6 | 310 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); |
bd0362dd JC |
311 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
312 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
313 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); | |
3a581073 | 314 | rx_ring->cpu = cpu; |
bd0362dd JC |
315 | } |
316 | put_cpu(); | |
317 | } | |
318 | ||
319 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
b4617240 | 320 | struct ixgbe_ring *tx_ring) |
bd0362dd JC |
321 | { |
322 | u32 txctrl; | |
323 | int cpu = get_cpu(); | |
3a581073 | 324 | int q = tx_ring - adapter->tx_ring; |
bd0362dd | 325 | |
3a581073 | 326 | if (tx_ring->cpu != cpu) { |
bd0362dd JC |
327 | txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q)); |
328 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; | |
96b0e0f6 | 329 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); |
bd0362dd JC |
330 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
331 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl); | |
3a581073 | 332 | tx_ring->cpu = cpu; |
bd0362dd JC |
333 | } |
334 | put_cpu(); | |
335 | } | |
336 | ||
337 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
338 | { | |
339 | int i; | |
340 | ||
341 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
342 | return; | |
343 | ||
344 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
345 | adapter->tx_ring[i].cpu = -1; | |
346 | ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]); | |
347 | } | |
348 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
349 | adapter->rx_ring[i].cpu = -1; | |
350 | ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]); | |
351 | } | |
352 | } | |
353 | ||
354 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
355 | { | |
356 | struct net_device *netdev = dev_get_drvdata(dev); | |
357 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
358 | unsigned long event = *(unsigned long *)data; | |
359 | ||
360 | switch (event) { | |
361 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
362 | /* if we're already enabled, don't do it again */ |
363 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
364 | break; | |
bd0362dd JC |
365 | /* Always use CB2 mode, difference is masked |
366 | * in the CB driver. */ | |
367 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
652f093f | 368 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 369 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
370 | ixgbe_setup_dca(adapter); |
371 | break; | |
372 | } | |
373 | /* Fall Through since DCA is disabled. */ | |
374 | case DCA_PROVIDER_REMOVE: | |
375 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
376 | dca_remove_requester(dev); | |
377 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
378 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
379 | } | |
380 | break; | |
381 | } | |
382 | ||
652f093f | 383 | return 0; |
bd0362dd JC |
384 | } |
385 | ||
5dd2d332 | 386 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
387 | /** |
388 | * ixgbe_receive_skb - Send a completed packet up the stack | |
389 | * @adapter: board private structure | |
390 | * @skb: packet to send up | |
177db6ff MC |
391 | * @status: hardware indication of status of receive |
392 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
393 | * @rx_desc: rx descriptor | |
9a799d71 AK |
394 | **/ |
395 | static void ixgbe_receive_skb(struct ixgbe_adapter *adapter, | |
b4617240 PW |
396 | struct sk_buff *skb, u8 status, |
397 | struct ixgbe_ring *ring, | |
177db6ff | 398 | union ixgbe_adv_rx_desc *rx_desc) |
9a799d71 | 399 | { |
177db6ff MC |
400 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
401 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 402 | |
177db6ff MC |
403 | if (adapter->netdev->features & NETIF_F_LRO && |
404 | skb->ip_summed == CHECKSUM_UNNECESSARY) { | |
9a799d71 | 405 | if (adapter->vlgrp && is_vlan) |
177db6ff MC |
406 | lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb, |
407 | adapter->vlgrp, tag, | |
408 | rx_desc); | |
9a799d71 | 409 | else |
177db6ff MC |
410 | lro_receive_skb(&ring->lro_mgr, skb, rx_desc); |
411 | ring->lro_used = true; | |
412 | } else { | |
413 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { | |
414 | if (adapter->vlgrp && is_vlan) | |
415 | vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag); | |
416 | else | |
417 | netif_receive_skb(skb); | |
418 | } else { | |
419 | if (adapter->vlgrp && is_vlan) | |
420 | vlan_hwaccel_rx(skb, adapter->vlgrp, tag); | |
421 | else | |
422 | netif_rx(skb); | |
423 | } | |
9a799d71 AK |
424 | } |
425 | } | |
426 | ||
e59bd25d AV |
427 | /** |
428 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
429 | * @adapter: address of board private structure | |
430 | * @status_err: hardware indication of status of receive | |
431 | * @skb: skb currently being received and modified | |
432 | **/ | |
9a799d71 | 433 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
712744be | 434 | u32 status_err, struct sk_buff *skb) |
9a799d71 AK |
435 | { |
436 | skb->ip_summed = CHECKSUM_NONE; | |
437 | ||
712744be JB |
438 | /* Rx csum disabled */ |
439 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 440 | return; |
e59bd25d AV |
441 | |
442 | /* if IP and error */ | |
443 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
444 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
445 | adapter->hw_csum_rx_error++; |
446 | return; | |
447 | } | |
e59bd25d AV |
448 | |
449 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
450 | return; | |
451 | ||
452 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
453 | adapter->hw_csum_rx_error++; | |
454 | return; | |
455 | } | |
456 | ||
9a799d71 | 457 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 458 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
459 | adapter->hw_csum_rx_good++; |
460 | } | |
461 | ||
462 | /** | |
463 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
464 | * @adapter: address of board private structure | |
465 | **/ | |
466 | static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter, | |
7c6e0a43 JB |
467 | struct ixgbe_ring *rx_ring, |
468 | int cleaned_count) | |
9a799d71 | 469 | { |
9a799d71 AK |
470 | struct pci_dev *pdev = adapter->pdev; |
471 | union ixgbe_adv_rx_desc *rx_desc; | |
3a581073 | 472 | struct ixgbe_rx_buffer *bi; |
9a799d71 | 473 | unsigned int i; |
7c6e0a43 | 474 | unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN; |
9a799d71 AK |
475 | |
476 | i = rx_ring->next_to_use; | |
3a581073 | 477 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
478 | |
479 | while (cleaned_count--) { | |
480 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
481 | ||
762f4c57 | 482 | if (!bi->page_dma && |
3a581073 | 483 | (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) { |
3a581073 | 484 | if (!bi->page) { |
762f4c57 JB |
485 | bi->page = alloc_page(GFP_ATOMIC); |
486 | if (!bi->page) { | |
487 | adapter->alloc_rx_page_failed++; | |
488 | goto no_buffers; | |
489 | } | |
490 | bi->page_offset = 0; | |
491 | } else { | |
492 | /* use a half page if we're re-using */ | |
493 | bi->page_offset ^= (PAGE_SIZE / 2); | |
9a799d71 | 494 | } |
762f4c57 JB |
495 | |
496 | bi->page_dma = pci_map_page(pdev, bi->page, | |
497 | bi->page_offset, | |
498 | (PAGE_SIZE / 2), | |
499 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
500 | } |
501 | ||
3a581073 | 502 | if (!bi->skb) { |
74ce8dd2 JB |
503 | struct sk_buff *skb = netdev_alloc_skb(adapter->netdev, |
504 | bufsz); | |
9a799d71 AK |
505 | |
506 | if (!skb) { | |
507 | adapter->alloc_rx_buff_failed++; | |
508 | goto no_buffers; | |
509 | } | |
510 | ||
511 | /* | |
512 | * Make buffer alignment 2 beyond a 16 byte boundary | |
513 | * this will result in a 16 byte aligned IP header after | |
514 | * the 14 byte MAC header is removed | |
515 | */ | |
516 | skb_reserve(skb, NET_IP_ALIGN); | |
517 | ||
3a581073 JB |
518 | bi->skb = skb; |
519 | bi->dma = pci_map_single(pdev, skb->data, bufsz, | |
520 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
521 | } |
522 | /* Refresh the desc even if buffer_addrs didn't change because | |
523 | * each write-back erases this info. */ | |
524 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
3a581073 JB |
525 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
526 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 527 | } else { |
3a581073 | 528 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
9a799d71 AK |
529 | } |
530 | ||
531 | i++; | |
532 | if (i == rx_ring->count) | |
533 | i = 0; | |
3a581073 | 534 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 | 535 | } |
7c6e0a43 | 536 | |
9a799d71 AK |
537 | no_buffers: |
538 | if (rx_ring->next_to_use != i) { | |
539 | rx_ring->next_to_use = i; | |
540 | if (i-- == 0) | |
541 | i = (rx_ring->count - 1); | |
542 | ||
543 | /* | |
544 | * Force memory writes to complete before letting h/w | |
545 | * know there are new descriptors to fetch. (Only | |
546 | * applicable for weak-ordered memory model archs, | |
547 | * such as IA-64). | |
548 | */ | |
549 | wmb(); | |
550 | writel(i, adapter->hw.hw_addr + rx_ring->tail); | |
551 | } | |
552 | } | |
553 | ||
7c6e0a43 JB |
554 | static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc) |
555 | { | |
556 | return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
557 | } | |
558 | ||
559 | static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) | |
560 | { | |
561 | return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
562 | } | |
563 | ||
9a799d71 | 564 | static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter, |
b4617240 PW |
565 | struct ixgbe_ring *rx_ring, |
566 | int *work_done, int work_to_do) | |
9a799d71 | 567 | { |
9a799d71 AK |
568 | struct pci_dev *pdev = adapter->pdev; |
569 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
570 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
571 | struct sk_buff *skb; | |
572 | unsigned int i; | |
7c6e0a43 | 573 | u32 len, staterr; |
177db6ff MC |
574 | u16 hdr_info; |
575 | bool cleaned = false; | |
9a799d71 | 576 | int cleaned_count = 0; |
d2f4fbe2 | 577 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
9a799d71 AK |
578 | |
579 | i = rx_ring->next_to_clean; | |
9a799d71 AK |
580 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); |
581 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
582 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
9a799d71 AK |
583 | |
584 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 585 | u32 upper_len = 0; |
9a799d71 AK |
586 | if (*work_done >= work_to_do) |
587 | break; | |
588 | (*work_done)++; | |
589 | ||
590 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 JB |
591 | hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); |
592 | len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
762f4c57 | 593 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; |
9a799d71 AK |
594 | if (hdr_info & IXGBE_RXDADV_SPH) |
595 | adapter->rx_hdr_split++; | |
596 | if (len > IXGBE_RX_HDR_SIZE) | |
597 | len = IXGBE_RX_HDR_SIZE; | |
598 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
7c6e0a43 | 599 | } else { |
9a799d71 | 600 | len = le16_to_cpu(rx_desc->wb.upper.length); |
7c6e0a43 | 601 | } |
9a799d71 AK |
602 | |
603 | cleaned = true; | |
604 | skb = rx_buffer_info->skb; | |
605 | prefetch(skb->data - NET_IP_ALIGN); | |
606 | rx_buffer_info->skb = NULL; | |
607 | ||
608 | if (len && !skb_shinfo(skb)->nr_frags) { | |
609 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
b4617240 PW |
610 | rx_ring->rx_buf_len + NET_IP_ALIGN, |
611 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
612 | skb_put(skb, len); |
613 | } | |
614 | ||
615 | if (upper_len) { | |
616 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
762f4c57 | 617 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9a799d71 AK |
618 | rx_buffer_info->page_dma = 0; |
619 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
762f4c57 JB |
620 | rx_buffer_info->page, |
621 | rx_buffer_info->page_offset, | |
622 | upper_len); | |
623 | ||
624 | if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || | |
625 | (page_count(rx_buffer_info->page) != 1)) | |
626 | rx_buffer_info->page = NULL; | |
627 | else | |
628 | get_page(rx_buffer_info->page); | |
9a799d71 AK |
629 | |
630 | skb->len += upper_len; | |
631 | skb->data_len += upper_len; | |
632 | skb->truesize += upper_len; | |
633 | } | |
634 | ||
635 | i++; | |
636 | if (i == rx_ring->count) | |
637 | i = 0; | |
638 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
639 | ||
640 | next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
641 | prefetch(next_rxd); | |
642 | ||
643 | cleaned_count++; | |
644 | if (staterr & IXGBE_RXD_STAT_EOP) { | |
645 | rx_ring->stats.packets++; | |
646 | rx_ring->stats.bytes += skb->len; | |
647 | } else { | |
648 | rx_buffer_info->skb = next_buffer->skb; | |
649 | rx_buffer_info->dma = next_buffer->dma; | |
650 | next_buffer->skb = skb; | |
762f4c57 | 651 | next_buffer->dma = 0; |
9a799d71 AK |
652 | adapter->non_eop_descs++; |
653 | goto next_desc; | |
654 | } | |
655 | ||
656 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { | |
657 | dev_kfree_skb_irq(skb); | |
658 | goto next_desc; | |
659 | } | |
660 | ||
661 | ixgbe_rx_checksum(adapter, staterr, skb); | |
d2f4fbe2 AV |
662 | |
663 | /* probably a little skewed due to removing CRC */ | |
664 | total_rx_bytes += skb->len; | |
665 | total_rx_packets++; | |
666 | ||
74ce8dd2 | 667 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
177db6ff | 668 | ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc); |
74ce8dd2 | 669 | adapter->netdev->last_rx = jiffies; |
9a799d71 AK |
670 | |
671 | next_desc: | |
672 | rx_desc->wb.upper.status_error = 0; | |
673 | ||
674 | /* return some buffers to hardware, one at a time is too slow */ | |
675 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
676 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
677 | cleaned_count = 0; | |
678 | } | |
679 | ||
680 | /* use prefetched values */ | |
681 | rx_desc = next_rxd; | |
682 | rx_buffer_info = next_buffer; | |
683 | ||
684 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
177db6ff MC |
685 | } |
686 | ||
687 | if (rx_ring->lro_used) { | |
688 | lro_flush_all(&rx_ring->lro_mgr); | |
689 | rx_ring->lro_used = false; | |
9a799d71 AK |
690 | } |
691 | ||
692 | rx_ring->next_to_clean = i; | |
693 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
694 | ||
695 | if (cleaned_count) | |
696 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
697 | ||
f494e8fa AV |
698 | rx_ring->total_packets += total_rx_packets; |
699 | rx_ring->total_bytes += total_rx_bytes; | |
700 | adapter->net_stats.rx_bytes += total_rx_bytes; | |
701 | adapter->net_stats.rx_packets += total_rx_packets; | |
702 | ||
9a799d71 AK |
703 | return cleaned; |
704 | } | |
705 | ||
021230d4 | 706 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
707 | /** |
708 | * ixgbe_configure_msix - Configure MSI-X hardware | |
709 | * @adapter: board private structure | |
710 | * | |
711 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
712 | * interrupts. | |
713 | **/ | |
714 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
715 | { | |
021230d4 AV |
716 | struct ixgbe_q_vector *q_vector; |
717 | int i, j, q_vectors, v_idx, r_idx; | |
718 | u32 mask; | |
9a799d71 | 719 | |
021230d4 | 720 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 721 | |
021230d4 AV |
722 | /* Populate the IVAR table and set the ITR values to the |
723 | * corresponding register. | |
724 | */ | |
725 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
726 | q_vector = &adapter->q_vector[v_idx]; | |
727 | /* XXX for_each_bit(...) */ | |
728 | r_idx = find_first_bit(q_vector->rxr_idx, | |
b4617240 | 729 | adapter->num_rx_queues); |
021230d4 AV |
730 | |
731 | for (i = 0; i < q_vector->rxr_count; i++) { | |
732 | j = adapter->rx_ring[r_idx].reg_idx; | |
733 | ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx); | |
734 | r_idx = find_next_bit(q_vector->rxr_idx, | |
b4617240 PW |
735 | adapter->num_rx_queues, |
736 | r_idx + 1); | |
021230d4 AV |
737 | } |
738 | r_idx = find_first_bit(q_vector->txr_idx, | |
b4617240 | 739 | adapter->num_tx_queues); |
021230d4 AV |
740 | |
741 | for (i = 0; i < q_vector->txr_count; i++) { | |
742 | j = adapter->tx_ring[r_idx].reg_idx; | |
743 | ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx); | |
744 | r_idx = find_next_bit(q_vector->txr_idx, | |
b4617240 PW |
745 | adapter->num_tx_queues, |
746 | r_idx + 1); | |
021230d4 AV |
747 | } |
748 | ||
30efa5a3 | 749 | /* if this is a tx only vector halve the interrupt rate */ |
021230d4 | 750 | if (q_vector->txr_count && !q_vector->rxr_count) |
30efa5a3 | 751 | q_vector->eitr = (adapter->eitr_param >> 1); |
021230d4 | 752 | else |
30efa5a3 JB |
753 | /* rx only */ |
754 | q_vector->eitr = adapter->eitr_param; | |
021230d4 AV |
755 | |
756 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), | |
b4617240 | 757 | EITR_INTS_PER_SEC_TO_REG(q_vector->eitr)); |
9a799d71 AK |
758 | } |
759 | ||
021230d4 AV |
760 | ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx); |
761 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); | |
762 | ||
41fb9248 | 763 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 764 | mask = IXGBE_EIMS_ENABLE_MASK; |
41fb9248 | 765 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); |
021230d4 | 766 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
767 | } |
768 | ||
f494e8fa AV |
769 | enum latency_range { |
770 | lowest_latency = 0, | |
771 | low_latency = 1, | |
772 | bulk_latency = 2, | |
773 | latency_invalid = 255 | |
774 | }; | |
775 | ||
776 | /** | |
777 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
778 | * @adapter: pointer to adapter | |
779 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
780 | * @itr_setting: current throttle rate in ints/second | |
781 | * @packets: the number of packets during this measurement interval | |
782 | * @bytes: the number of bytes during this measurement interval | |
783 | * | |
784 | * Stores a new ITR value based on packets and byte | |
785 | * counts during the last interrupt. The advantage of per interrupt | |
786 | * computation is faster updates and more accurate ITR for the current | |
787 | * traffic pattern. Constants in this function were computed | |
788 | * based on theoretical maximum wire speed and thresholds were set based | |
789 | * on testing data as well as attempting to minimize response time | |
790 | * while increasing bulk throughput. | |
791 | * this functionality is controlled by the InterruptThrottleRate module | |
792 | * parameter (see ixgbe_param.c) | |
793 | **/ | |
794 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
b4617240 PW |
795 | u32 eitr, u8 itr_setting, |
796 | int packets, int bytes) | |
f494e8fa AV |
797 | { |
798 | unsigned int retval = itr_setting; | |
799 | u32 timepassed_us; | |
800 | u64 bytes_perint; | |
801 | ||
802 | if (packets == 0) | |
803 | goto update_itr_done; | |
804 | ||
805 | ||
806 | /* simple throttlerate management | |
807 | * 0-20MB/s lowest (100000 ints/s) | |
808 | * 20-100MB/s low (20000 ints/s) | |
809 | * 100-1249MB/s bulk (8000 ints/s) | |
810 | */ | |
811 | /* what was last interrupt timeslice? */ | |
812 | timepassed_us = 1000000/eitr; | |
813 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
814 | ||
815 | switch (itr_setting) { | |
816 | case lowest_latency: | |
817 | if (bytes_perint > adapter->eitr_low) | |
818 | retval = low_latency; | |
819 | break; | |
820 | case low_latency: | |
821 | if (bytes_perint > adapter->eitr_high) | |
822 | retval = bulk_latency; | |
823 | else if (bytes_perint <= adapter->eitr_low) | |
824 | retval = lowest_latency; | |
825 | break; | |
826 | case bulk_latency: | |
827 | if (bytes_perint <= adapter->eitr_high) | |
828 | retval = low_latency; | |
829 | break; | |
830 | } | |
831 | ||
832 | update_itr_done: | |
833 | return retval; | |
834 | } | |
835 | ||
836 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) | |
837 | { | |
838 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
839 | struct ixgbe_hw *hw = &adapter->hw; | |
840 | u32 new_itr; | |
841 | u8 current_itr, ret_itr; | |
842 | int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) / | |
b4617240 | 843 | sizeof(struct ixgbe_q_vector); |
f494e8fa AV |
844 | struct ixgbe_ring *rx_ring, *tx_ring; |
845 | ||
846 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
847 | for (i = 0; i < q_vector->txr_count; i++) { | |
848 | tx_ring = &(adapter->tx_ring[r_idx]); | |
849 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
850 | q_vector->tx_itr, |
851 | tx_ring->total_packets, | |
852 | tx_ring->total_bytes); | |
f494e8fa AV |
853 | /* if the result for this queue would decrease interrupt |
854 | * rate for this vector then use that result */ | |
30efa5a3 | 855 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
b4617240 | 856 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 857 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 858 | r_idx + 1); |
f494e8fa AV |
859 | } |
860 | ||
861 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
862 | for (i = 0; i < q_vector->rxr_count; i++) { | |
863 | rx_ring = &(adapter->rx_ring[r_idx]); | |
864 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
865 | q_vector->rx_itr, |
866 | rx_ring->total_packets, | |
867 | rx_ring->total_bytes); | |
f494e8fa AV |
868 | /* if the result for this queue would decrease interrupt |
869 | * rate for this vector then use that result */ | |
30efa5a3 | 870 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
b4617240 | 871 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 872 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
b4617240 | 873 | r_idx + 1); |
f494e8fa AV |
874 | } |
875 | ||
30efa5a3 | 876 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
877 | |
878 | switch (current_itr) { | |
879 | /* counts and packets in update_itr are dependent on these numbers */ | |
880 | case lowest_latency: | |
881 | new_itr = 100000; | |
882 | break; | |
883 | case low_latency: | |
884 | new_itr = 20000; /* aka hwitr = ~200 */ | |
885 | break; | |
886 | case bulk_latency: | |
887 | default: | |
888 | new_itr = 8000; | |
889 | break; | |
890 | } | |
891 | ||
892 | if (new_itr != q_vector->eitr) { | |
893 | u32 itr_reg; | |
894 | /* do an exponential smoothing */ | |
895 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
896 | q_vector->eitr = new_itr; | |
897 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); | |
898 | /* must write high and low 16 bits to reset counter */ | |
899 | DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx, | |
b4617240 | 900 | itr_reg); |
f494e8fa AV |
901 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16); |
902 | } | |
903 | ||
904 | return; | |
905 | } | |
906 | ||
cf8280ee JB |
907 | |
908 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) | |
909 | { | |
910 | struct ixgbe_hw *hw = &adapter->hw; | |
911 | ||
912 | adapter->lsc_int++; | |
913 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
914 | adapter->link_check_timeout = jiffies; | |
915 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
916 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
917 | schedule_work(&adapter->watchdog_task); | |
918 | } | |
919 | } | |
920 | ||
9a799d71 AK |
921 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
922 | { | |
923 | struct net_device *netdev = data; | |
924 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
925 | struct ixgbe_hw *hw = &adapter->hw; | |
926 | u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
927 | ||
cf8280ee JB |
928 | if (eicr & IXGBE_EICR_LSC) |
929 | ixgbe_check_lsc(adapter); | |
d4f80882 AV |
930 | |
931 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
932 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
933 | |
934 | return IRQ_HANDLED; | |
935 | } | |
936 | ||
937 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) | |
938 | { | |
021230d4 AV |
939 | struct ixgbe_q_vector *q_vector = data; |
940 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 941 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
942 | int i, r_idx; |
943 | ||
944 | if (!q_vector->txr_count) | |
945 | return IRQ_HANDLED; | |
946 | ||
947 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
948 | for (i = 0; i < q_vector->txr_count; i++) { | |
3a581073 | 949 | tx_ring = &(adapter->tx_ring[r_idx]); |
5dd2d332 | 950 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 951 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 952 | ixgbe_update_tx_dca(adapter, tx_ring); |
bd0362dd | 953 | #endif |
3a581073 JB |
954 | tx_ring->total_bytes = 0; |
955 | tx_ring->total_packets = 0; | |
956 | ixgbe_clean_tx_irq(adapter, tx_ring); | |
021230d4 | 957 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 958 | r_idx + 1); |
021230d4 | 959 | } |
9a799d71 | 960 | |
9a799d71 AK |
961 | return IRQ_HANDLED; |
962 | } | |
963 | ||
021230d4 AV |
964 | /** |
965 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
966 | * @irq: unused | |
967 | * @data: pointer to our q_vector struct for this interrupt vector | |
968 | **/ | |
9a799d71 AK |
969 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
970 | { | |
021230d4 AV |
971 | struct ixgbe_q_vector *q_vector = data; |
972 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 973 | struct ixgbe_ring *rx_ring; |
021230d4 | 974 | int r_idx; |
30efa5a3 | 975 | int i; |
021230d4 AV |
976 | |
977 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
30efa5a3 JB |
978 | for (i = 0; i < q_vector->rxr_count; i++) { |
979 | rx_ring = &(adapter->rx_ring[r_idx]); | |
980 | rx_ring->total_bytes = 0; | |
981 | rx_ring->total_packets = 0; | |
982 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
983 | r_idx + 1); | |
984 | } | |
985 | ||
021230d4 AV |
986 | if (!q_vector->rxr_count) |
987 | return IRQ_HANDLED; | |
988 | ||
30efa5a3 | 989 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 990 | rx_ring = &(adapter->rx_ring[r_idx]); |
021230d4 | 991 | /* disable interrupts on this vector only */ |
3a581073 | 992 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx); |
021230d4 AV |
993 | netif_rx_schedule(adapter->netdev, &q_vector->napi); |
994 | ||
995 | return IRQ_HANDLED; | |
996 | } | |
997 | ||
998 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
999 | { | |
1000 | ixgbe_msix_clean_rx(irq, data); | |
1001 | ixgbe_msix_clean_tx(irq, data); | |
9a799d71 | 1002 | |
9a799d71 AK |
1003 | return IRQ_HANDLED; |
1004 | } | |
1005 | ||
021230d4 AV |
1006 | /** |
1007 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
1008 | * @napi: napi struct with our devices info in it | |
1009 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1010 | * | |
f0848276 JB |
1011 | * This function is optimized for cleaning one queue only on a single |
1012 | * q_vector!!! | |
021230d4 | 1013 | **/ |
9a799d71 AK |
1014 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
1015 | { | |
021230d4 | 1016 | struct ixgbe_q_vector *q_vector = |
b4617240 | 1017 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 1018 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 1019 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 1020 | int work_done = 0; |
021230d4 | 1021 | long r_idx; |
9a799d71 | 1022 | |
021230d4 | 1023 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1024 | rx_ring = &(adapter->rx_ring[r_idx]); |
5dd2d332 | 1025 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1026 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1027 | ixgbe_update_rx_dca(adapter, rx_ring); |
bd0362dd | 1028 | #endif |
9a799d71 | 1029 | |
3a581073 | 1030 | ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget); |
9a799d71 | 1031 | |
021230d4 AV |
1032 | /* If all Rx work done, exit the polling mode */ |
1033 | if (work_done < budget) { | |
1034 | netif_rx_complete(adapter->netdev, napi); | |
30efa5a3 | 1035 | if (adapter->itr_setting & 3) |
f494e8fa | 1036 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 1037 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
3a581073 | 1038 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx); |
9a799d71 AK |
1039 | } |
1040 | ||
1041 | return work_done; | |
1042 | } | |
1043 | ||
f0848276 JB |
1044 | /** |
1045 | * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine | |
1046 | * @napi: napi struct with our devices info in it | |
1047 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1048 | * | |
1049 | * This function will clean more than one rx queue associated with a | |
1050 | * q_vector. | |
1051 | **/ | |
1052 | static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget) | |
1053 | { | |
1054 | struct ixgbe_q_vector *q_vector = | |
1055 | container_of(napi, struct ixgbe_q_vector, napi); | |
1056 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f0848276 JB |
1057 | struct ixgbe_ring *rx_ring = NULL; |
1058 | int work_done = 0, i; | |
1059 | long r_idx; | |
1060 | u16 enable_mask = 0; | |
1061 | ||
1062 | /* attempt to distribute budget to each queue fairly, but don't allow | |
1063 | * the budget to go below 1 because we'll exit polling */ | |
1064 | budget /= (q_vector->rxr_count ?: 1); | |
1065 | budget = max(budget, 1); | |
1066 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1067 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1068 | rx_ring = &(adapter->rx_ring[r_idx]); | |
5dd2d332 | 1069 | #ifdef CONFIG_IXGBE_DCA |
f0848276 JB |
1070 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1071 | ixgbe_update_rx_dca(adapter, rx_ring); | |
1072 | #endif | |
1073 | ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget); | |
1074 | enable_mask |= rx_ring->v_idx; | |
1075 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1076 | r_idx + 1); | |
1077 | } | |
1078 | ||
1079 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1080 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1081 | /* If all Rx work done, exit the polling mode */ | |
7f821875 | 1082 | if (work_done < budget) { |
74ce8dd2 | 1083 | netif_rx_complete(adapter->netdev, napi); |
f0848276 JB |
1084 | if (adapter->itr_setting & 3) |
1085 | ixgbe_set_itr_msix(q_vector); | |
1086 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1087 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask); | |
1088 | return 0; | |
1089 | } | |
1090 | ||
1091 | return work_done; | |
1092 | } | |
021230d4 | 1093 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
b4617240 | 1094 | int r_idx) |
021230d4 AV |
1095 | { |
1096 | a->q_vector[v_idx].adapter = a; | |
1097 | set_bit(r_idx, a->q_vector[v_idx].rxr_idx); | |
1098 | a->q_vector[v_idx].rxr_count++; | |
1099 | a->rx_ring[r_idx].v_idx = 1 << v_idx; | |
1100 | } | |
1101 | ||
1102 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
b4617240 | 1103 | int r_idx) |
021230d4 AV |
1104 | { |
1105 | a->q_vector[v_idx].adapter = a; | |
1106 | set_bit(r_idx, a->q_vector[v_idx].txr_idx); | |
1107 | a->q_vector[v_idx].txr_count++; | |
1108 | a->tx_ring[r_idx].v_idx = 1 << v_idx; | |
1109 | } | |
1110 | ||
9a799d71 | 1111 | /** |
021230d4 AV |
1112 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
1113 | * @adapter: board private structure to initialize | |
1114 | * @vectors: allotted vector count for descriptor rings | |
9a799d71 | 1115 | * |
021230d4 AV |
1116 | * This function maps descriptor rings to the queue-specific vectors |
1117 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
1118 | * one vector per ring/queue, but on a constrained vector budget, we | |
1119 | * group the rings as "efficiently" as possible. You would add new | |
1120 | * mapping configurations in here. | |
9a799d71 | 1121 | **/ |
021230d4 | 1122 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 1123 | int vectors) |
021230d4 AV |
1124 | { |
1125 | int v_start = 0; | |
1126 | int rxr_idx = 0, txr_idx = 0; | |
1127 | int rxr_remaining = adapter->num_rx_queues; | |
1128 | int txr_remaining = adapter->num_tx_queues; | |
1129 | int i, j; | |
1130 | int rqpv, tqpv; | |
1131 | int err = 0; | |
1132 | ||
1133 | /* No mapping required if MSI-X is disabled. */ | |
1134 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1135 | goto out; | |
9a799d71 | 1136 | |
021230d4 AV |
1137 | /* |
1138 | * The ideal configuration... | |
1139 | * We have enough vectors to map one per queue. | |
1140 | */ | |
1141 | if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
1142 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
1143 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 1144 | |
021230d4 AV |
1145 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
1146 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 1147 | |
9a799d71 | 1148 | goto out; |
021230d4 | 1149 | } |
9a799d71 | 1150 | |
021230d4 AV |
1151 | /* |
1152 | * If we don't have enough vectors for a 1-to-1 | |
1153 | * mapping, we'll have to group them so there are | |
1154 | * multiple queues per vector. | |
1155 | */ | |
1156 | /* Re-adjusting *qpv takes care of the remainder. */ | |
1157 | for (i = v_start; i < vectors; i++) { | |
1158 | rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); | |
1159 | for (j = 0; j < rqpv; j++) { | |
1160 | map_vector_to_rxq(adapter, i, rxr_idx); | |
1161 | rxr_idx++; | |
1162 | rxr_remaining--; | |
1163 | } | |
1164 | } | |
1165 | for (i = v_start; i < vectors; i++) { | |
1166 | tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); | |
1167 | for (j = 0; j < tqpv; j++) { | |
1168 | map_vector_to_txq(adapter, i, txr_idx); | |
1169 | txr_idx++; | |
1170 | txr_remaining--; | |
9a799d71 | 1171 | } |
9a799d71 AK |
1172 | } |
1173 | ||
021230d4 AV |
1174 | out: |
1175 | return err; | |
1176 | } | |
1177 | ||
1178 | /** | |
1179 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
1180 | * @adapter: board private structure | |
1181 | * | |
1182 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
1183 | * interrupts from the kernel. | |
1184 | **/ | |
1185 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
1186 | { | |
1187 | struct net_device *netdev = adapter->netdev; | |
1188 | irqreturn_t (*handler)(int, void *); | |
1189 | int i, vector, q_vectors, err; | |
1190 | ||
1191 | /* Decrement for Other and TCP Timer vectors */ | |
1192 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1193 | ||
1194 | /* Map the Tx/Rx rings to the vectors we were allotted. */ | |
1195 | err = ixgbe_map_rings_to_vectors(adapter, q_vectors); | |
1196 | if (err) | |
1197 | goto out; | |
1198 | ||
1199 | #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ | |
b4617240 PW |
1200 | (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ |
1201 | &ixgbe_msix_clean_many) | |
021230d4 AV |
1202 | for (vector = 0; vector < q_vectors; vector++) { |
1203 | handler = SET_HANDLER(&adapter->q_vector[vector]); | |
1204 | sprintf(adapter->name[vector], "%s:v%d-%s", | |
b4617240 PW |
1205 | netdev->name, vector, |
1206 | (handler == &ixgbe_msix_clean_rx) ? "Rx" : | |
1207 | ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx")); | |
021230d4 | 1208 | err = request_irq(adapter->msix_entries[vector].vector, |
b4617240 PW |
1209 | handler, 0, adapter->name[vector], |
1210 | &(adapter->q_vector[vector])); | |
9a799d71 AK |
1211 | if (err) { |
1212 | DPRINTK(PROBE, ERR, | |
b4617240 PW |
1213 | "request_irq failed for MSIX interrupt " |
1214 | "Error: %d\n", err); | |
021230d4 | 1215 | goto free_queue_irqs; |
9a799d71 | 1216 | } |
9a799d71 AK |
1217 | } |
1218 | ||
021230d4 AV |
1219 | sprintf(adapter->name[vector], "%s:lsc", netdev->name); |
1220 | err = request_irq(adapter->msix_entries[vector].vector, | |
b4617240 | 1221 | &ixgbe_msix_lsc, 0, adapter->name[vector], netdev); |
9a799d71 AK |
1222 | if (err) { |
1223 | DPRINTK(PROBE, ERR, | |
1224 | "request_irq for msix_lsc failed: %d\n", err); | |
021230d4 | 1225 | goto free_queue_irqs; |
9a799d71 AK |
1226 | } |
1227 | ||
9a799d71 AK |
1228 | return 0; |
1229 | ||
021230d4 AV |
1230 | free_queue_irqs: |
1231 | for (i = vector - 1; i >= 0; i--) | |
1232 | free_irq(adapter->msix_entries[--vector].vector, | |
b4617240 | 1233 | &(adapter->q_vector[i])); |
021230d4 AV |
1234 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
1235 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
1236 | kfree(adapter->msix_entries); |
1237 | adapter->msix_entries = NULL; | |
021230d4 | 1238 | out: |
9a799d71 AK |
1239 | return err; |
1240 | } | |
1241 | ||
f494e8fa AV |
1242 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
1243 | { | |
1244 | struct ixgbe_hw *hw = &adapter->hw; | |
1245 | struct ixgbe_q_vector *q_vector = adapter->q_vector; | |
1246 | u8 current_itr; | |
1247 | u32 new_itr = q_vector->eitr; | |
1248 | struct ixgbe_ring *rx_ring = &adapter->rx_ring[0]; | |
1249 | struct ixgbe_ring *tx_ring = &adapter->tx_ring[0]; | |
1250 | ||
30efa5a3 | 1251 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1252 | q_vector->tx_itr, |
1253 | tx_ring->total_packets, | |
1254 | tx_ring->total_bytes); | |
30efa5a3 | 1255 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1256 | q_vector->rx_itr, |
1257 | rx_ring->total_packets, | |
1258 | rx_ring->total_bytes); | |
f494e8fa | 1259 | |
30efa5a3 | 1260 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1261 | |
1262 | switch (current_itr) { | |
1263 | /* counts and packets in update_itr are dependent on these numbers */ | |
1264 | case lowest_latency: | |
1265 | new_itr = 100000; | |
1266 | break; | |
1267 | case low_latency: | |
1268 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1269 | break; | |
1270 | case bulk_latency: | |
1271 | new_itr = 8000; | |
1272 | break; | |
1273 | default: | |
1274 | break; | |
1275 | } | |
1276 | ||
1277 | if (new_itr != q_vector->eitr) { | |
1278 | u32 itr_reg; | |
1279 | /* do an exponential smoothing */ | |
1280 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
1281 | q_vector->eitr = new_itr; | |
1282 | itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr); | |
1283 | /* must write high and low 16 bits to reset counter */ | |
1284 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16); | |
1285 | } | |
1286 | ||
1287 | return; | |
1288 | } | |
1289 | ||
79aefa45 AD |
1290 | /** |
1291 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
1292 | * @adapter: board private structure | |
1293 | **/ | |
1294 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
1295 | { | |
1296 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); | |
1297 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1298 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
1299 | int i; | |
1300 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
1301 | synchronize_irq(adapter->msix_entries[i].vector); | |
1302 | } else { | |
1303 | synchronize_irq(adapter->pdev->irq); | |
1304 | } | |
1305 | } | |
1306 | ||
1307 | /** | |
1308 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
1309 | * @adapter: board private structure | |
1310 | **/ | |
1311 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) | |
1312 | { | |
1313 | u32 mask; | |
1314 | mask = IXGBE_EIMS_ENABLE_MASK; | |
1315 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); | |
1316 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1317 | } | |
021230d4 | 1318 | |
9a799d71 | 1319 | /** |
021230d4 | 1320 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
1321 | * @irq: interrupt number |
1322 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
1323 | **/ |
1324 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
1325 | { | |
1326 | struct net_device *netdev = data; | |
1327 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1328 | struct ixgbe_hw *hw = &adapter->hw; | |
1329 | u32 eicr; | |
1330 | ||
021230d4 AV |
1331 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
1332 | * therefore no explict interrupt disable is necessary */ | |
1333 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e JB |
1334 | if (!eicr) { |
1335 | /* shared interrupt alert! | |
1336 | * make sure interrupts are enabled because the read will | |
1337 | * have disabled interrupts due to EIAM */ | |
1338 | ixgbe_irq_enable(adapter); | |
9a799d71 | 1339 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 1340 | } |
9a799d71 | 1341 | |
cf8280ee JB |
1342 | if (eicr & IXGBE_EICR_LSC) |
1343 | ixgbe_check_lsc(adapter); | |
021230d4 AV |
1344 | |
1345 | if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) { | |
f494e8fa AV |
1346 | adapter->tx_ring[0].total_packets = 0; |
1347 | adapter->tx_ring[0].total_bytes = 0; | |
1348 | adapter->rx_ring[0].total_packets = 0; | |
1349 | adapter->rx_ring[0].total_bytes = 0; | |
021230d4 AV |
1350 | /* would disable interrupts here but EIAM disabled it */ |
1351 | __netif_rx_schedule(netdev, &adapter->q_vector[0].napi); | |
9a799d71 AK |
1352 | } |
1353 | ||
1354 | return IRQ_HANDLED; | |
1355 | } | |
1356 | ||
021230d4 AV |
1357 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
1358 | { | |
1359 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1360 | ||
1361 | for (i = 0; i < q_vectors; i++) { | |
1362 | struct ixgbe_q_vector *q_vector = &adapter->q_vector[i]; | |
1363 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); | |
1364 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
1365 | q_vector->rxr_count = 0; | |
1366 | q_vector->txr_count = 0; | |
1367 | } | |
1368 | } | |
1369 | ||
9a799d71 AK |
1370 | /** |
1371 | * ixgbe_request_irq - initialize interrupts | |
1372 | * @adapter: board private structure | |
1373 | * | |
1374 | * Attempts to configure interrupts using the best available | |
1375 | * capabilities of the hardware and kernel. | |
1376 | **/ | |
021230d4 | 1377 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
1378 | { |
1379 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 1380 | int err; |
9a799d71 | 1381 | |
021230d4 AV |
1382 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1383 | err = ixgbe_request_msix_irqs(adapter); | |
1384 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
1385 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0, | |
b4617240 | 1386 | netdev->name, netdev); |
021230d4 AV |
1387 | } else { |
1388 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED, | |
b4617240 | 1389 | netdev->name, netdev); |
9a799d71 AK |
1390 | } |
1391 | ||
9a799d71 AK |
1392 | if (err) |
1393 | DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err); | |
1394 | ||
9a799d71 AK |
1395 | return err; |
1396 | } | |
1397 | ||
1398 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
1399 | { | |
1400 | struct net_device *netdev = adapter->netdev; | |
1401 | ||
1402 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 1403 | int i, q_vectors; |
9a799d71 | 1404 | |
021230d4 AV |
1405 | q_vectors = adapter->num_msix_vectors; |
1406 | ||
1407 | i = q_vectors - 1; | |
9a799d71 | 1408 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 1409 | |
021230d4 AV |
1410 | i--; |
1411 | for (; i >= 0; i--) { | |
1412 | free_irq(adapter->msix_entries[i].vector, | |
b4617240 | 1413 | &(adapter->q_vector[i])); |
021230d4 AV |
1414 | } |
1415 | ||
1416 | ixgbe_reset_q_vectors(adapter); | |
1417 | } else { | |
1418 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
1419 | } |
1420 | } | |
1421 | ||
9a799d71 AK |
1422 | /** |
1423 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
1424 | * | |
1425 | **/ | |
1426 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
1427 | { | |
9a799d71 AK |
1428 | struct ixgbe_hw *hw = &adapter->hw; |
1429 | ||
021230d4 | 1430 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
30efa5a3 | 1431 | EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param)); |
9a799d71 AK |
1432 | |
1433 | ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0); | |
021230d4 AV |
1434 | ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0); |
1435 | ||
1436 | map_vector_to_rxq(adapter, 0, 0); | |
1437 | map_vector_to_txq(adapter, 0, 0); | |
1438 | ||
1439 | DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n"); | |
9a799d71 AK |
1440 | } |
1441 | ||
1442 | /** | |
3a581073 | 1443 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
1444 | * @adapter: board private structure |
1445 | * | |
1446 | * Configure the Tx unit of the MAC after a reset. | |
1447 | **/ | |
1448 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
1449 | { | |
e01c31a5 | 1450 | u64 tdba, tdwba; |
9a799d71 | 1451 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 1452 | u32 i, j, tdlen, txctrl; |
9a799d71 AK |
1453 | |
1454 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
1455 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
e01c31a5 JB |
1456 | struct ixgbe_ring *ring = &adapter->tx_ring[i]; |
1457 | j = ring->reg_idx; | |
1458 | tdba = ring->dma; | |
1459 | tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc); | |
021230d4 | 1460 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), |
e01c31a5 | 1461 | (tdba & DMA_32BIT_MASK)); |
021230d4 | 1462 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); |
e01c31a5 JB |
1463 | tdwba = ring->dma + |
1464 | (ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
1465 | tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE; | |
1466 | IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK); | |
1467 | IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32)); | |
021230d4 AV |
1468 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen); |
1469 | IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | |
1470 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | |
1471 | adapter->tx_ring[i].head = IXGBE_TDH(j); | |
1472 | adapter->tx_ring[i].tail = IXGBE_TDT(j); | |
1473 | /* Disable Tx Head Writeback RO bit, since this hoses | |
1474 | * bookkeeping if things aren't delivered in order. | |
1475 | */ | |
e01c31a5 | 1476 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); |
021230d4 | 1477 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; |
e01c31a5 | 1478 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); |
9a799d71 | 1479 | } |
9a799d71 AK |
1480 | } |
1481 | ||
cc41ac7c JB |
1482 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
1483 | ||
1484 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index) | |
1485 | { | |
1486 | struct ixgbe_ring *rx_ring; | |
1487 | u32 srrctl; | |
1488 | int queue0; | |
3be1adfb AD |
1489 | unsigned long mask; |
1490 | ||
1491 | /* program one srrctl register per VMDq index */ | |
1492 | if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { | |
1493 | long shift, len; | |
1494 | mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask; | |
1495 | len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8; | |
1496 | shift = find_first_bit(&mask, len); | |
1497 | queue0 = index & mask; | |
1498 | index = (index & mask) >> shift; | |
1499 | /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */ | |
cc41ac7c | 1500 | } else { |
3be1adfb AD |
1501 | mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask; |
1502 | queue0 = index & mask; | |
1503 | index = index & mask; | |
cc41ac7c | 1504 | } |
3be1adfb | 1505 | |
cc41ac7c JB |
1506 | rx_ring = &adapter->rx_ring[queue0]; |
1507 | ||
1508 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); | |
1509 | ||
1510 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
1511 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
1512 | ||
1513 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
1514 | srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1515 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; | |
1516 | srrctl |= ((IXGBE_RX_HDR_SIZE << | |
b4617240 PW |
1517 | IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
1518 | IXGBE_SRRCTL_BSIZEHDR_MASK); | |
cc41ac7c JB |
1519 | } else { |
1520 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; | |
1521 | ||
1522 | if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE) | |
1523 | srrctl |= IXGBE_RXBUFFER_2048 >> | |
1524 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1525 | else | |
1526 | srrctl |= rx_ring->rx_buf_len >> | |
1527 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1528 | } | |
1529 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); | |
1530 | } | |
9a799d71 | 1531 | |
177db6ff MC |
1532 | /** |
1533 | * ixgbe_get_skb_hdr - helper function for LRO header processing | |
1534 | * @skb: pointer to sk_buff to be added to LRO packet | |
b4617240 | 1535 | * @iphdr: pointer to ip header structure |
177db6ff MC |
1536 | * @tcph: pointer to tcp header structure |
1537 | * @hdr_flags: pointer to header flags | |
1538 | * @priv: private data | |
1539 | **/ | |
1540 | static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph, | |
1541 | u64 *hdr_flags, void *priv) | |
1542 | { | |
1543 | union ixgbe_adv_rx_desc *rx_desc = priv; | |
1544 | ||
1545 | /* Verify that this is a valid IPv4 TCP packet */ | |
e9990a9c JB |
1546 | if (!((ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_IPV4) && |
1547 | (ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_TCP))) | |
177db6ff MC |
1548 | return -1; |
1549 | ||
1550 | /* Set network headers */ | |
1551 | skb_reset_network_header(skb); | |
1552 | skb_set_transport_header(skb, ip_hdrlen(skb)); | |
1553 | *iphdr = ip_hdr(skb); | |
1554 | *tcph = tcp_hdr(skb); | |
1555 | *hdr_flags = LRO_IPV4 | LRO_TCP; | |
1556 | return 0; | |
1557 | } | |
1558 | ||
cc41ac7c | 1559 | #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ |
b4617240 | 1560 | (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) |
cc41ac7c | 1561 | |
9a799d71 | 1562 | /** |
3a581073 | 1563 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset |
9a799d71 AK |
1564 | * @adapter: board private structure |
1565 | * | |
1566 | * Configure the Rx unit of the MAC after a reset. | |
1567 | **/ | |
1568 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
1569 | { | |
1570 | u64 rdba; | |
1571 | struct ixgbe_hw *hw = &adapter->hw; | |
1572 | struct net_device *netdev = adapter->netdev; | |
1573 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
021230d4 | 1574 | int i, j; |
9a799d71 | 1575 | u32 rdlen, rxctrl, rxcsum; |
7c6e0a43 JB |
1576 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, |
1577 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, | |
1578 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
9a799d71 | 1579 | u32 fctrl, hlreg0; |
9a799d71 | 1580 | u32 pages; |
cc41ac7c JB |
1581 | u32 reta = 0, mrqc; |
1582 | u32 rdrxctl; | |
7c6e0a43 | 1583 | int rx_buf_len; |
9a799d71 AK |
1584 | |
1585 | /* Decide whether to use packet split mode or not */ | |
762f4c57 | 1586 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; |
9a799d71 AK |
1587 | |
1588 | /* Set the RX buffer length according to the mode */ | |
1589 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 1590 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
9a799d71 AK |
1591 | } else { |
1592 | if (netdev->mtu <= ETH_DATA_LEN) | |
7c6e0a43 | 1593 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 1594 | else |
7c6e0a43 | 1595 | rx_buf_len = ALIGN(max_frame, 1024); |
9a799d71 AK |
1596 | } |
1597 | ||
1598 | fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); | |
1599 | fctrl |= IXGBE_FCTRL_BAM; | |
021230d4 | 1600 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ |
9a799d71 AK |
1601 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl); |
1602 | ||
1603 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
1604 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
1605 | hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; | |
1606 | else | |
1607 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
1608 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
1609 | ||
1610 | pages = PAGE_USE_COUNT(adapter->netdev->mtu); | |
1611 | ||
9a799d71 AK |
1612 | rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc); |
1613 | /* disable receives while setting up the descriptors */ | |
1614 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
1615 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
1616 | ||
1617 | /* Setup the HW Rx Head and Tail Descriptor Pointers and | |
1618 | * the Base and Length of the Rx Descriptor Ring */ | |
1619 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1620 | rdba = adapter->rx_ring[i].dma; | |
7c6e0a43 JB |
1621 | j = adapter->rx_ring[i].reg_idx; |
1622 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK)); | |
1623 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); | |
1624 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen); | |
1625 | IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); | |
1626 | IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); | |
1627 | adapter->rx_ring[i].head = IXGBE_RDH(j); | |
1628 | adapter->rx_ring[i].tail = IXGBE_RDT(j); | |
1629 | adapter->rx_ring[i].rx_buf_len = rx_buf_len; | |
e9990a9c JB |
1630 | /* Intitial LRO Settings */ |
1631 | adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE; | |
1632 | adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS; | |
1633 | adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr; | |
1634 | adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID; | |
1635 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) | |
1636 | adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI; | |
1637 | adapter->rx_ring[i].lro_mgr.dev = adapter->netdev; | |
1638 | adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; | |
1639 | adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; | |
cc41ac7c JB |
1640 | |
1641 | ixgbe_configure_srrctl(adapter, j); | |
9a799d71 AK |
1642 | } |
1643 | ||
cc41ac7c JB |
1644 | /* |
1645 | * For VMDq support of different descriptor types or | |
1646 | * buffer sizes through the use of multiple SRRCTL | |
1647 | * registers, RDRXCTL.MVMEN must be set to 1 | |
1648 | * | |
1649 | * also, the manual doesn't mention it clearly but DCA hints | |
1650 | * will only use queue 0's tags unless this bit is set. Side | |
1651 | * effects of setting this bit are only that SRRCTL must be | |
1652 | * fully programmed [0..15] | |
1653 | */ | |
1654 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
1655 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
1656 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
1657 | ||
177db6ff | 1658 | |
021230d4 | 1659 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
9a799d71 | 1660 | /* Fill out redirection table */ |
021230d4 AV |
1661 | for (i = 0, j = 0; i < 128; i++, j++) { |
1662 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
1663 | j = 0; | |
1664 | /* reta = 4-byte sliding window of | |
1665 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
1666 | reta = (reta << 8) | (j * 0x11); | |
1667 | if ((i & 3) == 3) | |
1668 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
9a799d71 AK |
1669 | } |
1670 | ||
1671 | /* Fill out hash function seeds */ | |
1672 | for (i = 0; i < 10; i++) | |
7c6e0a43 | 1673 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); |
9a799d71 AK |
1674 | |
1675 | mrqc = IXGBE_MRQC_RSSEN | |
1676 | /* Perform hash on these packet types */ | |
7c6e0a43 JB |
1677 | | IXGBE_MRQC_RSS_FIELD_IPV4 |
1678 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
1679 | | IXGBE_MRQC_RSS_FIELD_IPV4_UDP | |
1680 | | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP | |
1681 | | IXGBE_MRQC_RSS_FIELD_IPV6_EX | |
1682 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
1683 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP | |
1684 | | IXGBE_MRQC_RSS_FIELD_IPV6_UDP | |
1685 | | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP; | |
9a799d71 | 1686 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
021230d4 | 1687 | } |
9a799d71 | 1688 | |
021230d4 AV |
1689 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); |
1690 | ||
1691 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED || | |
1692 | adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) { | |
1693 | /* Disable indicating checksum in descriptor, enables | |
1694 | * RSS hash */ | |
9a799d71 | 1695 | rxcsum |= IXGBE_RXCSUM_PCSD; |
9a799d71 | 1696 | } |
021230d4 AV |
1697 | if (!(rxcsum & IXGBE_RXCSUM_PCSD)) { |
1698 | /* Enable IPv4 payload checksum for UDP fragments | |
1699 | * if PCSD is not set */ | |
1700 | rxcsum |= IXGBE_RXCSUM_IPPCSE; | |
1701 | } | |
1702 | ||
1703 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
9a799d71 AK |
1704 | } |
1705 | ||
1706 | static void ixgbe_vlan_rx_register(struct net_device *netdev, | |
b4617240 | 1707 | struct vlan_group *grp) |
9a799d71 AK |
1708 | { |
1709 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1710 | u32 ctrl; | |
1711 | ||
d4f80882 AV |
1712 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1713 | ixgbe_irq_disable(adapter); | |
9a799d71 AK |
1714 | adapter->vlgrp = grp; |
1715 | ||
1716 | if (grp) { | |
1717 | /* enable VLAN tag insert/strip */ | |
1718 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
746b9f02 | 1719 | ctrl |= IXGBE_VLNCTRL_VME; |
9a799d71 AK |
1720 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; |
1721 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
1722 | } | |
1723 | ||
d4f80882 AV |
1724 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1725 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
1726 | } |
1727 | ||
1728 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) | |
1729 | { | |
1730 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
c44ade9e | 1731 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
1732 | |
1733 | /* add VID to filter table */ | |
c44ade9e | 1734 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true); |
9a799d71 AK |
1735 | } |
1736 | ||
1737 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
1738 | { | |
1739 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
c44ade9e | 1740 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 1741 | |
d4f80882 AV |
1742 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1743 | ixgbe_irq_disable(adapter); | |
1744 | ||
9a799d71 | 1745 | vlan_group_set_device(adapter->vlgrp, vid, NULL); |
d4f80882 AV |
1746 | |
1747 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1748 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
1749 | |
1750 | /* remove VID from filter table */ | |
c44ade9e | 1751 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false); |
9a799d71 AK |
1752 | } |
1753 | ||
1754 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) | |
1755 | { | |
1756 | ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
1757 | ||
1758 | if (adapter->vlgrp) { | |
1759 | u16 vid; | |
1760 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
1761 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
1762 | continue; | |
1763 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
1764 | } | |
1765 | } | |
1766 | } | |
1767 | ||
2c5645cf CL |
1768 | static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq) |
1769 | { | |
1770 | struct dev_mc_list *mc_ptr; | |
1771 | u8 *addr = *mc_addr_ptr; | |
1772 | *vmdq = 0; | |
1773 | ||
1774 | mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]); | |
1775 | if (mc_ptr->next) | |
1776 | *mc_addr_ptr = mc_ptr->next->dmi_addr; | |
1777 | else | |
1778 | *mc_addr_ptr = NULL; | |
1779 | ||
1780 | return addr; | |
1781 | } | |
1782 | ||
9a799d71 | 1783 | /** |
2c5645cf | 1784 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
1785 | * @netdev: network interface device structure |
1786 | * | |
2c5645cf CL |
1787 | * The set_rx_method entry point is called whenever the unicast/multicast |
1788 | * address list or the network interface flags are updated. This routine is | |
1789 | * responsible for configuring the hardware for proper unicast, multicast and | |
1790 | * promiscuous mode. | |
9a799d71 | 1791 | **/ |
2c5645cf | 1792 | static void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
1793 | { |
1794 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1795 | struct ixgbe_hw *hw = &adapter->hw; | |
3d01625a | 1796 | u32 fctrl, vlnctrl; |
2c5645cf CL |
1797 | u8 *addr_list = NULL; |
1798 | int addr_count = 0; | |
9a799d71 AK |
1799 | |
1800 | /* Check for Promiscuous and All Multicast modes */ | |
1801 | ||
1802 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3d01625a | 1803 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
9a799d71 AK |
1804 | |
1805 | if (netdev->flags & IFF_PROMISC) { | |
2c5645cf | 1806 | hw->addr_ctrl.user_set_promisc = 1; |
9a799d71 | 1807 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
3d01625a | 1808 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; |
9a799d71 | 1809 | } else { |
746b9f02 PM |
1810 | if (netdev->flags & IFF_ALLMULTI) { |
1811 | fctrl |= IXGBE_FCTRL_MPE; | |
1812 | fctrl &= ~IXGBE_FCTRL_UPE; | |
1813 | } else { | |
1814 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
1815 | } | |
3d01625a | 1816 | vlnctrl |= IXGBE_VLNCTRL_VFE; |
2c5645cf | 1817 | hw->addr_ctrl.user_set_promisc = 0; |
9a799d71 AK |
1818 | } |
1819 | ||
1820 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3d01625a | 1821 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
9a799d71 | 1822 | |
2c5645cf CL |
1823 | /* reprogram secondary unicast list */ |
1824 | addr_count = netdev->uc_count; | |
1825 | if (addr_count) | |
1826 | addr_list = netdev->uc_list->dmi_addr; | |
c44ade9e JB |
1827 | hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count, |
1828 | ixgbe_addr_list_itr); | |
9a799d71 | 1829 | |
2c5645cf CL |
1830 | /* reprogram multicast list */ |
1831 | addr_count = netdev->mc_count; | |
1832 | if (addr_count) | |
1833 | addr_list = netdev->mc_list->dmi_addr; | |
c44ade9e JB |
1834 | hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count, |
1835 | ixgbe_addr_list_itr); | |
9a799d71 AK |
1836 | } |
1837 | ||
021230d4 AV |
1838 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
1839 | { | |
1840 | int q_idx; | |
1841 | struct ixgbe_q_vector *q_vector; | |
1842 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1843 | ||
1844 | /* legacy and MSI only use one vector */ | |
1845 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1846 | q_vectors = 1; | |
1847 | ||
1848 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 1849 | struct napi_struct *napi; |
021230d4 AV |
1850 | q_vector = &adapter->q_vector[q_idx]; |
1851 | if (!q_vector->rxr_count) | |
1852 | continue; | |
f0848276 JB |
1853 | napi = &q_vector->napi; |
1854 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) && | |
1855 | (q_vector->rxr_count > 1)) | |
1856 | napi->poll = &ixgbe_clean_rxonly_many; | |
1857 | ||
1858 | napi_enable(napi); | |
021230d4 AV |
1859 | } |
1860 | } | |
1861 | ||
1862 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
1863 | { | |
1864 | int q_idx; | |
1865 | struct ixgbe_q_vector *q_vector; | |
1866 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1867 | ||
1868 | /* legacy and MSI only use one vector */ | |
1869 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1870 | q_vectors = 1; | |
1871 | ||
1872 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
1873 | q_vector = &adapter->q_vector[q_idx]; | |
1874 | if (!q_vector->rxr_count) | |
1875 | continue; | |
1876 | napi_disable(&q_vector->napi); | |
1877 | } | |
1878 | } | |
1879 | ||
9a799d71 AK |
1880 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
1881 | { | |
1882 | struct net_device *netdev = adapter->netdev; | |
1883 | int i; | |
1884 | ||
2c5645cf | 1885 | ixgbe_set_rx_mode(netdev); |
9a799d71 AK |
1886 | |
1887 | ixgbe_restore_vlan(adapter); | |
1888 | ||
1889 | ixgbe_configure_tx(adapter); | |
1890 | ixgbe_configure_rx(adapter); | |
1891 | for (i = 0; i < adapter->num_rx_queues; i++) | |
1892 | ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i], | |
b4617240 | 1893 | (adapter->rx_ring[i].count - 1)); |
9a799d71 AK |
1894 | } |
1895 | ||
1896 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) | |
1897 | { | |
1898 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 1899 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 1900 | int i, j = 0; |
9a799d71 | 1901 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 AV |
1902 | u32 txdctl, rxdctl, mhadd; |
1903 | u32 gpie; | |
9a799d71 | 1904 | |
5eba3699 AV |
1905 | ixgbe_get_hw_control(adapter); |
1906 | ||
021230d4 AV |
1907 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) || |
1908 | (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) { | |
9a799d71 AK |
1909 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1910 | gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME | | |
b4617240 | 1911 | IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD); |
9a799d71 AK |
1912 | } else { |
1913 | /* MSI only */ | |
021230d4 | 1914 | gpie = 0; |
9a799d71 | 1915 | } |
021230d4 AV |
1916 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
1917 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
1918 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
9a799d71 AK |
1919 | } |
1920 | ||
021230d4 AV |
1921 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
1922 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, | |
1923 | * specifically only auto mask tx and rx interrupts */ | |
1924 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
1925 | } | |
9a799d71 | 1926 | |
021230d4 | 1927 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
9a799d71 AK |
1928 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { |
1929 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
1930 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
1931 | ||
1932 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
1933 | } | |
1934 | ||
1935 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
021230d4 AV |
1936 | j = adapter->tx_ring[i].reg_idx; |
1937 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
e01c31a5 JB |
1938 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ |
1939 | txdctl |= (8 << 16); | |
9a799d71 | 1940 | txdctl |= IXGBE_TXDCTL_ENABLE; |
021230d4 | 1941 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
9a799d71 AK |
1942 | } |
1943 | ||
1944 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
021230d4 AV |
1945 | j = adapter->rx_ring[i].reg_idx; |
1946 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
1947 | /* enable PTHRESH=32 descriptors (half the internal cache) | |
1948 | * and HTHRESH=0 descriptors (to minimize latency on fetch), | |
1949 | * this also removes a pesky rx_no_buffer_count increment */ | |
1950 | rxdctl |= 0x0020; | |
9a799d71 | 1951 | rxdctl |= IXGBE_RXDCTL_ENABLE; |
021230d4 | 1952 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl); |
9a799d71 AK |
1953 | } |
1954 | /* enable all receives */ | |
1955 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
1956 | rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); | |
1957 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl); | |
1958 | ||
1959 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
1960 | ixgbe_configure_msix(adapter); | |
1961 | else | |
1962 | ixgbe_configure_msi_and_legacy(adapter); | |
1963 | ||
1964 | clear_bit(__IXGBE_DOWN, &adapter->state); | |
021230d4 AV |
1965 | ixgbe_napi_enable_all(adapter); |
1966 | ||
1967 | /* clear any pending interrupts, may auto mask */ | |
1968 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
1969 | ||
9a799d71 AK |
1970 | ixgbe_irq_enable(adapter); |
1971 | ||
1972 | /* bring the link up in the watchdog, this could race with our first | |
1973 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
1974 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
1975 | adapter->link_check_timeout = jiffies; | |
9a799d71 AK |
1976 | mod_timer(&adapter->watchdog_timer, jiffies); |
1977 | return 0; | |
1978 | } | |
1979 | ||
d4f80882 AV |
1980 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
1981 | { | |
1982 | WARN_ON(in_interrupt()); | |
1983 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
1984 | msleep(1); | |
1985 | ixgbe_down(adapter); | |
1986 | ixgbe_up(adapter); | |
1987 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
1988 | } | |
1989 | ||
9a799d71 AK |
1990 | int ixgbe_up(struct ixgbe_adapter *adapter) |
1991 | { | |
1992 | /* hardware has been reset, we need to reload some things */ | |
1993 | ixgbe_configure(adapter); | |
1994 | ||
1995 | return ixgbe_up_complete(adapter); | |
1996 | } | |
1997 | ||
1998 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
1999 | { | |
c44ade9e JB |
2000 | struct ixgbe_hw *hw = &adapter->hw; |
2001 | if (hw->mac.ops.init_hw(hw)) | |
2002 | dev_err(&adapter->pdev->dev, "Hardware Error\n"); | |
9a799d71 AK |
2003 | |
2004 | /* reprogram the RAR[0] in case user changed it. */ | |
c44ade9e | 2005 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
2006 | |
2007 | } | |
2008 | ||
9a799d71 AK |
2009 | /** |
2010 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
2011 | * @adapter: board private structure | |
2012 | * @rx_ring: ring to free buffers from | |
2013 | **/ | |
2014 | static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2015 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
2016 | { |
2017 | struct pci_dev *pdev = adapter->pdev; | |
2018 | unsigned long size; | |
2019 | unsigned int i; | |
2020 | ||
2021 | /* Free all the Rx ring sk_buffs */ | |
2022 | ||
2023 | for (i = 0; i < rx_ring->count; i++) { | |
2024 | struct ixgbe_rx_buffer *rx_buffer_info; | |
2025 | ||
2026 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
2027 | if (rx_buffer_info->dma) { | |
2028 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
b4617240 PW |
2029 | rx_ring->rx_buf_len, |
2030 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
2031 | rx_buffer_info->dma = 0; |
2032 | } | |
2033 | if (rx_buffer_info->skb) { | |
2034 | dev_kfree_skb(rx_buffer_info->skb); | |
2035 | rx_buffer_info->skb = NULL; | |
2036 | } | |
2037 | if (!rx_buffer_info->page) | |
2038 | continue; | |
762f4c57 JB |
2039 | pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2, |
2040 | PCI_DMA_FROMDEVICE); | |
9a799d71 | 2041 | rx_buffer_info->page_dma = 0; |
9a799d71 AK |
2042 | put_page(rx_buffer_info->page); |
2043 | rx_buffer_info->page = NULL; | |
762f4c57 | 2044 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
2045 | } |
2046 | ||
2047 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
2048 | memset(rx_ring->rx_buffer_info, 0, size); | |
2049 | ||
2050 | /* Zero out the descriptor ring */ | |
2051 | memset(rx_ring->desc, 0, rx_ring->size); | |
2052 | ||
2053 | rx_ring->next_to_clean = 0; | |
2054 | rx_ring->next_to_use = 0; | |
2055 | ||
2056 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
2057 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
2058 | } | |
2059 | ||
2060 | /** | |
2061 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
2062 | * @adapter: board private structure | |
2063 | * @tx_ring: ring to be cleaned | |
2064 | **/ | |
2065 | static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2066 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
2067 | { |
2068 | struct ixgbe_tx_buffer *tx_buffer_info; | |
2069 | unsigned long size; | |
2070 | unsigned int i; | |
2071 | ||
2072 | /* Free all the Tx ring sk_buffs */ | |
2073 | ||
2074 | for (i = 0; i < tx_ring->count; i++) { | |
2075 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
2076 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
2077 | } | |
2078 | ||
2079 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
2080 | memset(tx_ring->tx_buffer_info, 0, size); | |
2081 | ||
2082 | /* Zero out the descriptor ring */ | |
2083 | memset(tx_ring->desc, 0, tx_ring->size); | |
2084 | ||
2085 | tx_ring->next_to_use = 0; | |
2086 | tx_ring->next_to_clean = 0; | |
2087 | ||
2088 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
2089 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
2090 | } | |
2091 | ||
2092 | /** | |
021230d4 | 2093 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
2094 | * @adapter: board private structure |
2095 | **/ | |
021230d4 | 2096 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2097 | { |
2098 | int i; | |
2099 | ||
021230d4 AV |
2100 | for (i = 0; i < adapter->num_rx_queues; i++) |
2101 | ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
2102 | } |
2103 | ||
2104 | /** | |
021230d4 | 2105 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
2106 | * @adapter: board private structure |
2107 | **/ | |
021230d4 | 2108 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2109 | { |
2110 | int i; | |
2111 | ||
021230d4 AV |
2112 | for (i = 0; i < adapter->num_tx_queues; i++) |
2113 | ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
2114 | } |
2115 | ||
2116 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
2117 | { | |
2118 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 2119 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 2120 | u32 rxctrl; |
7f821875 JB |
2121 | u32 txdctl; |
2122 | int i, j; | |
9a799d71 AK |
2123 | |
2124 | /* signal that we are down to the interrupt handler */ | |
2125 | set_bit(__IXGBE_DOWN, &adapter->state); | |
2126 | ||
2127 | /* disable receives */ | |
7f821875 JB |
2128 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
2129 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 AK |
2130 | |
2131 | netif_tx_disable(netdev); | |
2132 | ||
7f821875 | 2133 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
2134 | msleep(10); |
2135 | ||
7f821875 JB |
2136 | netif_tx_stop_all_queues(netdev); |
2137 | ||
9a799d71 AK |
2138 | ixgbe_irq_disable(adapter); |
2139 | ||
021230d4 | 2140 | ixgbe_napi_disable_all(adapter); |
7f821875 | 2141 | |
9a799d71 | 2142 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 2143 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 2144 | |
7f821875 JB |
2145 | /* disable transmits in the hardware now that interrupts are off */ |
2146 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2147 | j = adapter->tx_ring[i].reg_idx; | |
2148 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2149 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), | |
2150 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); | |
2151 | } | |
2152 | ||
9a799d71 | 2153 | netif_carrier_off(netdev); |
9a799d71 | 2154 | |
5dd2d332 | 2155 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 JB |
2156 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2157 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
2158 | dca_remove_requester(&adapter->pdev->dev); | |
2159 | } | |
2160 | ||
2161 | #endif | |
6f4a0e45 PL |
2162 | if (!pci_channel_offline(adapter->pdev)) |
2163 | ixgbe_reset(adapter); | |
9a799d71 AK |
2164 | ixgbe_clean_all_tx_rings(adapter); |
2165 | ixgbe_clean_all_rx_rings(adapter); | |
2166 | ||
5dd2d332 | 2167 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 JB |
2168 | /* since we reset the hardware DCA settings were cleared */ |
2169 | if (dca_add_requester(&adapter->pdev->dev) == 0) { | |
2170 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; | |
2171 | /* always use CB2 mode, difference is masked | |
2172 | * in the CB driver */ | |
b4617240 | 2173 | IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); |
96b0e0f6 JB |
2174 | ixgbe_setup_dca(adapter); |
2175 | } | |
2176 | #endif | |
9a799d71 AK |
2177 | } |
2178 | ||
9a799d71 | 2179 | /** |
021230d4 AV |
2180 | * ixgbe_poll - NAPI Rx polling callback |
2181 | * @napi: structure for representing this polling device | |
2182 | * @budget: how many packets driver is allowed to clean | |
2183 | * | |
2184 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 2185 | **/ |
021230d4 | 2186 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 2187 | { |
021230d4 | 2188 | struct ixgbe_q_vector *q_vector = container_of(napi, |
b4617240 | 2189 | struct ixgbe_q_vector, napi); |
021230d4 | 2190 | struct ixgbe_adapter *adapter = q_vector->adapter; |
74ce8dd2 | 2191 | int tx_cleaned, work_done = 0; |
9a799d71 | 2192 | |
5dd2d332 | 2193 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
2194 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2195 | ixgbe_update_tx_dca(adapter, adapter->tx_ring); | |
2196 | ixgbe_update_rx_dca(adapter, adapter->rx_ring); | |
2197 | } | |
2198 | #endif | |
2199 | ||
d2c7ddd6 | 2200 | tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring); |
021230d4 | 2201 | ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget); |
9a799d71 | 2202 | |
d2c7ddd6 DM |
2203 | if (tx_cleaned) |
2204 | work_done = budget; | |
2205 | ||
53e52c72 DM |
2206 | /* If budget not fully consumed, exit the polling mode */ |
2207 | if (work_done < budget) { | |
021230d4 | 2208 | netif_rx_complete(adapter->netdev, napi); |
30efa5a3 | 2209 | if (adapter->itr_setting & 3) |
f494e8fa | 2210 | ixgbe_set_itr(adapter); |
d4f80882 AV |
2211 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2212 | ixgbe_irq_enable(adapter); | |
9a799d71 | 2213 | } |
9a799d71 AK |
2214 | return work_done; |
2215 | } | |
2216 | ||
2217 | /** | |
2218 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
2219 | * @netdev: network interface device structure | |
2220 | **/ | |
2221 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
2222 | { | |
2223 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2224 | ||
2225 | /* Do the reset outside of interrupt context */ | |
2226 | schedule_work(&adapter->reset_task); | |
2227 | } | |
2228 | ||
2229 | static void ixgbe_reset_task(struct work_struct *work) | |
2230 | { | |
2231 | struct ixgbe_adapter *adapter; | |
2232 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
2233 | ||
2234 | adapter->tx_timeout_count++; | |
2235 | ||
d4f80882 | 2236 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
2237 | } |
2238 | ||
b9804972 JB |
2239 | static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
2240 | { | |
2241 | int nrq = 1, ntq = 1; | |
2242 | int feature_mask = 0, rss_i, rss_m; | |
2243 | ||
2244 | /* Number of supported queues */ | |
2245 | switch (adapter->hw.mac.type) { | |
2246 | case ixgbe_mac_82598EB: | |
2247 | rss_i = adapter->ring_feature[RING_F_RSS].indices; | |
2248 | rss_m = 0; | |
2249 | feature_mask |= IXGBE_FLAG_RSS_ENABLED; | |
2250 | ||
2251 | switch (adapter->flags & feature_mask) { | |
2252 | case (IXGBE_FLAG_RSS_ENABLED): | |
2253 | rss_m = 0xF; | |
2254 | nrq = rss_i; | |
2255 | ntq = rss_i; | |
2256 | break; | |
2257 | case 0: | |
2258 | default: | |
2259 | rss_i = 0; | |
2260 | rss_m = 0; | |
2261 | nrq = 1; | |
2262 | ntq = 1; | |
2263 | break; | |
2264 | } | |
2265 | ||
2266 | adapter->ring_feature[RING_F_RSS].indices = rss_i; | |
2267 | adapter->ring_feature[RING_F_RSS].mask = rss_m; | |
2268 | break; | |
2269 | default: | |
2270 | nrq = 1; | |
2271 | ntq = 1; | |
2272 | break; | |
2273 | } | |
2274 | ||
2275 | adapter->num_rx_queues = nrq; | |
2276 | adapter->num_tx_queues = ntq; | |
2277 | } | |
2278 | ||
021230d4 | 2279 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 2280 | int vectors) |
021230d4 AV |
2281 | { |
2282 | int err, vector_threshold; | |
2283 | ||
2284 | /* We'll want at least 3 (vector_threshold): | |
2285 | * 1) TxQ[0] Cleanup | |
2286 | * 2) RxQ[0] Cleanup | |
2287 | * 3) Other (Link Status Change, etc.) | |
2288 | * 4) TCP Timer (optional) | |
2289 | */ | |
2290 | vector_threshold = MIN_MSIX_COUNT; | |
2291 | ||
2292 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
2293 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
2294 | * Right now, we simply care about how many we'll get; we'll | |
2295 | * set them up later while requesting irq's. | |
2296 | */ | |
2297 | while (vectors >= vector_threshold) { | |
2298 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
b4617240 | 2299 | vectors); |
021230d4 AV |
2300 | if (!err) /* Success in acquiring all requested vectors. */ |
2301 | break; | |
2302 | else if (err < 0) | |
2303 | vectors = 0; /* Nasty failure, quit now */ | |
2304 | else /* err == number of vectors we should try again with */ | |
2305 | vectors = err; | |
2306 | } | |
2307 | ||
2308 | if (vectors < vector_threshold) { | |
2309 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
2310 | * This just means we'll go with either a single MSI | |
2311 | * vector or fall back to legacy interrupts. | |
2312 | */ | |
2313 | DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n"); | |
2314 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
2315 | kfree(adapter->msix_entries); | |
2316 | adapter->msix_entries = NULL; | |
2317 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
b9804972 | 2318 | ixgbe_set_num_queues(adapter); |
021230d4 AV |
2319 | } else { |
2320 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
2321 | adapter->num_msix_vectors = vectors; | |
2322 | } | |
2323 | } | |
2324 | ||
021230d4 AV |
2325 | /** |
2326 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
2327 | * @adapter: board private structure to initialize | |
2328 | * | |
2329 | * Once we know the feature-set enabled for the device, we'll cache | |
2330 | * the register offset the descriptor ring is assigned to. | |
2331 | **/ | |
43ced651 | 2332 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) |
021230d4 | 2333 | { |
021230d4 AV |
2334 | int feature_mask = 0, rss_i; |
2335 | int i, txr_idx, rxr_idx; | |
2336 | ||
2337 | /* Number of supported queues */ | |
2338 | switch (adapter->hw.mac.type) { | |
2339 | case ixgbe_mac_82598EB: | |
2340 | rss_i = adapter->ring_feature[RING_F_RSS].indices; | |
2341 | txr_idx = 0; | |
2342 | rxr_idx = 0; | |
2343 | feature_mask |= IXGBE_FLAG_RSS_ENABLED; | |
2344 | switch (adapter->flags & feature_mask) { | |
2345 | case (IXGBE_FLAG_RSS_ENABLED): | |
2346 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2347 | adapter->rx_ring[i].reg_idx = i; | |
2348 | for (i = 0; i < adapter->num_tx_queues; i++) | |
2349 | adapter->tx_ring[i].reg_idx = i; | |
2350 | break; | |
2351 | case 0: | |
2352 | default: | |
2353 | break; | |
2354 | } | |
2355 | break; | |
2356 | default: | |
2357 | break; | |
2358 | } | |
2359 | } | |
2360 | ||
9a799d71 AK |
2361 | /** |
2362 | * ixgbe_alloc_queues - Allocate memory for all rings | |
2363 | * @adapter: board private structure to initialize | |
2364 | * | |
2365 | * We allocate one ring per queue at run-time since we don't know the | |
2366 | * number of queues at compile-time. The polling_netdev array is | |
2367 | * intended for Multiqueue, but should work fine with a single queue. | |
2368 | **/ | |
43ced651 | 2369 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2370 | { |
2371 | int i; | |
2372 | ||
2373 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
b4617240 | 2374 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
9a799d71 | 2375 | if (!adapter->tx_ring) |
021230d4 | 2376 | goto err_tx_ring_allocation; |
9a799d71 AK |
2377 | |
2378 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
b4617240 | 2379 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
021230d4 AV |
2380 | if (!adapter->rx_ring) |
2381 | goto err_rx_ring_allocation; | |
9a799d71 | 2382 | |
021230d4 | 2383 | for (i = 0; i < adapter->num_tx_queues; i++) { |
b9804972 | 2384 | adapter->tx_ring[i].count = adapter->tx_ring_count; |
021230d4 AV |
2385 | adapter->tx_ring[i].queue_index = i; |
2386 | } | |
b9804972 | 2387 | |
9a799d71 | 2388 | for (i = 0; i < adapter->num_rx_queues; i++) { |
b9804972 | 2389 | adapter->rx_ring[i].count = adapter->rx_ring_count; |
021230d4 AV |
2390 | adapter->rx_ring[i].queue_index = i; |
2391 | } | |
2392 | ||
2393 | ixgbe_cache_ring_register(adapter); | |
2394 | ||
2395 | return 0; | |
2396 | ||
2397 | err_rx_ring_allocation: | |
2398 | kfree(adapter->tx_ring); | |
2399 | err_tx_ring_allocation: | |
2400 | return -ENOMEM; | |
2401 | } | |
2402 | ||
2403 | /** | |
2404 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
2405 | * @adapter: board private structure to initialize | |
2406 | * | |
2407 | * Attempt to configure the interrupts using the best available | |
2408 | * capabilities of the hardware and the kernel. | |
2409 | **/ | |
43ced651 | 2410 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
2411 | { |
2412 | int err = 0; | |
2413 | int vector, v_budget; | |
2414 | ||
2415 | /* | |
2416 | * It's easy to be greedy for MSI-X vectors, but it really | |
2417 | * doesn't do us much good if we have a lot more vectors | |
2418 | * than CPU's. So let's be conservative and only ask for | |
2419 | * (roughly) twice the number of vectors as there are CPU's. | |
2420 | */ | |
2421 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
b4617240 | 2422 | (int)(num_online_cpus() * 2)) + NON_Q_VECTORS; |
021230d4 AV |
2423 | |
2424 | /* | |
2425 | * At the same time, hardware can only support a maximum of | |
2426 | * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq, | |
2427 | * we can easily reach upwards of 64 Rx descriptor queues and | |
2428 | * 32 Tx queues. Thus, we cap it off in those rare cases where | |
2429 | * the cpu count also exceeds our vector limit. | |
2430 | */ | |
2431 | v_budget = min(v_budget, MAX_MSIX_COUNT); | |
2432 | ||
2433 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
2434 | * mean we disable MSI-X capabilities of the adapter. */ | |
2435 | adapter->msix_entries = kcalloc(v_budget, | |
b4617240 | 2436 | sizeof(struct msix_entry), GFP_KERNEL); |
021230d4 AV |
2437 | if (!adapter->msix_entries) { |
2438 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
2439 | ixgbe_set_num_queues(adapter); | |
2440 | kfree(adapter->tx_ring); | |
2441 | kfree(adapter->rx_ring); | |
2442 | err = ixgbe_alloc_queues(adapter); | |
2443 | if (err) { | |
2444 | DPRINTK(PROBE, ERR, "Unable to allocate memory " | |
b4617240 | 2445 | "for queues\n"); |
021230d4 AV |
2446 | goto out; |
2447 | } | |
2448 | ||
2449 | goto try_msi; | |
2450 | } | |
2451 | ||
2452 | for (vector = 0; vector < v_budget; vector++) | |
2453 | adapter->msix_entries[vector].entry = vector; | |
2454 | ||
2455 | ixgbe_acquire_msix_vectors(adapter, v_budget); | |
2456 | ||
2457 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2458 | goto out; | |
2459 | ||
2460 | try_msi: | |
2461 | err = pci_enable_msi(adapter->pdev); | |
2462 | if (!err) { | |
2463 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
2464 | } else { | |
2465 | DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, " | |
b4617240 | 2466 | "falling back to legacy. Error: %d\n", err); |
021230d4 AV |
2467 | /* reset err */ |
2468 | err = 0; | |
2469 | } | |
2470 | ||
2471 | out: | |
30eba97a | 2472 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ |
fd2ea0a7 | 2473 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; |
021230d4 AV |
2474 | |
2475 | return err; | |
2476 | } | |
2477 | ||
2478 | static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) | |
2479 | { | |
2480 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
2481 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
2482 | pci_disable_msix(adapter->pdev); | |
2483 | kfree(adapter->msix_entries); | |
2484 | adapter->msix_entries = NULL; | |
2485 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
2486 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
2487 | pci_disable_msi(adapter->pdev); | |
2488 | } | |
2489 | return; | |
2490 | } | |
2491 | ||
2492 | /** | |
2493 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
2494 | * @adapter: board private structure to initialize | |
2495 | * | |
2496 | * We determine which interrupt scheme to use based on... | |
2497 | * - Kernel support (MSI, MSI-X) | |
2498 | * - which can be user-defined (via MODULE_PARAM) | |
2499 | * - Hardware queue count (num_*_queues) | |
2500 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
2501 | **/ | |
43ced651 | 2502 | static int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
2503 | { |
2504 | int err; | |
2505 | ||
2506 | /* Number of supported queues */ | |
2507 | ixgbe_set_num_queues(adapter); | |
2508 | ||
2509 | err = ixgbe_alloc_queues(adapter); | |
2510 | if (err) { | |
2511 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); | |
2512 | goto err_alloc_queues; | |
2513 | } | |
2514 | ||
2515 | err = ixgbe_set_interrupt_capability(adapter); | |
2516 | if (err) { | |
2517 | DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); | |
2518 | goto err_set_interrupt; | |
9a799d71 AK |
2519 | } |
2520 | ||
021230d4 | 2521 | DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, " |
b4617240 PW |
2522 | "Tx Queue count = %u\n", |
2523 | (adapter->num_rx_queues > 1) ? "Enabled" : | |
2524 | "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
2525 | |
2526 | set_bit(__IXGBE_DOWN, &adapter->state); | |
2527 | ||
9a799d71 | 2528 | return 0; |
021230d4 AV |
2529 | |
2530 | err_set_interrupt: | |
2531 | kfree(adapter->tx_ring); | |
2532 | kfree(adapter->rx_ring); | |
2533 | err_alloc_queues: | |
2534 | return err; | |
9a799d71 AK |
2535 | } |
2536 | ||
2537 | /** | |
2538 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
2539 | * @adapter: board private structure to initialize | |
2540 | * | |
2541 | * ixgbe_sw_init initializes the Adapter private data structure. | |
2542 | * Fields are initialized based on PCI device information and | |
2543 | * OS network device settings (MTU size). | |
2544 | **/ | |
2545 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
2546 | { | |
2547 | struct ixgbe_hw *hw = &adapter->hw; | |
2548 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 AV |
2549 | unsigned int rss; |
2550 | ||
c44ade9e JB |
2551 | /* PCI config space info */ |
2552 | ||
2553 | hw->vendor_id = pdev->vendor; | |
2554 | hw->device_id = pdev->device; | |
2555 | hw->revision_id = pdev->revision; | |
2556 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
2557 | hw->subsystem_device_id = pdev->subsystem_device; | |
2558 | ||
021230d4 AV |
2559 | /* Set capability flags */ |
2560 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
2561 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
2562 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
9a799d71 AK |
2563 | |
2564 | /* default flow control settings */ | |
2b9ade93 JB |
2565 | hw->fc.original_type = ixgbe_fc_none; |
2566 | hw->fc.type = ixgbe_fc_none; | |
2567 | hw->fc.high_water = IXGBE_DEFAULT_FCRTH; | |
2568 | hw->fc.low_water = IXGBE_DEFAULT_FCRTL; | |
2569 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; | |
2570 | hw->fc.send_xon = true; | |
9a799d71 | 2571 | |
021230d4 | 2572 | /* select 10G link by default */ |
9a799d71 | 2573 | hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN; |
9a799d71 | 2574 | |
30efa5a3 JB |
2575 | /* enable itr by default in dynamic mode */ |
2576 | adapter->itr_setting = 1; | |
2577 | adapter->eitr_param = 20000; | |
2578 | ||
2579 | /* set defaults for eitr in MegaBytes */ | |
2580 | adapter->eitr_low = 10; | |
2581 | adapter->eitr_high = 20; | |
2582 | ||
2583 | /* set default ring sizes */ | |
2584 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
2585 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
2586 | ||
9a799d71 | 2587 | /* initialize eeprom parameters */ |
c44ade9e | 2588 | if (ixgbe_init_eeprom_params_generic(hw)) { |
9a799d71 AK |
2589 | dev_err(&pdev->dev, "EEPROM initialization failed\n"); |
2590 | return -EIO; | |
2591 | } | |
2592 | ||
021230d4 | 2593 | /* enable rx csum by default */ |
9a799d71 AK |
2594 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
2595 | ||
9a799d71 AK |
2596 | set_bit(__IXGBE_DOWN, &adapter->state); |
2597 | ||
2598 | return 0; | |
2599 | } | |
2600 | ||
2601 | /** | |
2602 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
2603 | * @adapter: board private structure | |
3a581073 | 2604 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
2605 | * |
2606 | * Return 0 on success, negative on failure | |
2607 | **/ | |
2608 | int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, | |
e01c31a5 | 2609 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
2610 | { |
2611 | struct pci_dev *pdev = adapter->pdev; | |
2612 | int size; | |
2613 | ||
3a581073 JB |
2614 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
2615 | tx_ring->tx_buffer_info = vmalloc(size); | |
e01c31a5 JB |
2616 | if (!tx_ring->tx_buffer_info) |
2617 | goto err; | |
3a581073 | 2618 | memset(tx_ring->tx_buffer_info, 0, size); |
9a799d71 AK |
2619 | |
2620 | /* round up to nearest 4K */ | |
e01c31a5 JB |
2621 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) + |
2622 | sizeof(u32); | |
3a581073 | 2623 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 2624 | |
3a581073 JB |
2625 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, |
2626 | &tx_ring->dma); | |
e01c31a5 JB |
2627 | if (!tx_ring->desc) |
2628 | goto err; | |
9a799d71 | 2629 | |
3a581073 JB |
2630 | tx_ring->next_to_use = 0; |
2631 | tx_ring->next_to_clean = 0; | |
2632 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 2633 | return 0; |
e01c31a5 JB |
2634 | |
2635 | err: | |
2636 | vfree(tx_ring->tx_buffer_info); | |
2637 | tx_ring->tx_buffer_info = NULL; | |
2638 | DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit " | |
2639 | "descriptor ring\n"); | |
2640 | return -ENOMEM; | |
9a799d71 AK |
2641 | } |
2642 | ||
69888674 AD |
2643 | /** |
2644 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
2645 | * @adapter: board private structure | |
2646 | * | |
2647 | * If this function returns with an error, then it's possible one or | |
2648 | * more of the rings is populated (while the rest are not). It is the | |
2649 | * callers duty to clean those orphaned rings. | |
2650 | * | |
2651 | * Return 0 on success, negative on failure | |
2652 | **/ | |
2653 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
2654 | { | |
2655 | int i, err = 0; | |
2656 | ||
2657 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2658 | err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
2659 | if (!err) | |
2660 | continue; | |
2661 | DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); | |
2662 | break; | |
2663 | } | |
2664 | ||
2665 | return err; | |
2666 | } | |
2667 | ||
9a799d71 AK |
2668 | /** |
2669 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
2670 | * @adapter: board private structure | |
3a581073 | 2671 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
2672 | * |
2673 | * Returns 0 on success, negative on failure | |
2674 | **/ | |
2675 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, | |
b4617240 | 2676 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
2677 | { |
2678 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 2679 | int size; |
9a799d71 | 2680 | |
177db6ff | 2681 | size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS; |
3a581073 JB |
2682 | rx_ring->lro_mgr.lro_arr = vmalloc(size); |
2683 | if (!rx_ring->lro_mgr.lro_arr) | |
177db6ff | 2684 | return -ENOMEM; |
3a581073 | 2685 | memset(rx_ring->lro_mgr.lro_arr, 0, size); |
177db6ff | 2686 | |
3a581073 JB |
2687 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
2688 | rx_ring->rx_buffer_info = vmalloc(size); | |
2689 | if (!rx_ring->rx_buffer_info) { | |
9a799d71 | 2690 | DPRINTK(PROBE, ERR, |
b4617240 | 2691 | "vmalloc allocation failed for the rx desc ring\n"); |
177db6ff | 2692 | goto alloc_failed; |
9a799d71 | 2693 | } |
3a581073 | 2694 | memset(rx_ring->rx_buffer_info, 0, size); |
9a799d71 | 2695 | |
9a799d71 | 2696 | /* Round up to nearest 4K */ |
3a581073 JB |
2697 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
2698 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 2699 | |
3a581073 | 2700 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma); |
9a799d71 | 2701 | |
3a581073 | 2702 | if (!rx_ring->desc) { |
9a799d71 | 2703 | DPRINTK(PROBE, ERR, |
b4617240 | 2704 | "Memory allocation failed for the rx desc ring\n"); |
3a581073 | 2705 | vfree(rx_ring->rx_buffer_info); |
177db6ff | 2706 | goto alloc_failed; |
9a799d71 AK |
2707 | } |
2708 | ||
3a581073 JB |
2709 | rx_ring->next_to_clean = 0; |
2710 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
2711 | |
2712 | return 0; | |
177db6ff MC |
2713 | |
2714 | alloc_failed: | |
3a581073 JB |
2715 | vfree(rx_ring->lro_mgr.lro_arr); |
2716 | rx_ring->lro_mgr.lro_arr = NULL; | |
177db6ff | 2717 | return -ENOMEM; |
9a799d71 AK |
2718 | } |
2719 | ||
69888674 AD |
2720 | /** |
2721 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
2722 | * @adapter: board private structure | |
2723 | * | |
2724 | * If this function returns with an error, then it's possible one or | |
2725 | * more of the rings is populated (while the rest are not). It is the | |
2726 | * callers duty to clean those orphaned rings. | |
2727 | * | |
2728 | * Return 0 on success, negative on failure | |
2729 | **/ | |
2730 | ||
2731 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) | |
2732 | { | |
2733 | int i, err = 0; | |
2734 | ||
2735 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2736 | err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
2737 | if (!err) | |
2738 | continue; | |
2739 | DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i); | |
2740 | break; | |
2741 | } | |
2742 | ||
2743 | return err; | |
2744 | } | |
2745 | ||
9a799d71 AK |
2746 | /** |
2747 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
2748 | * @adapter: board private structure | |
2749 | * @tx_ring: Tx descriptor ring for a specific queue | |
2750 | * | |
2751 | * Free all transmit software resources | |
2752 | **/ | |
c431f97e JB |
2753 | void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter, |
2754 | struct ixgbe_ring *tx_ring) | |
9a799d71 AK |
2755 | { |
2756 | struct pci_dev *pdev = adapter->pdev; | |
2757 | ||
2758 | ixgbe_clean_tx_ring(adapter, tx_ring); | |
2759 | ||
2760 | vfree(tx_ring->tx_buffer_info); | |
2761 | tx_ring->tx_buffer_info = NULL; | |
2762 | ||
2763 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
2764 | ||
2765 | tx_ring->desc = NULL; | |
2766 | } | |
2767 | ||
2768 | /** | |
2769 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
2770 | * @adapter: board private structure | |
2771 | * | |
2772 | * Free all transmit software resources | |
2773 | **/ | |
2774 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
2775 | { | |
2776 | int i; | |
2777 | ||
2778 | for (i = 0; i < adapter->num_tx_queues; i++) | |
2779 | ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]); | |
2780 | } | |
2781 | ||
2782 | /** | |
b4617240 | 2783 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
2784 | * @adapter: board private structure |
2785 | * @rx_ring: ring to clean the resources from | |
2786 | * | |
2787 | * Free all receive software resources | |
2788 | **/ | |
c431f97e JB |
2789 | void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter, |
2790 | struct ixgbe_ring *rx_ring) | |
9a799d71 AK |
2791 | { |
2792 | struct pci_dev *pdev = adapter->pdev; | |
2793 | ||
177db6ff MC |
2794 | vfree(rx_ring->lro_mgr.lro_arr); |
2795 | rx_ring->lro_mgr.lro_arr = NULL; | |
2796 | ||
9a799d71 AK |
2797 | ixgbe_clean_rx_ring(adapter, rx_ring); |
2798 | ||
2799 | vfree(rx_ring->rx_buffer_info); | |
2800 | rx_ring->rx_buffer_info = NULL; | |
2801 | ||
2802 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
2803 | ||
2804 | rx_ring->desc = NULL; | |
2805 | } | |
2806 | ||
2807 | /** | |
2808 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
2809 | * @adapter: board private structure | |
2810 | * | |
2811 | * Free all receive software resources | |
2812 | **/ | |
2813 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
2814 | { | |
2815 | int i; | |
2816 | ||
2817 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2818 | ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]); | |
2819 | } | |
2820 | ||
9a799d71 AK |
2821 | /** |
2822 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
2823 | * @netdev: network interface device structure | |
2824 | * @new_mtu: new value for maximum frame size | |
2825 | * | |
2826 | * Returns 0 on success, negative on failure | |
2827 | **/ | |
2828 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
2829 | { | |
2830 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2831 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
2832 | ||
42c783c5 JB |
2833 | /* MTU < 68 is an error and causes problems on some kernels */ |
2834 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
2835 | return -EINVAL; |
2836 | ||
021230d4 | 2837 | DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", |
b4617240 | 2838 | netdev->mtu, new_mtu); |
021230d4 | 2839 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
2840 | netdev->mtu = new_mtu; |
2841 | ||
d4f80882 AV |
2842 | if (netif_running(netdev)) |
2843 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
2844 | |
2845 | return 0; | |
2846 | } | |
2847 | ||
2848 | /** | |
2849 | * ixgbe_open - Called when a network interface is made active | |
2850 | * @netdev: network interface device structure | |
2851 | * | |
2852 | * Returns 0 on success, negative value on failure | |
2853 | * | |
2854 | * The open entry point is called when a network interface is made | |
2855 | * active by the system (IFF_UP). At this point all resources needed | |
2856 | * for transmit and receive operations are allocated, the interrupt | |
2857 | * handler is registered with the OS, the watchdog timer is started, | |
2858 | * and the stack is notified that the interface is ready. | |
2859 | **/ | |
2860 | static int ixgbe_open(struct net_device *netdev) | |
2861 | { | |
2862 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2863 | int err; | |
4bebfaa5 AK |
2864 | |
2865 | /* disallow open during test */ | |
2866 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
2867 | return -EBUSY; | |
9a799d71 | 2868 | |
9a799d71 AK |
2869 | /* allocate transmit descriptors */ |
2870 | err = ixgbe_setup_all_tx_resources(adapter); | |
2871 | if (err) | |
2872 | goto err_setup_tx; | |
2873 | ||
9a799d71 AK |
2874 | /* allocate receive descriptors */ |
2875 | err = ixgbe_setup_all_rx_resources(adapter); | |
2876 | if (err) | |
2877 | goto err_setup_rx; | |
2878 | ||
2879 | ixgbe_configure(adapter); | |
2880 | ||
021230d4 | 2881 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
2882 | if (err) |
2883 | goto err_req_irq; | |
2884 | ||
9a799d71 AK |
2885 | err = ixgbe_up_complete(adapter); |
2886 | if (err) | |
2887 | goto err_up; | |
2888 | ||
d55b53ff JK |
2889 | netif_tx_start_all_queues(netdev); |
2890 | ||
9a799d71 AK |
2891 | return 0; |
2892 | ||
2893 | err_up: | |
5eba3699 | 2894 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
2895 | ixgbe_free_irq(adapter); |
2896 | err_req_irq: | |
2897 | ixgbe_free_all_rx_resources(adapter); | |
2898 | err_setup_rx: | |
2899 | ixgbe_free_all_tx_resources(adapter); | |
2900 | err_setup_tx: | |
2901 | ixgbe_reset(adapter); | |
2902 | ||
2903 | return err; | |
2904 | } | |
2905 | ||
2906 | /** | |
2907 | * ixgbe_close - Disables a network interface | |
2908 | * @netdev: network interface device structure | |
2909 | * | |
2910 | * Returns 0, this is not allowed to fail | |
2911 | * | |
2912 | * The close entry point is called when an interface is de-activated | |
2913 | * by the OS. The hardware is still under the drivers control, but | |
2914 | * needs to be disabled. A global MAC reset is issued to stop the | |
2915 | * hardware, and all transmit and receive resources are freed. | |
2916 | **/ | |
2917 | static int ixgbe_close(struct net_device *netdev) | |
2918 | { | |
2919 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
2920 | |
2921 | ixgbe_down(adapter); | |
2922 | ixgbe_free_irq(adapter); | |
2923 | ||
2924 | ixgbe_free_all_tx_resources(adapter); | |
2925 | ixgbe_free_all_rx_resources(adapter); | |
2926 | ||
5eba3699 | 2927 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
2928 | |
2929 | return 0; | |
2930 | } | |
2931 | ||
b3c8b4ba AD |
2932 | /** |
2933 | * ixgbe_napi_add_all - prep napi structs for use | |
2934 | * @adapter: private struct | |
2935 | * helper function to napi_add each possible q_vector->napi | |
2936 | */ | |
2937 | static void ixgbe_napi_add_all(struct ixgbe_adapter *adapter) | |
2938 | { | |
2939 | int q_idx, q_vectors; | |
2940 | int (*poll)(struct napi_struct *, int); | |
2941 | ||
2942 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
2943 | poll = &ixgbe_clean_rxonly; | |
2944 | /* Only enable as many vectors as we have rx queues. */ | |
2945 | q_vectors = adapter->num_rx_queues; | |
2946 | } else { | |
2947 | poll = &ixgbe_poll; | |
2948 | /* only one q_vector for legacy modes */ | |
2949 | q_vectors = 1; | |
2950 | } | |
2951 | ||
2952 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
2953 | struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx]; | |
2954 | netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); | |
2955 | } | |
2956 | } | |
2957 | ||
2958 | static void ixgbe_napi_del_all(struct ixgbe_adapter *adapter) | |
2959 | { | |
2960 | int q_idx; | |
2961 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2962 | ||
2963 | /* legacy and MSI only use one vector */ | |
2964 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2965 | q_vectors = 1; | |
2966 | ||
2967 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
2968 | struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx]; | |
2969 | if (!q_vector->rxr_count) | |
2970 | continue; | |
2971 | netif_napi_del(&q_vector->napi); | |
2972 | } | |
2973 | } | |
2974 | ||
2975 | #ifdef CONFIG_PM | |
2976 | static int ixgbe_resume(struct pci_dev *pdev) | |
2977 | { | |
2978 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2979 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2980 | u32 err; | |
2981 | ||
2982 | pci_set_power_state(pdev, PCI_D0); | |
2983 | pci_restore_state(pdev); | |
2984 | err = pci_enable_device(pdev); | |
2985 | if (err) { | |
69888674 | 2986 | printk(KERN_ERR "ixgbe: Cannot enable PCI device from " |
b3c8b4ba AD |
2987 | "suspend\n"); |
2988 | return err; | |
2989 | } | |
2990 | pci_set_master(pdev); | |
2991 | ||
2992 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
2993 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
2994 | ||
2995 | err = ixgbe_init_interrupt_scheme(adapter); | |
2996 | if (err) { | |
2997 | printk(KERN_ERR "ixgbe: Cannot initialize interrupts for " | |
2998 | "device\n"); | |
2999 | return err; | |
3000 | } | |
3001 | ||
3002 | ixgbe_napi_add_all(adapter); | |
3003 | ixgbe_reset(adapter); | |
3004 | ||
3005 | if (netif_running(netdev)) { | |
3006 | err = ixgbe_open(adapter->netdev); | |
3007 | if (err) | |
3008 | return err; | |
3009 | } | |
3010 | ||
3011 | netif_device_attach(netdev); | |
3012 | ||
3013 | return 0; | |
3014 | } | |
3015 | ||
3016 | #endif /* CONFIG_PM */ | |
3017 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
3018 | { | |
3019 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3020 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3021 | #ifdef CONFIG_PM | |
3022 | int retval = 0; | |
3023 | #endif | |
3024 | ||
3025 | netif_device_detach(netdev); | |
3026 | ||
3027 | if (netif_running(netdev)) { | |
3028 | ixgbe_down(adapter); | |
3029 | ixgbe_free_irq(adapter); | |
3030 | ixgbe_free_all_tx_resources(adapter); | |
3031 | ixgbe_free_all_rx_resources(adapter); | |
3032 | } | |
3033 | ixgbe_reset_interrupt_capability(adapter); | |
3034 | ixgbe_napi_del_all(adapter); | |
3035 | kfree(adapter->tx_ring); | |
3036 | kfree(adapter->rx_ring); | |
3037 | ||
3038 | #ifdef CONFIG_PM | |
3039 | retval = pci_save_state(pdev); | |
3040 | if (retval) | |
3041 | return retval; | |
3042 | #endif | |
3043 | ||
3044 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
3045 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
3046 | ||
3047 | ixgbe_release_hw_control(adapter); | |
3048 | ||
3049 | pci_disable_device(pdev); | |
3050 | ||
3051 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
3052 | ||
3053 | return 0; | |
3054 | } | |
3055 | ||
3056 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
3057 | { | |
3058 | ixgbe_suspend(pdev, PMSG_SUSPEND); | |
3059 | } | |
3060 | ||
9a799d71 AK |
3061 | /** |
3062 | * ixgbe_update_stats - Update the board statistics counters. | |
3063 | * @adapter: board private structure | |
3064 | **/ | |
3065 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
3066 | { | |
3067 | struct ixgbe_hw *hw = &adapter->hw; | |
6f11eef7 AV |
3068 | u64 total_mpc = 0; |
3069 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
9a799d71 AK |
3070 | |
3071 | adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); | |
6f11eef7 AV |
3072 | for (i = 0; i < 8; i++) { |
3073 | /* for packet buffers not used, the register should read 0 */ | |
3074 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
3075 | missed_rx += mpc; | |
3076 | adapter->stats.mpc[i] += mpc; | |
3077 | total_mpc += adapter->stats.mpc[i]; | |
3078 | adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
3079 | } | |
3080 | adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); | |
3081 | /* work around hardware counting issue */ | |
3082 | adapter->stats.gprc -= missed_rx; | |
3083 | ||
3084 | /* 82598 hardware only has a 32 bit counter in the high register */ | |
9a799d71 | 3085 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
6f11eef7 AV |
3086 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); |
3087 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
9a799d71 AK |
3088 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
3089 | adapter->stats.bprc += bprc; | |
3090 | adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
3091 | adapter->stats.mprc -= bprc; | |
3092 | adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
3093 | adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
3094 | adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
3095 | adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
3096 | adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
3097 | adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
3098 | adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
9a799d71 AK |
3099 | adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); |
3100 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
9a799d71 | 3101 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); |
6f11eef7 AV |
3102 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
3103 | adapter->stats.lxontxc += lxon; | |
3104 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
3105 | adapter->stats.lxofftxc += lxoff; | |
9a799d71 AK |
3106 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
3107 | adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
6f11eef7 AV |
3108 | adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); |
3109 | /* | |
3110 | * 82598 errata - tx of flow control packets is included in tx counters | |
3111 | */ | |
3112 | xon_off_tot = lxon + lxoff; | |
3113 | adapter->stats.gptc -= xon_off_tot; | |
3114 | adapter->stats.mptc -= xon_off_tot; | |
3115 | adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
9a799d71 AK |
3116 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
3117 | adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
3118 | adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
9a799d71 AK |
3119 | adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR); |
3120 | adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6f11eef7 | 3121 | adapter->stats.ptc64 -= xon_off_tot; |
9a799d71 AK |
3122 | adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); |
3123 | adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
3124 | adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
3125 | adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
3126 | adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
9a799d71 AK |
3127 | adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); |
3128 | ||
3129 | /* Fill out the OS statistics structure */ | |
9a799d71 AK |
3130 | adapter->net_stats.multicast = adapter->stats.mprc; |
3131 | ||
3132 | /* Rx Errors */ | |
3133 | adapter->net_stats.rx_errors = adapter->stats.crcerrs + | |
b4617240 | 3134 | adapter->stats.rlec; |
9a799d71 AK |
3135 | adapter->net_stats.rx_dropped = 0; |
3136 | adapter->net_stats.rx_length_errors = adapter->stats.rlec; | |
3137 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | |
6f11eef7 | 3138 | adapter->net_stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
3139 | } |
3140 | ||
3141 | /** | |
3142 | * ixgbe_watchdog - Timer Call-back | |
3143 | * @data: pointer to adapter cast into an unsigned long | |
3144 | **/ | |
3145 | static void ixgbe_watchdog(unsigned long data) | |
3146 | { | |
3147 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee JB |
3148 | struct ixgbe_hw *hw = &adapter->hw; |
3149 | ||
3150 | /* Do the watchdog outside of interrupt context due to the lovely | |
3151 | * delays that some of the newer hardware requires */ | |
3152 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
3153 | /* Cause software interrupt to ensure rx rings are cleaned */ | |
3154 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3155 | u32 eics = | |
3156 | (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1; | |
3157 | IXGBE_WRITE_REG(hw, IXGBE_EICS, eics); | |
3158 | } else { | |
3159 | /* For legacy and MSI interrupts don't set any bits that | |
3160 | * are enabled for EIAM, because this operation would | |
3161 | * set *both* EIMS and EICS for any bit in EIAM */ | |
3162 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
3163 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
3164 | } | |
3165 | /* Reset the timer */ | |
3166 | mod_timer(&adapter->watchdog_timer, | |
3167 | round_jiffies(jiffies + 2 * HZ)); | |
3168 | } | |
9a799d71 | 3169 | |
cf8280ee JB |
3170 | schedule_work(&adapter->watchdog_task); |
3171 | } | |
3172 | ||
3173 | /** | |
69888674 AD |
3174 | * ixgbe_watchdog_task - worker thread to bring link up |
3175 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
3176 | **/ |
3177 | static void ixgbe_watchdog_task(struct work_struct *work) | |
3178 | { | |
3179 | struct ixgbe_adapter *adapter = container_of(work, | |
3180 | struct ixgbe_adapter, | |
3181 | watchdog_task); | |
3182 | struct net_device *netdev = adapter->netdev; | |
3183 | struct ixgbe_hw *hw = &adapter->hw; | |
3184 | u32 link_speed = adapter->link_speed; | |
3185 | bool link_up = adapter->link_up; | |
3186 | ||
3187 | adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK; | |
3188 | ||
3189 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
3190 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
3191 | if (link_up || | |
3192 | time_after(jiffies, (adapter->link_check_timeout + | |
3193 | IXGBE_TRY_LINK_TIMEOUT))) { | |
3194 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
3195 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
3196 | } | |
3197 | adapter->link_up = link_up; | |
3198 | adapter->link_speed = link_speed; | |
3199 | } | |
9a799d71 AK |
3200 | |
3201 | if (link_up) { | |
3202 | if (!netif_carrier_ok(netdev)) { | |
cf8280ee JB |
3203 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
3204 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
9a799d71 AK |
3205 | #define FLOW_RX (frctl & IXGBE_FCTRL_RFCE) |
3206 | #define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X) | |
3207 | DPRINTK(LINK, INFO, "NIC Link is Up %s, " | |
cf8280ee JB |
3208 | "Flow Control: %s\n", |
3209 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
3210 | "10 Gbps" : | |
3211 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
3212 | "1 Gbps" : "unknown speed")), | |
3213 | ((FLOW_RX && FLOW_TX) ? "RX/TX" : | |
3214 | (FLOW_RX ? "RX" : | |
3215 | (FLOW_TX ? "TX" : "None")))); | |
9a799d71 AK |
3216 | |
3217 | netif_carrier_on(netdev); | |
fd2ea0a7 | 3218 | netif_tx_wake_all_queues(netdev); |
9a799d71 AK |
3219 | } else { |
3220 | /* Force detection of hung controller */ | |
3221 | adapter->detect_tx_hung = true; | |
3222 | } | |
3223 | } else { | |
cf8280ee JB |
3224 | adapter->link_up = false; |
3225 | adapter->link_speed = 0; | |
9a799d71 AK |
3226 | if (netif_carrier_ok(netdev)) { |
3227 | DPRINTK(LINK, INFO, "NIC Link is Down\n"); | |
3228 | netif_carrier_off(netdev); | |
fd2ea0a7 | 3229 | netif_tx_stop_all_queues(netdev); |
9a799d71 AK |
3230 | } |
3231 | } | |
3232 | ||
3233 | ixgbe_update_stats(adapter); | |
cf8280ee | 3234 | adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK; |
9a799d71 AK |
3235 | } |
3236 | ||
9a799d71 | 3237 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
b4617240 PW |
3238 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
3239 | u32 tx_flags, u8 *hdr_len) | |
9a799d71 AK |
3240 | { |
3241 | struct ixgbe_adv_tx_context_desc *context_desc; | |
3242 | unsigned int i; | |
3243 | int err; | |
3244 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
3245 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
3246 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
3247 | |
3248 | if (skb_is_gso(skb)) { | |
3249 | if (skb_header_cloned(skb)) { | |
3250 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
3251 | if (err) | |
3252 | return err; | |
3253 | } | |
3254 | l4len = tcp_hdrlen(skb); | |
3255 | *hdr_len += l4len; | |
3256 | ||
8327d000 | 3257 | if (skb->protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
3258 | struct iphdr *iph = ip_hdr(skb); |
3259 | iph->tot_len = 0; | |
3260 | iph->check = 0; | |
3261 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
b4617240 PW |
3262 | iph->daddr, 0, |
3263 | IPPROTO_TCP, | |
3264 | 0); | |
9a799d71 AK |
3265 | adapter->hw_tso_ctxt++; |
3266 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | |
3267 | ipv6_hdr(skb)->payload_len = 0; | |
3268 | tcp_hdr(skb)->check = | |
3269 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
b4617240 PW |
3270 | &ipv6_hdr(skb)->daddr, |
3271 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
3272 | adapter->hw_tso6_ctxt++; |
3273 | } | |
3274 | ||
3275 | i = tx_ring->next_to_use; | |
3276 | ||
3277 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3278 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
3279 | ||
3280 | /* VLAN MACLEN IPLEN */ | |
3281 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
3282 | vlan_macip_lens |= | |
3283 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
3284 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
b4617240 | 3285 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
3286 | *hdr_len += skb_network_offset(skb); |
3287 | vlan_macip_lens |= | |
3288 | (skb_transport_header(skb) - skb_network_header(skb)); | |
3289 | *hdr_len += | |
3290 | (skb_transport_header(skb) - skb_network_header(skb)); | |
3291 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
3292 | context_desc->seqnum_seed = 0; | |
3293 | ||
3294 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 3295 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
b4617240 | 3296 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 3297 | |
8327d000 | 3298 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
3299 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
3300 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
3301 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
3302 | ||
3303 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 3304 | mss_l4len_idx = |
9a799d71 AK |
3305 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
3306 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
3307 | /* use index 1 for TSO */ |
3308 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
3309 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
3310 | ||
3311 | tx_buffer_info->time_stamp = jiffies; | |
3312 | tx_buffer_info->next_to_watch = i; | |
3313 | ||
3314 | i++; | |
3315 | if (i == tx_ring->count) | |
3316 | i = 0; | |
3317 | tx_ring->next_to_use = i; | |
3318 | ||
3319 | return true; | |
3320 | } | |
3321 | return false; | |
3322 | } | |
3323 | ||
3324 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, | |
b4617240 PW |
3325 | struct ixgbe_ring *tx_ring, |
3326 | struct sk_buff *skb, u32 tx_flags) | |
9a799d71 AK |
3327 | { |
3328 | struct ixgbe_adv_tx_context_desc *context_desc; | |
3329 | unsigned int i; | |
3330 | struct ixgbe_tx_buffer *tx_buffer_info; | |
3331 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
3332 | ||
3333 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
3334 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
3335 | i = tx_ring->next_to_use; | |
3336 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3337 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
3338 | ||
3339 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
3340 | vlan_macip_lens |= | |
3341 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
3342 | vlan_macip_lens |= (skb_network_offset(skb) << | |
b4617240 | 3343 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
3344 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
3345 | vlan_macip_lens |= (skb_transport_header(skb) - | |
b4617240 | 3346 | skb_network_header(skb)); |
9a799d71 AK |
3347 | |
3348 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
3349 | context_desc->seqnum_seed = 0; | |
3350 | ||
3351 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
b4617240 | 3352 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 AK |
3353 | |
3354 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
41825d71 AK |
3355 | switch (skb->protocol) { |
3356 | case __constant_htons(ETH_P_IP): | |
9a799d71 | 3357 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
41825d71 AK |
3358 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
3359 | type_tucmd_mlhl |= | |
b4617240 | 3360 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
41825d71 | 3361 | break; |
41825d71 AK |
3362 | case __constant_htons(ETH_P_IPV6): |
3363 | /* XXX what about other V6 headers?? */ | |
3364 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
3365 | type_tucmd_mlhl |= | |
b4617240 | 3366 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
41825d71 | 3367 | break; |
41825d71 AK |
3368 | default: |
3369 | if (unlikely(net_ratelimit())) { | |
3370 | DPRINTK(PROBE, WARNING, | |
3371 | "partial checksum but proto=%x!\n", | |
3372 | skb->protocol); | |
3373 | } | |
3374 | break; | |
3375 | } | |
9a799d71 AK |
3376 | } |
3377 | ||
3378 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 3379 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
3380 | context_desc->mss_l4len_idx = 0; |
3381 | ||
3382 | tx_buffer_info->time_stamp = jiffies; | |
3383 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 3384 | |
9a799d71 AK |
3385 | adapter->hw_csum_tx_good++; |
3386 | i++; | |
3387 | if (i == tx_ring->count) | |
3388 | i = 0; | |
3389 | tx_ring->next_to_use = i; | |
3390 | ||
3391 | return true; | |
3392 | } | |
9f8cdf4f | 3393 | |
9a799d71 AK |
3394 | return false; |
3395 | } | |
3396 | ||
3397 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
b4617240 PW |
3398 | struct ixgbe_ring *tx_ring, |
3399 | struct sk_buff *skb, unsigned int first) | |
9a799d71 AK |
3400 | { |
3401 | struct ixgbe_tx_buffer *tx_buffer_info; | |
3402 | unsigned int len = skb->len; | |
3403 | unsigned int offset = 0, size, count = 0, i; | |
3404 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
3405 | unsigned int f; | |
3406 | ||
3407 | len -= skb->data_len; | |
3408 | ||
3409 | i = tx_ring->next_to_use; | |
3410 | ||
3411 | while (len) { | |
3412 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3413 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
3414 | ||
3415 | tx_buffer_info->length = size; | |
3416 | tx_buffer_info->dma = pci_map_single(adapter->pdev, | |
b4617240 PW |
3417 | skb->data + offset, |
3418 | size, PCI_DMA_TODEVICE); | |
9a799d71 AK |
3419 | tx_buffer_info->time_stamp = jiffies; |
3420 | tx_buffer_info->next_to_watch = i; | |
3421 | ||
3422 | len -= size; | |
3423 | offset += size; | |
3424 | count++; | |
3425 | i++; | |
3426 | if (i == tx_ring->count) | |
3427 | i = 0; | |
3428 | } | |
3429 | ||
3430 | for (f = 0; f < nr_frags; f++) { | |
3431 | struct skb_frag_struct *frag; | |
3432 | ||
3433 | frag = &skb_shinfo(skb)->frags[f]; | |
3434 | len = frag->size; | |
3435 | offset = frag->page_offset; | |
3436 | ||
3437 | while (len) { | |
3438 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3439 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
3440 | ||
3441 | tx_buffer_info->length = size; | |
3442 | tx_buffer_info->dma = pci_map_page(adapter->pdev, | |
b4617240 PW |
3443 | frag->page, |
3444 | offset, | |
3445 | size, | |
3446 | PCI_DMA_TODEVICE); | |
9a799d71 AK |
3447 | tx_buffer_info->time_stamp = jiffies; |
3448 | tx_buffer_info->next_to_watch = i; | |
3449 | ||
3450 | len -= size; | |
3451 | offset += size; | |
3452 | count++; | |
3453 | i++; | |
3454 | if (i == tx_ring->count) | |
3455 | i = 0; | |
3456 | } | |
3457 | } | |
3458 | if (i == 0) | |
3459 | i = tx_ring->count - 1; | |
3460 | else | |
3461 | i = i - 1; | |
3462 | tx_ring->tx_buffer_info[i].skb = skb; | |
3463 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
3464 | ||
3465 | return count; | |
3466 | } | |
3467 | ||
3468 | static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, | |
b4617240 PW |
3469 | struct ixgbe_ring *tx_ring, |
3470 | int tx_flags, int count, u32 paylen, u8 hdr_len) | |
9a799d71 AK |
3471 | { |
3472 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
3473 | struct ixgbe_tx_buffer *tx_buffer_info; | |
3474 | u32 olinfo_status = 0, cmd_type_len = 0; | |
3475 | unsigned int i; | |
3476 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
3477 | ||
3478 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
3479 | ||
3480 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
3481 | ||
3482 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
3483 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
3484 | ||
3485 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
3486 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
3487 | ||
3488 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 3489 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 3490 | |
4eeae6fd PW |
3491 | /* use index 1 context for tso */ |
3492 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
3493 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
3494 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
b4617240 | 3495 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
3496 | |
3497 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
3498 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 3499 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
3500 | |
3501 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); | |
3502 | ||
3503 | i = tx_ring->next_to_use; | |
3504 | while (count--) { | |
3505 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
3506 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); | |
3507 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); | |
3508 | tx_desc->read.cmd_type_len = | |
b4617240 | 3509 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 3510 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
3511 | i++; |
3512 | if (i == tx_ring->count) | |
3513 | i = 0; | |
3514 | } | |
3515 | ||
3516 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
3517 | ||
3518 | /* | |
3519 | * Force memory writes to complete before letting h/w | |
3520 | * know there are new descriptors to fetch. (Only | |
3521 | * applicable for weak-ordered memory model archs, | |
3522 | * such as IA-64). | |
3523 | */ | |
3524 | wmb(); | |
3525 | ||
3526 | tx_ring->next_to_use = i; | |
3527 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
3528 | } | |
3529 | ||
e092be60 | 3530 | static int __ixgbe_maybe_stop_tx(struct net_device *netdev, |
b4617240 | 3531 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
3532 | { |
3533 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3534 | ||
30eba97a | 3535 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
3536 | /* Herbert's original patch had: |
3537 | * smp_mb__after_netif_stop_queue(); | |
3538 | * but since that doesn't exist yet, just open code it. */ | |
3539 | smp_mb(); | |
3540 | ||
3541 | /* We need to check again in a case another CPU has just | |
3542 | * made room available. */ | |
3543 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
3544 | return -EBUSY; | |
3545 | ||
3546 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
af72166f | 3547 | netif_start_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
3548 | ++adapter->restart_queue; |
3549 | return 0; | |
3550 | } | |
3551 | ||
3552 | static int ixgbe_maybe_stop_tx(struct net_device *netdev, | |
b4617240 | 3553 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
3554 | { |
3555 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
3556 | return 0; | |
3557 | return __ixgbe_maybe_stop_tx(netdev, tx_ring, size); | |
3558 | } | |
3559 | ||
9a799d71 AK |
3560 | static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
3561 | { | |
3562 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3563 | struct ixgbe_ring *tx_ring; | |
9a799d71 AK |
3564 | unsigned int first; |
3565 | unsigned int tx_flags = 0; | |
30eba97a AV |
3566 | u8 hdr_len = 0; |
3567 | int r_idx = 0, tso; | |
9a799d71 AK |
3568 | int count = 0; |
3569 | unsigned int f; | |
9f8cdf4f | 3570 | |
30eba97a | 3571 | r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping; |
30eba97a | 3572 | tx_ring = &adapter->tx_ring[r_idx]; |
9a799d71 | 3573 | |
9f8cdf4f JB |
3574 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
3575 | tx_flags |= vlan_tx_tag_get(skb); | |
3576 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
3577 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 3578 | } |
9f8cdf4f JB |
3579 | /* three things can cause us to need a context descriptor */ |
3580 | if (skb_is_gso(skb) || | |
3581 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
3582 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) | |
9a799d71 AK |
3583 | count++; |
3584 | ||
9f8cdf4f JB |
3585 | count += TXD_USE_COUNT(skb_headlen(skb)); |
3586 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
3587 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
3588 | ||
e092be60 | 3589 | if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { |
9a799d71 | 3590 | adapter->tx_busy++; |
9a799d71 AK |
3591 | return NETDEV_TX_BUSY; |
3592 | } | |
9a799d71 | 3593 | |
8327d000 | 3594 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
3595 | tx_flags |= IXGBE_TX_FLAGS_IPV4; |
3596 | first = tx_ring->next_to_use; | |
3597 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
3598 | if (tso < 0) { | |
3599 | dev_kfree_skb_any(skb); | |
3600 | return NETDEV_TX_OK; | |
3601 | } | |
3602 | ||
3603 | if (tso) | |
3604 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
3605 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) && | |
b4617240 | 3606 | (skb->ip_summed == CHECKSUM_PARTIAL)) |
9a799d71 AK |
3607 | tx_flags |= IXGBE_TX_FLAGS_CSUM; |
3608 | ||
3609 | ixgbe_tx_queue(adapter, tx_ring, tx_flags, | |
b4617240 PW |
3610 | ixgbe_tx_map(adapter, tx_ring, skb, first), |
3611 | skb->len, hdr_len); | |
9a799d71 AK |
3612 | |
3613 | netdev->trans_start = jiffies; | |
3614 | ||
e092be60 | 3615 | ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED); |
9a799d71 AK |
3616 | |
3617 | return NETDEV_TX_OK; | |
3618 | } | |
3619 | ||
3620 | /** | |
3621 | * ixgbe_get_stats - Get System Network Statistics | |
3622 | * @netdev: network interface device structure | |
3623 | * | |
3624 | * Returns the address of the device statistics structure. | |
3625 | * The statistics are actually updated from the timer callback. | |
3626 | **/ | |
3627 | static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev) | |
3628 | { | |
3629 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3630 | ||
3631 | /* only return the current stats */ | |
3632 | return &adapter->net_stats; | |
3633 | } | |
3634 | ||
3635 | /** | |
3636 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
3637 | * @netdev: network interface device structure | |
3638 | * @p: pointer to an address structure | |
3639 | * | |
3640 | * Returns 0 on success, negative on failure | |
3641 | **/ | |
3642 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
3643 | { | |
3644 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 3645 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
3646 | struct sockaddr *addr = p; |
3647 | ||
3648 | if (!is_valid_ether_addr(addr->sa_data)) | |
3649 | return -EADDRNOTAVAIL; | |
3650 | ||
3651 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 3652 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 3653 | |
b4617240 | 3654 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
3655 | |
3656 | return 0; | |
3657 | } | |
3658 | ||
3659 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3660 | /* | |
3661 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
3662 | * without having to re-enable interrupts. It's not called while | |
3663 | * the interrupt routine is executing. | |
3664 | */ | |
3665 | static void ixgbe_netpoll(struct net_device *netdev) | |
3666 | { | |
3667 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3668 | ||
3669 | disable_irq(adapter->pdev->irq); | |
3670 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; | |
3671 | ixgbe_intr(adapter->pdev->irq, netdev); | |
3672 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; | |
3673 | enable_irq(adapter->pdev->irq); | |
3674 | } | |
3675 | #endif | |
3676 | ||
c44ade9e JB |
3677 | /** |
3678 | * ixgbe_link_config - set up initial link with default speed and duplex | |
3679 | * @hw: pointer to private hardware struct | |
3680 | * | |
3681 | * Returns 0 on success, negative on failure | |
3682 | **/ | |
3683 | static int ixgbe_link_config(struct ixgbe_hw *hw) | |
3684 | { | |
3685 | u32 autoneg = IXGBE_LINK_SPEED_10GB_FULL; | |
3686 | ||
3687 | /* must always autoneg for both 1G and 10G link */ | |
3688 | hw->mac.autoneg = true; | |
3689 | ||
3690 | return hw->mac.ops.setup_link_speed(hw, autoneg, true, true); | |
3691 | } | |
3692 | ||
9a799d71 AK |
3693 | /** |
3694 | * ixgbe_probe - Device Initialization Routine | |
3695 | * @pdev: PCI device information struct | |
3696 | * @ent: entry in ixgbe_pci_tbl | |
3697 | * | |
3698 | * Returns 0 on success, negative on failure | |
3699 | * | |
3700 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
3701 | * The OS initialization, configuring of the adapter private structure, | |
3702 | * and a hardware reset occur. | |
3703 | **/ | |
3704 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
b4617240 | 3705 | const struct pci_device_id *ent) |
9a799d71 AK |
3706 | { |
3707 | struct net_device *netdev; | |
3708 | struct ixgbe_adapter *adapter = NULL; | |
3709 | struct ixgbe_hw *hw; | |
3710 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
3711 | static int cards_found; |
3712 | int i, err, pci_using_dac; | |
3713 | u16 link_status, link_speed, link_width; | |
c44ade9e | 3714 | u32 part_num, eec; |
9a799d71 AK |
3715 | |
3716 | err = pci_enable_device(pdev); | |
3717 | if (err) | |
3718 | return err; | |
3719 | ||
3720 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) && | |
3721 | !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) { | |
3722 | pci_using_dac = 1; | |
3723 | } else { | |
3724 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
3725 | if (err) { | |
3726 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
3727 | if (err) { | |
b4617240 PW |
3728 | dev_err(&pdev->dev, "No usable DMA " |
3729 | "configuration, aborting\n"); | |
9a799d71 AK |
3730 | goto err_dma; |
3731 | } | |
3732 | } | |
3733 | pci_using_dac = 0; | |
3734 | } | |
3735 | ||
3736 | err = pci_request_regions(pdev, ixgbe_driver_name); | |
3737 | if (err) { | |
3738 | dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err); | |
3739 | goto err_pci_reg; | |
3740 | } | |
3741 | ||
3742 | pci_set_master(pdev); | |
fb3b27bc | 3743 | pci_save_state(pdev); |
9a799d71 | 3744 | |
30eba97a | 3745 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES); |
9a799d71 AK |
3746 | if (!netdev) { |
3747 | err = -ENOMEM; | |
3748 | goto err_alloc_etherdev; | |
3749 | } | |
3750 | ||
9a799d71 AK |
3751 | SET_NETDEV_DEV(netdev, &pdev->dev); |
3752 | ||
3753 | pci_set_drvdata(pdev, netdev); | |
3754 | adapter = netdev_priv(netdev); | |
3755 | ||
3756 | adapter->netdev = netdev; | |
3757 | adapter->pdev = pdev; | |
3758 | hw = &adapter->hw; | |
3759 | hw->back = adapter; | |
3760 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
3761 | ||
05857980 JK |
3762 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
3763 | pci_resource_len(pdev, 0)); | |
9a799d71 AK |
3764 | if (!hw->hw_addr) { |
3765 | err = -EIO; | |
3766 | goto err_ioremap; | |
3767 | } | |
3768 | ||
3769 | for (i = 1; i <= 5; i++) { | |
3770 | if (pci_resource_len(pdev, i) == 0) | |
3771 | continue; | |
3772 | } | |
3773 | ||
3774 | netdev->open = &ixgbe_open; | |
3775 | netdev->stop = &ixgbe_close; | |
3776 | netdev->hard_start_xmit = &ixgbe_xmit_frame; | |
3777 | netdev->get_stats = &ixgbe_get_stats; | |
2c5645cf CL |
3778 | netdev->set_rx_mode = &ixgbe_set_rx_mode; |
3779 | netdev->set_multicast_list = &ixgbe_set_rx_mode; | |
9a799d71 AK |
3780 | netdev->set_mac_address = &ixgbe_set_mac; |
3781 | netdev->change_mtu = &ixgbe_change_mtu; | |
3782 | ixgbe_set_ethtool_ops(netdev); | |
3783 | netdev->tx_timeout = &ixgbe_tx_timeout; | |
3784 | netdev->watchdog_timeo = 5 * HZ; | |
9a799d71 AK |
3785 | netdev->vlan_rx_register = ixgbe_vlan_rx_register; |
3786 | netdev->vlan_rx_add_vid = ixgbe_vlan_rx_add_vid; | |
3787 | netdev->vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid; | |
3788 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3789 | netdev->poll_controller = ixgbe_netpoll; | |
3790 | #endif | |
3791 | strcpy(netdev->name, pci_name(pdev)); | |
3792 | ||
9a799d71 AK |
3793 | adapter->bd_number = cards_found; |
3794 | ||
9a799d71 AK |
3795 | /* Setup hw api */ |
3796 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 3797 | hw->mac.type = ii->mac; |
9a799d71 | 3798 | |
c44ade9e JB |
3799 | /* EEPROM */ |
3800 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
3801 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
3802 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
3803 | if (!(eec & (1 << 8))) | |
3804 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
3805 | ||
3806 | /* PHY */ | |
3807 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
3808 | /* phy->sfp_type = ixgbe_sfp_type_unknown; */ | |
3809 | ||
9a799d71 AK |
3810 | err = ii->get_invariants(hw); |
3811 | if (err) | |
3812 | goto err_hw_init; | |
3813 | ||
3814 | /* setup the private structure */ | |
3815 | err = ixgbe_sw_init(adapter); | |
3816 | if (err) | |
3817 | goto err_sw_init; | |
3818 | ||
c44ade9e JB |
3819 | /* reset_hw fills in the perm_addr as well */ |
3820 | err = hw->mac.ops.reset_hw(hw); | |
3821 | if (err) { | |
3822 | dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err); | |
3823 | goto err_sw_init; | |
3824 | } | |
3825 | ||
9a799d71 | 3826 | netdev->features = NETIF_F_SG | |
b4617240 PW |
3827 | NETIF_F_IP_CSUM | |
3828 | NETIF_F_HW_VLAN_TX | | |
3829 | NETIF_F_HW_VLAN_RX | | |
3830 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 3831 | |
e9990a9c | 3832 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 3833 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 3834 | netdev->features |= NETIF_F_TSO6; |
e9990a9c | 3835 | netdev->features |= NETIF_F_LRO; |
ad31c402 JK |
3836 | |
3837 | netdev->vlan_features |= NETIF_F_TSO; | |
3838 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 3839 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
ad31c402 JK |
3840 | netdev->vlan_features |= NETIF_F_SG; |
3841 | ||
9a799d71 AK |
3842 | if (pci_using_dac) |
3843 | netdev->features |= NETIF_F_HIGHDMA; | |
3844 | ||
9a799d71 | 3845 | /* make sure the EEPROM is good */ |
c44ade9e | 3846 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
9a799d71 AK |
3847 | dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); |
3848 | err = -EIO; | |
3849 | goto err_eeprom; | |
3850 | } | |
3851 | ||
3852 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
3853 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
3854 | ||
c44ade9e JB |
3855 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
3856 | dev_err(&pdev->dev, "invalid MAC address\n"); | |
9a799d71 AK |
3857 | err = -EIO; |
3858 | goto err_eeprom; | |
3859 | } | |
3860 | ||
3861 | init_timer(&adapter->watchdog_timer); | |
3862 | adapter->watchdog_timer.function = &ixgbe_watchdog; | |
3863 | adapter->watchdog_timer.data = (unsigned long)adapter; | |
3864 | ||
3865 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 3866 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 3867 | |
021230d4 AV |
3868 | err = ixgbe_init_interrupt_scheme(adapter); |
3869 | if (err) | |
3870 | goto err_sw_init; | |
9a799d71 AK |
3871 | |
3872 | /* print bus type/speed/width info */ | |
3873 | pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status); | |
3874 | link_speed = link_status & IXGBE_PCI_LINK_SPEED; | |
3875 | link_width = link_status & IXGBE_PCI_LINK_WIDTH; | |
3876 | dev_info(&pdev->dev, "(PCI Express:%s:%s) " | |
b4617240 PW |
3877 | "%02x:%02x:%02x:%02x:%02x:%02x\n", |
3878 | ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" : | |
3879 | (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" : | |
3880 | "Unknown"), | |
3881 | ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" : | |
3882 | (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" : | |
3883 | (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" : | |
3884 | (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" : | |
3885 | "Unknown"), | |
3886 | netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2], | |
3887 | netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]); | |
c44ade9e | 3888 | ixgbe_read_pba_num_generic(hw, &part_num); |
9a799d71 | 3889 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", |
b4617240 PW |
3890 | hw->mac.type, hw->phy.type, |
3891 | (part_num >> 8), (part_num & 0xff)); | |
9a799d71 | 3892 | |
0c254d86 AK |
3893 | if (link_width <= IXGBE_PCI_LINK_WIDTH_4) { |
3894 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for " | |
b4617240 PW |
3895 | "this card is not sufficient for optimal " |
3896 | "performance.\n"); | |
0c254d86 | 3897 | dev_warn(&pdev->dev, "For optimal performance a x8 " |
b4617240 | 3898 | "PCI-Express slot is required.\n"); |
0c254d86 AK |
3899 | } |
3900 | ||
9a799d71 | 3901 | /* reset the hardware with the new settings */ |
c44ade9e JB |
3902 | hw->mac.ops.start_hw(hw); |
3903 | ||
3904 | /* link_config depends on start_hw being called at least once */ | |
3905 | err = ixgbe_link_config(hw); | |
3906 | if (err) { | |
3907 | dev_err(&pdev->dev, "setup_link_speed FAILED %d\n", err); | |
3908 | goto err_register; | |
3909 | } | |
9a799d71 AK |
3910 | |
3911 | netif_carrier_off(netdev); | |
fd2ea0a7 | 3912 | netif_tx_stop_all_queues(netdev); |
9a799d71 | 3913 | |
021230d4 AV |
3914 | ixgbe_napi_add_all(adapter); |
3915 | ||
9a799d71 AK |
3916 | strcpy(netdev->name, "eth%d"); |
3917 | err = register_netdev(netdev); | |
3918 | if (err) | |
3919 | goto err_register; | |
3920 | ||
5dd2d332 | 3921 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 3922 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd JC |
3923 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
3924 | /* always use CB2 mode, difference is masked | |
3925 | * in the CB driver */ | |
3926 | IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2); | |
3927 | ixgbe_setup_dca(adapter); | |
3928 | } | |
3929 | #endif | |
9a799d71 AK |
3930 | |
3931 | dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n"); | |
3932 | cards_found++; | |
3933 | return 0; | |
3934 | ||
3935 | err_register: | |
5eba3699 | 3936 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3937 | err_hw_init: |
3938 | err_sw_init: | |
021230d4 | 3939 | ixgbe_reset_interrupt_capability(adapter); |
9a799d71 AK |
3940 | err_eeprom: |
3941 | iounmap(hw->hw_addr); | |
3942 | err_ioremap: | |
3943 | free_netdev(netdev); | |
3944 | err_alloc_etherdev: | |
3945 | pci_release_regions(pdev); | |
3946 | err_pci_reg: | |
3947 | err_dma: | |
3948 | pci_disable_device(pdev); | |
3949 | return err; | |
3950 | } | |
3951 | ||
3952 | /** | |
3953 | * ixgbe_remove - Device Removal Routine | |
3954 | * @pdev: PCI device information struct | |
3955 | * | |
3956 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
3957 | * that it should release a PCI device. The could be caused by a | |
3958 | * Hot-Plug event, or because the driver is going to be removed from | |
3959 | * memory. | |
3960 | **/ | |
3961 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
3962 | { | |
3963 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3964 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3965 | ||
3966 | set_bit(__IXGBE_DOWN, &adapter->state); | |
3967 | del_timer_sync(&adapter->watchdog_timer); | |
3968 | ||
3969 | flush_scheduled_work(); | |
3970 | ||
5dd2d332 | 3971 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
3972 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
3973 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
3974 | dca_remove_requester(&pdev->dev); | |
3975 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
3976 | } | |
3977 | ||
3978 | #endif | |
9a799d71 AK |
3979 | unregister_netdev(netdev); |
3980 | ||
021230d4 | 3981 | ixgbe_reset_interrupt_capability(adapter); |
5eba3699 | 3982 | |
021230d4 | 3983 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
3984 | |
3985 | iounmap(adapter->hw.hw_addr); | |
3986 | pci_release_regions(pdev); | |
3987 | ||
021230d4 | 3988 | DPRINTK(PROBE, INFO, "complete\n"); |
b3c8b4ba | 3989 | ixgbe_napi_del_all(adapter); |
021230d4 AV |
3990 | kfree(adapter->tx_ring); |
3991 | kfree(adapter->rx_ring); | |
3992 | ||
9a799d71 AK |
3993 | free_netdev(netdev); |
3994 | ||
3995 | pci_disable_device(pdev); | |
3996 | } | |
3997 | ||
3998 | /** | |
3999 | * ixgbe_io_error_detected - called when PCI error is detected | |
4000 | * @pdev: Pointer to PCI device | |
4001 | * @state: The current pci connection state | |
4002 | * | |
4003 | * This function is called after a PCI bus error affecting | |
4004 | * this device has been detected. | |
4005 | */ | |
4006 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
b4617240 | 4007 | pci_channel_state_t state) |
9a799d71 AK |
4008 | { |
4009 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4010 | struct ixgbe_adapter *adapter = netdev->priv; | |
4011 | ||
4012 | netif_device_detach(netdev); | |
4013 | ||
4014 | if (netif_running(netdev)) | |
4015 | ixgbe_down(adapter); | |
4016 | pci_disable_device(pdev); | |
4017 | ||
b4617240 | 4018 | /* Request a slot reset. */ |
9a799d71 AK |
4019 | return PCI_ERS_RESULT_NEED_RESET; |
4020 | } | |
4021 | ||
4022 | /** | |
4023 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
4024 | * @pdev: Pointer to PCI device | |
4025 | * | |
4026 | * Restart the card from scratch, as if from a cold-boot. | |
4027 | */ | |
4028 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
4029 | { | |
4030 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4031 | struct ixgbe_adapter *adapter = netdev->priv; | |
4032 | ||
4033 | if (pci_enable_device(pdev)) { | |
4034 | DPRINTK(PROBE, ERR, | |
b4617240 | 4035 | "Cannot re-enable PCI device after reset.\n"); |
9a799d71 AK |
4036 | return PCI_ERS_RESULT_DISCONNECT; |
4037 | } | |
4038 | pci_set_master(pdev); | |
fb3b27bc | 4039 | pci_restore_state(pdev); |
9a799d71 AK |
4040 | |
4041 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
4042 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
4043 | ||
4044 | ixgbe_reset(adapter); | |
4045 | ||
4046 | return PCI_ERS_RESULT_RECOVERED; | |
4047 | } | |
4048 | ||
4049 | /** | |
4050 | * ixgbe_io_resume - called when traffic can start flowing again. | |
4051 | * @pdev: Pointer to PCI device | |
4052 | * | |
4053 | * This callback is called when the error recovery driver tells us that | |
4054 | * its OK to resume normal operation. | |
4055 | */ | |
4056 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
4057 | { | |
4058 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4059 | struct ixgbe_adapter *adapter = netdev->priv; | |
4060 | ||
4061 | if (netif_running(netdev)) { | |
4062 | if (ixgbe_up(adapter)) { | |
4063 | DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n"); | |
4064 | return; | |
4065 | } | |
4066 | } | |
4067 | ||
4068 | netif_device_attach(netdev); | |
9a799d71 AK |
4069 | } |
4070 | ||
4071 | static struct pci_error_handlers ixgbe_err_handler = { | |
4072 | .error_detected = ixgbe_io_error_detected, | |
4073 | .slot_reset = ixgbe_io_slot_reset, | |
4074 | .resume = ixgbe_io_resume, | |
4075 | }; | |
4076 | ||
4077 | static struct pci_driver ixgbe_driver = { | |
4078 | .name = ixgbe_driver_name, | |
4079 | .id_table = ixgbe_pci_tbl, | |
4080 | .probe = ixgbe_probe, | |
4081 | .remove = __devexit_p(ixgbe_remove), | |
4082 | #ifdef CONFIG_PM | |
4083 | .suspend = ixgbe_suspend, | |
4084 | .resume = ixgbe_resume, | |
4085 | #endif | |
4086 | .shutdown = ixgbe_shutdown, | |
4087 | .err_handler = &ixgbe_err_handler | |
4088 | }; | |
4089 | ||
4090 | /** | |
4091 | * ixgbe_init_module - Driver Registration Routine | |
4092 | * | |
4093 | * ixgbe_init_module is the first routine called when the driver is | |
4094 | * loaded. All it does is register with the PCI subsystem. | |
4095 | **/ | |
4096 | static int __init ixgbe_init_module(void) | |
4097 | { | |
4098 | int ret; | |
4099 | printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name, | |
4100 | ixgbe_driver_string, ixgbe_driver_version); | |
4101 | ||
4102 | printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright); | |
4103 | ||
5dd2d332 | 4104 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 4105 | dca_register_notify(&dca_notifier); |
bd0362dd | 4106 | #endif |
5dd2d332 | 4107 | |
9a799d71 AK |
4108 | ret = pci_register_driver(&ixgbe_driver); |
4109 | return ret; | |
4110 | } | |
b4617240 | 4111 | |
9a799d71 AK |
4112 | module_init(ixgbe_init_module); |
4113 | ||
4114 | /** | |
4115 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
4116 | * | |
4117 | * ixgbe_exit_module is called just before the driver is removed | |
4118 | * from memory. | |
4119 | **/ | |
4120 | static void __exit ixgbe_exit_module(void) | |
4121 | { | |
5dd2d332 | 4122 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
4123 | dca_unregister_notify(&dca_notifier); |
4124 | #endif | |
9a799d71 AK |
4125 | pci_unregister_driver(&ixgbe_driver); |
4126 | } | |
bd0362dd | 4127 | |
5dd2d332 | 4128 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 4129 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
b4617240 | 4130 | void *p) |
bd0362dd JC |
4131 | { |
4132 | int ret_val; | |
4133 | ||
4134 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
b4617240 | 4135 | __ixgbe_notify_dca); |
bd0362dd JC |
4136 | |
4137 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
4138 | } | |
5dd2d332 | 4139 | #endif /* CONFIG_IXGBE_DCA */ |
bd0362dd | 4140 | |
9a799d71 AK |
4141 | module_exit(ixgbe_exit_module); |
4142 | ||
4143 | /* ixgbe_main.c */ |