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ixgbe: Merge watchdog functionality into service task
[linux-block.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71 38#include <linux/ipv6.h>
5a0e3ad6 39#include <linux/slab.h>
9a799d71
AK		 40#include <net/checksum.h>
41#include <net/ip6_checksum.h>
42#include <linux/ethtool.h>
43#include <linux/if_vlan.h>
eacd73f7 44#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 45
46#include "ixgbe.h"
47#include "ixgbe_common.h"
ee5f784a 48#include "ixgbe_dcb_82599.h"
1cdd1ec8 49#include "ixgbe_sriov.h"
9a799d71
AK		 50
51char ixgbe_driver_name[] = "ixgbe";
9c8eb720 52static const char ixgbe_driver_string[] =
e8e9f696 53 "Intel(R) 10 Gigabit PCI Express Network Driver";
75e3d3c6 54#define MAJ 3
c89c7112
DS		 55#define MIN 3
56#define BUILD 8
75e3d3c6
JK		 57#define KFIX 2
58#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
59 __stringify(BUILD) "-k" __stringify(KFIX)
9c8eb720 60const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 61static const char ixgbe_copyright[] =
62 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 63
64static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 65 [board_82598] = &ixgbe_82598_info,
e8e26350 66 [board_82599] = &ixgbe_82599_info,
fe15e8e1 67 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 68};
69
70/* ixgbe_pci_tbl - PCI Device ID Table
71 *
72 * Wildcard entries (PCI_ANY_ID) should come last
73 * Last entry must be all 0s
74 *
75 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
76 * Class, Class Mask, private data (not used) }
77 */
a3aa1884 78static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
80 board_82598 },
9a799d71 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 82 board_82598 },
9a799d71 83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 84 board_82598 },
0befdb3e
JB		 85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
86 board_82598 },
3845bec0
PWJ		 87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
88 board_82598 },
9a799d71 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 90 board_82598 },
8d792cd9
JB		 91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
92 board_82598 },
c4900be0
DS		 93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
94 board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
96 board_82598 },
b95f5fcb
JB		 97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
98 board_82598 },
c4900be0
DS		 99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
100 board_82598 },
2f21bdd3
DS		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
102 board_82598 },
e8e26350
PW		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
104 board_82599 },
1fcf03e6
PWJ		 105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
106 board_82599 },
74757d49
DS		 107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
108 board_82599 },
e8e26350
PW		 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
110 board_82599 },
38ad1c8e
DS		 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
112 board_82599 },
dbfec662
DS		 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
114 board_82599 },
8911184f
PWJ		 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
116 board_82599 },
dbffcb21
DS		 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
118 board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
120 board_82599 },
119fc60a
MC		 121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
122 board_82599 },
312eb931
DS		 123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
124 board_82599 },
b93a2226 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
d994653d 126 board_X540 },
4c40ef02
ET		 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
128 board_82599 },
9a799d71
AK		 129
130 /* required last entry */
131 {0, }
132};
133MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
134
5dd2d332 135#ifdef CONFIG_IXGBE_DCA
bd0362dd 136static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 137 void *p);
bd0362dd
JC		 138static struct notifier_block dca_notifier = {
139 .notifier_call = ixgbe_notify_dca,
140 .next = NULL,
141 .priority = 0
142};
143#endif
144
1cdd1ec8
GR		 145#ifdef CONFIG_PCI_IOV
146static unsigned int max_vfs;
147module_param(max_vfs, uint, 0);
e8e9f696
JP		 148MODULE_PARM_DESC(max_vfs,
149 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 150#endif /* CONFIG_PCI_IOV */
151
9a799d71
AK		 152MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
153MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
154MODULE_LICENSE("GPL");
155MODULE_VERSION(DRV_VERSION);
156
157#define DEFAULT_DEBUG_LEVEL_SHIFT 3
158
1cdd1ec8
GR		 159static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
160{
161 struct ixgbe_hw *hw = &adapter->hw;
162 u32 gcr;
163 u32 gpie;
164 u32 vmdctl;
165
166#ifdef CONFIG_PCI_IOV
167 /* disable iov and allow time for transactions to clear */
168 pci_disable_sriov(adapter->pdev);
169#endif
170
171 /* turn off device IOV mode */
172 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
173 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
174 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
175 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
176 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
177 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
178
179 /* set default pool back to 0 */
180 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
181 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
182 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
183
184 /* take a breather then clean up driver data */
185 msleep(100);
e8e9f696
JP		 186
187 kfree(adapter->vfinfo);
1cdd1ec8
GR		 188 adapter->vfinfo = NULL;
189
190 adapter->num_vfs = 0;
191 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
192}
193
7086400d
AD		 194static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
195{
196 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
197 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
198 schedule_work(&adapter->service_task);
199}
200
201static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
202{
203 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
204
205 /* flush memory to make sure state is correct before next watchog */
206 smp_mb__before_clear_bit();
207 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
208}
209
dcd79aeb
TI		 210struct ixgbe_reg_info {
211 u32 ofs;
212 char *name;
213};
214
215static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
216
217 /* General Registers */
218 {IXGBE_CTRL, "CTRL"},
219 {IXGBE_STATUS, "STATUS"},
220 {IXGBE_CTRL_EXT, "CTRL_EXT"},
221
222 /* Interrupt Registers */
223 {IXGBE_EICR, "EICR"},
224
225 /* RX Registers */
226 {IXGBE_SRRCTL(0), "SRRCTL"},
227 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
228 {IXGBE_RDLEN(0), "RDLEN"},
229 {IXGBE_RDH(0), "RDH"},
230 {IXGBE_RDT(0), "RDT"},
231 {IXGBE_RXDCTL(0), "RXDCTL"},
232 {IXGBE_RDBAL(0), "RDBAL"},
233 {IXGBE_RDBAH(0), "RDBAH"},
234
235 /* TX Registers */
236 {IXGBE_TDBAL(0), "TDBAL"},
237 {IXGBE_TDBAH(0), "TDBAH"},
238 {IXGBE_TDLEN(0), "TDLEN"},
239 {IXGBE_TDH(0), "TDH"},
240 {IXGBE_TDT(0), "TDT"},
241 {IXGBE_TXDCTL(0), "TXDCTL"},
242
243 /* List Terminator */
244 {}
245};
246
247
248/*
249 * ixgbe_regdump - register printout routine
250 */
251static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
252{
253 int i = 0, j = 0;
254 char rname[16];
255 u32 regs[64];
256
257 switch (reginfo->ofs) {
258 case IXGBE_SRRCTL(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
261 break;
262 case IXGBE_DCA_RXCTRL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
265 break;
266 case IXGBE_RDLEN(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
269 break;
270 case IXGBE_RDH(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
273 break;
274 case IXGBE_RDT(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
277 break;
278 case IXGBE_RXDCTL(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
281 break;
282 case IXGBE_RDBAL(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
285 break;
286 case IXGBE_RDBAH(0):
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
289 break;
290 case IXGBE_TDBAL(0):
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
293 break;
294 case IXGBE_TDBAH(0):
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
297 break;
298 case IXGBE_TDLEN(0):
299 for (i = 0; i < 64; i++)
300 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
301 break;
302 case IXGBE_TDH(0):
303 for (i = 0; i < 64; i++)
304 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
305 break;
306 case IXGBE_TDT(0):
307 for (i = 0; i < 64; i++)
308 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
309 break;
310 case IXGBE_TXDCTL(0):
311 for (i = 0; i < 64; i++)
312 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
313 break;
314 default:
c7689578 315 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 316 IXGBE_READ_REG(hw, reginfo->ofs));
317 return;
318 }
319
320 for (i = 0; i < 8; i++) {
321 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 322 pr_err("%-15s", rname);
dcd79aeb 323 for (j = 0; j < 8; j++)
c7689578
JP		 324 pr_cont(" %08x", regs[i*8+j]);
325 pr_cont("\n");
dcd79aeb
TI		 326 }
327
328}
329
330/*
331 * ixgbe_dump - Print registers, tx-rings and rx-rings
332 */
333static void ixgbe_dump(struct ixgbe_adapter *adapter)
334{
335 struct net_device *netdev = adapter->netdev;
336 struct ixgbe_hw *hw = &adapter->hw;
337 struct ixgbe_reg_info *reginfo;
338 int n = 0;
339 struct ixgbe_ring *tx_ring;
340 struct ixgbe_tx_buffer *tx_buffer_info;
341 union ixgbe_adv_tx_desc *tx_desc;
342 struct my_u0 { u64 a; u64 b; } *u0;
343 struct ixgbe_ring *rx_ring;
344 union ixgbe_adv_rx_desc *rx_desc;
345 struct ixgbe_rx_buffer *rx_buffer_info;
346 u32 staterr;
347 int i = 0;
348
349 if (!netif_msg_hw(adapter))
350 return;
351
352 /* Print netdevice Info */
353 if (netdev) {
354 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 355 pr_info("Device Name state "
dcd79aeb 356 "trans_start last_rx\n");
c7689578
JP		 357 pr_info("%-15s %016lX %016lX %016lX\n",
358 netdev->name,
359 netdev->state,
360 netdev->trans_start,
361 netdev->last_rx);
dcd79aeb
TI		 362 }
363
364 /* Print Registers */
365 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 366 pr_info(" Register Name Value\n");
dcd79aeb
TI		 367 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
368 reginfo->name; reginfo++) {
369 ixgbe_regdump(hw, reginfo);
370 }
371
372 /* Print TX Ring Summary */
373 if (!netdev || !netif_running(netdev))
374 goto exit;
375
376 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 377 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 378 for (n = 0; n < adapter->num_tx_queues; n++) {
379 tx_ring = adapter->tx_ring[n];
380 tx_buffer_info =
381 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
c7689578 382 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
dcd79aeb
TI		 383 n, tx_ring->next_to_use, tx_ring->next_to_clean,
384 (u64)tx_buffer_info->dma,
385 tx_buffer_info->length,
386 tx_buffer_info->next_to_watch,
387 (u64)tx_buffer_info->time_stamp);
388 }
389
390 /* Print TX Rings */
391 if (!netif_msg_tx_done(adapter))
392 goto rx_ring_summary;
393
394 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
395
396 /* Transmit Descriptor Formats
397 *
398 * Advanced Transmit Descriptor
399 * +--------------------------------------------------------------+
400 * 0 | Buffer Address [63:0] |
401 * +--------------------------------------------------------------+
402 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
403 * +--------------------------------------------------------------+
404 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
405 */
406
407 for (n = 0; n < adapter->num_tx_queues; n++) {
408 tx_ring = adapter->tx_ring[n];
c7689578
JP		 409 pr_info("------------------------------------\n");
410 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
411 pr_info("------------------------------------\n");
412 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 413 "[PlPOIdStDDt Ln] [bi->dma ] "
414 "leng ntw timestamp bi->skb\n");
415
416 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 417 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 418 tx_buffer_info = &tx_ring->tx_buffer_info[i];
419 u0 = (struct my_u0 *)tx_desc;
c7689578 420 pr_info("T [0x%03X] %016llX %016llX %016llX"
dcd79aeb
TI		 421 " %04X %3X %016llX %p", i,
422 le64_to_cpu(u0->a),
423 le64_to_cpu(u0->b),
424 (u64)tx_buffer_info->dma,
425 tx_buffer_info->length,
426 tx_buffer_info->next_to_watch,
427 (u64)tx_buffer_info->time_stamp,
428 tx_buffer_info->skb);
429 if (i == tx_ring->next_to_use &&
430 i == tx_ring->next_to_clean)
c7689578 431 pr_cont(" NTC/U\n");
dcd79aeb 432 else if (i == tx_ring->next_to_use)
c7689578 433 pr_cont(" NTU\n");
dcd79aeb 434 else if (i == tx_ring->next_to_clean)
c7689578 435 pr_cont(" NTC\n");
dcd79aeb 436 else
c7689578 437 pr_cont("\n");
dcd79aeb
TI		 438
439 if (netif_msg_pktdata(adapter) &&
440 tx_buffer_info->dma != 0)
441 print_hex_dump(KERN_INFO, "",
442 DUMP_PREFIX_ADDRESS, 16, 1,
443 phys_to_virt(tx_buffer_info->dma),
444 tx_buffer_info->length, true);
445 }
446 }
447
448 /* Print RX Rings Summary */
449rx_ring_summary:
450 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 451 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 452 for (n = 0; n < adapter->num_rx_queues; n++) {
453 rx_ring = adapter->rx_ring[n];
c7689578
JP		 454 pr_info("%5d %5X %5X\n",
455 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 456 }
457
458 /* Print RX Rings */
459 if (!netif_msg_rx_status(adapter))
460 goto exit;
461
462 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
463
464 /* Advanced Receive Descriptor (Read) Format
465 * 63 1 0
466 * +-----------------------------------------------------+
467 * 0 | Packet Buffer Address [63:1] |A0/NSE|
468 * +----------------------------------------------+------+
469 * 8 | Header Buffer Address [63:1] | DD |
470 * +-----------------------------------------------------+
471 *
472 *
473 * Advanced Receive Descriptor (Write-Back) Format
474 *
475 * 63 48 47 32 31 30 21 20 16 15 4 3 0
476 * +------------------------------------------------------+
477 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
478 * | Checksum Ident | | | | Type | Type |
479 * +------------------------------------------------------+
480 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
481 * +------------------------------------------------------+
482 * 63 48 47 32 31 20 19 0
483 */
484 for (n = 0; n < adapter->num_rx_queues; n++) {
485 rx_ring = adapter->rx_ring[n];
c7689578
JP		 486 pr_info("------------------------------------\n");
487 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
488 pr_info("------------------------------------\n");
489 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 490 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
491 "<-- Adv Rx Read format\n");
c7689578 492 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 493 "[vl er S cks ln] ---------------- [bi->skb] "
494 "<-- Adv Rx Write-Back format\n");
495
496 for (i = 0; i < rx_ring->count; i++) {
497 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 498 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 499 u0 = (struct my_u0 *)rx_desc;
500 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
501 if (staterr & IXGBE_RXD_STAT_DD) {
502 /* Descriptor Done */
c7689578 503 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 504 "%016llX ---------------- %p", i,
505 le64_to_cpu(u0->a),
506 le64_to_cpu(u0->b),
507 rx_buffer_info->skb);
508 } else {
c7689578 509 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 510 "%016llX %016llX %p", i,
511 le64_to_cpu(u0->a),
512 le64_to_cpu(u0->b),
513 (u64)rx_buffer_info->dma,
514 rx_buffer_info->skb);
515
516 if (netif_msg_pktdata(adapter)) {
517 print_hex_dump(KERN_INFO, "",
518 DUMP_PREFIX_ADDRESS, 16, 1,
519 phys_to_virt(rx_buffer_info->dma),
520 rx_ring->rx_buf_len, true);
521
522 if (rx_ring->rx_buf_len
523 < IXGBE_RXBUFFER_2048)
524 print_hex_dump(KERN_INFO, "",
525 DUMP_PREFIX_ADDRESS, 16, 1,
526 phys_to_virt(
527 rx_buffer_info->page_dma +
528 rx_buffer_info->page_offset
529 ),
530 PAGE_SIZE/2, true);
531 }
532 }
533
534 if (i == rx_ring->next_to_use)
c7689578 535 pr_cont(" NTU\n");
dcd79aeb 536 else if (i == rx_ring->next_to_clean)
c7689578 537 pr_cont(" NTC\n");
dcd79aeb 538 else
c7689578 539 pr_cont("\n");
dcd79aeb
TI		 540
541 }
542 }
543
544exit:
545 return;
546}
547
5eba3699
AV		 548static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
549{
550 u32 ctrl_ext;
551
552 /* Let firmware take over control of h/w */
553 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
554 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 555 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 556}
557
558static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
559{
560 u32 ctrl_ext;
561
562 /* Let firmware know the driver has taken over */
563 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
564 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 565 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 566}
9a799d71 567
e8e26350
PW		 568/*
569 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
570 * @adapter: pointer to adapter struct
571 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
572 * @queue: queue to map the corresponding interrupt to
573 * @msix_vector: the vector to map to the corresponding queue
574 *
575 */
576static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 577 u8 queue, u8 msix_vector)
9a799d71
AK		 578{
579 u32 ivar, index;
e8e26350
PW		 580 struct ixgbe_hw *hw = &adapter->hw;
581 switch (hw->mac.type) {
582 case ixgbe_mac_82598EB:
583 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
584 if (direction == -1)
585 direction = 0;
586 index = (((direction * 64) + queue) >> 2) & 0x1F;
587 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
588 ivar &= ~(0xFF << (8 * (queue & 0x3)));
589 ivar |= (msix_vector << (8 * (queue & 0x3)));
590 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
591 break;
592 case ixgbe_mac_82599EB:
b93a2226 593 case ixgbe_mac_X540:
e8e26350
PW		 594 if (direction == -1) {
595 /* other causes */
596 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
597 index = ((queue & 1) * 8);
598 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
599 ivar &= ~(0xFF << index);
600 ivar |= (msix_vector << index);
601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
602 break;
603 } else {
604 /* tx or rx causes */
605 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
606 index = ((16 * (queue & 1)) + (8 * direction));
607 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
608 ivar &= ~(0xFF << index);
609 ivar |= (msix_vector << index);
610 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
611 break;
612 }
613 default:
614 break;
615 }
9a799d71
AK		 616}
617
fe49f04a 618static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 619 u64 qmask)
fe49f04a
AD		 620{
621 u32 mask;
622
bd508178
AD		 623 switch (adapter->hw.mac.type) {
624 case ixgbe_mac_82598EB:
fe49f04a
AD		 625 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
626 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 627 break;
628 case ixgbe_mac_82599EB:
b93a2226 629 case ixgbe_mac_X540:
fe49f04a
AD		 630 mask = (qmask & 0xFFFFFFFF);
631 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
632 mask = (qmask >> 32);
633 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 634 break;
635 default:
636 break;
fe49f04a
AD		 637 }
638}
639
b6ec895e
AD		 640void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
641 struct ixgbe_tx_buffer *tx_buffer_info)
9a799d71 642{
e5a43549
AD		 643 if (tx_buffer_info->dma) {
644 if (tx_buffer_info->mapped_as_page)
b6ec895e 645 dma_unmap_page(tx_ring->dev,
e5a43549
AD		 646 tx_buffer_info->dma,
647 tx_buffer_info->length,
1b507730 648 DMA_TO_DEVICE);
e5a43549 649 else
b6ec895e 650 dma_unmap_single(tx_ring->dev,
e5a43549
AD		 651 tx_buffer_info->dma,
652 tx_buffer_info->length,
1b507730 653 DMA_TO_DEVICE);
e5a43549
AD		 654 tx_buffer_info->dma = 0;
655 }
9a799d71
AK		 656 if (tx_buffer_info->skb) {
657 dev_kfree_skb_any(tx_buffer_info->skb);
658 tx_buffer_info->skb = NULL;
659 }
44df32c5 660 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 661 /* tx_buffer_info must be completely set up in the transmit path */
662}
663
26f23d82 664/**
c84d324c
JF		 665 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
666 * @adapter: driver private struct
667 * @index: reg idx of queue to query (0-127)
26f23d82 668 *
25985edc 669 * Helper function to determine the traffic index for a particular
c84d324c 670 * register index.
26f23d82 671 *
c84d324c 672 * Returns : a tc index for use in range 0-7, or 0-3
26f23d82 673 */
3b2ee943 674static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
26f23d82 675{
c84d324c 676 int tc = -1;
e5b64635 677 int dcb_i = netdev_get_num_tc(adapter->netdev);
26f23d82 678
c84d324c
JF		 679 /* if DCB is not enabled the queues have no TC */
680 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
681 return tc;
26f23d82 682
c84d324c
JF		 683 /* check valid range */
684 if (reg_idx >= adapter->hw.mac.max_tx_queues)
685 return tc;
686
687 switch (adapter->hw.mac.type) {
688 case ixgbe_mac_82598EB:
689 tc = reg_idx >> 2;
690 break;
691 default:
692 if (dcb_i != 4 && dcb_i != 8)
6837e895 693 break;
c84d324c
JF		 694
695 /* if VMDq is enabled the lowest order bits determine TC */
696 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
697 IXGBE_FLAG_VMDQ_ENABLED)) {
698 tc = reg_idx & (dcb_i - 1);
699 break;
700 }
701
702 /*
703 * Convert the reg_idx into the correct TC. This bitmask
704 * targets the last full 32 ring traffic class and assigns
705 * it a value of 1. From there the rest of the rings are
706 * based on shifting the mask further up to include the
707 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
708 * will only ever be 8 or 4 and that reg_idx will never
709 * be greater then 128. The code without the power of 2
710 * optimizations would be:
711 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
712 */
713 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
714 tc >>= 9 - (reg_idx >> 5);
715 }
716
717 return tc;
718}
719
720static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
721{
722 struct ixgbe_hw *hw = &adapter->hw;
723 struct ixgbe_hw_stats *hwstats = &adapter->stats;
724 u32 data = 0;
725 u32 xoff[8] = {0};
726 int i;
727
728 if ((hw->fc.current_mode == ixgbe_fc_full) ||
729 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
730 switch (hw->mac.type) {
731 case ixgbe_mac_82598EB:
732 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 733 break;
734 default:
c84d324c
JF		 735 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
736 }
737 hwstats->lxoffrxc += data;
738
739 /* refill credits (no tx hang) if we received xoff */
740 if (!data)
741 return;
742
743 for (i = 0; i < adapter->num_tx_queues; i++)
744 clear_bit(__IXGBE_HANG_CHECK_ARMED,
745 &adapter->tx_ring[i]->state);
746 return;
747 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
748 return;
749
750 /* update stats for each tc, only valid with PFC enabled */
751 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
752 switch (hw->mac.type) {
753 case ixgbe_mac_82598EB:
754 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 755 break;
c84d324c
JF		 756 default:
757 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 758 }
c84d324c
JF		 759 hwstats->pxoffrxc[i] += xoff[i];
760 }
761
762 /* disarm tx queues that have received xoff frames */
763 for (i = 0; i < adapter->num_tx_queues; i++) {
764 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
765 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
766
767 if (xoff[tc])
768 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 769 }
26f23d82
YZ		 770}
771
c84d324c 772static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 773{
c84d324c
JF		 774 return ring->tx_stats.completed;
775}
776
777static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
778{
779 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 780 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 781
c84d324c
JF		 782 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
783 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
784
785 if (head != tail)
786 return (head < tail) ?
787 tail - head : (tail + ring->count - head);
788
789 return 0;
790}
791
792static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
793{
794 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
795 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
796 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
797 bool ret = false;
798
7d637bcc 799 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 800
801 /*
802 * Check for a hung queue, but be thorough. This verifies
803 * that a transmit has been completed since the previous
804 * check AND there is at least one packet pending. The
805 * ARMED bit is set to indicate a potential hang. The
806 * bit is cleared if a pause frame is received to remove
807 * false hang detection due to PFC or 802.3x frames. By
808 * requiring this to fail twice we avoid races with
809 * pfc clearing the ARMED bit and conditions where we
810 * run the check_tx_hang logic with a transmit completion
811 * pending but without time to complete it yet.
812 */
813 if ((tx_done_old == tx_done) && tx_pending) {
814 /* make sure it is true for two checks in a row */
815 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
816 &tx_ring->state);
817 } else {
818 /* update completed stats and continue */
819 tx_ring->tx_stats.tx_done_old = tx_done;
820 /* reset the countdown */
821 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 822 }
823
c84d324c 824 return ret;
9a799d71
AK		 825}
826
b4617240
PW		 827#define IXGBE_MAX_TXD_PWR 14
828#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 829
830/* Tx Descriptors needed, worst case */
831#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
832 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
833#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 834 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 835
e01c31a5
JB		 836static void ixgbe_tx_timeout(struct net_device *netdev);
837
9a799d71
AK		 838/**
839 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 840 * @q_vector: structure containing interrupt and ring information
e01c31a5 841 * @tx_ring: tx ring to clean
9a799d71 842 **/
fe49f04a 843static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 844 struct ixgbe_ring *tx_ring)
9a799d71 845{
fe49f04a 846 struct ixgbe_adapter *adapter = q_vector->adapter;
12207e49
PWJ		 847 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
848 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5 849 unsigned int total_bytes = 0, total_packets = 0;
b953799e 850 u16 i, eop, count = 0;
9a799d71
AK		 851
852 i = tx_ring->next_to_clean;
12207e49 853 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 854 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 855
856 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 857 (count < tx_ring->work_limit)) {
12207e49 858 bool cleaned = false;
2d0bb1c1 859 rmb(); /* read buffer_info after eop_desc */
12207e49 860 for ( ; !cleaned; count++) {
31f05a2d 861 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71 862 tx_buffer_info = &tx_ring->tx_buffer_info[i];
8ad494b0
AD		 863
864 tx_desc->wb.status = 0;
12207e49 865 cleaned = (i == eop);
9a799d71 866
8ad494b0
AD		 867 i++;
868 if (i == tx_ring->count)
869 i = 0;
e01c31a5 870
8ad494b0
AD		 871 if (cleaned && tx_buffer_info->skb) {
872 total_bytes += tx_buffer_info->bytecount;
873 total_packets += tx_buffer_info->gso_segs;
e092be60 874 }
e01c31a5 875
b6ec895e 876 ixgbe_unmap_and_free_tx_resource(tx_ring,
e8e9f696 877 tx_buffer_info);
e01c31a5 878 }
12207e49 879
c84d324c 880 tx_ring->tx_stats.completed++;
12207e49 881 eop = tx_ring->tx_buffer_info[i].next_to_watch;
31f05a2d 882 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
12207e49
PWJ		 883 }
884
9a799d71 885 tx_ring->next_to_clean = i;
b953799e
AD		 886 tx_ring->total_bytes += total_bytes;
887 tx_ring->total_packets += total_packets;
888 u64_stats_update_begin(&tx_ring->syncp);
889 tx_ring->stats.packets += total_packets;
890 tx_ring->stats.bytes += total_bytes;
891 u64_stats_update_end(&tx_ring->syncp);
892
c84d324c
JF		 893 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
894 /* schedule immediate reset if we believe we hung */
895 struct ixgbe_hw *hw = &adapter->hw;
896 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
897 e_err(drv, "Detected Tx Unit Hang\n"
898 " Tx Queue <%d>\n"
899 " TDH, TDT <%x>, <%x>\n"
900 " next_to_use <%x>\n"
901 " next_to_clean <%x>\n"
902 "tx_buffer_info[next_to_clean]\n"
903 " time_stamp <%lx>\n"
904 " jiffies <%lx>\n",
905 tx_ring->queue_index,
906 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
907 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
908 tx_ring->next_to_use, eop,
909 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
910
911 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
912
913 e_info(probe,
914 "tx hang %d detected on queue %d, resetting adapter\n",
915 adapter->tx_timeout_count + 1, tx_ring->queue_index);
916
b953799e 917 /* schedule immediate reset if we believe we hung */
b953799e
AD		 918 ixgbe_tx_timeout(adapter->netdev);
919
920 /* the adapter is about to reset, no point in enabling stuff */
921 return true;
922 }
9a799d71 923
e092be60 924#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
fc77dc3c 925 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
e8e9f696 926 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 927 /* Make sure that anybody stopping the queue after this
928 * sees the new next_to_clean.
929 */
930 smp_mb();
fc77dc3c 931 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 932 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 933 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 934 ++tx_ring->tx_stats.restart_queue;
30eba97a 935 }
e092be60 936 }
9a799d71 937
807540ba 938 return count < tx_ring->work_limit;
9a799d71
AK		 939}
940
5dd2d332 941#ifdef CONFIG_IXGBE_DCA
bd0362dd 942static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 943 struct ixgbe_ring *rx_ring,
944 int cpu)
bd0362dd 945{
33cf09c9 946 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 947 u32 rxctrl;
33cf09c9
AD		 948 u8 reg_idx = rx_ring->reg_idx;
949
950 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
951 switch (hw->mac.type) {
952 case ixgbe_mac_82598EB:
953 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
954 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
955 break;
956 case ixgbe_mac_82599EB:
b93a2226 957 case ixgbe_mac_X540:
33cf09c9
AD		 958 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
959 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
960 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
961 break;
962 default:
963 break;
bd0362dd 964 }
33cf09c9
AD		 965 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
966 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
967 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 968 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 969}
970
971static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 972 struct ixgbe_ring *tx_ring,
973 int cpu)
bd0362dd 974{
33cf09c9 975 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 976 u32 txctrl;
33cf09c9
AD		 977 u8 reg_idx = tx_ring->reg_idx;
978
979 switch (hw->mac.type) {
980 case ixgbe_mac_82598EB:
981 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
982 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
983 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
984 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 985 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
986 break;
987 case ixgbe_mac_82599EB:
b93a2226 988 case ixgbe_mac_X540:
33cf09c9
AD		 989 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
990 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
991 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
992 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
993 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 994 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
995 break;
996 default:
997 break;
998 }
999}
1000
1001static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1002{
1003 struct ixgbe_adapter *adapter = q_vector->adapter;
bd0362dd 1004 int cpu = get_cpu();
33cf09c9
AD		 1005 long r_idx;
1006 int i;
bd0362dd 1007
33cf09c9
AD		 1008 if (q_vector->cpu == cpu)
1009 goto out_no_update;
1010
1011 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1012 for (i = 0; i < q_vector->txr_count; i++) {
1013 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
1014 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1015 r_idx + 1);
bd0362dd 1016 }
33cf09c9
AD		 1017
1018 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1019 for (i = 0; i < q_vector->rxr_count; i++) {
1020 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1021 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1022 r_idx + 1);
1023 }
1024
1025 q_vector->cpu = cpu;
1026out_no_update:
bd0362dd
JC		 1027 put_cpu();
1028}
1029
1030static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1031{
33cf09c9 1032 int num_q_vectors;
bd0362dd
JC		 1033 int i;
1034
1035 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1036 return;
1037
e35ec126
AD		 1038 /* always use CB2 mode, difference is masked in the CB driver */
1039 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1040
33cf09c9
AD		 1041 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1042 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1043 else
1044 num_q_vectors = 1;
1045
1046 for (i = 0; i < num_q_vectors; i++) {
1047 adapter->q_vector[i]->cpu = -1;
1048 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1049 }
1050}
1051
1052static int __ixgbe_notify_dca(struct device *dev, void *data)
1053{
c60fbb00 1054 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1055 unsigned long event = *(unsigned long *)data;
1056
33cf09c9
AD		 1057 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1058 return 0;
1059
bd0362dd
JC		 1060 switch (event) {
1061 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1062 /* if we're already enabled, don't do it again */
1063 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1064 break;
652f093f 1065 if (dca_add_requester(dev) == 0) {
96b0e0f6 1066 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1067 ixgbe_setup_dca(adapter);
1068 break;
1069 }
1070 /* Fall Through since DCA is disabled. */
1071 case DCA_PROVIDER_REMOVE:
1072 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1073 dca_remove_requester(dev);
1074 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1075 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1076 }
1077 break;
1078 }
1079
652f093f 1080 return 0;
bd0362dd 1081}
5dd2d332 1082#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 1083
1084static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1085 struct sk_buff *skb)
1086{
1087 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1088}
1089
9a799d71
AK		 1090/**
1091 * ixgbe_receive_skb - Send a completed packet up the stack
1092 * @adapter: board private structure
1093 * @skb: packet to send up
177db6ff
MC		 1094 * @status: hardware indication of status of receive
1095 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1096 * @rx_desc: rx descriptor
9a799d71 1097 **/
78b6f4ce 1098static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1099 struct sk_buff *skb, u8 status,
1100 struct ixgbe_ring *ring,
1101 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1102{
78b6f4ce
HX		 1103 struct ixgbe_adapter *adapter = q_vector->adapter;
1104 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1105 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1106 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1107
f62bbb5e
JG		 1108 if (is_vlan && (tag & VLAN_VID_MASK))
1109 __vlan_hwaccel_put_tag(skb, tag);
1110
1111 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1112 napi_gro_receive(napi, skb);
1113 else
1114 netif_rx(skb);
9a799d71
AK		 1115}
1116
e59bd25d
AV		 1117/**
1118 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1119 * @adapter: address of board private structure
1120 * @status_err: hardware indication of status of receive
1121 * @skb: skb currently being received and modified
1122 **/
9a799d71 1123static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 1124 union ixgbe_adv_rx_desc *rx_desc,
1125 struct sk_buff *skb)
9a799d71 1126{
8bae1b2b
DS		 1127 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1128
bc8acf2c 1129 skb_checksum_none_assert(skb);
9a799d71 1130
712744be
JB		 1131 /* Rx csum disabled */
1132 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1133 return;
e59bd25d
AV		 1134
1135 /* if IP and error */
1136 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1137 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1138 adapter->hw_csum_rx_error++;
1139 return;
1140 }
e59bd25d
AV		 1141
1142 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1143 return;
1144
1145 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1146 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1147
1148 /*
1149 * 82599 errata, UDP frames with a 0 checksum can be marked as
1150 * checksum errors.
1151 */
1152 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1153 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1154 return;
1155
e59bd25d
AV		 1156 adapter->hw_csum_rx_error++;
1157 return;
1158 }
1159
9a799d71 1160 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1161 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1162}
1163
84ea2591 1164static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1165{
1166 /*
1167 * Force memory writes to complete before letting h/w
1168 * know there are new descriptors to fetch. (Only
1169 * applicable for weak-ordered memory model archs,
1170 * such as IA-64).
1171 */
1172 wmb();
84ea2591 1173 writel(val, rx_ring->tail);
e8e26350
PW		 1174}
1175
9a799d71
AK		 1176/**
1177 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1178 * @rx_ring: ring to place buffers on
1179 * @cleaned_count: number of buffers to replace
9a799d71 1180 **/
fc77dc3c 1181void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1182{
9a799d71 1183 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1184 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1185 struct sk_buff *skb;
1186 u16 i = rx_ring->next_to_use;
9a799d71 1187
fc77dc3c
AD		 1188 /* do nothing if no valid netdev defined */
1189 if (!rx_ring->netdev)
1190 return;
1191
9a799d71 1192 while (cleaned_count--) {
31f05a2d 1193 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1194 bi = &rx_ring->rx_buffer_info[i];
1195 skb = bi->skb;
9a799d71 1196
d5f398ed 1197 if (!skb) {
fc77dc3c 1198 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1199 rx_ring->rx_buf_len);
9a799d71 1200 if (!skb) {
5b7da515 1201 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1202 goto no_buffers;
1203 }
d716a7d8
AD		 1204 /* initialize queue mapping */
1205 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1206 bi->skb = skb;
d716a7d8 1207 }
9a799d71 1208
d716a7d8 1209 if (!bi->dma) {
b6ec895e 1210 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1211 skb->data,
e8e9f696 1212 rx_ring->rx_buf_len,
1b507730 1213 DMA_FROM_DEVICE);
b6ec895e 1214 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1215 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1216 bi->dma = 0;
1217 goto no_buffers;
1218 }
9a799d71 1219 }
d5f398ed 1220
7d637bcc 1221 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1222 if (!bi->page) {
fc77dc3c 1223 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1224 if (!bi->page) {
5b7da515 1225 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1226 goto no_buffers;
1227 }
1228 }
1229
1230 if (!bi->page_dma) {
1231 /* use a half page if we're re-using */
1232 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1233 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1234 bi->page,
1235 bi->page_offset,
1236 PAGE_SIZE / 2,
1237 DMA_FROM_DEVICE);
b6ec895e 1238 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1239 bi->page_dma)) {
5b7da515 1240 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1241 bi->page_dma = 0;
1242 goto no_buffers;
1243 }
1244 }
1245
1246 /* Refresh the desc even if buffer_addrs didn't change
1247 * because each write-back erases this info. */
3a581073
JB		 1248 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1249 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1250 } else {
3a581073 1251 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1252 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1253 }
1254
1255 i++;
1256 if (i == rx_ring->count)
1257 i = 0;
9a799d71 1258 }
7c6e0a43 1259
9a799d71
AK		 1260no_buffers:
1261 if (rx_ring->next_to_use != i) {
1262 rx_ring->next_to_use = i;
84ea2591 1263 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1264 }
1265}
1266
c267fc16 1267static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1268{
c267fc16
AD		 1269 /* HW will not DMA in data larger than the given buffer, even if it
1270 * parses the (NFS, of course) header to be larger. In that case, it
1271 * fills the header buffer and spills the rest into the page.
1272 */
1273 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1274 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1275 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1276 if (hlen > IXGBE_RX_HDR_SIZE)
1277 hlen = IXGBE_RX_HDR_SIZE;
1278 return hlen;
7c6e0a43
JB		 1279}
1280
f8212f97
AD		 1281/**
1282 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1283 * @skb: pointer to the last skb in the rsc queue
1284 *
1285 * This function changes a queue full of hw rsc buffers into a completed
1286 * packet. It uses the ->prev pointers to find the first packet and then
1287 * turns it into the frag list owner.
1288 **/
aa80175a 1289static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1290{
1291 unsigned int frag_list_size = 0;
aa80175a 1292 unsigned int skb_cnt = 1;
f8212f97
AD		 1293
1294 while (skb->prev) {
1295 struct sk_buff *prev = skb->prev;
1296 frag_list_size += skb->len;
1297 skb->prev = NULL;
1298 skb = prev;
aa80175a 1299 skb_cnt++;
f8212f97
AD		 1300 }
1301
1302 skb_shinfo(skb)->frag_list = skb->next;
1303 skb->next = NULL;
1304 skb->len += frag_list_size;
1305 skb->data_len += frag_list_size;
1306 skb->truesize += frag_list_size;
aa80175a
AD		 1307 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1308
f8212f97
AD		 1309 return skb;
1310}
1311
aa80175a
AD		 1312static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1313{
1314 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1315 IXGBE_RXDADV_RSCCNT_MASK);
1316}
43634e82 1317
c267fc16 1318static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1319 struct ixgbe_ring *rx_ring,
1320 int *work_done, int work_to_do)
9a799d71 1321{
78b6f4ce 1322 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1323 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1324 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1325 struct sk_buff *skb;
d2f4fbe2 1326 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1327 const int current_node = numa_node_id();
3d8fd385
YZ		 1328#ifdef IXGBE_FCOE
1329 int ddp_bytes = 0;
1330#endif /* IXGBE_FCOE */
c267fc16
AD		 1331 u32 staterr;
1332 u16 i;
1333 u16 cleaned_count = 0;
aa80175a 1334 bool pkt_is_rsc = false;
9a799d71
AK		 1335
1336 i = rx_ring->next_to_clean;
31f05a2d 1337 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1338 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1339
1340 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1341 u32 upper_len = 0;
9a799d71 1342
3c945e5b 1343 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1344
c267fc16
AD		 1345 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1346
9a799d71 1347 skb = rx_buffer_info->skb;
9a799d71 1348 rx_buffer_info->skb = NULL;
c267fc16 1349 prefetch(skb->data);
9a799d71 1350
c267fc16 1351 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1352 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16
AD		 1353
1354 /* if this is a skb from previous receive DMA will be 0 */
21fa4e66 1355 if (rx_buffer_info->dma) {
c267fc16 1356 u16 hlen;
aa80175a 1357 if (pkt_is_rsc &&
c267fc16
AD		 1358 !(staterr & IXGBE_RXD_STAT_EOP) &&
1359 !skb->prev) {
43634e82
MC		 1360 /*
1361 * When HWRSC is enabled, delay unmapping
1362 * of the first packet. It carries the
1363 * header information, HW may still
1364 * access the header after the writeback.
1365 * Only unmap it when EOP is reached
1366 */
e8171aaa 1367 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1368 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1369 } else {
b6ec895e 1370 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1371 rx_buffer_info->dma,
1372 rx_ring->rx_buf_len,
1373 DMA_FROM_DEVICE);
e8171aaa 1374 }
4f57ca6e 1375 rx_buffer_info->dma = 0;
c267fc16
AD		 1376
1377 if (ring_is_ps_enabled(rx_ring)) {
1378 hlen = ixgbe_get_hlen(rx_desc);
1379 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1380 } else {
1381 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1382 }
1383
1384 skb_put(skb, hlen);
1385 } else {
1386 /* assume packet split since header is unmapped */
1387 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1388 }
1389
1390 if (upper_len) {
b6ec895e
AD		 1391 dma_unmap_page(rx_ring->dev,
1392 rx_buffer_info->page_dma,
1393 PAGE_SIZE / 2,
1394 DMA_FROM_DEVICE);
9a799d71
AK		 1395 rx_buffer_info->page_dma = 0;
1396 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1397 rx_buffer_info->page,
1398 rx_buffer_info->page_offset,
1399 upper_len);
762f4c57 1400
c267fc16
AD		 1401 if ((page_count(rx_buffer_info->page) == 1) &&
1402 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1403 get_page(rx_buffer_info->page);
c267fc16
AD		 1404 else
1405 rx_buffer_info->page = NULL;
9a799d71
AK		 1406
1407 skb->len += upper_len;
1408 skb->data_len += upper_len;
1409 skb->truesize += upper_len;
1410 }
1411
1412 i++;
1413 if (i == rx_ring->count)
1414 i = 0;
9a799d71 1415
31f05a2d 1416 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1417 prefetch(next_rxd);
9a799d71 1418 cleaned_count++;
f8212f97 1419
aa80175a 1420 if (pkt_is_rsc) {
f8212f97
AD		 1421 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1422 IXGBE_RXDADV_NEXTP_SHIFT;
1423 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1424 } else {
1425 next_buffer = &rx_ring->rx_buffer_info[i];
1426 }
1427
c267fc16 1428 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1429 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1430 rx_buffer_info->skb = next_buffer->skb;
1431 rx_buffer_info->dma = next_buffer->dma;
1432 next_buffer->skb = skb;
1433 next_buffer->dma = 0;
1434 } else {
1435 skb->next = next_buffer->skb;
1436 skb->next->prev = skb;
1437 }
5b7da515 1438 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1439 goto next_desc;
1440 }
1441
aa80175a
AD		 1442 if (skb->prev) {
1443 skb = ixgbe_transform_rsc_queue(skb);
1444 /* if we got here without RSC the packet is invalid */
1445 if (!pkt_is_rsc) {
1446 __pskb_trim(skb, 0);
1447 rx_buffer_info->skb = skb;
1448 goto next_desc;
1449 }
1450 }
c267fc16
AD		 1451
1452 if (ring_is_rsc_enabled(rx_ring)) {
1453 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1454 dma_unmap_single(rx_ring->dev,
1455 IXGBE_RSC_CB(skb)->dma,
1456 rx_ring->rx_buf_len,
1457 DMA_FROM_DEVICE);
1458 IXGBE_RSC_CB(skb)->dma = 0;
1459 IXGBE_RSC_CB(skb)->delay_unmap = false;
1460 }
aa80175a
AD		 1461 }
1462 if (pkt_is_rsc) {
c267fc16
AD		 1463 if (ring_is_ps_enabled(rx_ring))
1464 rx_ring->rx_stats.rsc_count +=
aa80175a 1465 skb_shinfo(skb)->nr_frags;
c267fc16 1466 else
aa80175a
AD		 1467 rx_ring->rx_stats.rsc_count +=
1468 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1469 rx_ring->rx_stats.rsc_flush++;
1470 }
1471
1472 /* ERR_MASK will only have valid bits if EOP set */
9a799d71 1473 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
c267fc16
AD		 1474 /* trim packet back to size 0 and recycle it */
1475 __pskb_trim(skb, 0);
1476 rx_buffer_info->skb = skb;
9a799d71
AK		 1477 goto next_desc;
1478 }
1479
8bae1b2b 1480 ixgbe_rx_checksum(adapter, rx_desc, skb);
67a74ee2
ET		 1481 if (adapter->netdev->features & NETIF_F_RXHASH)
1482 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1483
1484 /* probably a little skewed due to removing CRC */
1485 total_rx_bytes += skb->len;
1486 total_rx_packets++;
1487
fc77dc3c 1488 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1489#ifdef IXGBE_FCOE
1490 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 1491 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1492 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1493 if (!ddp_bytes)
332d4a7d 1494 goto next_desc;
3d8fd385 1495 }
332d4a7d 1496#endif /* IXGBE_FCOE */
fdaff1ce 1497 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1498
1499next_desc:
1500 rx_desc->wb.upper.status_error = 0;
1501
c267fc16
AD		 1502 (*work_done)++;
1503 if (*work_done >= work_to_do)
1504 break;
1505
9a799d71
AK		 1506 /* return some buffers to hardware, one at a time is too slow */
1507 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1508 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1509 cleaned_count = 0;
1510 }
1511
1512 /* use prefetched values */
1513 rx_desc = next_rxd;
9a799d71 1514 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1515 }
1516
9a799d71
AK		 1517 rx_ring->next_to_clean = i;
1518 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1519
1520 if (cleaned_count)
fc77dc3c 1521 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1522
3d8fd385
YZ		 1523#ifdef IXGBE_FCOE
1524 /* include DDPed FCoE data */
1525 if (ddp_bytes > 0) {
1526 unsigned int mss;
1527
fc77dc3c 1528 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1529 sizeof(struct fc_frame_header) -
1530 sizeof(struct fcoe_crc_eof);
1531 if (mss > 512)
1532 mss &= ~511;
1533 total_rx_bytes += ddp_bytes;
1534 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1535 }
1536#endif /* IXGBE_FCOE */
1537
f494e8fa
AV		 1538 rx_ring->total_packets += total_rx_packets;
1539 rx_ring->total_bytes += total_rx_bytes;
c267fc16
AD		 1540 u64_stats_update_begin(&rx_ring->syncp);
1541 rx_ring->stats.packets += total_rx_packets;
1542 rx_ring->stats.bytes += total_rx_bytes;
1543 u64_stats_update_end(&rx_ring->syncp);
9a799d71
AK		 1544}
1545
021230d4 1546static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1547/**
1548 * ixgbe_configure_msix - Configure MSI-X hardware
1549 * @adapter: board private structure
1550 *
1551 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1552 * interrupts.
1553 **/
1554static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1555{
021230d4 1556 struct ixgbe_q_vector *q_vector;
bf29ee6c 1557 int i, q_vectors, v_idx, r_idx;
021230d4 1558 u32 mask;
9a799d71 1559
021230d4 1560 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1561
4df10466
JB		 1562 /*
1563 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1564 * corresponding register.
1565 */
1566 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 1567 q_vector = adapter->q_vector[v_idx];
984b3f57 1568 /* XXX for_each_set_bit(...) */
021230d4 1569 r_idx = find_first_bit(q_vector->rxr_idx,
e8e9f696 1570 adapter->num_rx_queues);
021230d4
AV		 1571
1572 for (i = 0; i < q_vector->rxr_count; i++) {
bf29ee6c
AD		 1573 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1574 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
021230d4 1575 r_idx = find_next_bit(q_vector->rxr_idx,
e8e9f696
JP		 1576 adapter->num_rx_queues,
1577 r_idx + 1);
021230d4
AV		 1578 }
1579 r_idx = find_first_bit(q_vector->txr_idx,
e8e9f696 1580 adapter->num_tx_queues);
021230d4
AV		 1581
1582 for (i = 0; i < q_vector->txr_count; i++) {
bf29ee6c
AD		 1583 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1584 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
021230d4 1585 r_idx = find_next_bit(q_vector->txr_idx,
e8e9f696
JP		 1586 adapter->num_tx_queues,
1587 r_idx + 1);
021230d4
AV		 1588 }
1589
021230d4 1590 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 1591 /* tx only */
1592 q_vector->eitr = adapter->tx_eitr_param;
509ee935 1593 else if (q_vector->rxr_count)
f7554a2b
NS		 1594 /* rx or mixed */
1595 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1596
fe49f04a 1597 ixgbe_write_eitr(q_vector);
b25ebfd2
PW		 1598 /* If Flow Director is enabled, set interrupt affinity */
1599 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1600 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1601 /*
1602 * Allocate the affinity_hint cpumask, assign the mask
1603 * for this vector, and set our affinity_hint for
1604 * this irq.
1605 */
1606 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1607 GFP_KERNEL))
1608 return;
1609 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1610 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1611 q_vector->affinity_mask);
1612 }
9a799d71
AK		 1613 }
1614
bd508178
AD		 1615 switch (adapter->hw.mac.type) {
1616 case ixgbe_mac_82598EB:
e8e26350 1617 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1618 v_idx);
bd508178
AD		 1619 break;
1620 case ixgbe_mac_82599EB:
b93a2226 1621 case ixgbe_mac_X540:
e8e26350 1622 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1623 break;
1624
1625 default:
1626 break;
1627 }
021230d4
AV		 1628 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1629
41fb9248 1630 /* set up to autoclear timer, and the vectors */
021230d4 1631 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1632 if (adapter->num_vfs)
1633 mask &= ~(IXGBE_EIMS_OTHER |
1634 IXGBE_EIMS_MAILBOX |
1635 IXGBE_EIMS_LSC);
1636 else
1637 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1638 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1639}
1640
f494e8fa
AV		 1641enum latency_range {
1642 lowest_latency = 0,
1643 low_latency = 1,
1644 bulk_latency = 2,
1645 latency_invalid = 255
1646};
1647
1648/**
1649 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1650 * @adapter: pointer to adapter
1651 * @eitr: eitr setting (ints per sec) to give last timeslice
1652 * @itr_setting: current throttle rate in ints/second
1653 * @packets: the number of packets during this measurement interval
1654 * @bytes: the number of bytes during this measurement interval
1655 *
1656 * Stores a new ITR value based on packets and byte
1657 * counts during the last interrupt. The advantage of per interrupt
1658 * computation is faster updates and more accurate ITR for the current
1659 * traffic pattern. Constants in this function were computed
1660 * based on theoretical maximum wire speed and thresholds were set based
1661 * on testing data as well as attempting to minimize response time
1662 * while increasing bulk throughput.
1663 * this functionality is controlled by the InterruptThrottleRate module
1664 * parameter (see ixgbe_param.c)
1665 **/
1666static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
e8e9f696
JP		 1667 u32 eitr, u8 itr_setting,
1668 int packets, int bytes)
f494e8fa
AV		 1669{
1670 unsigned int retval = itr_setting;
1671 u32 timepassed_us;
1672 u64 bytes_perint;
1673
1674 if (packets == 0)
1675 goto update_itr_done;
1676
1677
1678 /* simple throttlerate management
1679 * 0-20MB/s lowest (100000 ints/s)
1680 * 20-100MB/s low (20000 ints/s)
1681 * 100-1249MB/s bulk (8000 ints/s)
1682 */
1683 /* what was last interrupt timeslice? */
1684 timepassed_us = 1000000/eitr;
1685 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1686
1687 switch (itr_setting) {
1688 case lowest_latency:
1689 if (bytes_perint > adapter->eitr_low)
1690 retval = low_latency;
1691 break;
1692 case low_latency:
1693 if (bytes_perint > adapter->eitr_high)
1694 retval = bulk_latency;
1695 else if (bytes_perint <= adapter->eitr_low)
1696 retval = lowest_latency;
1697 break;
1698 case bulk_latency:
1699 if (bytes_perint <= adapter->eitr_high)
1700 retval = low_latency;
1701 break;
1702 }
1703
1704update_itr_done:
1705 return retval;
1706}
1707
509ee935
JB		 1708/**
1709 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1710 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1711 *
1712 * This function is made to be called by ethtool and by the driver
1713 * when it needs to update EITR registers at runtime. Hardware
1714 * specific quirks/differences are taken care of here.
1715 */
fe49f04a 1716void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1717{
fe49f04a 1718 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1719 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1720 int v_idx = q_vector->v_idx;
1721 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1722
bd508178
AD		 1723 switch (adapter->hw.mac.type) {
1724 case ixgbe_mac_82598EB:
509ee935
JB		 1725 /* must write high and low 16 bits to reset counter */
1726 itr_reg |= (itr_reg << 16);
bd508178
AD		 1727 break;
1728 case ixgbe_mac_82599EB:
b93a2226 1729 case ixgbe_mac_X540:
f8d1dcaf 1730 /*
b93a2226 1731 * 82599 and X540 can support a value of zero, so allow it for
f8d1dcaf
JB		 1732 * max interrupt rate, but there is an errata where it can
1733 * not be zero with RSC
1734 */
1735 if (itr_reg == 8 &&
1736 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1737 itr_reg = 0;
1738
509ee935
JB		 1739 /*
1740 * set the WDIS bit to not clear the timer bits and cause an
1741 * immediate assertion of the interrupt
1742 */
1743 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1744 break;
1745 default:
1746 break;
509ee935
JB		 1747 }
1748 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1749}
1750
f494e8fa
AV		 1751static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1752{
1753 struct ixgbe_adapter *adapter = q_vector->adapter;
125601bf 1754 int i, r_idx;
f494e8fa
AV		 1755 u32 new_itr;
1756 u8 current_itr, ret_itr;
f494e8fa
AV		 1757
1758 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1759 for (i = 0; i < q_vector->txr_count; i++) {
125601bf 1760 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
f494e8fa 1761 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1762 q_vector->tx_itr,
1763 tx_ring->total_packets,
1764 tx_ring->total_bytes);
f494e8fa
AV		 1765 /* if the result for this queue would decrease interrupt
1766 * rate for this vector then use that result */
30efa5a3 1767 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
e8e9f696 1768 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1769 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 1770 r_idx + 1);
f494e8fa
AV		 1771 }
1772
1773 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1774 for (i = 0; i < q_vector->rxr_count; i++) {
125601bf 1775 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
f494e8fa 1776 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
e8e9f696
JP		 1777 q_vector->rx_itr,
1778 rx_ring->total_packets,
1779 rx_ring->total_bytes);
f494e8fa
AV		 1780 /* if the result for this queue would decrease interrupt
1781 * rate for this vector then use that result */
30efa5a3 1782 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
e8e9f696 1783 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1784 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 1785 r_idx + 1);
f494e8fa
AV		 1786 }
1787
30efa5a3 1788 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1789
1790 switch (current_itr) {
1791 /* counts and packets in update_itr are dependent on these numbers */
1792 case lowest_latency:
1793 new_itr = 100000;
1794 break;
1795 case low_latency:
1796 new_itr = 20000; /* aka hwitr = ~200 */
1797 break;
1798 case bulk_latency:
1799 default:
1800 new_itr = 8000;
1801 break;
1802 }
1803
1804 if (new_itr != q_vector->eitr) {
fe49f04a 1805 /* do an exponential smoothing */
125601bf 1806 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935
JB		 1807
1808 /* save the algorithm value here, not the smoothed one */
1809 q_vector->eitr = new_itr;
fe49f04a
AD		 1810
1811 ixgbe_write_eitr(q_vector);
f494e8fa 1812 }
f494e8fa
AV		 1813}
1814
119fc60a
MC		 1815/**
1816 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1817 * @work: pointer to work_struct containing our data
1818 **/
1819static void ixgbe_check_overtemp_task(struct work_struct *work)
1820{
1821 struct ixgbe_adapter *adapter = container_of(work,
e8e9f696
JP		 1822 struct ixgbe_adapter,
1823 check_overtemp_task);
119fc60a
MC		 1824 struct ixgbe_hw *hw = &adapter->hw;
1825 u32 eicr = adapter->interrupt_event;
1826
7ca647bd
JP		 1827 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1828 return;
1829
1830 switch (hw->device_id) {
1831 case IXGBE_DEV_ID_82599_T3_LOM: {
1832 u32 autoneg;
1833 bool link_up = false;
1834
1835 if (hw->mac.ops.check_link)
1836 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1837
1838 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1839 (eicr & IXGBE_EICR_LSC))
1840 /* Check if this is due to overtemp */
1841 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1842 break;
1843 return;
1844 }
1845 default:
1846 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1847 return;
7ca647bd 1848 break;
119fc60a 1849 }
7ca647bd
JP		 1850 e_crit(drv,
1851 "Network adapter has been stopped because it has over heated. "
1852 "Restart the computer. If the problem persists, "
1853 "power off the system and replace the adapter\n");
1854 /* write to clear the interrupt */
1855 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
119fc60a
MC		 1856}
1857
0befdb3e
JB		 1858static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1859{
1860 struct ixgbe_hw *hw = &adapter->hw;
1861
1862 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1863 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1864 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1865 /* write to clear the interrupt */
1866 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1867 }
1868}
cf8280ee 1869
e8e26350
PW		 1870static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1871{
1872 struct ixgbe_hw *hw = &adapter->hw;
1873
73c4b7cd
AD		 1874 if (eicr & IXGBE_EICR_GPI_SDP2) {
1875 /* Clear the interrupt */
1876 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1877 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1878 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1879 ixgbe_service_event_schedule(adapter);
1880 }
73c4b7cd
AD		 1881 }
1882
e8e26350
PW		 1883 if (eicr & IXGBE_EICR_GPI_SDP1) {
1884 /* Clear the interrupt */
1885 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1886 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1887 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1888 ixgbe_service_event_schedule(adapter);
1889 }
e8e26350
PW		 1890 }
1891}
1892
cf8280ee
JB		 1893static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1894{
1895 struct ixgbe_hw *hw = &adapter->hw;
1896
1897 adapter->lsc_int++;
1898 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1899 adapter->link_check_timeout = jiffies;
1900 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1901 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1902 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1903 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1904 }
1905}
1906
9a799d71
AK		 1907static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1908{
1909 struct net_device *netdev = data;
1910 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1911 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1912 u32 eicr;
1913
1914 /*
1915 * Workaround for Silicon errata. Use clear-by-write instead
1916 * of clear-by-read. Reading with EICS will return the
1917 * interrupt causes without clearing, which later be done
1918 * with the write to EICR.
1919 */
1920 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1921 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1922
cf8280ee
JB		 1923 if (eicr & IXGBE_EICR_LSC)
1924 ixgbe_check_lsc(adapter);
d4f80882 1925
1cdd1ec8
GR		 1926 if (eicr & IXGBE_EICR_MAILBOX)
1927 ixgbe_msg_task(adapter);
1928
bd508178
AD		 1929 switch (hw->mac.type) {
1930 case ixgbe_mac_82599EB:
d994653d
DS		 1931 ixgbe_check_sfp_event(adapter, eicr);
1932 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1933 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1934 adapter->interrupt_event = eicr;
1935 schedule_work(&adapter->check_overtemp_task);
1936 }
1937 /* now fallthrough to handle Flow Director */
b93a2226 1938 case ixgbe_mac_X540:
c4cf55e5
PWJ		 1939 /* Handle Flow Director Full threshold interrupt */
1940 if (eicr & IXGBE_EICR_FLOW_DIR) {
1941 int i;
1942 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1943 /* Disable transmits before FDIR Re-initialization */
1944 netif_tx_stop_all_queues(netdev);
1945 for (i = 0; i < adapter->num_tx_queues; i++) {
1946 struct ixgbe_ring *tx_ring =
e8e9f696 1947 adapter->tx_ring[i];
7d637bcc
AD		 1948 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1949 &tx_ring->state))
c4cf55e5
PWJ		 1950 schedule_work(&adapter->fdir_reinit_task);
1951 }
1952 }
bd508178
AD		 1953 break;
1954 default:
1955 break;
c4cf55e5 1956 }
bd508178
AD		 1957
1958 ixgbe_check_fan_failure(adapter, eicr);
1959
7086400d 1960 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 1961 if (!test_bit(__IXGBE_DOWN, &adapter->state))
7086400d
AD		 1962 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1963 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
9a799d71
AK		 1964
1965 return IRQ_HANDLED;
1966}
1967
fe49f04a
AD		 1968static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1969 u64 qmask)
1970{
1971 u32 mask;
bd508178 1972 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1973
bd508178
AD		 1974 switch (hw->mac.type) {
1975 case ixgbe_mac_82598EB:
fe49f04a 1976 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1977 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1978 break;
1979 case ixgbe_mac_82599EB:
b93a2226 1980 case ixgbe_mac_X540:
fe49f04a 1981 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1982 if (mask)
1983 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1984 mask = (qmask >> 32);
bd508178
AD		 1985 if (mask)
1986 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1987 break;
1988 default:
1989 break;
fe49f04a
AD		 1990 }
1991 /* skip the flush */
1992}
1993
1994static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1995 u64 qmask)
fe49f04a
AD		 1996{
1997 u32 mask;
bd508178 1998 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1999
bd508178
AD		 2000 switch (hw->mac.type) {
2001 case ixgbe_mac_82598EB:
fe49f04a 2002 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2003 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2004 break;
2005 case ixgbe_mac_82599EB:
b93a2226 2006 case ixgbe_mac_X540:
fe49f04a 2007 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2008 if (mask)
2009 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2010 mask = (qmask >> 32);
bd508178
AD		 2011 if (mask)
2012 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2013 break;
2014 default:
2015 break;
fe49f04a
AD		 2016 }
2017 /* skip the flush */
2018}
2019
9a799d71
AK		 2020static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
2021{
021230d4
AV		 2022 struct ixgbe_q_vector *q_vector = data;
2023 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2024 struct ixgbe_ring *tx_ring;
021230d4
AV		 2025 int i, r_idx;
2026
2027 if (!q_vector->txr_count)
2028 return IRQ_HANDLED;
2029
2030 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2031 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2032 tx_ring = adapter->tx_ring[r_idx];
3a581073
JB		 2033 tx_ring->total_bytes = 0;
2034 tx_ring->total_packets = 0;
021230d4 2035 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2036 r_idx + 1);
021230d4 2037 }
9a799d71 2038
9b471446 2039 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 2040 napi_schedule(&q_vector->napi);
2041
9a799d71
AK		 2042 return IRQ_HANDLED;
2043}
2044
021230d4
AV		 2045/**
2046 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2047 * @irq: unused
2048 * @data: pointer to our q_vector struct for this interrupt vector
2049 **/
9a799d71
AK		 2050static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2051{
021230d4
AV		 2052 struct ixgbe_q_vector *q_vector = data;
2053 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 2054 struct ixgbe_ring *rx_ring;
021230d4 2055 int r_idx;
30efa5a3 2056 int i;
021230d4 2057
33cf09c9
AD		 2058#ifdef CONFIG_IXGBE_DCA
2059 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2060 ixgbe_update_dca(q_vector);
2061#endif
2062
021230d4 2063 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
33cf09c9 2064 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2065 rx_ring = adapter->rx_ring[r_idx];
30efa5a3
JB		 2066 rx_ring->total_bytes = 0;
2067 rx_ring->total_packets = 0;
2068 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2069 r_idx + 1);
30efa5a3
JB		 2070 }
2071
021230d4
AV		 2072 if (!q_vector->rxr_count)
2073 return IRQ_HANDLED;
2074
9b471446 2075 /* EIAM disabled interrupts (on this vector) for us */
288379f0 2076 napi_schedule(&q_vector->napi);
021230d4
AV		 2077
2078 return IRQ_HANDLED;
2079}
2080
2081static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2082{
91281fd3
AD		 2083 struct ixgbe_q_vector *q_vector = data;
2084 struct ixgbe_adapter *adapter = q_vector->adapter;
2085 struct ixgbe_ring *ring;
2086 int r_idx;
2087 int i;
2088
2089 if (!q_vector->txr_count && !q_vector->rxr_count)
2090 return IRQ_HANDLED;
2091
2092 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2093 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2094 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2095 ring->total_bytes = 0;
2096 ring->total_packets = 0;
2097 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2098 r_idx + 1);
91281fd3
AD		 2099 }
2100
2101 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2102 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2103 ring = adapter->rx_ring[r_idx];
91281fd3
AD		 2104 ring->total_bytes = 0;
2105 ring->total_packets = 0;
2106 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2107 r_idx + 1);
91281fd3
AD		 2108 }
2109
9b471446 2110 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2111 napi_schedule(&q_vector->napi);
9a799d71 2112
9a799d71
AK		 2113 return IRQ_HANDLED;
2114}
2115
021230d4
AV		 2116/**
2117 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2118 * @napi: napi struct with our devices info in it
2119 * @budget: amount of work driver is allowed to do this pass, in packets
2120 *
f0848276
JB		 2121 * This function is optimized for cleaning one queue only on a single
2122 * q_vector!!!
021230d4 2123 **/
9a799d71
AK		 2124static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2125{
021230d4 2126 struct ixgbe_q_vector *q_vector =
e8e9f696 2127 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2128 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 2129 struct ixgbe_ring *rx_ring = NULL;
9a799d71 2130 int work_done = 0;
021230d4 2131 long r_idx;
9a799d71 2132
5dd2d332 2133#ifdef CONFIG_IXGBE_DCA
bd0362dd 2134 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2135 ixgbe_update_dca(q_vector);
bd0362dd 2136#endif
9a799d71 2137
33cf09c9
AD		 2138 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2139 rx_ring = adapter->rx_ring[r_idx];
2140
78b6f4ce 2141 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 2142
021230d4
AV		 2143 /* If all Rx work done, exit the polling mode */
2144 if (work_done < budget) {
288379f0 2145 napi_complete(napi);
f7554a2b 2146 if (adapter->rx_itr_setting & 1)
f494e8fa 2147 ixgbe_set_itr_msix(q_vector);
9a799d71 2148 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2149 ixgbe_irq_enable_queues(adapter,
e8e9f696 2150 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 2151 }
2152
2153 return work_done;
2154}
2155
f0848276 2156/**
91281fd3 2157 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 2158 * @napi: napi struct with our devices info in it
2159 * @budget: amount of work driver is allowed to do this pass, in packets
2160 *
2161 * This function will clean more than one rx queue associated with a
2162 * q_vector.
2163 **/
91281fd3 2164static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 2165{
2166 struct ixgbe_q_vector *q_vector =
e8e9f696 2167 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 2168 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 2169 struct ixgbe_ring *ring = NULL;
f0848276
JB		 2170 int work_done = 0, i;
2171 long r_idx;
91281fd3
AD		 2172 bool tx_clean_complete = true;
2173
33cf09c9
AD		 2174#ifdef CONFIG_IXGBE_DCA
2175 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2176 ixgbe_update_dca(q_vector);
2177#endif
2178
91281fd3
AD		 2179 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2180 for (i = 0; i < q_vector->txr_count; i++) {
4a0b9ca0 2181 ring = adapter->tx_ring[r_idx];
91281fd3
AD		 2182 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2183 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
e8e9f696 2184 r_idx + 1);
91281fd3 2185 }
f0848276
JB		 2186
2187 /* attempt to distribute budget to each queue fairly, but don't allow
2188 * the budget to go below 1 because we'll exit polling */
2189 budget /= (q_vector->rxr_count ?: 1);
2190 budget = max(budget, 1);
2191 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2192 for (i = 0; i < q_vector->rxr_count; i++) {
4a0b9ca0 2193 ring = adapter->rx_ring[r_idx];
91281fd3 2194 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 2195 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
e8e9f696 2196 r_idx + 1);
f0848276
JB		 2197 }
2198
2199 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
4a0b9ca0 2200 ring = adapter->rx_ring[r_idx];
f0848276 2201 /* If all Rx work done, exit the polling mode */
7f821875 2202 if (work_done < budget) {
288379f0 2203 napi_complete(napi);
f7554a2b 2204 if (adapter->rx_itr_setting & 1)
f0848276
JB		 2205 ixgbe_set_itr_msix(q_vector);
2206 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2207 ixgbe_irq_enable_queues(adapter,
e8e9f696 2208 ((u64)1 << q_vector->v_idx));
f0848276
JB		 2209 return 0;
2210 }
2211
2212 return work_done;
2213}
91281fd3
AD		 2214
2215/**
2216 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2217 * @napi: napi struct with our devices info in it
2218 * @budget: amount of work driver is allowed to do this pass, in packets
2219 *
2220 * This function is optimized for cleaning one queue only on a single
2221 * q_vector!!!
2222 **/
2223static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2224{
2225 struct ixgbe_q_vector *q_vector =
e8e9f696 2226 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3
AD		 2227 struct ixgbe_adapter *adapter = q_vector->adapter;
2228 struct ixgbe_ring *tx_ring = NULL;
2229 int work_done = 0;
2230 long r_idx;
2231
91281fd3
AD		 2232#ifdef CONFIG_IXGBE_DCA
2233 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2234 ixgbe_update_dca(q_vector);
91281fd3
AD		 2235#endif
2236
33cf09c9
AD		 2237 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2238 tx_ring = adapter->tx_ring[r_idx];
2239
91281fd3
AD		 2240 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2241 work_done = budget;
2242
f7554a2b 2243 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 2244 if (work_done < budget) {
2245 napi_complete(napi);
f7554a2b 2246 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 2247 ixgbe_set_itr_msix(q_vector);
2248 if (!test_bit(__IXGBE_DOWN, &adapter->state))
e8e9f696
JP		 2249 ixgbe_irq_enable_queues(adapter,
2250 ((u64)1 << q_vector->v_idx));
91281fd3
AD		 2251 }
2252
2253 return work_done;
2254}
2255
021230d4 2256static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2257 int r_idx)
021230d4 2258{
7a921c93 2259 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2260 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93
AD		 2261
2262 set_bit(r_idx, q_vector->rxr_idx);
2263 q_vector->rxr_count++;
2274543f 2264 rx_ring->q_vector = q_vector;
021230d4
AV		 2265}
2266
2267static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2268 int t_idx)
021230d4 2269{
7a921c93 2270 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2271 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93
AD		 2272
2273 set_bit(t_idx, q_vector->txr_idx);
2274 q_vector->txr_count++;
2274543f 2275 tx_ring->q_vector = q_vector;
021230d4
AV		 2276}
2277
9a799d71 2278/**
021230d4
AV		 2279 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2280 * @adapter: board private structure to initialize
9a799d71 2281 *
021230d4
AV		 2282 * This function maps descriptor rings to the queue-specific vectors
2283 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2284 * one vector per ring/queue, but on a constrained vector budget, we
2285 * group the rings as "efficiently" as possible. You would add new
2286 * mapping configurations in here.
9a799d71 2287 **/
d0759ebb 2288static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2289{
d0759ebb 2290 int q_vectors;
021230d4
AV		 2291 int v_start = 0;
2292 int rxr_idx = 0, txr_idx = 0;
2293 int rxr_remaining = adapter->num_rx_queues;
2294 int txr_remaining = adapter->num_tx_queues;
2295 int i, j;
2296 int rqpv, tqpv;
2297 int err = 0;
2298
2299 /* No mapping required if MSI-X is disabled. */
2300 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2301 goto out;
9a799d71 2302
d0759ebb
AD		 2303 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2304
021230d4
AV		 2305 /*
2306 * The ideal configuration...
2307 * We have enough vectors to map one per queue.
2308 */
d0759ebb 2309 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
021230d4
AV		 2310 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2311 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2312
021230d4
AV		 2313 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2314 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2315
9a799d71 2316 goto out;
021230d4 2317 }
9a799d71 2318
021230d4
AV		 2319 /*
2320 * If we don't have enough vectors for a 1-to-1
2321 * mapping, we'll have to group them so there are
2322 * multiple queues per vector.
2323 */
2324 /* Re-adjusting *qpv takes care of the remainder. */
d0759ebb
AD		 2325 for (i = v_start; i < q_vectors; i++) {
2326 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
021230d4
AV		 2327 for (j = 0; j < rqpv; j++) {
2328 map_vector_to_rxq(adapter, i, rxr_idx);
2329 rxr_idx++;
2330 rxr_remaining--;
2331 }
d0759ebb 2332 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
021230d4
AV		 2333 for (j = 0; j < tqpv; j++) {
2334 map_vector_to_txq(adapter, i, txr_idx);
2335 txr_idx++;
2336 txr_remaining--;
9a799d71 2337 }
9a799d71 2338 }
021230d4
AV		 2339out:
2340 return err;
2341}
2342
2343/**
2344 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2345 * @adapter: board private structure
2346 *
2347 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2348 * interrupts from the kernel.
2349 **/
2350static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2351{
2352 struct net_device *netdev = adapter->netdev;
2353 irqreturn_t (*handler)(int, void *);
2354 int i, vector, q_vectors, err;
e8e9f696 2355 int ri = 0, ti = 0;
021230d4
AV		 2356
2357 /* Decrement for Other and TCP Timer vectors */
2358 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2359
d0759ebb 2360 err = ixgbe_map_rings_to_vectors(adapter);
021230d4 2361 if (err)
d0759ebb 2362 return err;
021230d4 2363
d0759ebb
AD		 2364#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2365 ? &ixgbe_msix_clean_many : \
2366 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2367 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2368 NULL)
021230d4 2369 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb
AD		 2370 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2371 handler = SET_HANDLER(q_vector);
cb13fc20 2372
e8e9f696 2373 if (handler == &ixgbe_msix_clean_rx) {
9fe93afd
DS		 2374 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2375 "%s-%s-%d", netdev->name, "rx", ri++);
e8e9f696 2376 } else if (handler == &ixgbe_msix_clean_tx) {
9fe93afd
DS		 2377 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2378 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb 2379 } else if (handler == &ixgbe_msix_clean_many) {
9fe93afd
DS		 2380 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2381 "%s-%s-%d", netdev->name, "TxRx", ri++);
32aa77a4 2382 ti++;
d0759ebb
AD		 2383 } else {
2384 /* skip this unused q_vector */
2385 continue;
32aa77a4 2386 }
021230d4 2387 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb
AD		 2388 handler, 0, q_vector->name,
2389 q_vector);
9a799d71 2390 if (err) {
396e799c 2391 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2392 "Error: %d\n", err);
021230d4 2393 goto free_queue_irqs;
9a799d71 2394 }
9a799d71
AK		 2395 }
2396
d0759ebb 2397 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
021230d4 2398 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb 2399 ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
9a799d71 2400 if (err) {
396e799c 2401 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2402 goto free_queue_irqs;
9a799d71
AK		 2403 }
2404
9a799d71
AK		 2405 return 0;
2406
021230d4
AV		 2407free_queue_irqs:
2408 for (i = vector - 1; i >= 0; i--)
2409 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2410 adapter->q_vector[i]);
021230d4
AV		 2411 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2412 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2413 kfree(adapter->msix_entries);
2414 adapter->msix_entries = NULL;
9a799d71
AK		 2415 return err;
2416}
2417
f494e8fa
AV		 2418static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2419{
7a921c93 2420 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
4a0b9ca0
PW		 2421 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2422 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
125601bf
AD		 2423 u32 new_itr = q_vector->eitr;
2424 u8 current_itr;
f494e8fa 2425
30efa5a3 2426 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2427 q_vector->tx_itr,
2428 tx_ring->total_packets,
2429 tx_ring->total_bytes);
30efa5a3 2430 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
e8e9f696
JP		 2431 q_vector->rx_itr,
2432 rx_ring->total_packets,
2433 rx_ring->total_bytes);
f494e8fa 2434
30efa5a3 2435 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 2436
2437 switch (current_itr) {
2438 /* counts and packets in update_itr are dependent on these numbers */
2439 case lowest_latency:
2440 new_itr = 100000;
2441 break;
2442 case low_latency:
2443 new_itr = 20000; /* aka hwitr = ~200 */
2444 break;
2445 case bulk_latency:
2446 new_itr = 8000;
2447 break;
2448 default:
2449 break;
2450 }
2451
2452 if (new_itr != q_vector->eitr) {
fe49f04a 2453 /* do an exponential smoothing */
125601bf 2454 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 2455
125601bf 2456 /* save the algorithm value here */
509ee935 2457 q_vector->eitr = new_itr;
fe49f04a
AD		 2458
2459 ixgbe_write_eitr(q_vector);
f494e8fa 2460 }
f494e8fa
AV		 2461}
2462
79aefa45
AD		 2463/**
2464 * ixgbe_irq_enable - Enable default interrupt generation settings
2465 * @adapter: board private structure
2466 **/
6af3b9eb
ET		 2467static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2468 bool flush)
79aefa45
AD		 2469{
2470 u32 mask;
835462fc
NS		 2471
2472 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2473 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2474 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2475 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2476 mask |= IXGBE_EIMS_GPI_SDP1;
bd508178
AD		 2477 switch (adapter->hw.mac.type) {
2478 case ixgbe_mac_82599EB:
b93a2226 2479 case ixgbe_mac_X540:
2a41ff81 2480 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2481 mask |= IXGBE_EIMS_GPI_SDP1;
2482 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2483 if (adapter->num_vfs)
2484 mask |= IXGBE_EIMS_MAILBOX;
bd508178
AD		 2485 break;
2486 default:
2487 break;
e8e26350 2488 }
c4cf55e5
PWJ		 2489 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2490 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2491 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2492
79aefa45 2493 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2494 if (queues)
2495 ixgbe_irq_enable_queues(adapter, ~0);
2496 if (flush)
2497 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2498
2499 if (adapter->num_vfs > 32) {
2500 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2501 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2502 }
79aefa45 2503}
021230d4 2504
9a799d71 2505/**
021230d4 2506 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2507 * @irq: interrupt number
2508 * @data: pointer to a network interface device structure
9a799d71
AK		 2509 **/
2510static irqreturn_t ixgbe_intr(int irq, void *data)
2511{
2512 struct net_device *netdev = data;
2513 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2514 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2515 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2516 u32 eicr;
2517
54037505 2518 /*
6af3b9eb 2519 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2520 * before the read of EICR.
2521 */
2522 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2523
021230d4
AV		 2524 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2525 * therefore no explict interrupt disable is necessary */
2526 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2527 if (!eicr) {
6af3b9eb
ET		 2528 /*
2529 * shared interrupt alert!
f47cf66e 2530 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2531 * have disabled interrupts due to EIAM
2532 * finish the workaround of silicon errata on 82598. Unmask
2533 * the interrupt that we masked before the EICR read.
2534 */
2535 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2536 ixgbe_irq_enable(adapter, true, true);
9a799d71 2537 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2538 }
9a799d71 2539
cf8280ee
JB		 2540 if (eicr & IXGBE_EICR_LSC)
2541 ixgbe_check_lsc(adapter);
021230d4 2542
bd508178
AD		 2543 switch (hw->mac.type) {
2544 case ixgbe_mac_82599EB:
e8e26350 2545 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2546 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2547 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2548 adapter->interrupt_event = eicr;
2549 schedule_work(&adapter->check_overtemp_task);
2550 }
2551 break;
2552 default:
2553 break;
2554 }
e8e26350 2555
0befdb3e
JB		 2556 ixgbe_check_fan_failure(adapter, eicr);
2557
7a921c93 2558 if (napi_schedule_prep(&(q_vector->napi))) {
4a0b9ca0
PW		 2559 adapter->tx_ring[0]->total_packets = 0;
2560 adapter->tx_ring[0]->total_bytes = 0;
2561 adapter->rx_ring[0]->total_packets = 0;
2562 adapter->rx_ring[0]->total_bytes = 0;
021230d4 2563 /* would disable interrupts here but EIAM disabled it */
7a921c93 2564 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2565 }
2566
6af3b9eb
ET		 2567 /*
2568 * re-enable link(maybe) and non-queue interrupts, no flush.
2569 * ixgbe_poll will re-enable the queue interrupts
2570 */
2571
2572 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2573 ixgbe_irq_enable(adapter, false, false);
2574
9a799d71
AK		 2575 return IRQ_HANDLED;
2576}
2577
021230d4
AV		 2578static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2579{
2580 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2581
2582 for (i = 0; i < q_vectors; i++) {
7a921c93 2583 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 2584 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2585 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2586 q_vector->rxr_count = 0;
2587 q_vector->txr_count = 0;
2588 }
2589}
2590
9a799d71
AK		 2591/**
2592 * ixgbe_request_irq - initialize interrupts
2593 * @adapter: board private structure
2594 *
2595 * Attempts to configure interrupts using the best available
2596 * capabilities of the hardware and kernel.
2597 **/
021230d4 2598static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2599{
2600 struct net_device *netdev = adapter->netdev;
021230d4 2601 int err;
9a799d71 2602
021230d4
AV		 2603 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2604 err = ixgbe_request_msix_irqs(adapter);
2605 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2606 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
e8e9f696 2607 netdev->name, netdev);
021230d4 2608 } else {
a0607fd3 2609 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
e8e9f696 2610 netdev->name, netdev);
9a799d71
AK		 2611 }
2612
9a799d71 2613 if (err)
396e799c 2614 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2615
9a799d71
AK		 2616 return err;
2617}
2618
2619static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2620{
2621 struct net_device *netdev = adapter->netdev;
2622
2623 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2624 int i, q_vectors;
9a799d71 2625
021230d4
AV		 2626 q_vectors = adapter->num_msix_vectors;
2627
2628 i = q_vectors - 1;
9a799d71 2629 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 2630
021230d4
AV		 2631 i--;
2632 for (; i >= 0; i--) {
894ff7cf
AD		 2633 /* free only the irqs that were actually requested */
2634 if (!adapter->q_vector[i]->rxr_count &&
2635 !adapter->q_vector[i]->txr_count)
2636 continue;
2637
021230d4 2638 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2639 adapter->q_vector[i]);
021230d4
AV		 2640 }
2641
2642 ixgbe_reset_q_vectors(adapter);
2643 } else {
2644 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 2645 }
2646}
2647
22d5a71b
JB		 2648/**
2649 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2650 * @adapter: board private structure
2651 **/
2652static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2653{
bd508178
AD		 2654 switch (adapter->hw.mac.type) {
2655 case ixgbe_mac_82598EB:
835462fc 2656 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2657 break;
2658 case ixgbe_mac_82599EB:
b93a2226 2659 case ixgbe_mac_X540:
835462fc
NS		 2660 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2661 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2662 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2663 if (adapter->num_vfs > 32)
2664 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
bd508178
AD		 2665 break;
2666 default:
2667 break;
22d5a71b
JB		 2668 }
2669 IXGBE_WRITE_FLUSH(&adapter->hw);
2670 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2671 int i;
2672 for (i = 0; i < adapter->num_msix_vectors; i++)
2673 synchronize_irq(adapter->msix_entries[i].vector);
2674 } else {
2675 synchronize_irq(adapter->pdev->irq);
2676 }
2677}
2678
9a799d71
AK		 2679/**
2680 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2681 *
2682 **/
2683static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2684{
9a799d71
AK		 2685 struct ixgbe_hw *hw = &adapter->hw;
2686
021230d4 2687 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2688 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2689
e8e26350
PW		 2690 ixgbe_set_ivar(adapter, 0, 0, 0);
2691 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2692
2693 map_vector_to_rxq(adapter, 0, 0);
2694 map_vector_to_txq(adapter, 0, 0);
2695
396e799c 2696 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2697}
2698
43e69bf0
AD		 2699/**
2700 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2701 * @adapter: board private structure
2702 * @ring: structure containing ring specific data
2703 *
2704 * Configure the Tx descriptor ring after a reset.
2705 **/
84418e3b
AD		 2706void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2707 struct ixgbe_ring *ring)
43e69bf0
AD		 2708{
2709 struct ixgbe_hw *hw = &adapter->hw;
2710 u64 tdba = ring->dma;
2f1860b8
AD		 2711 int wait_loop = 10;
2712 u32 txdctl;
bf29ee6c 2713 u8 reg_idx = ring->reg_idx;
43e69bf0 2714
2f1860b8
AD		 2715 /* disable queue to avoid issues while updating state */
2716 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2717 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2718 txdctl & ~IXGBE_TXDCTL_ENABLE);
2719 IXGBE_WRITE_FLUSH(hw);
2720
43e69bf0 2721 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2722 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2723 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2724 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2725 ring->count * sizeof(union ixgbe_adv_tx_desc));
2726 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2727 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2728 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2729
2f1860b8
AD		 2730 /* configure fetching thresholds */
2731 if (adapter->rx_itr_setting == 0) {
2732 /* cannot set wthresh when itr==0 */
2733 txdctl &= ~0x007F0000;
2734 } else {
2735 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2736 txdctl |= (8 << 16);
2737 }
2738 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2739 /* PThresh workaround for Tx hang with DFP enabled. */
2740 txdctl |= 32;
2741 }
2742
2743 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2744 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2745 adapter->atr_sample_rate) {
2746 ring->atr_sample_rate = adapter->atr_sample_rate;
2747 ring->atr_count = 0;
2748 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2749 } else {
2750 ring->atr_sample_rate = 0;
2751 }
2f1860b8 2752
c84d324c
JF		 2753 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2754
2f1860b8
AD		 2755 /* enable queue */
2756 txdctl |= IXGBE_TXDCTL_ENABLE;
2757 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2758
2759 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2760 if (hw->mac.type == ixgbe_mac_82598EB &&
2761 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2762 return;
2763
2764 /* poll to verify queue is enabled */
2765 do {
032b4325 2766 usleep_range(1000, 2000);
2f1860b8
AD		 2767 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2768 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2769 if (!wait_loop)
2770 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2771}
2772
120ff942
AD		 2773static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2774{
2775 struct ixgbe_hw *hw = &adapter->hw;
2776 u32 rttdcs;
2777 u32 mask;
2778
2779 if (hw->mac.type == ixgbe_mac_82598EB)
2780 return;
2781
2782 /* disable the arbiter while setting MTQC */
2783 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2784 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2785 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2786
2787 /* set transmit pool layout */
2788 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2789 switch (adapter->flags & mask) {
2790
2791 case (IXGBE_FLAG_SRIOV_ENABLED):
2792 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2793 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2794 break;
2795
2796 case (IXGBE_FLAG_DCB_ENABLED):
2797 /* We enable 8 traffic classes, DCB only */
2798 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2799 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2800 break;
2801
2802 default:
2803 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2804 break;
2805 }
2806
2807 /* re-enable the arbiter */
2808 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2809 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2810}
2811
9a799d71 2812/**
3a581073 2813 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2814 * @adapter: board private structure
2815 *
2816 * Configure the Tx unit of the MAC after a reset.
2817 **/
2818static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2819{
2f1860b8
AD		 2820 struct ixgbe_hw *hw = &adapter->hw;
2821 u32 dmatxctl;
43e69bf0 2822 u32 i;
9a799d71 2823
2f1860b8
AD		 2824 ixgbe_setup_mtqc(adapter);
2825
2826 if (hw->mac.type != ixgbe_mac_82598EB) {
2827 /* DMATXCTL.EN must be before Tx queues are enabled */
2828 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2829 dmatxctl |= IXGBE_DMATXCTL_TE;
2830 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2831 }
2832
9a799d71 2833 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2834 for (i = 0; i < adapter->num_tx_queues; i++)
2835 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2836}
2837
e8e26350 2838#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2839
a6616b42 2840static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2841 struct ixgbe_ring *rx_ring)
cc41ac7c 2842{
cc41ac7c 2843 u32 srrctl;
bf29ee6c 2844 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2845
bd508178
AD		 2846 switch (adapter->hw.mac.type) {
2847 case ixgbe_mac_82598EB: {
2848 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2849 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2850 reg_idx = reg_idx & mask;
cc41ac7c 2851 }
bd508178
AD		 2852 break;
2853 case ixgbe_mac_82599EB:
b93a2226 2854 case ixgbe_mac_X540:
bd508178
AD		 2855 default:
2856 break;
2857 }
2858
bf29ee6c 2859 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2860
2861 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2862 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2863 if (adapter->num_vfs)
2864 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2865
afafd5b0
AD		 2866 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2867 IXGBE_SRRCTL_BSIZEHDR_MASK;
2868
7d637bcc 2869 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2870#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2871 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2872#else
2873 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2874#endif
cc41ac7c 2875 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2876 } else {
afafd5b0
AD		 2877 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2878 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2879 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2880 }
e8e26350 2881
bf29ee6c 2882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2883}
9a799d71 2884
05abb126 2885static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2886{
05abb126
AD		 2887 struct ixgbe_hw *hw = &adapter->hw;
2888 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2889 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2890 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2891 u32 mrqc = 0, reta = 0;
2892 u32 rxcsum;
2893 int i, j;
0cefafad
JB		 2894 int mask;
2895
05abb126
AD		 2896 /* Fill out hash function seeds */
2897 for (i = 0; i < 10; i++)
2898 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2899
2900 /* Fill out redirection table */
2901 for (i = 0, j = 0; i < 128; i++, j++) {
2902 if (j == adapter->ring_feature[RING_F_RSS].indices)
2903 j = 0;
2904 /* reta = 4-byte sliding window of
2905 * 0x00..(indices-1)(indices-1)00..etc. */
2906 reta = (reta << 8) | (j * 0x11);
2907 if ((i & 3) == 3)
2908 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2909 }
0cefafad 2910
05abb126
AD		 2911 /* Disable indicating checksum in descriptor, enables RSS hash */
2912 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2913 rxcsum |= IXGBE_RXCSUM_PCSD;
2914 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2915
2916 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2917 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2918 else
2919 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
0cefafad 2920#ifdef CONFIG_IXGBE_DCB
05abb126 2921 | IXGBE_FLAG_DCB_ENABLED
0cefafad 2922#endif
05abb126
AD		 2923 | IXGBE_FLAG_SRIOV_ENABLED
2924 );
0cefafad
JB		 2925
2926 switch (mask) {
8187cd48
JF		 2927#ifdef CONFIG_IXGBE_DCB
2928 case (IXGBE_FLAG_DCB_ENABLED | IXGBE_FLAG_RSS_ENABLED):
2929 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2930 break;
2931 case (IXGBE_FLAG_DCB_ENABLED):
2932 mrqc = IXGBE_MRQC_RT8TCEN;
2933 break;
2934#endif /* CONFIG_IXGBE_DCB */
0cefafad
JB		 2935 case (IXGBE_FLAG_RSS_ENABLED):
2936 mrqc = IXGBE_MRQC_RSSEN;
2937 break;
1cdd1ec8
GR		 2938 case (IXGBE_FLAG_SRIOV_ENABLED):
2939 mrqc = IXGBE_MRQC_VMDQEN;
2940 break;
0cefafad
JB		 2941 default:
2942 break;
2943 }
2944
05abb126
AD		 2945 /* Perform hash on these packet types */
2946 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2947 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2948 | IXGBE_MRQC_RSS_FIELD_IPV6
2949 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2950
2951 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2952}
2953
b93a2226
DS		 2954/**
2955 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2956 * @adapter: address of board private structure
2957 * @ring: structure containing ring specific data
2958 **/
2959void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2960 struct ixgbe_ring *ring)
2961{
2962 struct ixgbe_hw *hw = &adapter->hw;
2963 u32 rscctrl;
2964 u8 reg_idx = ring->reg_idx;
2965
2966 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2967 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2968 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2969}
2970
bb5a9ad2
NS		 2971/**
2972 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2973 * @adapter: address of board private structure
2974 * @index: index of ring to set
bb5a9ad2 2975 **/
b93a2226 2976void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2977 struct ixgbe_ring *ring)
bb5a9ad2 2978{
bb5a9ad2 2979 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2980 u32 rscctrl;
edd2ea55 2981 int rx_buf_len;
bf29ee6c 2982 u8 reg_idx = ring->reg_idx;
7367096a 2983
7d637bcc 2984 if (!ring_is_rsc_enabled(ring))
7367096a 2985 return;
bb5a9ad2 2986
7367096a
AD		 2987 rx_buf_len = ring->rx_buf_len;
2988 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2989 rscctrl |= IXGBE_RSCCTL_RSCEN;
2990 /*
2991 * we must limit the number of descriptors so that the
2992 * total size of max desc * buf_len is not greater
2993 * than 65535
2994 */
7d637bcc 2995 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2996#if (MAX_SKB_FRAGS > 16)
2997 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2998#elif (MAX_SKB_FRAGS > 8)
2999 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
3000#elif (MAX_SKB_FRAGS > 4)
3001 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3002#else
3003 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
3004#endif
3005 } else {
3006 if (rx_buf_len < IXGBE_RXBUFFER_4096)
3007 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3008 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
3009 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
3010 else
3011 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3012 }
7367096a 3013 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3014}
3015
9e10e045
AD		 3016/**
3017 * ixgbe_set_uta - Set unicast filter table address
3018 * @adapter: board private structure
3019 *
3020 * The unicast table address is a register array of 32-bit registers.
3021 * The table is meant to be used in a way similar to how the MTA is used
3022 * however due to certain limitations in the hardware it is necessary to
3023 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
3024 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
3025 **/
3026static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
3027{
3028 struct ixgbe_hw *hw = &adapter->hw;
3029 int i;
3030
3031 /* The UTA table only exists on 82599 hardware and newer */
3032 if (hw->mac.type < ixgbe_mac_82599EB)
3033 return;
3034
3035 /* we only need to do this if VMDq is enabled */
3036 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3037 return;
3038
3039 for (i = 0; i < 128; i++)
3040 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3041}
3042
3043#define IXGBE_MAX_RX_DESC_POLL 10
3044static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3045 struct ixgbe_ring *ring)
3046{
3047 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3048 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3049 u32 rxdctl;
bf29ee6c 3050 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3051
3052 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3053 if (hw->mac.type == ixgbe_mac_82598EB &&
3054 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3055 return;
3056
3057 do {
032b4325 3058 usleep_range(1000, 2000);
9e10e045
AD		 3059 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3060 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3061
3062 if (!wait_loop) {
3063 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3064 "the polling period\n", reg_idx);
3065 }
3066}
3067
2d39d576
YZ		 3068void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3069 struct ixgbe_ring *ring)
3070{
3071 struct ixgbe_hw *hw = &adapter->hw;
3072 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3073 u32 rxdctl;
3074 u8 reg_idx = ring->reg_idx;
3075
3076 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3077 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3078
3079 /* write value back with RXDCTL.ENABLE bit cleared */
3080 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3081
3082 if (hw->mac.type == ixgbe_mac_82598EB &&
3083 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3084 return;
3085
3086 /* the hardware may take up to 100us to really disable the rx queue */
3087 do {
3088 udelay(10);
3089 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3090 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3091
3092 if (!wait_loop) {
3093 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3094 "the polling period\n", reg_idx);
3095 }
3096}
3097
84418e3b
AD		 3098void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3099 struct ixgbe_ring *ring)
acd37177
AD		 3100{
3101 struct ixgbe_hw *hw = &adapter->hw;
3102 u64 rdba = ring->dma;
9e10e045 3103 u32 rxdctl;
bf29ee6c 3104 u8 reg_idx = ring->reg_idx;
acd37177 3105
9e10e045
AD		 3106 /* disable queue to avoid issues while updating state */
3107 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3108 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3109
acd37177
AD		 3110 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3111 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3112 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3113 ring->count * sizeof(union ixgbe_adv_rx_desc));
3114 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3115 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3116 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3117
3118 ixgbe_configure_srrctl(adapter, ring);
3119 ixgbe_configure_rscctl(adapter, ring);
3120
e9f98072
GR		 3121 /* If operating in IOV mode set RLPML for X540 */
3122 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3123 hw->mac.type == ixgbe_mac_X540) {
3124 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3125 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3126 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3127 }
3128
9e10e045
AD		 3129 if (hw->mac.type == ixgbe_mac_82598EB) {
3130 /*
3131 * enable cache line friendly hardware writes:
3132 * PTHRESH=32 descriptors (half the internal cache),
3133 * this also removes ugly rx_no_buffer_count increment
3134 * HTHRESH=4 descriptors (to minimize latency on fetch)
3135 * WTHRESH=8 burst writeback up to two cache lines
3136 */
3137 rxdctl &= ~0x3FFFFF;
3138 rxdctl |= 0x080420;
3139 }
3140
3141 /* enable receive descriptor ring */
3142 rxdctl |= IXGBE_RXDCTL_ENABLE;
3143 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3144
3145 ixgbe_rx_desc_queue_enable(adapter, ring);
fc77dc3c 3146 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
acd37177
AD		 3147}
3148
48654521
AD		 3149static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3150{
3151 struct ixgbe_hw *hw = &adapter->hw;
3152 int p;
3153
3154 /* PSRTYPE must be initialized in non 82598 adapters */
3155 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3156 IXGBE_PSRTYPE_UDPHDR |
3157 IXGBE_PSRTYPE_IPV4HDR |
48654521 3158 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3159 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3160
3161 if (hw->mac.type == ixgbe_mac_82598EB)
3162 return;
3163
3164 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3165 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3166
3167 for (p = 0; p < adapter->num_rx_pools; p++)
3168 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3169 psrtype);
3170}
3171
f5b4a52e
AD		 3172static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3173{
3174 struct ixgbe_hw *hw = &adapter->hw;
3175 u32 gcr_ext;
3176 u32 vt_reg_bits;
3177 u32 reg_offset, vf_shift;
3178 u32 vmdctl;
3179
3180 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3181 return;
3182
3183 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3184 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3185 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3186 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3187
3188 vf_shift = adapter->num_vfs % 32;
3189 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3190
3191 /* Enable only the PF's pool for Tx/Rx */
3192 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3193 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3194 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3195 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3196 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3197
3198 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3199 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3200
3201 /*
3202 * Set up VF register offsets for selected VT Mode,
3203 * i.e. 32 or 64 VFs for SR-IOV
3204 */
3205 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3206 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3207 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3208 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3209
3210 /* enable Tx loopback for VF/PF communication */
3211 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 3212 /* Enable MAC Anti-Spoofing */
a1cbb15c
GR		 3213 hw->mac.ops.set_mac_anti_spoofing(hw,
3214 (adapter->antispoofing_enabled =
3215 (adapter->num_vfs != 0)),
a985b6c3 3216 adapter->num_vfs);
f5b4a52e
AD		 3217}
3218
477de6ed 3219static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3220{
9a799d71
AK		 3221 struct ixgbe_hw *hw = &adapter->hw;
3222 struct net_device *netdev = adapter->netdev;
3223 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3224 int rx_buf_len;
477de6ed
AD		 3225 struct ixgbe_ring *rx_ring;
3226 int i;
3227 u32 mhadd, hlreg0;
48654521 3228
9a799d71 3229 /* Decide whether to use packet split mode or not */
a124339a
DS		 3230 /* On by default */
3231 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3232
1cdd1ec8 3233 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 3234 if (adapter->num_vfs)
3235 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3236
3237 /* Disable packet split due to 82599 erratum #45 */
3238 if (hw->mac.type == ixgbe_mac_82599EB)
3239 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 3240
3241 /* Set the RX buffer length according to the mode */
3242 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 3243 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 3244 } else {
0c19d6af 3245 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 3246 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 3247 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 3248 else
477de6ed 3249 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 3250 }
3251
63f39bd1 3252#ifdef IXGBE_FCOE
477de6ed
AD		 3253 /* adjust max frame to be able to do baby jumbo for FCoE */
3254 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3255 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3256 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3257
477de6ed
AD		 3258#endif /* IXGBE_FCOE */
3259 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3260 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3261 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3262 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3263
3264 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3265 }
3266
3267 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3268 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3269 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3270 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3271
0cefafad
JB		 3272 /*
3273 * Setup the HW Rx Head and Tail Descriptor Pointers and
3274 * the Base and Length of the Rx Descriptor Ring
3275 */
9a799d71 3276 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3277 rx_ring = adapter->rx_ring[i];
a6616b42 3278 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3279
6e455b89 3280 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3281 set_ring_ps_enabled(rx_ring);
3282 else
3283 clear_ring_ps_enabled(rx_ring);
3284
3285 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3286 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3287 else
7d637bcc 3288 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3289
63f39bd1 3290#ifdef IXGBE_FCOE
e8e9f696 3291 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3292 struct ixgbe_ring_feature *f;
3293 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3294 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3295 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3296 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3297 rx_ring->rx_buf_len =
e8e9f696 3298 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3299 } else if (!ring_is_rsc_enabled(rx_ring) &&
3300 !ring_is_ps_enabled(rx_ring)) {
3301 rx_ring->rx_buf_len =
3302 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3303 }
63f39bd1 3304 }
63f39bd1 3305#endif /* IXGBE_FCOE */
477de6ed 3306 }
477de6ed
AD		 3307}
3308
7367096a
AD		 3309static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3310{
3311 struct ixgbe_hw *hw = &adapter->hw;
3312 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3313
3314 switch (hw->mac.type) {
3315 case ixgbe_mac_82598EB:
3316 /*
3317 * For VMDq support of different descriptor types or
3318 * buffer sizes through the use of multiple SRRCTL
3319 * registers, RDRXCTL.MVMEN must be set to 1
3320 *
3321 * also, the manual doesn't mention it clearly but DCA hints
3322 * will only use queue 0's tags unless this bit is set. Side
3323 * effects of setting this bit are only that SRRCTL must be
3324 * fully programmed [0..15]
3325 */
3326 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3327 break;
3328 case ixgbe_mac_82599EB:
b93a2226 3329 case ixgbe_mac_X540:
7367096a
AD		 3330 /* Disable RSC for ACK packets */
3331 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3332 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3333 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3334 /* hardware requires some bits to be set by default */
3335 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3336 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3337 break;
3338 default:
3339 /* We should do nothing since we don't know this hardware */
3340 return;
3341 }
3342
3343 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3344}
3345
477de6ed
AD		 3346/**
3347 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3348 * @adapter: board private structure
3349 *
3350 * Configure the Rx unit of the MAC after a reset.
3351 **/
3352static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3353{
3354 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3355 int i;
3356 u32 rxctrl;
477de6ed
AD		 3357
3358 /* disable receives while setting up the descriptors */
3359 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3360 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3361
3362 ixgbe_setup_psrtype(adapter);
7367096a 3363 ixgbe_setup_rdrxctl(adapter);
477de6ed 3364
9e10e045 3365 /* Program registers for the distribution of queues */
f5b4a52e 3366 ixgbe_setup_mrqc(adapter);
f5b4a52e 3367
9e10e045
AD		 3368 ixgbe_set_uta(adapter);
3369
477de6ed
AD		 3370 /* set_rx_buffer_len must be called before ring initialization */
3371 ixgbe_set_rx_buffer_len(adapter);
3372
3373 /*
3374 * Setup the HW Rx Head and Tail Descriptor Pointers and
3375 * the Base and Length of the Rx Descriptor Ring
3376 */
9e10e045
AD		 3377 for (i = 0; i < adapter->num_rx_queues; i++)
3378 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3379
9e10e045
AD		 3380 /* disable drop enable for 82598 parts */
3381 if (hw->mac.type == ixgbe_mac_82598EB)
3382 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3383
3384 /* enable all receives */
3385 rxctrl |= IXGBE_RXCTRL_RXEN;
3386 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3387}
3388
068c89b0
DS		 3389static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3390{
3391 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3392 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3393 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3394
3395 /* add VID to filter table */
1ada1b1b 3396 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3397 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3398}
3399
3400static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3401{
3402 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3403 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3404 int pool_ndx = adapter->num_vfs;
068c89b0 3405
068c89b0 3406 /* remove VID from filter table */
1ada1b1b 3407 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3408 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3409}
3410
5f6c0181
JB		 3411/**
3412 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3413 * @adapter: driver data
3414 */
3415static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3416{
3417 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3418 u32 vlnctrl;
3419
3420 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3421 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3422 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3423}
3424
3425/**
3426 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3427 * @adapter: driver data
3428 */
3429static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3430{
3431 struct ixgbe_hw *hw = &adapter->hw;
3432 u32 vlnctrl;
3433
3434 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3435 vlnctrl |= IXGBE_VLNCTRL_VFE;
3436 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3437 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3438}
3439
3440/**
3441 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3442 * @adapter: driver data
3443 */
3444static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3445{
3446 struct ixgbe_hw *hw = &adapter->hw;
3447 u32 vlnctrl;
5f6c0181
JB		 3448 int i, j;
3449
3450 switch (hw->mac.type) {
3451 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3452 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3453 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3454 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3455 break;
3456 case ixgbe_mac_82599EB:
b93a2226 3457 case ixgbe_mac_X540:
5f6c0181
JB		 3458 for (i = 0; i < adapter->num_rx_queues; i++) {
3459 j = adapter->rx_ring[i]->reg_idx;
3460 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3461 vlnctrl &= ~IXGBE_RXDCTL_VME;
3462 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3463 }
3464 break;
3465 default:
3466 break;
3467 }
3468}
3469
3470/**
f62bbb5e 3471 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3472 * @adapter: driver data
3473 */
f62bbb5e 3474static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3475{
3476 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3477 u32 vlnctrl;
5f6c0181
JB		 3478 int i, j;
3479
3480 switch (hw->mac.type) {
3481 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3482 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3483 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3484 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3485 break;
3486 case ixgbe_mac_82599EB:
b93a2226 3487 case ixgbe_mac_X540:
5f6c0181
JB		 3488 for (i = 0; i < adapter->num_rx_queues; i++) {
3489 j = adapter->rx_ring[i]->reg_idx;
3490 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3491 vlnctrl |= IXGBE_RXDCTL_VME;
3492 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3493 }
3494 break;
3495 default:
3496 break;
3497 }
3498}
3499
9a799d71
AK		 3500static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3501{
f62bbb5e 3502 u16 vid;
9a799d71 3503
f62bbb5e
JG		 3504 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3505
3506 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3507 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3508}
3509
2850062a
AD		 3510/**
3511 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3512 * @netdev: network interface device structure
3513 *
3514 * Writes unicast address list to the RAR table.
3515 * Returns: -ENOMEM on failure/insufficient address space
3516 * 0 on no addresses written
3517 * X on writing X addresses to the RAR table
3518 **/
3519static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3520{
3521 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3522 struct ixgbe_hw *hw = &adapter->hw;
3523 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3524 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3525 int count = 0;
3526
3527 /* return ENOMEM indicating insufficient memory for addresses */
3528 if (netdev_uc_count(netdev) > rar_entries)
3529 return -ENOMEM;
3530
3531 if (!netdev_uc_empty(netdev) && rar_entries) {
3532 struct netdev_hw_addr *ha;
3533 /* return error if we do not support writing to RAR table */
3534 if (!hw->mac.ops.set_rar)
3535 return -ENOMEM;
3536
3537 netdev_for_each_uc_addr(ha, netdev) {
3538 if (!rar_entries)
3539 break;
3540 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3541 vfn, IXGBE_RAH_AV);
3542 count++;
3543 }
3544 }
3545 /* write the addresses in reverse order to avoid write combining */
3546 for (; rar_entries > 0 ; rar_entries--)
3547 hw->mac.ops.clear_rar(hw, rar_entries);
3548
3549 return count;
3550}
3551
9a799d71 3552/**
2c5645cf 3553 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3554 * @netdev: network interface device structure
3555 *
2c5645cf
CL		 3556 * The set_rx_method entry point is called whenever the unicast/multicast
3557 * address list or the network interface flags are updated. This routine is
3558 * responsible for configuring the hardware for proper unicast, multicast and
3559 * promiscuous mode.
9a799d71 3560 **/
7f870475 3561void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3562{
3563 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3564 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3565 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3566 int count;
9a799d71
AK		 3567
3568 /* Check for Promiscuous and All Multicast modes */
3569
3570 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3571
f5dc442b
AD		 3572 /* set all bits that we expect to always be set */
3573 fctrl |= IXGBE_FCTRL_BAM;
3574 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3575 fctrl |= IXGBE_FCTRL_PMCF;
3576
2850062a
AD		 3577 /* clear the bits we are changing the status of */
3578 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3579
9a799d71 3580 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3581 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3582 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3583 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3584 /* don't hardware filter vlans in promisc mode */
3585 ixgbe_vlan_filter_disable(adapter);
9a799d71 3586 } else {
746b9f02
PM		 3587 if (netdev->flags & IFF_ALLMULTI) {
3588 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3589 vmolr |= IXGBE_VMOLR_MPE;
3590 } else {
3591 /*
3592 * Write addresses to the MTA, if the attempt fails
25985edc 3593 * then we should just turn on promiscuous mode so
2850062a
AD		 3594 * that we can at least receive multicast traffic
3595 */
3596 hw->mac.ops.update_mc_addr_list(hw, netdev);
3597 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3598 }
5f6c0181 3599 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3600 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3601 /*
3602 * Write addresses to available RAR registers, if there is not
3603 * sufficient space to store all the addresses then enable
25985edc 3604 * unicast promiscuous mode
2850062a
AD		 3605 */
3606 count = ixgbe_write_uc_addr_list(netdev);
3607 if (count < 0) {
3608 fctrl |= IXGBE_FCTRL_UPE;
3609 vmolr |= IXGBE_VMOLR_ROPE;
3610 }
9a799d71
AK		 3611 }
3612
2850062a 3613 if (adapter->num_vfs) {
1cdd1ec8 3614 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3615 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3616 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3617 IXGBE_VMOLR_ROPE);
3618 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3619 }
3620
3621 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3622
3623 if (netdev->features & NETIF_F_HW_VLAN_RX)
3624 ixgbe_vlan_strip_enable(adapter);
3625 else
3626 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3627}
3628
021230d4
AV		 3629static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3630{
3631 int q_idx;
3632 struct ixgbe_q_vector *q_vector;
3633 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3634
3635 /* legacy and MSI only use one vector */
3636 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3637 q_vectors = 1;
3638
3639 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3640 struct napi_struct *napi;
7a921c93 3641 q_vector = adapter->q_vector[q_idx];
f0848276 3642 napi = &q_vector->napi;
91281fd3
AD		 3643 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3644 if (!q_vector->rxr_count || !q_vector->txr_count) {
3645 if (q_vector->txr_count == 1)
3646 napi->poll = &ixgbe_clean_txonly;
3647 else if (q_vector->rxr_count == 1)
3648 napi->poll = &ixgbe_clean_rxonly;
3649 }
3650 }
f0848276
JB		 3651
3652 napi_enable(napi);
021230d4
AV		 3653 }
3654}
3655
3656static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3657{
3658 int q_idx;
3659 struct ixgbe_q_vector *q_vector;
3660 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3661
3662 /* legacy and MSI only use one vector */
3663 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3664 q_vectors = 1;
3665
3666 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3667 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3668 napi_disable(&q_vector->napi);
3669 }
3670}
3671
7a6b6f51 3672#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3673/*
3674 * ixgbe_configure_dcb - Configure DCB hardware
3675 * @adapter: ixgbe adapter struct
3676 *
3677 * This is called by the driver on open to configure the DCB hardware.
3678 * This is also called by the gennetlink interface when reconfiguring
3679 * the DCB state.
3680 */
3681static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3682{
3683 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3684 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3685
67ebd791
AD		 3686 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3687 if (hw->mac.type == ixgbe_mac_82598EB)
3688 netif_set_gso_max_size(adapter->netdev, 65536);
3689 return;
3690 }
3691
3692 if (hw->mac.type == ixgbe_mac_82598EB)
3693 netif_set_gso_max_size(adapter->netdev, 32768);
3694
2f90b865 3695
2f90b865 3696 /* Enable VLAN tag insert/strip */
f62bbb5e 3697 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3698
2f90b865 3699 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3700
3701 /* reconfigure the hardware */
c27931da
JF		 3702 if (adapter->dcbx_cap & (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE)) {
3703#ifdef CONFIG_FCOE
3704 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3705 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3706#endif
3707 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3708 DCB_TX_CONFIG);
3709 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3710 DCB_RX_CONFIG);
3711 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3712 } else {
3713 struct net_device *dev = adapter->netdev;
3714
3715 if (adapter->ixgbe_ieee_ets)
3716 dev->dcbnl_ops->ieee_setets(dev,
3717 adapter->ixgbe_ieee_ets);
3718 if (adapter->ixgbe_ieee_pfc)
3719 dev->dcbnl_ops->ieee_setpfc(dev,
3720 adapter->ixgbe_ieee_pfc);
3721 }
8187cd48
JF		 3722
3723 /* Enable RSS Hash per TC */
3724 if (hw->mac.type != ixgbe_mac_82598EB) {
3725 int i;
3726 u32 reg = 0;
3727
3728 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3729 u8 msb = 0;
3730 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3731
3732 while (cnt >>= 1)
3733 msb++;
3734
3735 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3736 }
3737 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3738 }
2f90b865
AD		 3739}
3740
3741#endif
9a799d71
AK		 3742static void ixgbe_configure(struct ixgbe_adapter *adapter)
3743{
3744 struct net_device *netdev = adapter->netdev;
c4cf55e5 3745 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3746 int i;
3747
7a6b6f51 3748#ifdef CONFIG_IXGBE_DCB
67ebd791 3749 ixgbe_configure_dcb(adapter);
2f90b865 3750#endif
9a799d71 3751
f62bbb5e
JG		 3752 ixgbe_set_rx_mode(netdev);
3753 ixgbe_restore_vlan(adapter);
3754
eacd73f7
YZ		 3755#ifdef IXGBE_FCOE
3756 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3757 ixgbe_configure_fcoe(adapter);
3758
3759#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3760 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3761 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3762 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3763 adapter->atr_sample_rate;
c4cf55e5
PWJ		 3764 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3765 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3766 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3767 }
933d41f1 3768 ixgbe_configure_virtualization(adapter);
c4cf55e5 3769
9a799d71
AK		 3770 ixgbe_configure_tx(adapter);
3771 ixgbe_configure_rx(adapter);
9a799d71
AK		 3772}
3773
e8e26350
PW		 3774static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3775{
3776 switch (hw->phy.type) {
3777 case ixgbe_phy_sfp_avago:
3778 case ixgbe_phy_sfp_ftl:
3779 case ixgbe_phy_sfp_intel:
3780 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3781 case ixgbe_phy_sfp_passive_tyco:
3782 case ixgbe_phy_sfp_passive_unknown:
3783 case ixgbe_phy_sfp_active_unknown:
3784 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3785 return true;
3786 default:
3787 return false;
3788 }
3789}
3790
0ecc061d 3791/**
e8e26350
PW		 3792 * ixgbe_sfp_link_config - set up SFP+ link
3793 * @adapter: pointer to private adapter struct
3794 **/
3795static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3796{
7086400d
AD		 3797 /*
3798 * We are assuming the worst case scenerio here, and that
3799 * is that an SFP was inserted/removed after the reset
3800 * but before SFP detection was enabled. As such the best
3801 * solution is to just start searching as soon as we start
3802 */
3803 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3804 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3805
7086400d 3806 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3807}
3808
3809/**
3810 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3811 * @hw: pointer to private hardware struct
3812 *
3813 * Returns 0 on success, negative on failure
3814 **/
e8e26350 3815static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3816{
3817 u32 autoneg;
8620a103 3818 bool negotiation, link_up = false;
0ecc061d
PWJ		 3819 u32 ret = IXGBE_ERR_LINK_SETUP;
3820
3821 if (hw->mac.ops.check_link)
3822 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3823
3824 if (ret)
3825 goto link_cfg_out;
3826
0b0c2b31
ET		 3827 autoneg = hw->phy.autoneg_advertised;
3828 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3829 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3830 &negotiation);
0ecc061d
PWJ		 3831 if (ret)
3832 goto link_cfg_out;
3833
8620a103
MC		 3834 if (hw->mac.ops.setup_link)
3835 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3836link_cfg_out:
3837 return ret;
3838}
3839
a34bcfff 3840static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3841{
9a799d71 3842 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3843 u32 gpie = 0;
9a799d71 3844
9b471446 3845 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3846 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3847 IXGBE_GPIE_OCD;
3848 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3849 /*
3850 * use EIAM to auto-mask when MSI-X interrupt is asserted
3851 * this saves a register write for every interrupt
3852 */
3853 switch (hw->mac.type) {
3854 case ixgbe_mac_82598EB:
3855 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3856 break;
9b471446 3857 case ixgbe_mac_82599EB:
b93a2226
DS		 3858 case ixgbe_mac_X540:
3859 default:
9b471446
JB		 3860 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3861 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3862 break;
3863 }
3864 } else {
021230d4
AV		 3865 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3866 * specifically only auto mask tx and rx interrupts */
3867 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3868 }
9a799d71 3869
a34bcfff
AD		 3870 /* XXX: to interrupt immediately for EICS writes, enable this */
3871 /* gpie |= IXGBE_GPIE_EIMEN; */
3872
3873 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3874 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3875 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3876 }
3877
a34bcfff
AD		 3878 /* Enable fan failure interrupt */
3879 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3880 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3881
2698b208 3882 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3883 gpie |= IXGBE_SDP1_GPIEN;
3884 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3885 }
a34bcfff
AD		 3886
3887 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3888}
3889
3890static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3891{
3892 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3893 int err;
a34bcfff
AD		 3894 u32 ctrl_ext;
3895
3896 ixgbe_get_hw_control(adapter);
3897 ixgbe_setup_gpie(adapter);
e8e26350 3898
9a799d71
AK		 3899 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3900 ixgbe_configure_msix(adapter);
3901 else
3902 ixgbe_configure_msi_and_legacy(adapter);
3903
c6ecf39a
DS		 3904 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3905 if (hw->mac.ops.enable_tx_laser &&
3906 ((hw->phy.multispeed_fiber) ||
9f911707 3907 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3908 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3909 hw->mac.ops.enable_tx_laser(hw);
3910
9a799d71 3911 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3912 ixgbe_napi_enable_all(adapter);
3913
73c4b7cd
AD		 3914 if (ixgbe_is_sfp(hw)) {
3915 ixgbe_sfp_link_config(adapter);
3916 } else {
3917 err = ixgbe_non_sfp_link_config(hw);
3918 if (err)
3919 e_err(probe, "link_config FAILED %d\n", err);
3920 }
3921
021230d4
AV		 3922 /* clear any pending interrupts, may auto mask */
3923 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3924 ixgbe_irq_enable(adapter, true, true);
9a799d71 3925
bf069c97
DS		 3926 /*
3927 * If this adapter has a fan, check to see if we had a failure
3928 * before we enabled the interrupt.
3929 */
3930 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3931 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3932 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3933 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3934 }
3935
1da100bb 3936 /* enable transmits */
477de6ed 3937 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3938
9a799d71
AK		 3939 /* bring the link up in the watchdog, this could race with our first
3940 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3941 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3942 adapter->link_check_timeout = jiffies;
7086400d 3943 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3944
3945 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3946 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3947 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3948 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3949
9a799d71
AK		 3950 return 0;
3951}
3952
d4f80882
AV		 3953void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3954{
3955 WARN_ON(in_interrupt());
7086400d
AD		 3956 /* put off any impending NetWatchDogTimeout */
3957 adapter->netdev->trans_start = jiffies;
3958
d4f80882 3959 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3960 usleep_range(1000, 2000);
d4f80882 3961 ixgbe_down(adapter);
5809a1ae
GR		 3962 /*
3963 * If SR-IOV enabled then wait a bit before bringing the adapter
3964 * back up to give the VFs time to respond to the reset. The
3965 * two second wait is based upon the watchdog timer cycle in
3966 * the VF driver.
3967 */
3968 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3969 msleep(2000);
d4f80882
AV		 3970 ixgbe_up(adapter);
3971 clear_bit(__IXGBE_RESETTING, &adapter->state);
3972}
3973
9a799d71
AK		 3974int ixgbe_up(struct ixgbe_adapter *adapter)
3975{
3976 /* hardware has been reset, we need to reload some things */
3977 ixgbe_configure(adapter);
3978
3979 return ixgbe_up_complete(adapter);
3980}
3981
3982void ixgbe_reset(struct ixgbe_adapter *adapter)
3983{
c44ade9e 3984 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3985 int err;
3986
7086400d
AD		 3987 /* lock SFP init bit to prevent race conditions with the watchdog */
3988 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3989 usleep_range(1000, 2000);
3990
3991 /* clear all SFP and link config related flags while holding SFP_INIT */
3992 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3993 IXGBE_FLAG2_SFP_NEEDS_RESET);
3994 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3995
8ca783ab 3996 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3997 switch (err) {
3998 case 0:
3999 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4000 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4001 break;
4002 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4003 e_dev_err("master disable timed out\n");
da4dd0f7 4004 break;
794caeb2
PWJ		 4005 case IXGBE_ERR_EEPROM_VERSION:
4006 /* We are running on a pre-production device, log a warning */
849c4542
ET		 4007 e_dev_warn("This device is a pre-production adapter/LOM. "
4008 "Please be aware there may be issuesassociated with "
4009 "your hardware. If you are experiencing problems "
4010 "please contact your Intel or hardware "
4011 "representative who provided you with this "
4012 "hardware.\n");
794caeb2 4013 break;
da4dd0f7 4014 default:
849c4542 4015 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4016 }
9a799d71 4017
7086400d
AD		 4018 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4019
9a799d71 4020 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 4021 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4022 IXGBE_RAH_AV);
9a799d71
AK		 4023}
4024
9a799d71
AK		 4025/**
4026 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4027 * @rx_ring: ring to free buffers from
4028 **/
b6ec895e 4029static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4030{
b6ec895e 4031 struct device *dev = rx_ring->dev;
9a799d71 4032 unsigned long size;
b6ec895e 4033 u16 i;
9a799d71 4034
84418e3b
AD		 4035 /* ring already cleared, nothing to do */
4036 if (!rx_ring->rx_buffer_info)
4037 return;
9a799d71 4038
84418e3b 4039 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 4040 for (i = 0; i < rx_ring->count; i++) {
4041 struct ixgbe_rx_buffer *rx_buffer_info;
4042
4043 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4044 if (rx_buffer_info->dma) {
b6ec895e 4045 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 4046 rx_ring->rx_buf_len,
1b507730 4047 DMA_FROM_DEVICE);
9a799d71
AK		 4048 rx_buffer_info->dma = 0;
4049 }
4050 if (rx_buffer_info->skb) {
f8212f97 4051 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 4052 rx_buffer_info->skb = NULL;
f8212f97
AD		 4053 do {
4054 struct sk_buff *this = skb;
e8171aaa 4055 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 4056 dma_unmap_single(dev,
1b507730 4057 IXGBE_RSC_CB(this)->dma,
e8e9f696 4058 rx_ring->rx_buf_len,
1b507730 4059 DMA_FROM_DEVICE);
fd3686a8 4060 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 4061 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 4062 }
f8212f97
AD		 4063 skb = skb->prev;
4064 dev_kfree_skb(this);
4065 } while (skb);
9a799d71
AK		 4066 }
4067 if (!rx_buffer_info->page)
4068 continue;
4f57ca6e 4069 if (rx_buffer_info->page_dma) {
b6ec895e 4070 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 4071 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 4072 rx_buffer_info->page_dma = 0;
4073 }
9a799d71
AK		 4074 put_page(rx_buffer_info->page);
4075 rx_buffer_info->page = NULL;
762f4c57 4076 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4077 }
4078
4079 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4080 memset(rx_ring->rx_buffer_info, 0, size);
4081
4082 /* Zero out the descriptor ring */
4083 memset(rx_ring->desc, 0, rx_ring->size);
4084
4085 rx_ring->next_to_clean = 0;
4086 rx_ring->next_to_use = 0;
9a799d71
AK		 4087}
4088
4089/**
4090 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4091 * @tx_ring: ring to be cleaned
4092 **/
b6ec895e 4093static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4094{
4095 struct ixgbe_tx_buffer *tx_buffer_info;
4096 unsigned long size;
b6ec895e 4097 u16 i;
9a799d71 4098
84418e3b
AD		 4099 /* ring already cleared, nothing to do */
4100 if (!tx_ring->tx_buffer_info)
4101 return;
9a799d71 4102
84418e3b 4103 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4104 for (i = 0; i < tx_ring->count; i++) {
4105 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4106 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4107 }
4108
4109 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4110 memset(tx_ring->tx_buffer_info, 0, size);
4111
4112 /* Zero out the descriptor ring */
4113 memset(tx_ring->desc, 0, tx_ring->size);
4114
4115 tx_ring->next_to_use = 0;
4116 tx_ring->next_to_clean = 0;
9a799d71
AK		 4117}
4118
4119/**
021230d4 4120 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4121 * @adapter: board private structure
4122 **/
021230d4 4123static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4124{
4125 int i;
4126
021230d4 4127 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4128 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4129}
4130
4131/**
021230d4 4132 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4133 * @adapter: board private structure
4134 **/
021230d4 4135static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4136{
4137 int i;
4138
021230d4 4139 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4140 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4141}
4142
4143void ixgbe_down(struct ixgbe_adapter *adapter)
4144{
4145 struct net_device *netdev = adapter->netdev;
7f821875 4146 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4147 u32 rxctrl;
7f821875 4148 u32 txdctl;
bf29ee6c 4149 int i;
b25ebfd2 4150 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 4151
4152 /* signal that we are down to the interrupt handler */
4153 set_bit(__IXGBE_DOWN, &adapter->state);
4154
767081ad
GR		 4155 /* disable receive for all VFs and wait one second */
4156 if (adapter->num_vfs) {
767081ad
GR		 4157 /* ping all the active vfs to let them know we are going down */
4158 ixgbe_ping_all_vfs(adapter);
581d1aa7 4159
767081ad
GR		 4160 /* Disable all VFTE/VFRE TX/RX */
4161 ixgbe_disable_tx_rx(adapter);
581d1aa7
GR		 4162
4163 /* Mark all the VFs as inactive */
4164 for (i = 0 ; i < adapter->num_vfs; i++)
4165 adapter->vfinfo[i].clear_to_send = 0;
767081ad
GR		 4166 }
4167
9a799d71 4168 /* disable receives */
7f821875
JB		 4169 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4170 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4171
2d39d576
YZ		 4172 /* disable all enabled rx queues */
4173 for (i = 0; i < adapter->num_rx_queues; i++)
4174 /* this call also flushes the previous write */
4175 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4176
032b4325 4177 usleep_range(10000, 20000);
9a799d71 4178
7f821875
JB		 4179 netif_tx_stop_all_queues(netdev);
4180
7086400d 4181 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4182 netif_carrier_off(netdev);
4183 netif_tx_disable(netdev);
4184
4185 ixgbe_irq_disable(adapter);
4186
4187 ixgbe_napi_disable_all(adapter);
4188
7086400d
AD		 4189 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4190
4191 del_timer_sync(&adapter->service_timer);
4192
b25ebfd2
PW		 4193 /* Cleanup the affinity_hint CPU mask memory and callback */
4194 for (i = 0; i < num_q_vectors; i++) {
4195 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4196 /* clear the affinity_mask in the IRQ descriptor */
4197 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4198 /* release the CPU mask memory */
4199 free_cpumask_var(q_vector->affinity_mask);
4200 }
4201
c4cf55e5
PWJ		 4202 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4203 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4204 cancel_work_sync(&adapter->fdir_reinit_task);
4205
119fc60a
MC		 4206 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4207 cancel_work_sync(&adapter->check_overtemp_task);
4208
7f821875
JB		 4209 /* disable transmits in the hardware now that interrupts are off */
4210 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c
AD		 4211 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4212 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4213 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
e8e9f696 4214 (txdctl & ~IXGBE_TXDCTL_ENABLE));
7f821875 4215 }
88512539 4216 /* Disable the Tx DMA engine on 82599 */
bd508178
AD		 4217 switch (hw->mac.type) {
4218 case ixgbe_mac_82599EB:
b93a2226 4219 case ixgbe_mac_X540:
88512539 4220 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4221 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4222 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4223 break;
4224 default:
4225 break;
4226 }
7f821875 4227
6f4a0e45
PL		 4228 if (!pci_channel_offline(adapter->pdev))
4229 ixgbe_reset(adapter);
c6ecf39a
DS		 4230
4231 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4232 if (hw->mac.ops.disable_tx_laser &&
4233 ((hw->phy.multispeed_fiber) ||
9f911707 4234 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4235 (hw->mac.type == ixgbe_mac_82599EB))))
4236 hw->mac.ops.disable_tx_laser(hw);
4237
9a799d71
AK		 4238 ixgbe_clean_all_tx_rings(adapter);
4239 ixgbe_clean_all_rx_rings(adapter);
4240
5dd2d332 4241#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4242 /* since we reset the hardware DCA settings were cleared */
e35ec126 4243 ixgbe_setup_dca(adapter);
96b0e0f6 4244#endif
9a799d71
AK		 4245}
4246
9a799d71 4247/**
021230d4
AV		 4248 * ixgbe_poll - NAPI Rx polling callback
4249 * @napi: structure for representing this polling device
4250 * @budget: how many packets driver is allowed to clean
4251 *
4252 * This function is used for legacy and MSI, NAPI mode
9a799d71 4253 **/
021230d4 4254static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4255{
9a1a69ad 4256 struct ixgbe_q_vector *q_vector =
e8e9f696 4257 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4258 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 4259 int tx_clean_complete, work_done = 0;
9a799d71 4260
5dd2d332 4261#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4262 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4263 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4264#endif
4265
4a0b9ca0
PW		 4266 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4267 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 4268
9a1a69ad 4269 if (!tx_clean_complete)
d2c7ddd6
DM		 4270 work_done = budget;
4271
53e52c72
DM		 4272 /* If budget not fully consumed, exit the polling mode */
4273 if (work_done < budget) {
288379f0 4274 napi_complete(napi);
f7554a2b 4275 if (adapter->rx_itr_setting & 1)
f494e8fa 4276 ixgbe_set_itr(adapter);
d4f80882 4277 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 4278 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 4279 }
9a799d71
AK		 4280 return work_done;
4281}
4282
4283/**
4284 * ixgbe_tx_timeout - Respond to a Tx Hang
4285 * @netdev: network interface device structure
4286 **/
4287static void ixgbe_tx_timeout(struct net_device *netdev)
4288{
4289 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4290
c84d324c
JF		 4291 adapter->tx_timeout_count++;
4292
9a799d71
AK		 4293 /* Do the reset outside of interrupt context */
4294 schedule_work(&adapter->reset_task);
4295}
4296
4297static void ixgbe_reset_task(struct work_struct *work)
4298{
4299 struct ixgbe_adapter *adapter;
4300 adapter = container_of(work, struct ixgbe_adapter, reset_task);
4301
2f90b865
AD		 4302 /* If we're already down or resetting, just bail */
4303 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4304 test_bit(__IXGBE_RESETTING, &adapter->state))
4305 return;
4306
dcd79aeb
TI		 4307 ixgbe_dump(adapter);
4308 netdev_err(adapter->netdev, "Reset adapter\n");
d4f80882 4309 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4310}
4311
4df10466
JB		 4312/**
4313 * ixgbe_set_rss_queues: Allocate queues for RSS
4314 * @adapter: board private structure to initialize
4315 *
4316 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4317 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4318 *
4319 **/
bc97114d
PWJ		 4320static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4321{
4322 bool ret = false;
0cefafad 4323 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4324
4325 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4326 f->mask = 0xF;
4327 adapter->num_rx_queues = f->indices;
4328 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4329 ret = true;
4330 } else {
bc97114d 4331 ret = false;
b9804972
JB		 4332 }
4333
bc97114d
PWJ		 4334 return ret;
4335}
4336
c4cf55e5
PWJ		 4337/**
4338 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4339 * @adapter: board private structure to initialize
4340 *
4341 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4342 * to the original CPU that initiated the Tx session. This runs in addition
4343 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4344 * Rx load across CPUs using RSS.
4345 *
4346 **/
e8e9f696 4347static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4348{
4349 bool ret = false;
4350 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4351
4352 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4353 f_fdir->mask = 0;
4354
4355 /* Flow Director must have RSS enabled */
4356 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4357 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4358 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4359 adapter->num_tx_queues = f_fdir->indices;
4360 adapter->num_rx_queues = f_fdir->indices;
4361 ret = true;
4362 } else {
4363 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4364 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4365 }
4366 return ret;
4367}
4368
0331a832
YZ		 4369#ifdef IXGBE_FCOE
4370/**
4371 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4372 * @adapter: board private structure to initialize
4373 *
4374 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4375 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4376 * rx queues out of the max number of rx queues, instead, it is used as the
4377 * index of the first rx queue used by FCoE.
4378 *
4379 **/
4380static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4381{
0331a832
YZ		 4382 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4383
e5b64635
JF		 4384 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4385 return false;
4386
4387 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
0331a832 4388#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4389 int tc;
4390 struct net_device *dev = adapter->netdev;
4391
4392 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4393 f->indices = dev->tc_to_txq[tc].count;
4394 f->mask = dev->tc_to_txq[tc].offset;
0331a832 4395#endif
e5b64635
JF		 4396 } else {
4397 f->indices = min((int)num_online_cpus(), f->indices);
4398
4399 adapter->num_rx_queues = 1;
4400 adapter->num_tx_queues = 1;
4401
0331a832 4402 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
396e799c 4403 e_info(probe, "FCoE enabled with RSS\n");
8faa2a78
YZ		 4404 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4405 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4406 ixgbe_set_fdir_queues(adapter);
4407 else
4408 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 4409 }
4410 /* adding FCoE rx rings to the end */
4411 f->mask = adapter->num_rx_queues;
4412 adapter->num_rx_queues += f->indices;
8de8b2e6 4413 adapter->num_tx_queues += f->indices;
e5b64635 4414 }
0331a832 4415
e5b64635
JF		 4416 return true;
4417}
4418#endif /* IXGBE_FCOE */
4419
4420#ifdef CONFIG_IXGBE_DCB
4421static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4422{
4423 bool ret = false;
4424 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4425 int i, q;
4426
4427 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4428 return ret;
4429
4430 f->indices = 0;
4431 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
4432 q = min((int)num_online_cpus(), MAX_TRAFFIC_CLASS);
4433 f->indices += q;
0331a832
YZ		 4434 }
4435
e5b64635
JF		 4436 f->mask = 0x7 << 3;
4437 adapter->num_rx_queues = f->indices;
4438 adapter->num_tx_queues = f->indices;
4439 ret = true;
4440
4441#ifdef IXGBE_FCOE
4442 /* FCoE enabled queues require special configuration done through
4443 * configure_fcoe() and others. Here we map FCoE indices onto the
4444 * DCB queue pairs allowing FCoE to own configuration later.
4445 */
4446 ixgbe_set_fcoe_queues(adapter);
4447#endif
4448
0331a832
YZ		 4449 return ret;
4450}
e5b64635 4451#endif
0331a832 4452
1cdd1ec8
GR		 4453/**
4454 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4455 * @adapter: board private structure to initialize
4456 *
4457 * IOV doesn't actually use anything, so just NAK the
4458 * request for now and let the other queue routines
4459 * figure out what to do.
4460 */
4461static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4462{
4463 return false;
4464}
4465
4df10466 4466/*
25985edc 4467 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4468 * @adapter: board private structure to initialize
4469 *
4470 * This is the top level queue allocation routine. The order here is very
4471 * important, starting with the "most" number of features turned on at once,
4472 * and ending with the smallest set of features. This way large combinations
4473 * can be allocated if they're turned on, and smaller combinations are the
4474 * fallthrough conditions.
4475 *
4476 **/
847f53ff 4477static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4478{
1cdd1ec8
GR		 4479 /* Start with base case */
4480 adapter->num_rx_queues = 1;
4481 adapter->num_tx_queues = 1;
4482 adapter->num_rx_pools = adapter->num_rx_queues;
4483 adapter->num_rx_queues_per_pool = 1;
4484
4485 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4486 goto done;
1cdd1ec8 4487
bc97114d
PWJ		 4488#ifdef CONFIG_IXGBE_DCB
4489 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4490 goto done;
bc97114d
PWJ		 4491
4492#endif
e5b64635
JF		 4493#ifdef IXGBE_FCOE
4494 if (ixgbe_set_fcoe_queues(adapter))
4495 goto done;
4496
4497#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4498 if (ixgbe_set_fdir_queues(adapter))
4499 goto done;
4500
bc97114d 4501 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4502 goto done;
4503
4504 /* fallback to base case */
4505 adapter->num_rx_queues = 1;
4506 adapter->num_tx_queues = 1;
4507
4508done:
847f53ff 4509 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4510 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4511 return netif_set_real_num_rx_queues(adapter->netdev,
4512 adapter->num_rx_queues);
b9804972
JB		 4513}
4514
021230d4 4515static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4516 int vectors)
021230d4
AV		 4517{
4518 int err, vector_threshold;
4519
4520 /* We'll want at least 3 (vector_threshold):
4521 * 1) TxQ[0] Cleanup
4522 * 2) RxQ[0] Cleanup
4523 * 3) Other (Link Status Change, etc.)
4524 * 4) TCP Timer (optional)
4525 */
4526 vector_threshold = MIN_MSIX_COUNT;
4527
4528 /* The more we get, the more we will assign to Tx/Rx Cleanup
4529 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4530 * Right now, we simply care about how many we'll get; we'll
4531 * set them up later while requesting irq's.
4532 */
4533 while (vectors >= vector_threshold) {
4534 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4535 vectors);
021230d4
AV		 4536 if (!err) /* Success in acquiring all requested vectors. */
4537 break;
4538 else if (err < 0)
4539 vectors = 0; /* Nasty failure, quit now */
4540 else /* err == number of vectors we should try again with */
4541 vectors = err;
4542 }
4543
4544 if (vectors < vector_threshold) {
4545 /* Can't allocate enough MSI-X interrupts? Oh well.
4546 * This just means we'll go with either a single MSI
4547 * vector or fall back to legacy interrupts.
4548 */
849c4542
ET		 4549 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4550 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4551 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4552 kfree(adapter->msix_entries);
4553 adapter->msix_entries = NULL;
021230d4
AV		 4554 } else {
4555 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4556 /*
4557 * Adjust for only the vectors we'll use, which is minimum
4558 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4559 * vectors we were allocated.
4560 */
4561 adapter->num_msix_vectors = min(vectors,
e8e9f696 4562 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4563 }
4564}
4565
021230d4 4566/**
bc97114d 4567 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4568 * @adapter: board private structure to initialize
4569 *
bc97114d
PWJ		 4570 * Cache the descriptor ring offsets for RSS to the assigned rings.
4571 *
021230d4 4572 **/
bc97114d 4573static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4574{
bc97114d 4575 int i;
bc97114d 4576
9d6b758f
AD		 4577 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4578 return false;
bc97114d 4579
9d6b758f
AD		 4580 for (i = 0; i < adapter->num_rx_queues; i++)
4581 adapter->rx_ring[i]->reg_idx = i;
4582 for (i = 0; i < adapter->num_tx_queues; i++)
4583 adapter->tx_ring[i]->reg_idx = i;
4584
4585 return true;
bc97114d
PWJ		 4586}
4587
4588#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4589
4590/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4591static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4592 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4593{
4594 struct net_device *dev = adapter->netdev;
4595 struct ixgbe_hw *hw = &adapter->hw;
4596 u8 num_tcs = netdev_get_num_tc(dev);
4597
4598 *tx = 0;
4599 *rx = 0;
4600
4601 switch (hw->mac.type) {
4602 case ixgbe_mac_82598EB:
4603 *tx = tc << 3;
4604 *rx = tc << 2;
4605 break;
4606 case ixgbe_mac_82599EB:
4607 case ixgbe_mac_X540:
4608 if (num_tcs == 8) {
4609 if (tc < 3) {
4610 *tx = tc << 5;
4611 *rx = tc << 4;
4612 } else if (tc < 5) {
4613 *tx = ((tc + 2) << 4);
4614 *rx = tc << 4;
4615 } else if (tc < num_tcs) {
4616 *tx = ((tc + 8) << 3);
4617 *rx = tc << 4;
4618 }
4619 } else if (num_tcs == 4) {
4620 *rx = tc << 5;
4621 switch (tc) {
4622 case 0:
4623 *tx = 0;
4624 break;
4625 case 1:
4626 *tx = 64;
4627 break;
4628 case 2:
4629 *tx = 96;
4630 break;
4631 case 3:
4632 *tx = 112;
4633 break;
4634 default:
4635 break;
4636 }
4637 }
4638 break;
4639 default:
4640 break;
4641 }
4642}
4643
4644#define IXGBE_MAX_Q_PER_TC (IXGBE_MAX_DCB_INDICES / MAX_TRAFFIC_CLASS)
4645
4646/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
4647 * classes.
4648 *
4649 * @netdev: net device to configure
4650 * @tc: number of traffic classes to enable
4651 */
4652int ixgbe_setup_tc(struct net_device *dev, u8 tc)
4653{
4654 int i;
4655 unsigned int q, offset = 0;
4656
4657 if (!tc) {
4658 netdev_reset_tc(dev);
4659 } else {
24095aa3
JF		 4660 struct ixgbe_adapter *adapter = netdev_priv(dev);
4661
4662 /* Hardware supports up to 8 traffic classes */
4663 if (tc > MAX_TRAFFIC_CLASS || netdev_set_num_tc(dev, tc))
e5b64635
JF		 4664 return -EINVAL;
4665
4666 /* Partition Tx queues evenly amongst traffic classes */
4667 for (i = 0; i < tc; i++) {
4668 q = min((int)num_online_cpus(), IXGBE_MAX_Q_PER_TC);
4669 netdev_set_prio_tc_map(dev, i, i);
4670 netdev_set_tc_queue(dev, i, q, offset);
4671 offset += q;
4672 }
24095aa3
JF		 4673
4674 /* This enables multiple traffic class support in the hardware
4675 * which defaults to strict priority transmission by default.
4676 * If traffic classes are already enabled perhaps through DCB
4677 * code path then existing configuration will be used.
4678 */
4679 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
4680 dev->dcbnl_ops && dev->dcbnl_ops->setdcbx) {
4681 struct ieee_ets ets = {
4682 .prio_tc = {0, 1, 2, 3, 4, 5, 6, 7},
4683 };
4684 u8 mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
4685
4686 dev->dcbnl_ops->setdcbx(dev, mode);
4687 dev->dcbnl_ops->ieee_setets(dev, &ets);
4688 }
e5b64635
JF		 4689 }
4690 return 0;
4691}
4692
bc97114d
PWJ		 4693/**
4694 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4695 * @adapter: board private structure to initialize
4696 *
4697 * Cache the descriptor ring offsets for DCB to the assigned rings.
4698 *
4699 **/
4700static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4701{
e5b64635
JF		 4702 struct net_device *dev = adapter->netdev;
4703 int i, j, k;
4704 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4705
bd508178
AD		 4706 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4707 return false;
f92ef202 4708
e5b64635
JF		 4709 for (i = 0, k = 0; i < num_tcs; i++) {
4710 unsigned int tx_s, rx_s;
4711 u16 count = dev->tc_to_txq[i].count;
4712
4713 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4714 for (j = 0; j < count; j++, k++) {
4715 adapter->tx_ring[k]->reg_idx = tx_s + j;
4716 adapter->rx_ring[k]->reg_idx = rx_s + j;
4717 adapter->tx_ring[k]->dcb_tc = i;
4718 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4719 }
021230d4 4720 }
e5b64635
JF		 4721
4722 return true;
bc97114d
PWJ		 4723}
4724#endif
4725
c4cf55e5
PWJ		 4726/**
4727 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4728 * @adapter: board private structure to initialize
4729 *
4730 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4731 *
4732 **/
e8e9f696 4733static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4734{
4735 int i;
4736 bool ret = false;
4737
4738 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4739 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4740 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4741 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4742 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4743 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4744 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4745 ret = true;
4746 }
4747
4748 return ret;
4749}
4750
0331a832
YZ		 4751#ifdef IXGBE_FCOE
4752/**
4753 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4754 * @adapter: board private structure to initialize
4755 *
4756 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4757 *
4758 */
4759static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4760{
0331a832 4761 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4762 int i;
4763 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4764
4765 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4766 return false;
0331a832 4767
bf29ee6c
AD		 4768 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4769 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4770 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4771 ixgbe_cache_ring_fdir(adapter);
4772 else
4773 ixgbe_cache_ring_rss(adapter);
8faa2a78 4774
bf29ee6c
AD		 4775 fcoe_rx_i = f->mask;
4776 fcoe_tx_i = f->mask;
0331a832 4777 }
bf29ee6c
AD		 4778 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4779 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4780 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4781 }
4782 return true;
0331a832
YZ		 4783}
4784
4785#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4786/**
4787 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4788 * @adapter: board private structure to initialize
4789 *
4790 * SR-IOV doesn't use any descriptor rings but changes the default if
4791 * no other mapping is used.
4792 *
4793 */
4794static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4795{
4a0b9ca0
PW		 4796 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4797 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4798 if (adapter->num_vfs)
4799 return true;
4800 else
4801 return false;
4802}
4803
bc97114d
PWJ		 4804/**
4805 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4806 * @adapter: board private structure to initialize
4807 *
4808 * Once we know the feature-set enabled for the device, we'll cache
4809 * the register offset the descriptor ring is assigned to.
4810 *
4811 * Note, the order the various feature calls is important. It must start with
4812 * the "most" features enabled at the same time, then trickle down to the
4813 * least amount of features turned on at once.
4814 **/
4815static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4816{
4817 /* start with default case */
4a0b9ca0
PW		 4818 adapter->rx_ring[0]->reg_idx = 0;
4819 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4820
1cdd1ec8
GR		 4821 if (ixgbe_cache_ring_sriov(adapter))
4822 return;
4823
e5b64635
JF		 4824#ifdef CONFIG_IXGBE_DCB
4825 if (ixgbe_cache_ring_dcb(adapter))
4826 return;
4827#endif
4828
0331a832
YZ		 4829#ifdef IXGBE_FCOE
4830 if (ixgbe_cache_ring_fcoe(adapter))
4831 return;
0331a832 4832#endif /* IXGBE_FCOE */
bc97114d 4833
c4cf55e5
PWJ		 4834 if (ixgbe_cache_ring_fdir(adapter))
4835 return;
4836
bc97114d
PWJ		 4837 if (ixgbe_cache_ring_rss(adapter))
4838 return;
021230d4
AV		 4839}
4840
9a799d71
AK		 4841/**
4842 * ixgbe_alloc_queues - Allocate memory for all rings
4843 * @adapter: board private structure to initialize
4844 *
4845 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4846 * number of queues at compile-time. The polling_netdev array is
4847 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4848 **/
2f90b865 4849static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4850{
e2ddeba9 4851 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4852
e2ddeba9
ED		 4853 if (nid < 0 || !node_online(nid))
4854 nid = first_online_node;
4855
4856 for (; tx < adapter->num_tx_queues; tx++) {
4857 struct ixgbe_ring *ring;
4858
4859 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4860 if (!ring)
e2ddeba9 4861 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4862 if (!ring)
e2ddeba9 4863 goto err_allocation;
4a0b9ca0 4864 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4865 ring->queue_index = tx;
4866 ring->numa_node = nid;
b6ec895e 4867 ring->dev = &adapter->pdev->dev;
fc77dc3c 4868 ring->netdev = adapter->netdev;
4a0b9ca0 4869
e2ddeba9 4870 adapter->tx_ring[tx] = ring;
021230d4 4871 }
b9804972 4872
e2ddeba9
ED		 4873 for (; rx < adapter->num_rx_queues; rx++) {
4874 struct ixgbe_ring *ring;
4a0b9ca0 4875
e2ddeba9 4876 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4877 if (!ring)
e2ddeba9 4878 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4879 if (!ring)
e2ddeba9
ED		 4880 goto err_allocation;
4881 ring->count = adapter->rx_ring_count;
4882 ring->queue_index = rx;
4883 ring->numa_node = nid;
b6ec895e 4884 ring->dev = &adapter->pdev->dev;
fc77dc3c 4885 ring->netdev = adapter->netdev;
4a0b9ca0 4886
e2ddeba9 4887 adapter->rx_ring[rx] = ring;
021230d4
AV		 4888 }
4889
4890 ixgbe_cache_ring_register(adapter);
4891
4892 return 0;
4893
e2ddeba9
ED		 4894err_allocation:
4895 while (tx)
4896 kfree(adapter->tx_ring[--tx]);
4897
4898 while (rx)
4899 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4900 return -ENOMEM;
4901}
4902
4903/**
4904 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4905 * @adapter: board private structure to initialize
4906 *
4907 * Attempt to configure the interrupts using the best available
4908 * capabilities of the hardware and the kernel.
4909 **/
feea6a57 4910static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4911{
8be0e467 4912 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4913 int err = 0;
4914 int vector, v_budget;
4915
4916 /*
4917 * It's easy to be greedy for MSI-X vectors, but it really
4918 * doesn't do us much good if we have a lot more vectors
4919 * than CPU's. So let's be conservative and only ask for
342bde1b 4920 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4921 */
4922 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4923 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4924
4925 /*
4926 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4927 * hw.mac->max_msix_vectors vectors. With features
4928 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4929 * descriptor queues supported by our device. Thus, we cap it off in
4930 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4931 */
8be0e467 4932 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4933
4934 /* A failure in MSI-X entry allocation isn't fatal, but it does
4935 * mean we disable MSI-X capabilities of the adapter. */
4936 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4937 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4938 if (adapter->msix_entries) {
4939 for (vector = 0; vector < v_budget; vector++)
4940 adapter->msix_entries[vector].entry = vector;
021230d4 4941
7a921c93 4942 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4943
7a921c93
AD		 4944 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4945 goto out;
4946 }
26d27844 4947
7a921c93
AD		 4948 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4949 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
45b9f509
AD		 4950 if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4951 IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4952 e_err(probe,
4953 "Flow Director is not supported while multiple "
4954 "queues are disabled. Disabling Flow Director\n");
4955 }
c4cf55e5
PWJ		 4956 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4957 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4958 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4959 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4960 ixgbe_disable_sriov(adapter);
4961
847f53ff
BH		 4962 err = ixgbe_set_num_queues(adapter);
4963 if (err)
4964 return err;
021230d4 4965
021230d4
AV		 4966 err = pci_enable_msi(adapter->pdev);
4967 if (!err) {
4968 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4969 } else {
849c4542
ET		 4970 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4971 "Unable to allocate MSI interrupt, "
4972 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4973 /* reset err */
4974 err = 0;
4975 }
4976
4977out:
021230d4
AV		 4978 return err;
4979}
4980
7a921c93
AD		 4981/**
4982 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4983 * @adapter: board private structure to initialize
4984 *
4985 * We allocate one q_vector per queue interrupt. If allocation fails we
4986 * return -ENOMEM.
4987 **/
4988static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4989{
4990 int q_idx, num_q_vectors;
4991 struct ixgbe_q_vector *q_vector;
7a921c93
AD		 4992 int (*poll)(struct napi_struct *, int);
4993
4994 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4995 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4996 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4997 } else {
4998 num_q_vectors = 1;
7a921c93
AD		 4999 poll = &ixgbe_poll;
5000 }
5001
5002 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 5003 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 5004 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 5005 if (!q_vector)
5006 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 5007 GFP_KERNEL);
7a921c93
AD		 5008 if (!q_vector)
5009 goto err_out;
5010 q_vector->adapter = adapter;
f7554a2b
NS		 5011 if (q_vector->txr_count && !q_vector->rxr_count)
5012 q_vector->eitr = adapter->tx_eitr_param;
5013 else
5014 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 5015 q_vector->v_idx = q_idx;
91281fd3 5016 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 5017 adapter->q_vector[q_idx] = q_vector;
5018 }
5019
5020 return 0;
5021
5022err_out:
5023 while (q_idx) {
5024 q_idx--;
5025 q_vector = adapter->q_vector[q_idx];
5026 netif_napi_del(&q_vector->napi);
5027 kfree(q_vector);
5028 adapter->q_vector[q_idx] = NULL;
5029 }
5030 return -ENOMEM;
5031}
5032
5033/**
5034 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5035 * @adapter: board private structure to initialize
5036 *
5037 * This function frees the memory allocated to the q_vectors. In addition if
5038 * NAPI is enabled it will delete any references to the NAPI struct prior
5039 * to freeing the q_vector.
5040 **/
5041static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5042{
5043 int q_idx, num_q_vectors;
7a921c93 5044
91281fd3 5045 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 5046 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 5047 else
7a921c93 5048 num_q_vectors = 1;
7a921c93
AD		 5049
5050 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5051 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 5052 adapter->q_vector[q_idx] = NULL;
91281fd3 5053 netif_napi_del(&q_vector->napi);
7a921c93
AD		 5054 kfree(q_vector);
5055 }
5056}
5057
7b25cdba 5058static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 5059{
5060 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5061 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5062 pci_disable_msix(adapter->pdev);
5063 kfree(adapter->msix_entries);
5064 adapter->msix_entries = NULL;
5065 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5066 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5067 pci_disable_msi(adapter->pdev);
5068 }
021230d4
AV		 5069}
5070
5071/**
5072 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5073 * @adapter: board private structure to initialize
5074 *
5075 * We determine which interrupt scheme to use based on...
5076 * - Kernel support (MSI, MSI-X)
5077 * - which can be user-defined (via MODULE_PARAM)
5078 * - Hardware queue count (num_*_queues)
5079 * - defined by miscellaneous hardware support/features (RSS, etc.)
5080 **/
2f90b865 5081int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 5082{
5083 int err;
5084
5085 /* Number of supported queues */
847f53ff
BH		 5086 err = ixgbe_set_num_queues(adapter);
5087 if (err)
5088 return err;
021230d4 5089
021230d4
AV		 5090 err = ixgbe_set_interrupt_capability(adapter);
5091 if (err) {
849c4542 5092 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 5093 goto err_set_interrupt;
9a799d71
AK		 5094 }
5095
7a921c93
AD		 5096 err = ixgbe_alloc_q_vectors(adapter);
5097 if (err) {
849c4542 5098 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 5099 goto err_alloc_q_vectors;
5100 }
5101
5102 err = ixgbe_alloc_queues(adapter);
5103 if (err) {
849c4542 5104 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 5105 goto err_alloc_queues;
5106 }
5107
849c4542 5108 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5109 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5110 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5111
5112 set_bit(__IXGBE_DOWN, &adapter->state);
5113
9a799d71 5114 return 0;
021230d4 5115
7a921c93
AD		 5116err_alloc_queues:
5117 ixgbe_free_q_vectors(adapter);
5118err_alloc_q_vectors:
5119 ixgbe_reset_interrupt_capability(adapter);
021230d4 5120err_set_interrupt:
7a921c93
AD		 5121 return err;
5122}
5123
1a51502b
ED		 5124static void ring_free_rcu(struct rcu_head *head)
5125{
5126 kfree(container_of(head, struct ixgbe_ring, rcu));
5127}
5128
7a921c93
AD		 5129/**
5130 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5131 * @adapter: board private structure to clear interrupt scheme on
5132 *
5133 * We go through and clear interrupt specific resources and reset the structure
5134 * to pre-load conditions
5135 **/
5136void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5137{
4a0b9ca0
PW		 5138 int i;
5139
5140 for (i = 0; i < adapter->num_tx_queues; i++) {
5141 kfree(adapter->tx_ring[i]);
5142 adapter->tx_ring[i] = NULL;
5143 }
5144 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 5145 struct ixgbe_ring *ring = adapter->rx_ring[i];
5146
5147 /* ixgbe_get_stats64() might access this ring, we must wait
5148 * a grace period before freeing it.
5149 */
5150 call_rcu(&ring->rcu, ring_free_rcu);
4a0b9ca0
PW		 5151 adapter->rx_ring[i] = NULL;
5152 }
7a921c93 5153
b8eb3a10
DS		 5154 adapter->num_tx_queues = 0;
5155 adapter->num_rx_queues = 0;
5156
7a921c93
AD		 5157 ixgbe_free_q_vectors(adapter);
5158 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5159}
5160
5161/**
5162 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5163 * @adapter: board private structure to initialize
5164 *
5165 * ixgbe_sw_init initializes the Adapter private data structure.
5166 * Fields are initialized based on PCI device information and
5167 * OS network device settings (MTU size).
5168 **/
5169static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5170{
5171 struct ixgbe_hw *hw = &adapter->hw;
5172 struct pci_dev *pdev = adapter->pdev;
9a713e7c 5173 struct net_device *dev = adapter->netdev;
021230d4 5174 unsigned int rss;
7a6b6f51 5175#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5176 int j;
5177 struct tc_configuration *tc;
5178#endif
16b61beb 5179 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 5180
c44ade9e
JB		 5181 /* PCI config space info */
5182
5183 hw->vendor_id = pdev->vendor;
5184 hw->device_id = pdev->device;
5185 hw->revision_id = pdev->revision;
5186 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5187 hw->subsystem_device_id = pdev->subsystem_device;
5188
021230d4
AV		 5189 /* Set capability flags */
5190 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5191 adapter->ring_feature[RING_F_RSS].indices = rss;
5192 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 5193 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bd508178
AD		 5194 switch (hw->mac.type) {
5195 case ixgbe_mac_82598EB:
bf069c97
DS		 5196 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5197 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5198 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 5199 break;
5200 case ixgbe_mac_82599EB:
b93a2226 5201 case ixgbe_mac_X540:
e8e26350 5202 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5203 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5204 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5205 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5206 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5207 /* n-tuple support exists, always init our spinlock */
5208 spin_lock_init(&adapter->fdir_perfect_lock);
5209 /* Flow Director hash filters enabled */
5210 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5211 adapter->atr_sample_rate = 20;
c4cf55e5 5212 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5213 IXGBE_MAX_FDIR_INDICES;
c4cf55e5 5214 adapter->fdir_pballoc = 0;
eacd73f7 5215#ifdef IXGBE_FCOE
0d551589
YZ		 5216 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5217 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5218 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5219#ifdef CONFIG_IXGBE_DCB
6ee16520
YZ		 5220 /* Default traffic class to use for FCoE */
5221 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
56075a98 5222 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5223#endif
eacd73f7 5224#endif /* IXGBE_FCOE */
bd508178
AD		 5225 break;
5226 default:
5227 break;
f8212f97 5228 }
2f90b865 5229
7a6b6f51 5230#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5231 /* Configure DCB traffic classes */
5232 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5233 tc = &adapter->dcb_cfg.tc_config[j];
5234 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5235 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5236 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5237 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5238 tc->dcb_pfc = pfc_disabled;
5239 }
5240 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5241 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5242 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 5243 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5244 adapter->dcb_set_bitmap = 0x00;
3032309b 5245 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5246 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5247 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5248
5249#endif
9a799d71
AK		 5250
5251 /* default flow control settings */
cd7664f6 5252 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5253 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5254#ifdef CONFIG_DCB
5255 adapter->last_lfc_mode = hw->fc.current_mode;
5256#endif
16b61beb
JF		 5257 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5258 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 5259 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5260 hw->fc.send_xon = true;
71fd570b 5261 hw->fc.disable_fc_autoneg = false;
9a799d71 5262
30efa5a3 5263 /* enable itr by default in dynamic mode */
f7554a2b
NS		 5264 adapter->rx_itr_setting = 1;
5265 adapter->rx_eitr_param = 20000;
5266 adapter->tx_itr_setting = 1;
5267 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 5268
5269 /* set defaults for eitr in MegaBytes */
5270 adapter->eitr_low = 10;
5271 adapter->eitr_high = 20;
5272
5273 /* set default ring sizes */
5274 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5275 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5276
9a799d71 5277 /* initialize eeprom parameters */
c44ade9e 5278 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5279 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5280 return -EIO;
5281 }
5282
021230d4 5283 /* enable rx csum by default */
9a799d71
AK		 5284 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5285
1a6c14a2
JB		 5286 /* get assigned NUMA node */
5287 adapter->node = dev_to_node(&pdev->dev);
5288
9a799d71
AK		 5289 set_bit(__IXGBE_DOWN, &adapter->state);
5290
5291 return 0;
5292}
5293
5294/**
5295 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5296 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5297 *
5298 * Return 0 on success, negative on failure
5299 **/
b6ec895e 5300int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5301{
b6ec895e 5302 struct device *dev = tx_ring->dev;
9a799d71
AK		 5303 int size;
5304
3a581073 5305 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5306 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5307 if (!tx_ring->tx_buffer_info)
89bf67f1 5308 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5309 if (!tx_ring->tx_buffer_info)
5310 goto err;
9a799d71
AK		 5311
5312 /* round up to nearest 4K */
12207e49 5313 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5314 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5315
b6ec895e 5316 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5317 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5318 if (!tx_ring->desc)
5319 goto err;
9a799d71 5320
3a581073
JB		 5321 tx_ring->next_to_use = 0;
5322 tx_ring->next_to_clean = 0;
5323 tx_ring->work_limit = tx_ring->count;
9a799d71 5324 return 0;
e01c31a5
JB		 5325
5326err:
5327 vfree(tx_ring->tx_buffer_info);
5328 tx_ring->tx_buffer_info = NULL;
b6ec895e 5329 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5330 return -ENOMEM;
9a799d71
AK		 5331}
5332
69888674
AD		 5333/**
5334 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5335 * @adapter: board private structure
5336 *
5337 * If this function returns with an error, then it's possible one or
5338 * more of the rings is populated (while the rest are not). It is the
5339 * callers duty to clean those orphaned rings.
5340 *
5341 * Return 0 on success, negative on failure
5342 **/
5343static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5344{
5345 int i, err = 0;
5346
5347 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5348 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5349 if (!err)
5350 continue;
396e799c 5351 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5352 break;
5353 }
5354
5355 return err;
5356}
5357
9a799d71
AK		 5358/**
5359 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5360 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5361 *
5362 * Returns 0 on success, negative on failure
5363 **/
b6ec895e 5364int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5365{
b6ec895e 5366 struct device *dev = rx_ring->dev;
021230d4 5367 int size;
9a799d71 5368
3a581073 5369 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5370 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5371 if (!rx_ring->rx_buffer_info)
89bf67f1 5372 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5373 if (!rx_ring->rx_buffer_info)
5374 goto err;
9a799d71 5375
9a799d71 5376 /* Round up to nearest 4K */
3a581073
JB		 5377 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5378 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5379
b6ec895e 5380 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5381 &rx_ring->dma, GFP_KERNEL);
9a799d71 5382
b6ec895e
AD		 5383 if (!rx_ring->desc)
5384 goto err;
9a799d71 5385
3a581073
JB		 5386 rx_ring->next_to_clean = 0;
5387 rx_ring->next_to_use = 0;
9a799d71
AK		 5388
5389 return 0;
b6ec895e
AD		 5390err:
5391 vfree(rx_ring->rx_buffer_info);
5392 rx_ring->rx_buffer_info = NULL;
5393 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5394 return -ENOMEM;
9a799d71
AK		 5395}
5396
69888674
AD		 5397/**
5398 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5399 * @adapter: board private structure
5400 *
5401 * If this function returns with an error, then it's possible one or
5402 * more of the rings is populated (while the rest are not). It is the
5403 * callers duty to clean those orphaned rings.
5404 *
5405 * Return 0 on success, negative on failure
5406 **/
69888674
AD		 5407static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5408{
5409 int i, err = 0;
5410
5411 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5412 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5413 if (!err)
5414 continue;
396e799c 5415 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5416 break;
5417 }
5418
5419 return err;
5420}
5421
9a799d71
AK		 5422/**
5423 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5424 * @tx_ring: Tx descriptor ring for a specific queue
5425 *
5426 * Free all transmit software resources
5427 **/
b6ec895e 5428void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5429{
b6ec895e 5430 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5431
5432 vfree(tx_ring->tx_buffer_info);
5433 tx_ring->tx_buffer_info = NULL;
5434
b6ec895e
AD		 5435 /* if not set, then don't free */
5436 if (!tx_ring->desc)
5437 return;
5438
5439 dma_free_coherent(tx_ring->dev, tx_ring->size,
5440 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5441
5442 tx_ring->desc = NULL;
5443}
5444
5445/**
5446 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5447 * @adapter: board private structure
5448 *
5449 * Free all transmit software resources
5450 **/
5451static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5452{
5453 int i;
5454
5455 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5456 if (adapter->tx_ring[i]->desc)
b6ec895e 5457 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5458}
5459
5460/**
b4617240 5461 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5462 * @rx_ring: ring to clean the resources from
5463 *
5464 * Free all receive software resources
5465 **/
b6ec895e 5466void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5467{
b6ec895e 5468 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5469
5470 vfree(rx_ring->rx_buffer_info);
5471 rx_ring->rx_buffer_info = NULL;
5472
b6ec895e
AD		 5473 /* if not set, then don't free */
5474 if (!rx_ring->desc)
5475 return;
5476
5477 dma_free_coherent(rx_ring->dev, rx_ring->size,
5478 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5479
5480 rx_ring->desc = NULL;
5481}
5482
5483/**
5484 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5485 * @adapter: board private structure
5486 *
5487 * Free all receive software resources
5488 **/
5489static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5490{
5491 int i;
5492
5493 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5494 if (adapter->rx_ring[i]->desc)
b6ec895e 5495 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5496}
5497
9a799d71
AK		 5498/**
5499 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5500 * @netdev: network interface device structure
5501 * @new_mtu: new value for maximum frame size
5502 *
5503 * Returns 0 on success, negative on failure
5504 **/
5505static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5506{
5507 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5508 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5509 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5510
42c783c5 5511 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5512 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5513 hw->mac.type != ixgbe_mac_X540) {
5514 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5515 return -EINVAL;
5516 } else {
5517 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5518 return -EINVAL;
5519 }
9a799d71 5520
396e799c 5521 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5522 /* must set new MTU before calling down or up */
9a799d71
AK		 5523 netdev->mtu = new_mtu;
5524
16b61beb
JF		 5525 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5526 hw->fc.low_water = FC_LOW_WATER(max_frame);
5527
d4f80882
AV		 5528 if (netif_running(netdev))
5529 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5530
5531 return 0;
5532}
5533
5534/**
5535 * ixgbe_open - Called when a network interface is made active
5536 * @netdev: network interface device structure
5537 *
5538 * Returns 0 on success, negative value on failure
5539 *
5540 * The open entry point is called when a network interface is made
5541 * active by the system (IFF_UP). At this point all resources needed
5542 * for transmit and receive operations are allocated, the interrupt
5543 * handler is registered with the OS, the watchdog timer is started,
5544 * and the stack is notified that the interface is ready.
5545 **/
5546static int ixgbe_open(struct net_device *netdev)
5547{
5548 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5549 int err;
4bebfaa5
AK		 5550
5551 /* disallow open during test */
5552 if (test_bit(__IXGBE_TESTING, &adapter->state))
5553 return -EBUSY;
9a799d71 5554
54386467
JB		 5555 netif_carrier_off(netdev);
5556
9a799d71
AK		 5557 /* allocate transmit descriptors */
5558 err = ixgbe_setup_all_tx_resources(adapter);
5559 if (err)
5560 goto err_setup_tx;
5561
9a799d71
AK		 5562 /* allocate receive descriptors */
5563 err = ixgbe_setup_all_rx_resources(adapter);
5564 if (err)
5565 goto err_setup_rx;
5566
5567 ixgbe_configure(adapter);
5568
021230d4 5569 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5570 if (err)
5571 goto err_req_irq;
5572
9a799d71
AK		 5573 err = ixgbe_up_complete(adapter);
5574 if (err)
5575 goto err_up;
5576
d55b53ff
JK		 5577 netif_tx_start_all_queues(netdev);
5578
9a799d71
AK		 5579 return 0;
5580
5581err_up:
5eba3699 5582 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5583 ixgbe_free_irq(adapter);
5584err_req_irq:
9a799d71 5585err_setup_rx:
a20a1199 5586 ixgbe_free_all_rx_resources(adapter);
9a799d71 5587err_setup_tx:
a20a1199 5588 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5589 ixgbe_reset(adapter);
5590
5591 return err;
5592}
5593
5594/**
5595 * ixgbe_close - Disables a network interface
5596 * @netdev: network interface device structure
5597 *
5598 * Returns 0, this is not allowed to fail
5599 *
5600 * The close entry point is called when an interface is de-activated
5601 * by the OS. The hardware is still under the drivers control, but
5602 * needs to be disabled. A global MAC reset is issued to stop the
5603 * hardware, and all transmit and receive resources are freed.
5604 **/
5605static int ixgbe_close(struct net_device *netdev)
5606{
5607 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5608
5609 ixgbe_down(adapter);
5610 ixgbe_free_irq(adapter);
5611
5612 ixgbe_free_all_tx_resources(adapter);
5613 ixgbe_free_all_rx_resources(adapter);
5614
5eba3699 5615 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5616
5617 return 0;
5618}
5619
b3c8b4ba
AD		 5620#ifdef CONFIG_PM
5621static int ixgbe_resume(struct pci_dev *pdev)
5622{
c60fbb00
AD		 5623 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5624 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5625 u32 err;
5626
5627 pci_set_power_state(pdev, PCI_D0);
5628 pci_restore_state(pdev);
656ab817
DS		 5629 /*
5630 * pci_restore_state clears dev->state_saved so call
5631 * pci_save_state to restore it.
5632 */
5633 pci_save_state(pdev);
9ce77666 5634
5635 err = pci_enable_device_mem(pdev);
b3c8b4ba 5636 if (err) {
849c4542 5637 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5638 return err;
5639 }
5640 pci_set_master(pdev);
5641
dd4d8ca6 5642 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5643
5644 err = ixgbe_init_interrupt_scheme(adapter);
5645 if (err) {
849c4542 5646 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5647 return err;
5648 }
5649
b3c8b4ba
AD		 5650 ixgbe_reset(adapter);
5651
495dce12
WJP		 5652 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5653
b3c8b4ba 5654 if (netif_running(netdev)) {
c60fbb00 5655 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5656 if (err)
5657 return err;
5658 }
5659
5660 netif_device_attach(netdev);
5661
5662 return 0;
5663}
b3c8b4ba 5664#endif /* CONFIG_PM */
9d8d05ae
RW		 5665
5666static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5667{
c60fbb00
AD		 5668 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5669 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5670 struct ixgbe_hw *hw = &adapter->hw;
5671 u32 ctrl, fctrl;
5672 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5673#ifdef CONFIG_PM
5674 int retval = 0;
5675#endif
5676
5677 netif_device_detach(netdev);
5678
5679 if (netif_running(netdev)) {
5680 ixgbe_down(adapter);
5681 ixgbe_free_irq(adapter);
5682 ixgbe_free_all_tx_resources(adapter);
5683 ixgbe_free_all_rx_resources(adapter);
5684 }
b3c8b4ba 5685
5f5ae6fc 5686 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5687#ifdef CONFIG_DCB
5688 kfree(adapter->ixgbe_ieee_pfc);
5689 kfree(adapter->ixgbe_ieee_ets);
5690#endif
5f5ae6fc 5691
b3c8b4ba
AD		 5692#ifdef CONFIG_PM
5693 retval = pci_save_state(pdev);
5694 if (retval)
5695 return retval;
4df10466 5696
b3c8b4ba 5697#endif
e8e26350
PW		 5698 if (wufc) {
5699 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5700
e8e26350
PW		 5701 /* turn on all-multi mode if wake on multicast is enabled */
5702 if (wufc & IXGBE_WUFC_MC) {
5703 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5704 fctrl |= IXGBE_FCTRL_MPE;
5705 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5706 }
5707
5708 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5709 ctrl |= IXGBE_CTRL_GIO_DIS;
5710 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5711
5712 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5713 } else {
5714 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5715 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5716 }
5717
bd508178
AD		 5718 switch (hw->mac.type) {
5719 case ixgbe_mac_82598EB:
dd4d8ca6 5720 pci_wake_from_d3(pdev, false);
bd508178
AD		 5721 break;
5722 case ixgbe_mac_82599EB:
b93a2226 5723 case ixgbe_mac_X540:
bd508178
AD		 5724 pci_wake_from_d3(pdev, !!wufc);
5725 break;
5726 default:
5727 break;
5728 }
b3c8b4ba 5729
9d8d05ae
RW		 5730 *enable_wake = !!wufc;
5731
b3c8b4ba
AD		 5732 ixgbe_release_hw_control(adapter);
5733
5734 pci_disable_device(pdev);
5735
9d8d05ae
RW		 5736 return 0;
5737}
5738
5739#ifdef CONFIG_PM
5740static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5741{
5742 int retval;
5743 bool wake;
5744
5745 retval = __ixgbe_shutdown(pdev, &wake);
5746 if (retval)
5747 return retval;
5748
5749 if (wake) {
5750 pci_prepare_to_sleep(pdev);
5751 } else {
5752 pci_wake_from_d3(pdev, false);
5753 pci_set_power_state(pdev, PCI_D3hot);
5754 }
b3c8b4ba
AD		 5755
5756 return 0;
5757}
9d8d05ae 5758#endif /* CONFIG_PM */
b3c8b4ba
AD		 5759
5760static void ixgbe_shutdown(struct pci_dev *pdev)
5761{
9d8d05ae
RW		 5762 bool wake;
5763
5764 __ixgbe_shutdown(pdev, &wake);
5765
5766 if (system_state == SYSTEM_POWER_OFF) {
5767 pci_wake_from_d3(pdev, wake);
5768 pci_set_power_state(pdev, PCI_D3hot);
5769 }
b3c8b4ba
AD		 5770}
5771
9a799d71
AK		 5772/**
5773 * ixgbe_update_stats - Update the board statistics counters.
5774 * @adapter: board private structure
5775 **/
5776void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5777{
2d86f139 5778 struct net_device *netdev = adapter->netdev;
9a799d71 5779 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5780 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5781 u64 total_mpc = 0;
5782 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5783 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5784 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5785 u64 bytes = 0, packets = 0;
9a799d71 5786
d08935c2
DS		 5787 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5788 test_bit(__IXGBE_RESETTING, &adapter->state))
5789 return;
5790
94b982b2 5791 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5792 u64 rsc_count = 0;
94b982b2 5793 u64 rsc_flush = 0;
d51019a4
PW		 5794 for (i = 0; i < 16; i++)
5795 adapter->hw_rx_no_dma_resources +=
7ca647bd 5796 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5797 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5798 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5799 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5800 }
5801 adapter->rsc_total_count = rsc_count;
5802 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5803 }
5804
5b7da515
AD		 5805 for (i = 0; i < adapter->num_rx_queues; i++) {
5806 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5807 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5808 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5809 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5810 bytes += rx_ring->stats.bytes;
5811 packets += rx_ring->stats.packets;
5812 }
5813 adapter->non_eop_descs = non_eop_descs;
5814 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5815 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5816 netdev->stats.rx_bytes = bytes;
5817 netdev->stats.rx_packets = packets;
5818
5819 bytes = 0;
5820 packets = 0;
7ca3bc58 5821 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5822 for (i = 0; i < adapter->num_tx_queues; i++) {
5823 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5824 restart_queue += tx_ring->tx_stats.restart_queue;
5825 tx_busy += tx_ring->tx_stats.tx_busy;
5826 bytes += tx_ring->stats.bytes;
5827 packets += tx_ring->stats.packets;
5828 }
eb985f09 5829 adapter->restart_queue = restart_queue;
5b7da515
AD		 5830 adapter->tx_busy = tx_busy;
5831 netdev->stats.tx_bytes = bytes;
5832 netdev->stats.tx_packets = packets;
7ca3bc58 5833
7ca647bd 5834 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5835 for (i = 0; i < 8; i++) {
5836 /* for packet buffers not used, the register should read 0 */
5837 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5838 missed_rx += mpc;
7ca647bd
JP		 5839 hwstats->mpc[i] += mpc;
5840 total_mpc += hwstats->mpc[i];
e8e26350 5841 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5842 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5843 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5844 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5845 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5846 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
bd508178
AD		 5847 switch (hw->mac.type) {
5848 case ixgbe_mac_82598EB:
7ca647bd
JP		 5849 hwstats->pxonrxc[i] +=
5850 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5851 break;
5852 case ixgbe_mac_82599EB:
b93a2226 5853 case ixgbe_mac_X540:
bd508178
AD		 5854 hwstats->pxonrxc[i] +=
5855 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5856 break;
5857 default:
5858 break;
e8e26350 5859 }
7ca647bd
JP		 5860 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5861 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5862 }
7ca647bd 5863 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5864 /* work around hardware counting issue */
7ca647bd 5865 hwstats->gprc -= missed_rx;
6f11eef7 5866
c84d324c
JF		 5867 ixgbe_update_xoff_received(adapter);
5868
6f11eef7 5869 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5870 switch (hw->mac.type) {
5871 case ixgbe_mac_82598EB:
5872 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5873 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5874 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5875 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5876 break;
b93a2226 5877 case ixgbe_mac_X540:
58f6bcf9
ET		 5878 /* OS2BMC stats are X540 only*/
5879 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5880 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5881 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5882 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5883 case ixgbe_mac_82599EB:
7ca647bd 5884 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5885 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5886 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5887 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5888 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5889 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5890 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5891 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5892 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5893#ifdef IXGBE_FCOE
7ca647bd
JP		 5894 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5895 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5896 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5897 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5898 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5899 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5900#endif /* IXGBE_FCOE */
bd508178
AD		 5901 break;
5902 default:
5903 break;
e8e26350 5904 }
9a799d71 5905 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5906 hwstats->bprc += bprc;
5907 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5908 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5909 hwstats->mprc -= bprc;
5910 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5911 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5912 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5913 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5914 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5915 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5916 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5917 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5918 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5919 hwstats->lxontxc += lxon;
6f11eef7 5920 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5921 hwstats->lxofftxc += lxoff;
5922 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5923 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5924 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5925 /*
5926 * 82598 errata - tx of flow control packets is included in tx counters
5927 */
5928 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5929 hwstats->gptc -= xon_off_tot;
5930 hwstats->mptc -= xon_off_tot;
5931 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5932 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5933 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5934 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5935 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5936 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5937 hwstats->ptc64 -= xon_off_tot;
5938 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5939 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5940 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5941 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5942 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5943 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5944
5945 /* Fill out the OS statistics structure */
7ca647bd 5946 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5947
5948 /* Rx Errors */
7ca647bd 5949 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5950 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5951 netdev->stats.rx_length_errors = hwstats->rlec;
5952 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5953 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5954}
5955
5956/**
93c52dd0
AD		 5957 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5958 * @work: pointer to work_struct containing our data
9a799d71 5959 **/
93c52dd0
AD		 5960static void ixgbe_fdir_reinit_task(struct work_struct *work)
5961{
5962 struct ixgbe_adapter *adapter = container_of(work,
5963 struct ixgbe_adapter,
5964 fdir_reinit_task);
5965 struct ixgbe_hw *hw = &adapter->hw;
5966 int i;
5967
5968 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5969 for (i = 0; i < adapter->num_tx_queues; i++)
5970 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5971 &(adapter->tx_ring[i]->state));
5972 } else {
5973 e_err(probe, "failed to finish FDIR re-initialization, "
5974 "ignored adding FDIR ATR filters\n");
5975 }
5976 /* Done FDIR Re-initialization, enable transmits */
5977 netif_tx_start_all_queues(adapter->netdev);
5978}
5979
5980/**
5981 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5982 * @adapter - pointer to the device adapter structure
5983 *
5984 * This function serves two purposes. First it strobes the interrupt lines
5985 * in order to make certain interrupts are occuring. Secondly it sets the
5986 * bits needed to check for TX hangs. As a result we should immediately
5987 * determine if a hang has occured.
5988 */
5989static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5990{
cf8280ee 5991 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5992 u64 eics = 0;
5993 int i;
cf8280ee 5994
93c52dd0
AD		 5995 /* If we're down or resetting, just bail */
5996 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5997 test_bit(__IXGBE_RESETTING, &adapter->state))
5998 return;
22d5a71b 5999
93c52dd0
AD		 6000 /* Force detection of hung controller */
6001 if (netif_carrier_ok(adapter->netdev)) {
6002 for (i = 0; i < adapter->num_tx_queues; i++)
6003 set_check_for_tx_hang(adapter->tx_ring[i]);
6004 }
22d5a71b 6005
fe49f04a
AD		 6006 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6007 /*
6008 * for legacy and MSI interrupts don't set any bits
6009 * that are enabled for EIAM, because this operation
6010 * would set *both* EIMS and EICS for any bit in EIAM
6011 */
6012 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6013 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6014 } else {
6015 /* get one bit for every active tx/rx interrupt vector */
6016 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6017 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6018 if (qv->rxr_count || qv->txr_count)
6019 eics |= ((u64)1 << i);
6020 }
cf8280ee 6021 }
9a799d71 6022
93c52dd0 6023 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6024 ixgbe_irq_rearm_queues(adapter, eics);
6025
cf8280ee
JB		 6026}
6027
c4cf55e5 6028/**
93c52dd0
AD		 6029 * ixgbe_watchdog_update_link - update the link status
6030 * @adapter - pointer to the device adapter structure
6031 * @link_speed - pointer to a u32 to store the link_speed
c4cf55e5 6032 **/
93c52dd0 6033static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
c4cf55e5 6034{
c4cf55e5 6035 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6036 u32 link_speed = adapter->link_speed;
6037 bool link_up = adapter->link_up;
c4cf55e5
PWJ		 6038 int i;
6039
93c52dd0
AD		 6040 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6041 return;
6042
6043 if (hw->mac.ops.check_link) {
6044 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6045 } else {
93c52dd0
AD		 6046 /* always assume link is up, if no check link function */
6047 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6048 link_up = true;
c4cf55e5 6049 }
93c52dd0
AD		 6050 if (link_up) {
6051 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6052 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6053 hw->mac.ops.fc_enable(hw, i);
6054 } else {
6055 hw->mac.ops.fc_enable(hw, 0);
6056 }
6057 }
6058
6059 if (link_up ||
6060 time_after(jiffies, (adapter->link_check_timeout +
6061 IXGBE_TRY_LINK_TIMEOUT))) {
6062 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6063 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6064 IXGBE_WRITE_FLUSH(hw);
6065 }
6066
6067 adapter->link_up = link_up;
6068 adapter->link_speed = link_speed;
c4cf55e5
PWJ		 6069}
6070
93c52dd0
AD		 6071/**
6072 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6073 * print link up message
6074 * @adapter - pointer to the device adapter structure
6075 **/
6076static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
a985b6c3 6077{
93c52dd0
AD		 6078 struct net_device *netdev = adapter->netdev;
6079 struct ixgbe_hw *hw = &adapter->hw;
6080 u32 link_speed = adapter->link_speed;
6081 bool flow_rx, flow_tx;
a985b6c3 6082
93c52dd0
AD		 6083 /* only continue if link was previously down */
6084 if (netif_carrier_ok(netdev))
a985b6c3
GR		 6085 return;
6086
93c52dd0 6087 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
a985b6c3 6088
93c52dd0
AD		 6089 switch (hw->mac.type) {
6090 case ixgbe_mac_82598EB: {
6091 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6092 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6093 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6094 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6095 }
6096 break;
6097 case ixgbe_mac_X540:
6098 case ixgbe_mac_82599EB: {
6099 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6100 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6101 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6102 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6103 }
6104 break;
6105 default:
6106 flow_tx = false;
6107 flow_rx = false;
6108 break;
6109 }
6110 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6111 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6112 "10 Gbps" :
6113 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6114 "1 Gbps" :
6115 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6116 "100 Mbps" :
6117 "unknown speed"))),
6118 ((flow_rx && flow_tx) ? "RX/TX" :
6119 (flow_rx ? "RX" :
6120 (flow_tx ? "TX" : "None"))));
a985b6c3 6121
93c52dd0
AD		 6122 netif_carrier_on(netdev);
6123#ifdef HAVE_IPLINK_VF_CONFIG
6124 ixgbe_check_vf_rate_limit(adapter);
6125#endif /* HAVE_IPLINK_VF_CONFIG */
a985b6c3
GR		 6126}
6127
cf8280ee 6128/**
93c52dd0
AD		 6129 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6130 * print link down message
6131 * @adapter - pointer to the adapter structure
cf8280ee 6132 **/
93c52dd0 6133static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
cf8280ee 6134{
cf8280ee
JB		 6135 struct net_device *netdev = adapter->netdev;
6136 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6137
93c52dd0
AD		 6138 adapter->link_up = false;
6139 adapter->link_speed = 0;
cf8280ee 6140
93c52dd0
AD		 6141 /* only continue if link was up previously */
6142 if (!netif_carrier_ok(netdev))
6143 return;
264857b8 6144
93c52dd0
AD		 6145 /* poll for SFP+ cable when link is down */
6146 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6147 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6148
93c52dd0
AD		 6149 e_info(drv, "NIC Link is Down\n");
6150 netif_carrier_off(netdev);
6151}
e8e26350 6152
93c52dd0
AD		 6153/**
6154 * ixgbe_watchdog_flush_tx - flush queues on link down
6155 * @adapter - pointer to the device adapter structure
6156 **/
6157static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6158{
6159 int i;
6160 int some_tx_pending = 0;
9a799d71 6161
93c52dd0 6162 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6163 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6164 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6165 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6166 some_tx_pending = 1;
6167 break;
6168 }
6169 }
6170
6171 if (some_tx_pending) {
6172 /* We've lost link, so the controller stops DMA,
6173 * but we've got queued Tx work that's never going
6174 * to get done, so reset controller to flush Tx.
6175 * (Do the reset outside of interrupt context).
6176 */
93c52dd0 6177 schedule_work(&adapter->reset_task);
bc59fcda
NS		 6178 }
6179 }
93c52dd0
AD		 6180}
6181
6182static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6183{
6184 u32 ssvpc;
6185
6186 /* Do not perform spoof check for 82598 */
6187 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6188 return;
6189
6190 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6191
6192 /*
6193 * ssvpc register is cleared on read, if zero then no
6194 * spoofed packets in the last interval.
6195 */
6196 if (!ssvpc)
6197 return;
6198
6199 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6200}
6201
6202/**
6203 * ixgbe_watchdog_subtask - check and bring link up
6204 * @adapter - pointer to the device adapter structure
6205 **/
6206static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6207{
6208 /* if interface is down do nothing */
6209 if (test_bit(__IXGBE_DOWN, &adapter->state))
6210 return;
6211
6212 ixgbe_watchdog_update_link(adapter);
6213
6214 if (adapter->link_up)
6215 ixgbe_watchdog_link_is_up(adapter);
6216 else
6217 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6218
a985b6c3 6219 ixgbe_spoof_check(adapter);
9a799d71 6220 ixgbe_update_stats(adapter);
93c52dd0
AD		 6221
6222 ixgbe_watchdog_flush_tx(adapter);
9a799d71
AK		 6223}
6224
7086400d
AD		 6225/**
6226 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6227 * @adapter - the ixgbe adapter structure
6228 **/
6229static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6230{
6231 struct ixgbe_hw *hw = &adapter->hw;
6232 s32 err;
6233
6234 /* not searching for SFP so there is nothing to do here */
6235 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6236 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6237 return;
6238
6239 /* someone else is in init, wait until next service event */
6240 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6241 return;
6242
6243 err = hw->phy.ops.identify_sfp(hw);
6244 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6245 goto sfp_out;
6246
6247 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6248 /* If no cable is present, then we need to reset
6249 * the next time we find a good cable. */
6250 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6251 }
6252
6253 /* exit on error */
6254 if (err)
6255 goto sfp_out;
6256
6257 /* exit if reset not needed */
6258 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6259 goto sfp_out;
6260
6261 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6262
6263 /*
6264 * A module may be identified correctly, but the EEPROM may not have
6265 * support for that module. setup_sfp() will fail in that case, so
6266 * we should not allow that module to load.
6267 */
6268 if (hw->mac.type == ixgbe_mac_82598EB)
6269 err = hw->phy.ops.reset(hw);
6270 else
6271 err = hw->mac.ops.setup_sfp(hw);
6272
6273 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6274 goto sfp_out;
6275
6276 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6277 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6278
6279sfp_out:
6280 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6281
6282 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6283 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6284 e_dev_err("failed to initialize because an unsupported "
6285 "SFP+ module type was detected.\n");
6286 e_dev_err("Reload the driver after installing a "
6287 "supported module.\n");
6288 unregister_netdev(adapter->netdev);
6289 }
6290}
6291
6292/**
6293 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6294 * @adapter - the ixgbe adapter structure
6295 **/
6296static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6297{
6298 struct ixgbe_hw *hw = &adapter->hw;
6299 u32 autoneg;
6300 bool negotiation;
6301
6302 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6303 return;
6304
6305 /* someone else is in init, wait until next service event */
6306 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6307 return;
6308
6309 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6310
6311 autoneg = hw->phy.autoneg_advertised;
6312 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6313 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6314 hw->mac.autotry_restart = false;
6315 if (hw->mac.ops.setup_link)
6316 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6317
6318 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6319 adapter->link_check_timeout = jiffies;
6320 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6321}
6322
6323/**
6324 * ixgbe_service_timer - Timer Call-back
6325 * @data: pointer to adapter cast into an unsigned long
6326 **/
6327static void ixgbe_service_timer(unsigned long data)
6328{
6329 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6330 unsigned long next_event_offset;
6331
6332 /* poll faster when waiting for link */
6333 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6334 next_event_offset = HZ / 10;
6335 else
6336 next_event_offset = HZ * 2;
6337
6338 /* Reset the timer */
6339 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6340
6341 ixgbe_service_event_schedule(adapter);
6342}
6343
6344/**
6345 * ixgbe_service_task - manages and runs subtasks
6346 * @work: pointer to work_struct containing our data
6347 **/
6348static void ixgbe_service_task(struct work_struct *work)
6349{
6350 struct ixgbe_adapter *adapter = container_of(work,
6351 struct ixgbe_adapter,
6352 service_task);
6353
6354 ixgbe_sfp_detection_subtask(adapter);
6355 ixgbe_sfp_link_config_subtask(adapter);
93c52dd0
AD		 6356 ixgbe_watchdog_subtask(adapter);
6357 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6358
6359 ixgbe_service_event_complete(adapter);
6360}
6361
9a799d71 6362static int ixgbe_tso(struct ixgbe_adapter *adapter,
e8e9f696 6363 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5e09a105 6364 u32 tx_flags, u8 *hdr_len, __be16 protocol)
9a799d71
AK		 6365{
6366 struct ixgbe_adv_tx_context_desc *context_desc;
6367 unsigned int i;
6368 int err;
6369 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 6370 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6371 u32 mss_l4len_idx, l4len;
9a799d71
AK		 6372
6373 if (skb_is_gso(skb)) {
6374 if (skb_header_cloned(skb)) {
6375 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6376 if (err)
6377 return err;
6378 }
6379 l4len = tcp_hdrlen(skb);
6380 *hdr_len += l4len;
6381
5e09a105 6382 if (protocol == htons(ETH_P_IP)) {
9a799d71
AK		 6383 struct iphdr *iph = ip_hdr(skb);
6384 iph->tot_len = 0;
6385 iph->check = 0;
6386 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
e8e9f696
JP		 6387 iph->daddr, 0,
6388 IPPROTO_TCP,
6389 0);
8e1e8a47 6390 } else if (skb_is_gso_v6(skb)) {
9a799d71
AK		 6391 ipv6_hdr(skb)->payload_len = 0;
6392 tcp_hdr(skb)->check =
6393 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
e8e9f696
JP		 6394 &ipv6_hdr(skb)->daddr,
6395 0, IPPROTO_TCP, 0);
9a799d71
AK		 6396 }
6397
6398 i = tx_ring->next_to_use;
6399
6400 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6401 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6402
6403 /* VLAN MACLEN IPLEN */
6404 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6405 vlan_macip_lens |=
6406 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6407 vlan_macip_lens |= ((skb_network_offset(skb)) <<
e8e9f696 6408 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6409 *hdr_len += skb_network_offset(skb);
6410 vlan_macip_lens |=
6411 (skb_transport_header(skb) - skb_network_header(skb));
6412 *hdr_len +=
6413 (skb_transport_header(skb) - skb_network_header(skb));
6414 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6415 context_desc->seqnum_seed = 0;
6416
6417 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 6418 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
e8e9f696 6419 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6420
5e09a105 6421 if (protocol == htons(ETH_P_IP))
9a799d71
AK		 6422 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6423 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6424 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6425
6426 /* MSS L4LEN IDX */
9f8cdf4f 6427 mss_l4len_idx =
9a799d71
AK		 6428 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6429 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 6430 /* use index 1 for TSO */
6431 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6432 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6433
6434 tx_buffer_info->time_stamp = jiffies;
6435 tx_buffer_info->next_to_watch = i;
6436
6437 i++;
6438 if (i == tx_ring->count)
6439 i = 0;
6440 tx_ring->next_to_use = i;
6441
6442 return true;
6443 }
6444 return false;
6445}
6446
5e09a105
HZ		 6447static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6448 __be16 protocol)
7ca647bd
JP		 6449{
6450 u32 rtn = 0;
7ca647bd
JP		 6451
6452 switch (protocol) {
6453 case cpu_to_be16(ETH_P_IP):
6454 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6455 switch (ip_hdr(skb)->protocol) {
6456 case IPPROTO_TCP:
6457 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6458 break;
6459 case IPPROTO_SCTP:
6460 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6461 break;
6462 }
6463 break;
6464 case cpu_to_be16(ETH_P_IPV6):
6465 /* XXX what about other V6 headers?? */
6466 switch (ipv6_hdr(skb)->nexthdr) {
6467 case IPPROTO_TCP:
6468 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6469 break;
6470 case IPPROTO_SCTP:
6471 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6472 break;
6473 }
6474 break;
6475 default:
6476 if (unlikely(net_ratelimit()))
6477 e_warn(probe, "partial checksum but proto=%x!\n",
5e09a105 6478 protocol);
7ca647bd
JP		 6479 break;
6480 }
6481
6482 return rtn;
6483}
6484
9a799d71 6485static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
e8e9f696 6486 struct ixgbe_ring *tx_ring,
5e09a105
HZ		 6487 struct sk_buff *skb, u32 tx_flags,
6488 __be16 protocol)
9a799d71
AK		 6489{
6490 struct ixgbe_adv_tx_context_desc *context_desc;
6491 unsigned int i;
6492 struct ixgbe_tx_buffer *tx_buffer_info;
6493 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6494
6495 if (skb->ip_summed == CHECKSUM_PARTIAL ||
6496 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6497 i = tx_ring->next_to_use;
6498 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6499 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71
AK		 6500
6501 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6502 vlan_macip_lens |=
6503 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6504 vlan_macip_lens |= (skb_network_offset(skb) <<
e8e9f696 6505 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 6506 if (skb->ip_summed == CHECKSUM_PARTIAL)
6507 vlan_macip_lens |= (skb_transport_header(skb) -
e8e9f696 6508 skb_network_header(skb));
9a799d71
AK		 6509
6510 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6511 context_desc->seqnum_seed = 0;
6512
6513 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
e8e9f696 6514 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 6515
7ca647bd 6516 if (skb->ip_summed == CHECKSUM_PARTIAL)
5e09a105 6517 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
9a799d71
AK		 6518
6519 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 6520 /* use index zero for tx checksum offload */
9a799d71
AK		 6521 context_desc->mss_l4len_idx = 0;
6522
6523 tx_buffer_info->time_stamp = jiffies;
6524 tx_buffer_info->next_to_watch = i;
9f8cdf4f 6525
9a799d71
AK		 6526 i++;
6527 if (i == tx_ring->count)
6528 i = 0;
6529 tx_ring->next_to_use = i;
6530
6531 return true;
6532 }
9f8cdf4f 6533
9a799d71
AK		 6534 return false;
6535}
6536
6537static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
e8e9f696
JP		 6538 struct ixgbe_ring *tx_ring,
6539 struct sk_buff *skb, u32 tx_flags,
8ad494b0 6540 unsigned int first, const u8 hdr_len)
9a799d71 6541{
b6ec895e 6542 struct device *dev = tx_ring->dev;
9a799d71 6543 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 6544 unsigned int len;
6545 unsigned int total = skb->len;
9a799d71
AK		 6546 unsigned int offset = 0, size, count = 0, i;
6547 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6548 unsigned int f;
8ad494b0
AD		 6549 unsigned int bytecount = skb->len;
6550 u16 gso_segs = 1;
9a799d71
AK		 6551
6552 i = tx_ring->next_to_use;
6553
eacd73f7
YZ		 6554 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6555 /* excluding fcoe_crc_eof for FCoE */
6556 total -= sizeof(struct fcoe_crc_eof);
6557
6558 len = min(skb_headlen(skb), total);
9a799d71
AK		 6559 while (len) {
6560 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6561 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6562
6563 tx_buffer_info->length = size;
e5a43549 6564 tx_buffer_info->mapped_as_page = false;
b6ec895e 6565 tx_buffer_info->dma = dma_map_single(dev,
e5a43549 6566 skb->data + offset,
1b507730 6567 size, DMA_TO_DEVICE);
b6ec895e 6568 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6569 goto dma_error;
9a799d71
AK		 6570 tx_buffer_info->time_stamp = jiffies;
6571 tx_buffer_info->next_to_watch = i;
6572
6573 len -= size;
eacd73f7 6574 total -= size;
9a799d71
AK		 6575 offset += size;
6576 count++;
44df32c5
AD		 6577
6578 if (len) {
6579 i++;
6580 if (i == tx_ring->count)
6581 i = 0;
6582 }
9a799d71
AK		 6583 }
6584
6585 for (f = 0; f < nr_frags; f++) {
6586 struct skb_frag_struct *frag;
6587
6588 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 6589 len = min((unsigned int)frag->size, total);
e5a43549 6590 offset = frag->page_offset;
9a799d71
AK		 6591
6592 while (len) {
44df32c5
AD		 6593 i++;
6594 if (i == tx_ring->count)
6595 i = 0;
6596
9a799d71
AK		 6597 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6598 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6599
6600 tx_buffer_info->length = size;
b6ec895e 6601 tx_buffer_info->dma = dma_map_page(dev,
e5a43549
AD		 6602 frag->page,
6603 offset, size,
1b507730 6604 DMA_TO_DEVICE);
e5a43549 6605 tx_buffer_info->mapped_as_page = true;
b6ec895e 6606 if (dma_mapping_error(dev, tx_buffer_info->dma))
e5a43549 6607 goto dma_error;
9a799d71
AK		 6608 tx_buffer_info->time_stamp = jiffies;
6609 tx_buffer_info->next_to_watch = i;
6610
6611 len -= size;
eacd73f7 6612 total -= size;
9a799d71
AK		 6613 offset += size;
6614 count++;
9a799d71 6615 }
eacd73f7
YZ		 6616 if (total == 0)
6617 break;
9a799d71 6618 }
44df32c5 6619
8ad494b0
AD		 6620 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6621 gso_segs = skb_shinfo(skb)->gso_segs;
6622#ifdef IXGBE_FCOE
6623 /* adjust for FCoE Sequence Offload */
6624 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6625 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6626 skb_shinfo(skb)->gso_size);
6627#endif /* IXGBE_FCOE */
6628 bytecount += (gso_segs - 1) * hdr_len;
6629
6630 /* multiply data chunks by size of headers */
6631 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6632 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
9a799d71
AK		 6633 tx_ring->tx_buffer_info[i].skb = skb;
6634 tx_ring->tx_buffer_info[first].next_to_watch = i;
6635
e5a43549
AD		 6636 return count;
6637
6638dma_error:
849c4542 6639 e_dev_err("TX DMA map failed\n");
e5a43549
AD		 6640
6641 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6642 tx_buffer_info->dma = 0;
6643 tx_buffer_info->time_stamp = 0;
6644 tx_buffer_info->next_to_watch = 0;
c1fa347f
RK		 6645 if (count)
6646 count--;
e5a43549
AD		 6647
6648 /* clear timestamp and dma mappings for remaining portion of packet */
c1fa347f 6649 while (count--) {
e8e9f696 6650 if (i == 0)
e5a43549 6651 i += tx_ring->count;
c1fa347f 6652 i--;
e5a43549 6653 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 6654 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
e5a43549
AD		 6655 }
6656
e44d38e1 6657 return 0;
9a799d71
AK		 6658}
6659
84ea2591 6660static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
e8e9f696 6661 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 6662{
6663 union ixgbe_adv_tx_desc *tx_desc = NULL;
6664 struct ixgbe_tx_buffer *tx_buffer_info;
6665 u32 olinfo_status = 0, cmd_type_len = 0;
6666 unsigned int i;
6667 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6668
6669 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6670
6671 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6672
6673 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6674 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6675
6676 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6677 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6678
6679 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6680 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6681
4eeae6fd
PW		 6682 /* use index 1 context for tso */
6683 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 6684 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6685 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
e8e9f696 6686 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 6687
6688 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6689 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
e8e9f696 6690 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 6691
eacd73f7
YZ		 6692 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6693 olinfo_status |= IXGBE_ADVTXD_CC;
6694 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6695 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6696 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6697 }
6698
9a799d71
AK		 6699 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6700
6701 i = tx_ring->next_to_use;
6702 while (count--) {
6703 tx_buffer_info = &tx_ring->tx_buffer_info[i];
31f05a2d 6704 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
9a799d71
AK		 6705 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6706 tx_desc->read.cmd_type_len =
e8e9f696 6707 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 6708 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 6709 i++;
6710 if (i == tx_ring->count)
6711 i = 0;
6712 }
6713
6714 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6715
6716 /*
6717 * Force memory writes to complete before letting h/w
6718 * know there are new descriptors to fetch. (Only
6719 * applicable for weak-ordered memory model archs,
6720 * such as IA-64).
6721 */
6722 wmb();
6723
6724 tx_ring->next_to_use = i;
84ea2591 6725 writel(i, tx_ring->tail);
9a799d71
AK		 6726}
6727
69830529
AD		 6728static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6729 u32 tx_flags, __be16 protocol)
6730{
6731 struct ixgbe_q_vector *q_vector = ring->q_vector;
6732 union ixgbe_atr_hash_dword input = { .dword = 0 };
6733 union ixgbe_atr_hash_dword common = { .dword = 0 };
6734 union {
6735 unsigned char *network;
6736 struct iphdr *ipv4;
6737 struct ipv6hdr *ipv6;
6738 } hdr;
ee9e0f0b 6739 struct tcphdr *th;
905e4a41 6740 __be16 vlan_id;
c4cf55e5 6741
69830529
AD		 6742 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6743 if (!q_vector)
6744 return;
6745
6746 /* do nothing if sampling is disabled */
6747 if (!ring->atr_sample_rate)
d3ead241 6748 return;
c4cf55e5 6749
69830529 6750 ring->atr_count++;
c4cf55e5 6751
69830529
AD		 6752 /* snag network header to get L4 type and address */
6753 hdr.network = skb_network_header(skb);
6754
6755 /* Currently only IPv4/IPv6 with TCP is supported */
6756 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6757 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6758 (protocol != __constant_htons(ETH_P_IP) ||
6759 hdr.ipv4->protocol != IPPROTO_TCP))
6760 return;
ee9e0f0b
AD		 6761
6762 th = tcp_hdr(skb);
c4cf55e5 6763
69830529
AD		 6764 /* skip this packet since the socket is closing */
6765 if (th->fin)
6766 return;
6767
6768 /* sample on all syn packets or once every atr sample count */
6769 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6770 return;
6771
6772 /* reset sample count */
6773 ring->atr_count = 0;
6774
6775 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6776
6777 /*
6778 * src and dst are inverted, think how the receiver sees them
6779 *
6780 * The input is broken into two sections, a non-compressed section
6781 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6782 * is XORed together and stored in the compressed dword.
6783 */
6784 input.formatted.vlan_id = vlan_id;
6785
6786 /*
6787 * since src port and flex bytes occupy the same word XOR them together
6788 * and write the value to source port portion of compressed dword
6789 */
6790 if (vlan_id)
6791 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6792 else
6793 common.port.src ^= th->dest ^ protocol;
6794 common.port.dst ^= th->source;
6795
6796 if (protocol == __constant_htons(ETH_P_IP)) {
6797 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6798 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6799 } else {
6800 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6801 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6802 hdr.ipv6->saddr.s6_addr32[1] ^
6803 hdr.ipv6->saddr.s6_addr32[2] ^
6804 hdr.ipv6->saddr.s6_addr32[3] ^
6805 hdr.ipv6->daddr.s6_addr32[0] ^
6806 hdr.ipv6->daddr.s6_addr32[1] ^
6807 hdr.ipv6->daddr.s6_addr32[2] ^
6808 hdr.ipv6->daddr.s6_addr32[3];
6809 }
c4cf55e5
PWJ		 6810
6811 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6812 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6813 input, common, ring->queue_index);
c4cf55e5
PWJ		 6814}
6815
fc77dc3c 6816static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60 6817{
fc77dc3c 6818 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6819 /* Herbert's original patch had:
6820 * smp_mb__after_netif_stop_queue();
6821 * but since that doesn't exist yet, just open code it. */
6822 smp_mb();
6823
6824 /* We need to check again in a case another CPU has just
6825 * made room available. */
6826 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6827 return -EBUSY;
6828
6829 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6830 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6831 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6832 return 0;
6833}
6834
fc77dc3c 6835static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 6836{
6837 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6838 return 0;
fc77dc3c 6839 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6840}
6841
09a3b1f8
SH		 6842static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6843{
6844 struct ixgbe_adapter *adapter = netdev_priv(dev);
5f715823 6845 int txq = smp_processor_id();
56075a98 6846#ifdef IXGBE_FCOE
5e09a105
HZ		 6847 __be16 protocol;
6848
6849 protocol = vlan_get_protocol(skb);
6850
e5b64635
JF		 6851 if (((protocol == htons(ETH_P_FCOE)) ||
6852 (protocol == htons(ETH_P_FIP))) &&
6853 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6854 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6855 txq += adapter->ring_feature[RING_F_FCOE].mask;
6856 return txq;
56075a98
JF		 6857 }
6858#endif
6859
fdd3d631
KK		 6860 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6861 while (unlikely(txq >= dev->real_num_tx_queues))
6862 txq -= dev->real_num_tx_queues;
5f715823 6863 return txq;
fdd3d631 6864 }
c4cf55e5 6865
09a3b1f8
SH		 6866 return skb_tx_hash(dev, skb);
6867}
6868
fc77dc3c 6869netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6870 struct ixgbe_adapter *adapter,
6871 struct ixgbe_ring *tx_ring)
9a799d71 6872{
9a799d71
AK		 6873 unsigned int first;
6874 unsigned int tx_flags = 0;
30eba97a 6875 u8 hdr_len = 0;
5f715823 6876 int tso;
9a799d71
AK		 6877 int count = 0;
6878 unsigned int f;
5e09a105
HZ		 6879 __be16 protocol;
6880
6881 protocol = vlan_get_protocol(skb);
9f8cdf4f 6882
eab6d18d 6883 if (vlan_tx_tag_present(skb)) {
9f8cdf4f 6884 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 6885 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6886 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
e5b64635 6887 tx_flags |= tx_ring->dcb_tc << 13;
2f90b865
AD		 6888 }
6889 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6890 tx_flags |= IXGBE_TX_FLAGS_VLAN;
33c66bd1
JF		 6891 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6892 skb->priority != TC_PRIO_CONTROL) {
e5b64635 6893 tx_flags |= tx_ring->dcb_tc << 13;
2ea186ae
JF		 6894 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6895 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 6896 }
eacd73f7 6897
09ad1cc0 6898#ifdef IXGBE_FCOE
56075a98
JF		 6899 /* for FCoE with DCB, we force the priority to what
6900 * was specified by the switch */
6901 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
e5b64635
JF		 6902 (protocol == htons(ETH_P_FCOE)))
6903 tx_flags |= IXGBE_TX_FLAGS_FCOE;
ca77cd59
RL		 6904#endif
6905
eacd73f7 6906 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 6907 if (skb_is_gso(skb) ||
6908 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 6909 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6910 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 6911 count++;
6912
9f8cdf4f
JB		 6913 count += TXD_USE_COUNT(skb_headlen(skb));
6914 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 6915 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6916
fc77dc3c 6917 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
5b7da515 6918 tx_ring->tx_stats.tx_busy++;
9a799d71
AK		 6919 return NETDEV_TX_BUSY;
6920 }
9a799d71 6921
9a799d71 6922 first = tx_ring->next_to_use;
eacd73f7
YZ		 6923 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6924#ifdef IXGBE_FCOE
6925 /* setup tx offload for FCoE */
6926 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6927 if (tso < 0) {
6928 dev_kfree_skb_any(skb);
6929 return NETDEV_TX_OK;
6930 }
6931 if (tso)
6932 tx_flags |= IXGBE_TX_FLAGS_FSO;
6933#endif /* IXGBE_FCOE */
6934 } else {
5e09a105 6935 if (protocol == htons(ETH_P_IP))
eacd73f7 6936 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5e09a105
HZ		 6937 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6938 protocol);
eacd73f7
YZ		 6939 if (tso < 0) {
6940 dev_kfree_skb_any(skb);
6941 return NETDEV_TX_OK;
6942 }
9a799d71 6943
eacd73f7
YZ		 6944 if (tso)
6945 tx_flags |= IXGBE_TX_FLAGS_TSO;
5e09a105
HZ		 6946 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6947 protocol) &&
eacd73f7
YZ		 6948 (skb->ip_summed == CHECKSUM_PARTIAL))
6949 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6950 }
9a799d71 6951
8ad494b0 6952 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
44df32c5 6953 if (count) {
c4cf55e5 6954 /* add the ATR filter if ATR is on */
69830529
AD		 6955 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6956 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
84ea2591 6957 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
fc77dc3c 6958 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71 6959
44df32c5
AD		 6960 } else {
6961 dev_kfree_skb_any(skb);
6962 tx_ring->tx_buffer_info[first].time_stamp = 0;
6963 tx_ring->next_to_use = first;
6964 }
9a799d71
AK		 6965
6966 return NETDEV_TX_OK;
6967}
6968
84418e3b
AD		 6969static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6970{
6971 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6972 struct ixgbe_ring *tx_ring;
6973
6974 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6975 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6976}
6977
9a799d71
AK		 6978/**
6979 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6980 * @netdev: network interface device structure
6981 * @p: pointer to an address structure
6982 *
6983 * Returns 0 on success, negative on failure
6984 **/
6985static int ixgbe_set_mac(struct net_device *netdev, void *p)
6986{
6987 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6988 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6989 struct sockaddr *addr = p;
6990
6991 if (!is_valid_ether_addr(addr->sa_data))
6992 return -EADDRNOTAVAIL;
6993
6994 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6995 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6996
1cdd1ec8
GR		 6997 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6998 IXGBE_RAH_AV);
9a799d71
AK		 6999
7000 return 0;
7001}
7002
6b73e10d
BH		 7003static int
7004ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7005{
7006 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7007 struct ixgbe_hw *hw = &adapter->hw;
7008 u16 value;
7009 int rc;
7010
7011 if (prtad != hw->phy.mdio.prtad)
7012 return -EINVAL;
7013 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7014 if (!rc)
7015 rc = value;
7016 return rc;
7017}
7018
7019static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7020 u16 addr, u16 value)
7021{
7022 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7023 struct ixgbe_hw *hw = &adapter->hw;
7024
7025 if (prtad != hw->phy.mdio.prtad)
7026 return -EINVAL;
7027 return hw->phy.ops.write_reg(hw, addr, devad, value);
7028}
7029
7030static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7031{
7032 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7033
7034 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7035}
7036
0365e6e4
PW		 7037/**
7038 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7039 * netdev->dev_addrs
0365e6e4
PW		 7040 * @netdev: network interface device structure
7041 *
7042 * Returns non-zero on failure
7043 **/
7044static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7045{
7046 int err = 0;
7047 struct ixgbe_adapter *adapter = netdev_priv(dev);
7048 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7049
7050 if (is_valid_ether_addr(mac->san_addr)) {
7051 rtnl_lock();
7052 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7053 rtnl_unlock();
7054 }
7055 return err;
7056}
7057
7058/**
7059 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7060 * netdev->dev_addrs
0365e6e4
PW		 7061 * @netdev: network interface device structure
7062 *
7063 * Returns non-zero on failure
7064 **/
7065static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7066{
7067 int err = 0;
7068 struct ixgbe_adapter *adapter = netdev_priv(dev);
7069 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7070
7071 if (is_valid_ether_addr(mac->san_addr)) {
7072 rtnl_lock();
7073 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7074 rtnl_unlock();
7075 }
7076 return err;
7077}
7078
9a799d71
AK		 7079#ifdef CONFIG_NET_POLL_CONTROLLER
7080/*
7081 * Polling 'interrupt' - used by things like netconsole to send skbs
7082 * without having to re-enable interrupts. It's not called while
7083 * the interrupt routine is executing.
7084 */
7085static void ixgbe_netpoll(struct net_device *netdev)
7086{
7087 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7088 int i;
9a799d71 7089
1a647bd2
AD		 7090 /* if interface is down do nothing */
7091 if (test_bit(__IXGBE_DOWN, &adapter->state))
7092 return;
7093
9a799d71 7094 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7095 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7096 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7097 for (i = 0; i < num_q_vectors; i++) {
7098 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7099 ixgbe_msix_clean_many(0, q_vector);
7100 }
7101 } else {
7102 ixgbe_intr(adapter->pdev->irq, netdev);
7103 }
9a799d71 7104 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7105}
7106#endif
7107
de1036b1
ED		 7108static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7109 struct rtnl_link_stats64 *stats)
7110{
7111 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7112 int i;
7113
1a51502b 7114 rcu_read_lock();
de1036b1 7115 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7116 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7117 u64 bytes, packets;
7118 unsigned int start;
7119
1a51502b
ED		 7120 if (ring) {
7121 do {
7122 start = u64_stats_fetch_begin_bh(&ring->syncp);
7123 packets = ring->stats.packets;
7124 bytes = ring->stats.bytes;
7125 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7126 stats->rx_packets += packets;
7127 stats->rx_bytes += bytes;
7128 }
de1036b1 7129 }
1ac9ad13
ED		 7130
7131 for (i = 0; i < adapter->num_tx_queues; i++) {
7132 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7133 u64 bytes, packets;
7134 unsigned int start;
7135
7136 if (ring) {
7137 do {
7138 start = u64_stats_fetch_begin_bh(&ring->syncp);
7139 packets = ring->stats.packets;
7140 bytes = ring->stats.bytes;
7141 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7142 stats->tx_packets += packets;
7143 stats->tx_bytes += bytes;
7144 }
7145 }
1a51502b 7146 rcu_read_unlock();
de1036b1
ED		 7147 /* following stats updated by ixgbe_watchdog_task() */
7148 stats->multicast = netdev->stats.multicast;
7149 stats->rx_errors = netdev->stats.rx_errors;
7150 stats->rx_length_errors = netdev->stats.rx_length_errors;
7151 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7152 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7153 return stats;
7154}
7155
7156
0edc3527 7157static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7158 .ndo_open = ixgbe_open,
0edc3527 7159 .ndo_stop = ixgbe_close,
00829823 7160 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7161 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7162 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7163 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7164 .ndo_validate_addr = eth_validate_addr,
7165 .ndo_set_mac_address = ixgbe_set_mac,
7166 .ndo_change_mtu = ixgbe_change_mtu,
7167 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7168 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7169 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7170 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7171 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7172 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7173 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7174 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7175 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3
JF		 7176#ifdef CONFIG_IXGBE_DCB
7177 .ndo_setup_tc = ixgbe_setup_tc,
7178#endif
0edc3527
SH		 7179#ifdef CONFIG_NET_POLL_CONTROLLER
7180 .ndo_poll_controller = ixgbe_netpoll,
7181#endif
332d4a7d
YZ		 7182#ifdef IXGBE_FCOE
7183 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7184 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7185 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7186 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7187 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7188 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7189#endif /* IXGBE_FCOE */
0edc3527
SH		 7190};
7191
1cdd1ec8
GR		 7192static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7193 const struct ixgbe_info *ii)
7194{
7195#ifdef CONFIG_PCI_IOV
7196 struct ixgbe_hw *hw = &adapter->hw;
7197 int err;
a1cbb15c
GR		 7198 int num_vf_macvlans, i;
7199 struct vf_macvlans *mv_list;
1cdd1ec8 7200
3377eba7 7201 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
1cdd1ec8
GR		 7202 return;
7203
7204 /* The 82599 supports up to 64 VFs per physical function
7205 * but this implementation limits allocation to 63 so that
7206 * basic networking resources are still available to the
7207 * physical function
7208 */
7209 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7210 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7211 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7212 if (err) {
396e799c 7213 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 7214 goto err_novfs;
7215 }
a1cbb15c
GR		 7216
7217 num_vf_macvlans = hw->mac.num_rar_entries -
7218 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7219
7220 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7221 sizeof(struct vf_macvlans),
7222 GFP_KERNEL);
7223 if (mv_list) {
7224 /* Initialize list of VF macvlans */
7225 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7226 for (i = 0; i < num_vf_macvlans; i++) {
7227 mv_list->vf = -1;
7228 mv_list->free = true;
7229 mv_list->rar_entry = hw->mac.num_rar_entries -
7230 (i + adapter->num_vfs + 1);
7231 list_add(&mv_list->l, &adapter->vf_mvs.l);
7232 mv_list++;
7233 }
7234 }
7235
1cdd1ec8
GR		 7236 /* If call to enable VFs succeeded then allocate memory
7237 * for per VF control structures.
7238 */
7239 adapter->vfinfo =
7240 kcalloc(adapter->num_vfs,
7241 sizeof(struct vf_data_storage), GFP_KERNEL);
7242 if (adapter->vfinfo) {
7243 /* Now that we're sure SR-IOV is enabled
7244 * and memory allocated set up the mailbox parameters
7245 */
7246 ixgbe_init_mbx_params_pf(hw);
7247 memcpy(&hw->mbx.ops, ii->mbx_ops,
7248 sizeof(hw->mbx.ops));
7249
7250 /* Disable RSC when in SR-IOV mode */
7251 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7252 IXGBE_FLAG2_RSC_ENABLED);
7253 return;
7254 }
7255
7256 /* Oh oh */
396e799c
ET		 7257 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7258 "SRIOV disabled\n");
1cdd1ec8
GR		 7259 pci_disable_sriov(adapter->pdev);
7260
7261err_novfs:
7262 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7263 adapter->num_vfs = 0;
7264#endif /* CONFIG_PCI_IOV */
7265}
7266
9a799d71
AK		 7267/**
7268 * ixgbe_probe - Device Initialization Routine
7269 * @pdev: PCI device information struct
7270 * @ent: entry in ixgbe_pci_tbl
7271 *
7272 * Returns 0 on success, negative on failure
7273 *
7274 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7275 * The OS initialization, configuring of the adapter private structure,
7276 * and a hardware reset occur.
7277 **/
7278static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7279 const struct pci_device_id *ent)
9a799d71
AK		 7280{
7281 struct net_device *netdev;
7282 struct ixgbe_adapter *adapter = NULL;
7283 struct ixgbe_hw *hw;
7284 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7285 static int cards_found;
7286 int i, err, pci_using_dac;
289700db 7287 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7288 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7289#ifdef IXGBE_FCOE
7290 u16 device_caps;
7291#endif
289700db 7292 u32 eec;
9a799d71 7293
bded64a7
AG		 7294 /* Catch broken hardware that put the wrong VF device ID in
7295 * the PCIe SR-IOV capability.
7296 */
7297 if (pdev->is_virtfn) {
7298 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7299 pci_name(pdev), pdev->vendor, pdev->device);
7300 return -EINVAL;
7301 }
7302
9ce77666 7303 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7304 if (err)
7305 return err;
7306
1b507730
NN		 7307 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7308 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7309 pci_using_dac = 1;
7310 } else {
1b507730 7311 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7312 if (err) {
1b507730
NN		 7313 err = dma_set_coherent_mask(&pdev->dev,
7314 DMA_BIT_MASK(32));
9a799d71 7315 if (err) {
b8bc0421
DC		 7316 dev_err(&pdev->dev,
7317 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7318 goto err_dma;
7319 }
7320 }
7321 pci_using_dac = 0;
7322 }
7323
9ce77666 7324 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7325 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7326 if (err) {
b8bc0421
DC		 7327 dev_err(&pdev->dev,
7328 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7329 goto err_pci_reg;
7330 }
7331
19d5afd4 7332 pci_enable_pcie_error_reporting(pdev);
6fabd715 7333
9a799d71 7334 pci_set_master(pdev);
fb3b27bc 7335 pci_save_state(pdev);
9a799d71 7336
c85a2618
JF		 7337 if (ii->mac == ixgbe_mac_82598EB)
7338 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7339 else
7340 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7341
e5b64635 7342#if defined(CONFIG_DCB)
c85a2618 7343 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
e5b64635 7344#elif defined(IXGBE_FCOE)
c85a2618
JF		 7345 indices += min_t(unsigned int, num_possible_cpus(),
7346 IXGBE_MAX_FCOE_INDICES);
7347#endif
c85a2618 7348 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7349 if (!netdev) {
7350 err = -ENOMEM;
7351 goto err_alloc_etherdev;
7352 }
7353
9a799d71
AK		 7354 SET_NETDEV_DEV(netdev, &pdev->dev);
7355
9a799d71 7356 adapter = netdev_priv(netdev);
c60fbb00 7357 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7358
7359 adapter->netdev = netdev;
7360 adapter->pdev = pdev;
7361 hw = &adapter->hw;
7362 hw->back = adapter;
7363 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7364
05857980 7365 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7366 pci_resource_len(pdev, 0));
9a799d71
AK		 7367 if (!hw->hw_addr) {
7368 err = -EIO;
7369 goto err_ioremap;
7370 }
7371
7372 for (i = 1; i <= 5; i++) {
7373 if (pci_resource_len(pdev, i) == 0)
7374 continue;
7375 }
7376
0edc3527 7377 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7378 ixgbe_set_ethtool_ops(netdev);
9a799d71 7379 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7380 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7381
9a799d71
AK		 7382 adapter->bd_number = cards_found;
7383
9a799d71
AK		 7384 /* Setup hw api */
7385 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7386 hw->mac.type = ii->mac;
9a799d71 7387
c44ade9e
JB		 7388 /* EEPROM */
7389 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7390 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7391 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7392 if (!(eec & (1 << 8)))
7393 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7394
7395 /* PHY */
7396 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7397 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7398 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7399 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7400 hw->phy.mdio.mmds = 0;
7401 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7402 hw->phy.mdio.dev = netdev;
7403 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7404 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7405
8ca783ab 7406 ii->get_invariants(hw);
9a799d71
AK		 7407
7408 /* setup the private structure */
7409 err = ixgbe_sw_init(adapter);
7410 if (err)
7411 goto err_sw_init;
7412
e86bff0e 7413 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7414 switch (adapter->hw.mac.type) {
7415 case ixgbe_mac_82599EB:
7416 case ixgbe_mac_X540:
e86bff0e 7417 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7418 break;
7419 default:
7420 break;
7421 }
e86bff0e 7422
bf069c97
DS		 7423 /*
7424 * If there is a fan on this device and it has failed log the
7425 * failure.
7426 */
7427 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7428 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7429 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7430 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7431 }
7432
c44ade9e 7433 /* reset_hw fills in the perm_addr as well */
119fc60a 7434 hw->phy.reset_if_overtemp = true;
c44ade9e 7435 err = hw->mac.ops.reset_hw(hw);
119fc60a 7436 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7437 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7438 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7439 err = 0;
7440 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7441 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7442 "module type was detected.\n");
7443 e_dev_err("Reload the driver after installing a supported "
7444 "module.\n");
04f165ef
PW		 7445 goto err_sw_init;
7446 } else if (err) {
849c4542 7447 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7448 goto err_sw_init;
7449 }
7450
1cdd1ec8
GR		 7451 ixgbe_probe_vf(adapter, ii);
7452
396e799c 7453 netdev->features = NETIF_F_SG |
e8e9f696
JP		 7454 NETIF_F_IP_CSUM |
7455 NETIF_F_HW_VLAN_TX |
7456 NETIF_F_HW_VLAN_RX |
7457 NETIF_F_HW_VLAN_FILTER;
9a799d71 7458
e9990a9c 7459 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 7460 netdev->features |= NETIF_F_TSO;
9a799d71 7461 netdev->features |= NETIF_F_TSO6;
78b6f4ce 7462 netdev->features |= NETIF_F_GRO;
67a74ee2 7463 netdev->features |= NETIF_F_RXHASH;
ad31c402 7464
58be7666
DS		 7465 switch (adapter->hw.mac.type) {
7466 case ixgbe_mac_82599EB:
7467 case ixgbe_mac_X540:
45a5ead0 7468 netdev->features |= NETIF_F_SCTP_CSUM;
58be7666
DS		 7469 break;
7470 default:
7471 break;
7472 }
45a5ead0 7473
ad31c402
JK		 7474 netdev->vlan_features |= NETIF_F_TSO;
7475 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7476 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7477 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7478 netdev->vlan_features |= NETIF_F_SG;
7479
1cdd1ec8
GR		 7480 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7481 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7482 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7483
7a6b6f51 7484#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7485 netdev->dcbnl_ops = &dcbnl_ops;
7486#endif
7487
eacd73f7 7488#ifdef IXGBE_FCOE
0d551589 7489 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7490 if (hw->mac.ops.get_device_caps) {
7491 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7492 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7493 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7494 }
7495 }
5e09d7f6
YZ		 7496 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7497 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7498 netdev->vlan_features |= NETIF_F_FSO;
7499 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7500 }
eacd73f7 7501#endif /* IXGBE_FCOE */
7b872a55 7502 if (pci_using_dac) {
9a799d71 7503 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7504 netdev->vlan_features |= NETIF_F_HIGHDMA;
7505 }
9a799d71 7506
0c19d6af 7507 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7508 netdev->features |= NETIF_F_LRO;
7509
9a799d71 7510 /* make sure the EEPROM is good */
c44ade9e 7511 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7512 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7513 err = -EIO;
7514 goto err_eeprom;
7515 }
7516
7517 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7518 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7519
c44ade9e 7520 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7521 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7522 err = -EIO;
7523 goto err_eeprom;
7524 }
7525
c6ecf39a
DS		 7526 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7527 if (hw->mac.ops.disable_tx_laser &&
7528 ((hw->phy.multispeed_fiber) ||
9f911707 7529 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7530 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7531 hw->mac.ops.disable_tx_laser(hw);
7532
7086400d
AD		 7533 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7534 (unsigned long) adapter);
9a799d71
AK		 7535
7536 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7537
7086400d
AD		 7538 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7539 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7540
021230d4
AV		 7541 err = ixgbe_init_interrupt_scheme(adapter);
7542 if (err)
7543 goto err_sw_init;
9a799d71 7544
67a74ee2
ET		 7545 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7546 netdev->features &= ~NETIF_F_RXHASH;
7547
e8e26350 7548 switch (pdev->device) {
0b077fea
DS		 7549 case IXGBE_DEV_ID_82599_SFP:
7550 /* Only this subdevice supports WOL */
7551 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7552 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7553 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7554 break;
50d6c681
AD		 7555 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7556 /* All except this subdevice support WOL */
0b077fea
DS		 7557 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7558 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7559 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7560 break;
e8e26350 7561 case IXGBE_DEV_ID_82599_KX4:
495dce12 7562 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
e8e9f696 7563 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
e8e26350
PW		 7564 break;
7565 default:
7566 adapter->wol = 0;
7567 break;
7568 }
e8e26350
PW		 7569 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7570
04f165ef
PW		 7571 /* pick up the PCI bus settings for reporting later */
7572 hw->mac.ops.get_bus_info(hw);
7573
9a799d71 7574 /* print bus type/speed/width info */
849c4542 7575 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7576 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7577 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7578 "Unknown"),
7579 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7580 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7581 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7582 "Unknown"),
7583 netdev->dev_addr);
289700db
DS		 7584
7585 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7586 if (err)
9fe93afd 7587 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7588 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7589 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7590 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7591 part_str);
e8e26350 7592 else
289700db
DS		 7593 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7594 hw->mac.type, hw->phy.type, part_str);
9a799d71 7595
e8e26350 7596 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7597 e_dev_warn("PCI-Express bandwidth available for this card is "
7598 "not sufficient for optimal performance.\n");
7599 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7600 "is required.\n");
0c254d86
AK		 7601 }
7602
34b0368c
PWJ		 7603 /* save off EEPROM version number */
7604 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7605
9a799d71 7606 /* reset the hardware with the new settings */
794caeb2 7607 err = hw->mac.ops.start_hw(hw);
c44ade9e 7608
794caeb2
PWJ		 7609 if (err == IXGBE_ERR_EEPROM_VERSION) {
7610 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7611 e_dev_warn("This device is a pre-production adapter/LOM. "
7612 "Please be aware there may be issues associated "
7613 "with your hardware. If you are experiencing "
7614 "problems please contact your Intel or hardware "
7615 "representative who provided you with this "
7616 "hardware.\n");
794caeb2 7617 }
9a799d71
AK		 7618 strcpy(netdev->name, "eth%d");
7619 err = register_netdev(netdev);
7620 if (err)
7621 goto err_register;
7622
54386467
JB		 7623 /* carrier off reporting is important to ethtool even BEFORE open */
7624 netif_carrier_off(netdev);
7625
c4cf55e5
PWJ		 7626 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7627 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7628 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7629
119fc60a 7630 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
e8e9f696
JP		 7631 INIT_WORK(&adapter->check_overtemp_task,
7632 ixgbe_check_overtemp_task);
5dd2d332 7633#ifdef CONFIG_IXGBE_DCA
652f093f 7634 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7635 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7636 ixgbe_setup_dca(adapter);
7637 }
7638#endif
1cdd1ec8 7639 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7640 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7641 for (i = 0; i < adapter->num_vfs; i++)
7642 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7643 }
7644
0365e6e4
PW		 7645 /* add san mac addr to netdev */
7646 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7647
849c4542 7648 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7649 cards_found++;
7650 return 0;
7651
7652err_register:
5eba3699 7653 ixgbe_release_hw_control(adapter);
7a921c93 7654 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7655err_sw_init:
7656err_eeprom:
1cdd1ec8
GR		 7657 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7658 ixgbe_disable_sriov(adapter);
7086400d 7659 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7660 iounmap(hw->hw_addr);
7661err_ioremap:
7662 free_netdev(netdev);
7663err_alloc_etherdev:
e8e9f696
JP		 7664 pci_release_selected_regions(pdev,
7665 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7666err_pci_reg:
7667err_dma:
7668 pci_disable_device(pdev);
7669 return err;
7670}
7671
7672/**
7673 * ixgbe_remove - Device Removal Routine
7674 * @pdev: PCI device information struct
7675 *
7676 * ixgbe_remove is called by the PCI subsystem to alert the driver
7677 * that it should release a PCI device. The could be caused by a
7678 * Hot-Plug event, or because the driver is going to be removed from
7679 * memory.
7680 **/
7681static void __devexit ixgbe_remove(struct pci_dev *pdev)
7682{
c60fbb00
AD		 7683 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7684 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7685
7686 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7687 cancel_work_sync(&adapter->service_task);
760141a5 7688
c4cf55e5
PWJ		 7689 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7690 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7691 cancel_work_sync(&adapter->fdir_reinit_task);
760141a5
TH		 7692 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7693 cancel_work_sync(&adapter->check_overtemp_task);
9a799d71 7694
5dd2d332 7695#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7696 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7697 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7698 dca_remove_requester(&pdev->dev);
7699 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7700 }
7701
7702#endif
332d4a7d
YZ		 7703#ifdef IXGBE_FCOE
7704 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7705 ixgbe_cleanup_fcoe(adapter);
7706
7707#endif /* IXGBE_FCOE */
0365e6e4
PW		 7708
7709 /* remove the added san mac */
7710 ixgbe_del_sanmac_netdev(netdev);
7711
c4900be0
DS		 7712 if (netdev->reg_state == NETREG_REGISTERED)
7713 unregister_netdev(netdev);
9a799d71 7714
1cdd1ec8
GR		 7715 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7716 ixgbe_disable_sriov(adapter);
7717
7a921c93 7718 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7719
021230d4 7720 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7721
7722 iounmap(adapter->hw.hw_addr);
9ce77666 7723 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7724 IORESOURCE_MEM));
9a799d71 7725
849c4542 7726 e_dev_info("complete\n");
021230d4 7727
9a799d71
AK		 7728 free_netdev(netdev);
7729
19d5afd4 7730 pci_disable_pcie_error_reporting(pdev);
6fabd715 7731
9a799d71
AK		 7732 pci_disable_device(pdev);
7733}
7734
7735/**
7736 * ixgbe_io_error_detected - called when PCI error is detected
7737 * @pdev: Pointer to PCI device
7738 * @state: The current pci connection state
7739 *
7740 * This function is called after a PCI bus error affecting
7741 * this device has been detected.
7742 */
7743static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7744 pci_channel_state_t state)
9a799d71 7745{
c60fbb00
AD		 7746 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7747 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7748
7749 netif_device_detach(netdev);
7750
3044b8d1
BL		 7751 if (state == pci_channel_io_perm_failure)
7752 return PCI_ERS_RESULT_DISCONNECT;
7753
9a799d71
AK		 7754 if (netif_running(netdev))
7755 ixgbe_down(adapter);
7756 pci_disable_device(pdev);
7757
b4617240 7758 /* Request a slot reset. */
9a799d71
AK		 7759 return PCI_ERS_RESULT_NEED_RESET;
7760}
7761
7762/**
7763 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7764 * @pdev: Pointer to PCI device
7765 *
7766 * Restart the card from scratch, as if from a cold-boot.
7767 */
7768static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7769{
c60fbb00 7770 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7771 pci_ers_result_t result;
7772 int err;
9a799d71 7773
9ce77666 7774 if (pci_enable_device_mem(pdev)) {
396e799c 7775 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7776 result = PCI_ERS_RESULT_DISCONNECT;
7777 } else {
7778 pci_set_master(pdev);
7779 pci_restore_state(pdev);
c0e1f68b 7780 pci_save_state(pdev);
9a799d71 7781
dd4d8ca6 7782 pci_wake_from_d3(pdev, false);
9a799d71 7783
6fabd715 7784 ixgbe_reset(adapter);
88512539 7785 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7786 result = PCI_ERS_RESULT_RECOVERED;
7787 }
7788
7789 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7790 if (err) {
849c4542
ET		 7791 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7792 "failed 0x%0x\n", err);
6fabd715
PWJ		 7793 /* non-fatal, continue */
7794 }
9a799d71 7795
6fabd715 7796 return result;
9a799d71
AK		 7797}
7798
7799/**
7800 * ixgbe_io_resume - called when traffic can start flowing again.
7801 * @pdev: Pointer to PCI device
7802 *
7803 * This callback is called when the error recovery driver tells us that
7804 * its OK to resume normal operation.
7805 */
7806static void ixgbe_io_resume(struct pci_dev *pdev)
7807{
c60fbb00
AD		 7808 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7809 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7810
7811 if (netif_running(netdev)) {
7812 if (ixgbe_up(adapter)) {
396e799c 7813 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7814 return;
7815 }
7816 }
7817
7818 netif_device_attach(netdev);
9a799d71
AK		 7819}
7820
7821static struct pci_error_handlers ixgbe_err_handler = {
7822 .error_detected = ixgbe_io_error_detected,
7823 .slot_reset = ixgbe_io_slot_reset,
7824 .resume = ixgbe_io_resume,
7825};
7826
7827static struct pci_driver ixgbe_driver = {
7828 .name = ixgbe_driver_name,
7829 .id_table = ixgbe_pci_tbl,
7830 .probe = ixgbe_probe,
7831 .remove = __devexit_p(ixgbe_remove),
7832#ifdef CONFIG_PM
7833 .suspend = ixgbe_suspend,
7834 .resume = ixgbe_resume,
7835#endif
7836 .shutdown = ixgbe_shutdown,
7837 .err_handler = &ixgbe_err_handler
7838};
7839
7840/**
7841 * ixgbe_init_module - Driver Registration Routine
7842 *
7843 * ixgbe_init_module is the first routine called when the driver is
7844 * loaded. All it does is register with the PCI subsystem.
7845 **/
7846static int __init ixgbe_init_module(void)
7847{
7848 int ret;
c7689578 7849 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7850 pr_info("%s\n", ixgbe_copyright);
9a799d71 7851
5dd2d332 7852#ifdef CONFIG_IXGBE_DCA
bd0362dd 7853 dca_register_notify(&dca_notifier);
bd0362dd 7854#endif
5dd2d332 7855
9a799d71
AK		 7856 ret = pci_register_driver(&ixgbe_driver);
7857 return ret;
7858}
b4617240 7859
9a799d71
AK		 7860module_init(ixgbe_init_module);
7861
7862/**
7863 * ixgbe_exit_module - Driver Exit Cleanup Routine
7864 *
7865 * ixgbe_exit_module is called just before the driver is removed
7866 * from memory.
7867 **/
7868static void __exit ixgbe_exit_module(void)
7869{
5dd2d332 7870#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7871 dca_unregister_notify(&dca_notifier);
7872#endif
9a799d71 7873 pci_unregister_driver(&ixgbe_driver);
1a51502b 7874 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7875}
bd0362dd 7876
5dd2d332 7877#ifdef CONFIG_IXGBE_DCA
bd0362dd 7878static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7879 void *p)
bd0362dd
JC		 7880{
7881 int ret_val;
7882
7883 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7884 __ixgbe_notify_dca);
bd0362dd
JC		 7885
7886 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7887}
b453368d 7888
5dd2d332 7889#endif /* CONFIG_IXGBE_DCA */
849c4542 7890
9a799d71
AK		 7891module_exit(ixgbe_exit_module);
7892
7893/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)