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ixgbe: add support for 82599 Combined Backplane
[linux-block.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
60127865 37#include <linux/pkt_sched.h>
9a799d71
AK		 38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
eacd73f7 43#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 44
45#include "ixgbe.h"
46#include "ixgbe_common.h"
47
48char ixgbe_driver_name[] = "ixgbe";
9c8eb720 49static const char ixgbe_driver_string[] =
b4617240 50 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 51
e0f4daff 52#define DRV_VERSION "2.0.44-k2"
9c8eb720 53const char ixgbe_driver_version[] = DRV_VERSION;
3efac5a0 54static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
9a799d71
AK		 55
56static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 57 [board_82598] = &ixgbe_82598_info,
e8e26350 58 [board_82599] = &ixgbe_82599_info,
9a799d71
AK		 59};
60
61/* ixgbe_pci_tbl - PCI Device ID Table
62 *
63 * Wildcard entries (PCI_ANY_ID) should come last
64 * Last entry must be all 0s
65 *
66 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67 * Class, Class Mask, private data (not used) }
68 */
69static struct pci_device_id ixgbe_pci_tbl[] = {
1e336d0f
DS		 70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
71 board_82598 },
9a799d71 72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 73 board_82598 },
9a799d71 74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 75 board_82598 },
0befdb3e
JB		 76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
77 board_82598 },
3845bec0
PWJ		 78 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
79 board_82598 },
9a799d71 80 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 81 board_82598 },
8d792cd9
JB		 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
83 board_82598 },
c4900be0
DS		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
85 board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
87 board_82598 },
b95f5fcb
JB		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
89 board_82598 },
c4900be0
DS		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
91 board_82598 },
2f21bdd3
DS		 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
93 board_82598 },
e8e26350
PW		 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
95 board_82599 },
1fcf03e6
PWJ		 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
97 board_82599 },
e8e26350
PW		 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
99 board_82599 },
8911184f
PWJ		 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
101 board_82599 },
312eb931
DS		 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
103 board_82599 },
9a799d71
AK		 104
105 /* required last entry */
106 {0, }
107};
108MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
109
5dd2d332 110#ifdef CONFIG_IXGBE_DCA
bd0362dd 111static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 112 void *p);
bd0362dd
JC		 113static struct notifier_block dca_notifier = {
114 .notifier_call = ixgbe_notify_dca,
115 .next = NULL,
116 .priority = 0
117};
118#endif
119
9a799d71
AK		 120MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
121MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
122MODULE_LICENSE("GPL");
123MODULE_VERSION(DRV_VERSION);
124
125#define DEFAULT_DEBUG_LEVEL_SHIFT 3
126
5eba3699
AV		 127static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
128{
129 u32 ctrl_ext;
130
131 /* Let firmware take over control of h/w */
132 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 134 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 135}
136
137static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
138{
139 u32 ctrl_ext;
140
141 /* Let firmware know the driver has taken over */
142 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
143 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 144 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 145}
9a799d71 146
e8e26350
PW		 147/*
148 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
149 * @adapter: pointer to adapter struct
150 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
151 * @queue: queue to map the corresponding interrupt to
152 * @msix_vector: the vector to map to the corresponding queue
153 *
154 */
155static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
156 u8 queue, u8 msix_vector)
9a799d71
AK		 157{
158 u32 ivar, index;
e8e26350
PW		 159 struct ixgbe_hw *hw = &adapter->hw;
160 switch (hw->mac.type) {
161 case ixgbe_mac_82598EB:
162 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
163 if (direction == -1)
164 direction = 0;
165 index = (((direction * 64) + queue) >> 2) & 0x1F;
166 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
167 ivar &= ~(0xFF << (8 * (queue & 0x3)));
168 ivar |= (msix_vector << (8 * (queue & 0x3)));
169 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
170 break;
171 case ixgbe_mac_82599EB:
172 if (direction == -1) {
173 /* other causes */
174 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
175 index = ((queue & 1) * 8);
176 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
177 ivar &= ~(0xFF << index);
178 ivar |= (msix_vector << index);
179 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
180 break;
181 } else {
182 /* tx or rx causes */
183 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
184 index = ((16 * (queue & 1)) + (8 * direction));
185 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
186 ivar &= ~(0xFF << index);
187 ivar |= (msix_vector << index);
188 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
189 break;
190 }
191 default:
192 break;
193 }
9a799d71
AK		 194}
195
fe49f04a
AD		 196static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
197 u64 qmask)
198{
199 u32 mask;
200
201 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
202 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
203 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
204 } else {
205 mask = (qmask & 0xFFFFFFFF);
206 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
207 mask = (qmask >> 32);
208 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
209 }
210}
211
9a799d71 212static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 213 struct ixgbe_tx_buffer
214 *tx_buffer_info)
9a799d71 215{
44df32c5 216 tx_buffer_info->dma = 0;
9a799d71 217 if (tx_buffer_info->skb) {
44df32c5
AD		 218 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
219 DMA_TO_DEVICE);
9a799d71
AK		 220 dev_kfree_skb_any(tx_buffer_info->skb);
221 tx_buffer_info->skb = NULL;
222 }
44df32c5 223 tx_buffer_info->time_stamp = 0;
9a799d71
AK		 224 /* tx_buffer_info must be completely set up in the transmit path */
225}
226
227static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 228 struct ixgbe_ring *tx_ring,
229 unsigned int eop)
9a799d71 230{
e01c31a5 231 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 232
9a799d71 233 /* Detect a transmit hang in hardware, this serializes the
e01c31a5 234 * check with the clearing of time_stamp and movement of eop */
9a799d71 235 adapter->detect_tx_hung = false;
44df32c5 236 if (tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 237 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
238 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
239 /* detected Tx unit hang */
e01c31a5
JB		 240 union ixgbe_adv_tx_desc *tx_desc;
241 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 242 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 243 " Tx Queue <%d>\n"
244 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 245 " next_to_use <%x>\n"
246 " next_to_clean <%x>\n"
247 "tx_buffer_info[next_to_clean]\n"
248 " time_stamp <%lx>\n"
e01c31a5
JB		 249 " jiffies <%lx>\n",
250 tx_ring->queue_index,
44df32c5
AD		 251 IXGBE_READ_REG(hw, tx_ring->head),
252 IXGBE_READ_REG(hw, tx_ring->tail),
e01c31a5
JB		 253 tx_ring->next_to_use, eop,
254 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 255 return true;
256 }
257
258 return false;
259}
260
b4617240
PW		 261#define IXGBE_MAX_TXD_PWR 14
262#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 263
264/* Tx Descriptors needed, worst case */
265#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
266 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
267#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 268 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 269
e01c31a5
JB		 270static void ixgbe_tx_timeout(struct net_device *netdev);
271
9a799d71
AK		 272/**
273 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 274 * @q_vector: structure containing interrupt and ring information
e01c31a5 275 * @tx_ring: tx ring to clean
9a799d71 276 **/
fe49f04a 277static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e01c31a5 278 struct ixgbe_ring *tx_ring)
9a799d71 279{
fe49f04a 280 struct ixgbe_adapter *adapter = q_vector->adapter;
e01c31a5 281 struct net_device *netdev = adapter->netdev;
12207e49
PWJ		 282 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
283 struct ixgbe_tx_buffer *tx_buffer_info;
284 unsigned int i, eop, count = 0;
e01c31a5 285 unsigned int total_bytes = 0, total_packets = 0;
9a799d71
AK		 286
287 i = tx_ring->next_to_clean;
12207e49
PWJ		 288 eop = tx_ring->tx_buffer_info[i].next_to_watch;
289 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
290
291 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
9a1a69ad 292 (count < tx_ring->work_limit)) {
12207e49
PWJ		 293 bool cleaned = false;
294 for ( ; !cleaned; count++) {
295 struct sk_buff *skb;
9a799d71
AK		 296 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
297 tx_buffer_info = &tx_ring->tx_buffer_info[i];
12207e49 298 cleaned = (i == eop);
e01c31a5 299 skb = tx_buffer_info->skb;
9a799d71 300
12207e49 301 if (cleaned && skb) {
e092be60 302 unsigned int segs, bytecount;
3d8fd385 303 unsigned int hlen = skb_headlen(skb);
e01c31a5
JB		 304
305 /* gso_segs is currently only valid for tcp */
e092be60 306 segs = skb_shinfo(skb)->gso_segs ?: 1;
3d8fd385
YZ		 307#ifdef IXGBE_FCOE
308 /* adjust for FCoE Sequence Offload */
309 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
310 && (skb->protocol == htons(ETH_P_FCOE)) &&
311 skb_is_gso(skb)) {
312 hlen = skb_transport_offset(skb) +
313 sizeof(struct fc_frame_header) +
314 sizeof(struct fcoe_crc_eof);
315 segs = DIV_ROUND_UP(skb->len - hlen,
316 skb_shinfo(skb)->gso_size);
317 }
318#endif /* IXGBE_FCOE */
e092be60 319 /* multiply data chunks by size of headers */
3d8fd385 320 bytecount = ((segs - 1) * hlen) + skb->len;
e01c31a5
JB		 321 total_packets += segs;
322 total_bytes += bytecount;
e092be60 323 }
e01c31a5 324
9a799d71 325 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 326 tx_buffer_info);
9a799d71 327
12207e49
PWJ		 328 tx_desc->wb.status = 0;
329
9a799d71
AK		 330 i++;
331 if (i == tx_ring->count)
332 i = 0;
e01c31a5 333 }
12207e49
PWJ		 334
335 eop = tx_ring->tx_buffer_info[i].next_to_watch;
336 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
337 }
338
9a799d71
AK		 339 tx_ring->next_to_clean = i;
340
e092be60 341#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 342 if (unlikely(count && netif_carrier_ok(netdev) &&
343 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 344 /* Make sure that anybody stopping the queue after this
345 * sees the new next_to_clean.
346 */
347 smp_mb();
30eba97a
AV		 348 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
349 !test_bit(__IXGBE_DOWN, &adapter->state)) {
350 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 351 ++adapter->restart_queue;
30eba97a 352 }
e092be60 353 }
9a799d71 354
e01c31a5
JB		 355 if (adapter->detect_tx_hung) {
356 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
357 /* schedule immediate reset if we believe we hung */
358 DPRINTK(PROBE, INFO,
359 "tx hang %d detected, resetting adapter\n",
360 adapter->tx_timeout_count + 1);
361 ixgbe_tx_timeout(adapter->netdev);
362 }
363 }
9a799d71 364
e01c31a5 365 /* re-arm the interrupt */
fe49f04a
AD		 366 if (count >= tx_ring->work_limit)
367 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
9a799d71 368
e01c31a5
JB		 369 tx_ring->total_bytes += total_bytes;
370 tx_ring->total_packets += total_packets;
e01c31a5 371 tx_ring->stats.packets += total_packets;
12207e49 372 tx_ring->stats.bytes += total_bytes;
e01c31a5
JB		 373 adapter->net_stats.tx_bytes += total_bytes;
374 adapter->net_stats.tx_packets += total_packets;
9a1a69ad 375 return (count < tx_ring->work_limit);
9a799d71
AK		 376}
377
5dd2d332 378#ifdef CONFIG_IXGBE_DCA
bd0362dd 379static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 380 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 381{
382 u32 rxctrl;
383 int cpu = get_cpu();
3a581073 384 int q = rx_ring - adapter->rx_ring;
bd0362dd 385
3a581073 386 if (rx_ring->cpu != cpu) {
bd0362dd 387 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
e8e26350
PW		 388 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
389 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
390 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
391 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
392 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
393 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
394 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
395 }
bd0362dd
JC		 396 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
397 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
15005a32
DS		 398 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
399 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
e8e26350 400 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
bd0362dd 401 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 402 rx_ring->cpu = cpu;
bd0362dd
JC		 403 }
404 put_cpu();
405}
406
407static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 408 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 409{
410 u32 txctrl;
411 int cpu = get_cpu();
3a581073 412 int q = tx_ring - adapter->tx_ring;
bd0362dd 413
3a581073 414 if (tx_ring->cpu != cpu) {
bd0362dd 415 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
e8e26350
PW		 416 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
417 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
418 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
419 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
420 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
421 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
422 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
423 }
bd0362dd
JC		 424 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
425 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 426 tx_ring->cpu = cpu;
bd0362dd
JC		 427 }
428 put_cpu();
429}
430
431static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
432{
433 int i;
434
435 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
436 return;
437
e35ec126
AD		 438 /* always use CB2 mode, difference is masked in the CB driver */
439 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
440
bd0362dd
JC		 441 for (i = 0; i < adapter->num_tx_queues; i++) {
442 adapter->tx_ring[i].cpu = -1;
443 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
444 }
445 for (i = 0; i < adapter->num_rx_queues; i++) {
446 adapter->rx_ring[i].cpu = -1;
447 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
448 }
449}
450
451static int __ixgbe_notify_dca(struct device *dev, void *data)
452{
453 struct net_device *netdev = dev_get_drvdata(dev);
454 struct ixgbe_adapter *adapter = netdev_priv(netdev);
455 unsigned long event = *(unsigned long *)data;
456
457 switch (event) {
458 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 459 /* if we're already enabled, don't do it again */
460 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
461 break;
652f093f 462 if (dca_add_requester(dev) == 0) {
96b0e0f6 463 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 464 ixgbe_setup_dca(adapter);
465 break;
466 }
467 /* Fall Through since DCA is disabled. */
468 case DCA_PROVIDER_REMOVE:
469 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
470 dca_remove_requester(dev);
471 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
472 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
473 }
474 break;
475 }
476
652f093f 477 return 0;
bd0362dd
JC		 478}
479
5dd2d332 480#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 481/**
482 * ixgbe_receive_skb - Send a completed packet up the stack
483 * @adapter: board private structure
484 * @skb: packet to send up
177db6ff
MC		 485 * @status: hardware indication of status of receive
486 * @rx_ring: rx descriptor ring (for a specific queue) to setup
487 * @rx_desc: rx descriptor
9a799d71 488 **/
78b6f4ce 489static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
b4617240 490 struct sk_buff *skb, u8 status,
fdaff1ce 491 struct ixgbe_ring *ring,
177db6ff 492 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 493{
78b6f4ce
HX		 494 struct ixgbe_adapter *adapter = q_vector->adapter;
495 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 496 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
497 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 498
fdaff1ce 499 skb_record_rx_queue(skb, ring->queue_index);
182ff8df 500 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
8a62babf 501 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
78b6f4ce 502 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
9a799d71 503 else
78b6f4ce 504 napi_gro_receive(napi, skb);
177db6ff 505 } else {
8a62babf 506 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
182ff8df
AD		 507 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
508 else
509 netif_rx(skb);
9a799d71
AK		 510 }
511}
512
e59bd25d
AV		 513/**
514 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
515 * @adapter: address of board private structure
516 * @status_err: hardware indication of status of receive
517 * @skb: skb currently being received and modified
518 **/
9a799d71 519static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b
DS		 520 union ixgbe_adv_rx_desc *rx_desc,
521 struct sk_buff *skb)
9a799d71 522{
8bae1b2b
DS		 523 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
524
9a799d71
AK		 525 skb->ip_summed = CHECKSUM_NONE;
526
712744be
JB		 527 /* Rx csum disabled */
528 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 529 return;
e59bd25d
AV		 530
531 /* if IP and error */
532 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
533 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 534 adapter->hw_csum_rx_error++;
535 return;
536 }
e59bd25d
AV		 537
538 if (!(status_err & IXGBE_RXD_STAT_L4CS))
539 return;
540
541 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 542 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
543
544 /*
545 * 82599 errata, UDP frames with a 0 checksum can be marked as
546 * checksum errors.
547 */
548 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
549 (adapter->hw.mac.type == ixgbe_mac_82599EB))
550 return;
551
e59bd25d
AV		 552 adapter->hw_csum_rx_error++;
553 return;
554 }
555
9a799d71 556 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 557 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 558 adapter->hw_csum_rx_good++;
559}
560
e8e26350
PW		 561static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
562 struct ixgbe_ring *rx_ring, u32 val)
563{
564 /*
565 * Force memory writes to complete before letting h/w
566 * know there are new descriptors to fetch. (Only
567 * applicable for weak-ordered memory model archs,
568 * such as IA-64).
569 */
570 wmb();
571 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
572}
573
9a799d71
AK		 574/**
575 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
576 * @adapter: address of board private structure
577 **/
578static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 579 struct ixgbe_ring *rx_ring,
580 int cleaned_count)
9a799d71 581{
9a799d71
AK		 582 struct pci_dev *pdev = adapter->pdev;
583 union ixgbe_adv_rx_desc *rx_desc;
3a581073 584 struct ixgbe_rx_buffer *bi;
9a799d71 585 unsigned int i;
9a799d71
AK		 586
587 i = rx_ring->next_to_use;
3a581073 588 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 589
590 while (cleaned_count--) {
591 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
592
762f4c57 593 if (!bi->page_dma &&
6e455b89 594 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
3a581073 595 if (!bi->page) {
762f4c57
JB		 596 bi->page = alloc_page(GFP_ATOMIC);
597 if (!bi->page) {
598 adapter->alloc_rx_page_failed++;
599 goto no_buffers;
600 }
601 bi->page_offset = 0;
602 } else {
603 /* use a half page if we're re-using */
604 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 605 }
762f4c57
JB		 606
607 bi->page_dma = pci_map_page(pdev, bi->page,
608 bi->page_offset,
609 (PAGE_SIZE / 2),
610 PCI_DMA_FROMDEVICE);
9a799d71
AK		 611 }
612
3a581073 613 if (!bi->skb) {
5ecc3614 614 struct sk_buff *skb;
4f57ca6e
JB		 615 skb = netdev_alloc_skb(adapter->netdev,
616 (rx_ring->rx_buf_len +
617 NET_IP_ALIGN));
9a799d71
AK		 618
619 if (!skb) {
620 adapter->alloc_rx_buff_failed++;
621 goto no_buffers;
622 }
623
624 /*
625 * Make buffer alignment 2 beyond a 16 byte boundary
626 * this will result in a 16 byte aligned IP header after
627 * the 14 byte MAC header is removed
628 */
629 skb_reserve(skb, NET_IP_ALIGN);
630
3a581073 631 bi->skb = skb;
4f57ca6e
JB		 632 bi->dma = pci_map_single(pdev, skb->data,
633 rx_ring->rx_buf_len,
3a581073 634 PCI_DMA_FROMDEVICE);
9a799d71
AK		 635 }
636 /* Refresh the desc even if buffer_addrs didn't change because
637 * each write-back erases this info. */
6e455b89 638 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
3a581073
JB		 639 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
640 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 641 } else {
3a581073 642 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 643 }
644
645 i++;
646 if (i == rx_ring->count)
647 i = 0;
3a581073 648 bi = &rx_ring->rx_buffer_info[i];
9a799d71 649 }
7c6e0a43 650
9a799d71
AK		 651no_buffers:
652 if (rx_ring->next_to_use != i) {
653 rx_ring->next_to_use = i;
654 if (i-- == 0)
655 i = (rx_ring->count - 1);
656
e8e26350 657 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
9a799d71
AK		 658 }
659}
660
7c6e0a43
JB		 661static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
662{
663 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
664}
665
666static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
667{
668 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
669}
670
f8212f97
AD		 671static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
672{
673 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
674 IXGBE_RXDADV_RSCCNT_MASK) >>
675 IXGBE_RXDADV_RSCCNT_SHIFT;
676}
677
678/**
679 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
680 * @skb: pointer to the last skb in the rsc queue
681 *
682 * This function changes a queue full of hw rsc buffers into a completed
683 * packet. It uses the ->prev pointers to find the first packet and then
684 * turns it into the frag list owner.
685 **/
686static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
687{
688 unsigned int frag_list_size = 0;
689
690 while (skb->prev) {
691 struct sk_buff *prev = skb->prev;
692 frag_list_size += skb->len;
693 skb->prev = NULL;
694 skb = prev;
695 }
696
697 skb_shinfo(skb)->frag_list = skb->next;
698 skb->next = NULL;
699 skb->len += frag_list_size;
700 skb->data_len += frag_list_size;
701 skb->truesize += frag_list_size;
702 return skb;
703}
704
78b6f4ce 705static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
b4617240
PW		 706 struct ixgbe_ring *rx_ring,
707 int *work_done, int work_to_do)
9a799d71 708{
78b6f4ce 709 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 710 struct pci_dev *pdev = adapter->pdev;
711 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
712 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
713 struct sk_buff *skb;
f8212f97 714 unsigned int i, rsc_count = 0;
7c6e0a43 715 u32 len, staterr;
177db6ff
MC		 716 u16 hdr_info;
717 bool cleaned = false;
9a799d71 718 int cleaned_count = 0;
d2f4fbe2 719 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3d8fd385
YZ		 720#ifdef IXGBE_FCOE
721 int ddp_bytes = 0;
722#endif /* IXGBE_FCOE */
9a799d71
AK		 723
724 i = rx_ring->next_to_clean;
9a799d71
AK		 725 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
726 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
727 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 728
729 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 730 u32 upper_len = 0;
9a799d71
AK		 731 if (*work_done >= work_to_do)
732 break;
733 (*work_done)++;
734
6e455b89 735 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
7c6e0a43
JB		 736 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
737 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 738 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 739 if (hdr_info & IXGBE_RXDADV_SPH)
740 adapter->rx_hdr_split++;
741 if (len > IXGBE_RX_HDR_SIZE)
742 len = IXGBE_RX_HDR_SIZE;
743 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 744 } else {
9a799d71 745 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 746 }
9a799d71
AK		 747
748 cleaned = true;
749 skb = rx_buffer_info->skb;
750 prefetch(skb->data - NET_IP_ALIGN);
751 rx_buffer_info->skb = NULL;
752
21fa4e66 753 if (rx_buffer_info->dma) {
9a799d71 754 pci_unmap_single(pdev, rx_buffer_info->dma,
5ecc3614 755 rx_ring->rx_buf_len,
b4617240 756 PCI_DMA_FROMDEVICE);
4f57ca6e 757 rx_buffer_info->dma = 0;
9a799d71
AK		 758 skb_put(skb, len);
759 }
760
761 if (upper_len) {
762 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 763 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 764 rx_buffer_info->page_dma = 0;
765 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 766 rx_buffer_info->page,
767 rx_buffer_info->page_offset,
768 upper_len);
769
770 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
771 (page_count(rx_buffer_info->page) != 1))
772 rx_buffer_info->page = NULL;
773 else
774 get_page(rx_buffer_info->page);
9a799d71
AK		 775
776 skb->len += upper_len;
777 skb->data_len += upper_len;
778 skb->truesize += upper_len;
779 }
780
781 i++;
782 if (i == rx_ring->count)
783 i = 0;
9a799d71
AK		 784
785 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
786 prefetch(next_rxd);
9a799d71 787 cleaned_count++;
f8212f97 788
0c19d6af 789 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
f8212f97
AD		 790 rsc_count = ixgbe_get_rsc_count(rx_desc);
791
792 if (rsc_count) {
793 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
794 IXGBE_RXDADV_NEXTP_SHIFT;
795 next_buffer = &rx_ring->rx_buffer_info[nextp];
796 rx_ring->rsc_count += (rsc_count - 1);
797 } else {
798 next_buffer = &rx_ring->rx_buffer_info[i];
799 }
800
9a799d71 801 if (staterr & IXGBE_RXD_STAT_EOP) {
f8212f97
AD		 802 if (skb->prev)
803 skb = ixgbe_transform_rsc_queue(skb);
9a799d71
AK		 804 rx_ring->stats.packets++;
805 rx_ring->stats.bytes += skb->len;
806 } else {
6e455b89 807 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
f8212f97
AD		 808 rx_buffer_info->skb = next_buffer->skb;
809 rx_buffer_info->dma = next_buffer->dma;
810 next_buffer->skb = skb;
811 next_buffer->dma = 0;
812 } else {
813 skb->next = next_buffer->skb;
814 skb->next->prev = skb;
815 }
9a799d71
AK		 816 adapter->non_eop_descs++;
817 goto next_desc;
818 }
819
820 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
821 dev_kfree_skb_irq(skb);
822 goto next_desc;
823 }
824
8bae1b2b 825 ixgbe_rx_checksum(adapter, rx_desc, skb);
d2f4fbe2
AV		 826
827 /* probably a little skewed due to removing CRC */
828 total_rx_bytes += skb->len;
829 total_rx_packets++;
830
74ce8dd2 831 skb->protocol = eth_type_trans(skb, adapter->netdev);
332d4a7d
YZ		 832#ifdef IXGBE_FCOE
833 /* if ddp, not passing to ULD unless for FCP_RSP or error */
3d8fd385
YZ		 834 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
835 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
836 if (!ddp_bytes)
332d4a7d 837 goto next_desc;
3d8fd385 838 }
332d4a7d 839#endif /* IXGBE_FCOE */
fdaff1ce 840 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 841
842next_desc:
843 rx_desc->wb.upper.status_error = 0;
844
845 /* return some buffers to hardware, one at a time is too slow */
846 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
847 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
848 cleaned_count = 0;
849 }
850
851 /* use prefetched values */
852 rx_desc = next_rxd;
f8212f97 853 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 854
855 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 856 }
857
9a799d71
AK		 858 rx_ring->next_to_clean = i;
859 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
860
861 if (cleaned_count)
862 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
863
3d8fd385
YZ		 864#ifdef IXGBE_FCOE
865 /* include DDPed FCoE data */
866 if (ddp_bytes > 0) {
867 unsigned int mss;
868
869 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
870 sizeof(struct fc_frame_header) -
871 sizeof(struct fcoe_crc_eof);
872 if (mss > 512)
873 mss &= ~511;
874 total_rx_bytes += ddp_bytes;
875 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
876 }
877#endif /* IXGBE_FCOE */
878
f494e8fa
AV		 879 rx_ring->total_packets += total_rx_packets;
880 rx_ring->total_bytes += total_rx_bytes;
881 adapter->net_stats.rx_bytes += total_rx_bytes;
882 adapter->net_stats.rx_packets += total_rx_packets;
883
9a799d71
AK		 884 return cleaned;
885}
886
021230d4 887static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 888/**
889 * ixgbe_configure_msix - Configure MSI-X hardware
890 * @adapter: board private structure
891 *
892 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
893 * interrupts.
894 **/
895static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
896{
021230d4
AV		 897 struct ixgbe_q_vector *q_vector;
898 int i, j, q_vectors, v_idx, r_idx;
899 u32 mask;
9a799d71 900
021230d4 901 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 902
4df10466
JB		 903 /*
904 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 905 * corresponding register.
906 */
907 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
7a921c93 908 q_vector = adapter->q_vector[v_idx];
021230d4
AV		 909 /* XXX for_each_bit(...) */
910 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 911 adapter->num_rx_queues);
021230d4
AV		 912
913 for (i = 0; i < q_vector->rxr_count; i++) {
914 j = adapter->rx_ring[r_idx].reg_idx;
e8e26350 915 ixgbe_set_ivar(adapter, 0, j, v_idx);
021230d4 916 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 917 adapter->num_rx_queues,
918 r_idx + 1);
021230d4
AV		 919 }
920 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 921 adapter->num_tx_queues);
021230d4
AV		 922
923 for (i = 0; i < q_vector->txr_count; i++) {
924 j = adapter->tx_ring[r_idx].reg_idx;
e8e26350 925 ixgbe_set_ivar(adapter, 1, j, v_idx);
021230d4 926 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 927 adapter->num_tx_queues,
928 r_idx + 1);
021230d4
AV		 929 }
930
021230d4 931 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 932 /* tx only */
933 q_vector->eitr = adapter->tx_eitr_param;
509ee935 934 else if (q_vector->rxr_count)
f7554a2b
NS		 935 /* rx or mixed */
936 q_vector->eitr = adapter->rx_eitr_param;
021230d4 937
fe49f04a 938 ixgbe_write_eitr(q_vector);
9a799d71
AK		 939 }
940
e8e26350
PW		 941 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
942 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
943 v_idx);
944 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
945 ixgbe_set_ivar(adapter, -1, 1, v_idx);
021230d4
AV		 946 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
947
41fb9248 948 /* set up to autoclear timer, and the vectors */
021230d4 949 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 950 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 951 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 952}
953
f494e8fa
AV		 954enum latency_range {
955 lowest_latency = 0,
956 low_latency = 1,
957 bulk_latency = 2,
958 latency_invalid = 255
959};
960
961/**
962 * ixgbe_update_itr - update the dynamic ITR value based on statistics
963 * @adapter: pointer to adapter
964 * @eitr: eitr setting (ints per sec) to give last timeslice
965 * @itr_setting: current throttle rate in ints/second
966 * @packets: the number of packets during this measurement interval
967 * @bytes: the number of bytes during this measurement interval
968 *
969 * Stores a new ITR value based on packets and byte
970 * counts during the last interrupt. The advantage of per interrupt
971 * computation is faster updates and more accurate ITR for the current
972 * traffic pattern. Constants in this function were computed
973 * based on theoretical maximum wire speed and thresholds were set based
974 * on testing data as well as attempting to minimize response time
975 * while increasing bulk throughput.
976 * this functionality is controlled by the InterruptThrottleRate module
977 * parameter (see ixgbe_param.c)
978 **/
979static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 980 u32 eitr, u8 itr_setting,
981 int packets, int bytes)
f494e8fa
AV		 982{
983 unsigned int retval = itr_setting;
984 u32 timepassed_us;
985 u64 bytes_perint;
986
987 if (packets == 0)
988 goto update_itr_done;
989
990
991 /* simple throttlerate management
992 * 0-20MB/s lowest (100000 ints/s)
993 * 20-100MB/s low (20000 ints/s)
994 * 100-1249MB/s bulk (8000 ints/s)
995 */
996 /* what was last interrupt timeslice? */
997 timepassed_us = 1000000/eitr;
998 bytes_perint = bytes / timepassed_us; /* bytes/usec */
999
1000 switch (itr_setting) {
1001 case lowest_latency:
1002 if (bytes_perint > adapter->eitr_low)
1003 retval = low_latency;
1004 break;
1005 case low_latency:
1006 if (bytes_perint > adapter->eitr_high)
1007 retval = bulk_latency;
1008 else if (bytes_perint <= adapter->eitr_low)
1009 retval = lowest_latency;
1010 break;
1011 case bulk_latency:
1012 if (bytes_perint <= adapter->eitr_high)
1013 retval = low_latency;
1014 break;
1015 }
1016
1017update_itr_done:
1018 return retval;
1019}
1020
509ee935
JB		 1021/**
1022 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1023 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1024 *
1025 * This function is made to be called by ethtool and by the driver
1026 * when it needs to update EITR registers at runtime. Hardware
1027 * specific quirks/differences are taken care of here.
1028 */
fe49f04a 1029void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1030{
fe49f04a 1031 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1032 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1033 int v_idx = q_vector->v_idx;
1034 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1035
509ee935
JB		 1036 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1037 /* must write high and low 16 bits to reset counter */
1038 itr_reg |= (itr_reg << 16);
1039 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1040 /*
1041 * set the WDIS bit to not clear the timer bits and cause an
1042 * immediate assertion of the interrupt
1043 */
1044 itr_reg |= IXGBE_EITR_CNT_WDIS;
1045 }
1046 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1047}
1048
f494e8fa
AV		 1049static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1050{
1051 struct ixgbe_adapter *adapter = q_vector->adapter;
f494e8fa
AV		 1052 u32 new_itr;
1053 u8 current_itr, ret_itr;
fe49f04a 1054 int i, r_idx;
f494e8fa
AV		 1055 struct ixgbe_ring *rx_ring, *tx_ring;
1056
1057 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1058 for (i = 0; i < q_vector->txr_count; i++) {
1059 tx_ring = &(adapter->tx_ring[r_idx]);
1060 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1061 q_vector->tx_itr,
1062 tx_ring->total_packets,
1063 tx_ring->total_bytes);
f494e8fa
AV		 1064 /* if the result for this queue would decrease interrupt
1065 * rate for this vector then use that result */
30efa5a3 1066 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 1067 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 1068 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1069 r_idx + 1);
f494e8fa
AV		 1070 }
1071
1072 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1073 for (i = 0; i < q_vector->rxr_count; i++) {
1074 rx_ring = &(adapter->rx_ring[r_idx]);
1075 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 1076 q_vector->rx_itr,
1077 rx_ring->total_packets,
1078 rx_ring->total_bytes);
f494e8fa
AV		 1079 /* if the result for this queue would decrease interrupt
1080 * rate for this vector then use that result */
30efa5a3 1081 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 1082 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 1083 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 1084 r_idx + 1);
f494e8fa
AV		 1085 }
1086
30efa5a3 1087 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1088
1089 switch (current_itr) {
1090 /* counts and packets in update_itr are dependent on these numbers */
1091 case lowest_latency:
1092 new_itr = 100000;
1093 break;
1094 case low_latency:
1095 new_itr = 20000; /* aka hwitr = ~200 */
1096 break;
1097 case bulk_latency:
1098 default:
1099 new_itr = 8000;
1100 break;
1101 }
1102
1103 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1104 /* do an exponential smoothing */
1105 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1106
1107 /* save the algorithm value here, not the smoothed one */
1108 q_vector->eitr = new_itr;
fe49f04a
AD		 1109
1110 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1111 }
1112
1113 return;
1114}
1115
0befdb3e
JB		 1116static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1117{
1118 struct ixgbe_hw *hw = &adapter->hw;
1119
1120 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1121 (eicr & IXGBE_EICR_GPI_SDP1)) {
1122 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1123 /* write to clear the interrupt */
1124 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1125 }
1126}
cf8280ee 1127
e8e26350
PW		 1128static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1129{
1130 struct ixgbe_hw *hw = &adapter->hw;
1131
1132 if (eicr & IXGBE_EICR_GPI_SDP1) {
1133 /* Clear the interrupt */
1134 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1135 schedule_work(&adapter->multispeed_fiber_task);
1136 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1137 /* Clear the interrupt */
1138 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1139 schedule_work(&adapter->sfp_config_module_task);
1140 } else {
1141 /* Interrupt isn't for us... */
1142 return;
1143 }
1144}
1145
cf8280ee
JB		 1146static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1147{
1148 struct ixgbe_hw *hw = &adapter->hw;
1149
1150 adapter->lsc_int++;
1151 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1152 adapter->link_check_timeout = jiffies;
1153 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1154 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1155 schedule_work(&adapter->watchdog_task);
1156 }
1157}
1158
9a799d71
AK		 1159static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1160{
1161 struct net_device *netdev = data;
1162 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1163 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1164 u32 eicr;
1165
1166 /*
1167 * Workaround for Silicon errata. Use clear-by-write instead
1168 * of clear-by-read. Reading with EICS will return the
1169 * interrupt causes without clearing, which later be done
1170 * with the write to EICR.
1171 */
1172 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1173 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1174
cf8280ee
JB		 1175 if (eicr & IXGBE_EICR_LSC)
1176 ixgbe_check_lsc(adapter);
d4f80882 1177
e8e26350
PW		 1178 if (hw->mac.type == ixgbe_mac_82598EB)
1179 ixgbe_check_fan_failure(adapter, eicr);
0befdb3e 1180
c4cf55e5 1181 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 1182 ixgbe_check_sfp_event(adapter, eicr);
c4cf55e5
PWJ		 1183
1184 /* Handle Flow Director Full threshold interrupt */
1185 if (eicr & IXGBE_EICR_FLOW_DIR) {
1186 int i;
1187 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1188 /* Disable transmits before FDIR Re-initialization */
1189 netif_tx_stop_all_queues(netdev);
1190 for (i = 0; i < adapter->num_tx_queues; i++) {
1191 struct ixgbe_ring *tx_ring =
1192 &adapter->tx_ring[i];
1193 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1194 &tx_ring->reinit_state))
1195 schedule_work(&adapter->fdir_reinit_task);
1196 }
1197 }
1198 }
d4f80882
AV		 1199 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1200 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 1201
1202 return IRQ_HANDLED;
1203}
1204
fe49f04a
AD		 1205static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1206 u64 qmask)
1207{
1208 u32 mask;
1209
1210 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1211 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1212 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1213 } else {
1214 mask = (qmask & 0xFFFFFFFF);
1215 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1216 mask = (qmask >> 32);
1217 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1218 }
1219 /* skip the flush */
1220}
1221
1222static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1223 u64 qmask)
1224{
1225 u32 mask;
1226
1227 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1228 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1229 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1230 } else {
1231 mask = (qmask & 0xFFFFFFFF);
1232 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1233 mask = (qmask >> 32);
1234 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1235 }
1236 /* skip the flush */
1237}
1238
9a799d71
AK		 1239static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1240{
021230d4
AV		 1241 struct ixgbe_q_vector *q_vector = data;
1242 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1243 struct ixgbe_ring *tx_ring;
021230d4
AV		 1244 int i, r_idx;
1245
1246 if (!q_vector->txr_count)
1247 return IRQ_HANDLED;
1248
1249 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1250 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 1251 tx_ring = &(adapter->tx_ring[r_idx]);
3a581073
JB		 1252 tx_ring->total_bytes = 0;
1253 tx_ring->total_packets = 0;
021230d4 1254 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 1255 r_idx + 1);
021230d4 1256 }
9a799d71 1257
91281fd3
AD		 1258 /* disable interrupts on this vector only */
1259 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1260 napi_schedule(&q_vector->napi);
1261
9a799d71
AK		 1262 return IRQ_HANDLED;
1263}
1264
021230d4
AV		 1265/**
1266 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1267 * @irq: unused
1268 * @data: pointer to our q_vector struct for this interrupt vector
1269 **/
9a799d71
AK		 1270static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1271{
021230d4
AV		 1272 struct ixgbe_q_vector *q_vector = data;
1273 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 1274 struct ixgbe_ring *rx_ring;
021230d4 1275 int r_idx;
30efa5a3 1276 int i;
021230d4
AV		 1277
1278 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 1279 for (i = 0; i < q_vector->rxr_count; i++) {
1280 rx_ring = &(adapter->rx_ring[r_idx]);
1281 rx_ring->total_bytes = 0;
1282 rx_ring->total_packets = 0;
1283 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1284 r_idx + 1);
1285 }
1286
021230d4
AV		 1287 if (!q_vector->rxr_count)
1288 return IRQ_HANDLED;
1289
30efa5a3 1290 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1291 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1292 /* disable interrupts on this vector only */
fe49f04a 1293 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
288379f0 1294 napi_schedule(&q_vector->napi);
021230d4
AV		 1295
1296 return IRQ_HANDLED;
1297}
1298
1299static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1300{
91281fd3
AD		 1301 struct ixgbe_q_vector *q_vector = data;
1302 struct ixgbe_adapter *adapter = q_vector->adapter;
1303 struct ixgbe_ring *ring;
1304 int r_idx;
1305 int i;
1306
1307 if (!q_vector->txr_count && !q_vector->rxr_count)
1308 return IRQ_HANDLED;
1309
1310 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1311 for (i = 0; i < q_vector->txr_count; i++) {
1312 ring = &(adapter->tx_ring[r_idx]);
1313 ring->total_bytes = 0;
1314 ring->total_packets = 0;
1315 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1316 r_idx + 1);
1317 }
1318
1319 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1320 for (i = 0; i < q_vector->rxr_count; i++) {
1321 ring = &(adapter->rx_ring[r_idx]);
1322 ring->total_bytes = 0;
1323 ring->total_packets = 0;
1324 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1325 r_idx + 1);
1326 }
1327
1328 /* disable interrupts on this vector only */
1329 ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1330 napi_schedule(&q_vector->napi);
9a799d71 1331
9a799d71
AK		 1332 return IRQ_HANDLED;
1333}
1334
021230d4
AV		 1335/**
1336 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1337 * @napi: napi struct with our devices info in it
1338 * @budget: amount of work driver is allowed to do this pass, in packets
1339 *
f0848276
JB		 1340 * This function is optimized for cleaning one queue only on a single
1341 * q_vector!!!
021230d4 1342 **/
9a799d71
AK		 1343static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1344{
021230d4 1345 struct ixgbe_q_vector *q_vector =
b4617240 1346 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1347 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1348 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1349 int work_done = 0;
021230d4 1350 long r_idx;
9a799d71 1351
021230d4 1352 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1353 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1354#ifdef CONFIG_IXGBE_DCA
bd0362dd 1355 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1356 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1357#endif
9a799d71 1358
78b6f4ce 1359 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
9a799d71 1360
021230d4
AV		 1361 /* If all Rx work done, exit the polling mode */
1362 if (work_done < budget) {
288379f0 1363 napi_complete(napi);
f7554a2b 1364 if (adapter->rx_itr_setting & 1)
f494e8fa 1365 ixgbe_set_itr_msix(q_vector);
9a799d71 1366 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1367 ixgbe_irq_enable_queues(adapter,
1368 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 1369 }
1370
1371 return work_done;
1372}
1373
f0848276 1374/**
91281fd3 1375 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 1376 * @napi: napi struct with our devices info in it
1377 * @budget: amount of work driver is allowed to do this pass, in packets
1378 *
1379 * This function will clean more than one rx queue associated with a
1380 * q_vector.
1381 **/
91281fd3 1382static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 1383{
1384 struct ixgbe_q_vector *q_vector =
1385 container_of(napi, struct ixgbe_q_vector, napi);
1386 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 1387 struct ixgbe_ring *ring = NULL;
f0848276
JB		 1388 int work_done = 0, i;
1389 long r_idx;
91281fd3
AD		 1390 bool tx_clean_complete = true;
1391
1392 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1393 for (i = 0; i < q_vector->txr_count; i++) {
1394 ring = &(adapter->tx_ring[r_idx]);
1395#ifdef CONFIG_IXGBE_DCA
1396 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1397 ixgbe_update_tx_dca(adapter, ring);
1398#endif
1399 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1400 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1401 r_idx + 1);
1402 }
f0848276
JB		 1403
1404 /* attempt to distribute budget to each queue fairly, but don't allow
1405 * the budget to go below 1 because we'll exit polling */
1406 budget /= (q_vector->rxr_count ?: 1);
1407 budget = max(budget, 1);
1408 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1409 for (i = 0; i < q_vector->rxr_count; i++) {
91281fd3 1410 ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1411#ifdef CONFIG_IXGBE_DCA
f0848276 1412 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
91281fd3 1413 ixgbe_update_rx_dca(adapter, ring);
f0848276 1414#endif
91281fd3 1415 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276
JB		 1416 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1417 r_idx + 1);
1418 }
1419
1420 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
91281fd3 1421 ring = &(adapter->rx_ring[r_idx]);
f0848276 1422 /* If all Rx work done, exit the polling mode */
7f821875 1423 if (work_done < budget) {
288379f0 1424 napi_complete(napi);
f7554a2b 1425 if (adapter->rx_itr_setting & 1)
f0848276
JB		 1426 ixgbe_set_itr_msix(q_vector);
1427 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a
AD		 1428 ixgbe_irq_enable_queues(adapter,
1429 ((u64)1 << q_vector->v_idx));
f0848276
JB		 1430 return 0;
1431 }
1432
1433 return work_done;
1434}
91281fd3
AD		 1435
1436/**
1437 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1438 * @napi: napi struct with our devices info in it
1439 * @budget: amount of work driver is allowed to do this pass, in packets
1440 *
1441 * This function is optimized for cleaning one queue only on a single
1442 * q_vector!!!
1443 **/
1444static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1445{
1446 struct ixgbe_q_vector *q_vector =
1447 container_of(napi, struct ixgbe_q_vector, napi);
1448 struct ixgbe_adapter *adapter = q_vector->adapter;
1449 struct ixgbe_ring *tx_ring = NULL;
1450 int work_done = 0;
1451 long r_idx;
1452
1453 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1454 tx_ring = &(adapter->tx_ring[r_idx]);
1455#ifdef CONFIG_IXGBE_DCA
1456 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1457 ixgbe_update_tx_dca(adapter, tx_ring);
1458#endif
1459
1460 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1461 work_done = budget;
1462
f7554a2b 1463 /* If all Tx work done, exit the polling mode */
91281fd3
AD		 1464 if (work_done < budget) {
1465 napi_complete(napi);
f7554a2b 1466 if (adapter->tx_itr_setting & 1)
91281fd3
AD		 1467 ixgbe_set_itr_msix(q_vector);
1468 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1469 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1470 }
1471
1472 return work_done;
1473}
1474
021230d4 1475static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1476 int r_idx)
021230d4 1477{
7a921c93
AD		 1478 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1479
1480 set_bit(r_idx, q_vector->rxr_idx);
1481 q_vector->rxr_count++;
021230d4
AV		 1482}
1483
1484static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
7a921c93 1485 int t_idx)
021230d4 1486{
7a921c93
AD		 1487 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1488
1489 set_bit(t_idx, q_vector->txr_idx);
1490 q_vector->txr_count++;
021230d4
AV		 1491}
1492
9a799d71 1493/**
021230d4
AV		 1494 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1495 * @adapter: board private structure to initialize
1496 * @vectors: allotted vector count for descriptor rings
9a799d71 1497 *
021230d4
AV		 1498 * This function maps descriptor rings to the queue-specific vectors
1499 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1500 * one vector per ring/queue, but on a constrained vector budget, we
1501 * group the rings as "efficiently" as possible. You would add new
1502 * mapping configurations in here.
9a799d71 1503 **/
021230d4 1504static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1505 int vectors)
021230d4
AV		 1506{
1507 int v_start = 0;
1508 int rxr_idx = 0, txr_idx = 0;
1509 int rxr_remaining = adapter->num_rx_queues;
1510 int txr_remaining = adapter->num_tx_queues;
1511 int i, j;
1512 int rqpv, tqpv;
1513 int err = 0;
1514
1515 /* No mapping required if MSI-X is disabled. */
1516 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1517 goto out;
9a799d71 1518
021230d4
AV		 1519 /*
1520 * The ideal configuration...
1521 * We have enough vectors to map one per queue.
1522 */
1523 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1524 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1525 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1526
021230d4
AV		 1527 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1528 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1529
9a799d71 1530 goto out;
021230d4 1531 }
9a799d71 1532
021230d4
AV		 1533 /*
1534 * If we don't have enough vectors for a 1-to-1
1535 * mapping, we'll have to group them so there are
1536 * multiple queues per vector.
1537 */
1538 /* Re-adjusting *qpv takes care of the remainder. */
1539 for (i = v_start; i < vectors; i++) {
1540 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1541 for (j = 0; j < rqpv; j++) {
1542 map_vector_to_rxq(adapter, i, rxr_idx);
1543 rxr_idx++;
1544 rxr_remaining--;
1545 }
1546 }
1547 for (i = v_start; i < vectors; i++) {
1548 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1549 for (j = 0; j < tqpv; j++) {
1550 map_vector_to_txq(adapter, i, txr_idx);
1551 txr_idx++;
1552 txr_remaining--;
9a799d71 1553 }
9a799d71
AK		 1554 }
1555
021230d4
AV		 1556out:
1557 return err;
1558}
1559
1560/**
1561 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1562 * @adapter: board private structure
1563 *
1564 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1565 * interrupts from the kernel.
1566 **/
1567static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1568{
1569 struct net_device *netdev = adapter->netdev;
1570 irqreturn_t (*handler)(int, void *);
1571 int i, vector, q_vectors, err;
cb13fc20 1572 int ri=0, ti=0;
021230d4
AV		 1573
1574 /* Decrement for Other and TCP Timer vectors */
1575 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1576
1577 /* Map the Tx/Rx rings to the vectors we were allotted. */
1578 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1579 if (err)
1580 goto out;
1581
1582#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1583 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1584 &ixgbe_msix_clean_many)
021230d4 1585 for (vector = 0; vector < q_vectors; vector++) {
7a921c93 1586 handler = SET_HANDLER(adapter->q_vector[vector]);
cb13fc20
RO		 1587
1588 if(handler == &ixgbe_msix_clean_rx) {
1589 sprintf(adapter->name[vector], "%s-%s-%d",
1590 netdev->name, "rx", ri++);
1591 }
1592 else if(handler == &ixgbe_msix_clean_tx) {
1593 sprintf(adapter->name[vector], "%s-%s-%d",
1594 netdev->name, "tx", ti++);
1595 }
1596 else
1597 sprintf(adapter->name[vector], "%s-%s-%d",
1598 netdev->name, "TxRx", vector);
1599
021230d4 1600 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1601 handler, 0, adapter->name[vector],
7a921c93 1602 adapter->q_vector[vector]);
9a799d71
AK		 1603 if (err) {
1604 DPRINTK(PROBE, ERR,
b4617240
PW		 1605 "request_irq failed for MSIX interrupt "
1606 "Error: %d\n", err);
021230d4 1607 goto free_queue_irqs;
9a799d71 1608 }
9a799d71
AK		 1609 }
1610
021230d4
AV		 1611 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1612 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1613 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1614 if (err) {
1615 DPRINTK(PROBE, ERR,
1616 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1617 goto free_queue_irqs;
9a799d71
AK		 1618 }
1619
9a799d71
AK		 1620 return 0;
1621
021230d4
AV		 1622free_queue_irqs:
1623 for (i = vector - 1; i >= 0; i--)
1624 free_irq(adapter->msix_entries[--vector].vector,
7a921c93 1625 adapter->q_vector[i]);
021230d4
AV		 1626 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1627 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1628 kfree(adapter->msix_entries);
1629 adapter->msix_entries = NULL;
021230d4 1630out:
9a799d71
AK		 1631 return err;
1632}
1633
f494e8fa
AV		 1634static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1635{
7a921c93 1636 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
f494e8fa
AV		 1637 u8 current_itr;
1638 u32 new_itr = q_vector->eitr;
1639 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1640 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1641
30efa5a3 1642 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1643 q_vector->tx_itr,
1644 tx_ring->total_packets,
1645 tx_ring->total_bytes);
30efa5a3 1646 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1647 q_vector->rx_itr,
1648 rx_ring->total_packets,
1649 rx_ring->total_bytes);
f494e8fa 1650
30efa5a3 1651 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1652
1653 switch (current_itr) {
1654 /* counts and packets in update_itr are dependent on these numbers */
1655 case lowest_latency:
1656 new_itr = 100000;
1657 break;
1658 case low_latency:
1659 new_itr = 20000; /* aka hwitr = ~200 */
1660 break;
1661 case bulk_latency:
1662 new_itr = 8000;
1663 break;
1664 default:
1665 break;
1666 }
1667
1668 if (new_itr != q_vector->eitr) {
fe49f04a
AD		 1669 /* do an exponential smoothing */
1670 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
509ee935
JB		 1671
1672 /* save the algorithm value here, not the smoothed one */
1673 q_vector->eitr = new_itr;
fe49f04a
AD		 1674
1675 ixgbe_write_eitr(q_vector);
f494e8fa
AV		 1676 }
1677
1678 return;
1679}
1680
79aefa45
AD		 1681/**
1682 * ixgbe_irq_enable - Enable default interrupt generation settings
1683 * @adapter: board private structure
1684 **/
1685static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1686{
1687 u32 mask;
835462fc
NS		 1688
1689 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
6ab33d51
DM		 1690 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1691 mask |= IXGBE_EIMS_GPI_SDP1;
e8e26350 1692 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2a41ff81 1693 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 1694 mask |= IXGBE_EIMS_GPI_SDP1;
1695 mask |= IXGBE_EIMS_GPI_SDP2;
1696 }
c4cf55e5
PWJ		 1697 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1698 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1699 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 1700
79aefa45 1701 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
835462fc 1702 ixgbe_irq_enable_queues(adapter, ~0);
79aefa45
AD		 1703 IXGBE_WRITE_FLUSH(&adapter->hw);
1704}
021230d4 1705
9a799d71 1706/**
021230d4 1707 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1708 * @irq: interrupt number
1709 * @data: pointer to a network interface device structure
9a799d71
AK		 1710 **/
1711static irqreturn_t ixgbe_intr(int irq, void *data)
1712{
1713 struct net_device *netdev = data;
1714 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1715 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 1716 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 1717 u32 eicr;
1718
54037505
DS		 1719 /*
1720 * Workaround for silicon errata. Mask the interrupts
1721 * before the read of EICR.
1722 */
1723 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1724
021230d4
AV		 1725 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1726 * therefore no explict interrupt disable is necessary */
1727 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1728 if (!eicr) {
1729 /* shared interrupt alert!
1730 * make sure interrupts are enabled because the read will
1731 * have disabled interrupts due to EIAM */
1732 ixgbe_irq_enable(adapter);
9a799d71 1733 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1734 }
9a799d71 1735
cf8280ee
JB		 1736 if (eicr & IXGBE_EICR_LSC)
1737 ixgbe_check_lsc(adapter);
021230d4 1738
e8e26350
PW		 1739 if (hw->mac.type == ixgbe_mac_82599EB)
1740 ixgbe_check_sfp_event(adapter, eicr);
1741
0befdb3e
JB		 1742 ixgbe_check_fan_failure(adapter, eicr);
1743
7a921c93 1744 if (napi_schedule_prep(&(q_vector->napi))) {
f494e8fa
AV		 1745 adapter->tx_ring[0].total_packets = 0;
1746 adapter->tx_ring[0].total_bytes = 0;
1747 adapter->rx_ring[0].total_packets = 0;
1748 adapter->rx_ring[0].total_bytes = 0;
021230d4 1749 /* would disable interrupts here but EIAM disabled it */
7a921c93 1750 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 1751 }
1752
1753 return IRQ_HANDLED;
1754}
1755
021230d4
AV		 1756static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1757{
1758 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1759
1760 for (i = 0; i < q_vectors; i++) {
7a921c93 1761 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
021230d4
AV		 1762 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1763 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1764 q_vector->rxr_count = 0;
1765 q_vector->txr_count = 0;
1766 }
1767}
1768
9a799d71
AK		 1769/**
1770 * ixgbe_request_irq - initialize interrupts
1771 * @adapter: board private structure
1772 *
1773 * Attempts to configure interrupts using the best available
1774 * capabilities of the hardware and kernel.
1775 **/
021230d4 1776static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1777{
1778 struct net_device *netdev = adapter->netdev;
021230d4 1779 int err;
9a799d71 1780
021230d4
AV		 1781 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1782 err = ixgbe_request_msix_irqs(adapter);
1783 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1784 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1785 netdev->name, netdev);
021230d4
AV		 1786 } else {
1787 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1788 netdev->name, netdev);
9a799d71
AK		 1789 }
1790
9a799d71
AK		 1791 if (err)
1792 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1793
9a799d71
AK		 1794 return err;
1795}
1796
1797static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1798{
1799 struct net_device *netdev = adapter->netdev;
1800
1801 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1802 int i, q_vectors;
9a799d71 1803
021230d4
AV		 1804 q_vectors = adapter->num_msix_vectors;
1805
1806 i = q_vectors - 1;
9a799d71 1807 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1808
021230d4
AV		 1809 i--;
1810 for (; i >= 0; i--) {
1811 free_irq(adapter->msix_entries[i].vector,
7a921c93 1812 adapter->q_vector[i]);
021230d4
AV		 1813 }
1814
1815 ixgbe_reset_q_vectors(adapter);
1816 } else {
1817 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1818 }
1819}
1820
22d5a71b
JB		 1821/**
1822 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1823 * @adapter: board private structure
1824 **/
1825static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1826{
835462fc
NS		 1827 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1828 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1829 } else {
1830 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1831 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 1832 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
22d5a71b
JB		 1833 }
1834 IXGBE_WRITE_FLUSH(&adapter->hw);
1835 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1836 int i;
1837 for (i = 0; i < adapter->num_msix_vectors; i++)
1838 synchronize_irq(adapter->msix_entries[i].vector);
1839 } else {
1840 synchronize_irq(adapter->pdev->irq);
1841 }
1842}
1843
9a799d71
AK		 1844/**
1845 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1846 *
1847 **/
1848static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1849{
9a799d71
AK		 1850 struct ixgbe_hw *hw = &adapter->hw;
1851
021230d4 1852 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
f7554a2b 1853 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 1854
e8e26350
PW		 1855 ixgbe_set_ivar(adapter, 0, 0, 0);
1856 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 1857
1858 map_vector_to_rxq(adapter, 0, 0);
1859 map_vector_to_txq(adapter, 0, 0);
1860
1861 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1862}
1863
1864/**
3a581073 1865 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1866 * @adapter: board private structure
1867 *
1868 * Configure the Tx unit of the MAC after a reset.
1869 **/
1870static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1871{
12207e49 1872 u64 tdba;
9a799d71 1873 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1874 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1875
1876 /* Setup the HW Tx Head and Tail descriptor pointers */
1877 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1878 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1879 j = ring->reg_idx;
1880 tdba = ring->dma;
1881 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1882 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
284901a9 1883 (tdba & DMA_BIT_MASK(32)));
021230d4
AV		 1884 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1885 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1886 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1887 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1888 adapter->tx_ring[i].head = IXGBE_TDH(j);
1889 adapter->tx_ring[i].tail = IXGBE_TDT(j);
84f62d4b
PWJ		 1890 /*
1891 * Disable Tx Head Writeback RO bit, since this hoses
021230d4
AV		 1892 * bookkeeping if things aren't delivered in order.
1893 */
84f62d4b
PWJ		 1894 switch (hw->mac.type) {
1895 case ixgbe_mac_82598EB:
1896 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1897 break;
1898 case ixgbe_mac_82599EB:
1899 default:
1900 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(j));
1901 break;
1902 }
021230d4 1903 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
84f62d4b
PWJ		 1904 switch (hw->mac.type) {
1905 case ixgbe_mac_82598EB:
1906 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1907 break;
1908 case ixgbe_mac_82599EB:
1909 default:
1910 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(j), txctrl);
1911 break;
1912 }
9a799d71 1913 }
e8e26350
PW		 1914 if (hw->mac.type == ixgbe_mac_82599EB) {
1915 /* We enable 8 traffic classes, DCB only */
1916 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1917 IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1918 IXGBE_MTQC_8TC_8TQ));
1919 }
9a799d71
AK		 1920}
1921
e8e26350 1922#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 1923
a6616b42
YZ		 1924static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1925 struct ixgbe_ring *rx_ring)
cc41ac7c 1926{
cc41ac7c 1927 u32 srrctl;
a6616b42 1928 int index;
0cefafad 1929 struct ixgbe_ring_feature *feature = adapter->ring_feature;
3be1adfb 1930
a6616b42
YZ		 1931 index = rx_ring->reg_idx;
1932 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1933 unsigned long mask;
0cefafad 1934 mask = (unsigned long) feature[RING_F_RSS].mask;
3be1adfb 1935 index = index & mask;
cc41ac7c 1936 }
cc41ac7c
JB		 1937 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1938
1939 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1940 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1941
afafd5b0
AD		 1942 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1943 IXGBE_SRRCTL_BSIZEHDR_MASK;
1944
6e455b89 1945 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
afafd5b0
AD		 1946#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1947 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1948#else
1949 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1950#endif
cc41ac7c 1951 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 1952 } else {
afafd5b0
AD		 1953 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1954 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 1955 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 1956 }
e8e26350 1957
cc41ac7c
JB		 1958 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1959}
9a799d71 1960
0cefafad
JB		 1961static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1962{
1963 u32 mrqc = 0;
1964 int mask;
1965
1966 if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1967 return mrqc;
1968
1969 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1970#ifdef CONFIG_IXGBE_DCB
1971 | IXGBE_FLAG_DCB_ENABLED
1972#endif
1973 );
1974
1975 switch (mask) {
1976 case (IXGBE_FLAG_RSS_ENABLED):
1977 mrqc = IXGBE_MRQC_RSSEN;
1978 break;
1979#ifdef CONFIG_IXGBE_DCB
1980 case (IXGBE_FLAG_DCB_ENABLED):
1981 mrqc = IXGBE_MRQC_RT8TCEN;
1982 break;
1983#endif /* CONFIG_IXGBE_DCB */
1984 default:
1985 break;
1986 }
1987
1988 return mrqc;
1989}
1990
bb5a9ad2
NS		 1991/**
1992 * ixgbe_configure_rscctl - enable RSC for the indicated ring
1993 * @adapter: address of board private structure
1994 * @index: index of ring to set
1995 * @rx_buf_len: rx buffer length
1996 **/
1997static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, int index,
1998 int rx_buf_len)
1999{
2000 struct ixgbe_ring *rx_ring;
2001 struct ixgbe_hw *hw = &adapter->hw;
2002 int j;
2003 u32 rscctrl;
2004
2005 rx_ring = &adapter->rx_ring[index];
2006 j = rx_ring->reg_idx;
2007 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2008 rscctrl |= IXGBE_RSCCTL_RSCEN;
2009 /*
2010 * we must limit the number of descriptors so that the
2011 * total size of max desc * buf_len is not greater
2012 * than 65535
2013 */
2014 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2015#if (MAX_SKB_FRAGS > 16)
2016 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2017#elif (MAX_SKB_FRAGS > 8)
2018 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2019#elif (MAX_SKB_FRAGS > 4)
2020 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2021#else
2022 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2023#endif
2024 } else {
2025 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2026 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2027 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2028 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2029 else
2030 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2031 }
2032 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2033}
2034
9a799d71 2035/**
3a581073 2036 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 2037 * @adapter: board private structure
2038 *
2039 * Configure the Rx unit of the MAC after a reset.
2040 **/
2041static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2042{
2043 u64 rdba;
2044 struct ixgbe_hw *hw = &adapter->hw;
a6616b42 2045 struct ixgbe_ring *rx_ring;
9a799d71
AK		 2046 struct net_device *netdev = adapter->netdev;
2047 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2048 int i, j;
9a799d71 2049 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 2050 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2051 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2052 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 2053 u32 fctrl, hlreg0;
509ee935 2054 u32 reta = 0, mrqc = 0;
cc41ac7c 2055 u32 rdrxctl;
7c6e0a43 2056 int rx_buf_len;
9a799d71
AK		 2057
2058 /* Decide whether to use packet split mode or not */
762f4c57 2059 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2060
2061 /* Set the RX buffer length according to the mode */
2062 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2063 rx_buf_len = IXGBE_RX_HDR_SIZE;
e8e26350
PW		 2064 if (hw->mac.type == ixgbe_mac_82599EB) {
2065 /* PSRTYPE must be initialized in 82599 */
2066 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2067 IXGBE_PSRTYPE_UDPHDR |
2068 IXGBE_PSRTYPE_IPV4HDR |
dfa12f05
YZ		 2069 IXGBE_PSRTYPE_IPV6HDR |
2070 IXGBE_PSRTYPE_L2HDR;
e8e26350
PW		 2071 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2072 }
9a799d71 2073 } else {
0c19d6af 2074 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2075 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2076 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2077 else
7c6e0a43 2078 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 2079 }
2080
2081 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2082 fctrl |= IXGBE_FCTRL_BAM;
021230d4 2083 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
e8e26350 2084 fctrl |= IXGBE_FCTRL_PMCF;
9a799d71
AK		 2085 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2086
2087 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2088 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2089 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2090 else
2091 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
63f39bd1 2092#ifdef IXGBE_FCOE
f34c5c82 2093 if (netdev->features & NETIF_F_FCOE_MTU)
63f39bd1
YZ		 2094 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2095#endif
9a799d71
AK		 2096 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2097
9a799d71
AK		 2098 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2099 /* disable receives while setting up the descriptors */
2100 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2101 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2102
0cefafad
JB		 2103 /*
2104 * Setup the HW Rx Head and Tail Descriptor Pointers and
2105 * the Base and Length of the Rx Descriptor Ring
2106 */
9a799d71 2107 for (i = 0; i < adapter->num_rx_queues; i++) {
a6616b42
YZ		 2108 rx_ring = &adapter->rx_ring[i];
2109 rdba = rx_ring->dma;
2110 j = rx_ring->reg_idx;
284901a9 2111 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
7c6e0a43
JB		 2112 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2113 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2114 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2115 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
a6616b42
YZ		 2116 rx_ring->head = IXGBE_RDH(j);
2117 rx_ring->tail = IXGBE_RDT(j);
2118 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2119
6e455b89
YZ		 2120 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2121 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
1b3ff02e
PWJ		 2122 else
2123 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
cc41ac7c 2124
63f39bd1 2125#ifdef IXGBE_FCOE
f34c5c82 2126 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2127 struct ixgbe_ring_feature *f;
2128 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89
YZ		 2129 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2130 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2131 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2132 rx_ring->rx_buf_len =
2133 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2134 }
63f39bd1
YZ		 2135 }
2136
2137#endif /* IXGBE_FCOE */
a6616b42 2138 ixgbe_configure_srrctl(adapter, rx_ring);
9a799d71
AK		 2139 }
2140
e8e26350
PW		 2141 if (hw->mac.type == ixgbe_mac_82598EB) {
2142 /*
2143 * For VMDq support of different descriptor types or
2144 * buffer sizes through the use of multiple SRRCTL
2145 * registers, RDRXCTL.MVMEN must be set to 1
2146 *
2147 * also, the manual doesn't mention it clearly but DCA hints
2148 * will only use queue 0's tags unless this bit is set. Side
2149 * effects of setting this bit are only that SRRCTL must be
2150 * fully programmed [0..15]
2151 */
2a41ff81
JB		 2152 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2153 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2154 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2f90b865 2155 }
177db6ff 2156
e8e26350 2157 /* Program MRQC for the distribution of queues */
0cefafad 2158 mrqc = ixgbe_setup_mrqc(adapter);
e8e26350 2159
021230d4 2160 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 2161 /* Fill out redirection table */
021230d4
AV		 2162 for (i = 0, j = 0; i < 128; i++, j++) {
2163 if (j == adapter->ring_feature[RING_F_RSS].indices)
2164 j = 0;
2165 /* reta = 4-byte sliding window of
2166 * 0x00..(indices-1)(indices-1)00..etc. */
2167 reta = (reta << 8) | (j * 0x11);
2168 if ((i & 3) == 3)
2169 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 2170 }
2171
2172 /* Fill out hash function seeds */
2173 for (i = 0; i < 10; i++)
7c6e0a43 2174 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71 2175
2a41ff81
JB		 2176 if (hw->mac.type == ixgbe_mac_82598EB)
2177 mrqc |= IXGBE_MRQC_RSSEN;
9a799d71 2178 /* Perform hash on these packet types */
2a41ff81
JB		 2179 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2180 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2181 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2182 | IXGBE_MRQC_RSS_FIELD_IPV6
2183 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2184 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
021230d4 2185 }
2a41ff81 2186 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
9a799d71 2187
021230d4
AV		 2188 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2189
2190 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2191 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2192 /* Disable indicating checksum in descriptor, enables
2193 * RSS hash */
9a799d71 2194 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 2195 }
021230d4
AV		 2196 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2197 /* Enable IPv4 payload checksum for UDP fragments
2198 * if PCSD is not set */
2199 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2200 }
2201
2202 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
e8e26350
PW		 2203
2204 if (hw->mac.type == ixgbe_mac_82599EB) {
2205 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2206 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
f8212f97 2207 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
e8e26350
PW		 2208 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2209 }
f8212f97 2210
0c19d6af 2211 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 2212 /* Enable 82599 HW-RSC */
bb5a9ad2
NS		 2213 for (i = 0; i < adapter->num_rx_queues; i++)
2214 ixgbe_configure_rscctl(adapter, i, rx_buf_len);
2215
f8212f97
AD		 2216 /* Disable RSC for ACK packets */
2217 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2218 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2219 }
9a799d71
AK		 2220}
2221
068c89b0
DS		 2222static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2223{
2224 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2225 struct ixgbe_hw *hw = &adapter->hw;
2226
2227 /* add VID to filter table */
2228 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2229}
2230
2231static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2232{
2233 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2234 struct ixgbe_hw *hw = &adapter->hw;
2235
2236 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2237 ixgbe_irq_disable(adapter);
2238
2239 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2240
2241 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2242 ixgbe_irq_enable(adapter);
2243
2244 /* remove VID from filter table */
2245 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2246}
2247
9a799d71 2248static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 2249 struct vlan_group *grp)
9a799d71
AK		 2250{
2251 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2252 u32 ctrl;
e8e26350 2253 int i, j;
9a799d71 2254
d4f80882
AV		 2255 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2256 ixgbe_irq_disable(adapter);
9a799d71
AK		 2257 adapter->vlgrp = grp;
2258
2f90b865
AD		 2259 /*
2260 * For a DCB driver, always enable VLAN tag stripping so we can
2261 * still receive traffic from a DCB-enabled host even if we're
2262 * not in DCB mode.
2263 */
2264 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
e8e26350
PW		 2265 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2266 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2267 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2268 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2269 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2270 ctrl |= IXGBE_VLNCTRL_VFE;
9a799d71
AK		 2271 /* enable VLAN tag insert/strip */
2272 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
9a799d71
AK		 2273 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2274 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
e8e26350
PW		 2275 for (i = 0; i < adapter->num_rx_queues; i++) {
2276 j = adapter->rx_ring[i].reg_idx;
2277 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2278 ctrl |= IXGBE_RXDCTL_VME;
2279 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2280 }
9a799d71 2281 }
e8e26350 2282 ixgbe_vlan_rx_add_vid(netdev, 0);
9a799d71 2283
d4f80882
AV		 2284 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2285 ixgbe_irq_enable(adapter);
9a799d71
AK		 2286}
2287
9a799d71
AK		 2288static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2289{
2290 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2291
2292 if (adapter->vlgrp) {
2293 u16 vid;
2294 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2295 if (!vlan_group_get_device(adapter->vlgrp, vid))
2296 continue;
2297 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2298 }
2299 }
2300}
2301
2c5645cf
CL		 2302static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2303{
2304 struct dev_mc_list *mc_ptr;
2305 u8 *addr = *mc_addr_ptr;
2306 *vmdq = 0;
2307
2308 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2309 if (mc_ptr->next)
2310 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2311 else
2312 *mc_addr_ptr = NULL;
2313
2314 return addr;
2315}
2316
9a799d71 2317/**
2c5645cf 2318 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 2319 * @netdev: network interface device structure
2320 *
2c5645cf
CL		 2321 * The set_rx_method entry point is called whenever the unicast/multicast
2322 * address list or the network interface flags are updated. This routine is
2323 * responsible for configuring the hardware for proper unicast, multicast and
2324 * promiscuous mode.
9a799d71 2325 **/
2c5645cf 2326static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 2327{
2328 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2329 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 2330 u32 fctrl, vlnctrl;
2c5645cf
CL		 2331 u8 *addr_list = NULL;
2332 int addr_count = 0;
9a799d71
AK		 2333
2334 /* Check for Promiscuous and All Multicast modes */
2335
2336 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 2337 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 2338
2339 if (netdev->flags & IFF_PROMISC) {
2c5645cf 2340 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 2341 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 2342 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 2343 } else {
746b9f02
PM		 2344 if (netdev->flags & IFF_ALLMULTI) {
2345 fctrl |= IXGBE_FCTRL_MPE;
2346 fctrl &= ~IXGBE_FCTRL_UPE;
2347 } else {
2348 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2349 }
3d01625a 2350 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 2351 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 2352 }
2353
2354 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 2355 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 2356
2c5645cf 2357 /* reprogram secondary unicast list */
31278e71 2358 hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
9a799d71 2359
2c5645cf
CL		 2360 /* reprogram multicast list */
2361 addr_count = netdev->mc_count;
2362 if (addr_count)
2363 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 2364 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2365 ixgbe_addr_list_itr);
9a799d71
AK		 2366}
2367
021230d4
AV		 2368static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2369{
2370 int q_idx;
2371 struct ixgbe_q_vector *q_vector;
2372 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2373
2374 /* legacy and MSI only use one vector */
2375 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2376 q_vectors = 1;
2377
2378 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 2379 struct napi_struct *napi;
7a921c93 2380 q_vector = adapter->q_vector[q_idx];
f0848276 2381 napi = &q_vector->napi;
91281fd3
AD		 2382 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2383 if (!q_vector->rxr_count || !q_vector->txr_count) {
2384 if (q_vector->txr_count == 1)
2385 napi->poll = &ixgbe_clean_txonly;
2386 else if (q_vector->rxr_count == 1)
2387 napi->poll = &ixgbe_clean_rxonly;
2388 }
2389 }
f0848276
JB		 2390
2391 napi_enable(napi);
021230d4
AV		 2392 }
2393}
2394
2395static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2396{
2397 int q_idx;
2398 struct ixgbe_q_vector *q_vector;
2399 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2400
2401 /* legacy and MSI only use one vector */
2402 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2403 q_vectors = 1;
2404
2405 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 2406 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 2407 napi_disable(&q_vector->napi);
2408 }
2409}
2410
7a6b6f51 2411#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2412/*
2413 * ixgbe_configure_dcb - Configure DCB hardware
2414 * @adapter: ixgbe adapter struct
2415 *
2416 * This is called by the driver on open to configure the DCB hardware.
2417 * This is also called by the gennetlink interface when reconfiguring
2418 * the DCB state.
2419 */
2420static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2421{
2422 struct ixgbe_hw *hw = &adapter->hw;
2423 u32 txdctl, vlnctrl;
2424 int i, j;
2425
2426 ixgbe_dcb_check_config(&adapter->dcb_cfg);
2427 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2428 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2429
2430 /* reconfigure the hardware */
2431 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2432
2433 for (i = 0; i < adapter->num_tx_queues; i++) {
2434 j = adapter->tx_ring[i].reg_idx;
2435 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2436 /* PThresh workaround for Tx hang with DFP enabled. */
2437 txdctl |= 32;
2438 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2439 }
2440 /* Enable VLAN tag insert/strip */
2441 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
e8e26350
PW		 2442 if (hw->mac.type == ixgbe_mac_82598EB) {
2443 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2444 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2445 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2446 } else if (hw->mac.type == ixgbe_mac_82599EB) {
2447 vlnctrl |= IXGBE_VLNCTRL_VFE;
2448 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2449 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2450 for (i = 0; i < adapter->num_rx_queues; i++) {
2451 j = adapter->rx_ring[i].reg_idx;
2452 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2453 vlnctrl |= IXGBE_RXDCTL_VME;
2454 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2455 }
2456 }
2f90b865
AD		 2457 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2458}
2459
2460#endif
9a799d71
AK		 2461static void ixgbe_configure(struct ixgbe_adapter *adapter)
2462{
2463 struct net_device *netdev = adapter->netdev;
c4cf55e5 2464 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 2465 int i;
2466
2c5645cf 2467 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 2468
2469 ixgbe_restore_vlan(adapter);
7a6b6f51 2470#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 2471 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2472 netif_set_gso_max_size(netdev, 32768);
2473 ixgbe_configure_dcb(adapter);
2474 } else {
2475 netif_set_gso_max_size(netdev, 65536);
2476 }
2477#else
2478 netif_set_gso_max_size(netdev, 65536);
2479#endif
9a799d71 2480
eacd73f7
YZ		 2481#ifdef IXGBE_FCOE
2482 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2483 ixgbe_configure_fcoe(adapter);
2484
2485#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 2486 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2487 for (i = 0; i < adapter->num_tx_queues; i++)
2488 adapter->tx_ring[i].atr_sample_rate =
2489 adapter->atr_sample_rate;
2490 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2491 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2492 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2493 }
2494
9a799d71
AK		 2495 ixgbe_configure_tx(adapter);
2496 ixgbe_configure_rx(adapter);
2497 for (i = 0; i < adapter->num_rx_queues; i++)
2498 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 2499 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 2500}
2501
e8e26350
PW		 2502static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2503{
2504 switch (hw->phy.type) {
2505 case ixgbe_phy_sfp_avago:
2506 case ixgbe_phy_sfp_ftl:
2507 case ixgbe_phy_sfp_intel:
2508 case ixgbe_phy_sfp_unknown:
2509 case ixgbe_phy_tw_tyco:
2510 case ixgbe_phy_tw_unknown:
2511 return true;
2512 default:
2513 return false;
2514 }
2515}
2516
0ecc061d 2517/**
e8e26350
PW		 2518 * ixgbe_sfp_link_config - set up SFP+ link
2519 * @adapter: pointer to private adapter struct
2520 **/
2521static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2522{
2523 struct ixgbe_hw *hw = &adapter->hw;
2524
2525 if (hw->phy.multispeed_fiber) {
2526 /*
2527 * In multispeed fiber setups, the device may not have
2528 * had a physical connection when the driver loaded.
2529 * If that's the case, the initial link configuration
2530 * couldn't get the MAC into 10G or 1G mode, so we'll
2531 * never have a link status change interrupt fire.
2532 * We need to try and force an autonegotiation
2533 * session, then bring up link.
2534 */
2535 hw->mac.ops.setup_sfp(hw);
2536 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2537 schedule_work(&adapter->multispeed_fiber_task);
2538 } else {
2539 /*
2540 * Direct Attach Cu and non-multispeed fiber modules
2541 * still need to be configured properly prior to
2542 * attempting link.
2543 */
2544 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2545 schedule_work(&adapter->sfp_config_module_task);
2546 }
2547}
2548
2549/**
2550 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 2551 * @hw: pointer to private hardware struct
2552 *
2553 * Returns 0 on success, negative on failure
2554 **/
e8e26350 2555static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 2556{
2557 u32 autoneg;
8620a103 2558 bool negotiation, link_up = false;
0ecc061d
PWJ		 2559 u32 ret = IXGBE_ERR_LINK_SETUP;
2560
2561 if (hw->mac.ops.check_link)
2562 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2563
2564 if (ret)
2565 goto link_cfg_out;
2566
2567 if (hw->mac.ops.get_link_capabilities)
8620a103 2568 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
0ecc061d
PWJ		 2569 if (ret)
2570 goto link_cfg_out;
2571
8620a103
MC		 2572 if (hw->mac.ops.setup_link)
2573 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 2574link_cfg_out:
2575 return ret;
2576}
2577
e8e26350
PW		 2578#define IXGBE_MAX_RX_DESC_POLL 10
2579static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2580 int rxr)
2581{
2582 int j = adapter->rx_ring[rxr].reg_idx;
2583 int k;
2584
2585 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2586 if (IXGBE_READ_REG(&adapter->hw,
2587 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2588 break;
2589 else
2590 msleep(1);
2591 }
2592 if (k >= IXGBE_MAX_RX_DESC_POLL) {
2593 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2594 "not set within the polling period\n", rxr);
2595 }
2596 ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2597 (adapter->rx_ring[rxr].count - 1));
2598}
2599
9a799d71
AK		 2600static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2601{
2602 struct net_device *netdev = adapter->netdev;
9a799d71 2603 struct ixgbe_hw *hw = &adapter->hw;
021230d4 2604 int i, j = 0;
e8e26350 2605 int num_rx_rings = adapter->num_rx_queues;
0ecc061d 2606 int err;
9a799d71 2607 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 2608 u32 txdctl, rxdctl, mhadd;
e8e26350 2609 u32 dmatxctl;
021230d4 2610 u32 gpie;
9a799d71 2611
5eba3699
AV		 2612 ixgbe_get_hw_control(adapter);
2613
021230d4
AV		 2614 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2615 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 2616 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2617 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 2618 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 2619 } else {
2620 /* MSI only */
021230d4 2621 gpie = 0;
9a799d71 2622 }
021230d4
AV		 2623 /* XXX: to interrupt immediately for EICS writes, enable this */
2624 /* gpie |= IXGBE_GPIE_EIMEN; */
2625 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 2626 }
2627
021230d4
AV		 2628 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2629 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2630 * specifically only auto mask tx and rx interrupts */
2631 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2632 }
9a799d71 2633
0befdb3e
JB		 2634 /* Enable fan failure interrupt if media type is copper */
2635 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2636 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2637 gpie |= IXGBE_SDP1_GPIEN;
2638 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2639 }
2640
e8e26350
PW		 2641 if (hw->mac.type == ixgbe_mac_82599EB) {
2642 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2643 gpie |= IXGBE_SDP1_GPIEN;
2644 gpie |= IXGBE_SDP2_GPIEN;
2645 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2646 }
2647
63f39bd1
YZ		 2648#ifdef IXGBE_FCOE
2649 /* adjust max frame to be able to do baby jumbo for FCoE */
f34c5c82 2650 if ((netdev->features & NETIF_F_FCOE_MTU) &&
63f39bd1
YZ		 2651 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2652 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2653
2654#endif /* IXGBE_FCOE */
021230d4 2655 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2656 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2657 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2658 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2659
2660 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2661 }
2662
2663 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2664 j = adapter->tx_ring[i].reg_idx;
2665 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2666 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2667 txdctl |= (8 << 16);
e8e26350
PW		 2668 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2669 }
2670
2671 if (hw->mac.type == ixgbe_mac_82599EB) {
2672 /* DMATXCTL.EN must be set after all Tx queue config is done */
2673 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2674 dmatxctl |= IXGBE_DMATXCTL_TE;
2675 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2676 }
2677 for (i = 0; i < adapter->num_tx_queues; i++) {
2678 j = adapter->tx_ring[i].reg_idx;
2679 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
9a799d71 2680 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2681 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2682 }
2683
e8e26350 2684 for (i = 0; i < num_rx_rings; i++) {
021230d4
AV		 2685 j = adapter->rx_ring[i].reg_idx;
2686 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2687 /* enable PTHRESH=32 descriptors (half the internal cache)
2688 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2689 * this also removes a pesky rx_no_buffer_count increment */
2690 rxdctl |= 0x0020;
9a799d71 2691 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2692 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
e8e26350
PW		 2693 if (hw->mac.type == ixgbe_mac_82599EB)
2694 ixgbe_rx_desc_queue_enable(adapter, i);
9a799d71
AK		 2695 }
2696 /* enable all receives */
2697 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
e8e26350
PW		 2698 if (hw->mac.type == ixgbe_mac_82598EB)
2699 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2700 else
2701 rxdctl |= IXGBE_RXCTRL_RXEN;
2702 hw->mac.ops.enable_rx_dma(hw, rxdctl);
9a799d71
AK		 2703
2704 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2705 ixgbe_configure_msix(adapter);
2706 else
2707 ixgbe_configure_msi_and_legacy(adapter);
2708
2709 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2710 ixgbe_napi_enable_all(adapter);
2711
2712 /* clear any pending interrupts, may auto mask */
2713 IXGBE_READ_REG(hw, IXGBE_EICR);
2714
9a799d71
AK		 2715 ixgbe_irq_enable(adapter);
2716
bf069c97
DS		 2717 /*
2718 * If this adapter has a fan, check to see if we had a failure
2719 * before we enabled the interrupt.
2720 */
2721 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2722 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2723 if (esdp & IXGBE_ESDP_SDP1)
2724 DPRINTK(DRV, CRIT,
2725 "Fan has stopped, replace the adapter\n");
2726 }
2727
e8e26350
PW		 2728 /*
2729 * For hot-pluggable SFP+ devices, a new SFP+ module may have
19343de2
DS		 2730 * arrived before interrupts were enabled but after probe. Such
2731 * devices wouldn't have their type identified yet. We need to
2732 * kick off the SFP+ module setup first, then try to bring up link.
e8e26350
PW		 2733 * If we're not hot-pluggable SFP+, we just need to configure link
2734 * and bring it up.
2735 */
19343de2
DS		 2736 if (hw->phy.type == ixgbe_phy_unknown) {
2737 err = hw->phy.ops.identify(hw);
2738 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5da43c1a
DS		 2739 /*
2740 * Take the device down and schedule the sfp tasklet
2741 * which will unregister_netdev and log it.
2742 */
19343de2 2743 ixgbe_down(adapter);
5da43c1a 2744 schedule_work(&adapter->sfp_config_module_task);
19343de2
DS		 2745 return err;
2746 }
e8e26350
PW		 2747 }
2748
2749 if (ixgbe_is_sfp(hw)) {
2750 ixgbe_sfp_link_config(adapter);
2751 } else {
2752 err = ixgbe_non_sfp_link_config(hw);
2753 if (err)
2754 DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2755 }
0ecc061d 2756
c4cf55e5
PWJ		 2757 for (i = 0; i < adapter->num_tx_queues; i++)
2758 set_bit(__IXGBE_FDIR_INIT_DONE,
2759 &(adapter->tx_ring[i].reinit_state));
2760
1da100bb
PWJ		 2761 /* enable transmits */
2762 netif_tx_start_all_queues(netdev);
2763
9a799d71
AK		 2764 /* bring the link up in the watchdog, this could race with our first
2765 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2766 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2767 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2768 mod_timer(&adapter->watchdog_timer, jiffies);
2769 return 0;
2770}
2771
d4f80882
AV		 2772void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2773{
2774 WARN_ON(in_interrupt());
2775 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2776 msleep(1);
2777 ixgbe_down(adapter);
2778 ixgbe_up(adapter);
2779 clear_bit(__IXGBE_RESETTING, &adapter->state);
2780}
2781
9a799d71
AK		 2782int ixgbe_up(struct ixgbe_adapter *adapter)
2783{
2784 /* hardware has been reset, we need to reload some things */
2785 ixgbe_configure(adapter);
2786
2787 return ixgbe_up_complete(adapter);
2788}
2789
2790void ixgbe_reset(struct ixgbe_adapter *adapter)
2791{
c44ade9e 2792 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 2793 int err;
2794
2795 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 2796 switch (err) {
2797 case 0:
2798 case IXGBE_ERR_SFP_NOT_PRESENT:
2799 break;
2800 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2801 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2802 break;
794caeb2
PWJ		 2803 case IXGBE_ERR_EEPROM_VERSION:
2804 /* We are running on a pre-production device, log a warning */
2805 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2806 "adapter/LOM. Please be aware there may be issues "
2807 "associated with your hardware. If you are "
2808 "experiencing problems please contact your Intel or "
2809 "hardware representative who provided you with this "
2810 "hardware.\n");
2811 break;
da4dd0f7
PWJ		 2812 default:
2813 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2814 }
9a799d71
AK		 2815
2816 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2817 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2818}
2819
9a799d71
AK		 2820/**
2821 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2822 * @adapter: board private structure
2823 * @rx_ring: ring to free buffers from
2824 **/
2825static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2826 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2827{
2828 struct pci_dev *pdev = adapter->pdev;
2829 unsigned long size;
2830 unsigned int i;
2831
2832 /* Free all the Rx ring sk_buffs */
2833
2834 for (i = 0; i < rx_ring->count; i++) {
2835 struct ixgbe_rx_buffer *rx_buffer_info;
2836
2837 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2838 if (rx_buffer_info->dma) {
2839 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2840 rx_ring->rx_buf_len,
2841 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2842 rx_buffer_info->dma = 0;
2843 }
2844 if (rx_buffer_info->skb) {
f8212f97 2845 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 2846 rx_buffer_info->skb = NULL;
f8212f97
AD		 2847 do {
2848 struct sk_buff *this = skb;
2849 skb = skb->prev;
2850 dev_kfree_skb(this);
2851 } while (skb);
9a799d71
AK		 2852 }
2853 if (!rx_buffer_info->page)
2854 continue;
4f57ca6e
JB		 2855 if (rx_buffer_info->page_dma) {
2856 pci_unmap_page(pdev, rx_buffer_info->page_dma,
2857 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2858 rx_buffer_info->page_dma = 0;
2859 }
9a799d71
AK		 2860 put_page(rx_buffer_info->page);
2861 rx_buffer_info->page = NULL;
762f4c57 2862 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2863 }
2864
2865 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2866 memset(rx_ring->rx_buffer_info, 0, size);
2867
2868 /* Zero out the descriptor ring */
2869 memset(rx_ring->desc, 0, rx_ring->size);
2870
2871 rx_ring->next_to_clean = 0;
2872 rx_ring->next_to_use = 0;
2873
9891ca7c
JB		 2874 if (rx_ring->head)
2875 writel(0, adapter->hw.hw_addr + rx_ring->head);
2876 if (rx_ring->tail)
2877 writel(0, adapter->hw.hw_addr + rx_ring->tail);
9a799d71
AK		 2878}
2879
2880/**
2881 * ixgbe_clean_tx_ring - Free Tx Buffers
2882 * @adapter: board private structure
2883 * @tx_ring: ring to be cleaned
2884 **/
2885static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2886 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2887{
2888 struct ixgbe_tx_buffer *tx_buffer_info;
2889 unsigned long size;
2890 unsigned int i;
2891
2892 /* Free all the Tx ring sk_buffs */
2893
2894 for (i = 0; i < tx_ring->count; i++) {
2895 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2896 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2897 }
2898
2899 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2900 memset(tx_ring->tx_buffer_info, 0, size);
2901
2902 /* Zero out the descriptor ring */
2903 memset(tx_ring->desc, 0, tx_ring->size);
2904
2905 tx_ring->next_to_use = 0;
2906 tx_ring->next_to_clean = 0;
2907
9891ca7c
JB		 2908 if (tx_ring->head)
2909 writel(0, adapter->hw.hw_addr + tx_ring->head);
2910 if (tx_ring->tail)
2911 writel(0, adapter->hw.hw_addr + tx_ring->tail);
9a799d71
AK		 2912}
2913
2914/**
021230d4 2915 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2916 * @adapter: board private structure
2917 **/
021230d4 2918static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2919{
2920 int i;
2921
021230d4
AV		 2922 for (i = 0; i < adapter->num_rx_queues; i++)
2923 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2924}
2925
2926/**
021230d4 2927 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2928 * @adapter: board private structure
2929 **/
021230d4 2930static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2931{
2932 int i;
2933
021230d4
AV		 2934 for (i = 0; i < adapter->num_tx_queues; i++)
2935 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2936}
2937
2938void ixgbe_down(struct ixgbe_adapter *adapter)
2939{
2940 struct net_device *netdev = adapter->netdev;
7f821875 2941 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2942 u32 rxctrl;
7f821875
JB		 2943 u32 txdctl;
2944 int i, j;
9a799d71
AK		 2945
2946 /* signal that we are down to the interrupt handler */
2947 set_bit(__IXGBE_DOWN, &adapter->state);
2948
2949 /* disable receives */
7f821875
JB		 2950 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2951 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2952
2953 netif_tx_disable(netdev);
2954
7f821875 2955 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2956 msleep(10);
2957
7f821875
JB		 2958 netif_tx_stop_all_queues(netdev);
2959
9a799d71
AK		 2960 ixgbe_irq_disable(adapter);
2961
021230d4 2962 ixgbe_napi_disable_all(adapter);
7f821875 2963
0a1f87cb
DS		 2964 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2965 del_timer_sync(&adapter->sfp_timer);
9a799d71 2966 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2967 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2968
c4cf55e5
PWJ		 2969 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2970 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2971 cancel_work_sync(&adapter->fdir_reinit_task);
2972
7f821875
JB		 2973 /* disable transmits in the hardware now that interrupts are off */
2974 for (i = 0; i < adapter->num_tx_queues; i++) {
2975 j = adapter->tx_ring[i].reg_idx;
2976 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2977 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2978 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2979 }
88512539
PW		 2980 /* Disable the Tx DMA engine on 82599 */
2981 if (hw->mac.type == ixgbe_mac_82599EB)
2982 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2983 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2984 ~IXGBE_DMATXCTL_TE));
7f821875 2985
9a799d71 2986 netif_carrier_off(netdev);
9a799d71 2987
6f4a0e45
PL		 2988 if (!pci_channel_offline(adapter->pdev))
2989 ixgbe_reset(adapter);
9a799d71
AK		 2990 ixgbe_clean_all_tx_rings(adapter);
2991 ixgbe_clean_all_rx_rings(adapter);
2992
5dd2d332 2993#ifdef CONFIG_IXGBE_DCA
96b0e0f6 2994 /* since we reset the hardware DCA settings were cleared */
e35ec126 2995 ixgbe_setup_dca(adapter);
96b0e0f6 2996#endif
9a799d71
AK		 2997}
2998
9a799d71 2999/**
021230d4
AV		 3000 * ixgbe_poll - NAPI Rx polling callback
3001 * @napi: structure for representing this polling device
3002 * @budget: how many packets driver is allowed to clean
3003 *
3004 * This function is used for legacy and MSI, NAPI mode
9a799d71 3005 **/
021230d4 3006static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3007{
9a1a69ad
JB		 3008 struct ixgbe_q_vector *q_vector =
3009 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3010 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 3011 int tx_clean_complete, work_done = 0;
9a799d71 3012
5dd2d332 3013#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 3014 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3015 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
3016 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
3017 }
3018#endif
3019
fe49f04a 3020 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
78b6f4ce 3021 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
9a799d71 3022
9a1a69ad 3023 if (!tx_clean_complete)
d2c7ddd6
DM		 3024 work_done = budget;
3025
53e52c72
DM		 3026 /* If budget not fully consumed, exit the polling mode */
3027 if (work_done < budget) {
288379f0 3028 napi_complete(napi);
f7554a2b 3029 if (adapter->rx_itr_setting & 1)
f494e8fa 3030 ixgbe_set_itr(adapter);
d4f80882 3031 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 3032 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 3033 }
9a799d71
AK		 3034 return work_done;
3035}
3036
3037/**
3038 * ixgbe_tx_timeout - Respond to a Tx Hang
3039 * @netdev: network interface device structure
3040 **/
3041static void ixgbe_tx_timeout(struct net_device *netdev)
3042{
3043 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3044
3045 /* Do the reset outside of interrupt context */
3046 schedule_work(&adapter->reset_task);
3047}
3048
3049static void ixgbe_reset_task(struct work_struct *work)
3050{
3051 struct ixgbe_adapter *adapter;
3052 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3053
2f90b865
AD		 3054 /* If we're already down or resetting, just bail */
3055 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3056 test_bit(__IXGBE_RESETTING, &adapter->state))
3057 return;
3058
9a799d71
AK		 3059 adapter->tx_timeout_count++;
3060
d4f80882 3061 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3062}
3063
bc97114d
PWJ		 3064#ifdef CONFIG_IXGBE_DCB
3065static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
b9804972 3066{
bc97114d 3067 bool ret = false;
0cefafad 3068 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
b9804972 3069
0cefafad
JB		 3070 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3071 return ret;
3072
3073 f->mask = 0x7 << 3;
3074 adapter->num_rx_queues = f->indices;
3075 adapter->num_tx_queues = f->indices;
3076 ret = true;
2f90b865 3077
bc97114d
PWJ		 3078 return ret;
3079}
3080#endif
3081
4df10466
JB		 3082/**
3083 * ixgbe_set_rss_queues: Allocate queues for RSS
3084 * @adapter: board private structure to initialize
3085 *
3086 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3087 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3088 *
3089 **/
bc97114d
PWJ		 3090static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3091{
3092 bool ret = false;
0cefafad 3093 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 3094
3095 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 3096 f->mask = 0xF;
3097 adapter->num_rx_queues = f->indices;
3098 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 3099 ret = true;
3100 } else {
bc97114d 3101 ret = false;
b9804972
JB		 3102 }
3103
bc97114d
PWJ		 3104 return ret;
3105}
3106
c4cf55e5
PWJ		 3107/**
3108 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3109 * @adapter: board private structure to initialize
3110 *
3111 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3112 * to the original CPU that initiated the Tx session. This runs in addition
3113 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3114 * Rx load across CPUs using RSS.
3115 *
3116 **/
3117static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3118{
3119 bool ret = false;
3120 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3121
3122 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3123 f_fdir->mask = 0;
3124
3125 /* Flow Director must have RSS enabled */
3126 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3127 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3128 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3129 adapter->num_tx_queues = f_fdir->indices;
3130 adapter->num_rx_queues = f_fdir->indices;
3131 ret = true;
3132 } else {
3133 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3134 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3135 }
3136 return ret;
3137}
3138
0331a832
YZ		 3139#ifdef IXGBE_FCOE
3140/**
3141 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3142 * @adapter: board private structure to initialize
3143 *
3144 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3145 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3146 * rx queues out of the max number of rx queues, instead, it is used as the
3147 * index of the first rx queue used by FCoE.
3148 *
3149 **/
3150static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3151{
3152 bool ret = false;
3153 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3154
3155 f->indices = min((int)num_online_cpus(), f->indices);
3156 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
8de8b2e6
YZ		 3157 adapter->num_rx_queues = 1;
3158 adapter->num_tx_queues = 1;
0331a832
YZ		 3159#ifdef CONFIG_IXGBE_DCB
3160 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6 3161 DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
0331a832
YZ		 3162 ixgbe_set_dcb_queues(adapter);
3163 }
3164#endif
3165 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8de8b2e6 3166 DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
8faa2a78
YZ		 3167 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3168 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3169 ixgbe_set_fdir_queues(adapter);
3170 else
3171 ixgbe_set_rss_queues(adapter);
0331a832
YZ		 3172 }
3173 /* adding FCoE rx rings to the end */
3174 f->mask = adapter->num_rx_queues;
3175 adapter->num_rx_queues += f->indices;
8de8b2e6 3176 adapter->num_tx_queues += f->indices;
0331a832
YZ		 3177
3178 ret = true;
3179 }
3180
3181 return ret;
3182}
3183
3184#endif /* IXGBE_FCOE */
4df10466
JB		 3185/*
3186 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3187 * @adapter: board private structure to initialize
3188 *
3189 * This is the top level queue allocation routine. The order here is very
3190 * important, starting with the "most" number of features turned on at once,
3191 * and ending with the smallest set of features. This way large combinations
3192 * can be allocated if they're turned on, and smaller combinations are the
3193 * fallthrough conditions.
3194 *
3195 **/
bc97114d
PWJ		 3196static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3197{
0331a832
YZ		 3198#ifdef IXGBE_FCOE
3199 if (ixgbe_set_fcoe_queues(adapter))
3200 goto done;
3201
3202#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3203#ifdef CONFIG_IXGBE_DCB
3204 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 3205 goto done;
bc97114d
PWJ		 3206
3207#endif
c4cf55e5
PWJ		 3208 if (ixgbe_set_fdir_queues(adapter))
3209 goto done;
3210
bc97114d 3211 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 3212 goto done;
3213
3214 /* fallback to base case */
3215 adapter->num_rx_queues = 1;
3216 adapter->num_tx_queues = 1;
3217
3218done:
3219 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3220 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
b9804972
JB		 3221}
3222
021230d4 3223static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 3224 int vectors)
021230d4
AV		 3225{
3226 int err, vector_threshold;
3227
3228 /* We'll want at least 3 (vector_threshold):
3229 * 1) TxQ[0] Cleanup
3230 * 2) RxQ[0] Cleanup
3231 * 3) Other (Link Status Change, etc.)
3232 * 4) TCP Timer (optional)
3233 */
3234 vector_threshold = MIN_MSIX_COUNT;
3235
3236 /* The more we get, the more we will assign to Tx/Rx Cleanup
3237 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3238 * Right now, we simply care about how many we'll get; we'll
3239 * set them up later while requesting irq's.
3240 */
3241 while (vectors >= vector_threshold) {
3242 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 3243 vectors);
021230d4
AV		 3244 if (!err) /* Success in acquiring all requested vectors. */
3245 break;
3246 else if (err < 0)
3247 vectors = 0; /* Nasty failure, quit now */
3248 else /* err == number of vectors we should try again with */
3249 vectors = err;
3250 }
3251
3252 if (vectors < vector_threshold) {
3253 /* Can't allocate enough MSI-X interrupts? Oh well.
3254 * This just means we'll go with either a single MSI
3255 * vector or fall back to legacy interrupts.
3256 */
3257 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3258 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3259 kfree(adapter->msix_entries);
3260 adapter->msix_entries = NULL;
021230d4
AV		 3261 } else {
3262 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 3263 /*
3264 * Adjust for only the vectors we'll use, which is minimum
3265 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3266 * vectors we were allocated.
3267 */
3268 adapter->num_msix_vectors = min(vectors,
3269 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 3270 }
3271}
3272
021230d4 3273/**
bc97114d 3274 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 3275 * @adapter: board private structure to initialize
3276 *
bc97114d
PWJ		 3277 * Cache the descriptor ring offsets for RSS to the assigned rings.
3278 *
021230d4 3279 **/
bc97114d 3280static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 3281{
bc97114d
PWJ		 3282 int i;
3283 bool ret = false;
3284
3285 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3286 for (i = 0; i < adapter->num_rx_queues; i++)
3287 adapter->rx_ring[i].reg_idx = i;
3288 for (i = 0; i < adapter->num_tx_queues; i++)
3289 adapter->tx_ring[i].reg_idx = i;
3290 ret = true;
3291 } else {
3292 ret = false;
3293 }
3294
3295 return ret;
3296}
3297
3298#ifdef CONFIG_IXGBE_DCB
3299/**
3300 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3301 * @adapter: board private structure to initialize
3302 *
3303 * Cache the descriptor ring offsets for DCB to the assigned rings.
3304 *
3305 **/
3306static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3307{
3308 int i;
3309 bool ret = false;
3310 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3311
3312 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3313 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2f90b865
AD		 3314 /* the number of queues is assumed to be symmetric */
3315 for (i = 0; i < dcb_i; i++) {
3316 adapter->rx_ring[i].reg_idx = i << 3;
3317 adapter->tx_ring[i].reg_idx = i << 2;
3318 }
bc97114d 3319 ret = true;
e8e26350 3320 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
f92ef202
PW		 3321 if (dcb_i == 8) {
3322 /*
3323 * Tx TC0 starts at: descriptor queue 0
3324 * Tx TC1 starts at: descriptor queue 32
3325 * Tx TC2 starts at: descriptor queue 64
3326 * Tx TC3 starts at: descriptor queue 80
3327 * Tx TC4 starts at: descriptor queue 96
3328 * Tx TC5 starts at: descriptor queue 104
3329 * Tx TC6 starts at: descriptor queue 112
3330 * Tx TC7 starts at: descriptor queue 120
3331 *
3332 * Rx TC0-TC7 are offset by 16 queues each
3333 */
3334 for (i = 0; i < 3; i++) {
3335 adapter->tx_ring[i].reg_idx = i << 5;
3336 adapter->rx_ring[i].reg_idx = i << 4;
3337 }
3338 for ( ; i < 5; i++) {
3339 adapter->tx_ring[i].reg_idx =
3340 ((i + 2) << 4);
3341 adapter->rx_ring[i].reg_idx = i << 4;
3342 }
3343 for ( ; i < dcb_i; i++) {
3344 adapter->tx_ring[i].reg_idx =
3345 ((i + 8) << 3);
3346 adapter->rx_ring[i].reg_idx = i << 4;
3347 }
3348
3349 ret = true;
3350 } else if (dcb_i == 4) {
3351 /*
3352 * Tx TC0 starts at: descriptor queue 0
3353 * Tx TC1 starts at: descriptor queue 64
3354 * Tx TC2 starts at: descriptor queue 96
3355 * Tx TC3 starts at: descriptor queue 112
3356 *
3357 * Rx TC0-TC3 are offset by 32 queues each
3358 */
3359 adapter->tx_ring[0].reg_idx = 0;
3360 adapter->tx_ring[1].reg_idx = 64;
3361 adapter->tx_ring[2].reg_idx = 96;
3362 adapter->tx_ring[3].reg_idx = 112;
3363 for (i = 0 ; i < dcb_i; i++)
3364 adapter->rx_ring[i].reg_idx = i << 5;
3365
3366 ret = true;
3367 } else {
3368 ret = false;
e8e26350 3369 }
bc97114d
PWJ		 3370 } else {
3371 ret = false;
021230d4 3372 }
bc97114d
PWJ		 3373 } else {
3374 ret = false;
021230d4 3375 }
bc97114d
PWJ		 3376
3377 return ret;
3378}
3379#endif
3380
c4cf55e5
PWJ		 3381/**
3382 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3383 * @adapter: board private structure to initialize
3384 *
3385 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3386 *
3387 **/
3388static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3389{
3390 int i;
3391 bool ret = false;
3392
3393 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3394 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3395 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3396 for (i = 0; i < adapter->num_rx_queues; i++)
3397 adapter->rx_ring[i].reg_idx = i;
3398 for (i = 0; i < adapter->num_tx_queues; i++)
3399 adapter->tx_ring[i].reg_idx = i;
3400 ret = true;
3401 }
3402
3403 return ret;
3404}
3405
0331a832
YZ		 3406#ifdef IXGBE_FCOE
3407/**
3408 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3409 * @adapter: board private structure to initialize
3410 *
3411 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3412 *
3413 */
3414static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3415{
8de8b2e6 3416 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
0331a832
YZ		 3417 bool ret = false;
3418 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3419
3420 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3421#ifdef CONFIG_IXGBE_DCB
3422 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
8de8b2e6
YZ		 3423 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3424
0331a832 3425 ixgbe_cache_ring_dcb(adapter);
8de8b2e6
YZ		 3426 /* find out queues in TC for FCoE */
3427 fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3428 fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3429 /*
3430 * In 82599, the number of Tx queues for each traffic
3431 * class for both 8-TC and 4-TC modes are:
3432 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3433 * 8 TCs: 32 32 16 16 8 8 8 8
3434 * 4 TCs: 64 64 32 32
3435 * We have max 8 queues for FCoE, where 8 the is
3436 * FCoE redirection table size. If TC for FCoE is
3437 * less than or equal to TC3, we have enough queues
3438 * to add max of 8 queues for FCoE, so we start FCoE
3439 * tx descriptor from the next one, i.e., reg_idx + 1.
3440 * If TC for FCoE is above TC3, implying 8 TC mode,
3441 * and we need 8 for FCoE, we have to take all queues
3442 * in that traffic class for FCoE.
3443 */
3444 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3445 fcoe_tx_i--;
0331a832
YZ		 3446 }
3447#endif /* CONFIG_IXGBE_DCB */
3448 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
8faa2a78
YZ		 3449 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3450 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3451 ixgbe_cache_ring_fdir(adapter);
3452 else
3453 ixgbe_cache_ring_rss(adapter);
3454
8de8b2e6
YZ		 3455 fcoe_rx_i = f->mask;
3456 fcoe_tx_i = f->mask;
3457 }
3458 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3459 adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3460 adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
0331a832 3461 }
0331a832
YZ		 3462 ret = true;
3463 }
3464 return ret;
3465}
3466
3467#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3468/**
3469 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3470 * @adapter: board private structure to initialize
3471 *
3472 * Once we know the feature-set enabled for the device, we'll cache
3473 * the register offset the descriptor ring is assigned to.
3474 *
3475 * Note, the order the various feature calls is important. It must start with
3476 * the "most" features enabled at the same time, then trickle down to the
3477 * least amount of features turned on at once.
3478 **/
3479static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3480{
3481 /* start with default case */
3482 adapter->rx_ring[0].reg_idx = 0;
3483 adapter->tx_ring[0].reg_idx = 0;
3484
0331a832
YZ		 3485#ifdef IXGBE_FCOE
3486 if (ixgbe_cache_ring_fcoe(adapter))
3487 return;
3488
3489#endif /* IXGBE_FCOE */
bc97114d
PWJ		 3490#ifdef CONFIG_IXGBE_DCB
3491 if (ixgbe_cache_ring_dcb(adapter))
3492 return;
3493
3494#endif
c4cf55e5
PWJ		 3495 if (ixgbe_cache_ring_fdir(adapter))
3496 return;
3497
bc97114d
PWJ		 3498 if (ixgbe_cache_ring_rss(adapter))
3499 return;
021230d4
AV		 3500}
3501
9a799d71
AK		 3502/**
3503 * ixgbe_alloc_queues - Allocate memory for all rings
3504 * @adapter: board private structure to initialize
3505 *
3506 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 3507 * number of queues at compile-time. The polling_netdev array is
3508 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 3509 **/
2f90b865 3510static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 3511{
3512 int i;
3513
3514 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 3515 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 3516 if (!adapter->tx_ring)
021230d4 3517 goto err_tx_ring_allocation;
9a799d71
AK		 3518
3519 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 3520 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 3521 if (!adapter->rx_ring)
3522 goto err_rx_ring_allocation;
9a799d71 3523
021230d4 3524 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 3525 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 3526 adapter->tx_ring[i].queue_index = i;
3527 }
b9804972 3528
9a799d71 3529 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 3530 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 3531 adapter->rx_ring[i].queue_index = i;
3532 }
3533
3534 ixgbe_cache_ring_register(adapter);
3535
3536 return 0;
3537
3538err_rx_ring_allocation:
3539 kfree(adapter->tx_ring);
3540err_tx_ring_allocation:
3541 return -ENOMEM;
3542}
3543
3544/**
3545 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3546 * @adapter: board private structure to initialize
3547 *
3548 * Attempt to configure the interrupts using the best available
3549 * capabilities of the hardware and the kernel.
3550 **/
feea6a57 3551static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 3552{
8be0e467 3553 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 3554 int err = 0;
3555 int vector, v_budget;
3556
3557 /*
3558 * It's easy to be greedy for MSI-X vectors, but it really
3559 * doesn't do us much good if we have a lot more vectors
3560 * than CPU's. So let's be conservative and only ask for
3561 * (roughly) twice the number of vectors as there are CPU's.
3562 */
3563 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 3564 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 3565
3566 /*
3567 * At the same time, hardware can only support a maximum of
8be0e467
PW		 3568 * hw.mac->max_msix_vectors vectors. With features
3569 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3570 * descriptor queues supported by our device. Thus, we cap it off in
3571 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 3572 */
8be0e467 3573 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 3574
3575 /* A failure in MSI-X entry allocation isn't fatal, but it does
3576 * mean we disable MSI-X capabilities of the adapter. */
3577 adapter->msix_entries = kcalloc(v_budget,
b4617240 3578 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 3579 if (adapter->msix_entries) {
3580 for (vector = 0; vector < v_budget; vector++)
3581 adapter->msix_entries[vector].entry = vector;
021230d4 3582
7a921c93 3583 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 3584
7a921c93
AD		 3585 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3586 goto out;
3587 }
021230d4 3588
7a921c93
AD		 3589 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3590 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
c4cf55e5
PWJ		 3591 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3592 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3593 adapter->atr_sample_rate = 0;
7a921c93 3594 ixgbe_set_num_queues(adapter);
021230d4 3595
021230d4
AV		 3596 err = pci_enable_msi(adapter->pdev);
3597 if (!err) {
3598 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3599 } else {
3600 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 3601 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 3602 /* reset err */
3603 err = 0;
3604 }
3605
3606out:
021230d4
AV		 3607 return err;
3608}
3609
7a921c93
AD		 3610/**
3611 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3612 * @adapter: board private structure to initialize
3613 *
3614 * We allocate one q_vector per queue interrupt. If allocation fails we
3615 * return -ENOMEM.
3616 **/
3617static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3618{
3619 int q_idx, num_q_vectors;
3620 struct ixgbe_q_vector *q_vector;
3621 int napi_vectors;
3622 int (*poll)(struct napi_struct *, int);
3623
3624 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3625 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3626 napi_vectors = adapter->num_rx_queues;
91281fd3 3627 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 3628 } else {
3629 num_q_vectors = 1;
3630 napi_vectors = 1;
3631 poll = &ixgbe_poll;
3632 }
3633
3634 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3635 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3636 if (!q_vector)
3637 goto err_out;
3638 q_vector->adapter = adapter;
f7554a2b
NS		 3639 if (q_vector->txr_count && !q_vector->rxr_count)
3640 q_vector->eitr = adapter->tx_eitr_param;
3641 else
3642 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 3643 q_vector->v_idx = q_idx;
91281fd3 3644 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 3645 adapter->q_vector[q_idx] = q_vector;
3646 }
3647
3648 return 0;
3649
3650err_out:
3651 while (q_idx) {
3652 q_idx--;
3653 q_vector = adapter->q_vector[q_idx];
3654 netif_napi_del(&q_vector->napi);
3655 kfree(q_vector);
3656 adapter->q_vector[q_idx] = NULL;
3657 }
3658 return -ENOMEM;
3659}
3660
3661/**
3662 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3663 * @adapter: board private structure to initialize
3664 *
3665 * This function frees the memory allocated to the q_vectors. In addition if
3666 * NAPI is enabled it will delete any references to the NAPI struct prior
3667 * to freeing the q_vector.
3668 **/
3669static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3670{
3671 int q_idx, num_q_vectors;
7a921c93 3672
91281fd3 3673 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 3674 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 3675 else
7a921c93 3676 num_q_vectors = 1;
7a921c93
AD		 3677
3678 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3679 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 3680 adapter->q_vector[q_idx] = NULL;
91281fd3 3681 netif_napi_del(&q_vector->napi);
7a921c93
AD		 3682 kfree(q_vector);
3683 }
3684}
3685
7b25cdba 3686static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 3687{
3688 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3689 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3690 pci_disable_msix(adapter->pdev);
3691 kfree(adapter->msix_entries);
3692 adapter->msix_entries = NULL;
3693 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3694 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3695 pci_disable_msi(adapter->pdev);
3696 }
3697 return;
3698}
3699
3700/**
3701 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3702 * @adapter: board private structure to initialize
3703 *
3704 * We determine which interrupt scheme to use based on...
3705 * - Kernel support (MSI, MSI-X)
3706 * - which can be user-defined (via MODULE_PARAM)
3707 * - Hardware queue count (num_*_queues)
3708 * - defined by miscellaneous hardware support/features (RSS, etc.)
3709 **/
2f90b865 3710int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 3711{
3712 int err;
3713
3714 /* Number of supported queues */
3715 ixgbe_set_num_queues(adapter);
3716
021230d4
AV		 3717 err = ixgbe_set_interrupt_capability(adapter);
3718 if (err) {
3719 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3720 goto err_set_interrupt;
9a799d71
AK		 3721 }
3722
7a921c93
AD		 3723 err = ixgbe_alloc_q_vectors(adapter);
3724 if (err) {
3725 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3726 "vectors\n");
3727 goto err_alloc_q_vectors;
3728 }
3729
3730 err = ixgbe_alloc_queues(adapter);
3731 if (err) {
3732 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3733 goto err_alloc_queues;
3734 }
3735
021230d4 3736 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 3737 "Tx Queue count = %u\n",
3738 (adapter->num_rx_queues > 1) ? "Enabled" :
3739 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 3740
3741 set_bit(__IXGBE_DOWN, &adapter->state);
3742
9a799d71 3743 return 0;
021230d4 3744
7a921c93
AD		 3745err_alloc_queues:
3746 ixgbe_free_q_vectors(adapter);
3747err_alloc_q_vectors:
3748 ixgbe_reset_interrupt_capability(adapter);
021230d4 3749err_set_interrupt:
7a921c93
AD		 3750 return err;
3751}
3752
3753/**
3754 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3755 * @adapter: board private structure to clear interrupt scheme on
3756 *
3757 * We go through and clear interrupt specific resources and reset the structure
3758 * to pre-load conditions
3759 **/
3760void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3761{
021230d4
AV		 3762 kfree(adapter->tx_ring);
3763 kfree(adapter->rx_ring);
7a921c93
AD		 3764 adapter->tx_ring = NULL;
3765 adapter->rx_ring = NULL;
3766
3767 ixgbe_free_q_vectors(adapter);
3768 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 3769}
3770
c4900be0
DS		 3771/**
3772 * ixgbe_sfp_timer - worker thread to find a missing module
3773 * @data: pointer to our adapter struct
3774 **/
3775static void ixgbe_sfp_timer(unsigned long data)
3776{
3777 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3778
4df10466
JB		 3779 /*
3780 * Do the sfp_timer outside of interrupt context due to the
c4900be0
DS		 3781 * delays that sfp+ detection requires
3782 */
3783 schedule_work(&adapter->sfp_task);
3784}
3785
3786/**
3787 * ixgbe_sfp_task - worker thread to find a missing module
3788 * @work: pointer to work_struct containing our data
3789 **/
3790static void ixgbe_sfp_task(struct work_struct *work)
3791{
3792 struct ixgbe_adapter *adapter = container_of(work,
3793 struct ixgbe_adapter,
3794 sfp_task);
3795 struct ixgbe_hw *hw = &adapter->hw;
3796
3797 if ((hw->phy.type == ixgbe_phy_nl) &&
3798 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3799 s32 ret = hw->phy.ops.identify_sfp(hw);
63d6e1d8 3800 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
c4900be0
DS		 3801 goto reschedule;
3802 ret = hw->phy.ops.reset(hw);
3803 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 3804 dev_err(&adapter->pdev->dev, "failed to initialize "
3805 "because an unsupported SFP+ module type "
3806 "was detected.\n"
3807 "Reload the driver after installing a "
3808 "supported module.\n");
c4900be0
DS		 3809 unregister_netdev(adapter->netdev);
3810 } else {
3811 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3812 hw->phy.sfp_type);
3813 }
3814 /* don't need this routine any more */
3815 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3816 }
3817 return;
3818reschedule:
3819 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3820 mod_timer(&adapter->sfp_timer,
3821 round_jiffies(jiffies + (2 * HZ)));
3822}
3823
9a799d71
AK		 3824/**
3825 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3826 * @adapter: board private structure to initialize
3827 *
3828 * ixgbe_sw_init initializes the Adapter private data structure.
3829 * Fields are initialized based on PCI device information and
3830 * OS network device settings (MTU size).
3831 **/
3832static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3833{
3834 struct ixgbe_hw *hw = &adapter->hw;
3835 struct pci_dev *pdev = adapter->pdev;
021230d4 3836 unsigned int rss;
7a6b6f51 3837#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3838 int j;
3839 struct tc_configuration *tc;
3840#endif
021230d4 3841
c44ade9e
JB		 3842 /* PCI config space info */
3843
3844 hw->vendor_id = pdev->vendor;
3845 hw->device_id = pdev->device;
3846 hw->revision_id = pdev->revision;
3847 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3848 hw->subsystem_device_id = pdev->subsystem_device;
3849
021230d4
AV		 3850 /* Set capability flags */
3851 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3852 adapter->ring_feature[RING_F_RSS].indices = rss;
3853 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 3854 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
bf069c97
DS		 3855 if (hw->mac.type == ixgbe_mac_82598EB) {
3856 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3857 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 3858 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bf069c97 3859 } else if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350 3860 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 3861 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3862 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
c4cf55e5
PWJ		 3863 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3864 adapter->ring_feature[RING_F_FDIR].indices =
3865 IXGBE_MAX_FDIR_INDICES;
3866 adapter->atr_sample_rate = 20;
3867 adapter->fdir_pballoc = 0;
eacd73f7 3868#ifdef IXGBE_FCOE
0d551589
YZ		 3869 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3870 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3871 adapter->ring_feature[RING_F_FCOE].indices = 0;
6ee16520
YZ		 3872 /* Default traffic class to use for FCoE */
3873 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
eacd73f7 3874#endif /* IXGBE_FCOE */
f8212f97 3875 }
2f90b865 3876
7a6b6f51 3877#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3878 /* Configure DCB traffic classes */
3879 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3880 tc = &adapter->dcb_cfg.tc_config[j];
3881 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3882 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3883 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3884 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3885 tc->dcb_pfc = pfc_disabled;
3886 }
3887 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3888 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3889 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
264857b8 3890 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865
AD		 3891 adapter->dcb_cfg.round_robin_enable = false;
3892 adapter->dcb_set_bitmap = 0x00;
3893 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3894 adapter->ring_feature[RING_F_DCB].indices);
3895
3896#endif
9a799d71
AK		 3897
3898 /* default flow control settings */
cd7664f6 3899 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 3900 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 3901#ifdef CONFIG_DCB
3902 adapter->last_lfc_mode = hw->fc.current_mode;
3903#endif
2b9ade93
JB		 3904 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3905 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3906 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3907 hw->fc.send_xon = true;
71fd570b 3908 hw->fc.disable_fc_autoneg = false;
9a799d71 3909
30efa5a3 3910 /* enable itr by default in dynamic mode */
f7554a2b
NS		 3911 adapter->rx_itr_setting = 1;
3912 adapter->rx_eitr_param = 20000;
3913 adapter->tx_itr_setting = 1;
3914 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 3915
3916 /* set defaults for eitr in MegaBytes */
3917 adapter->eitr_low = 10;
3918 adapter->eitr_high = 20;
3919
3920 /* set default ring sizes */
3921 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3922 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3923
9a799d71 3924 /* initialize eeprom parameters */
c44ade9e 3925 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 3926 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3927 return -EIO;
3928 }
3929
021230d4 3930 /* enable rx csum by default */
9a799d71
AK		 3931 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3932
9a799d71
AK		 3933 set_bit(__IXGBE_DOWN, &adapter->state);
3934
3935 return 0;
3936}
3937
3938/**
3939 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3940 * @adapter: board private structure
3a581073 3941 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 3942 *
3943 * Return 0 on success, negative on failure
3944 **/
3945int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 3946 struct ixgbe_ring *tx_ring)
9a799d71
AK		 3947{
3948 struct pci_dev *pdev = adapter->pdev;
3949 int size;
3950
3a581073
JB		 3951 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3952 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 3953 if (!tx_ring->tx_buffer_info)
3954 goto err;
3a581073 3955 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 3956
3957 /* round up to nearest 4K */
12207e49 3958 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 3959 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 3960
3a581073
JB		 3961 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3962 &tx_ring->dma);
e01c31a5
JB		 3963 if (!tx_ring->desc)
3964 goto err;
9a799d71 3965
3a581073
JB		 3966 tx_ring->next_to_use = 0;
3967 tx_ring->next_to_clean = 0;
3968 tx_ring->work_limit = tx_ring->count;
9a799d71 3969 return 0;
e01c31a5
JB		 3970
3971err:
3972 vfree(tx_ring->tx_buffer_info);
3973 tx_ring->tx_buffer_info = NULL;
3974 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3975 "descriptor ring\n");
3976 return -ENOMEM;
9a799d71
AK		 3977}
3978
69888674
AD		 3979/**
3980 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3981 * @adapter: board private structure
3982 *
3983 * If this function returns with an error, then it's possible one or
3984 * more of the rings is populated (while the rest are not). It is the
3985 * callers duty to clean those orphaned rings.
3986 *
3987 * Return 0 on success, negative on failure
3988 **/
3989static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3990{
3991 int i, err = 0;
3992
3993 for (i = 0; i < adapter->num_tx_queues; i++) {
3994 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3995 if (!err)
3996 continue;
3997 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3998 break;
3999 }
4000
4001 return err;
4002}
4003
9a799d71
AK		 4004/**
4005 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4006 * @adapter: board private structure
3a581073 4007 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4008 *
4009 * Returns 0 on success, negative on failure
4010 **/
4011int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 4012 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4013{
4014 struct pci_dev *pdev = adapter->pdev;
021230d4 4015 int size;
9a799d71 4016
3a581073
JB		 4017 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4018 rx_ring->rx_buffer_info = vmalloc(size);
4019 if (!rx_ring->rx_buffer_info) {
9a799d71 4020 DPRINTK(PROBE, ERR,
b4617240 4021 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 4022 goto alloc_failed;
9a799d71 4023 }
3a581073 4024 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 4025
9a799d71 4026 /* Round up to nearest 4K */
3a581073
JB		 4027 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4028 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4029
3a581073 4030 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 4031
3a581073 4032 if (!rx_ring->desc) {
9a799d71 4033 DPRINTK(PROBE, ERR,
b4617240 4034 "Memory allocation failed for the rx desc ring\n");
3a581073 4035 vfree(rx_ring->rx_buffer_info);
177db6ff 4036 goto alloc_failed;
9a799d71
AK		 4037 }
4038
3a581073
JB		 4039 rx_ring->next_to_clean = 0;
4040 rx_ring->next_to_use = 0;
9a799d71
AK		 4041
4042 return 0;
177db6ff
MC		 4043
4044alloc_failed:
177db6ff 4045 return -ENOMEM;
9a799d71
AK		 4046}
4047
69888674
AD		 4048/**
4049 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4050 * @adapter: board private structure
4051 *
4052 * If this function returns with an error, then it's possible one or
4053 * more of the rings is populated (while the rest are not). It is the
4054 * callers duty to clean those orphaned rings.
4055 *
4056 * Return 0 on success, negative on failure
4057 **/
4058
4059static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4060{
4061 int i, err = 0;
4062
4063 for (i = 0; i < adapter->num_rx_queues; i++) {
4064 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4065 if (!err)
4066 continue;
4067 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4068 break;
4069 }
4070
4071 return err;
4072}
4073
9a799d71
AK		 4074/**
4075 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4076 * @adapter: board private structure
4077 * @tx_ring: Tx descriptor ring for a specific queue
4078 *
4079 * Free all transmit software resources
4080 **/
c431f97e
JB		 4081void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4082 struct ixgbe_ring *tx_ring)
9a799d71
AK		 4083{
4084 struct pci_dev *pdev = adapter->pdev;
4085
4086 ixgbe_clean_tx_ring(adapter, tx_ring);
4087
4088 vfree(tx_ring->tx_buffer_info);
4089 tx_ring->tx_buffer_info = NULL;
4090
4091 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4092
4093 tx_ring->desc = NULL;
4094}
4095
4096/**
4097 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4098 * @adapter: board private structure
4099 *
4100 * Free all transmit software resources
4101 **/
4102static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4103{
4104 int i;
4105
4106 for (i = 0; i < adapter->num_tx_queues; i++)
9891ca7c
JB		 4107 if (adapter->tx_ring[i].desc)
4108 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 4109}
4110
4111/**
b4617240 4112 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4113 * @adapter: board private structure
4114 * @rx_ring: ring to clean the resources from
4115 *
4116 * Free all receive software resources
4117 **/
c431f97e
JB		 4118void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4119 struct ixgbe_ring *rx_ring)
9a799d71
AK		 4120{
4121 struct pci_dev *pdev = adapter->pdev;
4122
4123 ixgbe_clean_rx_ring(adapter, rx_ring);
4124
4125 vfree(rx_ring->rx_buffer_info);
4126 rx_ring->rx_buffer_info = NULL;
4127
4128 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4129
4130 rx_ring->desc = NULL;
4131}
4132
4133/**
4134 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4135 * @adapter: board private structure
4136 *
4137 * Free all receive software resources
4138 **/
4139static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4140{
4141 int i;
4142
4143 for (i = 0; i < adapter->num_rx_queues; i++)
9891ca7c
JB		 4144 if (adapter->rx_ring[i].desc)
4145 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 4146}
4147
9a799d71
AK		 4148/**
4149 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4150 * @netdev: network interface device structure
4151 * @new_mtu: new value for maximum frame size
4152 *
4153 * Returns 0 on success, negative on failure
4154 **/
4155static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4156{
4157 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4158 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4159
42c783c5
JB		 4160 /* MTU < 68 is an error and causes problems on some kernels */
4161 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 4162 return -EINVAL;
4163
021230d4 4164 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 4165 netdev->mtu, new_mtu);
021230d4 4166 /* must set new MTU before calling down or up */
9a799d71
AK		 4167 netdev->mtu = new_mtu;
4168
d4f80882
AV		 4169 if (netif_running(netdev))
4170 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4171
4172 return 0;
4173}
4174
4175/**
4176 * ixgbe_open - Called when a network interface is made active
4177 * @netdev: network interface device structure
4178 *
4179 * Returns 0 on success, negative value on failure
4180 *
4181 * The open entry point is called when a network interface is made
4182 * active by the system (IFF_UP). At this point all resources needed
4183 * for transmit and receive operations are allocated, the interrupt
4184 * handler is registered with the OS, the watchdog timer is started,
4185 * and the stack is notified that the interface is ready.
4186 **/
4187static int ixgbe_open(struct net_device *netdev)
4188{
4189 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4190 int err;
4bebfaa5
AK		 4191
4192 /* disallow open during test */
4193 if (test_bit(__IXGBE_TESTING, &adapter->state))
4194 return -EBUSY;
9a799d71 4195
54386467
JB		 4196 netif_carrier_off(netdev);
4197
9a799d71
AK		 4198 /* allocate transmit descriptors */
4199 err = ixgbe_setup_all_tx_resources(adapter);
4200 if (err)
4201 goto err_setup_tx;
4202
9a799d71
AK		 4203 /* allocate receive descriptors */
4204 err = ixgbe_setup_all_rx_resources(adapter);
4205 if (err)
4206 goto err_setup_rx;
4207
4208 ixgbe_configure(adapter);
4209
021230d4 4210 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4211 if (err)
4212 goto err_req_irq;
4213
9a799d71
AK		 4214 err = ixgbe_up_complete(adapter);
4215 if (err)
4216 goto err_up;
4217
d55b53ff
JK		 4218 netif_tx_start_all_queues(netdev);
4219
9a799d71
AK		 4220 return 0;
4221
4222err_up:
5eba3699 4223 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4224 ixgbe_free_irq(adapter);
4225err_req_irq:
9a799d71 4226err_setup_rx:
a20a1199 4227 ixgbe_free_all_rx_resources(adapter);
9a799d71 4228err_setup_tx:
a20a1199 4229 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4230 ixgbe_reset(adapter);
4231
4232 return err;
4233}
4234
4235/**
4236 * ixgbe_close - Disables a network interface
4237 * @netdev: network interface device structure
4238 *
4239 * Returns 0, this is not allowed to fail
4240 *
4241 * The close entry point is called when an interface is de-activated
4242 * by the OS. The hardware is still under the drivers control, but
4243 * needs to be disabled. A global MAC reset is issued to stop the
4244 * hardware, and all transmit and receive resources are freed.
4245 **/
4246static int ixgbe_close(struct net_device *netdev)
4247{
4248 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4249
4250 ixgbe_down(adapter);
4251 ixgbe_free_irq(adapter);
4252
4253 ixgbe_free_all_tx_resources(adapter);
4254 ixgbe_free_all_rx_resources(adapter);
4255
5eba3699 4256 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4257
4258 return 0;
4259}
4260
b3c8b4ba
AD		 4261#ifdef CONFIG_PM
4262static int ixgbe_resume(struct pci_dev *pdev)
4263{
4264 struct net_device *netdev = pci_get_drvdata(pdev);
4265 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4266 u32 err;
4267
4268 pci_set_power_state(pdev, PCI_D0);
4269 pci_restore_state(pdev);
9ce77666 4270
4271 err = pci_enable_device_mem(pdev);
b3c8b4ba 4272 if (err) {
69888674 4273 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 4274 "suspend\n");
4275 return err;
4276 }
4277 pci_set_master(pdev);
4278
dd4d8ca6 4279 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 4280
4281 err = ixgbe_init_interrupt_scheme(adapter);
4282 if (err) {
4283 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4284 "device\n");
4285 return err;
4286 }
4287
b3c8b4ba
AD		 4288 ixgbe_reset(adapter);
4289
495dce12
WJP		 4290 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4291
b3c8b4ba
AD		 4292 if (netif_running(netdev)) {
4293 err = ixgbe_open(adapter->netdev);
4294 if (err)
4295 return err;
4296 }
4297
4298 netif_device_attach(netdev);
4299
4300 return 0;
4301}
b3c8b4ba 4302#endif /* CONFIG_PM */
9d8d05ae
RW		 4303
4304static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba
AD		 4305{
4306 struct net_device *netdev = pci_get_drvdata(pdev);
4307 struct ixgbe_adapter *adapter = netdev_priv(netdev);
e8e26350
PW		 4308 struct ixgbe_hw *hw = &adapter->hw;
4309 u32 ctrl, fctrl;
4310 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4311#ifdef CONFIG_PM
4312 int retval = 0;
4313#endif
4314
4315 netif_device_detach(netdev);
4316
4317 if (netif_running(netdev)) {
4318 ixgbe_down(adapter);
4319 ixgbe_free_irq(adapter);
4320 ixgbe_free_all_tx_resources(adapter);
4321 ixgbe_free_all_rx_resources(adapter);
4322 }
7a921c93 4323 ixgbe_clear_interrupt_scheme(adapter);
b3c8b4ba
AD		 4324
4325#ifdef CONFIG_PM
4326 retval = pci_save_state(pdev);
4327 if (retval)
4328 return retval;
4df10466 4329
b3c8b4ba 4330#endif
e8e26350
PW		 4331 if (wufc) {
4332 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4333
e8e26350
PW		 4334 /* turn on all-multi mode if wake on multicast is enabled */
4335 if (wufc & IXGBE_WUFC_MC) {
4336 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4337 fctrl |= IXGBE_FCTRL_MPE;
4338 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4339 }
4340
4341 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4342 ctrl |= IXGBE_CTRL_GIO_DIS;
4343 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4344
4345 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4346 } else {
4347 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4348 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4349 }
4350
dd4d8ca6
DS		 4351 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4352 pci_wake_from_d3(pdev, true);
4353 else
4354 pci_wake_from_d3(pdev, false);
b3c8b4ba 4355
9d8d05ae
RW		 4356 *enable_wake = !!wufc;
4357
b3c8b4ba
AD		 4358 ixgbe_release_hw_control(adapter);
4359
4360 pci_disable_device(pdev);
4361
9d8d05ae
RW		 4362 return 0;
4363}
4364
4365#ifdef CONFIG_PM
4366static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4367{
4368 int retval;
4369 bool wake;
4370
4371 retval = __ixgbe_shutdown(pdev, &wake);
4372 if (retval)
4373 return retval;
4374
4375 if (wake) {
4376 pci_prepare_to_sleep(pdev);
4377 } else {
4378 pci_wake_from_d3(pdev, false);
4379 pci_set_power_state(pdev, PCI_D3hot);
4380 }
b3c8b4ba
AD		 4381
4382 return 0;
4383}
9d8d05ae 4384#endif /* CONFIG_PM */
b3c8b4ba
AD		 4385
4386static void ixgbe_shutdown(struct pci_dev *pdev)
4387{
9d8d05ae
RW		 4388 bool wake;
4389
4390 __ixgbe_shutdown(pdev, &wake);
4391
4392 if (system_state == SYSTEM_POWER_OFF) {
4393 pci_wake_from_d3(pdev, wake);
4394 pci_set_power_state(pdev, PCI_D3hot);
4395 }
b3c8b4ba
AD		 4396}
4397
9a799d71
AK		 4398/**
4399 * ixgbe_update_stats - Update the board statistics counters.
4400 * @adapter: board private structure
4401 **/
4402void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4403{
4404 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 4405 u64 total_mpc = 0;
4406 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71 4407
d51019a4 4408 if (hw->mac.type == ixgbe_mac_82599EB) {
f8212f97 4409 u64 rsc_count = 0;
d51019a4
PW		 4410 for (i = 0; i < 16; i++)
4411 adapter->hw_rx_no_dma_resources +=
4412 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
f8212f97
AD		 4413 for (i = 0; i < adapter->num_rx_queues; i++)
4414 rsc_count += adapter->rx_ring[i].rsc_count;
4415 adapter->rsc_count = rsc_count;
d51019a4
PW		 4416 }
4417
9a799d71 4418 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 4419 for (i = 0; i < 8; i++) {
4420 /* for packet buffers not used, the register should read 0 */
4421 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4422 missed_rx += mpc;
4423 adapter->stats.mpc[i] += mpc;
4424 total_mpc += adapter->stats.mpc[i];
e8e26350
PW		 4425 if (hw->mac.type == ixgbe_mac_82598EB)
4426 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 4427 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4428 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4429 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4430 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
e8e26350
PW		 4431 if (hw->mac.type == ixgbe_mac_82599EB) {
4432 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4433 IXGBE_PXONRXCNT(i));
4434 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4435 IXGBE_PXOFFRXCNT(i));
4436 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
e8e26350
PW		 4437 } else {
4438 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4439 IXGBE_PXONRXC(i));
4440 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4441 IXGBE_PXOFFRXC(i));
4442 }
2f90b865
AD		 4443 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4444 IXGBE_PXONTXC(i));
2f90b865 4445 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
e8e26350 4446 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 4447 }
4448 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4449 /* work around hardware counting issue */
4450 adapter->stats.gprc -= missed_rx;
4451
4452 /* 82598 hardware only has a 32 bit counter in the high register */
e8e26350 4453 if (hw->mac.type == ixgbe_mac_82599EB) {
aad71918 4454 u64 tmp;
e8e26350 4455 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
aad71918
BG		 4456 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
4457 adapter->stats.gorc += (tmp << 32);
e8e26350 4458 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
aad71918
BG		 4459 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
4460 adapter->stats.gotc += (tmp << 32);
e8e26350
PW		 4461 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4462 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4463 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4464 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
c4cf55e5
PWJ		 4465 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4466 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c
YZ		 4467#ifdef IXGBE_FCOE
4468 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4469 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4470 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4471 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4472 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4473 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4474#endif /* IXGBE_FCOE */
e8e26350
PW		 4475 } else {
4476 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4477 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4478 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4479 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4480 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4481 }
9a799d71
AK		 4482 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4483 adapter->stats.bprc += bprc;
4484 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350
PW		 4485 if (hw->mac.type == ixgbe_mac_82598EB)
4486 adapter->stats.mprc -= bprc;
9a799d71
AK		 4487 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4488 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4489 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4490 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4491 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4492 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4493 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71 4494 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7
AV		 4495 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4496 adapter->stats.lxontxc += lxon;
4497 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4498 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 4499 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4500 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 4501 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4502 /*
4503 * 82598 errata - tx of flow control packets is included in tx counters
4504 */
4505 xon_off_tot = lxon + lxoff;
4506 adapter->stats.gptc -= xon_off_tot;
4507 adapter->stats.mptc -= xon_off_tot;
4508 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 4509 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4510 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4511 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 4512 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4513 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 4514 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 4515 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4516 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4517 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4518 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4519 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 4520 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4521
4522 /* Fill out the OS statistics structure */
9a799d71
AK		 4523 adapter->net_stats.multicast = adapter->stats.mprc;
4524
4525 /* Rx Errors */
4526 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 4527 adapter->stats.rlec;
9a799d71
AK		 4528 adapter->net_stats.rx_dropped = 0;
4529 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4530 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 4531 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 4532}
4533
4534/**
4535 * ixgbe_watchdog - Timer Call-back
4536 * @data: pointer to adapter cast into an unsigned long
4537 **/
4538static void ixgbe_watchdog(unsigned long data)
4539{
4540 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee 4541 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 4542 u64 eics = 0;
4543 int i;
cf8280ee 4544
fe49f04a
AD		 4545 /*
4546 * Do the watchdog outside of interrupt context due to the lovely
4547 * delays that some of the newer hardware requires
4548 */
22d5a71b 4549
fe49f04a
AD		 4550 if (test_bit(__IXGBE_DOWN, &adapter->state))
4551 goto watchdog_short_circuit;
22d5a71b 4552
fe49f04a
AD		 4553 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4554 /*
4555 * for legacy and MSI interrupts don't set any bits
4556 * that are enabled for EIAM, because this operation
4557 * would set *both* EIMS and EICS for any bit in EIAM
4558 */
4559 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4560 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4561 goto watchdog_reschedule;
4562 }
4563
4564 /* get one bit for every active tx/rx interrupt vector */
4565 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4566 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4567 if (qv->rxr_count || qv->txr_count)
4568 eics |= ((u64)1 << i);
cf8280ee 4569 }
9a799d71 4570
fe49f04a
AD		 4571 /* Cause software interrupt to ensure rx rings are cleaned */
4572 ixgbe_irq_rearm_queues(adapter, eics);
4573
4574watchdog_reschedule:
4575 /* Reset the timer */
4576 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4577
4578watchdog_short_circuit:
cf8280ee
JB		 4579 schedule_work(&adapter->watchdog_task);
4580}
4581
e8e26350
PW		 4582/**
4583 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4584 * @work: pointer to work_struct containing our data
4585 **/
4586static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4587{
4588 struct ixgbe_adapter *adapter = container_of(work,
4589 struct ixgbe_adapter,
4590 multispeed_fiber_task);
4591 struct ixgbe_hw *hw = &adapter->hw;
4592 u32 autoneg;
8620a103 4593 bool negotiation;
e8e26350
PW		 4594
4595 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
a1f25324
MC		 4596 autoneg = hw->phy.autoneg_advertised;
4597 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
8620a103
MC		 4598 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4599 if (hw->mac.ops.setup_link)
4600 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
e8e26350
PW		 4601 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4602 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4603}
4604
4605/**
4606 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4607 * @work: pointer to work_struct containing our data
4608 **/
4609static void ixgbe_sfp_config_module_task(struct work_struct *work)
4610{
4611 struct ixgbe_adapter *adapter = container_of(work,
4612 struct ixgbe_adapter,
4613 sfp_config_module_task);
4614 struct ixgbe_hw *hw = &adapter->hw;
4615 u32 err;
4616
4617 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
63d6e1d8
DS		 4618
4619 /* Time for electrical oscillations to settle down */
4620 msleep(100);
e8e26350 4621 err = hw->phy.ops.identify_sfp(hw);
63d6e1d8 4622
e8e26350 4623 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 4624 dev_err(&adapter->pdev->dev, "failed to initialize because "
4625 "an unsupported SFP+ module type was detected.\n"
4626 "Reload the driver after installing a supported "
4627 "module.\n");
63d6e1d8 4628 unregister_netdev(adapter->netdev);
e8e26350
PW		 4629 return;
4630 }
4631 hw->mac.ops.setup_sfp(hw);
4632
8d1c3c07 4633 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
e8e26350
PW		 4634 /* This will also work for DA Twinax connections */
4635 schedule_work(&adapter->multispeed_fiber_task);
4636 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4637}
4638
c4cf55e5
PWJ		 4639/**
4640 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4641 * @work: pointer to work_struct containing our data
4642 **/
4643static void ixgbe_fdir_reinit_task(struct work_struct *work)
4644{
4645 struct ixgbe_adapter *adapter = container_of(work,
4646 struct ixgbe_adapter,
4647 fdir_reinit_task);
4648 struct ixgbe_hw *hw = &adapter->hw;
4649 int i;
4650
4651 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4652 for (i = 0; i < adapter->num_tx_queues; i++)
4653 set_bit(__IXGBE_FDIR_INIT_DONE,
4654 &(adapter->tx_ring[i].reinit_state));
4655 } else {
4656 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4657 "ignored adding FDIR ATR filters \n");
4658 }
4659 /* Done FDIR Re-initialization, enable transmits */
4660 netif_tx_start_all_queues(adapter->netdev);
4661}
4662
cf8280ee 4663/**
69888674
AD		 4664 * ixgbe_watchdog_task - worker thread to bring link up
4665 * @work: pointer to work_struct containing our data
cf8280ee
JB		 4666 **/
4667static void ixgbe_watchdog_task(struct work_struct *work)
4668{
4669 struct ixgbe_adapter *adapter = container_of(work,
4670 struct ixgbe_adapter,
4671 watchdog_task);
4672 struct net_device *netdev = adapter->netdev;
4673 struct ixgbe_hw *hw = &adapter->hw;
4674 u32 link_speed = adapter->link_speed;
4675 bool link_up = adapter->link_up;
bc59fcda
NS		 4676 int i;
4677 struct ixgbe_ring *tx_ring;
4678 int some_tx_pending = 0;
cf8280ee
JB		 4679
4680 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4681
4682 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4683 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
264857b8
PWJ		 4684 if (link_up) {
4685#ifdef CONFIG_DCB
4686 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4687 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
620fa036 4688 hw->mac.ops.fc_enable(hw, i);
264857b8 4689 } else {
620fa036 4690 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4691 }
4692#else
620fa036 4693 hw->mac.ops.fc_enable(hw, 0);
264857b8
PWJ		 4694#endif
4695 }
4696
cf8280ee
JB		 4697 if (link_up ||
4698 time_after(jiffies, (adapter->link_check_timeout +
4699 IXGBE_TRY_LINK_TIMEOUT))) {
cf8280ee 4700 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
264857b8 4701 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
cf8280ee
JB		 4702 }
4703 adapter->link_up = link_up;
4704 adapter->link_speed = link_speed;
4705 }
9a799d71
AK		 4706
4707 if (link_up) {
4708 if (!netif_carrier_ok(netdev)) {
e8e26350
PW		 4709 bool flow_rx, flow_tx;
4710
4711 if (hw->mac.type == ixgbe_mac_82599EB) {
4712 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4713 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
078788b6
PWJ		 4714 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4715 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
e8e26350
PW		 4716 } else {
4717 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4718 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
078788b6
PWJ		 4719 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4720 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
e8e26350
PW		 4721 }
4722
a46e534b
JK		 4723 printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4724 "Flow Control: %s\n",
4725 netdev->name,
4726 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4727 "10 Gbps" :
4728 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4729 "1 Gbps" : "unknown speed")),
e8e26350
PW		 4730 ((flow_rx && flow_tx) ? "RX/TX" :
4731 (flow_rx ? "RX" :
4732 (flow_tx ? "TX" : "None"))));
9a799d71
AK		 4733
4734 netif_carrier_on(netdev);
9a799d71
AK		 4735 } else {
4736 /* Force detection of hung controller */
4737 adapter->detect_tx_hung = true;
4738 }
4739 } else {
cf8280ee
JB		 4740 adapter->link_up = false;
4741 adapter->link_speed = 0;
9a799d71 4742 if (netif_carrier_ok(netdev)) {
a46e534b
JK		 4743 printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4744 netdev->name);
9a799d71 4745 netif_carrier_off(netdev);
9a799d71
AK		 4746 }
4747 }
4748
bc59fcda
NS		 4749 if (!netif_carrier_ok(netdev)) {
4750 for (i = 0; i < adapter->num_tx_queues; i++) {
4751 tx_ring = &adapter->tx_ring[i];
4752 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4753 some_tx_pending = 1;
4754 break;
4755 }
4756 }
4757
4758 if (some_tx_pending) {
4759 /* We've lost link, so the controller stops DMA,
4760 * but we've got queued Tx work that's never going
4761 * to get done, so reset controller to flush Tx.
4762 * (Do the reset outside of interrupt context).
4763 */
4764 schedule_work(&adapter->reset_task);
4765 }
4766 }
4767
9a799d71 4768 ixgbe_update_stats(adapter);
cf8280ee 4769 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 4770}
4771
9a799d71 4772static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 4773 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4774 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 4775{
4776 struct ixgbe_adv_tx_context_desc *context_desc;
4777 unsigned int i;
4778 int err;
4779 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 4780 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4781 u32 mss_l4len_idx, l4len;
9a799d71
AK		 4782
4783 if (skb_is_gso(skb)) {
4784 if (skb_header_cloned(skb)) {
4785 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4786 if (err)
4787 return err;
4788 }
4789 l4len = tcp_hdrlen(skb);
4790 *hdr_len += l4len;
4791
8327d000 4792 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 4793 struct iphdr *iph = ip_hdr(skb);
4794 iph->tot_len = 0;
4795 iph->check = 0;
4796 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 4797 iph->daddr, 0,
4798 IPPROTO_TCP,
4799 0);
9a799d71
AK		 4800 adapter->hw_tso_ctxt++;
4801 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4802 ipv6_hdr(skb)->payload_len = 0;
4803 tcp_hdr(skb)->check =
4804 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 4805 &ipv6_hdr(skb)->daddr,
4806 0, IPPROTO_TCP, 0);
9a799d71
AK		 4807 adapter->hw_tso6_ctxt++;
4808 }
4809
4810 i = tx_ring->next_to_use;
4811
4812 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4813 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4814
4815 /* VLAN MACLEN IPLEN */
4816 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4817 vlan_macip_lens |=
4818 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4819 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 4820 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4821 *hdr_len += skb_network_offset(skb);
4822 vlan_macip_lens |=
4823 (skb_transport_header(skb) - skb_network_header(skb));
4824 *hdr_len +=
4825 (skb_transport_header(skb) - skb_network_header(skb));
4826 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4827 context_desc->seqnum_seed = 0;
4828
4829 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 4830 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 4831 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 4832
8327d000 4833 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 4834 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4835 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4836 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4837
4838 /* MSS L4LEN IDX */
9f8cdf4f 4839 mss_l4len_idx =
9a799d71
AK		 4840 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4841 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 4842 /* use index 1 for TSO */
4843 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 4844 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4845
4846 tx_buffer_info->time_stamp = jiffies;
4847 tx_buffer_info->next_to_watch = i;
4848
4849 i++;
4850 if (i == tx_ring->count)
4851 i = 0;
4852 tx_ring->next_to_use = i;
4853
4854 return true;
4855 }
4856 return false;
4857}
4858
4859static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 4860 struct ixgbe_ring *tx_ring,
4861 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 4862{
4863 struct ixgbe_adv_tx_context_desc *context_desc;
4864 unsigned int i;
4865 struct ixgbe_tx_buffer *tx_buffer_info;
4866 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4867
4868 if (skb->ip_summed == CHECKSUM_PARTIAL ||
4869 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4870 i = tx_ring->next_to_use;
4871 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4872 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4873
4874 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4875 vlan_macip_lens |=
4876 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4877 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 4878 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 4879 if (skb->ip_summed == CHECKSUM_PARTIAL)
4880 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 4881 skb_network_header(skb));
9a799d71
AK		 4882
4883 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4884 context_desc->seqnum_seed = 0;
4885
4886 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 4887 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 4888
4889 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71 4890 switch (skb->protocol) {
09640e63 4891 case cpu_to_be16(ETH_P_IP):
9a799d71 4892 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 4893 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4894 type_tucmd_mlhl |=
b4617240 4895 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4896 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4897 type_tucmd_mlhl |=
4898 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4899 break;
09640e63 4900 case cpu_to_be16(ETH_P_IPV6):
41825d71
AK		 4901 /* XXX what about other V6 headers?? */
4902 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4903 type_tucmd_mlhl |=
b4617240 4904 IXGBE_ADVTXD_TUCMD_L4T_TCP;
45a5ead0
JB		 4905 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4906 type_tucmd_mlhl |=
4907 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
41825d71 4908 break;
41825d71
AK		 4909 default:
4910 if (unlikely(net_ratelimit())) {
4911 DPRINTK(PROBE, WARNING,
4912 "partial checksum but proto=%x!\n",
4913 skb->protocol);
4914 }
4915 break;
4916 }
9a799d71
AK		 4917 }
4918
4919 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 4920 /* use index zero for tx checksum offload */
9a799d71
AK		 4921 context_desc->mss_l4len_idx = 0;
4922
4923 tx_buffer_info->time_stamp = jiffies;
4924 tx_buffer_info->next_to_watch = i;
9f8cdf4f 4925
9a799d71
AK		 4926 adapter->hw_csum_tx_good++;
4927 i++;
4928 if (i == tx_ring->count)
4929 i = 0;
4930 tx_ring->next_to_use = i;
4931
4932 return true;
4933 }
9f8cdf4f 4934
9a799d71
AK		 4935 return false;
4936}
4937
4938static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240 4939 struct ixgbe_ring *tx_ring,
eacd73f7
YZ		 4940 struct sk_buff *skb, u32 tx_flags,
4941 unsigned int first)
9a799d71
AK		 4942{
4943 struct ixgbe_tx_buffer *tx_buffer_info;
eacd73f7
YZ		 4944 unsigned int len;
4945 unsigned int total = skb->len;
9a799d71
AK		 4946 unsigned int offset = 0, size, count = 0, i;
4947 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4948 unsigned int f;
44df32c5 4949 dma_addr_t *map;
9a799d71
AK		 4950
4951 i = tx_ring->next_to_use;
4952
44df32c5
AD		 4953 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4954 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4955 return 0;
4956 }
4957
4958 map = skb_shinfo(skb)->dma_maps;
4959
eacd73f7
YZ		 4960 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4961 /* excluding fcoe_crc_eof for FCoE */
4962 total -= sizeof(struct fcoe_crc_eof);
4963
4964 len = min(skb_headlen(skb), total);
9a799d71
AK		 4965 while (len) {
4966 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4967 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4968
4969 tx_buffer_info->length = size;
042a53a9 4970 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
9a799d71
AK		 4971 tx_buffer_info->time_stamp = jiffies;
4972 tx_buffer_info->next_to_watch = i;
4973
4974 len -= size;
eacd73f7 4975 total -= size;
9a799d71
AK		 4976 offset += size;
4977 count++;
44df32c5
AD		 4978
4979 if (len) {
4980 i++;
4981 if (i == tx_ring->count)
4982 i = 0;
4983 }
9a799d71
AK		 4984 }
4985
4986 for (f = 0; f < nr_frags; f++) {
4987 struct skb_frag_struct *frag;
4988
4989 frag = &skb_shinfo(skb)->frags[f];
eacd73f7 4990 len = min((unsigned int)frag->size, total);
44df32c5 4991 offset = 0;
9a799d71
AK		 4992
4993 while (len) {
44df32c5
AD		 4994 i++;
4995 if (i == tx_ring->count)
4996 i = 0;
4997
9a799d71
AK		 4998 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4999 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5000
5001 tx_buffer_info->length = size;
042a53a9 5002 tx_buffer_info->dma = map[f] + offset;
9a799d71
AK		 5003 tx_buffer_info->time_stamp = jiffies;
5004 tx_buffer_info->next_to_watch = i;
5005
5006 len -= size;
eacd73f7 5007 total -= size;
9a799d71
AK		 5008 offset += size;
5009 count++;
9a799d71 5010 }
eacd73f7
YZ		 5011 if (total == 0)
5012 break;
9a799d71 5013 }
44df32c5 5014
9a799d71
AK		 5015 tx_ring->tx_buffer_info[i].skb = skb;
5016 tx_ring->tx_buffer_info[first].next_to_watch = i;
5017
5018 return count;
5019}
5020
5021static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 5022 struct ixgbe_ring *tx_ring,
5023 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 5024{
5025 union ixgbe_adv_tx_desc *tx_desc = NULL;
5026 struct ixgbe_tx_buffer *tx_buffer_info;
5027 u32 olinfo_status = 0, cmd_type_len = 0;
5028 unsigned int i;
5029 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
5030
5031 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
5032
5033 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
5034
5035 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5036 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
5037
5038 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
5039 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5040
5041 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5042 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5043
4eeae6fd
PW		 5044 /* use index 1 context for tso */
5045 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 5046 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5047 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 5048 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 5049
5050 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5051 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 5052 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 5053
eacd73f7
YZ		 5054 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5055 olinfo_status |= IXGBE_ADVTXD_CC;
5056 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5057 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5058 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5059 }
5060
9a799d71
AK		 5061 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5062
5063 i = tx_ring->next_to_use;
5064 while (count--) {
5065 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5066 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5067 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5068 tx_desc->read.cmd_type_len =
b4617240 5069 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 5070 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 5071 i++;
5072 if (i == tx_ring->count)
5073 i = 0;
5074 }
5075
5076 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5077
5078 /*
5079 * Force memory writes to complete before letting h/w
5080 * know there are new descriptors to fetch. (Only
5081 * applicable for weak-ordered memory model archs,
5082 * such as IA-64).
5083 */
5084 wmb();
5085
5086 tx_ring->next_to_use = i;
5087 writel(i, adapter->hw.hw_addr + tx_ring->tail);
5088}
5089
c4cf55e5
PWJ		 5090static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5091 int queue, u32 tx_flags)
5092{
5093 /* Right now, we support IPv4 only */
5094 struct ixgbe_atr_input atr_input;
5095 struct tcphdr *th;
c4cf55e5
PWJ		 5096 struct iphdr *iph = ip_hdr(skb);
5097 struct ethhdr *eth = (struct ethhdr *)skb->data;
5098 u16 vlan_id, src_port, dst_port, flex_bytes;
5099 u32 src_ipv4_addr, dst_ipv4_addr;
5100 u8 l4type = 0;
5101
5102 /* check if we're UDP or TCP */
5103 if (iph->protocol == IPPROTO_TCP) {
5104 th = tcp_hdr(skb);
5105 src_port = th->source;
5106 dst_port = th->dest;
5107 l4type |= IXGBE_ATR_L4TYPE_TCP;
5108 /* l4type IPv4 type is 0, no need to assign */
c4cf55e5
PWJ		 5109 } else {
5110 /* Unsupported L4 header, just bail here */
5111 return;
5112 }
5113
5114 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5115
5116 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5117 IXGBE_TX_FLAGS_VLAN_SHIFT;
5118 src_ipv4_addr = iph->saddr;
5119 dst_ipv4_addr = iph->daddr;
5120 flex_bytes = eth->h_proto;
5121
5122 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5123 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5124 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5125 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5126 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5127 /* src and dst are inverted, think how the receiver sees them */
5128 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5129 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5130
5131 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5132 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5133}
5134
e092be60 5135static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5136 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5137{
5138 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5139
30eba97a 5140 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5141 /* Herbert's original patch had:
5142 * smp_mb__after_netif_stop_queue();
5143 * but since that doesn't exist yet, just open code it. */
5144 smp_mb();
5145
5146 /* We need to check again in a case another CPU has just
5147 * made room available. */
5148 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5149 return -EBUSY;
5150
5151 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 5152 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 5153 ++adapter->restart_queue;
5154 return 0;
5155}
5156
5157static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 5158 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 5159{
5160 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5161 return 0;
5162 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5163}
5164
09a3b1f8
SH		 5165static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5166{
5167 struct ixgbe_adapter *adapter = netdev_priv(dev);
5168
c4cf55e5
PWJ		 5169 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5170 return smp_processor_id();
5171
09a3b1f8 5172 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
36e89d73 5173 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
09a3b1f8
SH		 5174
5175 return skb_tx_hash(dev, skb);
5176}
5177
3b29a56d
SH		 5178static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5179 struct net_device *netdev)
9a799d71
AK		 5180{
5181 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5182 struct ixgbe_ring *tx_ring;
9a799d71
AK		 5183 unsigned int first;
5184 unsigned int tx_flags = 0;
30eba97a
AV		 5185 u8 hdr_len = 0;
5186 int r_idx = 0, tso;
9a799d71
AK		 5187 int count = 0;
5188 unsigned int f;
9f8cdf4f 5189
9f8cdf4f
JB		 5190 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5191 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 5192 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5193 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5194 tx_flags |= (skb->queue_mapping << 13);
5195 }
5196 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5197 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5198 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
60127865
LL		 5199 if (skb->priority != TC_PRIO_CONTROL) {
5200 tx_flags |= (skb->queue_mapping << 13);
5201 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5202 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5203 } else {
5204 skb->queue_mapping =
5205 adapter->ring_feature[RING_F_DCB].indices-1;
5206 }
9a799d71 5207 }
eacd73f7 5208
60127865
LL		 5209 r_idx = skb->queue_mapping;
5210 tx_ring = &adapter->tx_ring[r_idx];
5211
eacd73f7 5212 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
09ad1cc0 5213 (skb->protocol == htons(ETH_P_FCOE))) {
eacd73f7 5214 tx_flags |= IXGBE_TX_FLAGS_FCOE;
09ad1cc0
YZ		 5215#ifdef IXGBE_FCOE
5216 r_idx = smp_processor_id();
5217 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5218 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5219 tx_ring = &adapter->tx_ring[r_idx];
5220#endif
5221 }
eacd73f7 5222 /* four things can cause us to need a context descriptor */
9f8cdf4f
JB		 5223 if (skb_is_gso(skb) ||
5224 (skb->ip_summed == CHECKSUM_PARTIAL) ||
eacd73f7
YZ		 5225 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5226 (tx_flags & IXGBE_TX_FLAGS_FCOE))
9a799d71
AK		 5227 count++;
5228
9f8cdf4f
JB		 5229 count += TXD_USE_COUNT(skb_headlen(skb));
5230 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 5231 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5232
e092be60 5233 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 5234 adapter->tx_busy++;
9a799d71
AK		 5235 return NETDEV_TX_BUSY;
5236 }
9a799d71 5237
9a799d71 5238 first = tx_ring->next_to_use;
eacd73f7
YZ		 5239 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5240#ifdef IXGBE_FCOE
5241 /* setup tx offload for FCoE */
5242 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5243 if (tso < 0) {
5244 dev_kfree_skb_any(skb);
5245 return NETDEV_TX_OK;
5246 }
5247 if (tso)
5248 tx_flags |= IXGBE_TX_FLAGS_FSO;
5249#endif /* IXGBE_FCOE */
5250 } else {
5251 if (skb->protocol == htons(ETH_P_IP))
5252 tx_flags |= IXGBE_TX_FLAGS_IPV4;
5253 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5254 if (tso < 0) {
5255 dev_kfree_skb_any(skb);
5256 return NETDEV_TX_OK;
5257 }
9a799d71 5258
eacd73f7
YZ		 5259 if (tso)
5260 tx_flags |= IXGBE_TX_FLAGS_TSO;
5261 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5262 (skb->ip_summed == CHECKSUM_PARTIAL))
5263 tx_flags |= IXGBE_TX_FLAGS_CSUM;
5264 }
9a799d71 5265
eacd73f7 5266 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
44df32c5 5267 if (count) {
c4cf55e5
PWJ		 5268 /* add the ATR filter if ATR is on */
5269 if (tx_ring->atr_sample_rate) {
5270 ++tx_ring->atr_count;
5271 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5272 test_bit(__IXGBE_FDIR_INIT_DONE,
5273 &tx_ring->reinit_state)) {
5274 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5275 tx_flags);
5276 tx_ring->atr_count = 0;
5277 }
5278 }
44df32c5
AD		 5279 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5280 hdr_len);
44df32c5 5281 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71 5282
44df32c5
AD		 5283 } else {
5284 dev_kfree_skb_any(skb);
5285 tx_ring->tx_buffer_info[first].time_stamp = 0;
5286 tx_ring->next_to_use = first;
5287 }
9a799d71
AK		 5288
5289 return NETDEV_TX_OK;
5290}
5291
5292/**
5293 * ixgbe_get_stats - Get System Network Statistics
5294 * @netdev: network interface device structure
5295 *
5296 * Returns the address of the device statistics structure.
5297 * The statistics are actually updated from the timer callback.
5298 **/
5299static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5300{
5301 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5302
5303 /* only return the current stats */
5304 return &adapter->net_stats;
5305}
5306
5307/**
5308 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5309 * @netdev: network interface device structure
5310 * @p: pointer to an address structure
5311 *
5312 * Returns 0 on success, negative on failure
5313 **/
5314static int ixgbe_set_mac(struct net_device *netdev, void *p)
5315{
5316 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 5317 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5318 struct sockaddr *addr = p;
5319
5320 if (!is_valid_ether_addr(addr->sa_data))
5321 return -EADDRNOTAVAIL;
5322
5323 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 5324 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 5325
b4617240 5326 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 5327
5328 return 0;
5329}
5330
6b73e10d
BH		 5331static int
5332ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5333{
5334 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5335 struct ixgbe_hw *hw = &adapter->hw;
5336 u16 value;
5337 int rc;
5338
5339 if (prtad != hw->phy.mdio.prtad)
5340 return -EINVAL;
5341 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5342 if (!rc)
5343 rc = value;
5344 return rc;
5345}
5346
5347static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5348 u16 addr, u16 value)
5349{
5350 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5351 struct ixgbe_hw *hw = &adapter->hw;
5352
5353 if (prtad != hw->phy.mdio.prtad)
5354 return -EINVAL;
5355 return hw->phy.ops.write_reg(hw, addr, devad, value);
5356}
5357
5358static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5359{
5360 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5361
5362 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5363}
5364
0365e6e4
PW		 5365/**
5366 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 5367 * netdev->dev_addrs
0365e6e4
PW		 5368 * @netdev: network interface device structure
5369 *
5370 * Returns non-zero on failure
5371 **/
5372static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5373{
5374 int err = 0;
5375 struct ixgbe_adapter *adapter = netdev_priv(dev);
5376 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5377
5378 if (is_valid_ether_addr(mac->san_addr)) {
5379 rtnl_lock();
5380 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5381 rtnl_unlock();
5382 }
5383 return err;
5384}
5385
5386/**
5387 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 5388 * netdev->dev_addrs
0365e6e4
PW		 5389 * @netdev: network interface device structure
5390 *
5391 * Returns non-zero on failure
5392 **/
5393static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5394{
5395 int err = 0;
5396 struct ixgbe_adapter *adapter = netdev_priv(dev);
5397 struct ixgbe_mac_info *mac = &adapter->hw.mac;
5398
5399 if (is_valid_ether_addr(mac->san_addr)) {
5400 rtnl_lock();
5401 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5402 rtnl_unlock();
5403 }
5404 return err;
5405}
5406
9a799d71
AK		 5407#ifdef CONFIG_NET_POLL_CONTROLLER
5408/*
5409 * Polling 'interrupt' - used by things like netconsole to send skbs
5410 * without having to re-enable interrupts. It's not called while
5411 * the interrupt routine is executing.
5412 */
5413static void ixgbe_netpoll(struct net_device *netdev)
5414{
5415 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 5416 int i;
9a799d71 5417
9a799d71 5418 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 5419 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5420 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5421 for (i = 0; i < num_q_vectors; i++) {
5422 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5423 ixgbe_msix_clean_many(0, q_vector);
5424 }
5425 } else {
5426 ixgbe_intr(adapter->pdev->irq, netdev);
5427 }
9a799d71 5428 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 5429}
5430#endif
5431
0edc3527
SH		 5432static const struct net_device_ops ixgbe_netdev_ops = {
5433 .ndo_open = ixgbe_open,
5434 .ndo_stop = ixgbe_close,
00829823 5435 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 5436 .ndo_select_queue = ixgbe_select_queue,
0edc3527 5437 .ndo_get_stats = ixgbe_get_stats,
e90d400c 5438 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 5439 .ndo_set_multicast_list = ixgbe_set_rx_mode,
5440 .ndo_validate_addr = eth_validate_addr,
5441 .ndo_set_mac_address = ixgbe_set_mac,
5442 .ndo_change_mtu = ixgbe_change_mtu,
5443 .ndo_tx_timeout = ixgbe_tx_timeout,
5444 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
5445 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
5446 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 5447 .ndo_do_ioctl = ixgbe_ioctl,
0edc3527
SH		 5448#ifdef CONFIG_NET_POLL_CONTROLLER
5449 .ndo_poll_controller = ixgbe_netpoll,
5450#endif
332d4a7d
YZ		 5451#ifdef IXGBE_FCOE
5452 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5453 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 5454 .ndo_fcoe_enable = ixgbe_fcoe_enable,
5455 .ndo_fcoe_disable = ixgbe_fcoe_disable,
332d4a7d 5456#endif /* IXGBE_FCOE */
0edc3527
SH		 5457};
5458
9a799d71
AK		 5459/**
5460 * ixgbe_probe - Device Initialization Routine
5461 * @pdev: PCI device information struct
5462 * @ent: entry in ixgbe_pci_tbl
5463 *
5464 * Returns 0 on success, negative on failure
5465 *
5466 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5467 * The OS initialization, configuring of the adapter private structure,
5468 * and a hardware reset occur.
5469 **/
5470static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 5471 const struct pci_device_id *ent)
9a799d71
AK		 5472{
5473 struct net_device *netdev;
5474 struct ixgbe_adapter *adapter = NULL;
5475 struct ixgbe_hw *hw;
5476 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 5477 static int cards_found;
5478 int i, err, pci_using_dac;
eacd73f7
YZ		 5479#ifdef IXGBE_FCOE
5480 u16 device_caps;
5481#endif
c44ade9e 5482 u32 part_num, eec;
9a799d71 5483
9ce77666 5484 err = pci_enable_device_mem(pdev);
9a799d71
AK		 5485 if (err)
5486 return err;
5487
6a35528a
YH		 5488 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5489 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
9a799d71
AK		 5490 pci_using_dac = 1;
5491 } else {
284901a9 5492 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5493 if (err) {
284901a9 5494 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9a799d71 5495 if (err) {
b4617240
PW		 5496 dev_err(&pdev->dev, "No usable DMA "
5497 "configuration, aborting\n");
9a799d71
AK		 5498 goto err_dma;
5499 }
5500 }
5501 pci_using_dac = 0;
5502 }
5503
9ce77666 5504 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5505 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 5506 if (err) {
9ce77666 5507 dev_err(&pdev->dev,
5508 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 5509 goto err_pci_reg;
5510 }
5511
19d5afd4 5512 pci_enable_pcie_error_reporting(pdev);
6fabd715 5513
9a799d71 5514 pci_set_master(pdev);
fb3b27bc 5515 pci_save_state(pdev);
9a799d71 5516
30eba97a 5517 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 5518 if (!netdev) {
5519 err = -ENOMEM;
5520 goto err_alloc_etherdev;
5521 }
5522
9a799d71
AK		 5523 SET_NETDEV_DEV(netdev, &pdev->dev);
5524
5525 pci_set_drvdata(pdev, netdev);
5526 adapter = netdev_priv(netdev);
5527
5528 adapter->netdev = netdev;
5529 adapter->pdev = pdev;
5530 hw = &adapter->hw;
5531 hw->back = adapter;
5532 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5533
05857980
JK		 5534 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5535 pci_resource_len(pdev, 0));
9a799d71
AK		 5536 if (!hw->hw_addr) {
5537 err = -EIO;
5538 goto err_ioremap;
5539 }
5540
5541 for (i = 1; i <= 5; i++) {
5542 if (pci_resource_len(pdev, i) == 0)
5543 continue;
5544 }
5545
0edc3527 5546 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 5547 ixgbe_set_ethtool_ops(netdev);
9a799d71 5548 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 5549 strcpy(netdev->name, pci_name(pdev));
5550
9a799d71
AK		 5551 adapter->bd_number = cards_found;
5552
9a799d71
AK		 5553 /* Setup hw api */
5554 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 5555 hw->mac.type = ii->mac;
9a799d71 5556
c44ade9e
JB		 5557 /* EEPROM */
5558 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5559 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5560 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5561 if (!(eec & (1 << 8)))
5562 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5563
5564 /* PHY */
5565 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 5566 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 5567 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5568 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5569 hw->phy.mdio.mmds = 0;
5570 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5571 hw->phy.mdio.dev = netdev;
5572 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5573 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0
DS		 5574
5575 /* set up this timer and work struct before calling get_invariants
5576 * which might start the timer
5577 */
5578 init_timer(&adapter->sfp_timer);
5579 adapter->sfp_timer.function = &ixgbe_sfp_timer;
5580 adapter->sfp_timer.data = (unsigned long) adapter;
5581
5582 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
c44ade9e 5583
e8e26350
PW		 5584 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5585 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5586
5587 /* a new SFP+ module arrival, called from GPI SDP2 context */
5588 INIT_WORK(&adapter->sfp_config_module_task,
5589 ixgbe_sfp_config_module_task);
5590
8ca783ab 5591 ii->get_invariants(hw);
9a799d71
AK		 5592
5593 /* setup the private structure */
5594 err = ixgbe_sw_init(adapter);
5595 if (err)
5596 goto err_sw_init;
5597
bf069c97
DS		 5598 /*
5599 * If there is a fan on this device and it has failed log the
5600 * failure.
5601 */
5602 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5603 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5604 if (esdp & IXGBE_ESDP_SDP1)
5605 DPRINTK(PROBE, CRIT,
5606 "Fan has stopped, replace the adapter\n");
5607 }
5608
c44ade9e
JB		 5609 /* reset_hw fills in the perm_addr as well */
5610 err = hw->mac.ops.reset_hw(hw);
8ca783ab
DS		 5611 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5612 hw->mac.type == ixgbe_mac_82598EB) {
5613 /*
5614 * Start a kernel thread to watch for a module to arrive.
5615 * Only do this for 82598, since 82599 will generate
5616 * interrupts on module arrival.
5617 */
5618 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5619 mod_timer(&adapter->sfp_timer,
5620 round_jiffies(jiffies + (2 * HZ)));
5621 err = 0;
5622 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
88d2b81f
DS		 5623 dev_err(&adapter->pdev->dev, "failed to initialize because "
5624 "an unsupported SFP+ module type was detected.\n"
5625 "Reload the driver after installing a supported "
5626 "module.\n");
04f165ef
PW		 5627 goto err_sw_init;
5628 } else if (err) {
c44ade9e
JB		 5629 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5630 goto err_sw_init;
5631 }
5632
9a799d71 5633 netdev->features = NETIF_F_SG |
b4617240
PW		 5634 NETIF_F_IP_CSUM |
5635 NETIF_F_HW_VLAN_TX |
5636 NETIF_F_HW_VLAN_RX |
5637 NETIF_F_HW_VLAN_FILTER;
9a799d71 5638
e9990a9c 5639 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 5640 netdev->features |= NETIF_F_TSO;
9a799d71 5641 netdev->features |= NETIF_F_TSO6;
78b6f4ce 5642 netdev->features |= NETIF_F_GRO;
ad31c402 5643
45a5ead0
JB		 5644 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5645 netdev->features |= NETIF_F_SCTP_CSUM;
5646
ad31c402
JK		 5647 netdev->vlan_features |= NETIF_F_TSO;
5648 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 5649 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 5650 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 5651 netdev->vlan_features |= NETIF_F_SG;
5652
2f90b865
AD		 5653 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5654 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5655
7a6b6f51 5656#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5657 netdev->dcbnl_ops = &dcbnl_ops;
5658#endif
5659
eacd73f7 5660#ifdef IXGBE_FCOE
0d551589 5661 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 5662 if (hw->mac.ops.get_device_caps) {
5663 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 5664 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5665 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 5666 }
5667 }
5668#endif /* IXGBE_FCOE */
9a799d71
AK		 5669 if (pci_using_dac)
5670 netdev->features |= NETIF_F_HIGHDMA;
5671
0c19d6af 5672 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 5673 netdev->features |= NETIF_F_LRO;
5674
9a799d71 5675 /* make sure the EEPROM is good */
c44ade9e 5676 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 5677 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5678 err = -EIO;
5679 goto err_eeprom;
5680 }
5681
5682 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5683 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5684
c44ade9e
JB		 5685 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5686 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 5687 err = -EIO;
5688 goto err_eeprom;
5689 }
5690
5691 init_timer(&adapter->watchdog_timer);
5692 adapter->watchdog_timer.function = &ixgbe_watchdog;
5693 adapter->watchdog_timer.data = (unsigned long)adapter;
5694
5695 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 5696 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 5697
021230d4
AV		 5698 err = ixgbe_init_interrupt_scheme(adapter);
5699 if (err)
5700 goto err_sw_init;
9a799d71 5701
e8e26350
PW		 5702 switch (pdev->device) {
5703 case IXGBE_DEV_ID_82599_KX4:
495dce12
WJP		 5704 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5705 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
bdf0a550
PWJ		 5706 /* Enable ACPI wakeup in GRC */
5707 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5708 (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
e8e26350
PW		 5709 break;
5710 default:
5711 adapter->wol = 0;
5712 break;
5713 }
e8e26350
PW		 5714 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5715
04f165ef
PW		 5716 /* pick up the PCI bus settings for reporting later */
5717 hw->mac.ops.get_bus_info(hw);
5718
9a799d71 5719 /* print bus type/speed/width info */
7c510e4b 5720 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
e8e26350
PW		 5721 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5722 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5723 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5724 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5725 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
b4617240 5726 "Unknown"),
7c510e4b 5727 netdev->dev_addr);
c44ade9e 5728 ixgbe_read_pba_num_generic(hw, &part_num);
e8e26350
PW		 5729 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5730 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5731 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5732 (part_num >> 8), (part_num & 0xff));
5733 else
5734 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5735 hw->mac.type, hw->phy.type,
5736 (part_num >> 8), (part_num & 0xff));
9a799d71 5737
e8e26350 5738 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
0c254d86 5739 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 5740 "this card is not sufficient for optimal "
5741 "performance.\n");
0c254d86 5742 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 5743 "PCI-Express slot is required.\n");
0c254d86
AK		 5744 }
5745
34b0368c
PWJ		 5746 /* save off EEPROM version number */
5747 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5748
9a799d71 5749 /* reset the hardware with the new settings */
794caeb2 5750 err = hw->mac.ops.start_hw(hw);
c44ade9e 5751
794caeb2
PWJ		 5752 if (err == IXGBE_ERR_EEPROM_VERSION) {
5753 /* We are running on a pre-production device, log a warning */
5754 dev_warn(&pdev->dev, "This device is a pre-production "
5755 "adapter/LOM. Please be aware there may be issues "
5756 "associated with your hardware. If you are "
5757 "experiencing problems please contact your Intel or "
5758 "hardware representative who provided you with this "
5759 "hardware.\n");
5760 }
9a799d71
AK		 5761 strcpy(netdev->name, "eth%d");
5762 err = register_netdev(netdev);
5763 if (err)
5764 goto err_register;
5765
54386467
JB		 5766 /* carrier off reporting is important to ethtool even BEFORE open */
5767 netif_carrier_off(netdev);
5768
c4cf55e5
PWJ		 5769 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5770 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5771 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5772
5dd2d332 5773#ifdef CONFIG_IXGBE_DCA
652f093f 5774 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 5775 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 5776 ixgbe_setup_dca(adapter);
5777 }
5778#endif
0365e6e4
PW		 5779 /* add san mac addr to netdev */
5780 ixgbe_add_sanmac_netdev(netdev);
9a799d71
AK		 5781
5782 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5783 cards_found++;
5784 return 0;
5785
5786err_register:
5eba3699 5787 ixgbe_release_hw_control(adapter);
7a921c93 5788 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 5789err_sw_init:
5790err_eeprom:
c4900be0
DS		 5791 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5792 del_timer_sync(&adapter->sfp_timer);
5793 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5794 cancel_work_sync(&adapter->multispeed_fiber_task);
5795 cancel_work_sync(&adapter->sfp_config_module_task);
9a799d71
AK		 5796 iounmap(hw->hw_addr);
5797err_ioremap:
5798 free_netdev(netdev);
5799err_alloc_etherdev:
9ce77666 5800 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5801 IORESOURCE_MEM));
9a799d71
AK		 5802err_pci_reg:
5803err_dma:
5804 pci_disable_device(pdev);
5805 return err;
5806}
5807
5808/**
5809 * ixgbe_remove - Device Removal Routine
5810 * @pdev: PCI device information struct
5811 *
5812 * ixgbe_remove is called by the PCI subsystem to alert the driver
5813 * that it should release a PCI device. The could be caused by a
5814 * Hot-Plug event, or because the driver is going to be removed from
5815 * memory.
5816 **/
5817static void __devexit ixgbe_remove(struct pci_dev *pdev)
5818{
5819 struct net_device *netdev = pci_get_drvdata(pdev);
5820 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5821
5822 set_bit(__IXGBE_DOWN, &adapter->state);
c4900be0
DS		 5823 /* clear the module not found bit to make sure the worker won't
5824 * reschedule
5825 */
5826 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
9a799d71
AK		 5827 del_timer_sync(&adapter->watchdog_timer);
5828
c4900be0
DS		 5829 del_timer_sync(&adapter->sfp_timer);
5830 cancel_work_sync(&adapter->watchdog_task);
5831 cancel_work_sync(&adapter->sfp_task);
e8e26350
PW		 5832 cancel_work_sync(&adapter->multispeed_fiber_task);
5833 cancel_work_sync(&adapter->sfp_config_module_task);
c4cf55e5
PWJ		 5834 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5835 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5836 cancel_work_sync(&adapter->fdir_reinit_task);
9a799d71
AK		 5837 flush_scheduled_work();
5838
5dd2d332 5839#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 5840 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5841 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5842 dca_remove_requester(&pdev->dev);
5843 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5844 }
5845
5846#endif
332d4a7d
YZ		 5847#ifdef IXGBE_FCOE
5848 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5849 ixgbe_cleanup_fcoe(adapter);
5850
5851#endif /* IXGBE_FCOE */
0365e6e4
PW		 5852
5853 /* remove the added san mac */
5854 ixgbe_del_sanmac_netdev(netdev);
5855
c4900be0
DS		 5856 if (netdev->reg_state == NETREG_REGISTERED)
5857 unregister_netdev(netdev);
9a799d71 5858
7a921c93 5859 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 5860
021230d4 5861 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5862
5863 iounmap(adapter->hw.hw_addr);
9ce77666 5864 pci_release_selected_regions(pdev, pci_select_bars(pdev,
5865 IORESOURCE_MEM));
9a799d71 5866
021230d4 5867 DPRINTK(PROBE, INFO, "complete\n");
021230d4 5868
9a799d71
AK		 5869 free_netdev(netdev);
5870
19d5afd4 5871 pci_disable_pcie_error_reporting(pdev);
6fabd715 5872
9a799d71
AK		 5873 pci_disable_device(pdev);
5874}
5875
5876/**
5877 * ixgbe_io_error_detected - called when PCI error is detected
5878 * @pdev: Pointer to PCI device
5879 * @state: The current pci connection state
5880 *
5881 * This function is called after a PCI bus error affecting
5882 * this device has been detected.
5883 */
5884static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 5885 pci_channel_state_t state)
9a799d71
AK		 5886{
5887 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5888 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5889
5890 netif_device_detach(netdev);
5891
3044b8d1
BL		 5892 if (state == pci_channel_io_perm_failure)
5893 return PCI_ERS_RESULT_DISCONNECT;
5894
9a799d71
AK		 5895 if (netif_running(netdev))
5896 ixgbe_down(adapter);
5897 pci_disable_device(pdev);
5898
b4617240 5899 /* Request a slot reset. */
9a799d71
AK		 5900 return PCI_ERS_RESULT_NEED_RESET;
5901}
5902
5903/**
5904 * ixgbe_io_slot_reset - called after the pci bus has been reset.
5905 * @pdev: Pointer to PCI device
5906 *
5907 * Restart the card from scratch, as if from a cold-boot.
5908 */
5909static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5910{
5911 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5912 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6fabd715
PWJ		 5913 pci_ers_result_t result;
5914 int err;
9a799d71 5915
9ce77666 5916 if (pci_enable_device_mem(pdev)) {
9a799d71 5917 DPRINTK(PROBE, ERR,
b4617240 5918 "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 5919 result = PCI_ERS_RESULT_DISCONNECT;
5920 } else {
5921 pci_set_master(pdev);
5922 pci_restore_state(pdev);
9a799d71 5923
dd4d8ca6 5924 pci_wake_from_d3(pdev, false);
9a799d71 5925
6fabd715 5926 ixgbe_reset(adapter);
88512539 5927 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 5928 result = PCI_ERS_RESULT_RECOVERED;
5929 }
5930
5931 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5932 if (err) {
5933 dev_err(&pdev->dev,
5934 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5935 /* non-fatal, continue */
5936 }
9a799d71 5937
6fabd715 5938 return result;
9a799d71
AK		 5939}
5940
5941/**
5942 * ixgbe_io_resume - called when traffic can start flowing again.
5943 * @pdev: Pointer to PCI device
5944 *
5945 * This callback is called when the error recovery driver tells us that
5946 * its OK to resume normal operation.
5947 */
5948static void ixgbe_io_resume(struct pci_dev *pdev)
5949{
5950 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 5951 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5952
5953 if (netif_running(netdev)) {
5954 if (ixgbe_up(adapter)) {
5955 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5956 return;
5957 }
5958 }
5959
5960 netif_device_attach(netdev);
9a799d71
AK		 5961}
5962
5963static struct pci_error_handlers ixgbe_err_handler = {
5964 .error_detected = ixgbe_io_error_detected,
5965 .slot_reset = ixgbe_io_slot_reset,
5966 .resume = ixgbe_io_resume,
5967};
5968
5969static struct pci_driver ixgbe_driver = {
5970 .name = ixgbe_driver_name,
5971 .id_table = ixgbe_pci_tbl,
5972 .probe = ixgbe_probe,
5973 .remove = __devexit_p(ixgbe_remove),
5974#ifdef CONFIG_PM
5975 .suspend = ixgbe_suspend,
5976 .resume = ixgbe_resume,
5977#endif
5978 .shutdown = ixgbe_shutdown,
5979 .err_handler = &ixgbe_err_handler
5980};
5981
5982/**
5983 * ixgbe_init_module - Driver Registration Routine
5984 *
5985 * ixgbe_init_module is the first routine called when the driver is
5986 * loaded. All it does is register with the PCI subsystem.
5987 **/
5988static int __init ixgbe_init_module(void)
5989{
5990 int ret;
5991 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5992 ixgbe_driver_string, ixgbe_driver_version);
5993
5994 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5995
5dd2d332 5996#ifdef CONFIG_IXGBE_DCA
bd0362dd 5997 dca_register_notify(&dca_notifier);
bd0362dd 5998#endif
5dd2d332 5999
9a799d71
AK		 6000 ret = pci_register_driver(&ixgbe_driver);
6001 return ret;
6002}
b4617240 6003
9a799d71
AK		 6004module_init(ixgbe_init_module);
6005
6006/**
6007 * ixgbe_exit_module - Driver Exit Cleanup Routine
6008 *
6009 * ixgbe_exit_module is called just before the driver is removed
6010 * from memory.
6011 **/
6012static void __exit ixgbe_exit_module(void)
6013{
5dd2d332 6014#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 6015 dca_unregister_notify(&dca_notifier);
6016#endif
9a799d71
AK		 6017 pci_unregister_driver(&ixgbe_driver);
6018}
bd0362dd 6019
5dd2d332 6020#ifdef CONFIG_IXGBE_DCA
bd0362dd 6021static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 6022 void *p)
bd0362dd
JC		 6023{
6024 int ret_val;
6025
6026 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 6027 __ixgbe_notify_dca);
bd0362dd
JC		 6028
6029 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6030}
b453368d 6031
5dd2d332 6032#endif /* CONFIG_IXGBE_DCA */
b453368d
AD		 6033#ifdef DEBUG
6034/**
6035 * ixgbe_get_hw_dev_name - return device name string
6036 * used by hardware layer to print debugging information
6037 **/
6038char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6039{
6040 struct ixgbe_adapter *adapter = hw->back;
6041 return adapter->netdev->name;
6042}
bd0362dd 6043
b453368d 6044#endif
9a799d71
AK		 6045module_exit(ixgbe_exit_module);
6046
6047/* ixgbe_main.c */
Linux 6.x block layer and io_uring tree(s)