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net: remove interrupt.h inclusion from netdevice.h
[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for ixgbe */
29
a6b7a407 30#include <linux/interrupt.h>
9a799d71
AK		 31#include <linux/types.h>
32#include <linux/module.h>
5a0e3ad6 33#include <linux/slab.h>
9a799d71
AK		 34#include <linux/pci.h>
35#include <linux/netdevice.h>
36#include <linux/ethtool.h>
37#include <linux/vmalloc.h>
38#include <linux/uaccess.h>
39
40#include "ixgbe.h"
41
42
43#define IXGBE_ALL_RAR_ENTRIES 16
44
29c3a050
AK		 45enum {NETDEV_STATS, IXGBE_STATS};
46
9a799d71
AK		 47struct ixgbe_stats {
48 char stat_string[ETH_GSTRING_LEN];
29c3a050 49 int type;
9a799d71
AK		 50 int sizeof_stat;
51 int stat_offset;
52};
53
29c3a050
AK		 54#define IXGBE_STAT(m) IXGBE_STATS, \
55 sizeof(((struct ixgbe_adapter *)0)->m), \
56 offsetof(struct ixgbe_adapter, m)
57#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
55bad823
ED		 58 sizeof(((struct rtnl_link_stats64 *)0)->m), \
59 offsetof(struct rtnl_link_stats64, m)
29c3a050 60
9a799d71 61static struct ixgbe_stats ixgbe_gstrings_stats[] = {
55bad823
ED		 62 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
63 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
64 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
65 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
aad71918
BG		 66 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
67 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
68 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
69 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
9a799d71
AK		 70 {"lsc_int", IXGBE_STAT(lsc_int)},
71 {"tx_busy", IXGBE_STAT(tx_busy)},
72 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
55bad823
ED		 73 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
74 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
75 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
76 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
77 {"multicast", IXGBE_NETDEV_STAT(multicast)},
9a799d71
AK		 78 {"broadcast", IXGBE_STAT(stats.bprc)},
79 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
55bad823
ED		 80 {"collisions", IXGBE_NETDEV_STAT(collisions)},
81 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
82 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
83 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
94b982b2
MC		 84 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
85 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
c4cf55e5
PWJ		 86 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
87 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
d034acf1 88 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
55bad823
ED		 89 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
90 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
91 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
92 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
93 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
94 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
9a799d71
AK		 95 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
96 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
97 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
98 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
9a799d71
AK		 99 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
100 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
101 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
102 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
9a799d71 103 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
9a799d71
AK		 104 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
105 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 106 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
58f6bcf9
ET		 107 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
108 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
109 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
110 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
6d45522c
YZ		 111#ifdef IXGBE_FCOE
112 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
113 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
114 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
115 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
116 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
117 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
118#endif /* IXGBE_FCOE */
9a799d71
AK		 119};
120
121#define IXGBE_QUEUE_STATS_LEN \
454d7c9b
WC		 122 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
123 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
124 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 125#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 126#define IXGBE_PB_STATS_LEN ( \
9d2f4720 127 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
2f90b865
AD		 128 IXGBE_FLAG_DCB_ENABLED) ? \
129 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
130 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
131 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
132 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
133 / sizeof(u64) : 0)
134#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
135 IXGBE_PB_STATS_LEN + \
136 IXGBE_QUEUE_STATS_LEN)
9a799d71 137
da4dd0f7
PWJ		 138static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
139 "Register test (offline)", "Eeprom test (offline)",
140 "Interrupt test (offline)", "Loopback test (offline)",
141 "Link test (on/offline)"
142};
143#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
144
9a799d71 145static int ixgbe_get_settings(struct net_device *netdev,
b4617240 146 struct ethtool_cmd *ecmd)
9a799d71
AK		 147{
148 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb
AV		 149 struct ixgbe_hw *hw = &adapter->hw;
150 u32 link_speed = 0;
151 bool link_up;
9a799d71 152
735441fb
AV		 153 ecmd->supported = SUPPORTED_10000baseT_Full;
154 ecmd->autoneg = AUTONEG_ENABLE;
9a799d71 155 ecmd->transceiver = XCVR_EXTERNAL;
74766013 156 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 157 (hw->phy.multispeed_fiber)) {
735441fb 158 ecmd->supported |= (SUPPORTED_1000baseT_Full |
74766013 159 SUPPORTED_Autoneg);
735441fb 160
1b1c0a48
AS		 161 switch (hw->mac.type) {
162 case ixgbe_mac_X540:
163 ecmd->supported |= SUPPORTED_100baseT_Full;
164 break;
165 default:
166 break;
167 }
168
74766013 169 ecmd->advertising = ADVERTISED_Autoneg;
2b642ca5
ET		 170 if (hw->phy.autoneg_advertised) {
171 if (hw->phy.autoneg_advertised &
172 IXGBE_LINK_SPEED_100_FULL)
173 ecmd->advertising |= ADVERTISED_100baseT_Full;
174 if (hw->phy.autoneg_advertised &
175 IXGBE_LINK_SPEED_10GB_FULL)
176 ecmd->advertising |= ADVERTISED_10000baseT_Full;
177 if (hw->phy.autoneg_advertised &
178 IXGBE_LINK_SPEED_1GB_FULL)
179 ecmd->advertising |= ADVERTISED_1000baseT_Full;
180 } else {
181 /*
182 * Default advertised modes in case
183 * phy.autoneg_advertised isn't set.
184 */
7c5b8323
DS		 185 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
186 ADVERTISED_1000baseT_Full);
2b642ca5
ET		 187 if (hw->mac.type == ixgbe_mac_X540)
188 ecmd->advertising |= ADVERTISED_100baseT_Full;
1b1c0a48
AS		 189 }
190
74766013
MC		 191 if (hw->phy.media_type == ixgbe_media_type_copper) {
192 ecmd->supported |= SUPPORTED_TP;
193 ecmd->advertising |= ADVERTISED_TP;
194 ecmd->port = PORT_TP;
195 } else {
196 ecmd->supported |= SUPPORTED_FIBRE;
197 ecmd->advertising |= ADVERTISED_FIBRE;
198 ecmd->port = PORT_FIBRE;
199 }
1e336d0f
DS		 200 } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
201 /* Set as FIBRE until SERDES defined in kernel */
46a72b35 202 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
2f21bdd3
DS		 203 ecmd->supported = (SUPPORTED_1000baseT_Full |
204 SUPPORTED_FIBRE);
205 ecmd->advertising = (ADVERTISED_1000baseT_Full |
206 ADVERTISED_FIBRE);
207 ecmd->port = PORT_FIBRE;
208 ecmd->autoneg = AUTONEG_DISABLE;
50d6c681
AD		 209 } else if ((hw->device_id == IXGBE_DEV_ID_82599_COMBO_BACKPLANE) ||
210 (hw->device_id == IXGBE_DEV_ID_82599_KX4_MEZZ)) {
211 ecmd->supported |= (SUPPORTED_1000baseT_Full |
212 SUPPORTED_Autoneg |
213 SUPPORTED_FIBRE);
214 ecmd->advertising = (ADVERTISED_10000baseT_Full |
215 ADVERTISED_1000baseT_Full |
216 ADVERTISED_Autoneg |
217 ADVERTISED_FIBRE);
218 ecmd->port = PORT_FIBRE;
46a72b35
MC		 219 } else {
220 ecmd->supported |= (SUPPORTED_1000baseT_Full |
221 SUPPORTED_FIBRE);
222 ecmd->advertising = (ADVERTISED_10000baseT_Full |
223 ADVERTISED_1000baseT_Full |
224 ADVERTISED_FIBRE);
225 ecmd->port = PORT_FIBRE;
1e336d0f 226 }
735441fb
AV		 227 } else {
228 ecmd->supported |= SUPPORTED_FIBRE;
229 ecmd->advertising = (ADVERTISED_10000baseT_Full |
b4617240 230 ADVERTISED_FIBRE);
735441fb 231 ecmd->port = PORT_FIBRE;
c44ade9e 232 ecmd->autoneg = AUTONEG_DISABLE;
735441fb 233 }
9a799d71 234
3b8626ba
PW		 235 /* Get PHY type */
236 switch (adapter->hw.phy.type) {
237 case ixgbe_phy_tn:
fe15e8e1 238 case ixgbe_phy_aq:
3b8626ba
PW		 239 case ixgbe_phy_cu_unknown:
240 /* Copper 10G-BASET */
241 ecmd->port = PORT_TP;
242 break;
243 case ixgbe_phy_qt:
244 ecmd->port = PORT_FIBRE;
245 break;
246 case ixgbe_phy_nl:
ea0a04df
DS		 247 case ixgbe_phy_sfp_passive_tyco:
248 case ixgbe_phy_sfp_passive_unknown:
3b8626ba
PW		 249 case ixgbe_phy_sfp_ftl:
250 case ixgbe_phy_sfp_avago:
251 case ixgbe_phy_sfp_intel:
252 case ixgbe_phy_sfp_unknown:
253 switch (adapter->hw.phy.sfp_type) {
254 /* SFP+ devices, further checking needed */
255 case ixgbe_sfp_type_da_cu:
256 case ixgbe_sfp_type_da_cu_core0:
257 case ixgbe_sfp_type_da_cu_core1:
258 ecmd->port = PORT_DA;
259 break;
260 case ixgbe_sfp_type_sr:
261 case ixgbe_sfp_type_lr:
262 case ixgbe_sfp_type_srlr_core0:
263 case ixgbe_sfp_type_srlr_core1:
264 ecmd->port = PORT_FIBRE;
265 break;
266 case ixgbe_sfp_type_not_present:
267 ecmd->port = PORT_NONE;
268 break;
cb836a97
DS		 269 case ixgbe_sfp_type_1g_cu_core0:
270 case ixgbe_sfp_type_1g_cu_core1:
271 ecmd->port = PORT_TP;
272 ecmd->supported = SUPPORTED_TP;
273 ecmd->advertising = (ADVERTISED_1000baseT_Full |
274 ADVERTISED_TP);
275 break;
3b8626ba
PW		 276 case ixgbe_sfp_type_unknown:
277 default:
278 ecmd->port = PORT_OTHER;
279 break;
280 }
281 break;
282 case ixgbe_phy_xaui:
283 ecmd->port = PORT_NONE;
284 break;
285 case ixgbe_phy_unknown:
286 case ixgbe_phy_generic:
287 case ixgbe_phy_sfp_unsupported:
288 default:
289 ecmd->port = PORT_OTHER;
290 break;
291 }
292
c44ade9e 293 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
735441fb 294 if (link_up) {
1b1c0a48
AS		 295 switch (link_speed) {
296 case IXGBE_LINK_SPEED_10GB_FULL:
70739497 297 ethtool_cmd_speed_set(ecmd, SPEED_10000);
1b1c0a48
AS		 298 break;
299 case IXGBE_LINK_SPEED_1GB_FULL:
70739497 300 ethtool_cmd_speed_set(ecmd, SPEED_1000);
1b1c0a48
AS		 301 break;
302 case IXGBE_LINK_SPEED_100_FULL:
70739497 303 ethtool_cmd_speed_set(ecmd, SPEED_100);
1b1c0a48
AS		 304 break;
305 default:
306 break;
307 }
9a799d71
AK		 308 ecmd->duplex = DUPLEX_FULL;
309 } else {
70739497 310 ethtool_cmd_speed_set(ecmd, -1);
9a799d71
AK		 311 ecmd->duplex = -1;
312 }
313
9a799d71
AK		 314 return 0;
315}
316
317static int ixgbe_set_settings(struct net_device *netdev,
b4617240 318 struct ethtool_cmd *ecmd)
9a799d71
AK		 319{
320 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 321 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e 322 u32 advertised, old;
74766013 323 s32 err = 0;
9a799d71 324
74766013 325 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 326 (hw->phy.multispeed_fiber)) {
0befdb3e
JB		 327 /* 10000/copper and 1000/copper must autoneg
328 * this function does not support any duplex forcing, but can
329 * limit the advertising of the adapter to only 10000 or 1000 */
330 if (ecmd->autoneg == AUTONEG_DISABLE)
331 return -EINVAL;
332
333 old = hw->phy.autoneg_advertised;
334 advertised = 0;
335 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
336 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
337
338 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
339 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
340
2b642ca5
ET		 341 if (ecmd->advertising & ADVERTISED_100baseT_Full)
342 advertised |= IXGBE_LINK_SPEED_100_FULL;
343
0befdb3e 344 if (old == advertised)
74766013 345 return err;
0befdb3e 346 /* this sets the link speed and restarts auto-neg */
74766013 347 hw->mac.autotry_restart = true;
8620a103 348 err = hw->mac.ops.setup_link(hw, advertised, true, true);
0befdb3e 349 if (err) {
396e799c 350 e_info(probe, "setup link failed with code %d\n", err);
8620a103 351 hw->mac.ops.setup_link(hw, old, true, true);
0befdb3e 352 }
74766013
MC		 353 } else {
354 /* in this case we currently only support 10Gb/FULL */
25db0338 355 u32 speed = ethtool_cmd_speed(ecmd);
74766013 356 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
a3801379 357 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
25db0338 358 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
74766013 359 return -EINVAL;
9a799d71
AK		 360 }
361
74766013 362 return err;
9a799d71
AK		 363}
364
365static void ixgbe_get_pauseparam(struct net_device *netdev,
b4617240 366 struct ethtool_pauseparam *pause)
9a799d71
AK		 367{
368 struct ixgbe_adapter *adapter = netdev_priv(netdev);
369 struct ixgbe_hw *hw = &adapter->hw;
370
71fd570b
DS		 371 /*
372 * Flow Control Autoneg isn't on if
373 * - we didn't ask for it OR
374 * - it failed, we know this by tx & rx being off
375 */
376 if (hw->fc.disable_fc_autoneg ||
377 (hw->fc.current_mode == ixgbe_fc_none))
378 pause->autoneg = 0;
379 else
380 pause->autoneg = 1;
9a799d71 381
0ecc061d 382 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 383 pause->rx_pause = 1;
0ecc061d 384 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 385 pause->tx_pause = 1;
0ecc061d 386 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 387 pause->rx_pause = 1;
388 pause->tx_pause = 1;
673ac604
AD		 389#ifdef CONFIG_DCB
390 } else if (hw->fc.current_mode == ixgbe_fc_pfc) {
391 pause->rx_pause = 0;
392 pause->tx_pause = 0;
393#endif
9a799d71
AK		 394 }
395}
396
397static int ixgbe_set_pauseparam(struct net_device *netdev,
b4617240 398 struct ethtool_pauseparam *pause)
9a799d71
AK		 399{
400 struct ixgbe_adapter *adapter = netdev_priv(netdev);
401 struct ixgbe_hw *hw = &adapter->hw;
620fa036 402 struct ixgbe_fc_info fc;
9a799d71 403
264857b8
PWJ		 404#ifdef CONFIG_DCB
405 if (adapter->dcb_cfg.pfc_mode_enable ||
406 ((hw->mac.type == ixgbe_mac_82598EB) &&
407 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
408 return -EINVAL;
409
410#endif
620fa036
MC		 411 fc = hw->fc;
412
71fd570b 413 if (pause->autoneg != AUTONEG_ENABLE)
620fa036 414 fc.disable_fc_autoneg = true;
71fd570b 415 else
620fa036 416 fc.disable_fc_autoneg = false;
71fd570b 417
1c4f0ef8 418 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
620fa036 419 fc.requested_mode = ixgbe_fc_full;
9a799d71 420 else if (pause->rx_pause && !pause->tx_pause)
620fa036 421 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 422 else if (!pause->rx_pause && pause->tx_pause)
620fa036 423 fc.requested_mode = ixgbe_fc_tx_pause;
9a799d71 424 else if (!pause->rx_pause && !pause->tx_pause)
620fa036 425 fc.requested_mode = ixgbe_fc_none;
9c83b070
AV		 426 else
427 return -EINVAL;
9a799d71 428
264857b8 429#ifdef CONFIG_DCB
620fa036 430 adapter->last_lfc_mode = fc.requested_mode;
264857b8 431#endif
620fa036
MC		 432
433 /* if the thing changed then we'll update and use new autoneg */
434 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
435 hw->fc = fc;
436 if (netif_running(netdev))
437 ixgbe_reinit_locked(adapter);
438 else
439 ixgbe_reset(adapter);
440 }
9a799d71
AK		 441
442 return 0;
443}
444
445static u32 ixgbe_get_rx_csum(struct net_device *netdev)
446{
447 struct ixgbe_adapter *adapter = netdev_priv(netdev);
807540ba 448 return adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED;
9a799d71
AK		 449}
450
451static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
452{
453 struct ixgbe_adapter *adapter = netdev_priv(netdev);
454 if (data)
455 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
456 else
457 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
458
9a799d71
AK		 459 return 0;
460}
461
462static u32 ixgbe_get_tx_csum(struct net_device *netdev)
463{
22f32b7a 464 return (netdev->features & NETIF_F_IP_CSUM) != 0;
9a799d71
AK		 465}
466
467static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
468{
45a5ead0 469 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b93a2226 470 u32 feature_list;
45a5ead0 471
b93a2226
DS		 472 feature_list = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
473 switch (adapter->hw.mac.type) {
474 case ixgbe_mac_82599EB:
475 case ixgbe_mac_X540:
476 feature_list |= NETIF_F_SCTP_CSUM;
477 break;
478 default:
479 break;
45a5ead0 480 }
b93a2226
DS		 481 if (data)
482 netdev->features |= feature_list;
483 else
484 netdev->features &= ~feature_list;
9a799d71
AK		 485
486 return 0;
487}
488
489static int ixgbe_set_tso(struct net_device *netdev, u32 data)
490{
9a799d71
AK		 491 if (data) {
492 netdev->features |= NETIF_F_TSO;
493 netdev->features |= NETIF_F_TSO6;
494 } else {
495 netdev->features &= ~NETIF_F_TSO;
496 netdev->features &= ~NETIF_F_TSO6;
497 }
498 return 0;
499}
500
501static u32 ixgbe_get_msglevel(struct net_device *netdev)
502{
503 struct ixgbe_adapter *adapter = netdev_priv(netdev);
504 return adapter->msg_enable;
505}
506
507static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
508{
509 struct ixgbe_adapter *adapter = netdev_priv(netdev);
510 adapter->msg_enable = data;
511}
512
513static int ixgbe_get_regs_len(struct net_device *netdev)
514{
515#define IXGBE_REGS_LEN 1128
516 return IXGBE_REGS_LEN * sizeof(u32);
517}
518
519#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
520
521static void ixgbe_get_regs(struct net_device *netdev,
b4617240 522 struct ethtool_regs *regs, void *p)
9a799d71
AK		 523{
524 struct ixgbe_adapter *adapter = netdev_priv(netdev);
525 struct ixgbe_hw *hw = &adapter->hw;
526 u32 *regs_buff = p;
527 u8 i;
528
529 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
530
531 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
532
533 /* General Registers */
534 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
535 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
536 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
537 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
538 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
539 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
540 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
541 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
542
543 /* NVM Register */
544 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
545 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
546 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
547 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
548 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
549 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
550 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
551 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
552 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
553 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
554
555 /* Interrupt */
98c00a1c
JB		 556 /* don't read EICR because it can clear interrupt causes, instead
557 * read EICS which is a shadow but doesn't clear EICR */
558 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 559 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
560 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
561 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
562 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
563 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
564 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
565 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
566 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
567 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 568 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 569 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
570
571 /* Flow Control */
572 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
573 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
574 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
575 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
576 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
bd508178
AD		 577 for (i = 0; i < 8; i++) {
578 switch (hw->mac.type) {
579 case ixgbe_mac_82598EB:
580 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
581 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
582 break;
583 case ixgbe_mac_82599EB:
584 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
585 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
586 break;
587 default:
588 break;
589 }
590 }
9a799d71
AK		 591 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
592 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
593
594 /* Receive DMA */
595 for (i = 0; i < 64; i++)
596 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
597 for (i = 0; i < 64; i++)
598 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
599 for (i = 0; i < 64; i++)
600 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
601 for (i = 0; i < 64; i++)
602 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
603 for (i = 0; i < 64; i++)
604 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
605 for (i = 0; i < 64; i++)
606 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
607 for (i = 0; i < 16; i++)
608 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
609 for (i = 0; i < 16; i++)
610 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
611 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
612 for (i = 0; i < 8; i++)
613 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
614 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
615 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
616
617 /* Receive */
618 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
619 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
620 for (i = 0; i < 16; i++)
621 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
622 for (i = 0; i < 16; i++)
623 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 624 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 625 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
626 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
627 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
628 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
629 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
630 for (i = 0; i < 8; i++)
631 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
632 for (i = 0; i < 8; i++)
633 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
634 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
635
636 /* Transmit */
637 for (i = 0; i < 32; i++)
638 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
639 for (i = 0; i < 32; i++)
640 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
641 for (i = 0; i < 32; i++)
642 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
643 for (i = 0; i < 32; i++)
644 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
645 for (i = 0; i < 32; i++)
646 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
647 for (i = 0; i < 32; i++)
648 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
649 for (i = 0; i < 32; i++)
650 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
651 for (i = 0; i < 32; i++)
652 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
653 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
654 for (i = 0; i < 16; i++)
655 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
656 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
657 for (i = 0; i < 8; i++)
658 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
659 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
660
661 /* Wake Up */
662 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
663 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
664 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
665 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
666 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
667 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
668 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
669 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 670 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 671
673ac604 672 /* DCB */
9a799d71
AK		 673 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
674 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
675 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
676 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
677 for (i = 0; i < 8; i++)
678 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
679 for (i = 0; i < 8; i++)
680 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
681 for (i = 0; i < 8; i++)
682 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
683 for (i = 0; i < 8; i++)
684 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
685 for (i = 0; i < 8; i++)
686 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
687 for (i = 0; i < 8; i++)
688 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
689
690 /* Statistics */
691 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
692 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
693 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
694 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
695 for (i = 0; i < 8; i++)
696 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
697 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
698 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
699 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
700 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
701 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
702 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
703 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
704 for (i = 0; i < 8; i++)
705 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
706 for (i = 0; i < 8; i++)
707 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
708 for (i = 0; i < 8; i++)
709 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
710 for (i = 0; i < 8; i++)
711 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
712 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
713 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
714 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
715 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
716 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
717 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
718 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
719 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
720 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
721 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
722 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
723 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
724 for (i = 0; i < 8; i++)
725 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
726 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
727 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
728 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
729 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
730 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
731 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
732 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
733 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
734 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
735 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
736 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
737 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
738 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
739 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
740 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
741 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
742 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
743 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
744 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
745 for (i = 0; i < 16; i++)
746 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
747 for (i = 0; i < 16; i++)
748 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
749 for (i = 0; i < 16; i++)
750 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
751 for (i = 0; i < 16; i++)
752 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
753
754 /* MAC */
755 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
756 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
757 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
758 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
759 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
760 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
761 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
762 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
763 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
764 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
765 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
766 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
767 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
768 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
769 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
770 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
771 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
772 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
773 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
774 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
775 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
776 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
777 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
778 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
779 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
780 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
781 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
782 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
783 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
784 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
785 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
786 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
787 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
788
789 /* Diagnostic */
790 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
791 for (i = 0; i < 8; i++)
98c00a1c 792 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 793 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 794 for (i = 0; i < 4; i++)
795 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 796 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
797 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
798 for (i = 0; i < 8; i++)
98c00a1c 799 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 800 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 801 for (i = 0; i < 4; i++)
802 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 803 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
804 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
805 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
806 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
807 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
808 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
809 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
810 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
811 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
812 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
813 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
814 for (i = 0; i < 8; i++)
98c00a1c 815 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 816 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
817 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
818 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
819 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
820 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
821 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
822 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
823 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
824 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
825}
826
827static int ixgbe_get_eeprom_len(struct net_device *netdev)
828{
829 struct ixgbe_adapter *adapter = netdev_priv(netdev);
830 return adapter->hw.eeprom.word_size * 2;
831}
832
833static int ixgbe_get_eeprom(struct net_device *netdev,
b4617240 834 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 835{
836 struct ixgbe_adapter *adapter = netdev_priv(netdev);
837 struct ixgbe_hw *hw = &adapter->hw;
838 u16 *eeprom_buff;
839 int first_word, last_word, eeprom_len;
840 int ret_val = 0;
841 u16 i;
842
843 if (eeprom->len == 0)
844 return -EINVAL;
845
846 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
847
848 first_word = eeprom->offset >> 1;
849 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
850 eeprom_len = last_word - first_word + 1;
851
852 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
853 if (!eeprom_buff)
854 return -ENOMEM;
855
68c7005d
ET		 856 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
857 eeprom_buff);
9a799d71
AK		 858
859 /* Device's eeprom is always little-endian, word addressable */
860 for (i = 0; i < eeprom_len; i++)
861 le16_to_cpus(&eeprom_buff[i]);
862
863 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
864 kfree(eeprom_buff);
865
866 return ret_val;
867}
868
869static void ixgbe_get_drvinfo(struct net_device *netdev,
b4617240 870 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 871{
872 struct ixgbe_adapter *adapter = netdev_priv(netdev);
34b0368c 873 char firmware_version[32];
9a799d71 874
9fe93afd
DS		 875 strncpy(drvinfo->driver, ixgbe_driver_name,
876 sizeof(drvinfo->driver) - 1);
083fc582 877 strncpy(drvinfo->version, ixgbe_driver_version,
9fe93afd 878 sizeof(drvinfo->version) - 1);
083fc582
DS		 879
880 snprintf(firmware_version, sizeof(firmware_version), "%d.%d-%d",
881 (adapter->eeprom_version & 0xF000) >> 12,
882 (adapter->eeprom_version & 0x0FF0) >> 4,
883 adapter->eeprom_version & 0x000F);
884
885 strncpy(drvinfo->fw_version, firmware_version,
886 sizeof(drvinfo->fw_version));
887 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
888 sizeof(drvinfo->bus_info));
9a799d71 889 drvinfo->n_stats = IXGBE_STATS_LEN;
da4dd0f7 890 drvinfo->testinfo_len = IXGBE_TEST_LEN;
9a799d71
AK		 891 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
892}
893
894static void ixgbe_get_ringparam(struct net_device *netdev,
b4617240 895 struct ethtool_ringparam *ring)
9a799d71
AK		 896{
897 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4a0b9ca0
PW		 898 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
899 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
9a799d71
AK		 900
901 ring->rx_max_pending = IXGBE_MAX_RXD;
902 ring->tx_max_pending = IXGBE_MAX_TXD;
903 ring->rx_mini_max_pending = 0;
904 ring->rx_jumbo_max_pending = 0;
905 ring->rx_pending = rx_ring->count;
906 ring->tx_pending = tx_ring->count;
907 ring->rx_mini_pending = 0;
908 ring->rx_jumbo_pending = 0;
909}
910
911static int ixgbe_set_ringparam(struct net_device *netdev,
b4617240 912 struct ethtool_ringparam *ring)
9a799d71
AK		 913{
914 struct ixgbe_adapter *adapter = netdev_priv(netdev);
f9ed8854 915 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
759884b4 916 int i, err = 0;
c431f97e 917 u32 new_rx_count, new_tx_count;
f9ed8854 918 bool need_update = false;
9a799d71
AK		 919
920 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
921 return -EINVAL;
922
923 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
924 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
925 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
926
927 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
928 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
929 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
930
4a0b9ca0
PW		 931 if ((new_tx_count == adapter->tx_ring[0]->count) &&
932 (new_rx_count == adapter->rx_ring[0]->count)) {
9a799d71
AK		 933 /* nothing to do */
934 return 0;
935 }
936
d4f80882 937 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 938 usleep_range(1000, 2000);
d4f80882 939
759884b4
AD		 940 if (!netif_running(adapter->netdev)) {
941 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 942 adapter->tx_ring[i]->count = new_tx_count;
759884b4 943 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 944 adapter->rx_ring[i]->count = new_rx_count;
759884b4
AD		 945 adapter->tx_ring_count = new_tx_count;
946 adapter->rx_ring_count = new_rx_count;
4a0b9ca0 947 goto clear_reset;
759884b4
AD		 948 }
949
4a0b9ca0 950 temp_tx_ring = vmalloc(adapter->num_tx_queues * sizeof(struct ixgbe_ring));
f9ed8854
MC		 951 if (!temp_tx_ring) {
952 err = -ENOMEM;
4a0b9ca0 953 goto clear_reset;
f9ed8854
MC		 954 }
955
956 if (new_tx_count != adapter->tx_ring_count) {
9a799d71 957 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 958 memcpy(&temp_tx_ring[i], adapter->tx_ring[i],
959 sizeof(struct ixgbe_ring));
f9ed8854 960 temp_tx_ring[i].count = new_tx_count;
b6ec895e 961 err = ixgbe_setup_tx_resources(&temp_tx_ring[i]);
9a799d71 962 if (err) {
c431f97e
JB		 963 while (i) {
964 i--;
b6ec895e 965 ixgbe_free_tx_resources(&temp_tx_ring[i]);
c431f97e 966 }
4a0b9ca0 967 goto clear_reset;
9a799d71 968 }
9a799d71 969 }
f9ed8854 970 need_update = true;
9a799d71
AK		 971 }
972
4a0b9ca0
PW		 973 temp_rx_ring = vmalloc(adapter->num_rx_queues * sizeof(struct ixgbe_ring));
974 if (!temp_rx_ring) {
f9ed8854
MC		 975 err = -ENOMEM;
976 goto err_setup;
d3fa4721 977 }
9a799d71 978
f9ed8854 979 if (new_rx_count != adapter->rx_ring_count) {
c431f97e 980 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 981 memcpy(&temp_rx_ring[i], adapter->rx_ring[i],
982 sizeof(struct ixgbe_ring));
f9ed8854 983 temp_rx_ring[i].count = new_rx_count;
b6ec895e 984 err = ixgbe_setup_rx_resources(&temp_rx_ring[i]);
9a799d71 985 if (err) {
c431f97e
JB		 986 while (i) {
987 i--;
b6ec895e 988 ixgbe_free_rx_resources(&temp_rx_ring[i]);
c431f97e 989 }
9a799d71
AK		 990 goto err_setup;
991 }
9a799d71 992 }
f9ed8854
MC		 993 need_update = true;
994 }
995
996 /* if rings need to be updated, here's the place to do it in one shot */
997 if (need_update) {
759884b4 998 ixgbe_down(adapter);
f9ed8854
MC		 999
1000 /* tx */
1001 if (new_tx_count != adapter->tx_ring_count) {
4a0b9ca0 1002 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 1003 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4a0b9ca0
PW		 1004 memcpy(adapter->tx_ring[i], &temp_tx_ring[i],
1005 sizeof(struct ixgbe_ring));
1006 }
f9ed8854
MC		 1007 adapter->tx_ring_count = new_tx_count;
1008 }
1009
1010 /* rx */
1011 if (new_rx_count != adapter->rx_ring_count) {
4a0b9ca0 1012 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 1013 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4a0b9ca0
PW		 1014 memcpy(adapter->rx_ring[i], &temp_rx_ring[i],
1015 sizeof(struct ixgbe_ring));
1016 }
f9ed8854
MC		 1017 adapter->rx_ring_count = new_rx_count;
1018 }
f9ed8854 1019 ixgbe_up(adapter);
759884b4 1020 }
4a0b9ca0
PW		 1021
1022 vfree(temp_rx_ring);
f9ed8854 1023err_setup:
4a0b9ca0
PW		 1024 vfree(temp_tx_ring);
1025clear_reset:
d4f80882 1026 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 1027 return err;
1028}
1029
b9f2c044 1030static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 1031{
b9f2c044 1032 switch (sset) {
da4dd0f7
PWJ		 1033 case ETH_SS_TEST:
1034 return IXGBE_TEST_LEN;
b9f2c044
JG		 1035 case ETH_SS_STATS:
1036 return IXGBE_STATS_LEN;
1037 default:
1038 return -EOPNOTSUPP;
1039 }
9a799d71
AK		 1040}
1041
1042static void ixgbe_get_ethtool_stats(struct net_device *netdev,
b4617240 1043 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 1044{
1045 struct ixgbe_adapter *adapter = netdev_priv(netdev);
28172739
ED		 1046 struct rtnl_link_stats64 temp;
1047 const struct rtnl_link_stats64 *net_stats;
de1036b1
ED		 1048 unsigned int start;
1049 struct ixgbe_ring *ring;
1050 int i, j;
29c3a050 1051 char *p = NULL;
9a799d71
AK		 1052
1053 ixgbe_update_stats(adapter);
28172739 1054 net_stats = dev_get_stats(netdev, &temp);
9a799d71 1055 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
29c3a050
AK		 1056 switch (ixgbe_gstrings_stats[i].type) {
1057 case NETDEV_STATS:
28172739 1058 p = (char *) net_stats +
29c3a050
AK		 1059 ixgbe_gstrings_stats[i].stat_offset;
1060 break;
1061 case IXGBE_STATS:
1062 p = (char *) adapter +
1063 ixgbe_gstrings_stats[i].stat_offset;
1064 break;
1065 }
1066
9a799d71 1067 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
b4617240 1068 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71
AK		 1069 }
1070 for (j = 0; j < adapter->num_tx_queues; j++) {
de1036b1
ED		 1071 ring = adapter->tx_ring[j];
1072 do {
1073 start = u64_stats_fetch_begin_bh(&ring->syncp);
1074 data[i] = ring->stats.packets;
1075 data[i+1] = ring->stats.bytes;
1076 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1077 i += 2;
9a799d71
AK		 1078 }
1079 for (j = 0; j < adapter->num_rx_queues; j++) {
de1036b1
ED		 1080 ring = adapter->rx_ring[j];
1081 do {
1082 start = u64_stats_fetch_begin_bh(&ring->syncp);
1083 data[i] = ring->stats.packets;
1084 data[i+1] = ring->stats.bytes;
1085 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1086 i += 2;
9a799d71 1087 }
2f90b865
AD		 1088 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1089 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
1090 data[i++] = adapter->stats.pxontxc[j];
1091 data[i++] = adapter->stats.pxofftxc[j];
1092 }
1093 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
1094 data[i++] = adapter->stats.pxonrxc[j];
1095 data[i++] = adapter->stats.pxoffrxc[j];
1096 }
1097 }
9a799d71
AK		 1098}
1099
1100static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
b4617240 1101 u8 *data)
9a799d71
AK		 1102{
1103 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1104 char *p = (char *)data;
9a799d71
AK		 1105 int i;
1106
1107 switch (stringset) {
da4dd0f7
PWJ		 1108 case ETH_SS_TEST:
1109 memcpy(data, *ixgbe_gstrings_test,
1110 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
1111 break;
9a799d71
AK		 1112 case ETH_SS_STATS:
1113 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1114 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1115 ETH_GSTRING_LEN);
1116 p += ETH_GSTRING_LEN;
1117 }
1118 for (i = 0; i < adapter->num_tx_queues; i++) {
1119 sprintf(p, "tx_queue_%u_packets", i);
1120 p += ETH_GSTRING_LEN;
1121 sprintf(p, "tx_queue_%u_bytes", i);
1122 p += ETH_GSTRING_LEN;
1123 }
1124 for (i = 0; i < adapter->num_rx_queues; i++) {
1125 sprintf(p, "rx_queue_%u_packets", i);
1126 p += ETH_GSTRING_LEN;
1127 sprintf(p, "rx_queue_%u_bytes", i);
1128 p += ETH_GSTRING_LEN;
1129 }
2f90b865
AD		 1130 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1131 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1132 sprintf(p, "tx_pb_%u_pxon", i);
bfb8cc31
DS		 1133 p += ETH_GSTRING_LEN;
1134 sprintf(p, "tx_pb_%u_pxoff", i);
1135 p += ETH_GSTRING_LEN;
2f90b865
AD		 1136 }
1137 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
bfb8cc31
DS		 1138 sprintf(p, "rx_pb_%u_pxon", i);
1139 p += ETH_GSTRING_LEN;
1140 sprintf(p, "rx_pb_%u_pxoff", i);
1141 p += ETH_GSTRING_LEN;
2f90b865
AD		 1142 }
1143 }
b4617240 1144 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1145 break;
1146 }
1147}
1148
da4dd0f7
PWJ		 1149static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1150{
1151 struct ixgbe_hw *hw = &adapter->hw;
1152 bool link_up;
1153 u32 link_speed = 0;
1154 *data = 0;
1155
1156 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1157 if (link_up)
1158 return *data;
1159 else
1160 *data = 1;
1161 return *data;
1162}
1163
1164/* ethtool register test data */
1165struct ixgbe_reg_test {
1166 u16 reg;
1167 u8 array_len;
1168 u8 test_type;
1169 u32 mask;
1170 u32 write;
1171};
1172
1173/* In the hardware, registers are laid out either singly, in arrays
1174 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1175 * most tests take place on arrays or single registers (handled
1176 * as a single-element array) and special-case the tables.
1177 * Table tests are always pattern tests.
1178 *
1179 * We also make provision for some required setup steps by specifying
1180 * registers to be written without any read-back testing.
1181 */
1182
1183#define PATTERN_TEST 1
1184#define SET_READ_TEST 2
1185#define WRITE_NO_TEST 3
1186#define TABLE32_TEST 4
1187#define TABLE64_TEST_LO 5
1188#define TABLE64_TEST_HI 6
1189
1190/* default 82599 register test */
66744500 1191static const struct ixgbe_reg_test reg_test_82599[] = {
da4dd0f7
PWJ		 1192 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1193 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1194 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1195 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1196 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1197 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1198 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1199 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1200 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1201 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1202 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1203 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1204 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1205 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1206 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1207 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1208 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1209 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1210 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1211 { 0, 0, 0, 0 }
1212};
1213
1214/* default 82598 register test */
66744500 1215static const struct ixgbe_reg_test reg_test_82598[] = {
da4dd0f7
PWJ		 1216 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1217 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1218 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1219 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1220 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1221 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1222 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1223 /* Enable all four RX queues before testing. */
1224 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1225 /* RDH is read-only for 82598, only test RDT. */
1226 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1227 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1228 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1229 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1230 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1231 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1232 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1233 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1234 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1235 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1236 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1237 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1238 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1239 { 0, 0, 0, 0 }
1240};
1241
95a46011
ET		 1242static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1243 u32 mask, u32 write)
1244{
1245 u32 pat, val, before;
1246 static const u32 test_pattern[] = {
1247 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1248
1249 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1250 before = readl(adapter->hw.hw_addr + reg);
1251 writel((test_pattern[pat] & write),
1252 (adapter->hw.hw_addr + reg));
1253 val = readl(adapter->hw.hw_addr + reg);
1254 if (val != (test_pattern[pat] & write & mask)) {
1255 e_err(drv, "pattern test reg %04X failed: got "
1256 "0x%08X expected 0x%08X\n",
1257 reg, val, (test_pattern[pat] & write & mask));
1258 *data = reg;
1259 writel(before, adapter->hw.hw_addr + reg);
1260 return 1;
1261 }
1262 writel(before, adapter->hw.hw_addr + reg);
1263 }
1264 return 0;
da4dd0f7
PWJ		 1265}
1266
95a46011
ET		 1267static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1268 u32 mask, u32 write)
1269{
1270 u32 val, before;
1271 before = readl(adapter->hw.hw_addr + reg);
1272 writel((write & mask), (adapter->hw.hw_addr + reg));
1273 val = readl(adapter->hw.hw_addr + reg);
1274 if ((write & mask) != (val & mask)) {
1275 e_err(drv, "set/check reg %04X test failed: got 0x%08X "
1276 "expected 0x%08X\n", reg, (val & mask), (write & mask));
1277 *data = reg;
1278 writel(before, (adapter->hw.hw_addr + reg));
1279 return 1;
1280 }
1281 writel(before, (adapter->hw.hw_addr + reg));
1282 return 0;
da4dd0f7
PWJ		 1283}
1284
95a46011
ET		 1285#define REG_PATTERN_TEST(reg, mask, write) \
1286 do { \
1287 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1288 return 1; \
1289 } while (0) \
1290
1291
1292#define REG_SET_AND_CHECK(reg, mask, write) \
1293 do { \
1294 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1295 return 1; \
1296 } while (0) \
1297
da4dd0f7
PWJ		 1298static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1299{
66744500 1300 const struct ixgbe_reg_test *test;
da4dd0f7
PWJ		 1301 u32 value, before, after;
1302 u32 i, toggle;
1303
bd508178
AD		 1304 switch (adapter->hw.mac.type) {
1305 case ixgbe_mac_82598EB:
da4dd0f7
PWJ		 1306 toggle = 0x7FFFF3FF;
1307 test = reg_test_82598;
bd508178
AD		 1308 break;
1309 case ixgbe_mac_82599EB:
b93a2226 1310 case ixgbe_mac_X540:
bd508178
AD		 1311 toggle = 0x7FFFF30F;
1312 test = reg_test_82599;
1313 break;
1314 default:
1315 *data = 1;
1316 return 1;
1317 break;
da4dd0f7
PWJ		 1318 }
1319
1320 /*
1321 * Because the status register is such a special case,
1322 * we handle it separately from the rest of the register
1323 * tests. Some bits are read-only, some toggle, and some
1324 * are writeable on newer MACs.
1325 */
1326 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1327 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1328 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1329 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1330 if (value != after) {
396e799c
ET		 1331 e_err(drv, "failed STATUS register test got: 0x%08X "
1332 "expected: 0x%08X\n", after, value);
da4dd0f7
PWJ		 1333 *data = 1;
1334 return 1;
1335 }
1336 /* restore previous status */
1337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1338
1339 /*
1340 * Perform the remainder of the register test, looping through
1341 * the test table until we either fail or reach the null entry.
1342 */
1343 while (test->reg) {
1344 for (i = 0; i < test->array_len; i++) {
1345 switch (test->test_type) {
1346 case PATTERN_TEST:
1347 REG_PATTERN_TEST(test->reg + (i * 0x40),
95a46011
ET		 1348 test->mask,
1349 test->write);
da4dd0f7
PWJ		 1350 break;
1351 case SET_READ_TEST:
1352 REG_SET_AND_CHECK(test->reg + (i * 0x40),
95a46011
ET		 1353 test->mask,
1354 test->write);
da4dd0f7
PWJ		 1355 break;
1356 case WRITE_NO_TEST:
1357 writel(test->write,
1358 (adapter->hw.hw_addr + test->reg)
1359 + (i * 0x40));
1360 break;
1361 case TABLE32_TEST:
1362 REG_PATTERN_TEST(test->reg + (i * 4),
95a46011
ET		 1363 test->mask,
1364 test->write);
da4dd0f7
PWJ		 1365 break;
1366 case TABLE64_TEST_LO:
1367 REG_PATTERN_TEST(test->reg + (i * 8),
95a46011
ET		 1368 test->mask,
1369 test->write);
da4dd0f7
PWJ		 1370 break;
1371 case TABLE64_TEST_HI:
1372 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
95a46011
ET		 1373 test->mask,
1374 test->write);
da4dd0f7
PWJ		 1375 break;
1376 }
1377 }
1378 test++;
1379 }
1380
1381 *data = 0;
1382 return 0;
1383}
1384
1385static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1386{
1387 struct ixgbe_hw *hw = &adapter->hw;
1388 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1389 *data = 1;
1390 else
1391 *data = 0;
1392 return *data;
1393}
1394
1395static irqreturn_t ixgbe_test_intr(int irq, void *data)
1396{
1397 struct net_device *netdev = (struct net_device *) data;
1398 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1399
1400 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1401
1402 return IRQ_HANDLED;
1403}
1404
1405static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1406{
1407 struct net_device *netdev = adapter->netdev;
1408 u32 mask, i = 0, shared_int = true;
1409 u32 irq = adapter->pdev->irq;
1410
1411 *data = 0;
1412
1413 /* Hook up test interrupt handler just for this test */
1414 if (adapter->msix_entries) {
1415 /* NOTE: we don't test MSI-X interrupts here, yet */
1416 return 0;
1417 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1418 shared_int = false;
a0607fd3 1419 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
da4dd0f7
PWJ		 1420 netdev)) {
1421 *data = 1;
1422 return -1;
1423 }
a0607fd3 1424 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
da4dd0f7
PWJ		 1425 netdev->name, netdev)) {
1426 shared_int = false;
a0607fd3 1427 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
da4dd0f7
PWJ		 1428 netdev->name, netdev)) {
1429 *data = 1;
1430 return -1;
1431 }
396e799c
ET		 1432 e_info(hw, "testing %s interrupt\n", shared_int ?
1433 "shared" : "unshared");
da4dd0f7
PWJ		 1434
1435 /* Disable all the interrupts */
1436 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
032b4325 1437 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1438
1439 /* Test each interrupt */
1440 for (; i < 10; i++) {
1441 /* Interrupt to test */
1442 mask = 1 << i;
1443
1444 if (!shared_int) {
1445 /*
1446 * Disable the interrupts to be reported in
1447 * the cause register and then force the same
1448 * interrupt and see if one gets posted. If
1449 * an interrupt was posted to the bus, the
1450 * test failed.
1451 */
1452 adapter->test_icr = 0;
1453 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1454 ~mask & 0x00007FFF);
1455 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1456 ~mask & 0x00007FFF);
032b4325 1457 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1458
1459 if (adapter->test_icr & mask) {
1460 *data = 3;
1461 break;
1462 }
1463 }
1464
1465 /*
1466 * Enable the interrupt to be reported in the cause
1467 * register and then force the same interrupt and see
1468 * if one gets posted. If an interrupt was not posted
1469 * to the bus, the test failed.
1470 */
1471 adapter->test_icr = 0;
1472 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1473 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
032b4325 1474 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1475
1476 if (!(adapter->test_icr &mask)) {
1477 *data = 4;
1478 break;
1479 }
1480
1481 if (!shared_int) {
1482 /*
1483 * Disable the other interrupts to be reported in
1484 * the cause register and then force the other
1485 * interrupts and see if any get posted. If
1486 * an interrupt was posted to the bus, the
1487 * test failed.
1488 */
1489 adapter->test_icr = 0;
1490 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1491 ~mask & 0x00007FFF);
1492 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1493 ~mask & 0x00007FFF);
032b4325 1494 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1495
1496 if (adapter->test_icr) {
1497 *data = 5;
1498 break;
1499 }
1500 }
1501 }
1502
1503 /* Disable all the interrupts */
1504 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
032b4325 1505 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1506
1507 /* Unhook test interrupt handler */
1508 free_irq(irq, netdev);
1509
1510 return *data;
1511}
1512
1513static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1514{
1515 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1516 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1517 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7 1518 u32 reg_ctl;
da4dd0f7
PWJ		 1519
1520 /* shut down the DMA engines now so they can be reinitialized later */
1521
1522 /* first Rx */
1523 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1524 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1525 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
2d39d576 1526 ixgbe_disable_rx_queue(adapter, rx_ring);
da4dd0f7
PWJ		 1527
1528 /* now Tx */
84418e3b 1529 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
da4dd0f7 1530 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
84418e3b
AD		 1531 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1532
bd508178
AD		 1533 switch (hw->mac.type) {
1534 case ixgbe_mac_82599EB:
b93a2226 1535 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1536 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1537 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1538 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
bd508178
AD		 1539 break;
1540 default:
1541 break;
da4dd0f7
PWJ		 1542 }
1543
1544 ixgbe_reset(adapter);
1545
b6ec895e
AD		 1546 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1547 ixgbe_free_rx_resources(&adapter->test_rx_ring);
da4dd0f7
PWJ		 1548}
1549
1550static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1551{
1552 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1553 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
da4dd0f7 1554 u32 rctl, reg_data;
84418e3b
AD		 1555 int ret_val;
1556 int err;
da4dd0f7
PWJ		 1557
1558 /* Setup Tx descriptor ring and Tx buffers */
84418e3b
AD		 1559 tx_ring->count = IXGBE_DEFAULT_TXD;
1560 tx_ring->queue_index = 0;
b6ec895e 1561 tx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1562 tx_ring->netdev = adapter->netdev;
84418e3b
AD		 1563 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1564 tx_ring->numa_node = adapter->node;
da4dd0f7 1565
b6ec895e 1566 err = ixgbe_setup_tx_resources(tx_ring);
84418e3b
AD		 1567 if (err)
1568 return 1;
da4dd0f7 1569
bd508178
AD		 1570 switch (adapter->hw.mac.type) {
1571 case ixgbe_mac_82599EB:
b93a2226 1572 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1573 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1574 reg_data |= IXGBE_DMATXCTL_TE;
1575 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
bd508178
AD		 1576 break;
1577 default:
1578 break;
da4dd0f7 1579 }
f4ec443b 1580
84418e3b 1581 ixgbe_configure_tx_ring(adapter, tx_ring);
da4dd0f7
PWJ		 1582
1583 /* Setup Rx Descriptor ring and Rx buffers */
84418e3b
AD		 1584 rx_ring->count = IXGBE_DEFAULT_RXD;
1585 rx_ring->queue_index = 0;
b6ec895e 1586 rx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1587 rx_ring->netdev = adapter->netdev;
84418e3b
AD		 1588 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1589 rx_ring->rx_buf_len = IXGBE_RXBUFFER_2048;
1590 rx_ring->numa_node = adapter->node;
1591
b6ec895e 1592 err = ixgbe_setup_rx_resources(rx_ring);
84418e3b 1593 if (err) {
da4dd0f7
PWJ		 1594 ret_val = 4;
1595 goto err_nomem;
1596 }
1597
da4dd0f7
PWJ		 1598 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
da4dd0f7 1600
84418e3b 1601 ixgbe_configure_rx_ring(adapter, rx_ring);
da4dd0f7
PWJ		 1602
1603 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1605
da4dd0f7
PWJ		 1606 return 0;
1607
1608err_nomem:
1609 ixgbe_free_desc_rings(adapter);
1610 return ret_val;
1611}
1612
1613static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1614{
1615 struct ixgbe_hw *hw = &adapter->hw;
1616 u32 reg_data;
1617
e7fd9253
DS		 1618 /* X540 needs to set the MACC.FLU bit to force link up */
1619 if (adapter->hw.mac.type == ixgbe_mac_X540) {
1620 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MACC);
1621 reg_data |= IXGBE_MACC_FLU;
1622 IXGBE_WRITE_REG(&adapter->hw, IXGBE_MACC, reg_data);
1623 }
1624
da4dd0f7 1625 /* right now we only support MAC loopback in the driver */
da4dd0f7 1626 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
84418e3b 1627 /* Setup MAC loopback */
da4dd0f7
PWJ		 1628 reg_data |= IXGBE_HLREG0_LPBK;
1629 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1630
84418e3b
AD		 1631 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1632 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1633 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1634
da4dd0f7
PWJ		 1635 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1636 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1637 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1638 IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
84418e3b 1639 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1640 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1641
1642 /* Disable Atlas Tx lanes; re-enabled in reset path */
1643 if (hw->mac.type == ixgbe_mac_82598EB) {
1644 u8 atlas;
1645
1646 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1647 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1648 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1649
1650 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1651 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1652 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1653
1654 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1655 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1656 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1657
1658 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1659 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1660 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1661 }
1662
1663 return 0;
1664}
1665
1666static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1667{
1668 u32 reg_data;
1669
1670 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1671 reg_data &= ~IXGBE_HLREG0_LPBK;
1672 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1673}
1674
1675static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1676 unsigned int frame_size)
1677{
1678 memset(skb->data, 0xFF, frame_size);
1679 frame_size &= ~1;
1680 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1681 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1682 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1683}
1684
1685static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1686 unsigned int frame_size)
1687{
1688 frame_size &= ~1;
1689 if (*(skb->data + 3) == 0xFF) {
1690 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1691 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1692 return 0;
1693 }
1694 }
1695 return 13;
1696}
1697
fc77dc3c 1698static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
84418e3b
AD		 1699 struct ixgbe_ring *tx_ring,
1700 unsigned int size)
1701{
1702 union ixgbe_adv_rx_desc *rx_desc;
1703 struct ixgbe_rx_buffer *rx_buffer_info;
1704 struct ixgbe_tx_buffer *tx_buffer_info;
1705 const int bufsz = rx_ring->rx_buf_len;
1706 u32 staterr;
1707 u16 rx_ntc, tx_ntc, count = 0;
1708
1709 /* initialize next to clean and descriptor values */
1710 rx_ntc = rx_ring->next_to_clean;
1711 tx_ntc = tx_ring->next_to_clean;
1712 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1713 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1714
1715 while (staterr & IXGBE_RXD_STAT_DD) {
1716 /* check Rx buffer */
1717 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1718
1719 /* unmap Rx buffer, will be remapped by alloc_rx_buffers */
b6ec895e 1720 dma_unmap_single(rx_ring->dev,
84418e3b
AD		 1721 rx_buffer_info->dma,
1722 bufsz,
1723 DMA_FROM_DEVICE);
1724 rx_buffer_info->dma = 0;
1725
1726 /* verify contents of skb */
1727 if (!ixgbe_check_lbtest_frame(rx_buffer_info->skb, size))
1728 count++;
1729
1730 /* unmap buffer on Tx side */
1731 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
b6ec895e 1732 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
84418e3b
AD		 1733
1734 /* increment Rx/Tx next to clean counters */
1735 rx_ntc++;
1736 if (rx_ntc == rx_ring->count)
1737 rx_ntc = 0;
1738 tx_ntc++;
1739 if (tx_ntc == tx_ring->count)
1740 tx_ntc = 0;
1741
1742 /* fetch next descriptor */
1743 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1744 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1745 }
1746
1747 /* re-map buffers to ring, store next to clean values */
fc77dc3c 1748 ixgbe_alloc_rx_buffers(rx_ring, count);
84418e3b
AD		 1749 rx_ring->next_to_clean = rx_ntc;
1750 tx_ring->next_to_clean = tx_ntc;
1751
1752 return count;
1753}
1754
da4dd0f7
PWJ		 1755static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1756{
1757 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1758 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
84418e3b
AD		 1759 int i, j, lc, good_cnt, ret_val = 0;
1760 unsigned int size = 1024;
1761 netdev_tx_t tx_ret_val;
1762 struct sk_buff *skb;
1763
1764 /* allocate test skb */
1765 skb = alloc_skb(size, GFP_KERNEL);
1766 if (!skb)
1767 return 11;
da4dd0f7 1768
84418e3b
AD		 1769 /* place data into test skb */
1770 ixgbe_create_lbtest_frame(skb, size);
1771 skb_put(skb, size);
da4dd0f7
PWJ		 1772
1773 /*
1774 * Calculate the loop count based on the largest descriptor ring
1775 * The idea is to wrap the largest ring a number of times using 64
1776 * send/receive pairs during each loop
1777 */
1778
1779 if (rx_ring->count <= tx_ring->count)
1780 lc = ((tx_ring->count / 64) * 2) + 1;
1781 else
1782 lc = ((rx_ring->count / 64) * 2) + 1;
1783
da4dd0f7 1784 for (j = 0; j <= lc; j++) {
84418e3b 1785 /* reset count of good packets */
da4dd0f7 1786 good_cnt = 0;
84418e3b
AD		 1787
1788 /* place 64 packets on the transmit queue*/
1789 for (i = 0; i < 64; i++) {
1790 skb_get(skb);
1791 tx_ret_val = ixgbe_xmit_frame_ring(skb,
84418e3b
AD		 1792 adapter,
1793 tx_ring);
1794 if (tx_ret_val == NETDEV_TX_OK)
da4dd0f7 1795 good_cnt++;
84418e3b
AD		 1796 }
1797
da4dd0f7 1798 if (good_cnt != 64) {
84418e3b 1799 ret_val = 12;
da4dd0f7
PWJ		 1800 break;
1801 }
84418e3b
AD		 1802
1803 /* allow 200 milliseconds for packets to go from Tx to Rx */
1804 msleep(200);
1805
fc77dc3c 1806 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
84418e3b
AD		 1807 if (good_cnt != 64) {
1808 ret_val = 13;
da4dd0f7
PWJ		 1809 break;
1810 }
1811 }
1812
84418e3b
AD		 1813 /* free the original skb */
1814 kfree_skb(skb);
1815
da4dd0f7
PWJ		 1816 return ret_val;
1817}
1818
1819static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1820{
1821 *data = ixgbe_setup_desc_rings(adapter);
1822 if (*data)
1823 goto out;
1824 *data = ixgbe_setup_loopback_test(adapter);
1825 if (*data)
1826 goto err_loopback;
1827 *data = ixgbe_run_loopback_test(adapter);
1828 ixgbe_loopback_cleanup(adapter);
1829
1830err_loopback:
1831 ixgbe_free_desc_rings(adapter);
1832out:
1833 return *data;
1834}
1835
1836static void ixgbe_diag_test(struct net_device *netdev,
1837 struct ethtool_test *eth_test, u64 *data)
1838{
1839 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1840 bool if_running = netif_running(netdev);
1841
1842 set_bit(__IXGBE_TESTING, &adapter->state);
1843 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1844 /* Offline tests */
1845
396e799c 1846 e_info(hw, "offline testing starting\n");
da4dd0f7
PWJ		 1847
1848 /* Link test performed before hardware reset so autoneg doesn't
1849 * interfere with test result */
1850 if (ixgbe_link_test(adapter, &data[4]))
1851 eth_test->flags |= ETH_TEST_FL_FAILED;
1852
e7d481a6
GR		 1853 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1854 int i;
1855 for (i = 0; i < adapter->num_vfs; i++) {
1856 if (adapter->vfinfo[i].clear_to_send) {
1857 netdev_warn(netdev, "%s",
1858 "offline diagnostic is not "
1859 "supported when VFs are "
1860 "present\n");
1861 data[0] = 1;
1862 data[1] = 1;
1863 data[2] = 1;
1864 data[3] = 1;
1865 eth_test->flags |= ETH_TEST_FL_FAILED;
1866 clear_bit(__IXGBE_TESTING,
1867 &adapter->state);
1868 goto skip_ol_tests;
1869 }
1870 }
1871 }
1872
da4dd0f7
PWJ		 1873 if (if_running)
1874 /* indicate we're in test mode */
1875 dev_close(netdev);
1876 else
1877 ixgbe_reset(adapter);
1878
396e799c 1879 e_info(hw, "register testing starting\n");
da4dd0f7
PWJ		 1880 if (ixgbe_reg_test(adapter, &data[0]))
1881 eth_test->flags |= ETH_TEST_FL_FAILED;
1882
1883 ixgbe_reset(adapter);
396e799c 1884 e_info(hw, "eeprom testing starting\n");
da4dd0f7
PWJ		 1885 if (ixgbe_eeprom_test(adapter, &data[1]))
1886 eth_test->flags |= ETH_TEST_FL_FAILED;
1887
1888 ixgbe_reset(adapter);
396e799c 1889 e_info(hw, "interrupt testing starting\n");
da4dd0f7
PWJ		 1890 if (ixgbe_intr_test(adapter, &data[2]))
1891 eth_test->flags |= ETH_TEST_FL_FAILED;
1892
bdbec4b8
GR		 1893 /* If SRIOV or VMDq is enabled then skip MAC
1894 * loopback diagnostic. */
1895 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1896 IXGBE_FLAG_VMDQ_ENABLED)) {
396e799c
ET		 1897 e_info(hw, "Skip MAC loopback diagnostic in VT "
1898 "mode\n");
bdbec4b8
GR		 1899 data[3] = 0;
1900 goto skip_loopback;
1901 }
1902
da4dd0f7 1903 ixgbe_reset(adapter);
396e799c 1904 e_info(hw, "loopback testing starting\n");
da4dd0f7
PWJ		 1905 if (ixgbe_loopback_test(adapter, &data[3]))
1906 eth_test->flags |= ETH_TEST_FL_FAILED;
1907
bdbec4b8 1908skip_loopback:
da4dd0f7
PWJ		 1909 ixgbe_reset(adapter);
1910
1911 clear_bit(__IXGBE_TESTING, &adapter->state);
1912 if (if_running)
1913 dev_open(netdev);
1914 } else {
396e799c 1915 e_info(hw, "online testing starting\n");
da4dd0f7
PWJ		 1916 /* Online tests */
1917 if (ixgbe_link_test(adapter, &data[4]))
1918 eth_test->flags |= ETH_TEST_FL_FAILED;
1919
1920 /* Online tests aren't run; pass by default */
1921 data[0] = 0;
1922 data[1] = 0;
1923 data[2] = 0;
1924 data[3] = 0;
1925
1926 clear_bit(__IXGBE_TESTING, &adapter->state);
1927 }
e7d481a6 1928skip_ol_tests:
da4dd0f7
PWJ		 1929 msleep_interruptible(4 * 1000);
1930}
9a799d71 1931
d6c519e1
AD		 1932static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1933 struct ethtool_wolinfo *wol)
1934{
1935 struct ixgbe_hw *hw = &adapter->hw;
1936 int retval = 1;
1937
0b077fea 1938 /* WOL not supported except for the following */
d6c519e1 1939 switch(hw->device_id) {
0b077fea
DS		 1940 case IXGBE_DEV_ID_82599_SFP:
1941 /* Only this subdevice supports WOL */
1942 if (hw->subsystem_device_id != IXGBE_SUBDEV_ID_82599_SFP) {
1943 wol->supported = 0;
1944 break;
1945 }
1946 retval = 0;
1947 break;
50d6c681
AD		 1948 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
1949 /* All except this subdevice support WOL */
1950 if (hw->subsystem_device_id ==
1951 IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) {
1952 wol->supported = 0;
1953 break;
1954 }
0b077fea
DS		 1955 retval = 0;
1956 break;
d6c519e1
AD		 1957 case IXGBE_DEV_ID_82599_KX4:
1958 retval = 0;
1959 break;
1960 default:
1961 wol->supported = 0;
d6c519e1
AD		 1962 }
1963
1964 return retval;
1965}
1966
9a799d71 1967static void ixgbe_get_wol(struct net_device *netdev,
b4617240 1968 struct ethtool_wolinfo *wol)
9a799d71 1969{
e63d9762
PW		 1970 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1971
1972 wol->supported = WAKE_UCAST | WAKE_MCAST |
1973 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 1974 wol->wolopts = 0;
1975
d6c519e1
AD		 1976 if (ixgbe_wol_exclusion(adapter, wol) ||
1977 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 1978 return;
1979
1980 if (adapter->wol & IXGBE_WUFC_EX)
1981 wol->wolopts |= WAKE_UCAST;
1982 if (adapter->wol & IXGBE_WUFC_MC)
1983 wol->wolopts |= WAKE_MCAST;
1984 if (adapter->wol & IXGBE_WUFC_BC)
1985 wol->wolopts |= WAKE_BCAST;
1986 if (adapter->wol & IXGBE_WUFC_MAG)
1987 wol->wolopts |= WAKE_MAGIC;
9a799d71
AK		 1988}
1989
e63d9762
PW		 1990static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1991{
1992 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1993
1994 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1995 return -EOPNOTSUPP;
1996
d6c519e1
AD		 1997 if (ixgbe_wol_exclusion(adapter, wol))
1998 return wol->wolopts ? -EOPNOTSUPP : 0;
1999
e63d9762
PW		 2000 adapter->wol = 0;
2001
2002 if (wol->wolopts & WAKE_UCAST)
2003 adapter->wol |= IXGBE_WUFC_EX;
2004 if (wol->wolopts & WAKE_MCAST)
2005 adapter->wol |= IXGBE_WUFC_MC;
2006 if (wol->wolopts & WAKE_BCAST)
2007 adapter->wol |= IXGBE_WUFC_BC;
2008 if (wol->wolopts & WAKE_MAGIC)
2009 adapter->wol |= IXGBE_WUFC_MAG;
2010
2011 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2012
2013 return 0;
2014}
2015
9a799d71
AK		 2016static int ixgbe_nway_reset(struct net_device *netdev)
2017{
2018 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2019
d4f80882
AV		 2020 if (netif_running(netdev))
2021 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2022
2023 return 0;
2024}
2025
66e6961c
ET		 2026static int ixgbe_set_phys_id(struct net_device *netdev,
2027 enum ethtool_phys_id_state state)
9a799d71
AK		 2028{
2029 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 2030 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2031
66e6961c
ET		 2032 switch (state) {
2033 case ETHTOOL_ID_ACTIVE:
2034 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2035 return 2;
9a799d71 2036
66e6961c 2037 case ETHTOOL_ID_ON:
c44ade9e 2038 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
66e6961c
ET		 2039 break;
2040
2041 case ETHTOOL_ID_OFF:
c44ade9e 2042 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
66e6961c 2043 break;
9a799d71 2044
66e6961c
ET		 2045 case ETHTOOL_ID_INACTIVE:
2046 /* Restore LED settings */
2047 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2048 break;
2049 }
9a799d71
AK		 2050
2051 return 0;
2052}
2053
2054static int ixgbe_get_coalesce(struct net_device *netdev,
b4617240 2055 struct ethtool_coalesce *ec)
9a799d71
AK		 2056{
2057 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2058
4a0b9ca0 2059 ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0]->work_limit;
30efa5a3
JB		 2060
2061 /* only valid if in constant ITR mode */
f7554a2b 2062 switch (adapter->rx_itr_setting) {
30efa5a3
JB		 2063 case 0:
2064 /* throttling disabled */
2065 ec->rx_coalesce_usecs = 0;
2066 break;
2067 case 1:
2068 /* dynamic ITR mode */
2069 ec->rx_coalesce_usecs = 1;
2070 break;
2071 default:
2072 /* fixed interrupt rate mode */
f7554a2b 2073 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
30efa5a3
JB		 2074 break;
2075 }
f7554a2b 2076
cfb3f91a
SN		 2077 /* if in mixed tx/rx queues per vector mode, report only rx settings */
2078 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
2079 return 0;
2080
f7554a2b
NS		 2081 /* only valid if in constant ITR mode */
2082 switch (adapter->tx_itr_setting) {
2083 case 0:
2084 /* throttling disabled */
2085 ec->tx_coalesce_usecs = 0;
2086 break;
2087 case 1:
2088 /* dynamic ITR mode */
2089 ec->tx_coalesce_usecs = 1;
2090 break;
2091 default:
2092 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
2093 break;
2094 }
2095
9a799d71
AK		 2096 return 0;
2097}
2098
80fba3f4
AD		 2099/*
2100 * this function must be called before setting the new value of
2101 * rx_itr_setting
2102 */
2103static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter,
2104 struct ethtool_coalesce *ec)
2105{
2106 struct net_device *netdev = adapter->netdev;
2107
2108 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2109 return false;
2110
2111 /* if interrupt rate is too high then disable RSC */
2112 if (ec->rx_coalesce_usecs != 1 &&
2113 ec->rx_coalesce_usecs <= 1000000/IXGBE_MAX_RSC_INT_RATE) {
2114 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2115 e_info(probe, "rx-usecs set too low, "
2116 "disabling RSC\n");
2117 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2118 return true;
2119 }
2120 } else {
2121 /* check the feature flag value and enable RSC if necessary */
2122 if ((netdev->features & NETIF_F_LRO) &&
2123 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2124 e_info(probe, "rx-usecs set to %d, "
2125 "re-enabling RSC\n",
2126 ec->rx_coalesce_usecs);
2127 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2128 return true;
2129 }
2130 }
2131 return false;
2132}
2133
9a799d71 2134static int ixgbe_set_coalesce(struct net_device *netdev,
b4617240 2135 struct ethtool_coalesce *ec)
9a799d71
AK		 2136{
2137 struct ixgbe_adapter *adapter = netdev_priv(netdev);
237057ad 2138 struct ixgbe_q_vector *q_vector;
30efa5a3 2139 int i;
ef021194 2140 bool need_reset = false;
9a799d71 2141
cfb3f91a
SN		 2142 /* don't accept tx specific changes if we've got mixed RxTx vectors */
2143 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count
2144 && ec->tx_coalesce_usecs)
f7554a2b
NS		 2145 return -EINVAL;
2146
9a799d71 2147 if (ec->tx_max_coalesced_frames_irq)
4a0b9ca0 2148 adapter->tx_ring[0]->work_limit = ec->tx_max_coalesced_frames_irq;
30efa5a3
JB		 2149
2150 if (ec->rx_coalesce_usecs > 1) {
509ee935 2151 /* check the limits */
80fba3f4 2152 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
509ee935
JB		 2153 (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2154 return -EINVAL;
2155
80fba3f4
AD		 2156 /* check the old value and enable RSC if necessary */
2157 need_reset = ixgbe_update_rsc(adapter, ec);
2158
30efa5a3 2159 /* store the value in ints/second */
f7554a2b 2160 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
30efa5a3
JB		 2161
2162 /* static value of interrupt rate */
f7554a2b 2163 adapter->rx_itr_setting = adapter->rx_eitr_param;
509ee935 2164 /* clear the lower bit as its used for dynamic state */
f7554a2b 2165 adapter->rx_itr_setting &= ~1;
30efa5a3 2166 } else if (ec->rx_coalesce_usecs == 1) {
80fba3f4
AD		 2167 /* check the old value and enable RSC if necessary */
2168 need_reset = ixgbe_update_rsc(adapter, ec);
2169
30efa5a3 2170 /* 1 means dynamic mode */
f7554a2b
NS		 2171 adapter->rx_eitr_param = 20000;
2172 adapter->rx_itr_setting = 1;
30efa5a3 2173 } else {
80fba3f4
AD		 2174 /* check the old value and enable RSC if necessary */
2175 need_reset = ixgbe_update_rsc(adapter, ec);
509ee935
JB		 2176 /*
2177 * any other value means disable eitr, which is best
2178 * served by setting the interrupt rate very high
2179 */
f8d1dcaf 2180 adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
f7554a2b
NS		 2181 adapter->rx_itr_setting = 0;
2182 }
2183
2184 if (ec->tx_coalesce_usecs > 1) {
f8d1dcaf
JB		 2185 /*
2186 * don't have to worry about max_int as above because
2187 * tx vectors don't do hardware RSC (an rx function)
2188 */
f7554a2b
NS		 2189 /* check the limits */
2190 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2191 (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2192 return -EINVAL;
2193
2194 /* store the value in ints/second */
2195 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2196
2197 /* static value of interrupt rate */
2198 adapter->tx_itr_setting = adapter->tx_eitr_param;
2199
2200 /* clear the lower bit as its used for dynamic state */
2201 adapter->tx_itr_setting &= ~1;
2202 } else if (ec->tx_coalesce_usecs == 1) {
2203 /* 1 means dynamic mode */
2204 adapter->tx_eitr_param = 10000;
2205 adapter->tx_itr_setting = 1;
2206 } else {
2207 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2208 adapter->tx_itr_setting = 0;
30efa5a3 2209 }
9a799d71 2210
237057ad
DS		 2211 /* MSI/MSIx Interrupt Mode */
2212 if (adapter->flags &
2213 (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2214 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2215 for (i = 0; i < num_vectors; i++) {
2216 q_vector = adapter->q_vector[i];
2217 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 2218 /* tx only */
2219 q_vector->eitr = adapter->tx_eitr_param;
237057ad
DS		 2220 else
2221 /* rx only or mixed */
f7554a2b 2222 q_vector->eitr = adapter->rx_eitr_param;
237057ad
DS		 2223 ixgbe_write_eitr(q_vector);
2224 }
2225 /* Legacy Interrupt Mode */
2226 } else {
2227 q_vector = adapter->q_vector[0];
f7554a2b 2228 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 2229 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2230 }
2231
ef021194
JB		 2232 /*
2233 * do reset here at the end to make sure EITR==0 case is handled
2234 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2235 * also locks in RSC enable/disable which requires reset
2236 */
2237 if (need_reset) {
2238 if (netif_running(netdev))
2239 ixgbe_reinit_locked(adapter);
2240 else
2241 ixgbe_reset(adapter);
2242 }
2243
9a799d71
AK		 2244 return 0;
2245}
2246
f8212f97
AD		 2247static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2248{
2249 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a713e7c 2250 bool need_reset = false;
1437ce39 2251 int rc;
f8212f97 2252
f62bbb5e
JG		 2253#ifdef CONFIG_IXGBE_DCB
2254 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
2255 !(data & ETH_FLAG_RXVLAN))
2256 return -EINVAL;
2257#endif
2258
2259 need_reset = (data & ETH_FLAG_RXVLAN) !=
2260 (netdev->features & NETIF_F_HW_VLAN_RX);
2261
67a74ee2
ET		 2262 if ((data & ETH_FLAG_RXHASH) &&
2263 !(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
2264 return -EOPNOTSUPP;
2265
5136cad3 2266 rc = ethtool_op_set_flags(netdev, data, ETH_FLAG_LRO | ETH_FLAG_NTUPLE |
67a74ee2
ET		 2267 ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN |
2268 ETH_FLAG_RXHASH);
1437ce39
BH		 2269 if (rc)
2270 return rc;
f8212f97 2271
f8212f97 2272 /* if state changes we need to update adapter->flags and reset */
80fba3f4
AD		 2273 if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
2274 (!!(data & ETH_FLAG_LRO) !=
2275 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2276 if ((data & ETH_FLAG_LRO) &&
2277 (!adapter->rx_itr_setting ||
2278 (adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE))) {
2279 e_info(probe, "rx-usecs set too low, "
2280 "not enabling RSC.\n");
2281 } else {
f8d1dcaf
JB		 2282 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2283 switch (adapter->hw.mac.type) {
2284 case ixgbe_mac_82599EB:
2285 need_reset = true;
2286 break;
b93a2226
DS		 2287 case ixgbe_mac_X540: {
2288 int i;
2289 for (i = 0; i < adapter->num_rx_queues; i++) {
2290 struct ixgbe_ring *ring =
2291 adapter->rx_ring[i];
2292 if (adapter->flags2 &
2293 IXGBE_FLAG2_RSC_ENABLED) {
2294 ixgbe_configure_rscctl(adapter,
2295 ring);
2296 } else {
2297 ixgbe_clear_rscctl(adapter,
2298 ring);
2299 }
2300 }
2301 }
2302 break;
f8d1dcaf
JB		 2303 default:
2304 break;
2305 }
f8d1dcaf 2306 }
9a713e7c
PW		 2307 }
2308
2309 /*
2310 * Check if Flow Director n-tuple support was enabled or disabled. If
2311 * the state changed, we need to reset.
2312 */
2313 if ((adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) &&
2314 (!(data & ETH_FLAG_NTUPLE))) {
2315 /* turn off Flow Director perfect, set hash and reset */
2316 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2317 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
2318 need_reset = true;
2319 } else if ((!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) &&
2320 (data & ETH_FLAG_NTUPLE)) {
2321 /* turn off Flow Director hash, enable perfect and reset */
2322 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
2323 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2324 need_reset = true;
2325 } else {
2326 /* no state change */
2327 }
2328
2329 if (need_reset) {
f8212f97
AD		 2330 if (netif_running(netdev))
2331 ixgbe_reinit_locked(adapter);
2332 else
2333 ixgbe_reset(adapter);
2334 }
9a713e7c 2335
f8212f97 2336 return 0;
9a713e7c
PW		 2337}
2338
2339static int ixgbe_set_rx_ntuple(struct net_device *dev,
2340 struct ethtool_rx_ntuple *cmd)
2341{
2342 struct ixgbe_adapter *adapter = netdev_priv(dev);
45b9f509 2343 struct ethtool_rx_ntuple_flow_spec *fs = &cmd->fs;
905e4a41 2344 union ixgbe_atr_input input_struct;
9a713e7c
PW		 2345 struct ixgbe_atr_input_masks input_masks;
2346 int target_queue;
45b9f509 2347 int err;
9a713e7c
PW		 2348
2349 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2350 return -EOPNOTSUPP;
2351
2352 /*
2353 * Don't allow programming if the action is a queue greater than
2354 * the number of online Tx queues.
2355 */
45b9f509
AD		 2356 if ((fs->action >= adapter->num_tx_queues) ||
2357 (fs->action < ETHTOOL_RXNTUPLE_ACTION_DROP))
9a713e7c
PW		 2358 return -EINVAL;
2359
905e4a41 2360 memset(&input_struct, 0, sizeof(union ixgbe_atr_input));
9a713e7c
PW		 2361 memset(&input_masks, 0, sizeof(struct ixgbe_atr_input_masks));
2362
45b9f509
AD		 2363 /* record flow type */
2364 switch (fs->flow_type) {
2365 case IPV4_FLOW:
2366 input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2367 break;
9a713e7c 2368 case TCP_V4_FLOW:
45b9f509 2369 input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
9a713e7c
PW		 2370 break;
2371 case UDP_V4_FLOW:
45b9f509 2372 input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
9a713e7c
PW		 2373 break;
2374 case SCTP_V4_FLOW:
45b9f509 2375 input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
9a713e7c
PW		 2376 break;
2377 default:
2378 return -1;
2379 }
f8212f97 2380
45b9f509
AD		 2381 /* copy vlan tag minus the CFI bit */
2382 if ((fs->vlan_tag & 0xEFFF) || (~fs->vlan_tag_mask & 0xEFFF)) {
2383 input_struct.formatted.vlan_id = htons(fs->vlan_tag & 0xEFFF);
2384 if (!fs->vlan_tag_mask) {
2385 input_masks.vlan_id_mask = htons(0xEFFF);
2386 } else {
2387 switch (~fs->vlan_tag_mask & 0xEFFF) {
2388 /* all of these are valid vlan-mask values */
2389 case 0xEFFF:
2390 case 0xE000:
2391 case 0x0FFF:
2392 case 0x0000:
2393 input_masks.vlan_id_mask =
2394 htons(~fs->vlan_tag_mask);
2395 break;
2396 /* exit with error if vlan-mask is invalid */
2397 default:
2398 e_err(drv, "Partial VLAN ID or "
2399 "priority mask in vlan-mask is not "
2400 "supported by hardware\n");
2401 return -1;
2402 }
2403 }
2404 }
2405
2406 /* make sure we only use the first 2 bytes of user data */
2407 if ((fs->data & 0xFFFF) || (~fs->data_mask & 0xFFFF)) {
2408 input_struct.formatted.flex_bytes = htons(fs->data & 0xFFFF);
2409 if (!(fs->data_mask & 0xFFFF)) {
2410 input_masks.flex_mask = 0xFFFF;
2411 } else if (~fs->data_mask & 0xFFFF) {
2412 e_err(drv, "Partial user-def-mask is not "
2413 "supported by hardware\n");
2414 return -1;
2415 }
2416 }
2417
2418 /*
2419 * Copy input into formatted structures
2420 *
2421 * These assignments are based on the following logic
2422 * If neither input or mask are set assume value is masked out.
2423 * If input is set, but mask is not mask should default to accept all.
2424 * If input is not set, but mask is set then mask likely results in 0.
2425 * If input is set and mask is set then assign both.
2426 */
2427 if (fs->h_u.tcp_ip4_spec.ip4src || ~fs->m_u.tcp_ip4_spec.ip4src) {
2428 input_struct.formatted.src_ip[0] = fs->h_u.tcp_ip4_spec.ip4src;
2429 if (!fs->m_u.tcp_ip4_spec.ip4src)
2430 input_masks.src_ip_mask[0] = 0xFFFFFFFF;
2431 else
2432 input_masks.src_ip_mask[0] =
2433 ~fs->m_u.tcp_ip4_spec.ip4src;
2434 }
2435 if (fs->h_u.tcp_ip4_spec.ip4dst || ~fs->m_u.tcp_ip4_spec.ip4dst) {
2436 input_struct.formatted.dst_ip[0] = fs->h_u.tcp_ip4_spec.ip4dst;
2437 if (!fs->m_u.tcp_ip4_spec.ip4dst)
2438 input_masks.dst_ip_mask[0] = 0xFFFFFFFF;
2439 else
2440 input_masks.dst_ip_mask[0] =
2441 ~fs->m_u.tcp_ip4_spec.ip4dst;
2442 }
2443 if (fs->h_u.tcp_ip4_spec.psrc || ~fs->m_u.tcp_ip4_spec.psrc) {
2444 input_struct.formatted.src_port = fs->h_u.tcp_ip4_spec.psrc;
2445 if (!fs->m_u.tcp_ip4_spec.psrc)
2446 input_masks.src_port_mask = 0xFFFF;
2447 else
2448 input_masks.src_port_mask = ~fs->m_u.tcp_ip4_spec.psrc;
2449 }
2450 if (fs->h_u.tcp_ip4_spec.pdst || ~fs->m_u.tcp_ip4_spec.pdst) {
2451 input_struct.formatted.dst_port = fs->h_u.tcp_ip4_spec.pdst;
2452 if (!fs->m_u.tcp_ip4_spec.pdst)
2453 input_masks.dst_port_mask = 0xFFFF;
2454 else
2455 input_masks.dst_port_mask = ~fs->m_u.tcp_ip4_spec.pdst;
2456 }
9a713e7c
PW		 2457
2458 /* determine if we need to drop or route the packet */
45b9f509 2459 if (fs->action == ETHTOOL_RXNTUPLE_ACTION_DROP)
9a713e7c
PW		 2460 target_queue = MAX_RX_QUEUES - 1;
2461 else
45b9f509 2462 target_queue = fs->action;
9a713e7c
PW		 2463
2464 spin_lock(&adapter->fdir_perfect_lock);
45b9f509
AD		 2465 err = ixgbe_fdir_add_perfect_filter_82599(&adapter->hw,
2466 &input_struct,
2467 &input_masks, 0,
2468 target_queue);
9a713e7c
PW		 2469 spin_unlock(&adapter->fdir_perfect_lock);
2470
45b9f509 2471 return err ? -1 : 0;
f8212f97 2472}
9a799d71 2473
b9804972 2474static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 2475 .get_settings = ixgbe_get_settings,
2476 .set_settings = ixgbe_set_settings,
2477 .get_drvinfo = ixgbe_get_drvinfo,
2478 .get_regs_len = ixgbe_get_regs_len,
2479 .get_regs = ixgbe_get_regs,
2480 .get_wol = ixgbe_get_wol,
e63d9762 2481 .set_wol = ixgbe_set_wol,
9a799d71
AK		 2482 .nway_reset = ixgbe_nway_reset,
2483 .get_link = ethtool_op_get_link,
2484 .get_eeprom_len = ixgbe_get_eeprom_len,
2485 .get_eeprom = ixgbe_get_eeprom,
2486 .get_ringparam = ixgbe_get_ringparam,
2487 .set_ringparam = ixgbe_set_ringparam,
2488 .get_pauseparam = ixgbe_get_pauseparam,
2489 .set_pauseparam = ixgbe_set_pauseparam,
2490 .get_rx_csum = ixgbe_get_rx_csum,
2491 .set_rx_csum = ixgbe_set_rx_csum,
2492 .get_tx_csum = ixgbe_get_tx_csum,
2493 .set_tx_csum = ixgbe_set_tx_csum,
2494 .get_sg = ethtool_op_get_sg,
2495 .set_sg = ethtool_op_set_sg,
2496 .get_msglevel = ixgbe_get_msglevel,
2497 .set_msglevel = ixgbe_set_msglevel,
2498 .get_tso = ethtool_op_get_tso,
2499 .set_tso = ixgbe_set_tso,
da4dd0f7 2500 .self_test = ixgbe_diag_test,
9a799d71 2501 .get_strings = ixgbe_get_strings,
66e6961c 2502 .set_phys_id = ixgbe_set_phys_id,
b4617240 2503 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 2504 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2505 .get_coalesce = ixgbe_get_coalesce,
2506 .set_coalesce = ixgbe_set_coalesce,
177db6ff 2507 .get_flags = ethtool_op_get_flags,
f8212f97 2508 .set_flags = ixgbe_set_flags,
9a713e7c 2509 .set_rx_ntuple = ixgbe_set_rx_ntuple,
9a799d71
AK		 2510};
2511
2512void ixgbe_set_ethtool_ops(struct net_device *netdev)
2513{
2514 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2515}
Linux 6.x block layer and io_uring tree(s)