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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
8c47eaa7 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | /* ethtool support for ixgbe */ | |
29 | ||
30 | #include <linux/types.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/ethtool.h> | |
35 | #include <linux/vmalloc.h> | |
36 | #include <linux/uaccess.h> | |
37 | ||
38 | #include "ixgbe.h" | |
39 | ||
40 | ||
41 | #define IXGBE_ALL_RAR_ENTRIES 16 | |
42 | ||
29c3a050 AK |
43 | enum {NETDEV_STATS, IXGBE_STATS}; |
44 | ||
9a799d71 AK |
45 | struct ixgbe_stats { |
46 | char stat_string[ETH_GSTRING_LEN]; | |
29c3a050 | 47 | int type; |
9a799d71 AK |
48 | int sizeof_stat; |
49 | int stat_offset; | |
50 | }; | |
51 | ||
29c3a050 AK |
52 | #define IXGBE_STAT(m) IXGBE_STATS, \ |
53 | sizeof(((struct ixgbe_adapter *)0)->m), \ | |
54 | offsetof(struct ixgbe_adapter, m) | |
55 | #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \ | |
56 | sizeof(((struct net_device *)0)->m), \ | |
57 | offsetof(struct net_device, m) | |
58 | ||
9a799d71 | 59 | static struct ixgbe_stats ixgbe_gstrings_stats[] = { |
2d86f139 AK |
60 | {"rx_packets", IXGBE_NETDEV_STAT(stats.rx_packets)}, |
61 | {"tx_packets", IXGBE_NETDEV_STAT(stats.tx_packets)}, | |
62 | {"rx_bytes", IXGBE_NETDEV_STAT(stats.rx_bytes)}, | |
63 | {"tx_bytes", IXGBE_NETDEV_STAT(stats.tx_bytes)}, | |
aad71918 BG |
64 | {"rx_pkts_nic", IXGBE_STAT(stats.gprc)}, |
65 | {"tx_pkts_nic", IXGBE_STAT(stats.gptc)}, | |
66 | {"rx_bytes_nic", IXGBE_STAT(stats.gorc)}, | |
67 | {"tx_bytes_nic", IXGBE_STAT(stats.gotc)}, | |
9a799d71 AK |
68 | {"lsc_int", IXGBE_STAT(lsc_int)}, |
69 | {"tx_busy", IXGBE_STAT(tx_busy)}, | |
70 | {"non_eop_descs", IXGBE_STAT(non_eop_descs)}, | |
2d86f139 AK |
71 | {"rx_errors", IXGBE_NETDEV_STAT(stats.rx_errors)}, |
72 | {"tx_errors", IXGBE_NETDEV_STAT(stats.tx_errors)}, | |
73 | {"rx_dropped", IXGBE_NETDEV_STAT(stats.rx_dropped)}, | |
74 | {"tx_dropped", IXGBE_NETDEV_STAT(stats.tx_dropped)}, | |
75 | {"multicast", IXGBE_NETDEV_STAT(stats.multicast)}, | |
9a799d71 AK |
76 | {"broadcast", IXGBE_STAT(stats.bprc)}, |
77 | {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) }, | |
2d86f139 AK |
78 | {"collisions", IXGBE_NETDEV_STAT(stats.collisions)}, |
79 | {"rx_over_errors", IXGBE_NETDEV_STAT(stats.rx_over_errors)}, | |
80 | {"rx_crc_errors", IXGBE_NETDEV_STAT(stats.rx_crc_errors)}, | |
81 | {"rx_frame_errors", IXGBE_NETDEV_STAT(stats.rx_frame_errors)}, | |
94b982b2 MC |
82 | {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)}, |
83 | {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)}, | |
c4cf55e5 PWJ |
84 | {"fdir_match", IXGBE_STAT(stats.fdirmatch)}, |
85 | {"fdir_miss", IXGBE_STAT(stats.fdirmiss)}, | |
2d86f139 AK |
86 | {"rx_fifo_errors", IXGBE_NETDEV_STAT(stats.rx_fifo_errors)}, |
87 | {"rx_missed_errors", IXGBE_NETDEV_STAT(stats.rx_missed_errors)}, | |
88 | {"tx_aborted_errors", IXGBE_NETDEV_STAT(stats.tx_aborted_errors)}, | |
89 | {"tx_carrier_errors", IXGBE_NETDEV_STAT(stats.tx_carrier_errors)}, | |
90 | {"tx_fifo_errors", IXGBE_NETDEV_STAT(stats.tx_fifo_errors)}, | |
91 | {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(stats.tx_heartbeat_errors)}, | |
9a799d71 AK |
92 | {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)}, |
93 | {"tx_restart_queue", IXGBE_STAT(restart_queue)}, | |
94 | {"rx_long_length_errors", IXGBE_STAT(stats.roc)}, | |
95 | {"rx_short_length_errors", IXGBE_STAT(stats.ruc)}, | |
9a799d71 AK |
96 | {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)}, |
97 | {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)}, | |
98 | {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)}, | |
99 | {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)}, | |
9a799d71 | 100 | {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)}, |
9a799d71 AK |
101 | {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)}, |
102 | {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)}, | |
e8e26350 | 103 | {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)}, |
6d45522c YZ |
104 | #ifdef IXGBE_FCOE |
105 | {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)}, | |
106 | {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)}, | |
107 | {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)}, | |
108 | {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)}, | |
109 | {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)}, | |
110 | {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)}, | |
111 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
112 | }; |
113 | ||
114 | #define IXGBE_QUEUE_STATS_LEN \ | |
454d7c9b WC |
115 | ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \ |
116 | ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \ | |
117 | (sizeof(struct ixgbe_queue_stats) / sizeof(u64))) | |
b4617240 | 118 | #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats) |
2f90b865 | 119 | #define IXGBE_PB_STATS_LEN ( \ |
9d2f4720 | 120 | (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \ |
2f90b865 AD |
121 | IXGBE_FLAG_DCB_ENABLED) ? \ |
122 | (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \ | |
123 | sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \ | |
124 | sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \ | |
125 | sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \ | |
126 | / sizeof(u64) : 0) | |
127 | #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \ | |
128 | IXGBE_PB_STATS_LEN + \ | |
129 | IXGBE_QUEUE_STATS_LEN) | |
9a799d71 | 130 | |
da4dd0f7 PWJ |
131 | static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = { |
132 | "Register test (offline)", "Eeprom test (offline)", | |
133 | "Interrupt test (offline)", "Loopback test (offline)", | |
134 | "Link test (on/offline)" | |
135 | }; | |
136 | #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN | |
137 | ||
9a799d71 | 138 | static int ixgbe_get_settings(struct net_device *netdev, |
b4617240 | 139 | struct ethtool_cmd *ecmd) |
9a799d71 AK |
140 | { |
141 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
735441fb AV |
142 | struct ixgbe_hw *hw = &adapter->hw; |
143 | u32 link_speed = 0; | |
144 | bool link_up; | |
9a799d71 | 145 | |
735441fb AV |
146 | ecmd->supported = SUPPORTED_10000baseT_Full; |
147 | ecmd->autoneg = AUTONEG_ENABLE; | |
9a799d71 | 148 | ecmd->transceiver = XCVR_EXTERNAL; |
74766013 | 149 | if ((hw->phy.media_type == ixgbe_media_type_copper) || |
a3801379 | 150 | (hw->phy.multispeed_fiber)) { |
735441fb | 151 | ecmd->supported |= (SUPPORTED_1000baseT_Full | |
74766013 | 152 | SUPPORTED_Autoneg); |
735441fb | 153 | |
74766013 | 154 | ecmd->advertising = ADVERTISED_Autoneg; |
735441fb AV |
155 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) |
156 | ecmd->advertising |= ADVERTISED_10000baseT_Full; | |
157 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) | |
158 | ecmd->advertising |= ADVERTISED_1000baseT_Full; | |
7c5b8323 DS |
159 | /* |
160 | * It's possible that phy.autoneg_advertised may not be | |
161 | * set yet. If so display what the default would be - | |
162 | * both 1G and 10G supported. | |
163 | */ | |
164 | if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full | | |
165 | ADVERTISED_10000baseT_Full))) | |
166 | ecmd->advertising |= (ADVERTISED_10000baseT_Full | | |
167 | ADVERTISED_1000baseT_Full); | |
735441fb | 168 | |
74766013 MC |
169 | if (hw->phy.media_type == ixgbe_media_type_copper) { |
170 | ecmd->supported |= SUPPORTED_TP; | |
171 | ecmd->advertising |= ADVERTISED_TP; | |
172 | ecmd->port = PORT_TP; | |
173 | } else { | |
174 | ecmd->supported |= SUPPORTED_FIBRE; | |
175 | ecmd->advertising |= ADVERTISED_FIBRE; | |
176 | ecmd->port = PORT_FIBRE; | |
177 | } | |
1e336d0f DS |
178 | } else if (hw->phy.media_type == ixgbe_media_type_backplane) { |
179 | /* Set as FIBRE until SERDES defined in kernel */ | |
46a72b35 | 180 | if (hw->device_id == IXGBE_DEV_ID_82598_BX) { |
2f21bdd3 DS |
181 | ecmd->supported = (SUPPORTED_1000baseT_Full | |
182 | SUPPORTED_FIBRE); | |
183 | ecmd->advertising = (ADVERTISED_1000baseT_Full | | |
184 | ADVERTISED_FIBRE); | |
185 | ecmd->port = PORT_FIBRE; | |
186 | ecmd->autoneg = AUTONEG_DISABLE; | |
46a72b35 MC |
187 | } else { |
188 | ecmd->supported |= (SUPPORTED_1000baseT_Full | | |
189 | SUPPORTED_FIBRE); | |
190 | ecmd->advertising = (ADVERTISED_10000baseT_Full | | |
191 | ADVERTISED_1000baseT_Full | | |
192 | ADVERTISED_FIBRE); | |
193 | ecmd->port = PORT_FIBRE; | |
1e336d0f | 194 | } |
735441fb AV |
195 | } else { |
196 | ecmd->supported |= SUPPORTED_FIBRE; | |
197 | ecmd->advertising = (ADVERTISED_10000baseT_Full | | |
b4617240 | 198 | ADVERTISED_FIBRE); |
735441fb | 199 | ecmd->port = PORT_FIBRE; |
c44ade9e | 200 | ecmd->autoneg = AUTONEG_DISABLE; |
735441fb | 201 | } |
9a799d71 | 202 | |
3b8626ba PW |
203 | /* Get PHY type */ |
204 | switch (adapter->hw.phy.type) { | |
205 | case ixgbe_phy_tn: | |
206 | case ixgbe_phy_cu_unknown: | |
207 | /* Copper 10G-BASET */ | |
208 | ecmd->port = PORT_TP; | |
209 | break; | |
210 | case ixgbe_phy_qt: | |
211 | ecmd->port = PORT_FIBRE; | |
212 | break; | |
213 | case ixgbe_phy_nl: | |
214 | case ixgbe_phy_tw_tyco: | |
215 | case ixgbe_phy_tw_unknown: | |
216 | case ixgbe_phy_sfp_ftl: | |
217 | case ixgbe_phy_sfp_avago: | |
218 | case ixgbe_phy_sfp_intel: | |
219 | case ixgbe_phy_sfp_unknown: | |
220 | switch (adapter->hw.phy.sfp_type) { | |
221 | /* SFP+ devices, further checking needed */ | |
222 | case ixgbe_sfp_type_da_cu: | |
223 | case ixgbe_sfp_type_da_cu_core0: | |
224 | case ixgbe_sfp_type_da_cu_core1: | |
225 | ecmd->port = PORT_DA; | |
226 | break; | |
227 | case ixgbe_sfp_type_sr: | |
228 | case ixgbe_sfp_type_lr: | |
229 | case ixgbe_sfp_type_srlr_core0: | |
230 | case ixgbe_sfp_type_srlr_core1: | |
231 | ecmd->port = PORT_FIBRE; | |
232 | break; | |
233 | case ixgbe_sfp_type_not_present: | |
234 | ecmd->port = PORT_NONE; | |
235 | break; | |
236 | case ixgbe_sfp_type_unknown: | |
237 | default: | |
238 | ecmd->port = PORT_OTHER; | |
239 | break; | |
240 | } | |
241 | break; | |
242 | case ixgbe_phy_xaui: | |
243 | ecmd->port = PORT_NONE; | |
244 | break; | |
245 | case ixgbe_phy_unknown: | |
246 | case ixgbe_phy_generic: | |
247 | case ixgbe_phy_sfp_unsupported: | |
248 | default: | |
249 | ecmd->port = PORT_OTHER; | |
250 | break; | |
251 | } | |
252 | ||
c44ade9e | 253 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); |
735441fb AV |
254 | if (link_up) { |
255 | ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ? | |
b4617240 | 256 | SPEED_10000 : SPEED_1000; |
9a799d71 AK |
257 | ecmd->duplex = DUPLEX_FULL; |
258 | } else { | |
259 | ecmd->speed = -1; | |
260 | ecmd->duplex = -1; | |
261 | } | |
262 | ||
9a799d71 AK |
263 | return 0; |
264 | } | |
265 | ||
266 | static int ixgbe_set_settings(struct net_device *netdev, | |
b4617240 | 267 | struct ethtool_cmd *ecmd) |
9a799d71 AK |
268 | { |
269 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
735441fb | 270 | struct ixgbe_hw *hw = &adapter->hw; |
0befdb3e | 271 | u32 advertised, old; |
74766013 | 272 | s32 err = 0; |
9a799d71 | 273 | |
74766013 | 274 | if ((hw->phy.media_type == ixgbe_media_type_copper) || |
a3801379 | 275 | (hw->phy.multispeed_fiber)) { |
0befdb3e JB |
276 | /* 10000/copper and 1000/copper must autoneg |
277 | * this function does not support any duplex forcing, but can | |
278 | * limit the advertising of the adapter to only 10000 or 1000 */ | |
279 | if (ecmd->autoneg == AUTONEG_DISABLE) | |
280 | return -EINVAL; | |
281 | ||
282 | old = hw->phy.autoneg_advertised; | |
283 | advertised = 0; | |
284 | if (ecmd->advertising & ADVERTISED_10000baseT_Full) | |
285 | advertised |= IXGBE_LINK_SPEED_10GB_FULL; | |
286 | ||
287 | if (ecmd->advertising & ADVERTISED_1000baseT_Full) | |
288 | advertised |= IXGBE_LINK_SPEED_1GB_FULL; | |
289 | ||
290 | if (old == advertised) | |
74766013 | 291 | return err; |
0befdb3e | 292 | /* this sets the link speed and restarts auto-neg */ |
74766013 | 293 | hw->mac.autotry_restart = true; |
8620a103 | 294 | err = hw->mac.ops.setup_link(hw, advertised, true, true); |
0befdb3e JB |
295 | if (err) { |
296 | DPRINTK(PROBE, INFO, | |
297 | "setup link failed with code %d\n", err); | |
8620a103 | 298 | hw->mac.ops.setup_link(hw, old, true, true); |
0befdb3e | 299 | } |
74766013 MC |
300 | } else { |
301 | /* in this case we currently only support 10Gb/FULL */ | |
302 | if ((ecmd->autoneg == AUTONEG_ENABLE) || | |
a3801379 | 303 | (ecmd->advertising != ADVERTISED_10000baseT_Full) || |
74766013 MC |
304 | (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL)) |
305 | return -EINVAL; | |
9a799d71 AK |
306 | } |
307 | ||
74766013 | 308 | return err; |
9a799d71 AK |
309 | } |
310 | ||
311 | static void ixgbe_get_pauseparam(struct net_device *netdev, | |
b4617240 | 312 | struct ethtool_pauseparam *pause) |
9a799d71 AK |
313 | { |
314 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
315 | struct ixgbe_hw *hw = &adapter->hw; | |
316 | ||
71fd570b DS |
317 | /* |
318 | * Flow Control Autoneg isn't on if | |
319 | * - we didn't ask for it OR | |
320 | * - it failed, we know this by tx & rx being off | |
321 | */ | |
322 | if (hw->fc.disable_fc_autoneg || | |
323 | (hw->fc.current_mode == ixgbe_fc_none)) | |
324 | pause->autoneg = 0; | |
325 | else | |
326 | pause->autoneg = 1; | |
9a799d71 | 327 | |
8756924c PWJ |
328 | #ifdef CONFIG_DCB |
329 | if (hw->fc.current_mode == ixgbe_fc_pfc) { | |
330 | pause->rx_pause = 0; | |
331 | pause->tx_pause = 0; | |
332 | } | |
333 | ||
334 | #endif | |
0ecc061d | 335 | if (hw->fc.current_mode == ixgbe_fc_rx_pause) { |
9a799d71 | 336 | pause->rx_pause = 1; |
0ecc061d | 337 | } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) { |
9a799d71 | 338 | pause->tx_pause = 1; |
0ecc061d | 339 | } else if (hw->fc.current_mode == ixgbe_fc_full) { |
9a799d71 AK |
340 | pause->rx_pause = 1; |
341 | pause->tx_pause = 1; | |
342 | } | |
343 | } | |
344 | ||
345 | static int ixgbe_set_pauseparam(struct net_device *netdev, | |
b4617240 | 346 | struct ethtool_pauseparam *pause) |
9a799d71 AK |
347 | { |
348 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
349 | struct ixgbe_hw *hw = &adapter->hw; | |
620fa036 | 350 | struct ixgbe_fc_info fc; |
9a799d71 | 351 | |
264857b8 PWJ |
352 | #ifdef CONFIG_DCB |
353 | if (adapter->dcb_cfg.pfc_mode_enable || | |
354 | ((hw->mac.type == ixgbe_mac_82598EB) && | |
355 | (adapter->flags & IXGBE_FLAG_DCB_ENABLED))) | |
356 | return -EINVAL; | |
357 | ||
358 | #endif | |
620fa036 MC |
359 | |
360 | fc = hw->fc; | |
361 | ||
71fd570b | 362 | if (pause->autoneg != AUTONEG_ENABLE) |
620fa036 | 363 | fc.disable_fc_autoneg = true; |
71fd570b | 364 | else |
620fa036 | 365 | fc.disable_fc_autoneg = false; |
71fd570b DS |
366 | |
367 | if (pause->rx_pause && pause->tx_pause) | |
620fa036 | 368 | fc.requested_mode = ixgbe_fc_full; |
9a799d71 | 369 | else if (pause->rx_pause && !pause->tx_pause) |
620fa036 | 370 | fc.requested_mode = ixgbe_fc_rx_pause; |
9a799d71 | 371 | else if (!pause->rx_pause && pause->tx_pause) |
620fa036 | 372 | fc.requested_mode = ixgbe_fc_tx_pause; |
9a799d71 | 373 | else if (!pause->rx_pause && !pause->tx_pause) |
620fa036 | 374 | fc.requested_mode = ixgbe_fc_none; |
9c83b070 AV |
375 | else |
376 | return -EINVAL; | |
9a799d71 | 377 | |
264857b8 | 378 | #ifdef CONFIG_DCB |
620fa036 | 379 | adapter->last_lfc_mode = fc.requested_mode; |
264857b8 | 380 | #endif |
620fa036 MC |
381 | |
382 | /* if the thing changed then we'll update and use new autoneg */ | |
383 | if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) { | |
384 | hw->fc = fc; | |
385 | if (netif_running(netdev)) | |
386 | ixgbe_reinit_locked(adapter); | |
387 | else | |
388 | ixgbe_reset(adapter); | |
389 | } | |
9a799d71 AK |
390 | |
391 | return 0; | |
392 | } | |
393 | ||
394 | static u32 ixgbe_get_rx_csum(struct net_device *netdev) | |
395 | { | |
396 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
397 | return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED); | |
398 | } | |
399 | ||
400 | static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data) | |
401 | { | |
402 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
403 | if (data) | |
404 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; | |
405 | else | |
406 | adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED; | |
407 | ||
d4f80882 AV |
408 | if (netif_running(netdev)) |
409 | ixgbe_reinit_locked(adapter); | |
410 | else | |
9a799d71 | 411 | ixgbe_reset(adapter); |
9a799d71 AK |
412 | |
413 | return 0; | |
414 | } | |
415 | ||
416 | static u32 ixgbe_get_tx_csum(struct net_device *netdev) | |
417 | { | |
22f32b7a | 418 | return (netdev->features & NETIF_F_IP_CSUM) != 0; |
9a799d71 AK |
419 | } |
420 | ||
421 | static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data) | |
422 | { | |
45a5ead0 JB |
423 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
424 | ||
425 | if (data) { | |
22f32b7a | 426 | netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); |
45a5ead0 JB |
427 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
428 | netdev->features |= NETIF_F_SCTP_CSUM; | |
429 | } else { | |
3d3d6d3c | 430 | netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); |
45a5ead0 JB |
431 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
432 | netdev->features &= ~NETIF_F_SCTP_CSUM; | |
433 | } | |
9a799d71 AK |
434 | |
435 | return 0; | |
436 | } | |
437 | ||
438 | static int ixgbe_set_tso(struct net_device *netdev, u32 data) | |
439 | { | |
9a799d71 AK |
440 | if (data) { |
441 | netdev->features |= NETIF_F_TSO; | |
442 | netdev->features |= NETIF_F_TSO6; | |
443 | } else { | |
fd2ea0a7 | 444 | netif_tx_stop_all_queues(netdev); |
9a799d71 AK |
445 | netdev->features &= ~NETIF_F_TSO; |
446 | netdev->features &= ~NETIF_F_TSO6; | |
fd2ea0a7 | 447 | netif_tx_start_all_queues(netdev); |
9a799d71 AK |
448 | } |
449 | return 0; | |
450 | } | |
451 | ||
452 | static u32 ixgbe_get_msglevel(struct net_device *netdev) | |
453 | { | |
454 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
455 | return adapter->msg_enable; | |
456 | } | |
457 | ||
458 | static void ixgbe_set_msglevel(struct net_device *netdev, u32 data) | |
459 | { | |
460 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
461 | adapter->msg_enable = data; | |
462 | } | |
463 | ||
464 | static int ixgbe_get_regs_len(struct net_device *netdev) | |
465 | { | |
466 | #define IXGBE_REGS_LEN 1128 | |
467 | return IXGBE_REGS_LEN * sizeof(u32); | |
468 | } | |
469 | ||
470 | #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_ | |
471 | ||
472 | static void ixgbe_get_regs(struct net_device *netdev, | |
b4617240 | 473 | struct ethtool_regs *regs, void *p) |
9a799d71 AK |
474 | { |
475 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
476 | struct ixgbe_hw *hw = &adapter->hw; | |
477 | u32 *regs_buff = p; | |
478 | u8 i; | |
479 | ||
480 | memset(p, 0, IXGBE_REGS_LEN * sizeof(u32)); | |
481 | ||
482 | regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id; | |
483 | ||
484 | /* General Registers */ | |
485 | regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
486 | regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS); | |
487 | regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
488 | regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
489 | regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP); | |
490 | regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
491 | regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER); | |
492 | regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER); | |
493 | ||
494 | /* NVM Register */ | |
495 | regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC); | |
496 | regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD); | |
497 | regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA); | |
498 | regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL); | |
499 | regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA); | |
500 | regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL); | |
501 | regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA); | |
502 | regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT); | |
503 | regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP); | |
504 | regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC); | |
505 | ||
506 | /* Interrupt */ | |
98c00a1c JB |
507 | /* don't read EICR because it can clear interrupt causes, instead |
508 | * read EICS which is a shadow but doesn't clear EICR */ | |
509 | regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS); | |
9a799d71 AK |
510 | regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS); |
511 | regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS); | |
512 | regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC); | |
513 | regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC); | |
514 | regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM); | |
515 | regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0)); | |
516 | regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0)); | |
517 | regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT); | |
518 | regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA); | |
c44ade9e | 519 | regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0)); |
9a799d71 AK |
520 | regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE); |
521 | ||
522 | /* Flow Control */ | |
523 | regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP); | |
524 | regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0)); | |
525 | regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1)); | |
526 | regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2)); | |
527 | regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3)); | |
528 | for (i = 0; i < 8; i++) | |
529 | regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i)); | |
530 | for (i = 0; i < 8; i++) | |
531 | regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i)); | |
532 | regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV); | |
533 | regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS); | |
534 | ||
535 | /* Receive DMA */ | |
536 | for (i = 0; i < 64; i++) | |
537 | regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
538 | for (i = 0; i < 64; i++) | |
539 | regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
540 | for (i = 0; i < 64; i++) | |
541 | regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
542 | for (i = 0; i < 64; i++) | |
543 | regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
544 | for (i = 0; i < 64; i++) | |
545 | regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
546 | for (i = 0; i < 64; i++) | |
547 | regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
548 | for (i = 0; i < 16; i++) | |
549 | regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
550 | for (i = 0; i < 16; i++) | |
551 | regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
552 | regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
553 | for (i = 0; i < 8; i++) | |
554 | regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)); | |
555 | regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
556 | regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN); | |
557 | ||
558 | /* Receive */ | |
559 | regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
560 | regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL); | |
561 | for (i = 0; i < 16; i++) | |
562 | regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i)); | |
563 | for (i = 0; i < 16; i++) | |
564 | regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i)); | |
c44ade9e | 565 | regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0)); |
9a799d71 AK |
566 | regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
567 | regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
568 | regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL); | |
569 | regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC); | |
570 | regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); | |
571 | for (i = 0; i < 8; i++) | |
572 | regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i)); | |
573 | for (i = 0; i < 8; i++) | |
574 | regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i)); | |
575 | regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP); | |
576 | ||
577 | /* Transmit */ | |
578 | for (i = 0; i < 32; i++) | |
579 | regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
580 | for (i = 0; i < 32; i++) | |
581 | regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
582 | for (i = 0; i < 32; i++) | |
583 | regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
584 | for (i = 0; i < 32; i++) | |
585 | regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
586 | for (i = 0; i < 32; i++) | |
587 | regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
588 | for (i = 0; i < 32; i++) | |
589 | regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
590 | for (i = 0; i < 32; i++) | |
591 | regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i)); | |
592 | for (i = 0; i < 32; i++) | |
593 | regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i)); | |
594 | regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL); | |
595 | for (i = 0; i < 16; i++) | |
596 | regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i)); | |
597 | regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG); | |
598 | for (i = 0; i < 8; i++) | |
599 | regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i)); | |
600 | regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP); | |
601 | ||
602 | /* Wake Up */ | |
603 | regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC); | |
604 | regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC); | |
605 | regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS); | |
606 | regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV); | |
607 | regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT); | |
608 | regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); | |
609 | regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); | |
610 | regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); | |
11afc1b1 | 611 | regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0)); |
9a799d71 | 612 | |
9a799d71 AK |
613 | regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); |
614 | regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); | |
615 | regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); | |
616 | regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR); | |
617 | for (i = 0; i < 8; i++) | |
618 | regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i)); | |
619 | for (i = 0; i < 8; i++) | |
620 | regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i)); | |
621 | for (i = 0; i < 8; i++) | |
622 | regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i)); | |
623 | for (i = 0; i < 8; i++) | |
624 | regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i)); | |
625 | for (i = 0; i < 8; i++) | |
626 | regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); | |
627 | for (i = 0; i < 8; i++) | |
628 | regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); | |
629 | ||
630 | /* Statistics */ | |
631 | regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs); | |
632 | regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc); | |
633 | regs_buff[883] = IXGBE_GET_STAT(adapter, errbc); | |
634 | regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc); | |
635 | for (i = 0; i < 8; i++) | |
636 | regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]); | |
637 | regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc); | |
638 | regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc); | |
639 | regs_buff[895] = IXGBE_GET_STAT(adapter, rlec); | |
640 | regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc); | |
641 | regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc); | |
642 | regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc); | |
643 | regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc); | |
644 | for (i = 0; i < 8; i++) | |
645 | regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]); | |
646 | for (i = 0; i < 8; i++) | |
647 | regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]); | |
648 | for (i = 0; i < 8; i++) | |
649 | regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]); | |
650 | for (i = 0; i < 8; i++) | |
651 | regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]); | |
652 | regs_buff[932] = IXGBE_GET_STAT(adapter, prc64); | |
653 | regs_buff[933] = IXGBE_GET_STAT(adapter, prc127); | |
654 | regs_buff[934] = IXGBE_GET_STAT(adapter, prc255); | |
655 | regs_buff[935] = IXGBE_GET_STAT(adapter, prc511); | |
656 | regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023); | |
657 | regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522); | |
658 | regs_buff[938] = IXGBE_GET_STAT(adapter, gprc); | |
659 | regs_buff[939] = IXGBE_GET_STAT(adapter, bprc); | |
660 | regs_buff[940] = IXGBE_GET_STAT(adapter, mprc); | |
661 | regs_buff[941] = IXGBE_GET_STAT(adapter, gptc); | |
662 | regs_buff[942] = IXGBE_GET_STAT(adapter, gorc); | |
663 | regs_buff[944] = IXGBE_GET_STAT(adapter, gotc); | |
664 | for (i = 0; i < 8; i++) | |
665 | regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]); | |
666 | regs_buff[954] = IXGBE_GET_STAT(adapter, ruc); | |
667 | regs_buff[955] = IXGBE_GET_STAT(adapter, rfc); | |
668 | regs_buff[956] = IXGBE_GET_STAT(adapter, roc); | |
669 | regs_buff[957] = IXGBE_GET_STAT(adapter, rjc); | |
670 | regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc); | |
671 | regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc); | |
672 | regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc); | |
673 | regs_buff[961] = IXGBE_GET_STAT(adapter, tor); | |
674 | regs_buff[963] = IXGBE_GET_STAT(adapter, tpr); | |
675 | regs_buff[964] = IXGBE_GET_STAT(adapter, tpt); | |
676 | regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64); | |
677 | regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127); | |
678 | regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255); | |
679 | regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511); | |
680 | regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023); | |
681 | regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522); | |
682 | regs_buff[971] = IXGBE_GET_STAT(adapter, mptc); | |
683 | regs_buff[972] = IXGBE_GET_STAT(adapter, bptc); | |
684 | regs_buff[973] = IXGBE_GET_STAT(adapter, xec); | |
685 | for (i = 0; i < 16; i++) | |
686 | regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]); | |
687 | for (i = 0; i < 16; i++) | |
688 | regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]); | |
689 | for (i = 0; i < 16; i++) | |
690 | regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]); | |
691 | for (i = 0; i < 16; i++) | |
692 | regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]); | |
693 | ||
694 | /* MAC */ | |
695 | regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG); | |
696 | regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); | |
697 | regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); | |
698 | regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0); | |
699 | regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1); | |
700 | regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); | |
701 | regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); | |
702 | regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP); | |
703 | regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP); | |
704 | regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
705 | regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1); | |
706 | regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP); | |
707 | regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA); | |
708 | regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE); | |
709 | regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD); | |
710 | regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS); | |
711 | regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA); | |
712 | regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD); | |
713 | regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD); | |
714 | regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD); | |
715 | regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG); | |
716 | regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1); | |
717 | regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2); | |
718 | regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS); | |
719 | regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC); | |
720 | regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS); | |
721 | regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
722 | regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
723 | regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2); | |
724 | regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3); | |
725 | regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1); | |
726 | regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2); | |
727 | regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL); | |
728 | ||
729 | /* Diagnostic */ | |
730 | regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL); | |
731 | for (i = 0; i < 8; i++) | |
98c00a1c | 732 | regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i)); |
9a799d71 | 733 | regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN); |
98c00a1c JB |
734 | for (i = 0; i < 4; i++) |
735 | regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i)); | |
9a799d71 AK |
736 | regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE); |
737 | regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL); | |
738 | for (i = 0; i < 8; i++) | |
98c00a1c | 739 | regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i)); |
9a799d71 | 740 | regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN); |
98c00a1c JB |
741 | for (i = 0; i < 4; i++) |
742 | regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i)); | |
9a799d71 AK |
743 | regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE); |
744 | regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL); | |
745 | regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0); | |
746 | regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1); | |
747 | regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2); | |
748 | regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3); | |
749 | regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL); | |
750 | regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0); | |
751 | regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1); | |
752 | regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2); | |
753 | regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3); | |
754 | for (i = 0; i < 8; i++) | |
98c00a1c | 755 | regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i)); |
9a799d71 AK |
756 | regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL); |
757 | regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1); | |
758 | regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2); | |
759 | regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1); | |
760 | regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2); | |
761 | regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS); | |
762 | regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL); | |
763 | regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC); | |
764 | regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC); | |
765 | } | |
766 | ||
767 | static int ixgbe_get_eeprom_len(struct net_device *netdev) | |
768 | { | |
769 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
770 | return adapter->hw.eeprom.word_size * 2; | |
771 | } | |
772 | ||
773 | static int ixgbe_get_eeprom(struct net_device *netdev, | |
b4617240 | 774 | struct ethtool_eeprom *eeprom, u8 *bytes) |
9a799d71 AK |
775 | { |
776 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
777 | struct ixgbe_hw *hw = &adapter->hw; | |
778 | u16 *eeprom_buff; | |
779 | int first_word, last_word, eeprom_len; | |
780 | int ret_val = 0; | |
781 | u16 i; | |
782 | ||
783 | if (eeprom->len == 0) | |
784 | return -EINVAL; | |
785 | ||
786 | eeprom->magic = hw->vendor_id | (hw->device_id << 16); | |
787 | ||
788 | first_word = eeprom->offset >> 1; | |
789 | last_word = (eeprom->offset + eeprom->len - 1) >> 1; | |
790 | eeprom_len = last_word - first_word + 1; | |
791 | ||
792 | eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL); | |
793 | if (!eeprom_buff) | |
794 | return -ENOMEM; | |
795 | ||
796 | for (i = 0; i < eeprom_len; i++) { | |
c44ade9e | 797 | if ((ret_val = hw->eeprom.ops.read(hw, first_word + i, |
b4617240 | 798 | &eeprom_buff[i]))) |
9a799d71 AK |
799 | break; |
800 | } | |
801 | ||
802 | /* Device's eeprom is always little-endian, word addressable */ | |
803 | for (i = 0; i < eeprom_len; i++) | |
804 | le16_to_cpus(&eeprom_buff[i]); | |
805 | ||
806 | memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); | |
807 | kfree(eeprom_buff); | |
808 | ||
809 | return ret_val; | |
810 | } | |
811 | ||
812 | static void ixgbe_get_drvinfo(struct net_device *netdev, | |
b4617240 | 813 | struct ethtool_drvinfo *drvinfo) |
9a799d71 AK |
814 | { |
815 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
34b0368c | 816 | char firmware_version[32]; |
9a799d71 AK |
817 | |
818 | strncpy(drvinfo->driver, ixgbe_driver_name, 32); | |
819 | strncpy(drvinfo->version, ixgbe_driver_version, 32); | |
34b0368c PWJ |
820 | |
821 | sprintf(firmware_version, "%d.%d-%d", | |
822 | (adapter->eeprom_version & 0xF000) >> 12, | |
823 | (adapter->eeprom_version & 0x0FF0) >> 4, | |
824 | adapter->eeprom_version & 0x000F); | |
825 | ||
826 | strncpy(drvinfo->fw_version, firmware_version, 32); | |
9a799d71 AK |
827 | strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32); |
828 | drvinfo->n_stats = IXGBE_STATS_LEN; | |
da4dd0f7 | 829 | drvinfo->testinfo_len = IXGBE_TEST_LEN; |
9a799d71 AK |
830 | drvinfo->regdump_len = ixgbe_get_regs_len(netdev); |
831 | } | |
832 | ||
833 | static void ixgbe_get_ringparam(struct net_device *netdev, | |
b4617240 | 834 | struct ethtool_ringparam *ring) |
9a799d71 AK |
835 | { |
836 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4a0b9ca0 PW |
837 | struct ixgbe_ring *tx_ring = adapter->tx_ring[0]; |
838 | struct ixgbe_ring *rx_ring = adapter->rx_ring[0]; | |
9a799d71 AK |
839 | |
840 | ring->rx_max_pending = IXGBE_MAX_RXD; | |
841 | ring->tx_max_pending = IXGBE_MAX_TXD; | |
842 | ring->rx_mini_max_pending = 0; | |
843 | ring->rx_jumbo_max_pending = 0; | |
844 | ring->rx_pending = rx_ring->count; | |
845 | ring->tx_pending = tx_ring->count; | |
846 | ring->rx_mini_pending = 0; | |
847 | ring->rx_jumbo_pending = 0; | |
848 | } | |
849 | ||
850 | static int ixgbe_set_ringparam(struct net_device *netdev, | |
b4617240 | 851 | struct ethtool_ringparam *ring) |
9a799d71 AK |
852 | { |
853 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
f9ed8854 | 854 | struct ixgbe_ring *temp_tx_ring, *temp_rx_ring; |
759884b4 | 855 | int i, err = 0; |
c431f97e | 856 | u32 new_rx_count, new_tx_count; |
f9ed8854 | 857 | bool need_update = false; |
9a799d71 AK |
858 | |
859 | if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) | |
860 | return -EINVAL; | |
861 | ||
862 | new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD); | |
863 | new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD); | |
864 | new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE); | |
865 | ||
866 | new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD); | |
867 | new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD); | |
868 | new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE); | |
869 | ||
4a0b9ca0 PW |
870 | if ((new_tx_count == adapter->tx_ring[0]->count) && |
871 | (new_rx_count == adapter->rx_ring[0]->count)) { | |
9a799d71 AK |
872 | /* nothing to do */ |
873 | return 0; | |
874 | } | |
875 | ||
d4f80882 AV |
876 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) |
877 | msleep(1); | |
878 | ||
759884b4 AD |
879 | if (!netif_running(adapter->netdev)) { |
880 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 881 | adapter->tx_ring[i]->count = new_tx_count; |
759884b4 | 882 | for (i = 0; i < adapter->num_rx_queues; i++) |
4a0b9ca0 | 883 | adapter->rx_ring[i]->count = new_rx_count; |
759884b4 AD |
884 | adapter->tx_ring_count = new_tx_count; |
885 | adapter->rx_ring_count = new_rx_count; | |
4a0b9ca0 | 886 | goto clear_reset; |
759884b4 AD |
887 | } |
888 | ||
4a0b9ca0 | 889 | temp_tx_ring = vmalloc(adapter->num_tx_queues * sizeof(struct ixgbe_ring)); |
f9ed8854 MC |
890 | if (!temp_tx_ring) { |
891 | err = -ENOMEM; | |
4a0b9ca0 | 892 | goto clear_reset; |
f9ed8854 MC |
893 | } |
894 | ||
895 | if (new_tx_count != adapter->tx_ring_count) { | |
9a799d71 | 896 | for (i = 0; i < adapter->num_tx_queues; i++) { |
4a0b9ca0 PW |
897 | memcpy(&temp_tx_ring[i], adapter->tx_ring[i], |
898 | sizeof(struct ixgbe_ring)); | |
f9ed8854 MC |
899 | temp_tx_ring[i].count = new_tx_count; |
900 | err = ixgbe_setup_tx_resources(adapter, | |
901 | &temp_tx_ring[i]); | |
9a799d71 | 902 | if (err) { |
c431f97e JB |
903 | while (i) { |
904 | i--; | |
b4617240 | 905 | ixgbe_free_tx_resources(adapter, |
4a0b9ca0 | 906 | &temp_tx_ring[i]); |
c431f97e | 907 | } |
4a0b9ca0 | 908 | goto clear_reset; |
9a799d71 | 909 | } |
9a799d71 | 910 | } |
f9ed8854 | 911 | need_update = true; |
9a799d71 AK |
912 | } |
913 | ||
4a0b9ca0 PW |
914 | temp_rx_ring = vmalloc(adapter->num_rx_queues * sizeof(struct ixgbe_ring)); |
915 | if (!temp_rx_ring) { | |
f9ed8854 MC |
916 | err = -ENOMEM; |
917 | goto err_setup; | |
d3fa4721 | 918 | } |
9a799d71 | 919 | |
f9ed8854 | 920 | if (new_rx_count != adapter->rx_ring_count) { |
c431f97e | 921 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 PW |
922 | memcpy(&temp_rx_ring[i], adapter->rx_ring[i], |
923 | sizeof(struct ixgbe_ring)); | |
f9ed8854 MC |
924 | temp_rx_ring[i].count = new_rx_count; |
925 | err = ixgbe_setup_rx_resources(adapter, | |
926 | &temp_rx_ring[i]); | |
9a799d71 | 927 | if (err) { |
c431f97e JB |
928 | while (i) { |
929 | i--; | |
b4617240 | 930 | ixgbe_free_rx_resources(adapter, |
f9ed8854 | 931 | &temp_rx_ring[i]); |
c431f97e | 932 | } |
9a799d71 AK |
933 | goto err_setup; |
934 | } | |
9a799d71 | 935 | } |
f9ed8854 MC |
936 | need_update = true; |
937 | } | |
938 | ||
939 | /* if rings need to be updated, here's the place to do it in one shot */ | |
940 | if (need_update) { | |
759884b4 | 941 | ixgbe_down(adapter); |
f9ed8854 MC |
942 | |
943 | /* tx */ | |
944 | if (new_tx_count != adapter->tx_ring_count) { | |
4a0b9ca0 PW |
945 | for (i = 0; i < adapter->num_tx_queues; i++) { |
946 | ixgbe_free_tx_resources(adapter, | |
947 | adapter->tx_ring[i]); | |
948 | memcpy(adapter->tx_ring[i], &temp_tx_ring[i], | |
949 | sizeof(struct ixgbe_ring)); | |
950 | } | |
f9ed8854 MC |
951 | adapter->tx_ring_count = new_tx_count; |
952 | } | |
953 | ||
954 | /* rx */ | |
955 | if (new_rx_count != adapter->rx_ring_count) { | |
4a0b9ca0 PW |
956 | for (i = 0; i < adapter->num_rx_queues; i++) { |
957 | ixgbe_free_rx_resources(adapter, | |
958 | adapter->rx_ring[i]); | |
959 | memcpy(adapter->rx_ring[i], &temp_rx_ring[i], | |
960 | sizeof(struct ixgbe_ring)); | |
961 | } | |
f9ed8854 MC |
962 | adapter->rx_ring_count = new_rx_count; |
963 | } | |
f9ed8854 | 964 | ixgbe_up(adapter); |
759884b4 | 965 | } |
4a0b9ca0 PW |
966 | |
967 | vfree(temp_rx_ring); | |
f9ed8854 | 968 | err_setup: |
4a0b9ca0 PW |
969 | vfree(temp_tx_ring); |
970 | clear_reset: | |
d4f80882 | 971 | clear_bit(__IXGBE_RESETTING, &adapter->state); |
9a799d71 AK |
972 | return err; |
973 | } | |
974 | ||
b9f2c044 | 975 | static int ixgbe_get_sset_count(struct net_device *netdev, int sset) |
9a799d71 | 976 | { |
b9f2c044 | 977 | switch (sset) { |
da4dd0f7 PWJ |
978 | case ETH_SS_TEST: |
979 | return IXGBE_TEST_LEN; | |
b9f2c044 JG |
980 | case ETH_SS_STATS: |
981 | return IXGBE_STATS_LEN; | |
9a713e7c PW |
982 | case ETH_SS_NTUPLE_FILTERS: |
983 | return (ETHTOOL_MAX_NTUPLE_LIST_ENTRY * | |
984 | ETHTOOL_MAX_NTUPLE_STRING_PER_ENTRY); | |
b9f2c044 JG |
985 | default: |
986 | return -EOPNOTSUPP; | |
987 | } | |
9a799d71 AK |
988 | } |
989 | ||
990 | static void ixgbe_get_ethtool_stats(struct net_device *netdev, | |
b4617240 | 991 | struct ethtool_stats *stats, u64 *data) |
9a799d71 AK |
992 | { |
993 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
994 | u64 *queue_stat; | |
995 | int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64); | |
996 | int j, k; | |
997 | int i; | |
29c3a050 | 998 | char *p = NULL; |
9a799d71 AK |
999 | |
1000 | ixgbe_update_stats(adapter); | |
60d51134 | 1001 | dev_get_stats(netdev); |
9a799d71 | 1002 | for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { |
29c3a050 AK |
1003 | switch (ixgbe_gstrings_stats[i].type) { |
1004 | case NETDEV_STATS: | |
1005 | p = (char *) netdev + | |
1006 | ixgbe_gstrings_stats[i].stat_offset; | |
1007 | break; | |
1008 | case IXGBE_STATS: | |
1009 | p = (char *) adapter + | |
1010 | ixgbe_gstrings_stats[i].stat_offset; | |
1011 | break; | |
1012 | } | |
1013 | ||
9a799d71 | 1014 | data[i] = (ixgbe_gstrings_stats[i].sizeof_stat == |
b4617240 | 1015 | sizeof(u64)) ? *(u64 *)p : *(u32 *)p; |
9a799d71 AK |
1016 | } |
1017 | for (j = 0; j < adapter->num_tx_queues; j++) { | |
4a0b9ca0 | 1018 | queue_stat = (u64 *)&adapter->tx_ring[j]->stats; |
9a799d71 AK |
1019 | for (k = 0; k < stat_count; k++) |
1020 | data[i + k] = queue_stat[k]; | |
1021 | i += k; | |
1022 | } | |
1023 | for (j = 0; j < adapter->num_rx_queues; j++) { | |
4a0b9ca0 | 1024 | queue_stat = (u64 *)&adapter->rx_ring[j]->stats; |
9a799d71 AK |
1025 | for (k = 0; k < stat_count; k++) |
1026 | data[i + k] = queue_stat[k]; | |
1027 | i += k; | |
1028 | } | |
2f90b865 AD |
1029 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
1030 | for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) { | |
1031 | data[i++] = adapter->stats.pxontxc[j]; | |
1032 | data[i++] = adapter->stats.pxofftxc[j]; | |
1033 | } | |
1034 | for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) { | |
1035 | data[i++] = adapter->stats.pxonrxc[j]; | |
1036 | data[i++] = adapter->stats.pxoffrxc[j]; | |
1037 | } | |
1038 | } | |
9a799d71 AK |
1039 | } |
1040 | ||
1041 | static void ixgbe_get_strings(struct net_device *netdev, u32 stringset, | |
b4617240 | 1042 | u8 *data) |
9a799d71 AK |
1043 | { |
1044 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
c44ade9e | 1045 | char *p = (char *)data; |
9a799d71 AK |
1046 | int i; |
1047 | ||
1048 | switch (stringset) { | |
da4dd0f7 PWJ |
1049 | case ETH_SS_TEST: |
1050 | memcpy(data, *ixgbe_gstrings_test, | |
1051 | IXGBE_TEST_LEN * ETH_GSTRING_LEN); | |
1052 | break; | |
9a799d71 AK |
1053 | case ETH_SS_STATS: |
1054 | for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) { | |
1055 | memcpy(p, ixgbe_gstrings_stats[i].stat_string, | |
1056 | ETH_GSTRING_LEN); | |
1057 | p += ETH_GSTRING_LEN; | |
1058 | } | |
1059 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1060 | sprintf(p, "tx_queue_%u_packets", i); | |
1061 | p += ETH_GSTRING_LEN; | |
1062 | sprintf(p, "tx_queue_%u_bytes", i); | |
1063 | p += ETH_GSTRING_LEN; | |
1064 | } | |
1065 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1066 | sprintf(p, "rx_queue_%u_packets", i); | |
1067 | p += ETH_GSTRING_LEN; | |
1068 | sprintf(p, "rx_queue_%u_bytes", i); | |
1069 | p += ETH_GSTRING_LEN; | |
1070 | } | |
2f90b865 AD |
1071 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
1072 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
1073 | sprintf(p, "tx_pb_%u_pxon", i); | |
bfb8cc31 DS |
1074 | p += ETH_GSTRING_LEN; |
1075 | sprintf(p, "tx_pb_%u_pxoff", i); | |
1076 | p += ETH_GSTRING_LEN; | |
2f90b865 AD |
1077 | } |
1078 | for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) { | |
bfb8cc31 DS |
1079 | sprintf(p, "rx_pb_%u_pxon", i); |
1080 | p += ETH_GSTRING_LEN; | |
1081 | sprintf(p, "rx_pb_%u_pxoff", i); | |
1082 | p += ETH_GSTRING_LEN; | |
2f90b865 AD |
1083 | } |
1084 | } | |
b4617240 | 1085 | /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */ |
9a799d71 AK |
1086 | break; |
1087 | } | |
1088 | } | |
1089 | ||
da4dd0f7 PWJ |
1090 | static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data) |
1091 | { | |
1092 | struct ixgbe_hw *hw = &adapter->hw; | |
1093 | bool link_up; | |
1094 | u32 link_speed = 0; | |
1095 | *data = 0; | |
1096 | ||
1097 | hw->mac.ops.check_link(hw, &link_speed, &link_up, true); | |
1098 | if (link_up) | |
1099 | return *data; | |
1100 | else | |
1101 | *data = 1; | |
1102 | return *data; | |
1103 | } | |
1104 | ||
1105 | /* ethtool register test data */ | |
1106 | struct ixgbe_reg_test { | |
1107 | u16 reg; | |
1108 | u8 array_len; | |
1109 | u8 test_type; | |
1110 | u32 mask; | |
1111 | u32 write; | |
1112 | }; | |
1113 | ||
1114 | /* In the hardware, registers are laid out either singly, in arrays | |
1115 | * spaced 0x40 bytes apart, or in contiguous tables. We assume | |
1116 | * most tests take place on arrays or single registers (handled | |
1117 | * as a single-element array) and special-case the tables. | |
1118 | * Table tests are always pattern tests. | |
1119 | * | |
1120 | * We also make provision for some required setup steps by specifying | |
1121 | * registers to be written without any read-back testing. | |
1122 | */ | |
1123 | ||
1124 | #define PATTERN_TEST 1 | |
1125 | #define SET_READ_TEST 2 | |
1126 | #define WRITE_NO_TEST 3 | |
1127 | #define TABLE32_TEST 4 | |
1128 | #define TABLE64_TEST_LO 5 | |
1129 | #define TABLE64_TEST_HI 6 | |
1130 | ||
1131 | /* default 82599 register test */ | |
1132 | static struct ixgbe_reg_test reg_test_82599[] = { | |
1133 | { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, | |
1134 | { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, | |
1135 | { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1136 | { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, | |
1137 | { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 }, | |
1138 | { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1139 | { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, | |
1140 | { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, | |
1141 | { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
1142 | { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, | |
1143 | { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, | |
1144 | { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1145 | { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1146 | { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1147 | { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 }, | |
1148 | { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 }, | |
1149 | { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1150 | { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF }, | |
1151 | { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1152 | { 0, 0, 0, 0 } | |
1153 | }; | |
1154 | ||
1155 | /* default 82598 register test */ | |
1156 | static struct ixgbe_reg_test reg_test_82598[] = { | |
1157 | { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, | |
1158 | { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, | |
1159 | { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1160 | { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 }, | |
1161 | { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1162 | { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1163 | { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, | |
1164 | /* Enable all four RX queues before testing. */ | |
1165 | { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE }, | |
1166 | /* RDH is read-only for 82598, only test RDT. */ | |
1167 | { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
1168 | { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 }, | |
1169 | { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 }, | |
1170 | { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1171 | { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF }, | |
1172 | { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1173 | { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1174 | { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, | |
1175 | { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 }, | |
1176 | { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 }, | |
1177 | { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1178 | { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF }, | |
1179 | { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1180 | { 0, 0, 0, 0 } | |
1181 | }; | |
1182 | ||
1183 | #define REG_PATTERN_TEST(R, M, W) \ | |
1184 | { \ | |
1185 | u32 pat, val, before; \ | |
1186 | const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \ | |
1187 | for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \ | |
1188 | before = readl(adapter->hw.hw_addr + R); \ | |
1189 | writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \ | |
1190 | val = readl(adapter->hw.hw_addr + R); \ | |
1191 | if (val != (_test[pat] & W & M)) { \ | |
1192 | DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\ | |
1193 | "0x%08X expected 0x%08X\n", \ | |
1194 | R, val, (_test[pat] & W & M)); \ | |
1195 | *data = R; \ | |
1196 | writel(before, adapter->hw.hw_addr + R); \ | |
1197 | return 1; \ | |
1198 | } \ | |
1199 | writel(before, adapter->hw.hw_addr + R); \ | |
1200 | } \ | |
1201 | } | |
1202 | ||
1203 | #define REG_SET_AND_CHECK(R, M, W) \ | |
1204 | { \ | |
1205 | u32 val, before; \ | |
1206 | before = readl(adapter->hw.hw_addr + R); \ | |
1207 | writel((W & M), (adapter->hw.hw_addr + R)); \ | |
1208 | val = readl(adapter->hw.hw_addr + R); \ | |
1209 | if ((W & M) != (val & M)) { \ | |
1210 | DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\ | |
1211 | "expected 0x%08X\n", R, (val & M), (W & M)); \ | |
1212 | *data = R; \ | |
1213 | writel(before, (adapter->hw.hw_addr + R)); \ | |
1214 | return 1; \ | |
1215 | } \ | |
1216 | writel(before, (adapter->hw.hw_addr + R)); \ | |
1217 | } | |
1218 | ||
1219 | static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data) | |
1220 | { | |
1221 | struct ixgbe_reg_test *test; | |
1222 | u32 value, before, after; | |
1223 | u32 i, toggle; | |
1224 | ||
1225 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
1226 | toggle = 0x7FFFF30F; | |
1227 | test = reg_test_82599; | |
1228 | } else { | |
1229 | toggle = 0x7FFFF3FF; | |
1230 | test = reg_test_82598; | |
1231 | } | |
1232 | ||
1233 | /* | |
1234 | * Because the status register is such a special case, | |
1235 | * we handle it separately from the rest of the register | |
1236 | * tests. Some bits are read-only, some toggle, and some | |
1237 | * are writeable on newer MACs. | |
1238 | */ | |
1239 | before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS); | |
1240 | value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle); | |
1241 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle); | |
1242 | after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle; | |
1243 | if (value != after) { | |
1244 | DPRINTK(DRV, ERR, "failed STATUS register test got: " | |
1245 | "0x%08X expected: 0x%08X\n", after, value); | |
1246 | *data = 1; | |
1247 | return 1; | |
1248 | } | |
1249 | /* restore previous status */ | |
1250 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before); | |
1251 | ||
1252 | /* | |
1253 | * Perform the remainder of the register test, looping through | |
1254 | * the test table until we either fail or reach the null entry. | |
1255 | */ | |
1256 | while (test->reg) { | |
1257 | for (i = 0; i < test->array_len; i++) { | |
1258 | switch (test->test_type) { | |
1259 | case PATTERN_TEST: | |
1260 | REG_PATTERN_TEST(test->reg + (i * 0x40), | |
1261 | test->mask, | |
1262 | test->write); | |
1263 | break; | |
1264 | case SET_READ_TEST: | |
1265 | REG_SET_AND_CHECK(test->reg + (i * 0x40), | |
1266 | test->mask, | |
1267 | test->write); | |
1268 | break; | |
1269 | case WRITE_NO_TEST: | |
1270 | writel(test->write, | |
1271 | (adapter->hw.hw_addr + test->reg) | |
1272 | + (i * 0x40)); | |
1273 | break; | |
1274 | case TABLE32_TEST: | |
1275 | REG_PATTERN_TEST(test->reg + (i * 4), | |
1276 | test->mask, | |
1277 | test->write); | |
1278 | break; | |
1279 | case TABLE64_TEST_LO: | |
1280 | REG_PATTERN_TEST(test->reg + (i * 8), | |
1281 | test->mask, | |
1282 | test->write); | |
1283 | break; | |
1284 | case TABLE64_TEST_HI: | |
1285 | REG_PATTERN_TEST((test->reg + 4) + (i * 8), | |
1286 | test->mask, | |
1287 | test->write); | |
1288 | break; | |
1289 | } | |
1290 | } | |
1291 | test++; | |
1292 | } | |
1293 | ||
1294 | *data = 0; | |
1295 | return 0; | |
1296 | } | |
1297 | ||
1298 | static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data) | |
1299 | { | |
1300 | struct ixgbe_hw *hw = &adapter->hw; | |
1301 | if (hw->eeprom.ops.validate_checksum(hw, NULL)) | |
1302 | *data = 1; | |
1303 | else | |
1304 | *data = 0; | |
1305 | return *data; | |
1306 | } | |
1307 | ||
1308 | static irqreturn_t ixgbe_test_intr(int irq, void *data) | |
1309 | { | |
1310 | struct net_device *netdev = (struct net_device *) data; | |
1311 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1312 | ||
1313 | adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR); | |
1314 | ||
1315 | return IRQ_HANDLED; | |
1316 | } | |
1317 | ||
1318 | static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data) | |
1319 | { | |
1320 | struct net_device *netdev = adapter->netdev; | |
1321 | u32 mask, i = 0, shared_int = true; | |
1322 | u32 irq = adapter->pdev->irq; | |
1323 | ||
1324 | *data = 0; | |
1325 | ||
1326 | /* Hook up test interrupt handler just for this test */ | |
1327 | if (adapter->msix_entries) { | |
1328 | /* NOTE: we don't test MSI-X interrupts here, yet */ | |
1329 | return 0; | |
1330 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
1331 | shared_int = false; | |
a0607fd3 | 1332 | if (request_irq(irq, ixgbe_test_intr, 0, netdev->name, |
da4dd0f7 PWJ |
1333 | netdev)) { |
1334 | *data = 1; | |
1335 | return -1; | |
1336 | } | |
a0607fd3 | 1337 | } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED, |
da4dd0f7 PWJ |
1338 | netdev->name, netdev)) { |
1339 | shared_int = false; | |
a0607fd3 | 1340 | } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED, |
da4dd0f7 PWJ |
1341 | netdev->name, netdev)) { |
1342 | *data = 1; | |
1343 | return -1; | |
1344 | } | |
1345 | DPRINTK(HW, INFO, "testing %s interrupt\n", | |
1346 | (shared_int ? "shared" : "unshared")); | |
1347 | ||
1348 | /* Disable all the interrupts */ | |
1349 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); | |
1350 | msleep(10); | |
1351 | ||
1352 | /* Test each interrupt */ | |
1353 | for (; i < 10; i++) { | |
1354 | /* Interrupt to test */ | |
1355 | mask = 1 << i; | |
1356 | ||
1357 | if (!shared_int) { | |
1358 | /* | |
1359 | * Disable the interrupts to be reported in | |
1360 | * the cause register and then force the same | |
1361 | * interrupt and see if one gets posted. If | |
1362 | * an interrupt was posted to the bus, the | |
1363 | * test failed. | |
1364 | */ | |
1365 | adapter->test_icr = 0; | |
1366 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, | |
1367 | ~mask & 0x00007FFF); | |
1368 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, | |
1369 | ~mask & 0x00007FFF); | |
1370 | msleep(10); | |
1371 | ||
1372 | if (adapter->test_icr & mask) { | |
1373 | *data = 3; | |
1374 | break; | |
1375 | } | |
1376 | } | |
1377 | ||
1378 | /* | |
1379 | * Enable the interrupt to be reported in the cause | |
1380 | * register and then force the same interrupt and see | |
1381 | * if one gets posted. If an interrupt was not posted | |
1382 | * to the bus, the test failed. | |
1383 | */ | |
1384 | adapter->test_icr = 0; | |
1385 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); | |
1386 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
1387 | msleep(10); | |
1388 | ||
1389 | if (!(adapter->test_icr &mask)) { | |
1390 | *data = 4; | |
1391 | break; | |
1392 | } | |
1393 | ||
1394 | if (!shared_int) { | |
1395 | /* | |
1396 | * Disable the other interrupts to be reported in | |
1397 | * the cause register and then force the other | |
1398 | * interrupts and see if any get posted. If | |
1399 | * an interrupt was posted to the bus, the | |
1400 | * test failed. | |
1401 | */ | |
1402 | adapter->test_icr = 0; | |
1403 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, | |
1404 | ~mask & 0x00007FFF); | |
1405 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, | |
1406 | ~mask & 0x00007FFF); | |
1407 | msleep(10); | |
1408 | ||
1409 | if (adapter->test_icr) { | |
1410 | *data = 5; | |
1411 | break; | |
1412 | } | |
1413 | } | |
1414 | } | |
1415 | ||
1416 | /* Disable all the interrupts */ | |
1417 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF); | |
1418 | msleep(10); | |
1419 | ||
1420 | /* Unhook test interrupt handler */ | |
1421 | free_irq(irq, netdev); | |
1422 | ||
1423 | return *data; | |
1424 | } | |
1425 | ||
1426 | static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter) | |
1427 | { | |
1428 | struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; | |
1429 | struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; | |
1430 | struct ixgbe_hw *hw = &adapter->hw; | |
1431 | struct pci_dev *pdev = adapter->pdev; | |
1432 | u32 reg_ctl; | |
1433 | int i; | |
1434 | ||
1435 | /* shut down the DMA engines now so they can be reinitialized later */ | |
1436 | ||
1437 | /* first Rx */ | |
1438 | reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
1439 | reg_ctl &= ~IXGBE_RXCTRL_RXEN; | |
1440 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl); | |
1441 | reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0)); | |
1442 | reg_ctl &= ~IXGBE_RXDCTL_ENABLE; | |
1443 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl); | |
1444 | ||
1445 | /* now Tx */ | |
1446 | reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0)); | |
1447 | reg_ctl &= ~IXGBE_TXDCTL_ENABLE; | |
1448 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl); | |
1449 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
1450 | reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
1451 | reg_ctl &= ~IXGBE_DMATXCTL_TE; | |
1452 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl); | |
1453 | } | |
1454 | ||
1455 | ixgbe_reset(adapter); | |
1456 | ||
1457 | if (tx_ring->desc && tx_ring->tx_buffer_info) { | |
1458 | for (i = 0; i < tx_ring->count; i++) { | |
1459 | struct ixgbe_tx_buffer *buf = | |
1460 | &(tx_ring->tx_buffer_info[i]); | |
1461 | if (buf->dma) | |
1462 | pci_unmap_single(pdev, buf->dma, buf->length, | |
1463 | PCI_DMA_TODEVICE); | |
1464 | if (buf->skb) | |
1465 | dev_kfree_skb(buf->skb); | |
1466 | } | |
1467 | } | |
1468 | ||
1469 | if (rx_ring->desc && rx_ring->rx_buffer_info) { | |
1470 | for (i = 0; i < rx_ring->count; i++) { | |
1471 | struct ixgbe_rx_buffer *buf = | |
1472 | &(rx_ring->rx_buffer_info[i]); | |
1473 | if (buf->dma) | |
1474 | pci_unmap_single(pdev, buf->dma, | |
1475 | IXGBE_RXBUFFER_2048, | |
1476 | PCI_DMA_FROMDEVICE); | |
1477 | if (buf->skb) | |
1478 | dev_kfree_skb(buf->skb); | |
1479 | } | |
1480 | } | |
1481 | ||
1482 | if (tx_ring->desc) { | |
1483 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, | |
1484 | tx_ring->dma); | |
1485 | tx_ring->desc = NULL; | |
1486 | } | |
1487 | if (rx_ring->desc) { | |
1488 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, | |
1489 | rx_ring->dma); | |
1490 | rx_ring->desc = NULL; | |
1491 | } | |
1492 | ||
1493 | kfree(tx_ring->tx_buffer_info); | |
1494 | tx_ring->tx_buffer_info = NULL; | |
1495 | kfree(rx_ring->rx_buffer_info); | |
1496 | rx_ring->rx_buffer_info = NULL; | |
1497 | ||
1498 | return; | |
1499 | } | |
1500 | ||
1501 | static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter) | |
1502 | { | |
1503 | struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; | |
1504 | struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; | |
1505 | struct pci_dev *pdev = adapter->pdev; | |
1506 | u32 rctl, reg_data; | |
1507 | int i, ret_val; | |
1508 | ||
1509 | /* Setup Tx descriptor ring and Tx buffers */ | |
1510 | ||
1511 | if (!tx_ring->count) | |
1512 | tx_ring->count = IXGBE_DEFAULT_TXD; | |
1513 | ||
1514 | tx_ring->tx_buffer_info = kcalloc(tx_ring->count, | |
1515 | sizeof(struct ixgbe_tx_buffer), | |
1516 | GFP_KERNEL); | |
1517 | if (!(tx_ring->tx_buffer_info)) { | |
1518 | ret_val = 1; | |
1519 | goto err_nomem; | |
1520 | } | |
1521 | ||
f4ec443b | 1522 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
da4dd0f7 PWJ |
1523 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
1524 | if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, | |
1525 | &tx_ring->dma))) { | |
1526 | ret_val = 2; | |
1527 | goto err_nomem; | |
1528 | } | |
1529 | tx_ring->next_to_use = tx_ring->next_to_clean = 0; | |
1530 | ||
1531 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0), | |
1532 | ((u64) tx_ring->dma & 0x00000000FFFFFFFF)); | |
1533 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0), | |
1534 | ((u64) tx_ring->dma >> 32)); | |
1535 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0), | |
f4ec443b | 1536 | tx_ring->count * sizeof(union ixgbe_adv_tx_desc)); |
da4dd0f7 PWJ |
1537 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0); |
1538 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0); | |
1539 | ||
1540 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); | |
1541 | reg_data |= IXGBE_HLREG0_TXPADEN; | |
1542 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); | |
1543 | ||
1544 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
1545 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL); | |
1546 | reg_data |= IXGBE_DMATXCTL_TE; | |
1547 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data); | |
1548 | } | |
1549 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0)); | |
1550 | reg_data |= IXGBE_TXDCTL_ENABLE; | |
1551 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data); | |
1552 | ||
1553 | for (i = 0; i < tx_ring->count; i++) { | |
f4ec443b | 1554 | union ixgbe_adv_tx_desc *desc = IXGBE_TX_DESC_ADV(*tx_ring, i); |
da4dd0f7 PWJ |
1555 | struct sk_buff *skb; |
1556 | unsigned int size = 1024; | |
1557 | ||
1558 | skb = alloc_skb(size, GFP_KERNEL); | |
1559 | if (!skb) { | |
1560 | ret_val = 3; | |
1561 | goto err_nomem; | |
1562 | } | |
1563 | skb_put(skb, size); | |
1564 | tx_ring->tx_buffer_info[i].skb = skb; | |
1565 | tx_ring->tx_buffer_info[i].length = skb->len; | |
1566 | tx_ring->tx_buffer_info[i].dma = | |
1567 | pci_map_single(pdev, skb->data, skb->len, | |
f4ec443b PWJ |
1568 | PCI_DMA_TODEVICE); |
1569 | desc->read.buffer_addr = | |
1570 | cpu_to_le64(tx_ring->tx_buffer_info[i].dma); | |
1571 | desc->read.cmd_type_len = cpu_to_le32(skb->len); | |
1572 | desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD_EOP | | |
1573 | IXGBE_TXD_CMD_IFCS | | |
1574 | IXGBE_TXD_CMD_RS); | |
1575 | desc->read.olinfo_status = 0; | |
1576 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
1577 | desc->read.olinfo_status |= | |
1578 | (skb->len << IXGBE_ADVTXD_PAYLEN_SHIFT); | |
1579 | ||
da4dd0f7 PWJ |
1580 | } |
1581 | ||
1582 | /* Setup Rx Descriptor ring and Rx buffers */ | |
1583 | ||
1584 | if (!rx_ring->count) | |
1585 | rx_ring->count = IXGBE_DEFAULT_RXD; | |
1586 | ||
1587 | rx_ring->rx_buffer_info = kcalloc(rx_ring->count, | |
1588 | sizeof(struct ixgbe_rx_buffer), | |
1589 | GFP_KERNEL); | |
1590 | if (!(rx_ring->rx_buffer_info)) { | |
1591 | ret_val = 4; | |
1592 | goto err_nomem; | |
1593 | } | |
1594 | ||
f4ec443b | 1595 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
da4dd0f7 PWJ |
1596 | rx_ring->size = ALIGN(rx_ring->size, 4096); |
1597 | if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, | |
1598 | &rx_ring->dma))) { | |
1599 | ret_val = 5; | |
1600 | goto err_nomem; | |
1601 | } | |
1602 | rx_ring->next_to_use = rx_ring->next_to_clean = 0; | |
1603 | ||
1604 | rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL); | |
1605 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN); | |
1606 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0), | |
1607 | ((u64)rx_ring->dma & 0xFFFFFFFF)); | |
1608 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0), | |
1609 | ((u64) rx_ring->dma >> 32)); | |
1610 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size); | |
1611 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0); | |
1612 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0); | |
1613 | ||
1614 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); | |
1615 | reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE; | |
1616 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data); | |
1617 | ||
1618 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); | |
1619 | reg_data &= ~IXGBE_HLREG0_LPBK; | |
1620 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); | |
1621 | ||
1622 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL); | |
1623 | #define IXGBE_RDRXCTL_RDMTS_MASK 0x00000003 /* Receive Descriptor Minimum | |
1624 | Threshold Size mask */ | |
1625 | reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK; | |
1626 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data); | |
1627 | ||
1628 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL); | |
1629 | #define IXGBE_MCSTCTRL_MO_MASK 0x00000003 /* Multicast Offset mask */ | |
1630 | reg_data &= ~IXGBE_MCSTCTRL_MO_MASK; | |
1631 | reg_data |= adapter->hw.mac.mc_filter_type; | |
1632 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data); | |
1633 | ||
1634 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0)); | |
1635 | reg_data |= IXGBE_RXDCTL_ENABLE; | |
1636 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data); | |
1637 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
4a0b9ca0 | 1638 | int j = adapter->rx_ring[0]->reg_idx; |
da4dd0f7 PWJ |
1639 | u32 k; |
1640 | for (k = 0; k < 10; k++) { | |
1641 | if (IXGBE_READ_REG(&adapter->hw, | |
1642 | IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE) | |
1643 | break; | |
1644 | else | |
1645 | msleep(1); | |
1646 | } | |
1647 | } | |
1648 | ||
1649 | rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS; | |
1650 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl); | |
1651 | ||
1652 | for (i = 0; i < rx_ring->count; i++) { | |
f4ec443b PWJ |
1653 | union ixgbe_adv_rx_desc *rx_desc = |
1654 | IXGBE_RX_DESC_ADV(*rx_ring, i); | |
da4dd0f7 PWJ |
1655 | struct sk_buff *skb; |
1656 | ||
1657 | skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL); | |
1658 | if (!skb) { | |
1659 | ret_val = 6; | |
1660 | goto err_nomem; | |
1661 | } | |
1662 | skb_reserve(skb, NET_IP_ALIGN); | |
1663 | rx_ring->rx_buffer_info[i].skb = skb; | |
1664 | rx_ring->rx_buffer_info[i].dma = | |
1665 | pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048, | |
1666 | PCI_DMA_FROMDEVICE); | |
f4ec443b | 1667 | rx_desc->read.pkt_addr = |
da4dd0f7 PWJ |
1668 | cpu_to_le64(rx_ring->rx_buffer_info[i].dma); |
1669 | memset(skb->data, 0x00, skb->len); | |
1670 | } | |
1671 | ||
1672 | return 0; | |
1673 | ||
1674 | err_nomem: | |
1675 | ixgbe_free_desc_rings(adapter); | |
1676 | return ret_val; | |
1677 | } | |
1678 | ||
1679 | static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter) | |
1680 | { | |
1681 | struct ixgbe_hw *hw = &adapter->hw; | |
1682 | u32 reg_data; | |
1683 | ||
1684 | /* right now we only support MAC loopback in the driver */ | |
1685 | ||
1686 | /* Setup MAC loopback */ | |
1687 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); | |
1688 | reg_data |= IXGBE_HLREG0_LPBK; | |
1689 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); | |
1690 | ||
1691 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC); | |
1692 | reg_data &= ~IXGBE_AUTOC_LMS_MASK; | |
1693 | reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU; | |
1694 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data); | |
1695 | ||
1696 | /* Disable Atlas Tx lanes; re-enabled in reset path */ | |
1697 | if (hw->mac.type == ixgbe_mac_82598EB) { | |
1698 | u8 atlas; | |
1699 | ||
1700 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas); | |
1701 | atlas |= IXGBE_ATLAS_PDN_TX_REG_EN; | |
1702 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas); | |
1703 | ||
1704 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas); | |
1705 | atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL; | |
1706 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas); | |
1707 | ||
1708 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas); | |
1709 | atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL; | |
1710 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas); | |
1711 | ||
1712 | hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas); | |
1713 | atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL; | |
1714 | hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas); | |
1715 | } | |
1716 | ||
1717 | return 0; | |
1718 | } | |
1719 | ||
1720 | static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter) | |
1721 | { | |
1722 | u32 reg_data; | |
1723 | ||
1724 | reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0); | |
1725 | reg_data &= ~IXGBE_HLREG0_LPBK; | |
1726 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data); | |
1727 | } | |
1728 | ||
1729 | static void ixgbe_create_lbtest_frame(struct sk_buff *skb, | |
1730 | unsigned int frame_size) | |
1731 | { | |
1732 | memset(skb->data, 0xFF, frame_size); | |
1733 | frame_size &= ~1; | |
1734 | memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1); | |
1735 | memset(&skb->data[frame_size / 2 + 10], 0xBE, 1); | |
1736 | memset(&skb->data[frame_size / 2 + 12], 0xAF, 1); | |
1737 | } | |
1738 | ||
1739 | static int ixgbe_check_lbtest_frame(struct sk_buff *skb, | |
1740 | unsigned int frame_size) | |
1741 | { | |
1742 | frame_size &= ~1; | |
1743 | if (*(skb->data + 3) == 0xFF) { | |
1744 | if ((*(skb->data + frame_size / 2 + 10) == 0xBE) && | |
1745 | (*(skb->data + frame_size / 2 + 12) == 0xAF)) { | |
1746 | return 0; | |
1747 | } | |
1748 | } | |
1749 | return 13; | |
1750 | } | |
1751 | ||
1752 | static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter) | |
1753 | { | |
1754 | struct ixgbe_ring *tx_ring = &adapter->test_tx_ring; | |
1755 | struct ixgbe_ring *rx_ring = &adapter->test_rx_ring; | |
1756 | struct pci_dev *pdev = adapter->pdev; | |
1757 | int i, j, k, l, lc, good_cnt, ret_val = 0; | |
1758 | unsigned long time; | |
1759 | ||
1760 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1); | |
1761 | ||
1762 | /* | |
1763 | * Calculate the loop count based on the largest descriptor ring | |
1764 | * The idea is to wrap the largest ring a number of times using 64 | |
1765 | * send/receive pairs during each loop | |
1766 | */ | |
1767 | ||
1768 | if (rx_ring->count <= tx_ring->count) | |
1769 | lc = ((tx_ring->count / 64) * 2) + 1; | |
1770 | else | |
1771 | lc = ((rx_ring->count / 64) * 2) + 1; | |
1772 | ||
1773 | k = l = 0; | |
1774 | for (j = 0; j <= lc; j++) { | |
1775 | for (i = 0; i < 64; i++) { | |
1776 | ixgbe_create_lbtest_frame( | |
1777 | tx_ring->tx_buffer_info[k].skb, | |
1778 | 1024); | |
1779 | pci_dma_sync_single_for_device(pdev, | |
1780 | tx_ring->tx_buffer_info[k].dma, | |
1781 | tx_ring->tx_buffer_info[k].length, | |
1782 | PCI_DMA_TODEVICE); | |
1783 | if (unlikely(++k == tx_ring->count)) | |
1784 | k = 0; | |
1785 | } | |
1786 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k); | |
1787 | msleep(200); | |
1788 | /* set the start time for the receive */ | |
1789 | time = jiffies; | |
1790 | good_cnt = 0; | |
1791 | do { | |
1792 | /* receive the sent packets */ | |
1793 | pci_dma_sync_single_for_cpu(pdev, | |
1794 | rx_ring->rx_buffer_info[l].dma, | |
1795 | IXGBE_RXBUFFER_2048, | |
1796 | PCI_DMA_FROMDEVICE); | |
1797 | ret_val = ixgbe_check_lbtest_frame( | |
1798 | rx_ring->rx_buffer_info[l].skb, 1024); | |
1799 | if (!ret_val) | |
1800 | good_cnt++; | |
1801 | if (++l == rx_ring->count) | |
1802 | l = 0; | |
1803 | /* | |
1804 | * time + 20 msecs (200 msecs on 2.4) is more than | |
1805 | * enough time to complete the receives, if it's | |
1806 | * exceeded, break and error off | |
1807 | */ | |
1808 | } while (good_cnt < 64 && jiffies < (time + 20)); | |
1809 | if (good_cnt != 64) { | |
1810 | /* ret_val is the same as mis-compare */ | |
1811 | ret_val = 13; | |
1812 | break; | |
1813 | } | |
1814 | if (jiffies >= (time + 20)) { | |
1815 | /* Error code for time out error */ | |
1816 | ret_val = 14; | |
1817 | break; | |
1818 | } | |
1819 | } | |
1820 | ||
1821 | return ret_val; | |
1822 | } | |
1823 | ||
1824 | static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data) | |
1825 | { | |
1826 | *data = ixgbe_setup_desc_rings(adapter); | |
1827 | if (*data) | |
1828 | goto out; | |
1829 | *data = ixgbe_setup_loopback_test(adapter); | |
1830 | if (*data) | |
1831 | goto err_loopback; | |
1832 | *data = ixgbe_run_loopback_test(adapter); | |
1833 | ixgbe_loopback_cleanup(adapter); | |
1834 | ||
1835 | err_loopback: | |
1836 | ixgbe_free_desc_rings(adapter); | |
1837 | out: | |
1838 | return *data; | |
1839 | } | |
1840 | ||
1841 | static void ixgbe_diag_test(struct net_device *netdev, | |
1842 | struct ethtool_test *eth_test, u64 *data) | |
1843 | { | |
1844 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1845 | bool if_running = netif_running(netdev); | |
1846 | ||
1847 | set_bit(__IXGBE_TESTING, &adapter->state); | |
1848 | if (eth_test->flags == ETH_TEST_FL_OFFLINE) { | |
1849 | /* Offline tests */ | |
1850 | ||
1851 | DPRINTK(HW, INFO, "offline testing starting\n"); | |
1852 | ||
1853 | /* Link test performed before hardware reset so autoneg doesn't | |
1854 | * interfere with test result */ | |
1855 | if (ixgbe_link_test(adapter, &data[4])) | |
1856 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1857 | ||
1858 | if (if_running) | |
1859 | /* indicate we're in test mode */ | |
1860 | dev_close(netdev); | |
1861 | else | |
1862 | ixgbe_reset(adapter); | |
1863 | ||
1864 | DPRINTK(HW, INFO, "register testing starting\n"); | |
1865 | if (ixgbe_reg_test(adapter, &data[0])) | |
1866 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1867 | ||
1868 | ixgbe_reset(adapter); | |
1869 | DPRINTK(HW, INFO, "eeprom testing starting\n"); | |
1870 | if (ixgbe_eeprom_test(adapter, &data[1])) | |
1871 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1872 | ||
1873 | ixgbe_reset(adapter); | |
1874 | DPRINTK(HW, INFO, "interrupt testing starting\n"); | |
1875 | if (ixgbe_intr_test(adapter, &data[2])) | |
1876 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1877 | ||
bdbec4b8 GR |
1878 | /* If SRIOV or VMDq is enabled then skip MAC |
1879 | * loopback diagnostic. */ | |
1880 | if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED | | |
1881 | IXGBE_FLAG_VMDQ_ENABLED)) { | |
1882 | DPRINTK(HW, INFO, "Skip MAC loopback diagnostic in VT " | |
1883 | "mode\n"); | |
1884 | data[3] = 0; | |
1885 | goto skip_loopback; | |
1886 | } | |
1887 | ||
da4dd0f7 PWJ |
1888 | ixgbe_reset(adapter); |
1889 | DPRINTK(HW, INFO, "loopback testing starting\n"); | |
1890 | if (ixgbe_loopback_test(adapter, &data[3])) | |
1891 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1892 | ||
bdbec4b8 | 1893 | skip_loopback: |
da4dd0f7 PWJ |
1894 | ixgbe_reset(adapter); |
1895 | ||
1896 | clear_bit(__IXGBE_TESTING, &adapter->state); | |
1897 | if (if_running) | |
1898 | dev_open(netdev); | |
1899 | } else { | |
1900 | DPRINTK(HW, INFO, "online testing starting\n"); | |
1901 | /* Online tests */ | |
1902 | if (ixgbe_link_test(adapter, &data[4])) | |
1903 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1904 | ||
1905 | /* Online tests aren't run; pass by default */ | |
1906 | data[0] = 0; | |
1907 | data[1] = 0; | |
1908 | data[2] = 0; | |
1909 | data[3] = 0; | |
1910 | ||
1911 | clear_bit(__IXGBE_TESTING, &adapter->state); | |
1912 | } | |
1913 | msleep_interruptible(4 * 1000); | |
1914 | } | |
9a799d71 | 1915 | |
d6c519e1 AD |
1916 | static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter, |
1917 | struct ethtool_wolinfo *wol) | |
1918 | { | |
1919 | struct ixgbe_hw *hw = &adapter->hw; | |
1920 | int retval = 1; | |
1921 | ||
1922 | switch(hw->device_id) { | |
1923 | case IXGBE_DEV_ID_82599_KX4: | |
1924 | retval = 0; | |
1925 | break; | |
1926 | default: | |
1927 | wol->supported = 0; | |
d6c519e1 AD |
1928 | } |
1929 | ||
1930 | return retval; | |
1931 | } | |
1932 | ||
9a799d71 | 1933 | static void ixgbe_get_wol(struct net_device *netdev, |
b4617240 | 1934 | struct ethtool_wolinfo *wol) |
9a799d71 | 1935 | { |
e63d9762 PW |
1936 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
1937 | ||
1938 | wol->supported = WAKE_UCAST | WAKE_MCAST | | |
1939 | WAKE_BCAST | WAKE_MAGIC; | |
9a799d71 AK |
1940 | wol->wolopts = 0; |
1941 | ||
d6c519e1 AD |
1942 | if (ixgbe_wol_exclusion(adapter, wol) || |
1943 | !device_can_wakeup(&adapter->pdev->dev)) | |
e63d9762 PW |
1944 | return; |
1945 | ||
1946 | if (adapter->wol & IXGBE_WUFC_EX) | |
1947 | wol->wolopts |= WAKE_UCAST; | |
1948 | if (adapter->wol & IXGBE_WUFC_MC) | |
1949 | wol->wolopts |= WAKE_MCAST; | |
1950 | if (adapter->wol & IXGBE_WUFC_BC) | |
1951 | wol->wolopts |= WAKE_BCAST; | |
1952 | if (adapter->wol & IXGBE_WUFC_MAG) | |
1953 | wol->wolopts |= WAKE_MAGIC; | |
1954 | ||
9a799d71 AK |
1955 | return; |
1956 | } | |
1957 | ||
e63d9762 PW |
1958 | static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) |
1959 | { | |
1960 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1961 | ||
1962 | if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE)) | |
1963 | return -EOPNOTSUPP; | |
1964 | ||
d6c519e1 AD |
1965 | if (ixgbe_wol_exclusion(adapter, wol)) |
1966 | return wol->wolopts ? -EOPNOTSUPP : 0; | |
1967 | ||
e63d9762 PW |
1968 | adapter->wol = 0; |
1969 | ||
1970 | if (wol->wolopts & WAKE_UCAST) | |
1971 | adapter->wol |= IXGBE_WUFC_EX; | |
1972 | if (wol->wolopts & WAKE_MCAST) | |
1973 | adapter->wol |= IXGBE_WUFC_MC; | |
1974 | if (wol->wolopts & WAKE_BCAST) | |
1975 | adapter->wol |= IXGBE_WUFC_BC; | |
1976 | if (wol->wolopts & WAKE_MAGIC) | |
1977 | adapter->wol |= IXGBE_WUFC_MAG; | |
1978 | ||
1979 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); | |
1980 | ||
1981 | return 0; | |
1982 | } | |
1983 | ||
9a799d71 AK |
1984 | static int ixgbe_nway_reset(struct net_device *netdev) |
1985 | { | |
1986 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1987 | ||
d4f80882 AV |
1988 | if (netif_running(netdev)) |
1989 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
1990 | |
1991 | return 0; | |
1992 | } | |
1993 | ||
1994 | static int ixgbe_phys_id(struct net_device *netdev, u32 data) | |
1995 | { | |
1996 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
c44ade9e JB |
1997 | struct ixgbe_hw *hw = &adapter->hw; |
1998 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
9a799d71 AK |
1999 | u32 i; |
2000 | ||
2001 | if (!data || data > 300) | |
2002 | data = 300; | |
2003 | ||
2004 | for (i = 0; i < (data * 1000); i += 400) { | |
c44ade9e | 2005 | hw->mac.ops.led_on(hw, IXGBE_LED_ON); |
9a799d71 | 2006 | msleep_interruptible(200); |
c44ade9e | 2007 | hw->mac.ops.led_off(hw, IXGBE_LED_ON); |
9a799d71 AK |
2008 | msleep_interruptible(200); |
2009 | } | |
2010 | ||
2011 | /* Restore LED settings */ | |
2012 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg); | |
2013 | ||
2014 | return 0; | |
2015 | } | |
2016 | ||
2017 | static int ixgbe_get_coalesce(struct net_device *netdev, | |
b4617240 | 2018 | struct ethtool_coalesce *ec) |
9a799d71 AK |
2019 | { |
2020 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2021 | ||
4a0b9ca0 | 2022 | ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0]->work_limit; |
30efa5a3 JB |
2023 | |
2024 | /* only valid if in constant ITR mode */ | |
f7554a2b | 2025 | switch (adapter->rx_itr_setting) { |
30efa5a3 JB |
2026 | case 0: |
2027 | /* throttling disabled */ | |
2028 | ec->rx_coalesce_usecs = 0; | |
2029 | break; | |
2030 | case 1: | |
2031 | /* dynamic ITR mode */ | |
2032 | ec->rx_coalesce_usecs = 1; | |
2033 | break; | |
2034 | default: | |
2035 | /* fixed interrupt rate mode */ | |
f7554a2b | 2036 | ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param; |
30efa5a3 JB |
2037 | break; |
2038 | } | |
f7554a2b | 2039 | |
cfb3f91a SN |
2040 | /* if in mixed tx/rx queues per vector mode, report only rx settings */ |
2041 | if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count) | |
2042 | return 0; | |
2043 | ||
f7554a2b NS |
2044 | /* only valid if in constant ITR mode */ |
2045 | switch (adapter->tx_itr_setting) { | |
2046 | case 0: | |
2047 | /* throttling disabled */ | |
2048 | ec->tx_coalesce_usecs = 0; | |
2049 | break; | |
2050 | case 1: | |
2051 | /* dynamic ITR mode */ | |
2052 | ec->tx_coalesce_usecs = 1; | |
2053 | break; | |
2054 | default: | |
2055 | ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param; | |
2056 | break; | |
2057 | } | |
2058 | ||
9a799d71 AK |
2059 | return 0; |
2060 | } | |
2061 | ||
2062 | static int ixgbe_set_coalesce(struct net_device *netdev, | |
b4617240 | 2063 | struct ethtool_coalesce *ec) |
9a799d71 AK |
2064 | { |
2065 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
237057ad | 2066 | struct ixgbe_q_vector *q_vector; |
30efa5a3 | 2067 | int i; |
9a799d71 | 2068 | |
cfb3f91a SN |
2069 | /* don't accept tx specific changes if we've got mixed RxTx vectors */ |
2070 | if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count | |
2071 | && ec->tx_coalesce_usecs) | |
f7554a2b NS |
2072 | return -EINVAL; |
2073 | ||
9a799d71 | 2074 | if (ec->tx_max_coalesced_frames_irq) |
4a0b9ca0 | 2075 | adapter->tx_ring[0]->work_limit = ec->tx_max_coalesced_frames_irq; |
30efa5a3 JB |
2076 | |
2077 | if (ec->rx_coalesce_usecs > 1) { | |
509ee935 JB |
2078 | /* check the limits */ |
2079 | if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) || | |
2080 | (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE)) | |
2081 | return -EINVAL; | |
2082 | ||
30efa5a3 | 2083 | /* store the value in ints/second */ |
f7554a2b | 2084 | adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs; |
30efa5a3 JB |
2085 | |
2086 | /* static value of interrupt rate */ | |
f7554a2b | 2087 | adapter->rx_itr_setting = adapter->rx_eitr_param; |
509ee935 | 2088 | /* clear the lower bit as its used for dynamic state */ |
f7554a2b | 2089 | adapter->rx_itr_setting &= ~1; |
30efa5a3 JB |
2090 | } else if (ec->rx_coalesce_usecs == 1) { |
2091 | /* 1 means dynamic mode */ | |
f7554a2b NS |
2092 | adapter->rx_eitr_param = 20000; |
2093 | adapter->rx_itr_setting = 1; | |
30efa5a3 | 2094 | } else { |
509ee935 JB |
2095 | /* |
2096 | * any other value means disable eitr, which is best | |
2097 | * served by setting the interrupt rate very high | |
2098 | */ | |
0a924578 | 2099 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f7554a2b | 2100 | adapter->rx_eitr_param = IXGBE_MAX_RSC_INT_RATE; |
0a924578 | 2101 | else |
f7554a2b NS |
2102 | adapter->rx_eitr_param = IXGBE_MAX_INT_RATE; |
2103 | adapter->rx_itr_setting = 0; | |
2104 | } | |
2105 | ||
2106 | if (ec->tx_coalesce_usecs > 1) { | |
2107 | /* check the limits */ | |
2108 | if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) || | |
2109 | (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE)) | |
2110 | return -EINVAL; | |
2111 | ||
2112 | /* store the value in ints/second */ | |
2113 | adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs; | |
2114 | ||
2115 | /* static value of interrupt rate */ | |
2116 | adapter->tx_itr_setting = adapter->tx_eitr_param; | |
2117 | ||
2118 | /* clear the lower bit as its used for dynamic state */ | |
2119 | adapter->tx_itr_setting &= ~1; | |
2120 | } else if (ec->tx_coalesce_usecs == 1) { | |
2121 | /* 1 means dynamic mode */ | |
2122 | adapter->tx_eitr_param = 10000; | |
2123 | adapter->tx_itr_setting = 1; | |
2124 | } else { | |
2125 | adapter->tx_eitr_param = IXGBE_MAX_INT_RATE; | |
2126 | adapter->tx_itr_setting = 0; | |
30efa5a3 | 2127 | } |
9a799d71 | 2128 | |
237057ad DS |
2129 | /* MSI/MSIx Interrupt Mode */ |
2130 | if (adapter->flags & | |
2131 | (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) { | |
2132 | int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2133 | for (i = 0; i < num_vectors; i++) { | |
2134 | q_vector = adapter->q_vector[i]; | |
2135 | if (q_vector->txr_count && !q_vector->rxr_count) | |
f7554a2b NS |
2136 | /* tx only */ |
2137 | q_vector->eitr = adapter->tx_eitr_param; | |
237057ad DS |
2138 | else |
2139 | /* rx only or mixed */ | |
f7554a2b | 2140 | q_vector->eitr = adapter->rx_eitr_param; |
237057ad DS |
2141 | ixgbe_write_eitr(q_vector); |
2142 | } | |
2143 | /* Legacy Interrupt Mode */ | |
2144 | } else { | |
2145 | q_vector = adapter->q_vector[0]; | |
f7554a2b | 2146 | q_vector->eitr = adapter->rx_eitr_param; |
fe49f04a | 2147 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
2148 | } |
2149 | ||
2150 | return 0; | |
2151 | } | |
2152 | ||
f8212f97 AD |
2153 | static int ixgbe_set_flags(struct net_device *netdev, u32 data) |
2154 | { | |
2155 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a713e7c | 2156 | bool need_reset = false; |
f8212f97 AD |
2157 | |
2158 | ethtool_op_set_flags(netdev, data); | |
2159 | ||
f8212f97 AD |
2160 | /* if state changes we need to update adapter->flags and reset */ |
2161 | if ((!!(data & ETH_FLAG_LRO)) != | |
0c19d6af PWJ |
2162 | (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) { |
2163 | adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED; | |
9a713e7c PW |
2164 | need_reset = true; |
2165 | } | |
2166 | ||
2167 | /* | |
2168 | * Check if Flow Director n-tuple support was enabled or disabled. If | |
2169 | * the state changed, we need to reset. | |
2170 | */ | |
2171 | if ((adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) && | |
2172 | (!(data & ETH_FLAG_NTUPLE))) { | |
2173 | /* turn off Flow Director perfect, set hash and reset */ | |
2174 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
2175 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
2176 | need_reset = true; | |
2177 | } else if ((!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) && | |
2178 | (data & ETH_FLAG_NTUPLE)) { | |
2179 | /* turn off Flow Director hash, enable perfect and reset */ | |
2180 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
2181 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
2182 | need_reset = true; | |
2183 | } else { | |
2184 | /* no state change */ | |
2185 | } | |
2186 | ||
2187 | if (need_reset) { | |
f8212f97 AD |
2188 | if (netif_running(netdev)) |
2189 | ixgbe_reinit_locked(adapter); | |
2190 | else | |
2191 | ixgbe_reset(adapter); | |
2192 | } | |
9a713e7c | 2193 | |
f8212f97 | 2194 | return 0; |
9a713e7c PW |
2195 | } |
2196 | ||
2197 | static int ixgbe_set_rx_ntuple(struct net_device *dev, | |
2198 | struct ethtool_rx_ntuple *cmd) | |
2199 | { | |
2200 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
2201 | struct ethtool_rx_ntuple_flow_spec fs = cmd->fs; | |
2202 | struct ixgbe_atr_input input_struct; | |
2203 | struct ixgbe_atr_input_masks input_masks; | |
2204 | int target_queue; | |
2205 | ||
2206 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
2207 | return -EOPNOTSUPP; | |
2208 | ||
2209 | /* | |
2210 | * Don't allow programming if the action is a queue greater than | |
2211 | * the number of online Tx queues. | |
2212 | */ | |
2213 | if ((fs.action >= adapter->num_tx_queues) || | |
2214 | (fs.action < ETHTOOL_RXNTUPLE_ACTION_DROP)) | |
2215 | return -EINVAL; | |
2216 | ||
2217 | memset(&input_struct, 0, sizeof(struct ixgbe_atr_input)); | |
2218 | memset(&input_masks, 0, sizeof(struct ixgbe_atr_input_masks)); | |
2219 | ||
2220 | input_masks.src_ip_mask = fs.m_u.tcp_ip4_spec.ip4src; | |
2221 | input_masks.dst_ip_mask = fs.m_u.tcp_ip4_spec.ip4dst; | |
2222 | input_masks.src_port_mask = fs.m_u.tcp_ip4_spec.psrc; | |
2223 | input_masks.dst_port_mask = fs.m_u.tcp_ip4_spec.pdst; | |
2224 | input_masks.vlan_id_mask = fs.vlan_tag_mask; | |
2225 | /* only use the lowest 2 bytes for flex bytes */ | |
2226 | input_masks.data_mask = (fs.data_mask & 0xffff); | |
2227 | ||
2228 | switch (fs.flow_type) { | |
2229 | case TCP_V4_FLOW: | |
2230 | ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_TCP); | |
2231 | break; | |
2232 | case UDP_V4_FLOW: | |
2233 | ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_UDP); | |
2234 | break; | |
2235 | case SCTP_V4_FLOW: | |
2236 | ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_SCTP); | |
2237 | break; | |
2238 | default: | |
2239 | return -1; | |
2240 | } | |
f8212f97 | 2241 | |
9a713e7c PW |
2242 | /* Mask bits from the inputs based on user-supplied mask */ |
2243 | ixgbe_atr_set_src_ipv4_82599(&input_struct, | |
2244 | (fs.h_u.tcp_ip4_spec.ip4src & ~fs.m_u.tcp_ip4_spec.ip4src)); | |
2245 | ixgbe_atr_set_dst_ipv4_82599(&input_struct, | |
2246 | (fs.h_u.tcp_ip4_spec.ip4dst & ~fs.m_u.tcp_ip4_spec.ip4dst)); | |
2247 | /* 82599 expects these to be byte-swapped for perfect filtering */ | |
2248 | ixgbe_atr_set_src_port_82599(&input_struct, | |
2249 | ((ntohs(fs.h_u.tcp_ip4_spec.psrc)) & ~fs.m_u.tcp_ip4_spec.psrc)); | |
2250 | ixgbe_atr_set_dst_port_82599(&input_struct, | |
2251 | ((ntohs(fs.h_u.tcp_ip4_spec.pdst)) & ~fs.m_u.tcp_ip4_spec.pdst)); | |
2252 | ||
2253 | /* VLAN and Flex bytes are either completely masked or not */ | |
2254 | if (!fs.vlan_tag_mask) | |
2255 | ixgbe_atr_set_vlan_id_82599(&input_struct, fs.vlan_tag); | |
2256 | ||
2257 | if (!input_masks.data_mask) | |
2258 | /* make sure we only use the first 2 bytes of user data */ | |
2259 | ixgbe_atr_set_flex_byte_82599(&input_struct, | |
2260 | (fs.data & 0xffff)); | |
2261 | ||
2262 | /* determine if we need to drop or route the packet */ | |
2263 | if (fs.action == ETHTOOL_RXNTUPLE_ACTION_DROP) | |
2264 | target_queue = MAX_RX_QUEUES - 1; | |
2265 | else | |
2266 | target_queue = fs.action; | |
2267 | ||
2268 | spin_lock(&adapter->fdir_perfect_lock); | |
2269 | ixgbe_fdir_add_perfect_filter_82599(&adapter->hw, &input_struct, | |
2270 | &input_masks, 0, target_queue); | |
2271 | spin_unlock(&adapter->fdir_perfect_lock); | |
2272 | ||
2273 | return 0; | |
f8212f97 | 2274 | } |
9a799d71 | 2275 | |
b9804972 | 2276 | static const struct ethtool_ops ixgbe_ethtool_ops = { |
9a799d71 AK |
2277 | .get_settings = ixgbe_get_settings, |
2278 | .set_settings = ixgbe_set_settings, | |
2279 | .get_drvinfo = ixgbe_get_drvinfo, | |
2280 | .get_regs_len = ixgbe_get_regs_len, | |
2281 | .get_regs = ixgbe_get_regs, | |
2282 | .get_wol = ixgbe_get_wol, | |
e63d9762 | 2283 | .set_wol = ixgbe_set_wol, |
9a799d71 AK |
2284 | .nway_reset = ixgbe_nway_reset, |
2285 | .get_link = ethtool_op_get_link, | |
2286 | .get_eeprom_len = ixgbe_get_eeprom_len, | |
2287 | .get_eeprom = ixgbe_get_eeprom, | |
2288 | .get_ringparam = ixgbe_get_ringparam, | |
2289 | .set_ringparam = ixgbe_set_ringparam, | |
2290 | .get_pauseparam = ixgbe_get_pauseparam, | |
2291 | .set_pauseparam = ixgbe_set_pauseparam, | |
2292 | .get_rx_csum = ixgbe_get_rx_csum, | |
2293 | .set_rx_csum = ixgbe_set_rx_csum, | |
2294 | .get_tx_csum = ixgbe_get_tx_csum, | |
2295 | .set_tx_csum = ixgbe_set_tx_csum, | |
2296 | .get_sg = ethtool_op_get_sg, | |
2297 | .set_sg = ethtool_op_set_sg, | |
2298 | .get_msglevel = ixgbe_get_msglevel, | |
2299 | .set_msglevel = ixgbe_set_msglevel, | |
2300 | .get_tso = ethtool_op_get_tso, | |
2301 | .set_tso = ixgbe_set_tso, | |
da4dd0f7 | 2302 | .self_test = ixgbe_diag_test, |
9a799d71 AK |
2303 | .get_strings = ixgbe_get_strings, |
2304 | .phys_id = ixgbe_phys_id, | |
b4617240 | 2305 | .get_sset_count = ixgbe_get_sset_count, |
9a799d71 AK |
2306 | .get_ethtool_stats = ixgbe_get_ethtool_stats, |
2307 | .get_coalesce = ixgbe_get_coalesce, | |
2308 | .set_coalesce = ixgbe_set_coalesce, | |
177db6ff | 2309 | .get_flags = ethtool_op_get_flags, |
f8212f97 | 2310 | .set_flags = ixgbe_set_flags, |
9a713e7c | 2311 | .set_rx_ntuple = ixgbe_set_rx_ntuple, |
9a799d71 AK |
2312 | }; |
2313 | ||
2314 | void ixgbe_set_ethtool_ops(struct net_device *netdev) | |
2315 | { | |
2316 | SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops); | |
2317 | } |