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ixgbe: Add ethtool offline test support
[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
34
35#define IXGBE_82599_MAX_TX_QUEUES 128
36#define IXGBE_82599_MAX_RX_QUEUES 128
37#define IXGBE_82599_RAR_ENTRIES 128
38#define IXGBE_82599_MC_TBL_SIZE 128
39#define IXGBE_82599_VFT_TBL_SIZE 128
40
41s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
45s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
46s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed, bool autoneg,
48 bool autoneg_wait_to_complete);
49s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
50s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
51 ixgbe_link_speed *speed,
52 bool *link_up, bool link_up_wait_to_complete);
53s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
54 ixgbe_link_speed speed,
55 bool autoneg,
56 bool autoneg_wait_to_complete);
57static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
58 ixgbe_link_speed *speed,
59 bool *autoneg);
60static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
61static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
62 ixgbe_link_speed speed,
63 bool autoneg,
64 bool autoneg_wait_to_complete);
65s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
66s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
67s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
68s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
69 u32 vind, bool vlan_on);
70s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
11afc1b1
PW		 71s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
72s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
73s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
74s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw);
75s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
76s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
77u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
78
79void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
80{
81 struct ixgbe_mac_info *mac = &hw->mac;
82 if (hw->phy.multispeed_fiber) {
83 /* Set up dual speed SFP+ support */
84 mac->ops.setup_link =
85 &ixgbe_setup_mac_link_multispeed_fiber;
86 mac->ops.setup_link_speed =
87 &ixgbe_setup_mac_link_speed_multispeed_fiber;
88 } else {
89 mac->ops.setup_link =
90 &ixgbe_setup_mac_link_82599;
91 mac->ops.setup_link_speed =
92 &ixgbe_setup_mac_link_speed_82599;
93 }
94}
95
96s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
97{
98 s32 ret_val = 0;
99 u16 list_offset, data_offset, data_value;
100
101 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
102 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 103
104 hw->phy.ops.reset = NULL;
105
11afc1b1
PW		 106 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
107 &data_offset);
108
109 if (ret_val != 0)
110 goto setup_sfp_out;
111
aa5aec88
PWJ		 112 /* PHY config will finish before releasing the semaphore */
113 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
114 if (ret_val != 0) {
115 ret_val = IXGBE_ERR_SWFW_SYNC;
116 goto setup_sfp_out;
117 }
118
11afc1b1
PW		 119 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
120 while (data_value != 0xffff) {
121 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
122 IXGBE_WRITE_FLUSH(hw);
123 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
124 }
1479ad4f
PWJ		 125 /* Now restart DSP by setting Restart_AN */
126 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
127 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
aa5aec88
PWJ		 128
129 /* Release the semaphore */
130 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
131 /* Delay obtaining semaphore again to allow FW access */
132 msleep(hw->eeprom.semaphore_delay);
11afc1b1
PW		 133 }
134
135setup_sfp_out:
136 return ret_val;
137}
138
139/**
140 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
141 * @hw: pointer to hardware structure
142 *
143 * Read PCIe configuration space, and get the MSI-X vector count from
144 * the capabilities table.
145 **/
146u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
147{
148 struct ixgbe_adapter *adapter = hw->back;
149 u16 msix_count;
150 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
151 &msix_count);
152 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
153
154 /* MSI-X count is zero-based in HW, so increment to give proper value */
155 msix_count++;
156
157 return msix_count;
158}
159
160static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
161{
162 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 163
04f165ef 164 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 165
04f165ef
PW		 166 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
167 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
168 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
169 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
170 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
171 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
11afc1b1 172
04f165ef
PW		 173 return 0;
174}
11afc1b1 175
04f165ef
PW		 176/**
177 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
178 * @hw: pointer to hardware structure
179 *
180 * Initialize any function pointers that were not able to be
181 * set during get_invariants because the PHY/SFP type was
182 * not known. Perform the SFP init if necessary.
183 *
184 **/
185s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
186{
187 struct ixgbe_mac_info *mac = &hw->mac;
188 struct ixgbe_phy_info *phy = &hw->phy;
189 s32 ret_val = 0;
11afc1b1 190
04f165ef
PW		 191 /* Identify the PHY or SFP module */
192 ret_val = phy->ops.identify(hw);
193
194 /* Setup function pointers based on detected SFP module and speeds */
195 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 196
197 /* If copper media, overwrite with copper function pointers */
198 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
199 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
200 mac->ops.setup_link_speed =
04f165ef 201 &ixgbe_setup_copper_link_speed_82599;
11afc1b1
PW		 202 mac->ops.get_link_capabilities =
203 &ixgbe_get_copper_link_capabilities_82599;
204 }
205
04f165ef 206 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 207 switch (hw->phy.type) {
208 case ixgbe_phy_tn:
209 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
210 phy->ops.get_firmware_version =
04f165ef 211 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 212 break;
213 default:
214 break;
215 }
216
11afc1b1
PW		 217 return ret_val;
218}
219
220/**
221 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
222 * @hw: pointer to hardware structure
223 * @speed: pointer to link speed
224 * @negotiation: true when autoneg or autotry is enabled
225 *
226 * Determines the link capabilities by reading the AUTOC register.
227 **/
228s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
229 ixgbe_link_speed *speed,
230 bool *negotiation)
231{
232 s32 status = 0;
1eb99d5a 233 u32 autoc = 0;
11afc1b1 234
1eb99d5a
PW		 235 /*
236 * Determine link capabilities based on the stored value of AUTOC,
237 * which represents EEPROM defaults. If AUTOC value has not been
238 * stored, use the current register value.
239 */
240 if (hw->mac.orig_link_settings_stored)
241 autoc = hw->mac.orig_autoc;
242 else
243 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
244
245 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 246 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
247 *speed = IXGBE_LINK_SPEED_1GB_FULL;
248 *negotiation = false;
249 break;
250
251 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
252 *speed = IXGBE_LINK_SPEED_10GB_FULL;
253 *negotiation = false;
254 break;
255
256 case IXGBE_AUTOC_LMS_1G_AN:
257 *speed = IXGBE_LINK_SPEED_1GB_FULL;
258 *negotiation = true;
259 break;
260
261 case IXGBE_AUTOC_LMS_10G_SERIAL:
262 *speed = IXGBE_LINK_SPEED_10GB_FULL;
263 *negotiation = false;
264 break;
265
266 case IXGBE_AUTOC_LMS_KX4_KX_KR:
267 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
268 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 269 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 270 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 271 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 272 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 273 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 274 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
275 *negotiation = true;
276 break;
277
278 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
279 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 280 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 281 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 282 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 283 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 284 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 285 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
286 *negotiation = true;
287 break;
288
289 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
290 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
291 *negotiation = false;
292 break;
293
294 default:
295 status = IXGBE_ERR_LINK_SETUP;
296 goto out;
297 break;
298 }
299
300 if (hw->phy.multispeed_fiber) {
301 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
302 IXGBE_LINK_SPEED_1GB_FULL;
303 *negotiation = true;
304 }
305
306out:
307 return status;
308}
309
310/**
311 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
312 * @hw: pointer to hardware structure
313 * @speed: pointer to link speed
314 * @autoneg: boolean auto-negotiation value
315 *
316 * Determines the link capabilities by reading the AUTOC register.
317 **/
318static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
319 ixgbe_link_speed *speed,
320 bool *autoneg)
321{
322 s32 status = IXGBE_ERR_LINK_SETUP;
323 u16 speed_ability;
324
325 *speed = 0;
326 *autoneg = true;
327
6b73e10d 328 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
11afc1b1
PW		 329 &speed_ability);
330
331 if (status == 0) {
6b73e10d 332 if (speed_ability & MDIO_SPEED_10G)
11afc1b1 333 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
6b73e10d 334 if (speed_ability & MDIO_PMA_SPEED_1000)
11afc1b1
PW		 335 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
336 }
337
338 return status;
339}
340
341/**
342 * ixgbe_get_media_type_82599 - Get media type
343 * @hw: pointer to hardware structure
344 *
345 * Returns the media type (fiber, copper, backplane)
346 **/
347enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
348{
349 enum ixgbe_media_type media_type;
350
351 /* Detect if there is a copper PHY attached. */
352 if (hw->phy.type == ixgbe_phy_cu_unknown ||
353 hw->phy.type == ixgbe_phy_tn) {
354 media_type = ixgbe_media_type_copper;
355 goto out;
356 }
357
358 switch (hw->device_id) {
11afc1b1 359 case IXGBE_DEV_ID_82599_KX4:
1fcf03e6 360 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 361 /* Default device ID is mezzanine card KX/KX4 */
362 media_type = ixgbe_media_type_backplane;
363 break;
364 case IXGBE_DEV_ID_82599_SFP:
365 media_type = ixgbe_media_type_fiber;
366 break;
367 default:
368 media_type = ixgbe_media_type_unknown;
369 break;
370 }
371out:
372 return media_type;
373}
374
375/**
376 * ixgbe_setup_mac_link_82599 - Setup MAC link settings
377 * @hw: pointer to hardware structure
378 *
379 * Configures link settings based on values in the ixgbe_hw struct.
380 * Restarts the link. Performs autonegotiation if needed.
381 **/
382s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
383{
384 u32 autoc_reg;
385 u32 links_reg;
386 u32 i;
387 s32 status = 0;
388
389 /* Restart link */
390 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
391 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
392 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
393
394 /* Only poll for autoneg to complete if specified to do so */
395 if (hw->phy.autoneg_wait_to_complete) {
396 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
397 IXGBE_AUTOC_LMS_KX4_KX_KR ||
398 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
399 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
400 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
401 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
402 links_reg = 0; /* Just in case Autoneg time = 0 */
403 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
404 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
405 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
406 break;
407 msleep(100);
408 }
409 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
410 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
411 hw_dbg(hw, "Autoneg did not complete.\n");
412 }
413 }
414 }
415
416 /* Set up flow control */
417 status = ixgbe_setup_fc_generic(hw, 0);
418
419 /* Add delay to filter out noises during initial link setup */
420 msleep(50);
421
422 return status;
423}
424
425/**
426 * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
427 * @hw: pointer to hardware structure
428 *
429 * Configures link settings based on values in the ixgbe_hw struct.
430 * Restarts the link for multi-speed fiber at 1G speed, if link
431 * fails at 10G.
432 * Performs autonegotiation if needed.
433 **/
434s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
435{
436 s32 status = 0;
437 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
4df10466 438 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw, link_speed,
11afc1b1
PW		 439 true, true);
440 return status;
441}
442
443/**
444 * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
445 * @hw: pointer to hardware structure
446 * @speed: new link speed
447 * @autoneg: true if autonegotiation enabled
448 * @autoneg_wait_to_complete: true when waiting for completion is needed
449 *
450 * Set the link speed in the AUTOC register and restarts link.
451 **/
452s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
453 ixgbe_link_speed speed,
454 bool autoneg,
455 bool autoneg_wait_to_complete)
456{
457 s32 status = 0;
458 ixgbe_link_speed phy_link_speed;
459 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
460 u32 speedcnt = 0;
461 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
462 bool link_up = false;
463 bool negotiation;
464
465 /* Mask off requested but non-supported speeds */
466 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
467 speed &= phy_link_speed;
468
469 /*
470 * Try each speed one by one, highest priority first. We do this in
471 * software because 10gb fiber doesn't support speed autonegotiation.
472 */
473 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
474 speedcnt++;
475 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
476
477 /* Set hardware SDP's */
478 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
479 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
480
481 ixgbe_setup_mac_link_speed_82599(hw,
482 IXGBE_LINK_SPEED_10GB_FULL,
483 autoneg,
484 autoneg_wait_to_complete);
485
486 msleep(50);
487
488 /* If we have link, just jump out */
489 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
490 if (link_up)
491 goto out;
492 }
493
494 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
495 speedcnt++;
496 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
497 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
498
499 /* Set hardware SDP's */
500 esdp_reg &= ~IXGBE_ESDP_SDP5;
501 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
502 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
503
504 ixgbe_setup_mac_link_speed_82599(
505 hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg,
506 autoneg_wait_to_complete);
507
508 msleep(50);
509
510 /* If we have link, just jump out */
511 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
512 if (link_up)
513 goto out;
514 }
515
516 /*
517 * We didn't get link. Configure back to the highest speed we tried,
518 * (if there was more than one). We call ourselves back with just the
519 * single highest speed that the user requested.
520 */
521 if (speedcnt > 1)
522 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
523 highest_link_speed,
524 autoneg,
525 autoneg_wait_to_complete);
526
527out:
528 return status;
529}
530
531/**
532 * ixgbe_check_mac_link_82599 - Determine link and speed status
533 * @hw: pointer to hardware structure
534 * @speed: pointer to link speed
535 * @link_up: true when link is up
536 * @link_up_wait_to_complete: bool used to wait for link up or not
537 *
538 * Reads the links register to determine if link is up and the current speed
539 **/
540s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
541 bool *link_up, bool link_up_wait_to_complete)
542{
543 u32 links_reg;
544 u32 i;
545
546 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
547 if (link_up_wait_to_complete) {
548 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
549 if (links_reg & IXGBE_LINKS_UP) {
550 *link_up = true;
551 break;
552 } else {
553 *link_up = false;
554 }
555 msleep(100);
556 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
557 }
558 } else {
559 if (links_reg & IXGBE_LINKS_UP)
560 *link_up = true;
561 else
562 *link_up = false;
563 }
564
565 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
566 IXGBE_LINKS_SPEED_10G_82599)
567 *speed = IXGBE_LINK_SPEED_10GB_FULL;
568 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
569 IXGBE_LINKS_SPEED_1G_82599)
570 *speed = IXGBE_LINK_SPEED_1GB_FULL;
571 else
572 *speed = IXGBE_LINK_SPEED_100_FULL;
573
574
575 return 0;
576}
577
578/**
579 * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
580 * @hw: pointer to hardware structure
581 * @speed: new link speed
582 * @autoneg: true if autonegotiation enabled
583 * @autoneg_wait_to_complete: true when waiting for completion is needed
584 *
585 * Set the link speed in the AUTOC register and restarts link.
586 **/
587s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
588 ixgbe_link_speed speed, bool autoneg,
589 bool autoneg_wait_to_complete)
590{
591 s32 status = 0;
592 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
593 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1eb99d5a 594 u32 orig_autoc = 0;
11afc1b1
PW		 595 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
596 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
597 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
598 u32 links_reg;
599 u32 i;
600 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
601
602 /* Check to see if speed passed in is supported. */
603 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
604 speed &= link_capabilities;
605
1eb99d5a
PW		 606 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
607 if (hw->mac.orig_link_settings_stored)
608 orig_autoc = hw->mac.orig_autoc;
609 else
610 orig_autoc = autoc;
611
612
11afc1b1
PW		 613 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
614 status = IXGBE_ERR_LINK_SETUP;
615 } else if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
616 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
617 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
618 /* Set KX4/KX/KR support according to speed requested */
619 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
620 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 621 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 622 autoc |= IXGBE_AUTOC_KX4_SUPP;
1eb99d5a 623 if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1
PW		 624 autoc |= IXGBE_AUTOC_KR_SUPP;
625 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
626 autoc |= IXGBE_AUTOC_KX_SUPP;
627 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
628 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
629 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
630 /* Switch from 1G SFI to 10G SFI if requested */
631 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
632 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
633 autoc &= ~IXGBE_AUTOC_LMS_MASK;
634 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
635 }
636 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
637 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
638 /* Switch from 10G SFI to 1G SFI if requested */
639 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
640 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
641 autoc &= ~IXGBE_AUTOC_LMS_MASK;
642 if (autoneg)
643 autoc |= IXGBE_AUTOC_LMS_1G_AN;
644 else
645 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
646 }
647 }
648
649 if (status == 0) {
650 /* Restart link */
651 autoc |= IXGBE_AUTOC_AN_RESTART;
652 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
653
654 /* Only poll for autoneg to complete if specified to do so */
655 if (autoneg_wait_to_complete) {
656 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
657 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
658 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
659 links_reg = 0; /*Just in case Autoneg time=0*/
660 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
661 links_reg =
662 IXGBE_READ_REG(hw, IXGBE_LINKS);
663 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
664 break;
665 msleep(100);
666 }
667 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
668 status =
669 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
670 hw_dbg(hw, "Autoneg did not "
671 "complete.\n");
672 }
673 }
674 }
675
676 /* Set up flow control */
677 status = ixgbe_setup_fc_generic(hw, 0);
678
679 /* Add delay to filter out noises during initial link setup */
680 msleep(50);
681 }
682
683 return status;
684}
685
686/**
687 * ixgbe_setup_copper_link_82599 - Setup copper link settings
688 * @hw: pointer to hardware structure
689 *
690 * Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
691 **/
692static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
693{
694 s32 status;
695
696 /* Restart autonegotiation on PHY */
697 status = hw->phy.ops.setup_link(hw);
698
699 /* Set up MAC */
700 ixgbe_setup_mac_link_82599(hw);
701
702 return status;
703}
704
705/**
706 * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
707 * @hw: pointer to hardware structure
708 * @speed: new link speed
709 * @autoneg: true if autonegotiation enabled
710 * @autoneg_wait_to_complete: true if waiting is needed to complete
711 *
712 * Restarts link on PHY and MAC based on settings passed in.
713 **/
714static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
715 ixgbe_link_speed speed,
716 bool autoneg,
717 bool autoneg_wait_to_complete)
718{
719 s32 status;
720
721 /* Setup the PHY according to input speed */
722 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
723 autoneg_wait_to_complete);
724 /* Set up MAC */
725 ixgbe_setup_mac_link_82599(hw);
726
727 return status;
728}
729
730/**
731 * ixgbe_reset_hw_82599 - Perform hardware reset
732 * @hw: pointer to hardware structure
733 *
734 * Resets the hardware by resetting the transmit and receive units, masks
735 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
736 * reset.
737 **/
738s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
739{
740 s32 status = 0;
741 u32 ctrl, ctrl_ext;
742 u32 i;
743 u32 autoc;
744 u32 autoc2;
745
746 /* Call adapter stop to disable tx/rx and clear interrupts */
747 hw->mac.ops.stop_adapter(hw);
748
553b4497 749 /* PHY ops must be identified and initialized prior to reset */
04f165ef 750
553b4497
PW		 751 /* Init PHY and function pointers, perform SFP setup */
752 status = hw->phy.ops.init(hw);
04f165ef 753
553b4497
PW		 754 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
755 goto reset_hw_out;
04f165ef 756
553b4497
PW		 757 /* Setup SFP module if there is one present. */
758 if (hw->phy.sfp_setup_needed) {
759 status = hw->mac.ops.setup_sfp(hw);
760 hw->phy.sfp_setup_needed = false;
04f165ef 761 }
11afc1b1 762
553b4497
PW		 763 /* Reset PHY */
764 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
765 hw->phy.ops.reset(hw);
766
11afc1b1
PW		 767 /*
768 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
769 * access and verify no pending requests before reset
770 */
04f165ef
PW		 771 status = ixgbe_disable_pcie_master(hw);
772 if (status != 0) {
11afc1b1
PW		 773 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
774 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
775 }
776
777 /*
778 * Issue global reset to the MAC. This needs to be a SW reset.
779 * If link reset is used, it might reset the MAC when mng is using it
780 */
781 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
782 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
783 IXGBE_WRITE_FLUSH(hw);
784
785 /* Poll for reset bit to self-clear indicating reset is complete */
786 for (i = 0; i < 10; i++) {
787 udelay(1);
788 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
789 if (!(ctrl & IXGBE_CTRL_RST))
790 break;
791 }
792 if (ctrl & IXGBE_CTRL_RST) {
793 status = IXGBE_ERR_RESET_FAILED;
794 hw_dbg(hw, "Reset polling failed to complete.\n");
795 }
796 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
797 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
798 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
799 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
800
801 msleep(50);
802
803
804
805 /*
806 * Store the original AUTOC/AUTOC2 values if they have not been
807 * stored off yet. Otherwise restore the stored original
808 * values since the reset operation sets back to defaults.
809 */
810 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
811 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
812 if (hw->mac.orig_link_settings_stored == false) {
813 hw->mac.orig_autoc = autoc;
814 hw->mac.orig_autoc2 = autoc2;
815 hw->mac.orig_link_settings_stored = true;
4df10466 816 } else {
11afc1b1
PW		 817 if (autoc != hw->mac.orig_autoc)
818 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
819 IXGBE_AUTOC_AN_RESTART));
820
821 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
822 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
823 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
824 autoc2 |= (hw->mac.orig_autoc2 &
825 IXGBE_AUTOC2_UPPER_MASK);
826 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
827 }
828 }
829
aca6bee7
WJP		 830 /*
831 * Store MAC address from RAR0, clear receive address registers, and
832 * clear the multicast table. Also reset num_rar_entries to 128,
833 * since we modify this value when programming the SAN MAC address.
834 */
835 hw->mac.num_rar_entries = 128;
836 hw->mac.ops.init_rx_addrs(hw);
837
11afc1b1
PW		 838 /* Store the permanent mac address */
839 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
840
0365e6e4
PW		 841 /* Store the permanent SAN mac address */
842 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
843
aca6bee7
WJP		 844 /* Add the SAN MAC address to the RAR only if it's a valid address */
845 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
846 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
847 hw->mac.san_addr, 0, IXGBE_RAH_AV);
848
849 /* Reserve the last RAR for the SAN MAC address */
850 hw->mac.num_rar_entries--;
851 }
852
04f165ef 853reset_hw_out:
11afc1b1
PW		 854 return status;
855}
856
857/**
858 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
859 * @hw: pointer to hardware struct
860 * @rar: receive address register index to disassociate
861 * @vmdq: VMDq pool index to remove from the rar
862 **/
863s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
864{
865 u32 mpsar_lo, mpsar_hi;
866 u32 rar_entries = hw->mac.num_rar_entries;
867
868 if (rar < rar_entries) {
869 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
870 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
871
872 if (!mpsar_lo && !mpsar_hi)
873 goto done;
874
875 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
876 if (mpsar_lo) {
877 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
878 mpsar_lo = 0;
879 }
880 if (mpsar_hi) {
881 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
882 mpsar_hi = 0;
883 }
884 } else if (vmdq < 32) {
885 mpsar_lo &= ~(1 << vmdq);
886 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
887 } else {
888 mpsar_hi &= ~(1 << (vmdq - 32));
889 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
890 }
891
892 /* was that the last pool using this rar? */
893 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
894 hw->mac.ops.clear_rar(hw, rar);
895 } else {
896 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
897 }
898
899done:
900 return 0;
901}
902
903/**
904 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
905 * @hw: pointer to hardware struct
906 * @rar: receive address register index to associate with a VMDq index
907 * @vmdq: VMDq pool index
908 **/
909s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
910{
911 u32 mpsar;
912 u32 rar_entries = hw->mac.num_rar_entries;
913
914 if (rar < rar_entries) {
915 if (vmdq < 32) {
916 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
917 mpsar |= 1 << vmdq;
918 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
919 } else {
920 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
921 mpsar |= 1 << (vmdq - 32);
922 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
923 }
924 } else {
925 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
926 }
927 return 0;
928}
929
930/**
931 * ixgbe_set_vfta_82599 - Set VLAN filter table
932 * @hw: pointer to hardware structure
933 * @vlan: VLAN id to write to VLAN filter
934 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
935 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
936 *
937 * Turn on/off specified VLAN in the VLAN filter table.
938 **/
939s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
940 bool vlan_on)
941{
942 u32 regindex;
943 u32 bitindex;
944 u32 bits;
945 u32 first_empty_slot;
946
947 if (vlan > 4095)
948 return IXGBE_ERR_PARAM;
949
950 /*
951 * this is a 2 part operation - first the VFTA, then the
952 * VLVF and VLVFB if vind is set
953 */
954
955 /* Part 1
956 * The VFTA is a bitstring made up of 128 32-bit registers
957 * that enable the particular VLAN id, much like the MTA:
958 * bits[11-5]: which register
959 * bits[4-0]: which bit in the register
960 */
961 regindex = (vlan >> 5) & 0x7F;
962 bitindex = vlan & 0x1F;
963 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
964 if (vlan_on)
965 bits |= (1 << bitindex);
966 else
967 bits &= ~(1 << bitindex);
968 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
969
970
971 /* Part 2
972 * If the vind is set
973 * Either vlan_on
974 * make sure the vlan is in VLVF
975 * set the vind bit in the matching VLVFB
976 * Or !vlan_on
977 * clear the pool bit and possibly the vind
978 */
979 if (vind) {
980 /* find the vlanid or the first empty slot */
981 first_empty_slot = 0;
982
983 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
984 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
985 if (!bits && !first_empty_slot)
986 first_empty_slot = regindex;
987 else if ((bits & 0x0FFF) == vlan)
988 break;
989 }
990
991 if (regindex >= IXGBE_VLVF_ENTRIES) {
992 if (first_empty_slot)
993 regindex = first_empty_slot;
994 else {
995 hw_dbg(hw, "No space in VLVF.\n");
996 goto out;
997 }
998 }
999
1000 if (vlan_on) {
1001 /* set the pool bit */
1002 if (vind < 32) {
1003 bits = IXGBE_READ_REG(hw,
1004 IXGBE_VLVFB(regindex * 2));
1005 bits |= (1 << vind);
1006 IXGBE_WRITE_REG(hw,
1007 IXGBE_VLVFB(regindex * 2), bits);
1008 } else {
1009 bits = IXGBE_READ_REG(hw,
1010 IXGBE_VLVFB((regindex * 2) + 1));
1011 bits |= (1 << vind);
1012 IXGBE_WRITE_REG(hw,
1013 IXGBE_VLVFB((regindex * 2) + 1), bits);
1014 }
1015 } else {
1016 /* clear the pool bit */
1017 if (vind < 32) {
1018 bits = IXGBE_READ_REG(hw,
1019 IXGBE_VLVFB(regindex * 2));
1020 bits &= ~(1 << vind);
1021 IXGBE_WRITE_REG(hw,
1022 IXGBE_VLVFB(regindex * 2), bits);
1023 bits |= IXGBE_READ_REG(hw,
1024 IXGBE_VLVFB((regindex * 2) + 1));
1025 } else {
1026 bits = IXGBE_READ_REG(hw,
1027 IXGBE_VLVFB((regindex * 2) + 1));
1028 bits &= ~(1 << vind);
1029 IXGBE_WRITE_REG(hw,
1030 IXGBE_VLVFB((regindex * 2) + 1), bits);
1031 bits |= IXGBE_READ_REG(hw,
1032 IXGBE_VLVFB(regindex * 2));
1033 }
1034 }
1035
1036 if (bits)
1037 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1038 (IXGBE_VLVF_VIEN | vlan));
1039 else
1040 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1041 }
1042
1043out:
1044 return 0;
1045}
1046
1047/**
1048 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1049 * @hw: pointer to hardware structure
1050 *
1051 * Clears the VLAN filer table, and the VMDq index associated with the filter
1052 **/
1053s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1054{
1055 u32 offset;
1056
1057 for (offset = 0; offset < hw->mac.vft_size; offset++)
1058 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1059
1060 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1061 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1062 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1063 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1064 }
1065
1066 return 0;
1067}
1068
11afc1b1
PW		 1069/**
1070 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1071 * @hw: pointer to hardware structure
1072 **/
1073s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1074{
1075 int i;
1076 hw_dbg(hw, " Clearing UTA\n");
1077
1078 for (i = 0; i < 128; i++)
1079 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1080
1081 return 0;
1082}
1083
1084/**
1085 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1086 * @hw: pointer to hardware structure
1087 * @reg: analog register to read
1088 * @val: read value
1089 *
1090 * Performs read operation to Omer analog register specified.
1091 **/
1092s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1093{
1094 u32 core_ctl;
1095
1096 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1097 (reg << 8));
1098 IXGBE_WRITE_FLUSH(hw);
1099 udelay(10);
1100 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1101 *val = (u8)core_ctl;
1102
1103 return 0;
1104}
1105
1106/**
1107 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1108 * @hw: pointer to hardware structure
1109 * @reg: atlas register to write
1110 * @val: value to write
1111 *
1112 * Performs write operation to Omer analog register specified.
1113 **/
1114s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1115{
1116 u32 core_ctl;
1117
1118 core_ctl = (reg << 8) | val;
1119 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1120 IXGBE_WRITE_FLUSH(hw);
1121 udelay(10);
1122
1123 return 0;
1124}
1125
1126/**
1127 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1128 * @hw: pointer to hardware structure
1129 *
1130 * Starts the hardware using the generic start_hw function.
1131 * Then performs device-specific:
1132 * Clears the rate limiter registers.
1133 **/
1134s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1135{
1136 u32 q_num;
1137
1138 ixgbe_start_hw_generic(hw);
1139
1140 /* Clear the rate limiters */
1141 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1142 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1143 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1144 }
1145 IXGBE_WRITE_FLUSH(hw);
1146
1147 return 0;
1148}
1149
1150/**
1151 * ixgbe_identify_phy_82599 - Get physical layer module
1152 * @hw: pointer to hardware structure
1153 *
1154 * Determines the physical layer module found on the current adapter.
1155 **/
1156s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1157{
1158 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1159 status = ixgbe_identify_phy_generic(hw);
1160 if (status != 0)
1161 status = ixgbe_identify_sfp_module_generic(hw);
1162 return status;
1163}
1164
1165/**
1166 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1167 * @hw: pointer to hardware structure
1168 *
1169 * Determines physical layer capabilities of the current configuration.
1170 **/
1171u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1172{
1173 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 1174 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1175 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1176 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1177 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1178 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1179 u16 ext_ability = 0;
1339b9e9 1180 u8 comp_codes_10g = 0;
11afc1b1 1181
04193058
PWJ		 1182 hw->phy.ops.identify(hw);
1183
1184 if (hw->phy.type == ixgbe_phy_tn ||
1185 hw->phy.type == ixgbe_phy_cu_unknown) {
6b73e10d
BH		 1186 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1187 &ext_ability);
1188 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 1189 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 1190 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 1191 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 1192 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 1193 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1194 goto out;
1195 }
1196
1197 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1198 case IXGBE_AUTOC_LMS_1G_AN:
1199 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1200 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1201 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1202 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1203 goto out;
1204 } else
1205 /* SFI mode so read SFP module */
1206 goto sfp_check;
11afc1b1 1207 break;
04193058
PWJ		 1208 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1209 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1210 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1211 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1212 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 1213 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1214 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 1215 goto out;
1216 break;
1217 case IXGBE_AUTOC_LMS_10G_SERIAL:
1218 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1219 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1220 goto out;
1221 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1222 goto sfp_check;
1223 break;
1224 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1225 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1226 if (autoc & IXGBE_AUTOC_KX_SUPP)
1227 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1228 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1229 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1230 if (autoc & IXGBE_AUTOC_KR_SUPP)
1231 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1232 goto out;
1233 break;
1234 default:
1235 goto out;
1236 break;
1237 }
11afc1b1 1238
04193058
PWJ		 1239sfp_check:
1240 /* SFP check must be done last since DA modules are sometimes used to
1241 * test KR mode - we need to id KR mode correctly before SFP module.
1242 * Call identify_sfp because the pluggable module may have changed */
1243 hw->phy.ops.identify_sfp(hw);
1244 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1245 goto out;
1246
1247 switch (hw->phy.type) {
1248 case ixgbe_phy_tw_tyco:
1249 case ixgbe_phy_tw_unknown:
1250 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1251 break;
1252 case ixgbe_phy_sfp_avago:
1253 case ixgbe_phy_sfp_ftl:
1254 case ixgbe_phy_sfp_intel:
1255 case ixgbe_phy_sfp_unknown:
1256 hw->phy.ops.read_i2c_eeprom(hw,
1257 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1258 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 1259 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 1260 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 1261 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
11afc1b1
PW		 1262 break;
1263 default:
11afc1b1
PW		 1264 break;
1265 }
1266
04193058 1267out:
11afc1b1
PW		 1268 return physical_layer;
1269}
1270
1271/**
1272 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1273 * @hw: pointer to hardware structure
1274 * @regval: register value to write to RXCTRL
1275 *
1276 * Enables the Rx DMA unit for 82599
1277 **/
1278s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1279{
1280#define IXGBE_MAX_SECRX_POLL 30
1281 int i;
1282 int secrxreg;
1283
1284 /*
1285 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1286 * If traffic is incoming before we enable the Rx unit, it could hang
1287 * the Rx DMA unit. Therefore, make sure the security engine is
1288 * completely disabled prior to enabling the Rx unit.
1289 */
1290 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1291 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1292 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1293 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1294 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1295 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1296 break;
1297 else
1298 udelay(10);
1299 }
1300
1301 /* For informational purposes only */
1302 if (i >= IXGBE_MAX_SECRX_POLL)
1303 hw_dbg(hw, "Rx unit being enabled before security "
1304 "path fully disabled. Continuing with init.\n");
1305
1306 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1307 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1308 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1309 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1310 IXGBE_WRITE_FLUSH(hw);
1311
1312 return 0;
1313}
1314
04193058
PWJ		 1315/**
1316 * ixgbe_get_device_caps_82599 - Get additional device capabilities
1317 * @hw: pointer to hardware structure
1318 * @device_caps: the EEPROM word with the extra device capabilities
1319 *
1320 * This function will read the EEPROM location for the device capabilities,
1321 * and return the word through device_caps.
1322 **/
1323s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
1324{
1325 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
1326
1327 return 0;
1328}
1329
0365e6e4
PW		 1330/**
1331 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
1332 * @hw: pointer to hardware structure
1333 * @san_mac_offset: SAN MAC address offset
1334 *
1335 * This function will read the EEPROM location for the SAN MAC address
1336 * pointer, and returns the value at that location. This is used in both
1337 * get and set mac_addr routines.
1338 **/
1339s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
1340 u16 *san_mac_offset)
1341{
1342 /*
1343 * First read the EEPROM pointer to see if the MAC addresses are
1344 * available.
1345 */
1346 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
1347
1348 return 0;
1349}
1350
1351/**
1352 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
1353 * @hw: pointer to hardware structure
1354 * @san_mac_addr: SAN MAC address
1355 *
1356 * Reads the SAN MAC address from the EEPROM, if it's available. This is
1357 * per-port, so set_lan_id() must be called before reading the addresses.
1358 * set_lan_id() is called by identify_sfp(), but this cannot be relied
1359 * upon for non-SFP connections, so we must call it here.
1360 **/
1361s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
1362{
1363 u16 san_mac_data, san_mac_offset;
1364 u8 i;
1365
1366 /*
1367 * First read the EEPROM pointer to see if the MAC addresses are
1368 * available. If they're not, no point in calling set_lan_id() here.
1369 */
1370 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
1371
1372 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
1373 /*
1374 * No addresses available in this EEPROM. It's not an
1375 * error though, so just wipe the local address and return.
1376 */
1377 for (i = 0; i < 6; i++)
1378 san_mac_addr[i] = 0xFF;
1379
1380 goto san_mac_addr_out;
1381 }
1382
1383 /* make sure we know which port we need to program */
1384 hw->mac.ops.set_lan_id(hw);
1385 /* apply the port offset to the address offset */
1386 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1387 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1388 for (i = 0; i < 3; i++) {
1389 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
1390 san_mac_addr[i * 2] = (u8)(san_mac_data);
1391 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
1392 san_mac_offset++;
1393 }
1394
1395san_mac_addr_out:
1396 return 0;
1397}
1398
11afc1b1
PW		 1399static struct ixgbe_mac_operations mac_ops_82599 = {
1400 .init_hw = &ixgbe_init_hw_generic,
1401 .reset_hw = &ixgbe_reset_hw_82599,
1402 .start_hw = &ixgbe_start_hw_82599,
1403 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1404 .get_media_type = &ixgbe_get_media_type_82599,
1405 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1406 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
1407 .get_mac_addr = &ixgbe_get_mac_addr_generic,
0365e6e4 1408 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
04193058 1409 .get_device_caps = &ixgbe_get_device_caps_82599,
11afc1b1
PW		 1410 .stop_adapter = &ixgbe_stop_adapter_generic,
1411 .get_bus_info = &ixgbe_get_bus_info_generic,
1412 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
1413 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
1414 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
1415 .setup_link = &ixgbe_setup_mac_link_82599,
1416 .setup_link_speed = &ixgbe_setup_mac_link_speed_82599,
1417 .check_link = &ixgbe_check_mac_link_82599,
1418 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
1419 .led_on = &ixgbe_led_on_generic,
1420 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 1421 .blink_led_start = &ixgbe_blink_led_start_generic,
1422 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 1423 .set_rar = &ixgbe_set_rar_generic,
1424 .clear_rar = &ixgbe_clear_rar_generic,
1425 .set_vmdq = &ixgbe_set_vmdq_82599,
1426 .clear_vmdq = &ixgbe_clear_vmdq_82599,
1427 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1428 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1429 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1430 .enable_mc = &ixgbe_enable_mc_generic,
1431 .disable_mc = &ixgbe_disable_mc_generic,
1432 .clear_vfta = &ixgbe_clear_vfta_82599,
1433 .set_vfta = &ixgbe_set_vfta_82599,
1434 .setup_fc = &ixgbe_setup_fc_generic,
1435 .init_uta_tables = &ixgbe_init_uta_tables_82599,
1436 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
1437};
1438
1439static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
1440 .init_params = &ixgbe_init_eeprom_params_generic,
1441 .read = &ixgbe_read_eeprom_generic,
1442 .write = &ixgbe_write_eeprom_generic,
1443 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1444 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1445};
1446
1447static struct ixgbe_phy_operations phy_ops_82599 = {
1448 .identify = &ixgbe_identify_phy_82599,
1449 .identify_sfp = &ixgbe_identify_sfp_module_generic,
04f165ef 1450 .init = &ixgbe_init_phy_ops_82599,
11afc1b1
PW		 1451 .reset = &ixgbe_reset_phy_generic,
1452 .read_reg = &ixgbe_read_phy_reg_generic,
1453 .write_reg = &ixgbe_write_phy_reg_generic,
1454 .setup_link = &ixgbe_setup_phy_link_generic,
1455 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1456 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
1457 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
1458 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
1459 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
1460};
1461
1462struct ixgbe_info ixgbe_82599_info = {
1463 .mac = ixgbe_mac_82599EB,
1464 .get_invariants = &ixgbe_get_invariants_82599,
1465 .mac_ops = &mac_ops_82599,
1466 .eeprom_ops = &eeprom_ops_82599,
1467 .phy_ops = &phy_ops_82599,
1468};
Linux 6.x block layer and io_uring tree(s)