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ixgbe: fix 82599 KR downshift coexistence with LESM FW module
[linux-2.6-block.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
11afc1b1
PW		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
096a58fd 34#include "ixgbe_mbx.h"
11afc1b1
PW		 35
36#define IXGBE_82599_MAX_TX_QUEUES 128
37#define IXGBE_82599_MAX_RX_QUEUES 128
38#define IXGBE_82599_RAR_ENTRIES 128
39#define IXGBE_82599_MC_TBL_SIZE 128
40#define IXGBE_82599_VFT_TBL_SIZE 128
41
5d5b7c39
ET		 42static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
43static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
cd7e1f0b
DS		 49static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg,
52 bool autoneg_wait_to_complete);
5d5b7c39
ET		 53static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
8620a103
MC		 56 ixgbe_link_speed speed,
57 bool autoneg,
58 bool autoneg_wait_to_complete);
8620a103
MC		 59static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed speed,
61 bool autoneg,
62 bool autoneg_wait_to_complete);
794caeb2 63static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
0fa6d832 64static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
11afc1b1 65
7b25cdba 66static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 67{
68 struct ixgbe_mac_info *mac = &hw->mac;
c6ecf39a
DS		 69
70 /* enable the laser control functions for SFP+ fiber */
71 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
61fac744
PW		 72 mac->ops.disable_tx_laser =
73 &ixgbe_disable_tx_laser_multispeed_fiber;
74 mac->ops.enable_tx_laser =
75 &ixgbe_enable_tx_laser_multispeed_fiber;
1097cd17 76 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
11afc1b1 77 } else {
61fac744
PW		 78 mac->ops.disable_tx_laser = NULL;
79 mac->ops.enable_tx_laser = NULL;
1097cd17 80 mac->ops.flap_tx_laser = NULL;
c6ecf39a
DS		 81 }
82
83 if (hw->phy.multispeed_fiber) {
84 /* Set up dual speed SFP+ support */
85 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
86 } else {
cd7e1f0b
DS		 87 if ((mac->ops.get_media_type(hw) ==
88 ixgbe_media_type_backplane) &&
89 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
0fa6d832
ET		 90 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
91 !ixgbe_verify_lesm_fw_enabled_82599(hw))
cd7e1f0b
DS		 92 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
93 else
94 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
11afc1b1
PW		 95 }
96}
97
7b25cdba 98static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 99{
100 s32 ret_val = 0;
a7f5a5fc
DS		 101 u32 reg_anlp1 = 0;
102 u32 i = 0;
11afc1b1
PW		 103 u16 list_offset, data_offset, data_value;
104
105 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
106 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 107
108 hw->phy.ops.reset = NULL;
109
11afc1b1
PW		 110 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
111 &data_offset);
112
113 if (ret_val != 0)
114 goto setup_sfp_out;
115
aa5aec88 116 /* PHY config will finish before releasing the semaphore */
5e655105
DS		 117 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
118 IXGBE_GSSR_MAC_CSR_SM);
aa5aec88
PWJ		 119 if (ret_val != 0) {
120 ret_val = IXGBE_ERR_SWFW_SYNC;
121 goto setup_sfp_out;
122 }
123
11afc1b1
PW		 124 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
125 while (data_value != 0xffff) {
126 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
127 IXGBE_WRITE_FLUSH(hw);
128 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
129 }
aa5aec88
PWJ		 130
131 /* Release the semaphore */
132 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
133 /* Delay obtaining semaphore again to allow FW access */
134 msleep(hw->eeprom.semaphore_delay);
a7f5a5fc
DS		 135
136 /* Now restart DSP by setting Restart_AN and clearing LMS */
137 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
138 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
139 IXGBE_AUTOC_AN_RESTART));
140
141 /* Wait for AN to leave state 0 */
142 for (i = 0; i < 10; i++) {
143 msleep(4);
144 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
145 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
146 break;
147 }
148 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
149 hw_dbg(hw, "sfp module setup not complete\n");
150 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
151 goto setup_sfp_out;
152 }
153
154 /* Restart DSP by setting Restart_AN and return to SFI mode */
155 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
156 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
157 IXGBE_AUTOC_AN_RESTART));
11afc1b1
PW		 158 }
159
160setup_sfp_out:
161 return ret_val;
162}
163
11afc1b1
PW		 164static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
165{
166 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 167
04f165ef 168 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 169
04f165ef
PW		 170 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
171 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
172 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
173 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
174 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
21ce849b 175 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
11afc1b1 176
04f165ef
PW		 177 return 0;
178}
11afc1b1 179
04f165ef
PW		 180/**
181 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
182 * @hw: pointer to hardware structure
183 *
184 * Initialize any function pointers that were not able to be
185 * set during get_invariants because the PHY/SFP type was
186 * not known. Perform the SFP init if necessary.
187 *
188 **/
7b25cdba 189static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
04f165ef
PW		 190{
191 struct ixgbe_mac_info *mac = &hw->mac;
192 struct ixgbe_phy_info *phy = &hw->phy;
193 s32 ret_val = 0;
11afc1b1 194
04f165ef
PW		 195 /* Identify the PHY or SFP module */
196 ret_val = phy->ops.identify(hw);
197
198 /* Setup function pointers based on detected SFP module and speeds */
199 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 200
201 /* If copper media, overwrite with copper function pointers */
202 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
203 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
11afc1b1 204 mac->ops.get_link_capabilities =
a391f1d5 205 &ixgbe_get_copper_link_capabilities_generic;
11afc1b1
PW		 206 }
207
04f165ef 208 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 209 switch (hw->phy.type) {
210 case ixgbe_phy_tn:
211 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
212 phy->ops.get_firmware_version =
04f165ef 213 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1 214 break;
fe15e8e1
DS		 215 case ixgbe_phy_aq:
216 phy->ops.get_firmware_version =
217 &ixgbe_get_phy_firmware_version_generic;
218 break;
11afc1b1
PW		 219 default:
220 break;
221 }
222
11afc1b1
PW		 223 return ret_val;
224}
225
226/**
227 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
228 * @hw: pointer to hardware structure
229 * @speed: pointer to link speed
230 * @negotiation: true when autoneg or autotry is enabled
231 *
232 * Determines the link capabilities by reading the AUTOC register.
233 **/
7b25cdba
DS		 234static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
235 ixgbe_link_speed *speed,
236 bool *negotiation)
11afc1b1
PW		 237{
238 s32 status = 0;
1eb99d5a 239 u32 autoc = 0;
11afc1b1 240
cb836a97
DS		 241 /* Determine 1G link capabilities off of SFP+ type */
242 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
243 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
244 *speed = IXGBE_LINK_SPEED_1GB_FULL;
245 *negotiation = true;
246 goto out;
247 }
248
1eb99d5a
PW		 249 /*
250 * Determine link capabilities based on the stored value of AUTOC,
251 * which represents EEPROM defaults. If AUTOC value has not been
252 * stored, use the current register value.
253 */
254 if (hw->mac.orig_link_settings_stored)
255 autoc = hw->mac.orig_autoc;
256 else
257 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
258
259 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 260 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
261 *speed = IXGBE_LINK_SPEED_1GB_FULL;
262 *negotiation = false;
263 break;
264
265 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
266 *speed = IXGBE_LINK_SPEED_10GB_FULL;
267 *negotiation = false;
268 break;
269
270 case IXGBE_AUTOC_LMS_1G_AN:
271 *speed = IXGBE_LINK_SPEED_1GB_FULL;
272 *negotiation = true;
273 break;
274
275 case IXGBE_AUTOC_LMS_10G_SERIAL:
276 *speed = IXGBE_LINK_SPEED_10GB_FULL;
277 *negotiation = false;
278 break;
279
280 case IXGBE_AUTOC_LMS_KX4_KX_KR:
281 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
282 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 283 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 284 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 285 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 286 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 287 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 288 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
289 *negotiation = true;
290 break;
291
292 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
293 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 294 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 295 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 296 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 297 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 298 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 299 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
300 *negotiation = true;
301 break;
302
303 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
304 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
305 *negotiation = false;
306 break;
307
308 default:
309 status = IXGBE_ERR_LINK_SETUP;
310 goto out;
311 break;
312 }
313
314 if (hw->phy.multispeed_fiber) {
315 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
316 IXGBE_LINK_SPEED_1GB_FULL;
317 *negotiation = true;
318 }
319
320out:
321 return status;
322}
323
11afc1b1
PW		 324/**
325 * ixgbe_get_media_type_82599 - Get media type
326 * @hw: pointer to hardware structure
327 *
328 * Returns the media type (fiber, copper, backplane)
329 **/
7b25cdba 330static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 331{
332 enum ixgbe_media_type media_type;
333
334 /* Detect if there is a copper PHY attached. */
21cc5b4f
ET		 335 switch (hw->phy.type) {
336 case ixgbe_phy_cu_unknown:
337 case ixgbe_phy_tn:
338 case ixgbe_phy_aq:
11afc1b1
PW		 339 media_type = ixgbe_media_type_copper;
340 goto out;
21cc5b4f
ET		 341 default:
342 break;
11afc1b1
PW		 343 }
344
345 switch (hw->device_id) {
11afc1b1 346 case IXGBE_DEV_ID_82599_KX4:
dbfec662 347 case IXGBE_DEV_ID_82599_KX4_MEZZ:
312eb931 348 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
74757d49 349 case IXGBE_DEV_ID_82599_KR:
dbffcb21 350 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
1fcf03e6 351 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 352 /* Default device ID is mezzanine card KX/KX4 */
353 media_type = ixgbe_media_type_backplane;
354 break;
355 case IXGBE_DEV_ID_82599_SFP:
dbffcb21 356 case IXGBE_DEV_ID_82599_SFP_FCOE:
38ad1c8e 357 case IXGBE_DEV_ID_82599_SFP_EM:
11afc1b1
PW		 358 media_type = ixgbe_media_type_fiber;
359 break;
8911184f 360 case IXGBE_DEV_ID_82599_CX4:
6b1be199 361 media_type = ixgbe_media_type_cx4;
8911184f 362 break;
21cc5b4f
ET		 363 case IXGBE_DEV_ID_82599_T3_LOM:
364 media_type = ixgbe_media_type_copper;
365 break;
11afc1b1
PW		 366 default:
367 media_type = ixgbe_media_type_unknown;
368 break;
369 }
370out:
371 return media_type;
372}
373
374/**
8620a103 375 * ixgbe_start_mac_link_82599 - Setup MAC link settings
11afc1b1 376 * @hw: pointer to hardware structure
8620a103 377 * @autoneg_wait_to_complete: true when waiting for completion is needed
11afc1b1
PW		 378 *
379 * Configures link settings based on values in the ixgbe_hw struct.
380 * Restarts the link. Performs autonegotiation if needed.
381 **/
5d5b7c39 382static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
8620a103 383 bool autoneg_wait_to_complete)
11afc1b1
PW		 384{
385 u32 autoc_reg;
386 u32 links_reg;
387 u32 i;
388 s32 status = 0;
389
390 /* Restart link */
391 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
392 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
393 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
394
395 /* Only poll for autoneg to complete if specified to do so */
8620a103 396 if (autoneg_wait_to_complete) {
11afc1b1
PW		 397 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
398 IXGBE_AUTOC_LMS_KX4_KX_KR ||
399 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
400 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
401 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
402 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
403 links_reg = 0; /* Just in case Autoneg time = 0 */
404 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
405 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
406 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
407 break;
408 msleep(100);
409 }
410 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
411 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
412 hw_dbg(hw, "Autoneg did not complete.\n");
413 }
414 }
415 }
416
11afc1b1
PW		 417 /* Add delay to filter out noises during initial link setup */
418 msleep(50);
419
420 return status;
421}
422
8c7bea32
ET		 423/**
424 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
425 * @hw: pointer to hardware structure
426 *
427 * The base drivers may require better control over SFP+ module
428 * PHY states. This includes selectively shutting down the Tx
429 * laser on the PHY, effectively halting physical link.
430 **/
5d5b7c39 431static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
61fac744
PW		 432{
433 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
434
435 /* Disable tx laser; allow 100us to go dark per spec */
436 esdp_reg |= IXGBE_ESDP_SDP3;
437 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
438 IXGBE_WRITE_FLUSH(hw);
439 udelay(100);
440}
441
442/**
443 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
444 * @hw: pointer to hardware structure
445 *
446 * The base drivers may require better control over SFP+ module
447 * PHY states. This includes selectively turning on the Tx
448 * laser on the PHY, effectively starting physical link.
449 **/
5d5b7c39 450static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
61fac744
PW		 451{
452 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
453
454 /* Enable tx laser; allow 100ms to light up */
455 esdp_reg &= ~IXGBE_ESDP_SDP3;
456 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
457 IXGBE_WRITE_FLUSH(hw);
458 msleep(100);
459}
460
1097cd17
MC		 461/**
462 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
463 * @hw: pointer to hardware structure
464 *
465 * When the driver changes the link speeds that it can support,
466 * it sets autotry_restart to true to indicate that we need to
467 * initiate a new autotry session with the link partner. To do
468 * so, we set the speed then disable and re-enable the tx laser, to
469 * alert the link partner that it also needs to restart autotry on its
470 * end. This is consistent with true clause 37 autoneg, which also
471 * involves a loss of signal.
472 **/
5d5b7c39 473static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
1097cd17 474{
1097cd17 475 if (hw->mac.autotry_restart) {
61fac744
PW		 476 ixgbe_disable_tx_laser_multispeed_fiber(hw);
477 ixgbe_enable_tx_laser_multispeed_fiber(hw);
1097cd17
MC		 478 hw->mac.autotry_restart = false;
479 }
480}
481
11afc1b1 482/**
8620a103 483 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
11afc1b1
PW		 484 * @hw: pointer to hardware structure
485 * @speed: new link speed
486 * @autoneg: true if autonegotiation enabled
487 * @autoneg_wait_to_complete: true when waiting for completion is needed
488 *
489 * Set the link speed in the AUTOC register and restarts link.
490 **/
8620a103
MC		 491s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
492 ixgbe_link_speed speed,
493 bool autoneg,
494 bool autoneg_wait_to_complete)
11afc1b1
PW		 495{
496 s32 status = 0;
037c6d0a 497 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
11afc1b1
PW		 498 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
499 u32 speedcnt = 0;
500 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
037c6d0a 501 u32 i = 0;
11afc1b1
PW		 502 bool link_up = false;
503 bool negotiation;
504
505 /* Mask off requested but non-supported speeds */
037c6d0a
ET		 506 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
507 &negotiation);
508 if (status != 0)
509 return status;
510
511 speed &= link_speed;
11afc1b1
PW		 512
513 /*
514 * Try each speed one by one, highest priority first. We do this in
515 * software because 10gb fiber doesn't support speed autonegotiation.
516 */
517 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
518 speedcnt++;
519 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
520
50ac58ba 521 /* If we already have link at this speed, just jump out */
037c6d0a
ET		 522 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
523 false);
524 if (status != 0)
525 return status;
50ac58ba 526
037c6d0a 527 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
50ac58ba
PWJ		 528 goto out;
529
530 /* Set the module link speed */
11afc1b1
PW		 531 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
532 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 533 IXGBE_WRITE_FLUSH(hw);
11afc1b1 534
50ac58ba
PWJ		 535 /* Allow module to change analog characteristics (1G->10G) */
536 msleep(40);
11afc1b1 537
8620a103 538 status = ixgbe_setup_mac_link_82599(hw,
037c6d0a
ET		 539 IXGBE_LINK_SPEED_10GB_FULL,
540 autoneg,
541 autoneg_wait_to_complete);
50ac58ba 542 if (status != 0)
c3c74327 543 return status;
50ac58ba
PWJ		 544
545 /* Flap the tx laser if it has not already been done */
1097cd17 546 hw->mac.ops.flap_tx_laser(hw);
50ac58ba 547
cd7e1f0b
DS		 548 /*
549 * Wait for the controller to acquire link. Per IEEE 802.3ap,
550 * Section 73.10.2, we may have to wait up to 500ms if KR is
551 * attempted. 82599 uses the same timing for 10g SFI.
552 */
50ac58ba
PWJ		 553 for (i = 0; i < 5; i++) {
554 /* Wait for the link partner to also set speed */
555 msleep(100);
556
557 /* If we have link, just jump out */
037c6d0a
ET		 558 status = hw->mac.ops.check_link(hw, &link_speed,
559 &link_up, false);
560 if (status != 0)
561 return status;
562
50ac58ba
PWJ		 563 if (link_up)
564 goto out;
565 }
11afc1b1
PW		 566 }
567
568 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
569 speedcnt++;
570 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
571 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
572
50ac58ba 573 /* If we already have link at this speed, just jump out */
037c6d0a
ET		 574 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
575 false);
576 if (status != 0)
577 return status;
50ac58ba 578
037c6d0a 579 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
50ac58ba
PWJ		 580 goto out;
581
582 /* Set the module link speed */
11afc1b1
PW		 583 esdp_reg &= ~IXGBE_ESDP_SDP5;
584 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
585 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 586 IXGBE_WRITE_FLUSH(hw);
11afc1b1 587
50ac58ba
PWJ		 588 /* Allow module to change analog characteristics (10G->1G) */
589 msleep(40);
11afc1b1 590
8620a103 591 status = ixgbe_setup_mac_link_82599(hw,
037c6d0a
ET		 592 IXGBE_LINK_SPEED_1GB_FULL,
593 autoneg,
594 autoneg_wait_to_complete);
50ac58ba 595 if (status != 0)
c3c74327 596 return status;
50ac58ba
PWJ		 597
598 /* Flap the tx laser if it has not already been done */
1097cd17 599 hw->mac.ops.flap_tx_laser(hw);
50ac58ba
PWJ		 600
601 /* Wait for the link partner to also set speed */
602 msleep(100);
11afc1b1
PW		 603
604 /* If we have link, just jump out */
037c6d0a
ET		 605 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
606 false);
607 if (status != 0)
608 return status;
609
11afc1b1
PW		 610 if (link_up)
611 goto out;
612 }
613
614 /*
615 * We didn't get link. Configure back to the highest speed we tried,
616 * (if there was more than one). We call ourselves back with just the
617 * single highest speed that the user requested.
618 */
619 if (speedcnt > 1)
8620a103
MC		 620 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
621 highest_link_speed,
622 autoneg,
623 autoneg_wait_to_complete);
11afc1b1
PW		 624
625out:
c3c74327
MC		 626 /* Set autoneg_advertised value based on input link speed */
627 hw->phy.autoneg_advertised = 0;
628
629 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
630 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
631
632 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
633 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
634
11afc1b1
PW		 635 return status;
636}
637
cd7e1f0b
DS		 638/**
639 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
640 * @hw: pointer to hardware structure
641 * @speed: new link speed
642 * @autoneg: true if autonegotiation enabled
643 * @autoneg_wait_to_complete: true when waiting for completion is needed
644 *
645 * Implements the Intel SmartSpeed algorithm.
646 **/
647static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
648 ixgbe_link_speed speed, bool autoneg,
649 bool autoneg_wait_to_complete)
650{
651 s32 status = 0;
037c6d0a 652 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
cd7e1f0b
DS		 653 s32 i, j;
654 bool link_up = false;
655 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
cd7e1f0b
DS		 656
657 /* Set autoneg_advertised value based on input link speed */
658 hw->phy.autoneg_advertised = 0;
659
660 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
661 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
662
663 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
664 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
665
666 if (speed & IXGBE_LINK_SPEED_100_FULL)
667 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
668
669 /*
670 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
671 * autoneg advertisement if link is unable to be established at the
672 * highest negotiated rate. This can sometimes happen due to integrity
673 * issues with the physical media connection.
674 */
675
676 /* First, try to get link with full advertisement */
677 hw->phy.smart_speed_active = false;
678 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
679 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
680 autoneg_wait_to_complete);
037c6d0a 681 if (status != 0)
cd7e1f0b
DS		 682 goto out;
683
684 /*
685 * Wait for the controller to acquire link. Per IEEE 802.3ap,
686 * Section 73.10.2, we may have to wait up to 500ms if KR is
687 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
688 * Table 9 in the AN MAS.
689 */
690 for (i = 0; i < 5; i++) {
691 mdelay(100);
692
693 /* If we have link, just jump out */
037c6d0a
ET		 694 status = hw->mac.ops.check_link(hw, &link_speed,
695 &link_up, false);
696 if (status != 0)
697 goto out;
698
cd7e1f0b
DS		 699 if (link_up)
700 goto out;
701 }
702 }
703
704 /*
705 * We didn't get link. If we advertised KR plus one of KX4/KX
706 * (or BX4/BX), then disable KR and try again.
707 */
708 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
709 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
710 goto out;
711
712 /* Turn SmartSpeed on to disable KR support */
713 hw->phy.smart_speed_active = true;
714 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
715 autoneg_wait_to_complete);
037c6d0a 716 if (status != 0)
cd7e1f0b
DS		 717 goto out;
718
719 /*
720 * Wait for the controller to acquire link. 600ms will allow for
721 * the AN link_fail_inhibit_timer as well for multiple cycles of
722 * parallel detect, both 10g and 1g. This allows for the maximum
723 * connect attempts as defined in the AN MAS table 73-7.
724 */
725 for (i = 0; i < 6; i++) {
726 mdelay(100);
727
728 /* If we have link, just jump out */
037c6d0a
ET		 729 status = hw->mac.ops.check_link(hw, &link_speed,
730 &link_up, false);
731 if (status != 0)
732 goto out;
733
cd7e1f0b
DS		 734 if (link_up)
735 goto out;
736 }
737
738 /* We didn't get link. Turn SmartSpeed back off. */
739 hw->phy.smart_speed_active = false;
740 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
741 autoneg_wait_to_complete);
742
743out:
c4ee6a53 744 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
037c6d0a 745 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
849c4542 746 "the maximum advertised\n");
cd7e1f0b
DS		 747 return status;
748}
749
11afc1b1 750/**
8620a103 751 * ixgbe_setup_mac_link_82599 - Set MAC link speed
11afc1b1
PW		 752 * @hw: pointer to hardware structure
753 * @speed: new link speed
754 * @autoneg: true if autonegotiation enabled
755 * @autoneg_wait_to_complete: true when waiting for completion is needed
756 *
757 * Set the link speed in the AUTOC register and restarts link.
758 **/
5d5b7c39 759static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
8620a103
MC		 760 ixgbe_link_speed speed, bool autoneg,
761 bool autoneg_wait_to_complete)
11afc1b1
PW		 762{
763 s32 status = 0;
764 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
765 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
50ac58ba 766 u32 start_autoc = autoc;
1eb99d5a 767 u32 orig_autoc = 0;
11afc1b1
PW		 768 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
769 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
770 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
771 u32 links_reg;
772 u32 i;
773 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
774
775 /* Check to see if speed passed in is supported. */
776 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
0b0c2b31
ET		 777 if (status != 0)
778 goto out;
779
11afc1b1
PW		 780 speed &= link_capabilities;
781
50ac58ba
PWJ		 782 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
783 status = IXGBE_ERR_LINK_SETUP;
784 goto out;
785 }
786
1eb99d5a
PW		 787 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
788 if (hw->mac.orig_link_settings_stored)
789 orig_autoc = hw->mac.orig_autoc;
790 else
791 orig_autoc = autoc;
792
50ac58ba
PWJ		 793 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
794 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
795 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 796 /* Set KX4/KX/KR support according to speed requested */
797 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
798 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 799 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 800 autoc |= IXGBE_AUTOC_KX4_SUPP;
cd7e1f0b
DS		 801 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
802 (hw->phy.smart_speed_active == false))
11afc1b1
PW		 803 autoc |= IXGBE_AUTOC_KR_SUPP;
804 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
805 autoc |= IXGBE_AUTOC_KX_SUPP;
806 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
807 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
808 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
809 /* Switch from 1G SFI to 10G SFI if requested */
810 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
811 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
812 autoc &= ~IXGBE_AUTOC_LMS_MASK;
813 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
814 }
815 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
816 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
817 /* Switch from 10G SFI to 1G SFI if requested */
818 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
819 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
820 autoc &= ~IXGBE_AUTOC_LMS_MASK;
821 if (autoneg)
822 autoc |= IXGBE_AUTOC_LMS_1G_AN;
823 else
824 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
825 }
826 }
827
50ac58ba 828 if (autoc != start_autoc) {
11afc1b1
PW		 829 /* Restart link */
830 autoc |= IXGBE_AUTOC_AN_RESTART;
831 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
832
833 /* Only poll for autoneg to complete if specified to do so */
834 if (autoneg_wait_to_complete) {
835 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
836 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
837 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
838 links_reg = 0; /*Just in case Autoneg time=0*/
839 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
840 links_reg =
841 IXGBE_READ_REG(hw, IXGBE_LINKS);
842 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
843 break;
844 msleep(100);
845 }
846 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
847 status =
848 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
849 hw_dbg(hw, "Autoneg did not "
850 "complete.\n");
851 }
852 }
853 }
854
11afc1b1
PW		 855 /* Add delay to filter out noises during initial link setup */
856 msleep(50);
857 }
858
50ac58ba 859out:
11afc1b1
PW		 860 return status;
861}
862
863/**
8620a103 864 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
11afc1b1
PW		 865 * @hw: pointer to hardware structure
866 * @speed: new link speed
867 * @autoneg: true if autonegotiation enabled
868 * @autoneg_wait_to_complete: true if waiting is needed to complete
869 *
870 * Restarts link on PHY and MAC based on settings passed in.
871 **/
8620a103
MC		 872static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
873 ixgbe_link_speed speed,
874 bool autoneg,
875 bool autoneg_wait_to_complete)
11afc1b1
PW		 876{
877 s32 status;
878
879 /* Setup the PHY according to input speed */
880 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
881 autoneg_wait_to_complete);
882 /* Set up MAC */
8620a103 883 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
11afc1b1
PW		 884
885 return status;
886}
887
888/**
889 * ixgbe_reset_hw_82599 - Perform hardware reset
890 * @hw: pointer to hardware structure
891 *
892 * Resets the hardware by resetting the transmit and receive units, masks
893 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
894 * reset.
895 **/
7b25cdba 896static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 897{
898 s32 status = 0;
c9205697 899 u32 ctrl;
11afc1b1
PW		 900 u32 i;
901 u32 autoc;
902 u32 autoc2;
903
904 /* Call adapter stop to disable tx/rx and clear interrupts */
905 hw->mac.ops.stop_adapter(hw);
906
553b4497 907 /* PHY ops must be identified and initialized prior to reset */
04f165ef 908
037c6d0a 909 /* Identify PHY and related function pointers */
553b4497 910 status = hw->phy.ops.init(hw);
04f165ef 911
553b4497
PW		 912 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
913 goto reset_hw_out;
04f165ef 914
553b4497
PW		 915 /* Setup SFP module if there is one present. */
916 if (hw->phy.sfp_setup_needed) {
917 status = hw->mac.ops.setup_sfp(hw);
918 hw->phy.sfp_setup_needed = false;
04f165ef 919 }
11afc1b1 920
037c6d0a
ET		 921 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
922 goto reset_hw_out;
923
553b4497
PW		 924 /* Reset PHY */
925 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
926 hw->phy.ops.reset(hw);
927
11afc1b1
PW		 928 /*
929 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
930 * access and verify no pending requests before reset
931 */
a4297dc2 932 ixgbe_disable_pcie_master(hw);
11afc1b1 933
a4297dc2 934mac_reset_top:
11afc1b1
PW		 935 /*
936 * Issue global reset to the MAC. This needs to be a SW reset.
937 * If link reset is used, it might reset the MAC when mng is using it
938 */
939 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
940 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
941 IXGBE_WRITE_FLUSH(hw);
942
943 /* Poll for reset bit to self-clear indicating reset is complete */
944 for (i = 0; i < 10; i++) {
945 udelay(1);
946 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
947 if (!(ctrl & IXGBE_CTRL_RST))
948 break;
949 }
950 if (ctrl & IXGBE_CTRL_RST) {
951 status = IXGBE_ERR_RESET_FAILED;
952 hw_dbg(hw, "Reset polling failed to complete.\n");
953 }
11afc1b1 954
a4297dc2
ET		 955 /*
956 * Double resets are required for recovery from certain error
957 * conditions. Between resets, it is necessary to stall to allow time
958 * for any pending HW events to complete. We use 1usec since that is
959 * what is needed for ixgbe_disable_pcie_master(). The second reset
960 * then clears out any effects of those events.
961 */
962 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
963 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
964 udelay(1);
965 goto mac_reset_top;
966 }
967
11afc1b1
PW		 968 msleep(50);
969
11afc1b1
PW		 970 /*
971 * Store the original AUTOC/AUTOC2 values if they have not been
972 * stored off yet. Otherwise restore the stored original
973 * values since the reset operation sets back to defaults.
974 */
975 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
976 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
977 if (hw->mac.orig_link_settings_stored == false) {
978 hw->mac.orig_autoc = autoc;
979 hw->mac.orig_autoc2 = autoc2;
980 hw->mac.orig_link_settings_stored = true;
4df10466 981 } else {
11afc1b1
PW		 982 if (autoc != hw->mac.orig_autoc)
983 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
984 IXGBE_AUTOC_AN_RESTART));
985
986 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
987 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
988 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
989 autoc2 |= (hw->mac.orig_autoc2 &
990 IXGBE_AUTOC2_UPPER_MASK);
991 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
992 }
993 }
994
278675d8
ET		 995 /* Store the permanent mac address */
996 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
997
aca6bee7
WJP		 998 /*
999 * Store MAC address from RAR0, clear receive address registers, and
1000 * clear the multicast table. Also reset num_rar_entries to 128,
1001 * since we modify this value when programming the SAN MAC address.
1002 */
1003 hw->mac.num_rar_entries = 128;
1004 hw->mac.ops.init_rx_addrs(hw);
1005
0365e6e4
PW		 1006 /* Store the permanent SAN mac address */
1007 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1008
aca6bee7
WJP		 1009 /* Add the SAN MAC address to the RAR only if it's a valid address */
1010 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1011 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1012 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1013
1014 /* Reserve the last RAR for the SAN MAC address */
1015 hw->mac.num_rar_entries--;
1016 }
1017
383ff34b
YZ		 1018 /* Store the alternative WWNN/WWPN prefix */
1019 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1020 &hw->mac.wwpn_prefix);
1021
04f165ef 1022reset_hw_out:
11afc1b1
PW		 1023 return status;
1024}
1025
ffff4772
PWJ		 1026/**
1027 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1028 * @hw: pointer to hardware structure
1029 **/
1030s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1031{
1032 int i;
1033 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1034 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1035
1036 /*
1037 * Before starting reinitialization process,
1038 * FDIRCMD.CMD must be zero.
1039 */
1040 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1041 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1042 IXGBE_FDIRCMD_CMD_MASK))
1043 break;
1044 udelay(10);
1045 }
1046 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
905e4a41 1047 hw_dbg(hw, "Flow Director previous command isn't complete, "
d6dbee86 1048 "aborting table re-initialization.\n");
ffff4772
PWJ		 1049 return IXGBE_ERR_FDIR_REINIT_FAILED;
1050 }
1051
1052 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1053 IXGBE_WRITE_FLUSH(hw);
1054 /*
1055 * 82599 adapters flow director init flow cannot be restarted,
1056 * Workaround 82599 silicon errata by performing the following steps
1057 * before re-writing the FDIRCTRL control register with the same value.
1058 * - write 1 to bit 8 of FDIRCMD register &
1059 * - write 0 to bit 8 of FDIRCMD register
1060 */
1061 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1062 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1063 IXGBE_FDIRCMD_CLEARHT));
1064 IXGBE_WRITE_FLUSH(hw);
1065 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1066 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1067 ~IXGBE_FDIRCMD_CLEARHT));
1068 IXGBE_WRITE_FLUSH(hw);
1069 /*
1070 * Clear FDIR Hash register to clear any leftover hashes
1071 * waiting to be programmed.
1072 */
1073 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1074 IXGBE_WRITE_FLUSH(hw);
1075
1076 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1077 IXGBE_WRITE_FLUSH(hw);
1078
1079 /* Poll init-done after we write FDIRCTRL register */
1080 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1081 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1082 IXGBE_FDIRCTRL_INIT_DONE)
1083 break;
1084 udelay(10);
1085 }
1086 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1087 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1088 return IXGBE_ERR_FDIR_REINIT_FAILED;
1089 }
1090
1091 /* Clear FDIR statistics registers (read to clear) */
1092 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1093 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1094 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1095 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1096 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1097
1098 return 0;
1099}
1100
1101/**
1102 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1103 * @hw: pointer to hardware structure
1104 * @pballoc: which mode to allocate filters with
1105 **/
1106s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1107{
1108 u32 fdirctrl = 0;
1109 u32 pbsize;
1110 int i;
1111
1112 /*
1113 * Before enabling Flow Director, the Rx Packet Buffer size
1114 * must be reduced. The new value is the current size minus
1115 * flow director memory usage size.
1116 */
1117 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1118 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1119 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1120
1121 /*
1122 * The defaults in the HW for RX PB 1-7 are not zero and so should be
b595076a 1123 * initialized to zero for non DCB mode otherwise actual total RX PB
ffff4772
PWJ		 1124 * would be bigger than programmed and filter space would run into
1125 * the PB 0 region.
1126 */
1127 for (i = 1; i < 8; i++)
1128 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1129
1130 /* Send interrupt when 64 filters are left */
1131 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1132
1133 /* Set the maximum length per hash bucket to 0xA filters */
1134 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1135
1136 switch (pballoc) {
1137 case IXGBE_FDIR_PBALLOC_64K:
1138 /* 8k - 1 signature filters */
1139 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1140 break;
1141 case IXGBE_FDIR_PBALLOC_128K:
1142 /* 16k - 1 signature filters */
1143 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1144 break;
1145 case IXGBE_FDIR_PBALLOC_256K:
1146 /* 32k - 1 signature filters */
1147 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1148 break;
1149 default:
1150 /* bad value */
1151 return IXGBE_ERR_CONFIG;
1152 };
1153
1154 /* Move the flexible bytes to use the ethertype - shift 6 words */
1155 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1156
ffff4772
PWJ		 1157
1158 /* Prime the keys for hashing */
905e4a41
AD		 1159 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1160 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
ffff4772
PWJ		 1161
1162 /*
1163 * Poll init-done after we write the register. Estimated times:
1164 * 10G: PBALLOC = 11b, timing is 60us
1165 * 1G: PBALLOC = 11b, timing is 600us
1166 * 100M: PBALLOC = 11b, timing is 6ms
1167 *
1168 * Multiple these timings by 4 if under full Rx load
1169 *
1170 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1171 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1172 * this might not finish in our poll time, but we can live with that
1173 * for now.
1174 */
1175 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1176 IXGBE_WRITE_FLUSH(hw);
1177 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1178 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1179 IXGBE_FDIRCTRL_INIT_DONE)
1180 break;
1181 msleep(1);
1182 }
1183 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1184 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1185
1186 return 0;
1187}
1188
1189/**
1190 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1191 * @hw: pointer to hardware structure
1192 * @pballoc: which mode to allocate filters with
1193 **/
1194s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1195{
1196 u32 fdirctrl = 0;
1197 u32 pbsize;
1198 int i;
1199
1200 /*
1201 * Before enabling Flow Director, the Rx Packet Buffer size
1202 * must be reduced. The new value is the current size minus
1203 * flow director memory usage size.
1204 */
1205 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1206 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1207 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1208
1209 /*
1210 * The defaults in the HW for RX PB 1-7 are not zero and so should be
b595076a 1211 * initialized to zero for non DCB mode otherwise actual total RX PB
ffff4772
PWJ		 1212 * would be bigger than programmed and filter space would run into
1213 * the PB 0 region.
1214 */
1215 for (i = 1; i < 8; i++)
1216 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1217
1218 /* Send interrupt when 64 filters are left */
1219 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1220
9a713e7c
PW		 1221 /* Initialize the drop queue to Rx queue 127 */
1222 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1223
ffff4772
PWJ		 1224 switch (pballoc) {
1225 case IXGBE_FDIR_PBALLOC_64K:
1226 /* 2k - 1 perfect filters */
1227 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1228 break;
1229 case IXGBE_FDIR_PBALLOC_128K:
1230 /* 4k - 1 perfect filters */
1231 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1232 break;
1233 case IXGBE_FDIR_PBALLOC_256K:
1234 /* 8k - 1 perfect filters */
1235 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1236 break;
1237 default:
1238 /* bad value */
1239 return IXGBE_ERR_CONFIG;
1240 };
1241
1242 /* Turn perfect match filtering on */
1243 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1244 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1245
1246 /* Move the flexible bytes to use the ethertype - shift 6 words */
1247 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1248
1249 /* Prime the keys for hashing */
905e4a41
AD		 1250 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1251 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
ffff4772
PWJ		 1252
1253 /*
1254 * Poll init-done after we write the register. Estimated times:
1255 * 10G: PBALLOC = 11b, timing is 60us
1256 * 1G: PBALLOC = 11b, timing is 600us
1257 * 100M: PBALLOC = 11b, timing is 6ms
1258 *
1259 * Multiple these timings by 4 if under full Rx load
1260 *
1261 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1262 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1263 * this might not finish in our poll time, but we can live with that
1264 * for now.
1265 */
1266
1267 /* Set the maximum length per hash bucket to 0xA filters */
1268 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1269
1270 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1271 IXGBE_WRITE_FLUSH(hw);
1272 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1273 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1274 IXGBE_FDIRCTRL_INIT_DONE)
1275 break;
1276 msleep(1);
1277 }
1278 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1279 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1280
1281 return 0;
1282}
1283
1284
1285/**
1286 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1287 * @stream: input bitstream to compute the hash on
1288 * @key: 32-bit hash key
1289 **/
905e4a41
AD		 1290static u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
1291 u32 key)
ffff4772
PWJ		 1292{
1293 /*
1294 * The algorithm is as follows:
1295 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1296 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1297 * and A[n] x B[n] is bitwise AND between same length strings
1298 *
1299 * K[n] is 16 bits, defined as:
1300 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1301 * for n modulo 32 < 15, K[n] =
1302 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1303 *
1304 * S[n] is 16 bits, defined as:
1305 * for n >= 15, S[n] = S[n:n - 15]
1306 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1307 *
1308 * To simplify for programming, the algorithm is implemented
1309 * in software this way:
1310 *
905e4a41
AD		 1311 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
1312 *
1313 * for (i = 0; i < 352; i+=32)
1314 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
1315 *
1316 * lo_hash_dword[15:0] ^= Stream[15:0];
1317 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
1318 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
ffff4772 1319 *
905e4a41 1320 * hi_hash_dword[31:0] ^= Stream[351:320];
ffff4772 1321 *
905e4a41
AD		 1322 * if(key[0])
1323 * hash[15:0] ^= Stream[15:0];
1324 *
1325 * for (i = 0; i < 16; i++) {
1326 * if (key[i])
1327 * hash[15:0] ^= lo_hash_dword[(i+15):i];
1328 * if (key[i + 16])
1329 * hash[15:0] ^= hi_hash_dword[(i+15):i];
ffff4772 1330 * }
905e4a41 1331 *
ffff4772 1332 */
905e4a41
AD		 1333 __be32 common_hash_dword = 0;
1334 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1335 u32 hash_result = 0;
1336 u8 i;
ffff4772 1337
905e4a41
AD		 1338 /* record the flow_vm_vlan bits as they are a key part to the hash */
1339 flow_vm_vlan = ntohl(atr_input->dword_stream[0]);
ffff4772 1340
905e4a41
AD		 1341 /* generate common hash dword */
1342 for (i = 10; i; i -= 2)
1343 common_hash_dword ^= atr_input->dword_stream[i] ^
1344 atr_input->dword_stream[i - 1];
ffff4772 1345
905e4a41 1346 hi_hash_dword = ntohl(common_hash_dword);
ffff4772 1347
905e4a41
AD		 1348 /* low dword is word swapped version of common */
1349 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
ffff4772 1350
905e4a41
AD		 1351 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1352 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
ffff4772 1353
905e4a41
AD		 1354 /* Process bits 0 and 16 */
1355 if (key & 0x0001) hash_result ^= lo_hash_dword;
1356 if (key & 0x00010000) hash_result ^= hi_hash_dword;
ffff4772
PWJ		 1357
1358 /*
905e4a41
AD		 1359 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1360 * delay this because bit 0 of the stream should not be processed
1361 * so we do not add the vlan until after bit 0 was processed
ffff4772 1362 */
905e4a41 1363 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
ffff4772 1364
905e4a41
AD		 1365
1366 /* process the remaining 30 bits in the key 2 bits at a time */
1367 for (i = 15; i; i-- ) {
1368 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
1369 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
ffff4772
PWJ		 1370 }
1371
905e4a41 1372 return hash_result & IXGBE_ATR_HASH_MASK;
ffff4772
PWJ		 1373}
1374
69830529
AD		 1375/*
1376 * These defines allow us to quickly generate all of the necessary instructions
1377 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1378 * for values 0 through 15
1379 */
1380#define IXGBE_ATR_COMMON_HASH_KEY \
1381 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1382#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1383do { \
1384 u32 n = (_n); \
1385 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1386 common_hash ^= lo_hash_dword >> n; \
1387 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1388 bucket_hash ^= lo_hash_dword >> n; \
1389 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1390 sig_hash ^= lo_hash_dword << (16 - n); \
1391 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1392 common_hash ^= hi_hash_dword >> n; \
1393 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1394 bucket_hash ^= hi_hash_dword >> n; \
1395 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1396 sig_hash ^= hi_hash_dword << (16 - n); \
1397} while (0);
1398
1399/**
1400 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1401 * @stream: input bitstream to compute the hash on
1402 *
1403 * This function is almost identical to the function above but contains
1404 * several optomizations such as unwinding all of the loops, letting the
1405 * compiler work out all of the conditional ifs since the keys are static
1406 * defines, and computing two keys at once since the hashed dword stream
1407 * will be the same for both keys.
1408 **/
1409static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1410 union ixgbe_atr_hash_dword common)
1411{
1412 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1413 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1414
1415 /* record the flow_vm_vlan bits as they are a key part to the hash */
1416 flow_vm_vlan = ntohl(input.dword);
1417
1418 /* generate common hash dword */
1419 hi_hash_dword = ntohl(common.dword);
1420
1421 /* low dword is word swapped version of common */
1422 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1423
1424 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1425 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1426
1427 /* Process bits 0 and 16 */
1428 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1429
1430 /*
1431 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1432 * delay this because bit 0 of the stream should not be processed
1433 * so we do not add the vlan until after bit 0 was processed
1434 */
1435 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1436
1437 /* Process remaining 30 bit of the key */
1438 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1439 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1440 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1441 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1442 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1443 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1444 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1445 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1446 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1447 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1448 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1449 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1450 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1451 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1452 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1453
1454 /* combine common_hash result with signature and bucket hashes */
1455 bucket_hash ^= common_hash;
1456 bucket_hash &= IXGBE_ATR_HASH_MASK;
1457
1458 sig_hash ^= common_hash << 16;
1459 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1460
1461 /* return completed signature hash */
1462 return sig_hash ^ bucket_hash;
1463}
1464
ffff4772
PWJ		 1465/**
1466 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1467 * @hw: pointer to hardware structure
69830529
AD		 1468 * @input: unique input dword
1469 * @common: compressed common input dword
ffff4772
PWJ		 1470 * @queue: queue index to direct traffic to
1471 **/
1472s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
69830529
AD		 1473 union ixgbe_atr_hash_dword input,
1474 union ixgbe_atr_hash_dword common,
ffff4772
PWJ		 1475 u8 queue)
1476{
1477 u64 fdirhashcmd;
905e4a41 1478 u32 fdircmd;
ffff4772
PWJ		 1479
1480 /*
905e4a41
AD		 1481 * Get the flow_type in order to program FDIRCMD properly
1482 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
ffff4772 1483 */
69830529 1484 switch (input.formatted.flow_type) {
905e4a41
AD		 1485 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1486 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1487 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1488 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1489 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1490 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
ffff4772
PWJ		 1491 break;
1492 default:
905e4a41 1493 hw_dbg(hw, " Error on flow type input\n");
ffff4772
PWJ		 1494 return IXGBE_ERR_CONFIG;
1495 }
1496
905e4a41
AD		 1497 /* configure FDIRCMD register */
1498 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1499 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
69830529 1500 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
905e4a41
AD		 1501 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1502
1503 /*
1504 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1505 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1506 */
1507 fdirhashcmd = (u64)fdircmd << 32;
69830529 1508 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
ffff4772
PWJ		 1509
1510 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1511
69830529
AD		 1512 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1513
ffff4772
PWJ		 1514 return 0;
1515}
1516
45b9f509
AD		 1517/**
1518 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1519 * @input_mask: mask to be bit swapped
1520 *
1521 * The source and destination port masks for flow director are bit swapped
1522 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1523 * generate a correctly swapped value we need to bit swap the mask and that
1524 * is what is accomplished by this function.
1525 **/
1526static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks)
1527{
1528 u32 mask = ntohs(input_masks->dst_port_mask);
1529 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1530 mask |= ntohs(input_masks->src_port_mask);
1531 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1532 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1533 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1534 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1535}
1536
1537/*
1538 * These two macros are meant to address the fact that we have registers
1539 * that are either all or in part big-endian. As a result on big-endian
1540 * systems we will end up byte swapping the value to little-endian before
1541 * it is byte swapped again and written to the hardware in the original
1542 * big-endian format.
1543 */
1544#define IXGBE_STORE_AS_BE32(_value) \
1545 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1546 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1547
1548#define IXGBE_WRITE_REG_BE32(a, reg, value) \
1549 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1550
1551#define IXGBE_STORE_AS_BE16(_value) \
1552 (((u16)(_value) >> 8) | ((u16)(_value) << 8))
1553
ffff4772
PWJ		 1554/**
1555 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1556 * @hw: pointer to hardware structure
1557 * @input: input bitstream
9a713e7c
PW		 1558 * @input_masks: bitwise masks for relevant fields
1559 * @soft_id: software index into the silicon hash tables for filter storage
ffff4772
PWJ		 1560 * @queue: queue index to direct traffic to
1561 *
1562 * Note that the caller to this function must lock before calling, since the
1563 * hardware writes must be protected from one another.
1564 **/
1565s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
905e4a41 1566 union ixgbe_atr_input *input,
9a713e7c
PW		 1567 struct ixgbe_atr_input_masks *input_masks,
1568 u16 soft_id, u8 queue)
ffff4772 1569{
ffff4772 1570 u32 fdirhash;
45b9f509
AD		 1571 u32 fdircmd;
1572 u32 fdirport, fdirtcpm;
1573 u32 fdirvlan;
1574 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
1575 u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX |
1576 IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
ffff4772
PWJ		 1577
1578 /*
45b9f509 1579 * Check flow_type formatting, and bail out before we touch the hardware
ffff4772
PWJ		 1580 * if there's a configuration issue
1581 */
45b9f509
AD		 1582 switch (input->formatted.flow_type) {
1583 case IXGBE_ATR_FLOW_TYPE_IPV4:
1584 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
1585 fdirm |= IXGBE_FDIRM_L4P;
1586 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1587 if (input_masks->dst_port_mask || input_masks->src_port_mask) {
1588 hw_dbg(hw, " Error on src/dst port mask\n");
1589 return IXGBE_ERR_CONFIG;
1590 }
1591 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1592 case IXGBE_ATR_FLOW_TYPE_UDPV4:
ffff4772
PWJ		 1593 break;
1594 default:
45b9f509 1595 hw_dbg(hw, " Error on flow type input\n");
ffff4772
PWJ		 1596 return IXGBE_ERR_CONFIG;
1597 }
1598
9a713e7c 1599 /*
45b9f509
AD		 1600 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1601 * are zero, then assume a full mask for that field. Also assume that
1602 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1603 * cannot be masked out in this implementation.
9a713e7c
PW		 1604 *
1605 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1606 * point in time.
1607 */
45b9f509
AD		 1608
1609 /* Program FDIRM */
1610 switch (ntohs(input_masks->vlan_id_mask) & 0xEFFF) {
1611 case 0xEFFF:
1612 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */
1613 fdirm &= ~IXGBE_FDIRM_VLANID;
1614 case 0xE000:
1615 /* Unmask VLAN prio - bit 1 */
1616 fdirm &= ~IXGBE_FDIRM_VLANP;
9a713e7c 1617 break;
45b9f509
AD		 1618 case 0x0FFF:
1619 /* Unmask VLAN ID - bit 0 */
1620 fdirm &= ~IXGBE_FDIRM_VLANID;
9a713e7c 1621 break;
45b9f509
AD		 1622 case 0x0000:
1623 /* do nothing, vlans already masked */
9a713e7c 1624 break;
45b9f509
AD		 1625 default:
1626 hw_dbg(hw, " Error on VLAN mask\n");
1627 return IXGBE_ERR_CONFIG;
9a713e7c
PW		 1628 }
1629
45b9f509
AD		 1630 if (input_masks->flex_mask & 0xFFFF) {
1631 if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) {
1632 hw_dbg(hw, " Error on flexible byte mask\n");
1633 return IXGBE_ERR_CONFIG;
1634 }
1635 /* Unmask Flex Bytes - bit 4 */
1636 fdirm &= ~IXGBE_FDIRM_FLEX;
1637 }
9a713e7c
PW		 1638
1639 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
9a713e7c 1640 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
ffff4772 1641
45b9f509
AD		 1642 /* store the TCP/UDP port masks, bit reversed from port layout */
1643 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks);
1644
1645 /* write both the same so that UDP and TCP use the same mask */
1646 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1647 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1648
1649 /* store source and destination IP masks (big-enian) */
1650 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1651 ~input_masks->src_ip_mask[0]);
1652 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1653 ~input_masks->dst_ip_mask[0]);
1654
1655 /* Apply masks to input data */
1656 input->formatted.vlan_id &= input_masks->vlan_id_mask;
1657 input->formatted.flex_bytes &= input_masks->flex_mask;
1658 input->formatted.src_port &= input_masks->src_port_mask;
1659 input->formatted.dst_port &= input_masks->dst_port_mask;
1660 input->formatted.src_ip[0] &= input_masks->src_ip_mask[0];
1661 input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0];
1662
1663 /* record vlan (little-endian) and flex_bytes(big-endian) */
1664 fdirvlan =
1665 IXGBE_STORE_AS_BE16(ntohs(input->formatted.flex_bytes));
1666 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1667 fdirvlan |= ntohs(input->formatted.vlan_id);
1668 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1669
1670 /* record source and destination port (little-endian)*/
1671 fdirport = ntohs(input->formatted.dst_port);
1672 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1673 fdirport |= ntohs(input->formatted.src_port);
1674 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1675
1676 /* record the first 32 bits of the destination address (big-endian) */
1677 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1678
1679 /* record the source address (big-endian) */
1680 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1681
1682 /* configure FDIRCMD register */
1683 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1684 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1685 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1686 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1687
1688 /* we only want the bucket hash so drop the upper 16 bits */
1689 fdirhash = ixgbe_atr_compute_hash_82599(input,
1690 IXGBE_ATR_BUCKET_HASH_KEY);
1691 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
ffff4772
PWJ		 1692
1693 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1694 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1695
1696 return 0;
1697}
45b9f509 1698
11afc1b1
PW		 1699/**
1700 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1701 * @hw: pointer to hardware structure
1702 * @reg: analog register to read
1703 * @val: read value
1704 *
1705 * Performs read operation to Omer analog register specified.
1706 **/
7b25cdba 1707static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
11afc1b1
PW		 1708{
1709 u32 core_ctl;
1710
1711 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1712 (reg << 8));
1713 IXGBE_WRITE_FLUSH(hw);
1714 udelay(10);
1715 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1716 *val = (u8)core_ctl;
1717
1718 return 0;
1719}
1720
1721/**
1722 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1723 * @hw: pointer to hardware structure
1724 * @reg: atlas register to write
1725 * @val: value to write
1726 *
1727 * Performs write operation to Omer analog register specified.
1728 **/
7b25cdba 1729static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
11afc1b1
PW		 1730{
1731 u32 core_ctl;
1732
1733 core_ctl = (reg << 8) | val;
1734 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1735 IXGBE_WRITE_FLUSH(hw);
1736 udelay(10);
1737
1738 return 0;
1739}
1740
1741/**
1742 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1743 * @hw: pointer to hardware structure
1744 *
7184b7cf
ET		 1745 * Starts the hardware using the generic start_hw function
1746 * and the generation start_hw function.
1747 * Then performs revision-specific operations, if any.
11afc1b1 1748 **/
7b25cdba 1749static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
11afc1b1 1750{
7184b7cf 1751 s32 ret_val = 0;
11afc1b1 1752
794caeb2 1753 ret_val = ixgbe_start_hw_generic(hw);
7184b7cf
ET		 1754 if (ret_val != 0)
1755 goto out;
11afc1b1 1756
7184b7cf
ET		 1757 ret_val = ixgbe_start_hw_gen2(hw);
1758 if (ret_val != 0)
1759 goto out;
11afc1b1 1760
50ac58ba
PWJ		 1761 /* We need to run link autotry after the driver loads */
1762 hw->mac.autotry_restart = true;
1763
794caeb2
PWJ		 1764 if (ret_val == 0)
1765 ret_val = ixgbe_verify_fw_version_82599(hw);
7184b7cf 1766out:
794caeb2 1767 return ret_val;
11afc1b1
PW		 1768}
1769
1770/**
1771 * ixgbe_identify_phy_82599 - Get physical layer module
1772 * @hw: pointer to hardware structure
1773 *
1774 * Determines the physical layer module found on the current adapter.
21cc5b4f
ET		 1775 * If PHY already detected, maintains current PHY type in hw struct,
1776 * otherwise executes the PHY detection routine.
11afc1b1 1777 **/
d6cd8e0e 1778static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1779{
1780 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
21cc5b4f
ET		 1781
1782 /* Detect PHY if not unknown - returns success if already detected. */
11afc1b1 1783 status = ixgbe_identify_phy_generic(hw);
21cc5b4f
ET		 1784 if (status != 0) {
1785 /* 82599 10GBASE-T requires an external PHY */
1786 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1787 goto out;
1788 else
1789 status = ixgbe_identify_sfp_module_generic(hw);
1790 }
1791
1792 /* Set PHY type none if no PHY detected */
1793 if (hw->phy.type == ixgbe_phy_unknown) {
1794 hw->phy.type = ixgbe_phy_none;
1795 status = 0;
1796 }
1797
1798 /* Return error if SFP module has been detected but is not supported */
1799 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1800 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1801
1802out:
11afc1b1
PW		 1803 return status;
1804}
1805
1806/**
1807 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1808 * @hw: pointer to hardware structure
1809 *
1810 * Determines physical layer capabilities of the current configuration.
1811 **/
7b25cdba 1812static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1813{
1814 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 1815 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1816 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1817 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1818 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1819 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1820 u16 ext_ability = 0;
1339b9e9 1821 u8 comp_codes_10g = 0;
cb836a97 1822 u8 comp_codes_1g = 0;
11afc1b1 1823
04193058
PWJ		 1824 hw->phy.ops.identify(hw);
1825
21cc5b4f
ET		 1826 switch (hw->phy.type) {
1827 case ixgbe_phy_tn:
1828 case ixgbe_phy_aq:
1829 case ixgbe_phy_cu_unknown:
6b73e10d 1830 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
21cc5b4f 1831 &ext_ability);
6b73e10d 1832 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 1833 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 1834 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 1835 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 1836 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 1837 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1838 goto out;
21cc5b4f
ET		 1839 default:
1840 break;
04193058
PWJ		 1841 }
1842
1843 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1844 case IXGBE_AUTOC_LMS_1G_AN:
1845 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1846 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1847 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1848 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1849 goto out;
1850 } else
1851 /* SFI mode so read SFP module */
1852 goto sfp_check;
11afc1b1 1853 break;
04193058
PWJ		 1854 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1855 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1856 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1857 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1858 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 1859 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1860 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 1861 goto out;
1862 break;
1863 case IXGBE_AUTOC_LMS_10G_SERIAL:
1864 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1865 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1866 goto out;
1867 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1868 goto sfp_check;
1869 break;
1870 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1871 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1872 if (autoc & IXGBE_AUTOC_KX_SUPP)
1873 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1874 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1875 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1876 if (autoc & IXGBE_AUTOC_KR_SUPP)
1877 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1878 goto out;
1879 break;
1880 default:
1881 goto out;
1882 break;
1883 }
11afc1b1 1884
04193058
PWJ		 1885sfp_check:
1886 /* SFP check must be done last since DA modules are sometimes used to
1887 * test KR mode - we need to id KR mode correctly before SFP module.
1888 * Call identify_sfp because the pluggable module may have changed */
1889 hw->phy.ops.identify_sfp(hw);
1890 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1891 goto out;
1892
1893 switch (hw->phy.type) {
ea0a04df
DS		 1894 case ixgbe_phy_sfp_passive_tyco:
1895 case ixgbe_phy_sfp_passive_unknown:
04193058
PWJ		 1896 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1897 break;
ea0a04df
DS		 1898 case ixgbe_phy_sfp_ftl_active:
1899 case ixgbe_phy_sfp_active_unknown:
1900 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1901 break;
04193058
PWJ		 1902 case ixgbe_phy_sfp_avago:
1903 case ixgbe_phy_sfp_ftl:
1904 case ixgbe_phy_sfp_intel:
1905 case ixgbe_phy_sfp_unknown:
cb836a97
DS		 1906 hw->phy.ops.read_i2c_eeprom(hw,
1907 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
04193058
PWJ		 1908 hw->phy.ops.read_i2c_eeprom(hw,
1909 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1910 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 1911 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 1912 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 1913 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
cb836a97
DS		 1914 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1915 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
11afc1b1
PW		 1916 break;
1917 default:
11afc1b1
PW		 1918 break;
1919 }
1920
04193058 1921out:
11afc1b1
PW		 1922 return physical_layer;
1923}
1924
1925/**
1926 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1927 * @hw: pointer to hardware structure
1928 * @regval: register value to write to RXCTRL
1929 *
1930 * Enables the Rx DMA unit for 82599
1931 **/
7b25cdba 1932static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
11afc1b1
PW		 1933{
1934#define IXGBE_MAX_SECRX_POLL 30
1935 int i;
1936 int secrxreg;
1937
1938 /*
1939 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1940 * If traffic is incoming before we enable the Rx unit, it could hang
1941 * the Rx DMA unit. Therefore, make sure the security engine is
1942 * completely disabled prior to enabling the Rx unit.
1943 */
1944 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1945 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1946 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1947 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1948 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1949 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1950 break;
1951 else
8c7bea32 1952 /* Use interrupt-safe sleep just in case */
11afc1b1
PW		 1953 udelay(10);
1954 }
1955
1956 /* For informational purposes only */
1957 if (i >= IXGBE_MAX_SECRX_POLL)
1958 hw_dbg(hw, "Rx unit being enabled before security "
1959 "path fully disabled. Continuing with init.\n");
1960
1961 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1962 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1963 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1964 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1965 IXGBE_WRITE_FLUSH(hw);
1966
1967 return 0;
1968}
1969
04193058
PWJ		 1970/**
1971 * ixgbe_get_device_caps_82599 - Get additional device capabilities
1972 * @hw: pointer to hardware structure
1973 * @device_caps: the EEPROM word with the extra device capabilities
1974 *
1975 * This function will read the EEPROM location for the device capabilities,
1976 * and return the word through device_caps.
1977 **/
7b25cdba 1978static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
04193058
PWJ		 1979{
1980 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
1981
1982 return 0;
1983}
1984
794caeb2
PWJ		 1985/**
1986 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1987 * @hw: pointer to hardware structure
1988 *
1989 * Verifies that installed the firmware version is 0.6 or higher
1990 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1991 *
1992 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1993 * if the FW version is not supported.
1994 **/
1995static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
1996{
1997 s32 status = IXGBE_ERR_EEPROM_VERSION;
1998 u16 fw_offset, fw_ptp_cfg_offset;
1999 u16 fw_version = 0;
2000
2001 /* firmware check is only necessary for SFI devices */
2002 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2003 status = 0;
2004 goto fw_version_out;
2005 }
2006
2007 /* get the offset to the Firmware Module block */
2008 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2009
2010 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2011 goto fw_version_out;
2012
2013 /* get the offset to the Pass Through Patch Configuration block */
2014 hw->eeprom.ops.read(hw, (fw_offset +
2015 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2016 &fw_ptp_cfg_offset);
2017
2018 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2019 goto fw_version_out;
2020
2021 /* get the firmware version */
2022 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2023 IXGBE_FW_PATCH_VERSION_4),
2024 &fw_version);
2025
2026 if (fw_version > 0x5)
2027 status = 0;
2028
2029fw_version_out:
2030 return status;
2031}
2032
0fa6d832
ET		 2033/**
2034 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2035 * @hw: pointer to hardware structure
2036 *
2037 * Returns true if the LESM FW module is present and enabled. Otherwise
2038 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2039 **/
2040static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2041{
2042 bool lesm_enabled = false;
2043 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2044 s32 status;
2045
2046 /* get the offset to the Firmware Module block */
2047 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2048
2049 if ((status != 0) ||
2050 (fw_offset == 0) || (fw_offset == 0xFFFF))
2051 goto out;
2052
2053 /* get the offset to the LESM Parameters block */
2054 status = hw->eeprom.ops.read(hw, (fw_offset +
2055 IXGBE_FW_LESM_PARAMETERS_PTR),
2056 &fw_lesm_param_offset);
2057
2058 if ((status != 0) ||
2059 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2060 goto out;
2061
2062 /* get the lesm state word */
2063 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2064 IXGBE_FW_LESM_STATE_1),
2065 &fw_lesm_state);
2066
2067 if ((status == 0) &&
2068 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2069 lesm_enabled = true;
2070
2071out:
2072 return lesm_enabled;
2073}
2074
11afc1b1
PW		 2075static struct ixgbe_mac_operations mac_ops_82599 = {
2076 .init_hw = &ixgbe_init_hw_generic,
2077 .reset_hw = &ixgbe_reset_hw_82599,
2078 .start_hw = &ixgbe_start_hw_82599,
2079 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2080 .get_media_type = &ixgbe_get_media_type_82599,
2081 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2082 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2083 .get_mac_addr = &ixgbe_get_mac_addr_generic,
21ce849b 2084 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
04193058 2085 .get_device_caps = &ixgbe_get_device_caps_82599,
a391f1d5 2086 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
11afc1b1
PW		 2087 .stop_adapter = &ixgbe_stop_adapter_generic,
2088 .get_bus_info = &ixgbe_get_bus_info_generic,
2089 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2090 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2091 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2092 .setup_link = &ixgbe_setup_mac_link_82599,
21ce849b 2093 .check_link = &ixgbe_check_mac_link_generic,
11afc1b1
PW		 2094 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2095 .led_on = &ixgbe_led_on_generic,
2096 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 2097 .blink_led_start = &ixgbe_blink_led_start_generic,
2098 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 2099 .set_rar = &ixgbe_set_rar_generic,
2100 .clear_rar = &ixgbe_clear_rar_generic,
21ce849b
MC		 2101 .set_vmdq = &ixgbe_set_vmdq_generic,
2102 .clear_vmdq = &ixgbe_clear_vmdq_generic,
11afc1b1 2103 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
11afc1b1
PW		 2104 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2105 .enable_mc = &ixgbe_enable_mc_generic,
2106 .disable_mc = &ixgbe_disable_mc_generic,
21ce849b
MC		 2107 .clear_vfta = &ixgbe_clear_vfta_generic,
2108 .set_vfta = &ixgbe_set_vfta_generic,
2109 .fc_enable = &ixgbe_fc_enable_generic,
2110 .init_uta_tables = &ixgbe_init_uta_tables_generic,
11afc1b1 2111 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
a985b6c3
GR		 2112 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2113 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
5e655105
DS		 2114 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2115 .release_swfw_sync = &ixgbe_release_swfw_sync,
2116
11afc1b1
PW		 2117};
2118
2119static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
037c6d0a
ET		 2120 .init_params = &ixgbe_init_eeprom_params_generic,
2121 .read = &ixgbe_read_eerd_generic,
2122 .write = &ixgbe_write_eeprom_generic,
2123 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2124 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2125 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
11afc1b1
PW		 2126};
2127
2128static struct ixgbe_phy_operations phy_ops_82599 = {
037c6d0a
ET		 2129 .identify = &ixgbe_identify_phy_82599,
2130 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2131 .init = &ixgbe_init_phy_ops_82599,
2132 .reset = &ixgbe_reset_phy_generic,
2133 .read_reg = &ixgbe_read_phy_reg_generic,
2134 .write_reg = &ixgbe_write_phy_reg_generic,
2135 .setup_link = &ixgbe_setup_phy_link_generic,
2136 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2137 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2138 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2139 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2140 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2141 .check_overtemp = &ixgbe_tn_check_overtemp,
11afc1b1
PW		 2142};
2143
2144struct ixgbe_info ixgbe_82599_info = {
2145 .mac = ixgbe_mac_82599EB,
2146 .get_invariants = &ixgbe_get_invariants_82599,
2147 .mac_ops = &mac_ops_82599,
2148 .eeprom_ops = &eeprom_ops_82599,
2149 .phy_ops = &phy_ops_82599,
a391f1d5 2150 .mbx_ops = &mbx_ops_generic,
11afc1b1 2151};
Linux 6.x block layer and io_uring tree(s)