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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
8c47eaa7 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #ifndef _IXGBE_H_ | |
29 | #define _IXGBE_H_ | |
30 | ||
31 | #include <linux/types.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/netdevice.h> | |
6fabd715 | 34 | #include <linux/aer.h> |
9a799d71 AK |
35 | |
36 | #include "ixgbe_type.h" | |
37 | #include "ixgbe_common.h" | |
2f90b865 | 38 | #include "ixgbe_dcb.h" |
eacd73f7 YZ |
39 | #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) |
40 | #define IXGBE_FCOE | |
41 | #include "ixgbe_fcoe.h" | |
42 | #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ | |
5dd2d332 | 43 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
44 | #include <linux/dca.h> |
45 | #endif | |
9a799d71 | 46 | |
9a799d71 AK |
47 | #define PFX "ixgbe: " |
48 | #define DPRINTK(nlevel, klevel, fmt, args...) \ | |
49 | ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \ | |
50 | printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \ | |
b39d66a8 | 51 | __func__ , ## args))) |
9a799d71 AK |
52 | |
53 | /* TX/RX descriptor defines */ | |
6bacb300 | 54 | #define IXGBE_DEFAULT_TXD 512 |
9a799d71 AK |
55 | #define IXGBE_MAX_TXD 4096 |
56 | #define IXGBE_MIN_TXD 64 | |
57 | ||
6bacb300 | 58 | #define IXGBE_DEFAULT_RXD 512 |
9a799d71 AK |
59 | #define IXGBE_MAX_RXD 4096 |
60 | #define IXGBE_MIN_RXD 64 | |
61 | ||
9a799d71 AK |
62 | /* flow control */ |
63 | #define IXGBE_DEFAULT_FCRTL 0x10000 | |
2b9ade93 | 64 | #define IXGBE_MIN_FCRTL 0x40 |
9a799d71 AK |
65 | #define IXGBE_MAX_FCRTL 0x7FF80 |
66 | #define IXGBE_DEFAULT_FCRTH 0x20000 | |
2b9ade93 | 67 | #define IXGBE_MIN_FCRTH 0x600 |
9a799d71 | 68 | #define IXGBE_MAX_FCRTH 0x7FFF0 |
2b9ade93 | 69 | #define IXGBE_DEFAULT_FCPAUSE 0xFFFF |
9a799d71 AK |
70 | #define IXGBE_MIN_FCPAUSE 0 |
71 | #define IXGBE_MAX_FCPAUSE 0xFFFF | |
72 | ||
73 | /* Supported Rx Buffer Sizes */ | |
74 | #define IXGBE_RXBUFFER_64 64 /* Used for packet split */ | |
75 | #define IXGBE_RXBUFFER_128 128 /* Used for packet split */ | |
76 | #define IXGBE_RXBUFFER_256 256 /* Used for packet split */ | |
77 | #define IXGBE_RXBUFFER_2048 2048 | |
e76678dd AD |
78 | #define IXGBE_RXBUFFER_4096 4096 |
79 | #define IXGBE_RXBUFFER_8192 8192 | |
32344a39 | 80 | #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ |
9a799d71 AK |
81 | |
82 | #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256 | |
83 | ||
84 | #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) | |
85 | ||
9a799d71 AK |
86 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
87 | #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
88 | ||
89 | #define IXGBE_TX_FLAGS_CSUM (u32)(1) | |
90 | #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1) | |
91 | #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2) | |
92 | #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3) | |
eacd73f7 YZ |
93 | #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4) |
94 | #define IXGBE_TX_FLAGS_FSO (u32)(1 << 5) | |
9a799d71 | 95 | #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 |
2f90b865 | 96 | #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000 |
9a799d71 AK |
97 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 |
98 | ||
0a924578 PWJ |
99 | #define IXGBE_MAX_RSC_INT_RATE 162760 |
100 | ||
7f870475 GR |
101 | #define IXGBE_MAX_VF_MC_ENTRIES 30 |
102 | #define IXGBE_MAX_VF_FUNCTIONS 64 | |
103 | #define IXGBE_MAX_VFTA_ENTRIES 128 | |
104 | #define MAX_EMULATION_MAC_ADDRS 16 | |
105 | #define VMDQ_P(p) ((p) + adapter->num_vfs) | |
106 | ||
107 | struct vf_data_storage { | |
108 | unsigned char vf_mac_addresses[ETH_ALEN]; | |
109 | u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; | |
110 | u16 num_vf_mc_hashes; | |
111 | u16 default_vf_vlan_id; | |
112 | u16 vlans_enabled; | |
7f870475 GR |
113 | bool clear_to_send; |
114 | int rar; | |
115 | }; | |
116 | ||
9a799d71 AK |
117 | /* wrapper around a pointer to a socket buffer, |
118 | * so a DMA handle can be stored along with the buffer */ | |
119 | struct ixgbe_tx_buffer { | |
120 | struct sk_buff *skb; | |
121 | dma_addr_t dma; | |
122 | unsigned long time_stamp; | |
123 | u16 length; | |
124 | u16 next_to_watch; | |
e5a43549 | 125 | u16 mapped_as_page; |
9a799d71 AK |
126 | }; |
127 | ||
128 | struct ixgbe_rx_buffer { | |
129 | struct sk_buff *skb; | |
130 | dma_addr_t dma; | |
131 | struct page *page; | |
132 | dma_addr_t page_dma; | |
762f4c57 | 133 | unsigned int page_offset; |
9a799d71 AK |
134 | }; |
135 | ||
136 | struct ixgbe_queue_stats { | |
137 | u64 packets; | |
138 | u64 bytes; | |
139 | }; | |
140 | ||
141 | struct ixgbe_ring { | |
9a799d71 | 142 | void *desc; /* descriptor ring memory */ |
9a799d71 AK |
143 | union { |
144 | struct ixgbe_tx_buffer *tx_buffer_info; | |
145 | struct ixgbe_rx_buffer *rx_buffer_info; | |
146 | }; | |
ae540af1 JB |
147 | u8 atr_sample_rate; |
148 | u8 atr_count; | |
149 | u16 count; /* amount of descriptors */ | |
150 | u16 rx_buf_len; | |
151 | u16 next_to_use; | |
152 | u16 next_to_clean; | |
153 | ||
154 | u8 queue_index; /* needed for multiqueue queue management */ | |
9a799d71 | 155 | |
6e455b89 YZ |
156 | #define IXGBE_RING_RX_PS_ENABLED (u8)(1) |
157 | u8 flags; /* per ring feature flags */ | |
9a799d71 AK |
158 | u16 head; |
159 | u16 tail; | |
160 | ||
f494e8fa AV |
161 | unsigned int total_bytes; |
162 | unsigned int total_packets; | |
9a799d71 | 163 | |
5dd2d332 | 164 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
165 | /* cpu for tx queue */ |
166 | int cpu; | |
167 | #endif | |
ae540af1 JB |
168 | |
169 | u16 work_limit; /* max work per interrupt */ | |
170 | u16 reg_idx; /* holds the special value that gets | |
171 | * the hardware register offset | |
172 | * associated with this ring, which is | |
173 | * different for DCB and RSS modes | |
174 | */ | |
175 | ||
9a799d71 | 176 | struct ixgbe_queue_stats stats; |
c4cf55e5 | 177 | unsigned long reinit_state; |
4a0b9ca0 | 178 | int numa_node; |
ae540af1 | 179 | u64 rsc_count; /* stat for coalesced packets */ |
94b982b2 | 180 | u64 rsc_flush; /* stats for flushed packets */ |
7ca3bc58 JB |
181 | u32 restart_queue; /* track tx queue restarts */ |
182 | u32 non_eop_descs; /* track hardware descriptor chaining */ | |
9a799d71 | 183 | |
ae540af1 JB |
184 | unsigned int size; /* length in bytes */ |
185 | dma_addr_t dma; /* phys. address of descriptor ring */ | |
7ca3bc58 | 186 | } ____cacheline_internodealigned_in_smp; |
9a799d71 | 187 | |
c7e4358a SN |
188 | enum ixgbe_ring_f_enum { |
189 | RING_F_NONE = 0, | |
190 | RING_F_DCB, | |
7f870475 | 191 | RING_F_VMDQ, /* SR-IOV uses the same ring feature */ |
c7e4358a | 192 | RING_F_RSS, |
c4cf55e5 | 193 | RING_F_FDIR, |
0331a832 YZ |
194 | #ifdef IXGBE_FCOE |
195 | RING_F_FCOE, | |
196 | #endif /* IXGBE_FCOE */ | |
c7e4358a SN |
197 | |
198 | RING_F_ARRAY_SIZE /* must be last in enum set */ | |
199 | }; | |
200 | ||
2f90b865 | 201 | #define IXGBE_MAX_DCB_INDICES 8 |
021230d4 | 202 | #define IXGBE_MAX_RSS_INDICES 16 |
7f870475 | 203 | #define IXGBE_MAX_VMDQ_INDICES 64 |
c4cf55e5 | 204 | #define IXGBE_MAX_FDIR_INDICES 64 |
0331a832 YZ |
205 | #ifdef IXGBE_FCOE |
206 | #define IXGBE_MAX_FCOE_INDICES 8 | |
207 | #endif /* IXGBE_FCOE */ | |
021230d4 AV |
208 | struct ixgbe_ring_feature { |
209 | int indices; | |
210 | int mask; | |
7ca3bc58 | 211 | } ____cacheline_internodealigned_in_smp; |
021230d4 | 212 | |
e8e26350 PW |
213 | #define MAX_RX_QUEUES 128 |
214 | #define MAX_TX_QUEUES 128 | |
021230d4 | 215 | |
2f90b865 AD |
216 | #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ |
217 | ? 8 : 1) | |
218 | #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS | |
219 | ||
021230d4 AV |
220 | /* MAX_MSIX_Q_VECTORS of these are allocated, |
221 | * but we only use one per queue-specific vector. | |
222 | */ | |
223 | struct ixgbe_q_vector { | |
224 | struct ixgbe_adapter *adapter; | |
fe49f04a AD |
225 | unsigned int v_idx; /* index of q_vector within array, also used for |
226 | * finding the bit in EICR and friends that | |
227 | * represents the vector for this ring */ | |
021230d4 AV |
228 | struct napi_struct napi; |
229 | DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */ | |
230 | DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */ | |
231 | u8 rxr_count; /* Rx ring count assigned to this vector */ | |
232 | u8 txr_count; /* Tx ring count assigned to this vector */ | |
30efa5a3 JB |
233 | u8 tx_itr; |
234 | u8 rx_itr; | |
021230d4 AV |
235 | u32 eitr; |
236 | }; | |
237 | ||
9a799d71 | 238 | /* Helper macros to switch between ints/sec and what the register uses. |
509ee935 JB |
239 | * And yes, it's the same math going both ways. The lowest value |
240 | * supported by all of the ixgbe hardware is 8. | |
9a799d71 AK |
241 | */ |
242 | #define EITR_INTS_PER_SEC_TO_REG(_eitr) \ | |
509ee935 | 243 | ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8) |
9a799d71 AK |
244 | #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG |
245 | ||
246 | #define IXGBE_DESC_UNUSED(R) \ | |
247 | ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ | |
248 | (R)->next_to_clean - (R)->next_to_use - 1) | |
249 | ||
250 | #define IXGBE_RX_DESC_ADV(R, i) \ | |
251 | (&(((union ixgbe_adv_rx_desc *)((R).desc))[i])) | |
252 | #define IXGBE_TX_DESC_ADV(R, i) \ | |
253 | (&(((union ixgbe_adv_tx_desc *)((R).desc))[i])) | |
254 | #define IXGBE_TX_CTXTDESC_ADV(R, i) \ | |
255 | (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i])) | |
256 | ||
257 | #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128 | |
63f39bd1 YZ |
258 | #ifdef IXGBE_FCOE |
259 | /* Use 3K as the baby jumbo frame size for FCoE */ | |
260 | #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 | |
261 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 262 | |
021230d4 AV |
263 | #define OTHER_VECTOR 1 |
264 | #define NON_Q_VECTORS (OTHER_VECTOR) | |
265 | ||
e8e26350 PW |
266 | #define MAX_MSIX_VECTORS_82599 64 |
267 | #define MAX_MSIX_Q_VECTORS_82599 64 | |
eb7f139c PWJ |
268 | #define MAX_MSIX_VECTORS_82598 18 |
269 | #define MAX_MSIX_Q_VECTORS_82598 16 | |
270 | ||
e8e26350 PW |
271 | #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599 |
272 | #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 | |
eb7f139c | 273 | |
021230d4 | 274 | #define MIN_MSIX_Q_VECTORS 2 |
021230d4 AV |
275 | #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) |
276 | ||
9a799d71 AK |
277 | /* board specific private data structure */ |
278 | struct ixgbe_adapter { | |
279 | struct timer_list watchdog_timer; | |
280 | struct vlan_group *vlgrp; | |
281 | u16 bd_number; | |
9a799d71 | 282 | struct work_struct reset_task; |
7a921c93 | 283 | struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS]; |
e8e26350 | 284 | char name[MAX_MSIX_COUNT][IFNAMSIZ + 9]; |
2f90b865 AD |
285 | struct ixgbe_dcb_config dcb_cfg; |
286 | struct ixgbe_dcb_config temp_dcb_cfg; | |
287 | u8 dcb_set_bitmap; | |
264857b8 | 288 | enum ixgbe_fc_mode last_lfc_mode; |
9a799d71 | 289 | |
f494e8fa | 290 | /* Interrupt Throttle Rate */ |
f7554a2b NS |
291 | u32 rx_itr_setting; |
292 | u32 tx_itr_setting; | |
f494e8fa AV |
293 | u16 eitr_low; |
294 | u16 eitr_high; | |
295 | ||
9a799d71 | 296 | /* TX */ |
4a0b9ca0 | 297 | struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; |
30efa5a3 | 298 | int num_tx_queues; |
9a799d71 AK |
299 | u32 tx_timeout_count; |
300 | bool detect_tx_hung; | |
301 | ||
7ca3bc58 JB |
302 | u64 restart_queue; |
303 | u64 lsc_int; | |
304 | ||
9a799d71 | 305 | /* RX */ |
4a0b9ca0 | 306 | struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp; |
30efa5a3 | 307 | int num_rx_queues; |
7f870475 GR |
308 | int num_rx_pools; /* == num_rx_queues in 82598 */ |
309 | int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ | |
9a799d71 | 310 | u64 hw_csum_rx_error; |
e8e26350 | 311 | u64 hw_rx_no_dma_resources; |
9a799d71 | 312 | u64 non_eop_descs; |
021230d4 | 313 | int num_msix_vectors; |
eb7f139c | 314 | int max_msix_q_vectors; /* true count of q_vectors for device */ |
c7e4358a | 315 | struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; |
9a799d71 AK |
316 | struct msix_entry *msix_entries; |
317 | ||
9a799d71 AK |
318 | u32 alloc_rx_page_failed; |
319 | u32 alloc_rx_buff_failed; | |
320 | ||
021230d4 AV |
321 | /* Some features need tri-state capability, |
322 | * thus the additional *_CAPABLE flags. | |
323 | */ | |
9a799d71 | 324 | u32 flags; |
96b0e0f6 JB |
325 | #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1) |
326 | #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1) | |
327 | #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2) | |
328 | #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3) | |
329 | #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4) | |
330 | #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6) | |
331 | #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7) | |
332 | #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8) | |
333 | #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9) | |
334 | #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10) | |
335 | #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11) | |
336 | #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12) | |
337 | #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13) | |
e8e26350 | 338 | #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14) |
96b0e0f6 JB |
339 | #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16) |
340 | #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17) | |
341 | #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18) | |
342 | #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19) | |
0befdb3e | 343 | #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20) |
96b0e0f6 | 344 | #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22) |
10eec955 JF |
345 | #define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23) |
346 | #define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24) | |
347 | #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25) | |
348 | #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26) | |
349 | #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27) | |
350 | #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28) | |
351 | #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29) | |
352 | #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30) | |
96b0e0f6 | 353 | |
df647b5c PWJ |
354 | u32 flags2; |
355 | #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1) | |
356 | #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) | |
96b0e0f6 JB |
357 | /* default to trying for four seconds */ |
358 | #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) | |
9a799d71 AK |
359 | |
360 | /* OS defined structs */ | |
361 | struct net_device *netdev; | |
362 | struct pci_dev *pdev; | |
9a799d71 | 363 | |
da4dd0f7 PWJ |
364 | u32 test_icr; |
365 | struct ixgbe_ring test_tx_ring; | |
366 | struct ixgbe_ring test_rx_ring; | |
367 | ||
9a799d71 AK |
368 | /* structs defined in ixgbe_hw.h */ |
369 | struct ixgbe_hw hw; | |
370 | u16 msg_enable; | |
371 | struct ixgbe_hw_stats stats; | |
021230d4 AV |
372 | |
373 | /* Interrupt Throttle Rate */ | |
f7554a2b NS |
374 | u32 rx_eitr_param; |
375 | u32 tx_eitr_param; | |
9a799d71 AK |
376 | |
377 | unsigned long state; | |
378 | u64 tx_busy; | |
30efa5a3 JB |
379 | unsigned int tx_ring_count; |
380 | unsigned int rx_ring_count; | |
cf8280ee JB |
381 | |
382 | u32 link_speed; | |
383 | bool link_up; | |
384 | unsigned long link_check_timeout; | |
385 | ||
386 | struct work_struct watchdog_task; | |
c4900be0 DS |
387 | struct work_struct sfp_task; |
388 | struct timer_list sfp_timer; | |
e8e26350 PW |
389 | struct work_struct multispeed_fiber_task; |
390 | struct work_struct sfp_config_module_task; | |
c4cf55e5 PWJ |
391 | u32 fdir_pballoc; |
392 | u32 atr_sample_rate; | |
393 | spinlock_t fdir_perfect_lock; | |
394 | struct work_struct fdir_reinit_task; | |
d0ed8937 YZ |
395 | #ifdef IXGBE_FCOE |
396 | struct ixgbe_fcoe fcoe; | |
397 | #endif /* IXGBE_FCOE */ | |
94b982b2 MC |
398 | u64 rsc_total_count; |
399 | u64 rsc_total_flush; | |
e8e26350 | 400 | u32 wol; |
34b0368c | 401 | u16 eeprom_version; |
7f870475 | 402 | |
1a6c14a2 JB |
403 | int node; |
404 | ||
7f870475 GR |
405 | /* SR-IOV */ |
406 | DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); | |
407 | unsigned int num_vfs; | |
408 | struct vf_data_storage *vfinfo; | |
9a799d71 AK |
409 | }; |
410 | ||
411 | enum ixbge_state_t { | |
412 | __IXGBE_TESTING, | |
413 | __IXGBE_RESETTING, | |
c4900be0 | 414 | __IXGBE_DOWN, |
c4cf55e5 | 415 | __IXGBE_FDIR_INIT_DONE, |
c4900be0 | 416 | __IXGBE_SFP_MODULE_NOT_FOUND |
9a799d71 AK |
417 | }; |
418 | ||
419 | enum ixgbe_boards { | |
3957d63d | 420 | board_82598, |
e8e26350 | 421 | board_82599, |
9a799d71 AK |
422 | }; |
423 | ||
3957d63d | 424 | extern struct ixgbe_info ixgbe_82598_info; |
e8e26350 | 425 | extern struct ixgbe_info ixgbe_82599_info; |
7a6b6f51 | 426 | #ifdef CONFIG_IXGBE_DCB |
32953543 | 427 | extern const struct dcbnl_rtnl_ops dcbnl_ops; |
2f90b865 AD |
428 | extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg, |
429 | struct ixgbe_dcb_config *dst_dcb_cfg, | |
430 | int tc_max); | |
431 | #endif | |
9a799d71 AK |
432 | |
433 | extern char ixgbe_driver_name[]; | |
9c8eb720 | 434 | extern const char ixgbe_driver_version[]; |
9a799d71 AK |
435 | |
436 | extern int ixgbe_up(struct ixgbe_adapter *adapter); | |
437 | extern void ixgbe_down(struct ixgbe_adapter *adapter); | |
d4f80882 | 438 | extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); |
9a799d71 | 439 | extern void ixgbe_reset(struct ixgbe_adapter *adapter); |
9a799d71 | 440 | extern void ixgbe_set_ethtool_ops(struct net_device *netdev); |
b4617240 PW |
441 | extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); |
442 | extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); | |
443 | extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); | |
444 | extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *); | |
445 | extern void ixgbe_update_stats(struct ixgbe_adapter *adapter); | |
2f90b865 | 446 | extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); |
7a921c93 | 447 | extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); |
fe49f04a AD |
448 | extern void ixgbe_write_eitr(struct ixgbe_q_vector *); |
449 | extern int ethtool_ioctl(struct ifreq *ifr); | |
ffff4772 PWJ |
450 | extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); |
451 | extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc); | |
452 | extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc); | |
453 | extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, | |
454 | struct ixgbe_atr_input *input, | |
455 | u8 queue); | |
9a713e7c PW |
456 | extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, |
457 | struct ixgbe_atr_input *input, | |
458 | struct ixgbe_atr_input_masks *input_masks, | |
459 | u16 soft_id, u8 queue); | |
ffff4772 PWJ |
460 | extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, |
461 | u16 vlan_id); | |
462 | extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, | |
463 | u32 src_addr); | |
464 | extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, | |
465 | u32 dst_addr); | |
ffff4772 PWJ |
466 | extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, |
467 | u16 src_port); | |
468 | extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, | |
469 | u16 dst_port); | |
470 | extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, | |
471 | u16 flex_byte); | |
ffff4772 PWJ |
472 | extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, |
473 | u8 l4type); | |
7f870475 | 474 | extern void ixgbe_set_rx_mode(struct net_device *netdev); |
eacd73f7 YZ |
475 | #ifdef IXGBE_FCOE |
476 | extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); | |
477 | extern int ixgbe_fso(struct ixgbe_adapter *adapter, | |
478 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, | |
479 | u32 tx_flags, u8 *hdr_len); | |
332d4a7d YZ |
480 | extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter); |
481 | extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, | |
482 | union ixgbe_adv_rx_desc *rx_desc, | |
483 | struct sk_buff *skb); | |
484 | extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, | |
485 | struct scatterlist *sgl, unsigned int sgc); | |
486 | extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); | |
8450ff8c YZ |
487 | extern int ixgbe_fcoe_enable(struct net_device *netdev); |
488 | extern int ixgbe_fcoe_disable(struct net_device *netdev); | |
6ee16520 YZ |
489 | #ifdef CONFIG_IXGBE_DCB |
490 | extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); | |
491 | extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); | |
492 | #endif /* CONFIG_IXGBE_DCB */ | |
61a1fa10 | 493 | extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); |
eacd73f7 | 494 | #endif /* IXGBE_FCOE */ |
9a799d71 AK |
495 | |
496 | #endif /* _IXGBE_H_ */ |