projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /******************************************************************************* |
| 2 | ||
| 3 | ||
| d3f464b5 | 4 | Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved. |
| 1da177e4 LT |
5 | |
| 6 | This program is free software; you can redistribute it and/or modify it | |
| 7 | under the terms of the GNU General Public License as published by the Free | |
| 8 | Software Foundation; either version 2 of the License, or (at your option) | |
| 9 | any later version. | |
| 10 | ||
| 11 | This program is distributed in the hope that it will be useful, but WITHOUT | |
| 12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 14 | more details. | |
| 15 | ||
| 16 | You should have received a copy of the GNU General Public License along with | |
| 17 | this program; if not, write to the Free Software Foundation, Inc., 59 | |
| 18 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
| 19 | ||
| 20 | The full GNU General Public License is included in this distribution in the | |
| 21 | file called LICENSE. | |
| 22 | ||
| 23 | Contact Information: | |
| 24 | Linux NICS <linux.nics@intel.com> | |
| 25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
| 26 | ||
| 27 | *******************************************************************************/ | |
| 28 | ||
| 29 | /* glue for the OS independent part of ixgb | |
| 30 | * includes register access macros | |
| 31 | */ | |
| 32 | ||
| 33 | #ifndef _IXGB_OSDEP_H_ | |
| 34 | #define _IXGB_OSDEP_H_ | |
| 35 | ||
| 36 | #include <linux/types.h> | |
| 37 | #include <linux/pci.h> | |
| 38 | #include <linux/delay.h> | |
| 39 | #include <asm/io.h> | |
| 40 | #include <linux/interrupt.h> | |
| 41 | #include <linux/sched.h> | |
| 42 | ||
| 43 | #ifndef msec_delay | |
| 44 | #define msec_delay(x) do { if(in_interrupt()) { \ | |
| 45 | /* Don't mdelay in interrupt context! */ \ | |
| 46 | BUG(); \ | |
| 47 | } else { \ | |
| 37d16f82 | 48 | msleep(x); \ |
| 1da177e4 LT |
49 | } } while(0) |
| 50 | #endif | |
| 51 | ||
| 52 | #define PCI_COMMAND_REGISTER PCI_COMMAND | |
| 53 | #define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE | |
| 54 | ||
| 55 | typedef enum { | |
| 56 | #undef FALSE | |
| 57 | FALSE = 0, | |
| 58 | #undef TRUE | |
| 59 | TRUE = 1 | |
| 60 | } boolean_t; | |
| 61 | ||
| 62 | #undef ASSERT | |
| 63 | #define ASSERT(x) if(!(x)) BUG() | |
| 64 | #define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B) | |
| 65 | ||
| 66 | #ifdef DBG | |
| 67 | #define DEBUGOUT(S) printk(KERN_DEBUG S "\n") | |
| 68 | #define DEBUGOUT1(S, A...) printk(KERN_DEBUG S "\n", A) | |
| 69 | #else | |
| 70 | #define DEBUGOUT(S) | |
| 71 | #define DEBUGOUT1(S, A...) | |
| 72 | #endif | |
| 73 | ||
| 74 | #define DEBUGFUNC(F) DEBUGOUT(F) | |
| 75 | #define DEBUGOUT2 DEBUGOUT1 | |
| 76 | #define DEBUGOUT3 DEBUGOUT2 | |
| 77 | #define DEBUGOUT7 DEBUGOUT3 | |
| 78 | ||
| 79 | #define IXGB_WRITE_REG(a, reg, value) ( \ | |
| 80 | writel((value), ((a)->hw_addr + IXGB_##reg))) | |
| 81 | ||
| 82 | #define IXGB_READ_REG(a, reg) ( \ | |
| 83 | readl((a)->hw_addr + IXGB_##reg)) | |
| 84 | ||
| 85 | #define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) ( \ | |
| 86 | writel((value), ((a)->hw_addr + IXGB_##reg + ((offset) << 2)))) | |
| 87 | ||
| 88 | #define IXGB_READ_REG_ARRAY(a, reg, offset) ( \ | |
| 89 | readl((a)->hw_addr + IXGB_##reg + ((offset) << 2))) | |
| 90 | ||
| 91 | #define IXGB_WRITE_FLUSH(a) IXGB_READ_REG(a, STATUS) | |
| 92 | ||
| 93 | #define IXGB_MEMCPY memcpy | |
| 94 | ||
| 95 | #endif /* _IXGB_OSDEP_H_ */ |