Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Alchemy Semi Au1000 IrDA driver | |
3 | * | |
4 | * Copyright 2001 MontaVista Software Inc. | |
5 | * Author: MontaVista Software, Inc. | |
6 | * ppopov@mvista.com or source@mvista.com | |
7 | * | |
8 | * This program is free software; you can distribute it and/or modify it | |
9 | * under the terms of the GNU General Public License (Version 2) as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | * for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
e8478de3 | 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
1da177e4 | 19 | */ |
cd671c16 | 20 | |
9178af9a | 21 | #include <linux/clk.h> |
cd671c16 | 22 | #include <linux/module.h> |
1da177e4 | 23 | #include <linux/netdevice.h> |
1da177e4 | 24 | #include <linux/interrupt.h> |
cd671c16 ML |
25 | #include <linux/platform_device.h> |
26 | #include <linux/slab.h> | |
cd671c16 | 27 | #include <linux/types.h> |
94d8f2b1 | 28 | #include <linux/ioport.h> |
1da177e4 LT |
29 | |
30 | #include <net/irda/irda.h> | |
31 | #include <net/irda/irmod.h> | |
32 | #include <net/irda/wrapper.h> | |
33 | #include <net/irda/irda_device.h> | |
cd671c16 ML |
34 | #include <asm/mach-au1x00/au1000.h> |
35 | ||
36 | /* registers */ | |
37 | #define IR_RING_PTR_STATUS 0x00 | |
38 | #define IR_RING_BASE_ADDR_H 0x04 | |
39 | #define IR_RING_BASE_ADDR_L 0x08 | |
40 | #define IR_RING_SIZE 0x0C | |
41 | #define IR_RING_PROMPT 0x10 | |
42 | #define IR_RING_ADDR_CMPR 0x14 | |
43 | #define IR_INT_CLEAR 0x18 | |
44 | #define IR_CONFIG_1 0x20 | |
45 | #define IR_SIR_FLAGS 0x24 | |
46 | #define IR_STATUS 0x28 | |
47 | #define IR_READ_PHY_CONFIG 0x2C | |
48 | #define IR_WRITE_PHY_CONFIG 0x30 | |
49 | #define IR_MAX_PKT_LEN 0x34 | |
50 | #define IR_RX_BYTE_CNT 0x38 | |
51 | #define IR_CONFIG_2 0x3C | |
52 | #define IR_ENABLE 0x40 | |
53 | ||
54 | /* Config1 */ | |
55 | #define IR_RX_INVERT_LED (1 << 0) | |
56 | #define IR_TX_INVERT_LED (1 << 1) | |
57 | #define IR_ST (1 << 2) | |
58 | #define IR_SF (1 << 3) | |
59 | #define IR_SIR (1 << 4) | |
60 | #define IR_MIR (1 << 5) | |
61 | #define IR_FIR (1 << 6) | |
62 | #define IR_16CRC (1 << 7) | |
63 | #define IR_TD (1 << 8) | |
64 | #define IR_RX_ALL (1 << 9) | |
65 | #define IR_DMA_ENABLE (1 << 10) | |
66 | #define IR_RX_ENABLE (1 << 11) | |
67 | #define IR_TX_ENABLE (1 << 12) | |
68 | #define IR_LOOPBACK (1 << 14) | |
69 | #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ | |
70 | IR_RX_ALL | IR_RX_ENABLE | IR_SF | \ | |
71 | IR_16CRC) | |
72 | ||
73 | /* ir_status */ | |
74 | #define IR_RX_STATUS (1 << 9) | |
75 | #define IR_TX_STATUS (1 << 10) | |
76 | #define IR_PHYEN (1 << 15) | |
77 | ||
78 | /* ir_write_phy_config */ | |
79 | #define IR_BR(x) (((x) & 0x3f) << 10) /* baud rate */ | |
80 | #define IR_PW(x) (((x) & 0x1f) << 5) /* pulse width */ | |
81 | #define IR_P(x) ((x) & 0x1f) /* preamble bits */ | |
82 | ||
83 | /* Config2 */ | |
84 | #define IR_MODE_INV (1 << 0) | |
85 | #define IR_ONE_PIN (1 << 1) | |
86 | #define IR_PHYCLK_40MHZ (0 << 2) | |
87 | #define IR_PHYCLK_48MHZ (1 << 2) | |
88 | #define IR_PHYCLK_56MHZ (2 << 2) | |
89 | #define IR_PHYCLK_64MHZ (3 << 2) | |
90 | #define IR_DP (1 << 4) | |
91 | #define IR_DA (1 << 5) | |
92 | #define IR_FLT_HIGH (0 << 6) | |
93 | #define IR_FLT_MEDHI (1 << 6) | |
94 | #define IR_FLT_MEDLO (2 << 6) | |
95 | #define IR_FLT_LO (3 << 6) | |
96 | #define IR_IEN (1 << 8) | |
97 | ||
98 | /* ir_enable */ | |
99 | #define IR_HC (1 << 3) /* divide SBUS clock by 2 */ | |
100 | #define IR_CE (1 << 2) /* clock enable */ | |
101 | #define IR_C (1 << 1) /* coherency bit */ | |
102 | #define IR_BE (1 << 0) /* set in big endian mode */ | |
103 | ||
104 | #define NUM_IR_DESC 64 | |
105 | #define RING_SIZE_4 0x0 | |
106 | #define RING_SIZE_16 0x3 | |
107 | #define RING_SIZE_64 0xF | |
108 | #define MAX_NUM_IR_DESC 64 | |
109 | #define MAX_BUF_SIZE 2048 | |
110 | ||
111 | /* Ring descriptor flags */ | |
112 | #define AU_OWN (1 << 7) /* tx,rx */ | |
113 | #define IR_DIS_CRC (1 << 6) /* tx */ | |
114 | #define IR_BAD_CRC (1 << 5) /* tx */ | |
115 | #define IR_NEED_PULSE (1 << 4) /* tx */ | |
116 | #define IR_FORCE_UNDER (1 << 3) /* tx */ | |
117 | #define IR_DISABLE_TX (1 << 2) /* tx */ | |
118 | #define IR_HW_UNDER (1 << 0) /* tx */ | |
119 | #define IR_TX_ERROR (IR_DIS_CRC | IR_BAD_CRC | IR_HW_UNDER) | |
120 | ||
121 | #define IR_PHY_ERROR (1 << 6) /* rx */ | |
122 | #define IR_CRC_ERROR (1 << 5) /* rx */ | |
123 | #define IR_MAX_LEN (1 << 4) /* rx */ | |
124 | #define IR_FIFO_OVER (1 << 3) /* rx */ | |
125 | #define IR_SIR_ERROR (1 << 2) /* rx */ | |
126 | #define IR_RX_ERROR (IR_PHY_ERROR | IR_CRC_ERROR | \ | |
127 | IR_MAX_LEN | IR_FIFO_OVER | IR_SIR_ERROR) | |
128 | ||
129 | struct db_dest { | |
130 | struct db_dest *pnext; | |
131 | volatile u32 *vaddr; | |
132 | dma_addr_t dma_addr; | |
133 | }; | |
134 | ||
135 | struct ring_dest { | |
136 | u8 count_0; /* 7:0 */ | |
137 | u8 count_1; /* 12:8 */ | |
138 | u8 reserved; | |
139 | u8 flags; | |
140 | u8 addr_0; /* 7:0 */ | |
141 | u8 addr_1; /* 15:8 */ | |
142 | u8 addr_2; /* 23:16 */ | |
143 | u8 addr_3; /* 31:24 */ | |
144 | }; | |
145 | ||
146 | /* Private data for each instance */ | |
147 | struct au1k_private { | |
148 | void __iomem *iobase; | |
149 | int irq_rx, irq_tx; | |
150 | ||
151 | struct db_dest *pDBfree; | |
152 | struct db_dest db[2 * NUM_IR_DESC]; | |
153 | volatile struct ring_dest *rx_ring[NUM_IR_DESC]; | |
154 | volatile struct ring_dest *tx_ring[NUM_IR_DESC]; | |
155 | struct db_dest *rx_db_inuse[NUM_IR_DESC]; | |
156 | struct db_dest *tx_db_inuse[NUM_IR_DESC]; | |
157 | u32 rx_head; | |
158 | u32 tx_head; | |
159 | u32 tx_tail; | |
160 | u32 tx_full; | |
161 | ||
162 | iobuff_t rx_buff; | |
163 | ||
164 | struct net_device *netdev; | |
cd671c16 ML |
165 | struct qos_info qos; |
166 | struct irlap_cb *irlap; | |
167 | ||
168 | u8 open; | |
169 | u32 speed; | |
170 | u32 newspeed; | |
1da177e4 | 171 | |
cd671c16 | 172 | struct timer_list timer; |
1da177e4 | 173 | |
cd671c16 ML |
174 | struct resource *ioarea; |
175 | struct au1k_irda_platform_data *platdata; | |
9178af9a | 176 | struct clk *irda_clk; |
cd671c16 | 177 | }; |
1da177e4 LT |
178 | |
179 | static int qos_mtt_bits = 0x07; /* 1 ms or more */ | |
1da177e4 LT |
180 | |
181 | #define RUN_AT(x) (jiffies + (x)) | |
182 | ||
cd671c16 ML |
183 | static void au1k_irda_plat_set_phy_mode(struct au1k_private *p, int mode) |
184 | { | |
185 | if (p->platdata && p->platdata->set_phy_mode) | |
186 | p->platdata->set_phy_mode(mode); | |
187 | } | |
1da177e4 | 188 | |
cd671c16 ML |
189 | static inline unsigned long irda_read(struct au1k_private *p, |
190 | unsigned long ofs) | |
191 | { | |
192 | /* | |
193 | * IrDA peripheral bug. You have to read the register | |
194 | * twice to get the right value. | |
195 | */ | |
196 | (void)__raw_readl(p->iobase + ofs); | |
197 | return __raw_readl(p->iobase + ofs); | |
1da177e4 LT |
198 | } |
199 | ||
cd671c16 ML |
200 | static inline void irda_write(struct au1k_private *p, unsigned long ofs, |
201 | unsigned long val) | |
202 | { | |
203 | __raw_writel(val, p->iobase + ofs); | |
204 | wmb(); | |
205 | } | |
1da177e4 LT |
206 | |
207 | /* | |
208 | * Buffer allocation/deallocation routines. The buffer descriptor returned | |
cd671c16 | 209 | * has the virtual and dma address of a buffer suitable for |
1da177e4 LT |
210 | * both, receive and transmit operations. |
211 | */ | |
cd671c16 | 212 | static struct db_dest *GetFreeDB(struct au1k_private *aup) |
1da177e4 | 213 | { |
cd671c16 ML |
214 | struct db_dest *db; |
215 | db = aup->pDBfree; | |
1da177e4 | 216 | |
cd671c16 ML |
217 | if (db) |
218 | aup->pDBfree = db->pnext; | |
219 | return db; | |
1da177e4 LT |
220 | } |
221 | ||
1da177e4 LT |
222 | /* |
223 | DMA memory allocation, derived from pci_alloc_consistent. | |
224 | However, the Au1000 data cache is coherent (when programmed | |
225 | so), therefore we return KSEG0 address, not KSEG1. | |
226 | */ | |
cd671c16 | 227 | static void *dma_alloc(size_t size, dma_addr_t *dma_handle) |
1da177e4 LT |
228 | { |
229 | void *ret; | |
230 | int gfp = GFP_ATOMIC | GFP_DMA; | |
231 | ||
cd671c16 | 232 | ret = (void *)__get_free_pages(gfp, get_order(size)); |
1da177e4 LT |
233 | |
234 | if (ret != NULL) { | |
235 | memset(ret, 0, size); | |
236 | *dma_handle = virt_to_bus(ret); | |
237 | ret = (void *)KSEG0ADDR(ret); | |
238 | } | |
239 | return ret; | |
240 | } | |
241 | ||
1da177e4 LT |
242 | static void dma_free(void *vaddr, size_t size) |
243 | { | |
244 | vaddr = (void *)KSEG0ADDR(vaddr); | |
245 | free_pages((unsigned long) vaddr, get_order(size)); | |
246 | } | |
247 | ||
248 | ||
cd671c16 | 249 | static void setup_hw_rings(struct au1k_private *aup, u32 rx_base, u32 tx_base) |
1da177e4 LT |
250 | { |
251 | int i; | |
cd671c16 ML |
252 | for (i = 0; i < NUM_IR_DESC; i++) { |
253 | aup->rx_ring[i] = (volatile struct ring_dest *) | |
254 | (rx_base + sizeof(struct ring_dest) * i); | |
1da177e4 | 255 | } |
cd671c16 ML |
256 | for (i = 0; i < NUM_IR_DESC; i++) { |
257 | aup->tx_ring[i] = (volatile struct ring_dest *) | |
258 | (tx_base + sizeof(struct ring_dest) * i); | |
1da177e4 LT |
259 | } |
260 | } | |
261 | ||
1da177e4 LT |
262 | static int au1k_irda_init_iobuf(iobuff_t *io, int size) |
263 | { | |
264 | io->head = kmalloc(size, GFP_KERNEL); | |
265 | if (io->head != NULL) { | |
cd671c16 ML |
266 | io->truesize = size; |
267 | io->in_frame = FALSE; | |
268 | io->state = OUTSIDE_FRAME; | |
269 | io->data = io->head; | |
1da177e4 LT |
270 | } |
271 | return io->head ? 0 : -ENOMEM; | |
272 | } | |
273 | ||
cd671c16 ML |
274 | /* |
275 | * Set the IrDA communications speed. | |
276 | */ | |
277 | static int au1k_irda_set_speed(struct net_device *dev, int speed) | |
1da177e4 LT |
278 | { |
279 | struct au1k_private *aup = netdev_priv(dev); | |
cd671c16 ML |
280 | volatile struct ring_dest *ptxd; |
281 | unsigned long control; | |
282 | int ret = 0, timeout = 10, i; | |
1da177e4 | 283 | |
cd671c16 ML |
284 | if (speed == aup->speed) |
285 | return ret; | |
1da177e4 | 286 | |
cd671c16 ML |
287 | /* disable PHY first */ |
288 | au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF); | |
289 | irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) & ~IR_PHYEN); | |
1da177e4 | 290 | |
cd671c16 ML |
291 | /* disable RX/TX */ |
292 | irda_write(aup, IR_CONFIG_1, | |
293 | irda_read(aup, IR_CONFIG_1) & ~(IR_RX_ENABLE | IR_TX_ENABLE)); | |
294 | msleep(20); | |
295 | while (irda_read(aup, IR_STATUS) & (IR_RX_STATUS | IR_TX_STATUS)) { | |
296 | msleep(20); | |
297 | if (!timeout--) { | |
298 | printk(KERN_ERR "%s: rx/tx disable timeout\n", | |
299 | dev->name); | |
300 | break; | |
301 | } | |
302 | } | |
1da177e4 | 303 | |
cd671c16 ML |
304 | /* disable DMA */ |
305 | irda_write(aup, IR_CONFIG_1, | |
306 | irda_read(aup, IR_CONFIG_1) & ~IR_DMA_ENABLE); | |
307 | msleep(20); | |
1da177e4 | 308 | |
cd671c16 ML |
309 | /* After we disable tx/rx. the index pointers go back to zero. */ |
310 | aup->tx_head = aup->tx_tail = aup->rx_head = 0; | |
311 | for (i = 0; i < NUM_IR_DESC; i++) { | |
312 | ptxd = aup->tx_ring[i]; | |
313 | ptxd->flags = 0; | |
314 | ptxd->count_0 = 0; | |
315 | ptxd->count_1 = 0; | |
316 | } | |
1da177e4 | 317 | |
cd671c16 ML |
318 | for (i = 0; i < NUM_IR_DESC; i++) { |
319 | ptxd = aup->rx_ring[i]; | |
320 | ptxd->count_0 = 0; | |
321 | ptxd->count_1 = 0; | |
322 | ptxd->flags = AU_OWN; | |
323 | } | |
1da177e4 | 324 | |
cd671c16 ML |
325 | if (speed == 4000000) |
326 | au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_FIR); | |
327 | else | |
328 | au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR); | |
1da177e4 | 329 | |
cd671c16 ML |
330 | switch (speed) { |
331 | case 9600: | |
332 | irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(11) | IR_PW(12)); | |
333 | irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); | |
334 | break; | |
335 | case 19200: | |
336 | irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(5) | IR_PW(12)); | |
337 | irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); | |
338 | break; | |
339 | case 38400: | |
340 | irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(2) | IR_PW(12)); | |
341 | irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); | |
342 | break; | |
343 | case 57600: | |
344 | irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(1) | IR_PW(12)); | |
345 | irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); | |
346 | break; | |
347 | case 115200: | |
348 | irda_write(aup, IR_WRITE_PHY_CONFIG, IR_PW(12)); | |
349 | irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); | |
350 | break; | |
351 | case 4000000: | |
352 | irda_write(aup, IR_WRITE_PHY_CONFIG, IR_P(15)); | |
353 | irda_write(aup, IR_CONFIG_1, IR_FIR | IR_DMA_ENABLE | | |
354 | IR_RX_ENABLE); | |
355 | break; | |
356 | default: | |
357 | printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed); | |
358 | ret = -EINVAL; | |
359 | break; | |
360 | } | |
1da177e4 | 361 | |
cd671c16 ML |
362 | aup->speed = speed; |
363 | irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) | IR_PHYEN); | |
364 | ||
365 | control = irda_read(aup, IR_STATUS); | |
366 | irda_write(aup, IR_RING_PROMPT, 0); | |
367 | ||
368 | if (control & (1 << 14)) { | |
369 | printk(KERN_ERR "%s: configuration error\n", dev->name); | |
370 | } else { | |
371 | if (control & (1 << 11)) | |
372 | printk(KERN_DEBUG "%s Valid SIR config\n", dev->name); | |
373 | if (control & (1 << 12)) | |
374 | printk(KERN_DEBUG "%s Valid MIR config\n", dev->name); | |
375 | if (control & (1 << 13)) | |
376 | printk(KERN_DEBUG "%s Valid FIR config\n", dev->name); | |
377 | if (control & (1 << 10)) | |
378 | printk(KERN_DEBUG "%s TX enabled\n", dev->name); | |
379 | if (control & (1 << 9)) | |
380 | printk(KERN_DEBUG "%s RX enabled\n", dev->name); | |
1da177e4 | 381 | } |
1da177e4 | 382 | |
cd671c16 ML |
383 | return ret; |
384 | } | |
385 | ||
386 | static void update_rx_stats(struct net_device *dev, u32 status, u32 count) | |
387 | { | |
388 | struct net_device_stats *ps = &dev->stats; | |
389 | ||
390 | ps->rx_packets++; | |
391 | ||
392 | if (status & IR_RX_ERROR) { | |
393 | ps->rx_errors++; | |
394 | if (status & (IR_PHY_ERROR | IR_FIFO_OVER)) | |
395 | ps->rx_missed_errors++; | |
396 | if (status & IR_MAX_LEN) | |
397 | ps->rx_length_errors++; | |
398 | if (status & IR_CRC_ERROR) | |
399 | ps->rx_crc_errors++; | |
400 | } else | |
401 | ps->rx_bytes += count; | |
402 | } | |
403 | ||
404 | static void update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len) | |
405 | { | |
406 | struct net_device_stats *ps = &dev->stats; | |
407 | ||
408 | ps->tx_packets++; | |
409 | ps->tx_bytes += pkt_len; | |
410 | ||
411 | if (status & IR_TX_ERROR) { | |
412 | ps->tx_errors++; | |
413 | ps->tx_aborted_errors++; | |
1da177e4 | 414 | } |
cd671c16 ML |
415 | } |
416 | ||
417 | static void au1k_tx_ack(struct net_device *dev) | |
418 | { | |
419 | struct au1k_private *aup = netdev_priv(dev); | |
420 | volatile struct ring_dest *ptxd; | |
421 | ||
422 | ptxd = aup->tx_ring[aup->tx_tail]; | |
423 | while (!(ptxd->flags & AU_OWN) && (aup->tx_tail != aup->tx_head)) { | |
424 | update_tx_stats(dev, ptxd->flags, | |
425 | (ptxd->count_1 << 8) | ptxd->count_0); | |
426 | ptxd->count_0 = 0; | |
427 | ptxd->count_1 = 0; | |
428 | wmb(); | |
429 | aup->tx_tail = (aup->tx_tail + 1) & (NUM_IR_DESC - 1); | |
430 | ptxd = aup->tx_ring[aup->tx_tail]; | |
431 | ||
432 | if (aup->tx_full) { | |
433 | aup->tx_full = 0; | |
434 | netif_wake_queue(dev); | |
435 | } | |
1da177e4 LT |
436 | } |
437 | ||
cd671c16 ML |
438 | if (aup->tx_tail == aup->tx_head) { |
439 | if (aup->newspeed) { | |
440 | au1k_irda_set_speed(dev, aup->newspeed); | |
441 | aup->newspeed = 0; | |
442 | } else { | |
443 | irda_write(aup, IR_CONFIG_1, | |
444 | irda_read(aup, IR_CONFIG_1) & ~IR_TX_ENABLE); | |
445 | irda_write(aup, IR_CONFIG_1, | |
446 | irda_read(aup, IR_CONFIG_1) | IR_RX_ENABLE); | |
447 | irda_write(aup, IR_RING_PROMPT, 0); | |
448 | } | |
449 | } | |
450 | } | |
1da177e4 | 451 | |
cd671c16 ML |
452 | static int au1k_irda_rx(struct net_device *dev) |
453 | { | |
454 | struct au1k_private *aup = netdev_priv(dev); | |
455 | volatile struct ring_dest *prxd; | |
456 | struct sk_buff *skb; | |
457 | struct db_dest *pDB; | |
458 | u32 flags, count; | |
1da177e4 | 459 | |
cd671c16 ML |
460 | prxd = aup->rx_ring[aup->rx_head]; |
461 | flags = prxd->flags; | |
462 | ||
463 | while (!(flags & AU_OWN)) { | |
464 | pDB = aup->rx_db_inuse[aup->rx_head]; | |
465 | count = (prxd->count_1 << 8) | prxd->count_0; | |
466 | if (!(flags & IR_RX_ERROR)) { | |
467 | /* good frame */ | |
468 | update_rx_stats(dev, flags, count); | |
469 | skb = alloc_skb(count + 1, GFP_ATOMIC); | |
470 | if (skb == NULL) { | |
471 | dev->stats.rx_dropped++; | |
472 | continue; | |
473 | } | |
474 | skb_reserve(skb, 1); | |
475 | if (aup->speed == 4000000) | |
476 | skb_put(skb, count); | |
477 | else | |
478 | skb_put(skb, count - 2); | |
479 | skb_copy_to_linear_data(skb, (void *)pDB->vaddr, | |
480 | count - 2); | |
481 | skb->dev = dev; | |
482 | skb_reset_mac_header(skb); | |
483 | skb->protocol = htons(ETH_P_IRDA); | |
484 | netif_rx(skb); | |
485 | prxd->count_0 = 0; | |
486 | prxd->count_1 = 0; | |
487 | } | |
488 | prxd->flags |= AU_OWN; | |
489 | aup->rx_head = (aup->rx_head + 1) & (NUM_IR_DESC - 1); | |
490 | irda_write(aup, IR_RING_PROMPT, 0); | |
491 | ||
492 | /* next descriptor */ | |
493 | prxd = aup->rx_ring[aup->rx_head]; | |
494 | flags = prxd->flags; | |
495 | ||
496 | } | |
497 | return 0; | |
1da177e4 LT |
498 | } |
499 | ||
cd671c16 ML |
500 | static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id) |
501 | { | |
502 | struct net_device *dev = dev_id; | |
503 | struct au1k_private *aup = netdev_priv(dev); | |
504 | ||
505 | irda_write(aup, IR_INT_CLEAR, 0); /* ack irda interrupts */ | |
506 | ||
507 | au1k_irda_rx(dev); | |
508 | au1k_tx_ack(dev); | |
509 | ||
510 | return IRQ_HANDLED; | |
511 | } | |
1da177e4 LT |
512 | |
513 | static int au1k_init(struct net_device *dev) | |
514 | { | |
515 | struct au1k_private *aup = netdev_priv(dev); | |
9178af9a ML |
516 | u32 enable, ring_address, phyck; |
517 | struct clk *c; | |
1da177e4 | 518 | int i; |
1da177e4 | 519 | |
9178af9a ML |
520 | c = clk_get(NULL, "irda_clk"); |
521 | if (IS_ERR(c)) | |
522 | return PTR_ERR(c); | |
523 | i = clk_prepare_enable(c); | |
524 | if (i) { | |
525 | clk_put(c); | |
526 | return i; | |
527 | } | |
528 | ||
529 | switch (clk_get_rate(c)) { | |
530 | case 40000000: | |
531 | phyck = IR_PHYCLK_40MHZ; | |
532 | break; | |
533 | case 48000000: | |
534 | phyck = IR_PHYCLK_48MHZ; | |
535 | break; | |
536 | case 56000000: | |
537 | phyck = IR_PHYCLK_56MHZ; | |
538 | break; | |
539 | case 64000000: | |
540 | phyck = IR_PHYCLK_64MHZ; | |
541 | break; | |
542 | default: | |
543 | clk_disable_unprepare(c); | |
544 | clk_put(c); | |
545 | return -EINVAL; | |
546 | } | |
547 | aup->irda_clk = c; | |
548 | ||
cd671c16 | 549 | enable = IR_HC | IR_CE | IR_C; |
1da177e4 | 550 | #ifndef CONFIG_CPU_LITTLE_ENDIAN |
cd671c16 | 551 | enable |= IR_BE; |
1da177e4 LT |
552 | #endif |
553 | aup->tx_head = 0; | |
554 | aup->tx_tail = 0; | |
555 | aup->rx_head = 0; | |
556 | ||
cd671c16 | 557 | for (i = 0; i < NUM_IR_DESC; i++) |
1da177e4 | 558 | aup->rx_ring[i]->flags = AU_OWN; |
1da177e4 | 559 | |
cd671c16 ML |
560 | irda_write(aup, IR_ENABLE, enable); |
561 | msleep(20); | |
1da177e4 | 562 | |
cd671c16 ML |
563 | /* disable PHY */ |
564 | au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF); | |
565 | irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) & ~IR_PHYEN); | |
566 | msleep(20); | |
1da177e4 | 567 | |
cd671c16 | 568 | irda_write(aup, IR_MAX_PKT_LEN, MAX_BUF_SIZE); |
1da177e4 LT |
569 | |
570 | ring_address = (u32)virt_to_phys((void *)aup->rx_ring[0]); | |
cd671c16 ML |
571 | irda_write(aup, IR_RING_BASE_ADDR_H, ring_address >> 26); |
572 | irda_write(aup, IR_RING_BASE_ADDR_L, (ring_address >> 10) & 0xffff); | |
1da177e4 | 573 | |
cd671c16 ML |
574 | irda_write(aup, IR_RING_SIZE, |
575 | (RING_SIZE_64 << 8) | (RING_SIZE_64 << 12)); | |
1da177e4 | 576 | |
9178af9a | 577 | irda_write(aup, IR_CONFIG_2, phyck | IR_ONE_PIN); |
cd671c16 | 578 | irda_write(aup, IR_RING_ADDR_CMPR, 0); |
1da177e4 LT |
579 | |
580 | au1k_irda_set_speed(dev, 9600); | |
581 | return 0; | |
582 | } | |
583 | ||
584 | static int au1k_irda_start(struct net_device *dev) | |
585 | { | |
1da177e4 | 586 | struct au1k_private *aup = netdev_priv(dev); |
cd671c16 ML |
587 | char hwname[32]; |
588 | int retval; | |
1da177e4 | 589 | |
cd671c16 ML |
590 | retval = au1k_init(dev); |
591 | if (retval) { | |
1da177e4 LT |
592 | printk(KERN_ERR "%s: error in au1k_init\n", dev->name); |
593 | return retval; | |
594 | } | |
595 | ||
cd671c16 ML |
596 | retval = request_irq(aup->irq_tx, &au1k_irda_interrupt, 0, |
597 | dev->name, dev); | |
598 | if (retval) { | |
599 | printk(KERN_ERR "%s: unable to get IRQ %d\n", | |
1da177e4 LT |
600 | dev->name, dev->irq); |
601 | return retval; | |
602 | } | |
cd671c16 ML |
603 | retval = request_irq(aup->irq_rx, &au1k_irda_interrupt, 0, |
604 | dev->name, dev); | |
605 | if (retval) { | |
606 | free_irq(aup->irq_tx, dev); | |
607 | printk(KERN_ERR "%s: unable to get IRQ %d\n", | |
1da177e4 LT |
608 | dev->name, dev->irq); |
609 | return retval; | |
610 | } | |
611 | ||
612 | /* Give self a hardware name */ | |
613 | sprintf(hwname, "Au1000 SIR/FIR"); | |
614 | aup->irlap = irlap_open(dev, &aup->qos, hwname); | |
615 | netif_start_queue(dev); | |
616 | ||
cd671c16 ML |
617 | /* int enable */ |
618 | irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) | IR_IEN); | |
1da177e4 | 619 | |
cd671c16 ML |
620 | /* power up */ |
621 | au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR); | |
622 | ||
623 | aup->timer.expires = RUN_AT((3 * HZ)); | |
1da177e4 LT |
624 | aup->timer.data = (unsigned long)dev; |
625 | return 0; | |
626 | } | |
627 | ||
628 | static int au1k_irda_stop(struct net_device *dev) | |
629 | { | |
630 | struct au1k_private *aup = netdev_priv(dev); | |
631 | ||
cd671c16 ML |
632 | au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF); |
633 | ||
1da177e4 | 634 | /* disable interrupts */ |
cd671c16 ML |
635 | irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) & ~IR_IEN); |
636 | irda_write(aup, IR_CONFIG_1, 0); | |
637 | irda_write(aup, IR_ENABLE, 0); /* disable clock */ | |
1da177e4 LT |
638 | |
639 | if (aup->irlap) { | |
640 | irlap_close(aup->irlap); | |
641 | aup->irlap = NULL; | |
642 | } | |
643 | ||
644 | netif_stop_queue(dev); | |
645 | del_timer(&aup->timer); | |
646 | ||
647 | /* disable the interrupt */ | |
cd671c16 ML |
648 | free_irq(aup->irq_tx, dev); |
649 | free_irq(aup->irq_rx, dev); | |
1da177e4 | 650 | |
9178af9a ML |
651 | clk_disable_unprepare(aup->irda_clk); |
652 | clk_put(aup->irda_clk); | |
653 | ||
cd671c16 | 654 | return 0; |
1da177e4 LT |
655 | } |
656 | ||
1da177e4 LT |
657 | /* |
658 | * Au1000 transmit routine. | |
659 | */ | |
660 | static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) | |
661 | { | |
662 | struct au1k_private *aup = netdev_priv(dev); | |
663 | int speed = irda_get_next_speed(skb); | |
cd671c16 ML |
664 | volatile struct ring_dest *ptxd; |
665 | struct db_dest *pDB; | |
666 | u32 len, flags; | |
1da177e4 | 667 | |
cd671c16 | 668 | if (speed != aup->speed && speed != -1) |
1da177e4 | 669 | aup->newspeed = speed; |
1da177e4 LT |
670 | |
671 | if ((skb->len == 0) && (aup->newspeed)) { | |
672 | if (aup->tx_tail == aup->tx_head) { | |
673 | au1k_irda_set_speed(dev, speed); | |
674 | aup->newspeed = 0; | |
675 | } | |
676 | dev_kfree_skb(skb); | |
6ed10654 | 677 | return NETDEV_TX_OK; |
1da177e4 LT |
678 | } |
679 | ||
680 | ptxd = aup->tx_ring[aup->tx_head]; | |
681 | flags = ptxd->flags; | |
682 | ||
683 | if (flags & AU_OWN) { | |
684 | printk(KERN_DEBUG "%s: tx_full\n", dev->name); | |
685 | netif_stop_queue(dev); | |
686 | aup->tx_full = 1; | |
cd671c16 ML |
687 | return 1; |
688 | } else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) { | |
1da177e4 LT |
689 | printk(KERN_DEBUG "%s: tx_full\n", dev->name); |
690 | netif_stop_queue(dev); | |
691 | aup->tx_full = 1; | |
cd671c16 | 692 | return 1; |
1da177e4 LT |
693 | } |
694 | ||
695 | pDB = aup->tx_db_inuse[aup->tx_head]; | |
696 | ||
697 | #if 0 | |
cd671c16 ML |
698 | if (irda_read(aup, IR_RX_BYTE_CNT) != 0) { |
699 | printk(KERN_DEBUG "tx warning: rx byte cnt %x\n", | |
700 | irda_read(aup, IR_RX_BYTE_CNT)); | |
1da177e4 LT |
701 | } |
702 | #endif | |
cd671c16 | 703 | |
1da177e4 LT |
704 | if (aup->speed == 4000000) { |
705 | /* FIR */ | |
cd671c16 | 706 | skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len); |
1da177e4 LT |
707 | ptxd->count_0 = skb->len & 0xff; |
708 | ptxd->count_1 = (skb->len >> 8) & 0xff; | |
cd671c16 | 709 | } else { |
1da177e4 LT |
710 | /* SIR */ |
711 | len = async_wrap_skb(skb, (u8 *)pDB->vaddr, MAX_BUF_SIZE); | |
712 | ptxd->count_0 = len & 0xff; | |
713 | ptxd->count_1 = (len >> 8) & 0xff; | |
714 | ptxd->flags |= IR_DIS_CRC; | |
1da177e4 LT |
715 | } |
716 | ptxd->flags |= AU_OWN; | |
cd671c16 | 717 | wmb(); |
1da177e4 | 718 | |
cd671c16 ML |
719 | irda_write(aup, IR_CONFIG_1, |
720 | irda_read(aup, IR_CONFIG_1) | IR_TX_ENABLE); | |
721 | irda_write(aup, IR_RING_PROMPT, 0); | |
1da177e4 LT |
722 | |
723 | dev_kfree_skb(skb); | |
724 | aup->tx_head = (aup->tx_head + 1) & (NUM_IR_DESC - 1); | |
6ed10654 | 725 | return NETDEV_TX_OK; |
1da177e4 LT |
726 | } |
727 | ||
1da177e4 LT |
728 | /* |
729 | * The Tx ring has been full longer than the watchdog timeout | |
730 | * value. The transmitter must be hung? | |
731 | */ | |
732 | static void au1k_tx_timeout(struct net_device *dev) | |
733 | { | |
734 | u32 speed; | |
735 | struct au1k_private *aup = netdev_priv(dev); | |
736 | ||
737 | printk(KERN_ERR "%s: tx timeout\n", dev->name); | |
738 | speed = aup->speed; | |
739 | aup->speed = 0; | |
740 | au1k_irda_set_speed(dev, speed); | |
741 | aup->tx_full = 0; | |
742 | netif_wake_queue(dev); | |
743 | } | |
744 | ||
cd671c16 | 745 | static int au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) |
1da177e4 LT |
746 | { |
747 | struct if_irda_req *rq = (struct if_irda_req *)ifreq; | |
748 | struct au1k_private *aup = netdev_priv(dev); | |
749 | int ret = -EOPNOTSUPP; | |
750 | ||
751 | switch (cmd) { | |
752 | case SIOCSBANDWIDTH: | |
753 | if (capable(CAP_NET_ADMIN)) { | |
754 | /* | |
755 | * We are unable to set the speed if the | |
756 | * device is not running. | |
757 | */ | |
758 | if (aup->open) | |
759 | ret = au1k_irda_set_speed(dev, | |
760 | rq->ifr_baudrate); | |
761 | else { | |
762 | printk(KERN_ERR "%s ioctl: !netif_running\n", | |
763 | dev->name); | |
764 | ret = 0; | |
765 | } | |
766 | } | |
767 | break; | |
768 | ||
769 | case SIOCSMEDIABUSY: | |
770 | ret = -EPERM; | |
771 | if (capable(CAP_NET_ADMIN)) { | |
772 | irda_device_set_media_busy(dev, TRUE); | |
773 | ret = 0; | |
774 | } | |
775 | break; | |
776 | ||
777 | case SIOCGRECEIVING: | |
778 | rq->ifr_receiving = 0; | |
779 | break; | |
780 | default: | |
781 | break; | |
782 | } | |
783 | return ret; | |
784 | } | |
785 | ||
cd671c16 ML |
786 | static const struct net_device_ops au1k_irda_netdev_ops = { |
787 | .ndo_open = au1k_irda_start, | |
788 | .ndo_stop = au1k_irda_stop, | |
789 | .ndo_start_xmit = au1k_irda_hard_xmit, | |
790 | .ndo_tx_timeout = au1k_tx_timeout, | |
791 | .ndo_do_ioctl = au1k_irda_ioctl, | |
792 | }; | |
793 | ||
45ac936c | 794 | static int au1k_irda_net_init(struct net_device *dev) |
cd671c16 ML |
795 | { |
796 | struct au1k_private *aup = netdev_priv(dev); | |
797 | struct db_dest *pDB, *pDBfree; | |
798 | int i, err, retval = 0; | |
799 | dma_addr_t temp; | |
800 | ||
801 | err = au1k_irda_init_iobuf(&aup->rx_buff, 14384); | |
802 | if (err) | |
803 | goto out1; | |
804 | ||
805 | dev->netdev_ops = &au1k_irda_netdev_ops; | |
806 | ||
807 | irda_init_max_qos_capabilies(&aup->qos); | |
808 | ||
809 | /* The only value we must override it the baudrate */ | |
810 | aup->qos.baud_rate.bits = IR_9600 | IR_19200 | IR_38400 | | |
811 | IR_57600 | IR_115200 | IR_576000 | (IR_4000000 << 8); | |
812 | ||
813 | aup->qos.min_turn_time.bits = qos_mtt_bits; | |
814 | irda_qos_bits_to_value(&aup->qos); | |
815 | ||
816 | retval = -ENOMEM; | |
817 | ||
818 | /* Tx ring follows rx ring + 512 bytes */ | |
819 | /* we need a 1k aligned buffer */ | |
820 | aup->rx_ring[0] = (struct ring_dest *) | |
821 | dma_alloc(2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)), | |
822 | &temp); | |
823 | if (!aup->rx_ring[0]) | |
824 | goto out2; | |
825 | ||
826 | /* allocate the data buffers */ | |
827 | aup->db[0].vaddr = | |
c2fd03a0 | 828 | dma_alloc(MAX_BUF_SIZE * 2 * NUM_IR_DESC, &temp); |
cd671c16 ML |
829 | if (!aup->db[0].vaddr) |
830 | goto out3; | |
831 | ||
832 | setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512); | |
833 | ||
834 | pDBfree = NULL; | |
835 | pDB = aup->db; | |
836 | for (i = 0; i < (2 * NUM_IR_DESC); i++) { | |
837 | pDB->pnext = pDBfree; | |
838 | pDBfree = pDB; | |
839 | pDB->vaddr = | |
840 | (u32 *)((unsigned)aup->db[0].vaddr + (MAX_BUF_SIZE * i)); | |
841 | pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); | |
842 | pDB++; | |
843 | } | |
844 | aup->pDBfree = pDBfree; | |
845 | ||
846 | /* attach a data buffer to each descriptor */ | |
847 | for (i = 0; i < NUM_IR_DESC; i++) { | |
848 | pDB = GetFreeDB(aup); | |
849 | if (!pDB) | |
850 | goto out3; | |
851 | aup->rx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); | |
852 | aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr >> 8) & 0xff); | |
853 | aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr >> 16) & 0xff); | |
854 | aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr >> 24) & 0xff); | |
855 | aup->rx_db_inuse[i] = pDB; | |
856 | } | |
857 | for (i = 0; i < NUM_IR_DESC; i++) { | |
858 | pDB = GetFreeDB(aup); | |
859 | if (!pDB) | |
860 | goto out3; | |
861 | aup->tx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); | |
862 | aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr >> 8) & 0xff); | |
863 | aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr >> 16) & 0xff); | |
864 | aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr >> 24) & 0xff); | |
865 | aup->tx_ring[i]->count_0 = 0; | |
866 | aup->tx_ring[i]->count_1 = 0; | |
867 | aup->tx_ring[i]->flags = 0; | |
868 | aup->tx_db_inuse[i] = pDB; | |
869 | } | |
870 | ||
871 | return 0; | |
872 | ||
873 | out3: | |
874 | dma_free((void *)aup->rx_ring[0], | |
875 | 2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest))); | |
876 | out2: | |
877 | kfree(aup->rx_buff.head); | |
878 | out1: | |
879 | printk(KERN_ERR "au1k_irda_net_init() failed. Returns %d\n", retval); | |
880 | return retval; | |
881 | } | |
882 | ||
45ac936c | 883 | static int au1k_irda_probe(struct platform_device *pdev) |
cd671c16 ML |
884 | { |
885 | struct au1k_private *aup; | |
886 | struct net_device *dev; | |
887 | struct resource *r; | |
9178af9a | 888 | struct clk *c; |
cd671c16 ML |
889 | int err; |
890 | ||
891 | dev = alloc_irdadev(sizeof(struct au1k_private)); | |
892 | if (!dev) | |
893 | return -ENOMEM; | |
894 | ||
895 | aup = netdev_priv(dev); | |
896 | ||
897 | aup->platdata = pdev->dev.platform_data; | |
898 | ||
899 | err = -EINVAL; | |
900 | r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
901 | if (!r) | |
902 | goto out; | |
903 | ||
904 | aup->irq_tx = r->start; | |
905 | ||
906 | r = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | |
907 | if (!r) | |
908 | goto out; | |
909 | ||
910 | aup->irq_rx = r->start; | |
911 | ||
912 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
913 | if (!r) | |
914 | goto out; | |
915 | ||
916 | err = -EBUSY; | |
94d8f2b1 | 917 | aup->ioarea = request_mem_region(r->start, resource_size(r), |
cd671c16 ML |
918 | pdev->name); |
919 | if (!aup->ioarea) | |
920 | goto out; | |
921 | ||
9178af9a ML |
922 | /* bail out early if clock doesn't exist */ |
923 | c = clk_get(NULL, "irda_clk"); | |
924 | if (IS_ERR(c)) { | |
925 | err = PTR_ERR(c); | |
926 | goto out; | |
927 | } | |
928 | clk_put(c); | |
929 | ||
94d8f2b1 | 930 | aup->iobase = ioremap_nocache(r->start, resource_size(r)); |
cd671c16 ML |
931 | if (!aup->iobase) |
932 | goto out2; | |
933 | ||
934 | dev->irq = aup->irq_rx; | |
935 | ||
936 | err = au1k_irda_net_init(dev); | |
937 | if (err) | |
938 | goto out3; | |
939 | err = register_netdev(dev); | |
940 | if (err) | |
941 | goto out4; | |
942 | ||
943 | platform_set_drvdata(pdev, dev); | |
944 | ||
945 | printk(KERN_INFO "IrDA: Registered device %s\n", dev->name); | |
946 | return 0; | |
947 | ||
948 | out4: | |
949 | dma_free((void *)aup->db[0].vaddr, | |
950 | MAX_BUF_SIZE * 2 * NUM_IR_DESC); | |
951 | dma_free((void *)aup->rx_ring[0], | |
952 | 2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest))); | |
953 | kfree(aup->rx_buff.head); | |
954 | out3: | |
955 | iounmap(aup->iobase); | |
956 | out2: | |
957 | release_resource(aup->ioarea); | |
958 | kfree(aup->ioarea); | |
959 | out: | |
960 | free_netdev(dev); | |
961 | return err; | |
962 | } | |
963 | ||
45ac936c | 964 | static int au1k_irda_remove(struct platform_device *pdev) |
cd671c16 ML |
965 | { |
966 | struct net_device *dev = platform_get_drvdata(pdev); | |
967 | struct au1k_private *aup = netdev_priv(dev); | |
968 | ||
969 | unregister_netdev(dev); | |
970 | ||
971 | dma_free((void *)aup->db[0].vaddr, | |
972 | MAX_BUF_SIZE * 2 * NUM_IR_DESC); | |
973 | dma_free((void *)aup->rx_ring[0], | |
974 | 2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest))); | |
975 | kfree(aup->rx_buff.head); | |
976 | ||
977 | iounmap(aup->iobase); | |
978 | release_resource(aup->ioarea); | |
979 | kfree(aup->ioarea); | |
980 | ||
981 | free_netdev(dev); | |
982 | ||
983 | return 0; | |
984 | } | |
985 | ||
986 | static struct platform_driver au1k_irda_driver = { | |
987 | .driver = { | |
988 | .name = "au1000-irda", | |
cd671c16 ML |
989 | }, |
990 | .probe = au1k_irda_probe, | |
45ac936c | 991 | .remove = au1k_irda_remove, |
cd671c16 ML |
992 | }; |
993 | ||
95d158df | 994 | module_platform_driver(au1k_irda_driver); |
cd671c16 | 995 | |
1da177e4 LT |
996 | MODULE_AUTHOR("Pete Popov <ppopov@mvista.com>"); |
997 | MODULE_DESCRIPTION("Au1000 IrDA Device Driver"); |