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irda: Removed all unused timeval variables
[linux-2.6-block.git] / drivers / net / irda / ali-ircc.c
CommitLineData
1da177e4
LT		 1/*********************************************************************
2 *
3 * Filename: ali-ircc.h
4 * Version: 0.5
5 * Description: Driver for the ALI M1535D and M1543C FIR Controller
6 * Status: Experimental.
7 * Author: Benjamin Kong <benjamin_kong@ali.com.tw>
8 * Created at: 2000/10/16 03:46PM
9 * Modified at: 2001/1/3 02:55PM
10 * Modified by: Benjamin Kong <benjamin_kong@ali.com.tw>
11 * Modified at: 2003/11/6 and support for ALi south-bridge chipsets M1563
12 * Modified by: Clear Zhang <clear_zhang@ali.com.tw>
13 *
14 * Copyright (c) 2000 Benjamin Kong <benjamin_kong@ali.com.tw>
15 * All Rights Reserved
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 ********************************************************************/
23
24#include <linux/module.h>
5a0e3ad6 25#include <linux/gfp.h>
1da177e4
LT		 26
27#include <linux/kernel.h>
28#include <linux/types.h>
29#include <linux/skbuff.h>
30#include <linux/netdevice.h>
31#include <linux/ioport.h>
32#include <linux/delay.h>
1da177e4 33#include <linux/init.h>
a6b7a407 34#include <linux/interrupt.h>
1da177e4
LT		 35#include <linux/rtnetlink.h>
36#include <linux/serial_reg.h>
37#include <linux/dma-mapping.h>
898b1d16 38#include <linux/platform_device.h>
1da177e4
LT		 39
40#include <asm/io.h>
41#include <asm/dma.h>
42#include <asm/byteorder.h>
43
1da177e4
LT		 44#include <net/irda/wrapper.h>
45#include <net/irda/irda.h>
46#include <net/irda/irda_device.h>
47
48#include "ali-ircc.h"
49
50#define CHIP_IO_EXTENT 8
51#define BROKEN_DONGLE_ID
52
898b1d16
SO		 53#define ALI_IRCC_DRIVER_NAME "ali-ircc"
54
55/* Power Management */
56static int ali_ircc_suspend(struct platform_device *dev, pm_message_t state);
57static int ali_ircc_resume(struct platform_device *dev);
58
59static struct platform_driver ali_ircc_driver = {
60 .suspend = ali_ircc_suspend,
61 .resume = ali_ircc_resume,
62 .driver = {
63 .name = ALI_IRCC_DRIVER_NAME,
64 },
65};
1da177e4
LT		 66
67/* Module parameters */
68static int qos_mtt_bits = 0x07; /* 1 ms or more */
69
70/* Use BIOS settions by default, but user may supply module parameters */
71static unsigned int io[] = { ~0, ~0, ~0, ~0 };
72static unsigned int irq[] = { 0, 0, 0, 0 };
73static unsigned int dma[] = { 0, 0, 0, 0 };
74
75static int ali_ircc_probe_53(ali_chip_t *chip, chipio_t *info);
76static int ali_ircc_init_43(ali_chip_t *chip, chipio_t *info);
77static int ali_ircc_init_53(ali_chip_t *chip, chipio_t *info);
78
25985edc 79/* These are the currently known ALi south-bridge chipsets, the only one difference
1da177e4
LT		 80 * is that M1543C doesn't support HP HDSL-3600
81 */
82static ali_chip_t chips[] =
83{
84 { "M1543", { 0x3f0, 0x370 }, 0x51, 0x23, 0x20, 0x43, ali_ircc_probe_53, ali_ircc_init_43 },
85 { "M1535", { 0x3f0, 0x370 }, 0x51, 0x23, 0x20, 0x53, ali_ircc_probe_53, ali_ircc_init_53 },
86 { "M1563", { 0x3f0, 0x370 }, 0x51, 0x23, 0x20, 0x63, ali_ircc_probe_53, ali_ircc_init_53 },
87 { NULL }
88};
89
90/* Max 4 instances for now */
91static struct ali_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL };
92
93/* Dongle Types */
94static char *dongle_types[] = {
95 "TFDS6000",
96 "HP HSDL-3600",
97 "HP HSDL-1100",
98 "No dongle connected",
99};
100
101/* Some prototypes */
102static int ali_ircc_open(int i, chipio_t *info);
103
104static int ali_ircc_close(struct ali_ircc_cb *self);
105
106static int ali_ircc_setup(chipio_t *info);
107static int ali_ircc_is_receiving(struct ali_ircc_cb *self);
108static int ali_ircc_net_open(struct net_device *dev);
109static int ali_ircc_net_close(struct net_device *dev);
110static int ali_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 111static void ali_ircc_change_speed(struct ali_ircc_cb *self, __u32 baud);
1da177e4
LT		 112
113/* SIR function */
6518bbb8
SH		 114static netdev_tx_t ali_ircc_sir_hard_xmit(struct sk_buff *skb,
115 struct net_device *dev);
1da177e4
LT		 116static irqreturn_t ali_ircc_sir_interrupt(struct ali_ircc_cb *self);
117static void ali_ircc_sir_receive(struct ali_ircc_cb *self);
118static void ali_ircc_sir_write_wakeup(struct ali_ircc_cb *self);
119static int ali_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
120static void ali_ircc_sir_change_speed(struct ali_ircc_cb *priv, __u32 speed);
121
122/* FIR function */
6518bbb8
SH		 123static netdev_tx_t ali_ircc_fir_hard_xmit(struct sk_buff *skb,
124 struct net_device *dev);
1da177e4
LT		 125static void ali_ircc_fir_change_speed(struct ali_ircc_cb *priv, __u32 speed);
126static irqreturn_t ali_ircc_fir_interrupt(struct ali_ircc_cb *self);
127static int ali_ircc_dma_receive(struct ali_ircc_cb *self);
128static int ali_ircc_dma_receive_complete(struct ali_ircc_cb *self);
129static int ali_ircc_dma_xmit_complete(struct ali_ircc_cb *self);
130static void ali_ircc_dma_xmit(struct ali_ircc_cb *self);
131
132/* My Function */
133static int ali_ircc_read_dongle_id (int i, chipio_t *info);
134static void ali_ircc_change_dongle_speed(struct ali_ircc_cb *priv, int speed);
135
136/* ALi chip function */
137static void SIR2FIR(int iobase);
138static void FIR2SIR(int iobase);
139static void SetCOMInterrupts(struct ali_ircc_cb *self , unsigned char enable);
140
141/*
142 * Function ali_ircc_init ()
143 *
144 * Initialize chip. Find out whay kinds of chips we are dealing with
0b1974de 145 * and their configuration registers address
1da177e4
LT		 146 */
147static int __init ali_ircc_init(void)
148{
149 ali_chip_t *chip;
150 chipio_t info;
9c6c6795 151 int ret;
1da177e4
LT		 152 int cfg, cfg_base;
153 int reg, revision;
154 int i = 0;
155
898b1d16
SO		 156 ret = platform_driver_register(&ali_ircc_driver);
157 if (ret) {
6c91023d
JP		 158 net_err_ratelimited("%s, Can't register driver!\n",
159 ALI_IRCC_DRIVER_NAME);
898b1d16
SO		 160 return ret;
161 }
162
9c6c6795 163 ret = -ENODEV;
1da177e4
LT		 164
165 /* Probe for all the ALi chipsets we know about */
166 for (chip= chips; chip->name; chip++, i++)
167 {
955a9d20 168 pr_debug("%s(), Probing for %s ...\n", __func__, chip->name);
1da177e4
LT		 169
170 /* Try all config registers for this chip */
171 for (cfg=0; cfg<2; cfg++)
172 {
173 cfg_base = chip->cfg[cfg];
174 if (!cfg_base)
175 continue;
176
177 memset(&info, 0, sizeof(chipio_t));
178 info.cfg_base = cfg_base;
179 info.fir_base = io[i];
180 info.dma = dma[i];
181 info.irq = irq[i];
182
183
184 /* Enter Configuration */
185 outb(chip->entr1, cfg_base);
186 outb(chip->entr2, cfg_base);
187
188 /* Select Logical Device 5 Registers (UART2) */
189 outb(0x07, cfg_base);
190 outb(0x05, cfg_base+1);
191
192 /* Read Chip Identification Register */
193 outb(chip->cid_index, cfg_base);
194 reg = inb(cfg_base+1);
195
196 if (reg == chip->cid_value)
197 {
955a9d20
JP		 198 pr_debug("%s(), Chip found at 0x%03x\n",
199 __func__, cfg_base);
1da177e4
LT		 200
201 outb(0x1F, cfg_base);
202 revision = inb(cfg_base+1);
955a9d20
JP		 203 pr_debug("%s(), Found %s chip, revision=%d\n",
204 __func__, chip->name, revision);
1da177e4
LT		 205
206 /*
207 * If the user supplies the base address, then
208 * we init the chip, if not we probe the values
209 * set by the BIOS
210 */
211 if (io[i] < 2000)
212 {
213 chip->init(chip, &info);
214 }
215 else
216 {
217 chip->probe(chip, &info);
218 }
219
220 if (ali_ircc_open(i, &info) == 0)
221 ret = 0;
222 i++;
223 }
224 else
225 {
955a9d20
JP		 226 pr_debug("%s(), No %s chip at 0x%03x\n",
227 __func__, chip->name, cfg_base);
1da177e4
LT		 228 }
229 /* Exit configuration */
230 outb(0xbb, cfg_base);
231 }
232 }
233
898b1d16
SO		 234 if (ret)
235 platform_driver_unregister(&ali_ircc_driver);
236
1da177e4
LT		 237 return ret;
238}
239
240/*
241 * Function ali_ircc_cleanup ()
242 *
243 * Close all configured chips
244 *
245 */
246static void __exit ali_ircc_cleanup(void)
247{
248 int i;
249
9c3bd683 250 for (i=0; i < ARRAY_SIZE(dev_self); i++) {
1da177e4
LT		 251 if (dev_self[i])
252 ali_ircc_close(dev_self[i]);
253 }
254
898b1d16
SO		 255 platform_driver_unregister(&ali_ircc_driver);
256
1da177e4
LT		 257}
258
2d44a222
SH		 259static const struct net_device_ops ali_ircc_sir_ops = {
260 .ndo_open = ali_ircc_net_open,
261 .ndo_stop = ali_ircc_net_close,
262 .ndo_start_xmit = ali_ircc_sir_hard_xmit,
263 .ndo_do_ioctl = ali_ircc_net_ioctl,
264};
265
266static const struct net_device_ops ali_ircc_fir_ops = {
267 .ndo_open = ali_ircc_net_open,
268 .ndo_stop = ali_ircc_net_close,
269 .ndo_start_xmit = ali_ircc_fir_hard_xmit,
270 .ndo_do_ioctl = ali_ircc_net_ioctl,
271};
272
1da177e4
LT		 273/*
274 * Function ali_ircc_open (int i, chipio_t *inf)
275 *
276 * Open driver instance
277 *
278 */
279static int ali_ircc_open(int i, chipio_t *info)
280{
281 struct net_device *dev;
282 struct ali_ircc_cb *self;
1da177e4
LT		 283 int dongle_id;
284 int err;
285
9c3bd683 286 if (i >= ARRAY_SIZE(dev_self)) {
6c91023d
JP		 287 net_err_ratelimited("%s(), maximum number of supported chips reached!\n",
288 __func__);
9c3bd683
BH		 289 return -ENOMEM;
290 }
1da177e4
LT		 291
292 /* Set FIR FIFO and DMA Threshold */
293 if ((ali_ircc_setup(info)) == -1)
294 return -1;
295
296 dev = alloc_irdadev(sizeof(*self));
297 if (dev == NULL) {
6c91023d
JP		 298 net_err_ratelimited("%s(), can't allocate memory for control block!\n",
299 __func__);
1da177e4
LT		 300 return -ENOMEM;
301 }
302
4cf1653a 303 self = netdev_priv(dev);
1da177e4
LT		 304 self->netdev = dev;
305 spin_lock_init(&self->lock);
306
307 /* Need to store self somewhere */
308 dev_self[i] = self;
309 self->index = i;
310
311 /* Initialize IO */
312 self->io.cfg_base = info->cfg_base; /* In ali_ircc_probe_53 assign */
313 self->io.fir_base = info->fir_base; /* info->sir_base = info->fir_base */
314 self->io.sir_base = info->sir_base; /* ALi SIR and FIR use the same address */
315 self->io.irq = info->irq;
316 self->io.fir_ext = CHIP_IO_EXTENT;
317 self->io.dma = info->dma;
318 self->io.fifo_size = 16; /* SIR: 16, FIR: 32 Benjamin 2000/11/1 */
319
320 /* Reserve the ioports that we need */
898b1d16
SO		 321 if (!request_region(self->io.fir_base, self->io.fir_ext,
322 ALI_IRCC_DRIVER_NAME)) {
6c91023d
JP		 323 net_warn_ratelimited("%s(), can't get iobase of 0x%03x\n",
324 __func__, self->io.fir_base);
1da177e4
LT		 325 err = -ENODEV;
326 goto err_out1;
327 }
328
329 /* Initialize QoS for this device */
330 irda_init_max_qos_capabilies(&self->qos);
331
332 /* The only value we must override it the baudrate */
333 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
334 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8); // benjamin 2000/11/8 05:27PM
335
336 self->qos.min_turn_time.bits = qos_mtt_bits;
337
338 irda_qos_bits_to_value(&self->qos);
339
340 /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
341 self->rx_buff.truesize = 14384;
342 self->tx_buff.truesize = 14384;
343
344 /* Allocate memory if needed */
345 self->rx_buff.head =
ede23fa8
JP		 346 dma_zalloc_coherent(NULL, self->rx_buff.truesize,
347 &self->rx_buff_dma, GFP_KERNEL);
1da177e4
LT		 348 if (self->rx_buff.head == NULL) {
349 err = -ENOMEM;
350 goto err_out2;
351 }
1da177e4
LT		 352
353 self->tx_buff.head =
ede23fa8
JP		 354 dma_zalloc_coherent(NULL, self->tx_buff.truesize,
355 &self->tx_buff_dma, GFP_KERNEL);
1da177e4
LT		 356 if (self->tx_buff.head == NULL) {
357 err = -ENOMEM;
358 goto err_out3;
359 }
1da177e4
LT		 360
361 self->rx_buff.in_frame = FALSE;
362 self->rx_buff.state = OUTSIDE_FRAME;
363 self->tx_buff.data = self->tx_buff.head;
364 self->rx_buff.data = self->rx_buff.head;
365
366 /* Reset Tx queue info */
367 self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
368 self->tx_fifo.tail = self->tx_buff.head;
369
1da177e4 370 /* Override the network functions we need to use */
2d44a222 371 dev->netdev_ops = &ali_ircc_sir_ops;
1da177e4
LT		 372
373 err = register_netdev(dev);
374 if (err) {
6c91023d
JP		 375 net_err_ratelimited("%s(), register_netdev() failed!\n",
376 __func__);
1da177e4
LT		 377 goto err_out4;
378 }
6c91023d 379 net_info_ratelimited("IrDA: Registered device %s\n", dev->name);
1da177e4
LT		 380
381 /* Check dongle id */
382 dongle_id = ali_ircc_read_dongle_id(i, info);
6c91023d
JP		 383 net_info_ratelimited("%s(), %s, Found dongle: %s\n",
384 __func__, ALI_IRCC_DRIVER_NAME,
385 dongle_types[dongle_id]);
1da177e4
LT		 386
387 self->io.dongle_id = dongle_id;
1da177e4 388
1da177e4
LT		 389
390 return 0;
391
392 err_out4:
393 dma_free_coherent(NULL, self->tx_buff.truesize,
394 self->tx_buff.head, self->tx_buff_dma);
395 err_out3:
396 dma_free_coherent(NULL, self->rx_buff.truesize,
397 self->rx_buff.head, self->rx_buff_dma);
398 err_out2:
399 release_region(self->io.fir_base, self->io.fir_ext);
400 err_out1:
401 dev_self[i] = NULL;
402 free_netdev(dev);
403 return err;
404}
405
406
407/*
408 * Function ali_ircc_close (self)
409 *
410 * Close driver instance
411 *
412 */
413static int __exit ali_ircc_close(struct ali_ircc_cb *self)
414{
415 int iobase;
416
1da177e4
LT		 417 IRDA_ASSERT(self != NULL, return -1;);
418
419 iobase = self->io.fir_base;
420
421 /* Remove netdevice */
422 unregister_netdev(self->netdev);
423
424 /* Release the PORT that this driver is using */
955a9d20 425 pr_debug("%s(), Releasing Region %03x\n", __func__, self->io.fir_base);
1da177e4
LT		 426 release_region(self->io.fir_base, self->io.fir_ext);
427
428 if (self->tx_buff.head)
429 dma_free_coherent(NULL, self->tx_buff.truesize,
430 self->tx_buff.head, self->tx_buff_dma);
431
432 if (self->rx_buff.head)
433 dma_free_coherent(NULL, self->rx_buff.truesize,
434 self->rx_buff.head, self->rx_buff_dma);
435
436 dev_self[self->index] = NULL;
437 free_netdev(self->netdev);
438
1da177e4
LT		 439
440 return 0;
441}
442
443/*
444 * Function ali_ircc_init_43 (chip, info)
445 *
446 * Initialize the ALi M1543 chip.
447 */
448static int ali_ircc_init_43(ali_chip_t *chip, chipio_t *info)
449{
450 /* All controller information like I/O address, DMA channel, IRQ
451 * are set by BIOS
452 */
453
454 return 0;
455}
456
457/*
458 * Function ali_ircc_init_53 (chip, info)
459 *
460 * Initialize the ALi M1535 chip.
461 */
462static int ali_ircc_init_53(ali_chip_t *chip, chipio_t *info)
463{
464 /* All controller information like I/O address, DMA channel, IRQ
465 * are set by BIOS
466 */
467
468 return 0;
469}
470
471/*
472 * Function ali_ircc_probe_53 (chip, info)
473 *
474 * Probes for the ALi M1535D or M1535
475 */
476static int ali_ircc_probe_53(ali_chip_t *chip, chipio_t *info)
477{
478 int cfg_base = info->cfg_base;
479 int hi, low, reg;
480
1da177e4
LT		 481
482 /* Enter Configuration */
483 outb(chip->entr1, cfg_base);
484 outb(chip->entr2, cfg_base);
485
486 /* Select Logical Device 5 Registers (UART2) */
487 outb(0x07, cfg_base);
488 outb(0x05, cfg_base+1);
489
490 /* Read address control register */
491 outb(0x60, cfg_base);
492 hi = inb(cfg_base+1);
493 outb(0x61, cfg_base);
494 low = inb(cfg_base+1);
495 info->fir_base = (hi<<8) + low;
496
497 info->sir_base = info->fir_base;
498
955a9d20 499 pr_debug("%s(), probing fir_base=0x%03x\n", __func__, info->fir_base);
1da177e4
LT		 500
501 /* Read IRQ control register */
502 outb(0x70, cfg_base);
503 reg = inb(cfg_base+1);
504 info->irq = reg & 0x0f;
955a9d20 505 pr_debug("%s(), probing irq=%d\n", __func__, info->irq);
1da177e4
LT		 506
507 /* Read DMA channel */
508 outb(0x74, cfg_base);
509 reg = inb(cfg_base+1);
510 info->dma = reg & 0x07;
511
512 if(info->dma == 0x04)
6c91023d
JP		 513 net_warn_ratelimited("%s(), No DMA channel assigned !\n",
514 __func__);
1da177e4 515 else
955a9d20 516 pr_debug("%s(), probing dma=%d\n", __func__, info->dma);
1da177e4
LT		 517
518 /* Read Enabled Status */
519 outb(0x30, cfg_base);
520 reg = inb(cfg_base+1);
521 info->enabled = (reg & 0x80) && (reg & 0x01);
955a9d20 522 pr_debug("%s(), probing enabled=%d\n", __func__, info->enabled);
1da177e4
LT		 523
524 /* Read Power Status */
525 outb(0x22, cfg_base);
526 reg = inb(cfg_base+1);
527 info->suspended = (reg & 0x20);
955a9d20 528 pr_debug("%s(), probing suspended=%d\n", __func__, info->suspended);
1da177e4
LT		 529
530 /* Exit configuration */
531 outb(0xbb, cfg_base);
532
1da177e4
LT		 533
534 return 0;
535}
536
537/*
538 * Function ali_ircc_setup (info)
539 *
540 * Set FIR FIFO and DMA Threshold
541 * Returns non-negative on success.
542 *
543 */
544static int ali_ircc_setup(chipio_t *info)
545{
546 unsigned char tmp;
547 int version;
548 int iobase = info->fir_base;
549
1da177e4
LT		 550
551 /* Locking comments :
552 * Most operations here need to be protected. We are called before
553 * the device instance is created in ali_ircc_open(), therefore
554 * nobody can bother us - Jean II */
555
556 /* Switch to FIR space */
557 SIR2FIR(iobase);
558
559 /* Master Reset */
560 outb(0x40, iobase+FIR_MCR); // benjamin 2000/11/30 11:45AM
561
562 /* Read FIR ID Version Register */
563 switch_bank(iobase, BANK3);
564 version = inb(iobase+FIR_ID_VR);
565
566 /* Should be 0x00 in the M1535/M1535D */
567 if(version != 0x00)
568 {
6c91023d
JP		 569 net_err_ratelimited("%s, Wrong chip version %02x\n",
570 ALI_IRCC_DRIVER_NAME, version);
1da177e4
LT		 571 return -1;
572 }
573
1da177e4
LT		 574 /* Set FIR FIFO Threshold Register */
575 switch_bank(iobase, BANK1);
576 outb(RX_FIFO_Threshold, iobase+FIR_FIFO_TR);
577
578 /* Set FIR DMA Threshold Register */
579 outb(RX_DMA_Threshold, iobase+FIR_DMA_TR);
580
581 /* CRC enable */
582 switch_bank(iobase, BANK2);
583 outb(inb(iobase+FIR_IRDA_CR) | IRDA_CR_CRC, iobase+FIR_IRDA_CR);
584
585 /* NDIS driver set TX Length here BANK2 Alias 3, Alias4*/
586
587 /* Switch to Bank 0 */
588 switch_bank(iobase, BANK0);
589
590 tmp = inb(iobase+FIR_LCR_B);
591 tmp &=~0x20; // disable SIP
592 tmp |= 0x80; // these two steps make RX mode
593 tmp &= 0xbf;
594 outb(tmp, iobase+FIR_LCR_B);
595
596 /* Disable Interrupt */
597 outb(0x00, iobase+FIR_IER);
598
599
600 /* Switch to SIR space */
601 FIR2SIR(iobase);
602
6c91023d
JP		 603 net_info_ratelimited("%s, driver loaded (Benjamin Kong)\n",
604 ALI_IRCC_DRIVER_NAME);
1da177e4
LT		 605
606 /* Enable receive interrupts */
607 // outb(UART_IER_RDI, iobase+UART_IER); //benjamin 2000/11/23 01:25PM
608 // Turn on the interrupts in ali_ircc_net_open
609
1da177e4
LT		 610
611 return 0;
612}
613
614/*
615 * Function ali_ircc_read_dongle_id (int index, info)
616 *
3f79410c 617 * Try to read dongle identification. This procedure needs to be executed
1da177e4
LT		 618 * once after power-on/reset. It also needs to be used whenever you suspect
619 * that the user may have plugged/unplugged the IrDA Dongle.
620 */
621static int ali_ircc_read_dongle_id (int i, chipio_t *info)
622{
623 int dongle_id, reg;
624 int cfg_base = info->cfg_base;
625
1da177e4
LT		 626
627 /* Enter Configuration */
628 outb(chips[i].entr1, cfg_base);
629 outb(chips[i].entr2, cfg_base);
630
631 /* Select Logical Device 5 Registers (UART2) */
632 outb(0x07, cfg_base);
633 outb(0x05, cfg_base+1);
634
635 /* Read Dongle ID */
636 outb(0xf0, cfg_base);
637 reg = inb(cfg_base+1);
638 dongle_id = ((reg>>6)&0x02) | ((reg>>5)&0x01);
955a9d20
JP		 639 pr_debug("%s(), probing dongle_id=%d, dongle_types=%s\n",
640 __func__, dongle_id, dongle_types[dongle_id]);
1da177e4
LT		 641
642 /* Exit configuration */
643 outb(0xbb, cfg_base);
644
1da177e4
LT		 645
646 return dongle_id;
647}
648
649/*
650 * Function ali_ircc_interrupt (irq, dev_id, regs)
651 *
652 * An interrupt from the chip has arrived. Time to do some work
653 *
654 */
7d12e780 655static irqreturn_t ali_ircc_interrupt(int irq, void *dev_id)
1da177e4 656{
c31f28e7 657 struct net_device *dev = dev_id;
1da177e4
LT		 658 struct ali_ircc_cb *self;
659 int ret;
660
1da177e4 661
4cf1653a 662 self = netdev_priv(dev);
1da177e4
LT		 663
664 spin_lock(&self->lock);
665
666 /* Dispatch interrupt handler for the current speed */
667 if (self->io.speed > 115200)
668 ret = ali_ircc_fir_interrupt(self);
669 else
670 ret = ali_ircc_sir_interrupt(self);
671
672 spin_unlock(&self->lock);
673
1da177e4
LT		 674 return ret;
675}
676/*
677 * Function ali_ircc_fir_interrupt(irq, struct ali_ircc_cb *self)
678 *
679 * Handle MIR/FIR interrupt
680 *
681 */
682static irqreturn_t ali_ircc_fir_interrupt(struct ali_ircc_cb *self)
683{
684 __u8 eir, OldMessageCount;
685 int iobase, tmp;
686
1da177e4
LT		 687
688 iobase = self->io.fir_base;
689
690 switch_bank(iobase, BANK0);
691 self->InterruptID = inb(iobase+FIR_IIR);
692 self->BusStatus = inb(iobase+FIR_BSR);
693
694 OldMessageCount = (self->LineStatus + 1) & 0x07;
695 self->LineStatus = inb(iobase+FIR_LSR);
696 //self->ier = inb(iobase+FIR_IER); 2000/12/1 04:32PM
697 eir = self->InterruptID & self->ier; /* Mask out the interesting ones */
698
955a9d20
JP		 699 pr_debug("%s(), self->InterruptID = %x\n", __func__, self->InterruptID);
700 pr_debug("%s(), self->LineStatus = %x\n", __func__, self->LineStatus);
701 pr_debug("%s(), self->ier = %x\n", __func__, self->ier);
702 pr_debug("%s(), eir = %x\n", __func__, eir);
1da177e4
LT		 703
704 /* Disable interrupts */
705 SetCOMInterrupts(self, FALSE);
706
707 /* Tx or Rx Interrupt */
708
709 if (eir & IIR_EOM)
710 {
711 if (self->io.direction == IO_XMIT) /* TX */
712 {
955a9d20
JP		 713 pr_debug("%s(), ******* IIR_EOM (Tx) *******\n",
714 __func__);
1da177e4
LT		 715
716 if(ali_ircc_dma_xmit_complete(self))
717 {
718 if (irda_device_txqueue_empty(self->netdev))
719 {
720 /* Prepare for receive */
721 ali_ircc_dma_receive(self);
722 self->ier = IER_EOM;
723 }
724 }
725 else
726 {
727 self->ier = IER_EOM;
728 }
729
730 }
731 else /* RX */
732 {
955a9d20
JP		 733 pr_debug("%s(), ******* IIR_EOM (Rx) *******\n",
734 __func__);
1da177e4
LT		 735
736 if(OldMessageCount > ((self->LineStatus+1) & 0x07))
737 {
738 self->rcvFramesOverflow = TRUE;
955a9d20
JP		 739 pr_debug("%s(), ******* self->rcvFramesOverflow = TRUE ********\n",
740 __func__);
1da177e4
LT		 741 }
742
743 if (ali_ircc_dma_receive_complete(self))
744 {
955a9d20
JP		 745 pr_debug("%s(), ******* receive complete ********\n",
746 __func__);
1da177e4
LT		 747
748 self->ier = IER_EOM;
749 }
750 else
751 {
955a9d20
JP		 752 pr_debug("%s(), ******* Not receive complete ********\n",
753 __func__);
1da177e4
LT		 754
755 self->ier = IER_EOM | IER_TIMER;
756 }
757
758 }
759 }
760 /* Timer Interrupt */
761 else if (eir & IIR_TIMER)
762 {
763 if(OldMessageCount > ((self->LineStatus+1) & 0x07))
764 {
765 self->rcvFramesOverflow = TRUE;
955a9d20
JP		 766 pr_debug("%s(), ******* self->rcvFramesOverflow = TRUE *******\n",
767 __func__);
1da177e4
LT		 768 }
769 /* Disable Timer */
770 switch_bank(iobase, BANK1);
771 tmp = inb(iobase+FIR_CR);
772 outb( tmp& ~CR_TIMER_EN, iobase+FIR_CR);
773
774 /* Check if this is a Tx timer interrupt */
775 if (self->io.direction == IO_XMIT)
776 {
777 ali_ircc_dma_xmit(self);
778
779 /* Interrupt on EOM */
780 self->ier = IER_EOM;
781
782 }
783 else /* Rx */
784 {
785 if(ali_ircc_dma_receive_complete(self))
786 {
787 self->ier = IER_EOM;
788 }
789 else
790 {
791 self->ier = IER_EOM | IER_TIMER;
792 }
793 }
794 }
795
796 /* Restore Interrupt */
797 SetCOMInterrupts(self, TRUE);
798
1da177e4
LT		 799 return IRQ_RETVAL(eir);
800}
801
802/*
803 * Function ali_ircc_sir_interrupt (irq, self, eir)
804 *
805 * Handle SIR interrupt
806 *
807 */
808static irqreturn_t ali_ircc_sir_interrupt(struct ali_ircc_cb *self)
809{
810 int iobase;
811 int iir, lsr;
812
1da177e4
LT		 813
814 iobase = self->io.sir_base;
815
816 iir = inb(iobase+UART_IIR) & UART_IIR_ID;
817 if (iir) {
818 /* Clear interrupt */
819 lsr = inb(iobase+UART_LSR);
820
955a9d20
JP		 821 pr_debug("%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
822 __func__, iir, lsr, iobase);
1da177e4
LT		 823
824 switch (iir)
825 {
826 case UART_IIR_RLSI:
955a9d20 827 pr_debug("%s(), RLSI\n", __func__);
1da177e4
LT		 828 break;
829 case UART_IIR_RDI:
830 /* Receive interrupt */
831 ali_ircc_sir_receive(self);
832 break;
833 case UART_IIR_THRI:
834 if (lsr & UART_LSR_THRE)
835 {
836 /* Transmitter ready for data */
837 ali_ircc_sir_write_wakeup(self);
838 }
839 break;
840 default:
955a9d20
JP		 841 pr_debug("%s(), unhandled IIR=%#x\n",
842 __func__, iir);
1da177e4
LT		 843 break;
844 }
845
846 }
847
848
1da177e4
LT		 849 return IRQ_RETVAL(iir);
850}
851
852
853/*
854 * Function ali_ircc_sir_receive (self)
855 *
856 * Receive one frame from the infrared port
857 *
858 */
859static void ali_ircc_sir_receive(struct ali_ircc_cb *self)
860{
861 int boguscount = 0;
862 int iobase;
863
1da177e4
LT		 864 IRDA_ASSERT(self != NULL, return;);
865
866 iobase = self->io.sir_base;
867
868 /*
869 * Receive all characters in Rx FIFO, unwrap and unstuff them.
870 * async_unwrap_char will deliver all found frames
871 */
872 do {
af049081 873 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
1da177e4
LT		 874 inb(iobase+UART_RX));
875
876 /* Make sure we don't stay here too long */
877 if (boguscount++ > 32) {
955a9d20 878 pr_debug("%s(), breaking!\n", __func__);
1da177e4
LT		 879 break;
880 }
881 } while (inb(iobase+UART_LSR) & UART_LSR_DR);
882
1da177e4
LT		 883}
884
885/*
886 * Function ali_ircc_sir_write_wakeup (tty)
887 *
888 * Called by the driver when there's room for more data. If we have
889 * more packets to send, we send them here.
890 *
891 */
892static void ali_ircc_sir_write_wakeup(struct ali_ircc_cb *self)
893{
894 int actual = 0;
895 int iobase;
896
897 IRDA_ASSERT(self != NULL, return;);
898
1da177e4
LT		 899
900 iobase = self->io.sir_base;
901
902 /* Finished with frame? */
903 if (self->tx_buff.len > 0)
904 {
905 /* Write data left in transmit buffer */
906 actual = ali_ircc_sir_write(iobase, self->io.fifo_size,
907 self->tx_buff.data, self->tx_buff.len);
908 self->tx_buff.data += actual;
909 self->tx_buff.len -= actual;
910 }
911 else
912 {
913 if (self->new_speed)
914 {
915 /* We must wait until all data are gone */
916 while(!(inb(iobase+UART_LSR) & UART_LSR_TEMT))
955a9d20 917 pr_debug("%s(), UART_LSR_THRE\n", __func__);
1da177e4 918
955a9d20
JP		 919 pr_debug("%s(), Changing speed! self->new_speed = %d\n",
920 __func__, self->new_speed);
1da177e4
LT		 921 ali_ircc_change_speed(self, self->new_speed);
922 self->new_speed = 0;
923
924 // benjamin 2000/11/10 06:32PM
925 if (self->io.speed > 115200)
926 {
955a9d20
JP		 927 pr_debug("%s(), ali_ircc_change_speed from UART_LSR_TEMT\n",
928 __func__);
1da177e4
LT		 929
930 self->ier = IER_EOM;
931 // SetCOMInterrupts(self, TRUE);
932 return;
933 }
934 }
935 else
936 {
937 netif_wake_queue(self->netdev);
938 }
939
af049081 940 self->netdev->stats.tx_packets++;
1da177e4
LT		 941
942 /* Turn on receive interrupts */
943 outb(UART_IER_RDI, iobase+UART_IER);
944 }
945
1da177e4
LT		 946}
947
948static void ali_ircc_change_speed(struct ali_ircc_cb *self, __u32 baud)
949{
950 struct net_device *dev = self->netdev;
951 int iobase;
952
1da177e4 953
955a9d20 954 pr_debug("%s(), setting speed = %d\n", __func__, baud);
1da177e4
LT		 955
956 /* This function *must* be called with irq off and spin-lock.
957 * - Jean II */
958
959 iobase = self->io.fir_base;
960
961 SetCOMInterrupts(self, FALSE); // 2000/11/24 11:43AM
962
963 /* Go to MIR, FIR Speed */
964 if (baud > 115200)
965 {
966
967
968 ali_ircc_fir_change_speed(self, baud);
969
970 /* Install FIR xmit handler*/
2d44a222 971 dev->netdev_ops = &ali_ircc_fir_ops;
1da177e4
LT		 972
973 /* Enable Interuupt */
974 self->ier = IER_EOM; // benjamin 2000/11/20 07:24PM
975
d82603c6 976 /* Be ready for incoming frames */
1da177e4
LT		 977 ali_ircc_dma_receive(self); // benajmin 2000/11/8 07:46PM not complete
978 }
979 /* Go to SIR Speed */
980 else
981 {
982 ali_ircc_sir_change_speed(self, baud);
983
984 /* Install SIR xmit handler*/
2d44a222 985 dev->netdev_ops = &ali_ircc_sir_ops;
1da177e4
LT		 986 }
987
988
989 SetCOMInterrupts(self, TRUE); // 2000/11/24 11:43AM
990
991 netif_wake_queue(self->netdev);
992
1da177e4
LT		 993}
994
995static void ali_ircc_fir_change_speed(struct ali_ircc_cb *priv, __u32 baud)
996{
997
998 int iobase;
c2fd03a0 999 struct ali_ircc_cb *self = priv;
1da177e4
LT		 1000 struct net_device *dev;
1001
1da177e4
LT		 1002
1003 IRDA_ASSERT(self != NULL, return;);
1004
1005 dev = self->netdev;
1006 iobase = self->io.fir_base;
1007
955a9d20
JP		 1008 pr_debug("%s(), self->io.speed = %d, change to speed = %d\n",
1009 __func__, self->io.speed, baud);
1da177e4
LT		 1010
1011 /* Come from SIR speed */
1012 if(self->io.speed <=115200)
1013 {
1014 SIR2FIR(iobase);
1015 }
1016
1017 /* Update accounting for new speed */
1018 self->io.speed = baud;
1019
1020 // Set Dongle Speed mode
1021 ali_ircc_change_dongle_speed(self, baud);
1022
1da177e4
LT		 1023}
1024
1025/*
1026 * Function ali_sir_change_speed (self, speed)
1027 *
1028 * Set speed of IrDA port to specified baudrate
1029 *
1030 */
1031static void ali_ircc_sir_change_speed(struct ali_ircc_cb *priv, __u32 speed)
1032{
c2fd03a0 1033 struct ali_ircc_cb *self = priv;
1da177e4
LT		 1034 unsigned long flags;
1035 int iobase;
1036 int fcr; /* FIFO control reg */
1037 int lcr; /* Line control reg */
1038 int divisor;
1039
1da177e4 1040
955a9d20 1041 pr_debug("%s(), Setting speed to: %d\n", __func__, speed);
1da177e4
LT		 1042
1043 IRDA_ASSERT(self != NULL, return;);
1044
1045 iobase = self->io.sir_base;
1046
1047 /* Come from MIR or FIR speed */
1048 if(self->io.speed >115200)
1049 {
1050 // Set Dongle Speed mode first
1051 ali_ircc_change_dongle_speed(self, speed);
1052
1053 FIR2SIR(iobase);
1054 }
1055
1056 // Clear Line and Auxiluary status registers 2000/11/24 11:47AM
1057
1058 inb(iobase+UART_LSR);
1059 inb(iobase+UART_SCR);
1060
1061 /* Update accounting for new speed */
1062 self->io.speed = speed;
1063
1064 spin_lock_irqsave(&self->lock, flags);
1065
1066 divisor = 115200/speed;
1067
1068 fcr = UART_FCR_ENABLE_FIFO;
1069
1070 /*
1071 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1072 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1073 * about this timeout since it will always be fast enough.
1074 */
1075 if (self->io.speed < 38400)
1076 fcr |= UART_FCR_TRIGGER_1;
1077 else
1078 fcr |= UART_FCR_TRIGGER_14;
1079
1080 /* IrDA ports use 8N1 */
1081 lcr = UART_LCR_WLEN8;
1082
1083 outb(UART_LCR_DLAB | lcr, iobase+UART_LCR); /* Set DLAB */
1084 outb(divisor & 0xff, iobase+UART_DLL); /* Set speed */
1085 outb(divisor >> 8, iobase+UART_DLM);
1086 outb(lcr, iobase+UART_LCR); /* Set 8N1 */
1087 outb(fcr, iobase+UART_FCR); /* Enable FIFO's */
1088
25985edc 1089 /* without this, the connection will be broken after come back from FIR speed,
1da177e4
LT		 1090 but with this, the SIR connection is harder to established */
1091 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), iobase+UART_MCR);
1092
1093 spin_unlock_irqrestore(&self->lock, flags);
1094
1da177e4
LT		 1095}
1096
1097static void ali_ircc_change_dongle_speed(struct ali_ircc_cb *priv, int speed)
1098{
1099
c2fd03a0 1100 struct ali_ircc_cb *self = priv;
1da177e4
LT		 1101 int iobase,dongle_id;
1102 int tmp = 0;
1103
1da177e4
LT		 1104
1105 iobase = self->io.fir_base; /* or iobase = self->io.sir_base; */
1106 dongle_id = self->io.dongle_id;
1107
1108 /* We are already locked, no need to do it again */
1109
955a9d20
JP		 1110 pr_debug("%s(), Set Speed for %s , Speed = %d\n",
1111 __func__, dongle_types[dongle_id], speed);
1da177e4
LT		 1112
1113 switch_bank(iobase, BANK2);
1114 tmp = inb(iobase+FIR_IRDA_CR);
1115
1116 /* IBM type dongle */
1117 if(dongle_id == 0)
1118 {
1119 if(speed == 4000000)
1120 {
1121 // __ __
1122 // SD/MODE __| |__ __
1123 // __ __
1124 // IRTX __ __| |__
1125 // T1 T2 T3 T4 T5
1126
1127 tmp &= ~IRDA_CR_HDLC; // HDLC=0
1128 tmp |= IRDA_CR_CRC; // CRC=1
1129
1130 switch_bank(iobase, BANK2);
1131 outb(tmp, iobase+FIR_IRDA_CR);
1132
1133 // T1 -> SD/MODE:0 IRTX:0
1134 tmp &= ~0x09;
1135 tmp |= 0x02;
1136 outb(tmp, iobase+FIR_IRDA_CR);
1137 udelay(2);
1138
1139 // T2 -> SD/MODE:1 IRTX:0
1140 tmp &= ~0x01;
1141 tmp |= 0x0a;
1142 outb(tmp, iobase+FIR_IRDA_CR);
1143 udelay(2);
1144
1145 // T3 -> SD/MODE:1 IRTX:1
1146 tmp |= 0x0b;
1147 outb(tmp, iobase+FIR_IRDA_CR);
1148 udelay(2);
1149
1150 // T4 -> SD/MODE:0 IRTX:1
1151 tmp &= ~0x08;
1152 tmp |= 0x03;
1153 outb(tmp, iobase+FIR_IRDA_CR);
1154 udelay(2);
1155
1156 // T5 -> SD/MODE:0 IRTX:0
1157 tmp &= ~0x09;
1158 tmp |= 0x02;
1159 outb(tmp, iobase+FIR_IRDA_CR);
1160 udelay(2);
1161
1162 // reset -> Normal TX output Signal
1163 outb(tmp & ~0x02, iobase+FIR_IRDA_CR);
1164 }
1165 else /* speed <=1152000 */
1166 {
1167 // __
1168 // SD/MODE __| |__
1169 //
1170 // IRTX ________
1171 // T1 T2 T3
1172
1173 /* MIR 115200, 57600 */
1174 if (speed==1152000)
1175 {
1176 tmp |= 0xA0; //HDLC=1, 1.152Mbps=1
1177 }
1178 else
1179 {
1180 tmp &=~0x80; //HDLC 0.576Mbps
1181 tmp |= 0x20; //HDLC=1,
1182 }
1183
1184 tmp |= IRDA_CR_CRC; // CRC=1
1185
1186 switch_bank(iobase, BANK2);
1187 outb(tmp, iobase+FIR_IRDA_CR);
1188
1189 /* MIR 115200, 57600 */
1190
1191 //switch_bank(iobase, BANK2);
1192 // T1 -> SD/MODE:0 IRTX:0
1193 tmp &= ~0x09;
1194 tmp |= 0x02;
1195 outb(tmp, iobase+FIR_IRDA_CR);
1196 udelay(2);
1197
1198 // T2 -> SD/MODE:1 IRTX:0
1199 tmp &= ~0x01;
1200 tmp |= 0x0a;
1201 outb(tmp, iobase+FIR_IRDA_CR);
1202
1203 // T3 -> SD/MODE:0 IRTX:0
1204 tmp &= ~0x09;
1205 tmp |= 0x02;
1206 outb(tmp, iobase+FIR_IRDA_CR);
1207 udelay(2);
1208
1209 // reset -> Normal TX output Signal
1210 outb(tmp & ~0x02, iobase+FIR_IRDA_CR);
1211 }
1212 }
1213 else if (dongle_id == 1) /* HP HDSL-3600 */
1214 {
1215 switch(speed)
1216 {
1217 case 4000000:
1218 tmp &= ~IRDA_CR_HDLC; // HDLC=0
1219 break;
1220
1221 case 1152000:
1222 tmp |= 0xA0; // HDLC=1, 1.152Mbps=1
1223 break;
1224
1225 case 576000:
1226 tmp &=~0x80; // HDLC 0.576Mbps
1227 tmp |= 0x20; // HDLC=1,
1228 break;
1229 }
1230
1231 tmp |= IRDA_CR_CRC; // CRC=1
1232
1233 switch_bank(iobase, BANK2);
1234 outb(tmp, iobase+FIR_IRDA_CR);
1235 }
1236 else /* HP HDSL-1100 */
1237 {
1238 if(speed <= 115200) /* SIR */
1239 {
1240
1241 tmp &= ~IRDA_CR_FIR_SIN; // HP sin select = 0
1242
1243 switch_bank(iobase, BANK2);
1244 outb(tmp, iobase+FIR_IRDA_CR);
1245 }
1246 else /* MIR FIR */
1247 {
1248
1249 switch(speed)
1250 {
1251 case 4000000:
1252 tmp &= ~IRDA_CR_HDLC; // HDLC=0
1253 break;
1254
1255 case 1152000:
1256 tmp |= 0xA0; // HDLC=1, 1.152Mbps=1
1257 break;
1258
1259 case 576000:
1260 tmp &=~0x80; // HDLC 0.576Mbps
1261 tmp |= 0x20; // HDLC=1,
1262 break;
1263 }
1264
1265 tmp |= IRDA_CR_CRC; // CRC=1
1266 tmp |= IRDA_CR_FIR_SIN; // HP sin select = 1
1267
1268 switch_bank(iobase, BANK2);
1269 outb(tmp, iobase+FIR_IRDA_CR);
1270 }
1271 }
1272
1273 switch_bank(iobase, BANK0);
1274
1da177e4
LT		 1275}
1276
1277/*
1278 * Function ali_ircc_sir_write (driver)
1279 *
1280 * Fill Tx FIFO with transmit data
1281 *
1282 */
1283static int ali_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1284{
1285 int actual = 0;
1286
1da177e4
LT		 1287
1288 /* Tx FIFO should be empty! */
1289 if (!(inb(iobase+UART_LSR) & UART_LSR_THRE)) {
955a9d20 1290 pr_debug("%s(), failed, fifo not empty!\n", __func__);
1da177e4
LT		 1291 return 0;
1292 }
1293
1294 /* Fill FIFO with current frame */
1295 while ((fifo_size-- > 0) && (actual < len)) {
1296 /* Transmit next byte */
1297 outb(buf[actual], iobase+UART_TX);
1298
1299 actual++;
1300 }
1301
1da177e4
LT		 1302 return actual;
1303}
1304
1305/*
1306 * Function ali_ircc_net_open (dev)
1307 *
1308 * Start the device
1309 *
1310 */
1311static int ali_ircc_net_open(struct net_device *dev)
1312{
1313 struct ali_ircc_cb *self;
1314 int iobase;
1315 char hwname[32];
1316
1da177e4
LT		 1317
1318 IRDA_ASSERT(dev != NULL, return -1;);
1319
4cf1653a 1320 self = netdev_priv(dev);
1da177e4
LT		 1321
1322 IRDA_ASSERT(self != NULL, return 0;);
1323
1324 iobase = self->io.fir_base;
1325
1326 /* Request IRQ and install Interrupt Handler */
1327 if (request_irq(self->io.irq, ali_ircc_interrupt, 0, dev->name, dev))
1328 {
6c91023d
JP		 1329 net_warn_ratelimited("%s, unable to allocate irq=%d\n",
1330 ALI_IRCC_DRIVER_NAME, self->io.irq);
1da177e4
LT		 1331 return -EAGAIN;
1332 }
1333
1334 /*
1335 * Always allocate the DMA channel after the IRQ, and clean up on
1336 * failure.
1337 */
1338 if (request_dma(self->io.dma, dev->name)) {
6c91023d
JP		 1339 net_warn_ratelimited("%s, unable to allocate dma=%d\n",
1340 ALI_IRCC_DRIVER_NAME, self->io.dma);
a997cbb3 1341 free_irq(self->io.irq, dev);
1da177e4
LT		 1342 return -EAGAIN;
1343 }
1344
1345 /* Turn on interrups */
1346 outb(UART_IER_RDI , iobase+UART_IER);
1347
1348 /* Ready to play! */
1349 netif_start_queue(dev); //benjamin by irport
1350
1351 /* Give self a hardware name */
1352 sprintf(hwname, "ALI-FIR @ 0x%03x", self->io.fir_base);
1353
1354 /*
1355 * Open new IrLAP layer instance, now that everything should be
1356 * initialized properly
1357 */
1358 self->irlap = irlap_open(dev, &self->qos, hwname);
1359
1da177e4
LT		 1360
1361 return 0;
1362}
1363
1364/*
1365 * Function ali_ircc_net_close (dev)
1366 *
1367 * Stop the device
1368 *
1369 */
1370static int ali_ircc_net_close(struct net_device *dev)
1371{
1372
1373 struct ali_ircc_cb *self;
1374 //int iobase;
1375
1da177e4
LT		 1376
1377 IRDA_ASSERT(dev != NULL, return -1;);
1378
4cf1653a 1379 self = netdev_priv(dev);
1da177e4
LT		 1380 IRDA_ASSERT(self != NULL, return 0;);
1381
1382 /* Stop device */
1383 netif_stop_queue(dev);
1384
1385 /* Stop and remove instance of IrLAP */
1386 if (self->irlap)
1387 irlap_close(self->irlap);
1388 self->irlap = NULL;
1389
1390 disable_dma(self->io.dma);
1391
1392 /* Disable interrupts */
1393 SetCOMInterrupts(self, FALSE);
1394
1395 free_irq(self->io.irq, dev);
1396 free_dma(self->io.dma);
1397
1da177e4
LT		 1398
1399 return 0;
1400}
1401
1402/*
1403 * Function ali_ircc_fir_hard_xmit (skb, dev)
1404 *
1405 * Transmit the frame
1406 *
1407 */
6518bbb8
SH		 1408static netdev_tx_t ali_ircc_fir_hard_xmit(struct sk_buff *skb,
1409 struct net_device *dev)
1da177e4
LT		 1410{
1411 struct ali_ircc_cb *self;
1412 unsigned long flags;
1413 int iobase;
1414 __u32 speed;
1415 int mtt, diff;
1416
1da177e4 1417
4cf1653a 1418 self = netdev_priv(dev);
1da177e4
LT		 1419 iobase = self->io.fir_base;
1420
1421 netif_stop_queue(dev);
1422
1423 /* Make sure tests *& speed change are atomic */
1424 spin_lock_irqsave(&self->lock, flags);
1425
1426 /* Note : you should make sure that speed changes are not going
1427 * to corrupt any outgoing frame. Look at nsc-ircc for the gory
1428 * details - Jean II */
1429
1430 /* Check if we need to change the speed */
1431 speed = irda_get_next_speed(skb);
1432 if ((speed != self->io.speed) && (speed != -1)) {
1433 /* Check for empty frame */
1434 if (!skb->len) {
1435 ali_ircc_change_speed(self, speed);
1436 dev->trans_start = jiffies;
1437 spin_unlock_irqrestore(&self->lock, flags);
1438 dev_kfree_skb(skb);
6ed10654 1439 return NETDEV_TX_OK;
1da177e4
LT		 1440 } else
1441 self->new_speed = speed;
1442 }
1443
1444 /* Register and copy this frame to DMA memory */
1445 self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail;
1446 self->tx_fifo.queue[self->tx_fifo.free].len = skb->len;
1447 self->tx_fifo.tail += skb->len;
1448
af049081 1449 dev->stats.tx_bytes += skb->len;
1da177e4 1450
d626f62b
ACM		 1451 skb_copy_from_linear_data(skb, self->tx_fifo.queue[self->tx_fifo.free].start,
1452 skb->len);
1da177e4
LT		 1453 self->tx_fifo.len++;
1454 self->tx_fifo.free++;
1455
1456 /* Start transmit only if there is currently no transmit going on */
1457 if (self->tx_fifo.len == 1)
1458 {
1459 /* Check if we must wait the min turn time or not */
1460 mtt = irda_get_mtt(skb);
1461
1462 if (mtt)
1463 {
1464 /* Check how much time we have used already */
1465 do_gettimeofday(&self->now);
1466
1467 diff = self->now.tv_usec - self->stamp.tv_usec;
1468 /* self->stamp is set from ali_ircc_dma_receive_complete() */
1469
955a9d20
JP		 1470 pr_debug("%s(), ******* diff = %d *******\n",
1471 __func__, diff);
1da177e4
LT		 1472
1473 if (diff < 0)
1474 diff += 1000000;
1475
1476 /* Check if the mtt is larger than the time we have
1477 * already used by all the protocol processing
1478 */
1479 if (mtt > diff)
1480 {
1481 mtt -= diff;
1482
1483 /*
1484 * Use timer if delay larger than 1000 us, and
1485 * use udelay for smaller values which should
1486 * be acceptable
1487 */
1488 if (mtt > 500)
1489 {
1490 /* Adjust for timer resolution */
1491 mtt = (mtt+250) / 500; /* 4 discard, 5 get advanced, Let's round off */
1492
955a9d20
JP		 1493 pr_debug("%s(), ************** mtt = %d ***********\n",
1494 __func__, mtt);
1da177e4
LT		 1495
1496 /* Setup timer */
1497 if (mtt == 1) /* 500 us */
1498 {
1499 switch_bank(iobase, BANK1);
1500 outb(TIMER_IIR_500, iobase+FIR_TIMER_IIR);
1501 }
1502 else if (mtt == 2) /* 1 ms */
1503 {
1504 switch_bank(iobase, BANK1);
1505 outb(TIMER_IIR_1ms, iobase+FIR_TIMER_IIR);
1506 }
1507 else /* > 2ms -> 4ms */
1508 {
1509 switch_bank(iobase, BANK1);
1510 outb(TIMER_IIR_2ms, iobase+FIR_TIMER_IIR);
1511 }
1512
1513
1514 /* Start timer */
1515 outb(inb(iobase+FIR_CR) | CR_TIMER_EN, iobase+FIR_CR);
1516 self->io.direction = IO_XMIT;
1517
1518 /* Enable timer interrupt */
1519 self->ier = IER_TIMER;
1520 SetCOMInterrupts(self, TRUE);
1521
1522 /* Timer will take care of the rest */
1523 goto out;
1524 }
1525 else
1526 udelay(mtt);
1527 } // if (if (mtt > diff)
1528 }// if (mtt)
1529
1530 /* Enable EOM interrupt */
1531 self->ier = IER_EOM;
1532 SetCOMInterrupts(self, TRUE);
1533
1534 /* Transmit frame */
1535 ali_ircc_dma_xmit(self);
1536 } // if (self->tx_fifo.len == 1)
1537
1538 out:
1539
1540 /* Not busy transmitting anymore if window is not full */
1541 if (self->tx_fifo.free < MAX_TX_WINDOW)
1542 netif_wake_queue(self->netdev);
1543
1544 /* Restore bank register */
1545 switch_bank(iobase, BANK0);
1546
1547 dev->trans_start = jiffies;
1548 spin_unlock_irqrestore(&self->lock, flags);
1549 dev_kfree_skb(skb);
1550
6ed10654 1551 return NETDEV_TX_OK;
1da177e4
LT		 1552}
1553
1554
1555static void ali_ircc_dma_xmit(struct ali_ircc_cb *self)
1556{
1557 int iobase, tmp;
1558 unsigned char FIFO_OPTI, Hi, Lo;
1559
1560
1da177e4
LT		 1561
1562 iobase = self->io.fir_base;
1563
1564 /* FIFO threshold , this method comes from NDIS5 code */
1565
1566 if(self->tx_fifo.queue[self->tx_fifo.ptr].len < TX_FIFO_Threshold)
1567 FIFO_OPTI = self->tx_fifo.queue[self->tx_fifo.ptr].len-1;
1568 else
1569 FIFO_OPTI = TX_FIFO_Threshold;
1570
1571 /* Disable DMA */
1572 switch_bank(iobase, BANK1);
1573 outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR);
1574
1575 self->io.direction = IO_XMIT;
1576
1577 irda_setup_dma(self->io.dma,
1578 ((u8 *)self->tx_fifo.queue[self->tx_fifo.ptr].start -
1579 self->tx_buff.head) + self->tx_buff_dma,
1580 self->tx_fifo.queue[self->tx_fifo.ptr].len,
1581 DMA_TX_MODE);
1582
1583 /* Reset Tx FIFO */
1584 switch_bank(iobase, BANK0);
1585 outb(LCR_A_FIFO_RESET, iobase+FIR_LCR_A);
1586
1587 /* Set Tx FIFO threshold */
1588 if (self->fifo_opti_buf!=FIFO_OPTI)
1589 {
1590 switch_bank(iobase, BANK1);
1591 outb(FIFO_OPTI, iobase+FIR_FIFO_TR) ;
1592 self->fifo_opti_buf=FIFO_OPTI;
1593 }
1594
1595 /* Set Tx DMA threshold */
1596 switch_bank(iobase, BANK1);
1597 outb(TX_DMA_Threshold, iobase+FIR_DMA_TR);
1598
1599 /* Set max Tx frame size */
1600 Hi = (self->tx_fifo.queue[self->tx_fifo.ptr].len >> 8) & 0x0f;
1601 Lo = self->tx_fifo.queue[self->tx_fifo.ptr].len & 0xff;
1602 switch_bank(iobase, BANK2);
1603 outb(Hi, iobase+FIR_TX_DSR_HI);
1604 outb(Lo, iobase+FIR_TX_DSR_LO);
1605
1606 /* Disable SIP , Disable Brick Wall (we don't support in TX mode), Change to TX mode */
1607 switch_bank(iobase, BANK0);
1608 tmp = inb(iobase+FIR_LCR_B);
1609 tmp &= ~0x20; // Disable SIP
1610 outb(((unsigned char)(tmp & 0x3f) | LCR_B_TX_MODE) & ~LCR_B_BW, iobase+FIR_LCR_B);
955a9d20
JP		 1611 pr_debug("%s(), *** Change to TX mode: FIR_LCR_B = 0x%x ***\n",
1612 __func__, inb(iobase + FIR_LCR_B));
1da177e4
LT		 1613
1614 outb(0, iobase+FIR_LSR);
1615
1616 /* Enable DMA and Burst Mode */
1617 switch_bank(iobase, BANK1);
1618 outb(inb(iobase+FIR_CR) | CR_DMA_EN | CR_DMA_BURST, iobase+FIR_CR);
1619
1620 switch_bank(iobase, BANK0);
1621
1da177e4
LT		 1622}
1623
1624static int ali_ircc_dma_xmit_complete(struct ali_ircc_cb *self)
1625{
1626 int iobase;
1627 int ret = TRUE;
1628
1da177e4
LT		 1629
1630 iobase = self->io.fir_base;
1631
1632 /* Disable DMA */
1633 switch_bank(iobase, BANK1);
1634 outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR);
1635
1636 /* Check for underrun! */
1637 switch_bank(iobase, BANK0);
1638 if((inb(iobase+FIR_LSR) & LSR_FRAME_ABORT) == LSR_FRAME_ABORT)
1639
1640 {
6c91023d
JP		 1641 net_err_ratelimited("%s(), ********* LSR_FRAME_ABORT *********\n",
1642 __func__);
af049081
SH		 1643 self->netdev->stats.tx_errors++;
1644 self->netdev->stats.tx_fifo_errors++;
1da177e4
LT		 1645 }
1646 else
1647 {
af049081 1648 self->netdev->stats.tx_packets++;
1da177e4
LT		 1649 }
1650
1651 /* Check if we need to change the speed */
1652 if (self->new_speed)
1653 {
1654 ali_ircc_change_speed(self, self->new_speed);
1655 self->new_speed = 0;
1656 }
1657
1658 /* Finished with this frame, so prepare for next */
1659 self->tx_fifo.ptr++;
1660 self->tx_fifo.len--;
1661
1662 /* Any frames to be sent back-to-back? */
1663 if (self->tx_fifo.len)
1664 {
1665 ali_ircc_dma_xmit(self);
1666
1667 /* Not finished yet! */
1668 ret = FALSE;
1669 }
1670 else
1671 { /* Reset Tx FIFO info */
1672 self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
1673 self->tx_fifo.tail = self->tx_buff.head;
1674 }
1675
1676 /* Make sure we have room for more frames */
1677 if (self->tx_fifo.free < MAX_TX_WINDOW) {
1678 /* Not busy transmitting anymore */
1679 /* Tell the network layer, that we can accept more frames */
1680 netif_wake_queue(self->netdev);
1681 }
1682
1683 switch_bank(iobase, BANK0);
1684
1da177e4
LT		 1685 return ret;
1686}
1687
1688/*
1689 * Function ali_ircc_dma_receive (self)
1690 *
1691 * Get ready for receiving a frame. The device will initiate a DMA
1692 * if it starts to receive a frame.
1693 *
1694 */
1695static int ali_ircc_dma_receive(struct ali_ircc_cb *self)
1696{
1697 int iobase, tmp;
1698
1da177e4
LT		 1699
1700 iobase = self->io.fir_base;
1701
1702 /* Reset Tx FIFO info */
1703 self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
1704 self->tx_fifo.tail = self->tx_buff.head;
1705
1706 /* Disable DMA */
1707 switch_bank(iobase, BANK1);
1708 outb(inb(iobase+FIR_CR) & ~CR_DMA_EN, iobase+FIR_CR);
1709
1710 /* Reset Message Count */
1711 switch_bank(iobase, BANK0);
1712 outb(0x07, iobase+FIR_LSR);
1713
1714 self->rcvFramesOverflow = FALSE;
1715
1716 self->LineStatus = inb(iobase+FIR_LSR) ;
1717
1718 /* Reset Rx FIFO info */
1719 self->io.direction = IO_RECV;
1720 self->rx_buff.data = self->rx_buff.head;
1721
1722 /* Reset Rx FIFO */
1723 // switch_bank(iobase, BANK0);
1724 outb(LCR_A_FIFO_RESET, iobase+FIR_LCR_A);
1725
1726 self->st_fifo.len = self->st_fifo.pending_bytes = 0;
1727 self->st_fifo.tail = self->st_fifo.head = 0;
1728
1729 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1730 DMA_RX_MODE);
1731
1732 /* Set Receive Mode,Brick Wall */
1733 //switch_bank(iobase, BANK0);
1734 tmp = inb(iobase+FIR_LCR_B);
1735 outb((unsigned char)(tmp &0x3f) | LCR_B_RX_MODE | LCR_B_BW , iobase + FIR_LCR_B); // 2000/12/1 05:16PM
955a9d20
JP		 1736 pr_debug("%s(), *** Change To RX mode: FIR_LCR_B = 0x%x ***\n",
1737 __func__, inb(iobase + FIR_LCR_B));
1da177e4
LT		 1738
1739 /* Set Rx Threshold */
1740 switch_bank(iobase, BANK1);
1741 outb(RX_FIFO_Threshold, iobase+FIR_FIFO_TR);
1742 outb(RX_DMA_Threshold, iobase+FIR_DMA_TR);
1743
1744 /* Enable DMA and Burst Mode */
1745 // switch_bank(iobase, BANK1);
1746 outb(CR_DMA_EN | CR_DMA_BURST, iobase+FIR_CR);
1747
1748 switch_bank(iobase, BANK0);
1da177e4
LT		 1749 return 0;
1750}
1751
1752static int ali_ircc_dma_receive_complete(struct ali_ircc_cb *self)
1753{
1754 struct st_fifo *st_fifo;
1755 struct sk_buff *skb;
1756 __u8 status, MessageCount;
1757 int len, i, iobase, val;
1758
1da177e4
LT		 1759 st_fifo = &self->st_fifo;
1760 iobase = self->io.fir_base;
1761
1762 switch_bank(iobase, BANK0);
1763 MessageCount = inb(iobase+ FIR_LSR)&0x07;
1764
1765 if (MessageCount > 0)
955a9d20 1766 pr_debug("%s(), Message count = %d\n", __func__, MessageCount);
1da177e4
LT		 1767
1768 for (i=0; i<=MessageCount; i++)
1769 {
1770 /* Bank 0 */
1771 switch_bank(iobase, BANK0);
1772 status = inb(iobase+FIR_LSR);
1773
1774 switch_bank(iobase, BANK2);
1775 len = inb(iobase+FIR_RX_DSR_HI) & 0x0f;
1776 len = len << 8;
1777 len |= inb(iobase+FIR_RX_DSR_LO);
1778
955a9d20
JP		 1779 pr_debug("%s(), RX Length = 0x%.2x,\n", __func__ , len);
1780 pr_debug("%s(), RX Status = 0x%.2x,\n", __func__ , status);
1da177e4
LT		 1781
1782 if (st_fifo->tail >= MAX_RX_WINDOW) {
955a9d20 1783 pr_debug("%s(), window is full!\n", __func__);
1da177e4
LT		 1784 continue;
1785 }
1786
1787 st_fifo->entries[st_fifo->tail].status = status;
1788 st_fifo->entries[st_fifo->tail].len = len;
1789 st_fifo->pending_bytes += len;
1790 st_fifo->tail++;
1791 st_fifo->len++;
1792 }
1793
1794 for (i=0; i<=MessageCount; i++)
1795 {
1796 /* Get first entry */
1797 status = st_fifo->entries[st_fifo->head].status;
1798 len = st_fifo->entries[st_fifo->head].len;
1799 st_fifo->pending_bytes -= len;
1800 st_fifo->head++;
1801 st_fifo->len--;
1802
1803 /* Check for errors */
1804 if ((status & 0xd8) || self->rcvFramesOverflow || (len==0))
1805 {
955a9d20
JP		 1806 pr_debug("%s(), ************* RX Errors ************\n",
1807 __func__);
1da177e4
LT		 1808
1809 /* Skip frame */
af049081 1810 self->netdev->stats.rx_errors++;
1da177e4
LT		 1811
1812 self->rx_buff.data += len;
1813
1814 if (status & LSR_FIFO_UR)
1815 {
af049081 1816 self->netdev->stats.rx_frame_errors++;
955a9d20
JP		 1817 pr_debug("%s(), ************* FIFO Errors ************\n",
1818 __func__);
1da177e4
LT		 1819 }
1820 if (status & LSR_FRAME_ERROR)
1821 {
af049081 1822 self->netdev->stats.rx_frame_errors++;
955a9d20
JP		 1823 pr_debug("%s(), ************* FRAME Errors ************\n",
1824 __func__);
1da177e4
LT		 1825 }
1826
1827 if (status & LSR_CRC_ERROR)
1828 {
af049081 1829 self->netdev->stats.rx_crc_errors++;
955a9d20
JP		 1830 pr_debug("%s(), ************* CRC Errors ************\n",
1831 __func__);
1da177e4
LT		 1832 }
1833
1834 if(self->rcvFramesOverflow)
1835 {
af049081 1836 self->netdev->stats.rx_frame_errors++;
955a9d20
JP		 1837 pr_debug("%s(), ************* Overran DMA buffer ************\n",
1838 __func__);
1da177e4
LT		 1839 }
1840 if(len == 0)
1841 {
af049081 1842 self->netdev->stats.rx_frame_errors++;
955a9d20
JP		 1843 pr_debug("%s(), ********** Receive Frame Size = 0 *********\n",
1844 __func__);
1da177e4
LT		 1845 }
1846 }
1847 else
1848 {
1849
1850 if (st_fifo->pending_bytes < 32)
1851 {
1852 switch_bank(iobase, BANK0);
1853 val = inb(iobase+FIR_BSR);
1854 if ((val& BSR_FIFO_NOT_EMPTY)== 0x80)
1855 {
955a9d20
JP		 1856 pr_debug("%s(), ************* BSR_FIFO_NOT_EMPTY ************\n",
1857 __func__);
1da177e4
LT		 1858
1859 /* Put this entry back in fifo */
1860 st_fifo->head--;
1861 st_fifo->len++;
1862 st_fifo->pending_bytes += len;
1863 st_fifo->entries[st_fifo->head].status = status;
1864 st_fifo->entries[st_fifo->head].len = len;
1865
1866 /*
1867 * DMA not finished yet, so try again
1868 * later, set timer value, resolution
1869 * 500 us
1870 */
1871
1872 switch_bank(iobase, BANK1);
1873 outb(TIMER_IIR_500, iobase+FIR_TIMER_IIR); // 2001/1/2 05:07PM
1874
1875 /* Enable Timer */
1876 outb(inb(iobase+FIR_CR) | CR_TIMER_EN, iobase+FIR_CR);
1877
1878 return FALSE; /* I'll be back! */
1879 }
1880 }
1881
1882 /*
1883 * Remember the time we received this frame, so we can
1884 * reduce the min turn time a bit since we will know
1885 * how much time we have used for protocol processing
1886 */
1887 do_gettimeofday(&self->stamp);
1888
1889 skb = dev_alloc_skb(len+1);
1890 if (skb == NULL)
1891 {
af049081 1892 self->netdev->stats.rx_dropped++;
1da177e4
LT		 1893
1894 return FALSE;
1895 }
1896
1897 /* Make sure IP header gets aligned */
1898 skb_reserve(skb, 1);
1899
1900 /* Copy frame without CRC, CRC is removed by hardware*/
1901 skb_put(skb, len);
27d7ff46 1902 skb_copy_to_linear_data(skb, self->rx_buff.data, len);
1da177e4
LT		 1903
1904 /* Move to next frame */
1905 self->rx_buff.data += len;
af049081
SH		 1906 self->netdev->stats.rx_bytes += len;
1907 self->netdev->stats.rx_packets++;
1da177e4
LT		 1908
1909 skb->dev = self->netdev;
459a98ed 1910 skb_reset_mac_header(skb);
1da177e4
LT		 1911 skb->protocol = htons(ETH_P_IRDA);
1912 netif_rx(skb);
1da177e4
LT		 1913 }
1914 }
1915
1916 switch_bank(iobase, BANK0);
1917
1da177e4
LT		 1918 return TRUE;
1919}
1920
1921
1922
1923/*
1924 * Function ali_ircc_sir_hard_xmit (skb, dev)
1925 *
1926 * Transmit the frame!
1927 *
1928 */
6518bbb8
SH		 1929static netdev_tx_t ali_ircc_sir_hard_xmit(struct sk_buff *skb,
1930 struct net_device *dev)
1da177e4
LT		 1931{
1932 struct ali_ircc_cb *self;
1933 unsigned long flags;
1934 int iobase;
1935 __u32 speed;
1936
1da177e4 1937
ec634fe3 1938 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
1da177e4 1939
4cf1653a 1940 self = netdev_priv(dev);
ec634fe3 1941 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1da177e4
LT		 1942
1943 iobase = self->io.sir_base;
1944
1945 netif_stop_queue(dev);
1946
1947 /* Make sure tests *& speed change are atomic */
1948 spin_lock_irqsave(&self->lock, flags);
1949
1950 /* Note : you should make sure that speed changes are not going
1951 * to corrupt any outgoing frame. Look at nsc-ircc for the gory
1952 * details - Jean II */
1953
1954 /* Check if we need to change the speed */
1955 speed = irda_get_next_speed(skb);
1956 if ((speed != self->io.speed) && (speed != -1)) {
1957 /* Check for empty frame */
1958 if (!skb->len) {
1959 ali_ircc_change_speed(self, speed);
1960 dev->trans_start = jiffies;
1961 spin_unlock_irqrestore(&self->lock, flags);
1962 dev_kfree_skb(skb);
6ed10654 1963 return NETDEV_TX_OK;
1da177e4
LT		 1964 } else
1965 self->new_speed = speed;
1966 }
1967
1968 /* Init tx buffer */
1969 self->tx_buff.data = self->tx_buff.head;
1970
1971 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
1972 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
1973 self->tx_buff.truesize);
1974
af049081 1975 self->netdev->stats.tx_bytes += self->tx_buff.len;
1da177e4
LT		 1976
1977 /* Turn on transmit finished interrupt. Will fire immediately! */
1978 outb(UART_IER_THRI, iobase+UART_IER);
1979
1980 dev->trans_start = jiffies;
1981 spin_unlock_irqrestore(&self->lock, flags);
1982
1983 dev_kfree_skb(skb);
1984
1da177e4 1985
6ed10654 1986 return NETDEV_TX_OK;
1da177e4
LT		 1987}
1988
1989
1990/*
1991 * Function ali_ircc_net_ioctl (dev, rq, cmd)
1992 *
1993 * Process IOCTL commands for this device
1994 *
1995 */
1996static int ali_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1997{
1998 struct if_irda_req *irq = (struct if_irda_req *) rq;
1999 struct ali_ircc_cb *self;
2000 unsigned long flags;
2001 int ret = 0;
2002
1da177e4
LT		 2003
2004 IRDA_ASSERT(dev != NULL, return -1;);
2005
4cf1653a 2006 self = netdev_priv(dev);
1da177e4
LT		 2007
2008 IRDA_ASSERT(self != NULL, return -1;);
2009
955a9d20 2010 pr_debug("%s(), %s, (cmd=0x%X)\n", __func__ , dev->name, cmd);
1da177e4
LT		 2011
2012 switch (cmd) {
2013 case SIOCSBANDWIDTH: /* Set bandwidth */
955a9d20 2014 pr_debug("%s(), SIOCSBANDWIDTH\n", __func__);
1da177e4
LT		 2015 /*
2016 * This function will also be used by IrLAP to change the
2017 * speed, so we still must allow for speed change within
2018 * interrupt context.
2019 */
2020 if (!in_interrupt() && !capable(CAP_NET_ADMIN))
2021 return -EPERM;
2022
2023 spin_lock_irqsave(&self->lock, flags);
2024 ali_ircc_change_speed(self, irq->ifr_baudrate);
2025 spin_unlock_irqrestore(&self->lock, flags);
2026 break;
2027 case SIOCSMEDIABUSY: /* Set media busy */
955a9d20 2028 pr_debug("%s(), SIOCSMEDIABUSY\n", __func__);
1da177e4
LT		 2029 if (!capable(CAP_NET_ADMIN))
2030 return -EPERM;
2031 irda_device_set_media_busy(self->netdev, TRUE);
2032 break;
2033 case SIOCGRECEIVING: /* Check if we are receiving right now */
955a9d20 2034 pr_debug("%s(), SIOCGRECEIVING\n", __func__);
1da177e4
LT		 2035 /* This is protected */
2036 irq->ifr_receiving = ali_ircc_is_receiving(self);
2037 break;
2038 default:
2039 ret = -EOPNOTSUPP;
2040 }
2041
1da177e4
LT		 2042
2043 return ret;
2044}
2045
2046/*
2047 * Function ali_ircc_is_receiving (self)
2048 *
2049 * Return TRUE is we are currently receiving a frame
2050 *
2051 */
2052static int ali_ircc_is_receiving(struct ali_ircc_cb *self)
2053{
2054 unsigned long flags;
2055 int status = FALSE;
2056 int iobase;
2057
1da177e4
LT		 2058
2059 IRDA_ASSERT(self != NULL, return FALSE;);
2060
2061 spin_lock_irqsave(&self->lock, flags);
2062
2063 if (self->io.speed > 115200)
2064 {
2065 iobase = self->io.fir_base;
2066
2067 switch_bank(iobase, BANK1);
2068 if((inb(iobase+FIR_FIFO_FR) & 0x3f) != 0)
2069 {
2070 /* We are receiving something */
955a9d20
JP		 2071 pr_debug("%s(), We are receiving something\n",
2072 __func__);
1da177e4
LT		 2073 status = TRUE;
2074 }
2075 switch_bank(iobase, BANK0);
2076 }
2077 else
2078 {
2079 status = (self->rx_buff.state != OUTSIDE_FRAME);
2080 }
2081
2082 spin_unlock_irqrestore(&self->lock, flags);
2083
1da177e4
LT		 2084
2085 return status;
2086}
2087
898b1d16 2088static int ali_ircc_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 2089{
898b1d16 2090 struct ali_ircc_cb *self = platform_get_drvdata(dev);
1da177e4 2091
6c91023d 2092 net_info_ratelimited("%s, Suspending\n", ALI_IRCC_DRIVER_NAME);
1da177e4
LT		 2093
2094 if (self->io.suspended)
898b1d16 2095 return 0;
1da177e4
LT		 2096
2097 ali_ircc_net_close(self->netdev);
2098
2099 self->io.suspended = 1;
2100
898b1d16 2101 return 0;
1da177e4
LT		 2102}
2103
898b1d16 2104static int ali_ircc_resume(struct platform_device *dev)
1da177e4 2105{
898b1d16 2106 struct ali_ircc_cb *self = platform_get_drvdata(dev);
1da177e4
LT		 2107
2108 if (!self->io.suspended)
898b1d16 2109 return 0;
1da177e4
LT		 2110
2111 ali_ircc_net_open(self->netdev);
2112
6c91023d 2113 net_info_ratelimited("%s, Waking up\n", ALI_IRCC_DRIVER_NAME);
1da177e4
LT		 2114
2115 self->io.suspended = 0;
1da177e4 2116
1da177e4
LT		 2117 return 0;
2118}
2119
1da177e4
LT		 2120/* ALi Chip Function */
2121
2122static void SetCOMInterrupts(struct ali_ircc_cb *self , unsigned char enable)
2123{
2124
2125 unsigned char newMask;
2126
2127 int iobase = self->io.fir_base; /* or sir_base */
2128
955a9d20
JP		 2129 pr_debug("%s(), -------- Start -------- ( Enable = %d )\n",
2130 __func__, enable);
1da177e4
LT		 2131
2132 /* Enable the interrupt which we wish to */
2133 if (enable){
2134 if (self->io.direction == IO_XMIT)
2135 {
2136 if (self->io.speed > 115200) /* FIR, MIR */
2137 {
2138 newMask = self->ier;
2139 }
2140 else /* SIR */
2141 {
2142 newMask = UART_IER_THRI | UART_IER_RDI;
2143 }
2144 }
2145 else {
2146 if (self->io.speed > 115200) /* FIR, MIR */
2147 {
2148 newMask = self->ier;
2149 }
2150 else /* SIR */
2151 {
2152 newMask = UART_IER_RDI;
2153 }
2154 }
2155 }
2156 else /* Disable all the interrupts */
2157 {
2158 newMask = 0x00;
2159
2160 }
2161
2162 //SIR and FIR has different registers
2163 if (self->io.speed > 115200)
2164 {
2165 switch_bank(iobase, BANK0);
2166 outb(newMask, iobase+FIR_IER);
2167 }
2168 else
2169 outb(newMask, iobase+UART_IER);
2170
1da177e4
LT		 2171}
2172
2173static void SIR2FIR(int iobase)
2174{
2175 //unsigned char tmp;
2176
1da177e4
LT		 2177
2178 /* Already protected (change_speed() or setup()), no need to lock.
2179 * Jean II */
2180
2181 outb(0x28, iobase+UART_MCR);
2182 outb(0x68, iobase+UART_MCR);
2183 outb(0x88, iobase+UART_MCR);
2184
2185 outb(0x60, iobase+FIR_MCR); /* Master Reset */
2186 outb(0x20, iobase+FIR_MCR); /* Master Interrupt Enable */
2187
2188 //tmp = inb(iobase+FIR_LCR_B); /* SIP enable */
2189 //tmp |= 0x20;
2190 //outb(tmp, iobase+FIR_LCR_B);
2191
1da177e4
LT		 2192}
2193
2194static void FIR2SIR(int iobase)
2195{
2196 unsigned char val;
2197
1da177e4
LT		 2198
2199 /* Already protected (change_speed() or setup()), no need to lock.
2200 * Jean II */
2201
2202 outb(0x20, iobase+FIR_MCR); /* IRQ to low */
2203 outb(0x00, iobase+UART_IER);
2204
2205 outb(0xA0, iobase+FIR_MCR); /* Don't set master reset */
2206 outb(0x00, iobase+UART_FCR);
2207 outb(0x07, iobase+UART_FCR);
2208
2209 val = inb(iobase+UART_RX);
2210 val = inb(iobase+UART_LSR);
2211 val = inb(iobase+UART_MSR);
2212
1da177e4
LT		 2213}
2214
2215MODULE_AUTHOR("Benjamin Kong <benjamin_kong@ali.com.tw>");
2216MODULE_DESCRIPTION("ALi FIR Controller Driver");
2217MODULE_LICENSE("GPL");
72abb461 2218MODULE_ALIAS("platform:" ALI_IRCC_DRIVER_NAME);
1da177e4
LT		 2219
2220
2221module_param_array(io, int, NULL, 0);
2222MODULE_PARM_DESC(io, "Base I/O addresses");
2223module_param_array(irq, int, NULL, 0);
2224MODULE_PARM_DESC(irq, "IRQ lines");
2225module_param_array(dma, int, NULL, 0);
2226MODULE_PARM_DESC(dma, "DMA channels");
2227
2228module_init(ali_ircc_init);
2229module_exit(ali_ircc_cleanup);
Linux 6.x block layer and io_uring tree(s)