[linux-block.git] / drivers / net / ipa / reg / gsi_reg-v3.5.1.c

// SPDX-License-Identifier: GPL-2.0

/* Copyright (C) 2023 Linaro Ltd. */

#include <linux/types.h>

#include "../gsi.h"
#include "../reg.h"
#include "../gsi_reg.h"

REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
    0x0000c020 + 0x1000 * GSI_EE_AP);

REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
    0x0000c024 + 0x1000 * GSI_EE_AP);

static const u32 reg_ch_c_cntxt_0_fmask[] = {
	[CHTYPE_PROTOCOL]				= GENMASK(2, 0),
	[CHTYPE_DIR]					= BIT(3),
	[CH_EE]						= GENMASK(7, 4),
	[CHID]						= GENMASK(12, 8),
						/* Bit 13 reserved */
	[ERINDEX]					= GENMASK(18, 14),
						/* Bit 19 reserved */
	[CHSTATE]					= GENMASK(23, 20),
	[ELEMENT_SIZE]					= GENMASK(31, 24),
};

REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
		  0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);

static const u32 reg_ch_c_cntxt_1_fmask[] = {
	[CH_R_LENGTH]					= GENMASK(15, 0),
						/* Bits 16-31 reserved */
};

REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
		  0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);

static const u32 reg_ch_c_qos_fmask[] = {
	[WRR_WEIGHT]					= GENMASK(3, 0),
						/* Bits 4-7 reserved */
	[MAX_PREFETCH]					= BIT(8),
	[USE_DB_ENG]					= BIT(9),
						/* Bits 10-31 reserved */
};

REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);

static const u32 reg_error_log_fmask[] = {
	[ERR_ARG3]					= GENMASK(3, 0),
	[ERR_ARG2]					= GENMASK(7, 4),
	[ERR_ARG1]					= GENMASK(11, 8),
	[ERR_CODE]					= GENMASK(15, 12),
						/* Bits 16-18 reserved */
	[ERR_VIRT_IDX]					= GENMASK(23, 19),
	[ERR_TYPE]					= GENMASK(27, 24),
	[ERR_EE]					= GENMASK(31, 28),
};

REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
	   0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
	   0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
	   0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
	   0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);

static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
	[EV_CHTYPE]					= GENMASK(3, 0),
	[EV_EE]						= GENMASK(7, 4),
	[EV_EVCHID]					= GENMASK(15, 8),
	[EV_INTYPE]					= BIT(16),
						/* Bits 17-19 reserved */
	[EV_CHSTATE]					= GENMASK(23, 20),
	[EV_ELEMENT_SIZE]				= GENMASK(31, 24),
};

REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
		  0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
	   0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
	   0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
	   0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
	   0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);

static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
	[EV_MODT]					= GENMASK(15, 0),
	[EV_MODC]					= GENMASK(23, 16),
	[EV_MOD_CNT]					= GENMASK(31, 24),
};

REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
		  0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
	   0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
	   0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
	   0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
	   0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
	   0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
	   0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
	   0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);

REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
	   0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);

REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
	   0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);

static const u32 reg_gsi_status_fmask[] = {
	[ENABLED]					= BIT(0),
						/* Bits 1-31 reserved */
};

REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);

static const u32 reg_ch_cmd_fmask[] = {
	[CH_CHID]					= GENMASK(7, 0),
						/* Bits 8-23 reserved */
	[CH_OPCODE]					= GENMASK(31, 24),
};

REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);

static const u32 reg_ev_ch_cmd_fmask[] = {
	[EV_CHID]					= GENMASK(7, 0),
						/* Bits 8-23 reserved */
	[EV_OPCODE]					= GENMASK(31, 24),
};

REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);

static const u32 reg_generic_cmd_fmask[] = {
	[GENERIC_OPCODE]				= GENMASK(4, 0),
	[GENERIC_CHID]					= GENMASK(9, 5),
	[GENERIC_EE]					= GENMASK(13, 10),
						/* Bits 14-31 reserved */
};

REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);

static const u32 reg_hw_param_2_fmask[] = {
	[IRAM_SIZE]					= GENMASK(2, 0),
	[NUM_CH_PER_EE]					= GENMASK(7, 3),
	[NUM_EV_PER_EE]					= GENMASK(12, 8),
	[GSI_CH_PEND_TRANSLATE]				= BIT(13),
	[GSI_CH_FULL_LOGIC]				= BIT(14),
						/* Bits 15-31 reserved */
};

REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP);

REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);

REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);

REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);

REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);

REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
    0x0001f098 + 0x4000 * GSI_EE_AP);

REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
    0x0001f09c + 0x4000 * GSI_EE_AP);

REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
    0x0001f0a0 + 0x4000 * GSI_EE_AP);

REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
    0x0001f0a4 + 0x4000 * GSI_EE_AP);

REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);

REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
    0x0001f0b8 + 0x4000 * GSI_EE_AP);

REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
    0x0001f0c0 + 0x4000 * GSI_EE_AP);

REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);

REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);

REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);

REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);

REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);

REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);

static const u32 reg_cntxt_intset_fmask[] = {
	[INTYPE]					= BIT(0)
						/* Bits 1-31 reserved */
};

REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);

REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);

REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);

static const u32 reg_cntxt_scratch_0_fmask[] = {
	[INTER_EE_RESULT]				= GENMASK(2, 0),
						/* Bits 3-4 reserved */
	[GENERIC_EE_RESULT]				= GENMASK(7, 5),
						/* Bits 8-31 reserved */
};

REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);

static const struct reg *reg_array[] = {
	[INTER_EE_SRC_CH_IRQ_MSK]	= &reg_inter_ee_src_ch_irq_msk,
	[INTER_EE_SRC_EV_CH_IRQ_MSK]	= &reg_inter_ee_src_ev_ch_irq_msk,
	[CH_C_CNTXT_0]			= &reg_ch_c_cntxt_0,
	[CH_C_CNTXT_1]			= &reg_ch_c_cntxt_1,
	[CH_C_CNTXT_2]			= &reg_ch_c_cntxt_2,
	[CH_C_CNTXT_3]			= &reg_ch_c_cntxt_3,
	[CH_C_QOS]			= &reg_ch_c_qos,
	[CH_C_SCRATCH_0]		= &reg_ch_c_scratch_0,
	[CH_C_SCRATCH_1]		= &reg_ch_c_scratch_1,
	[CH_C_SCRATCH_2]		= &reg_ch_c_scratch_2,
	[CH_C_SCRATCH_3]		= &reg_ch_c_scratch_3,
	[EV_CH_E_CNTXT_0]		= &reg_ev_ch_e_cntxt_0,
	[EV_CH_E_CNTXT_1]		= &reg_ev_ch_e_cntxt_1,
	[EV_CH_E_CNTXT_2]		= &reg_ev_ch_e_cntxt_2,
	[EV_CH_E_CNTXT_3]		= &reg_ev_ch_e_cntxt_3,
	[EV_CH_E_CNTXT_4]		= &reg_ev_ch_e_cntxt_4,
	[EV_CH_E_CNTXT_8]		= &reg_ev_ch_e_cntxt_8,
	[EV_CH_E_CNTXT_9]		= &reg_ev_ch_e_cntxt_9,
	[EV_CH_E_CNTXT_10]		= &reg_ev_ch_e_cntxt_10,
	[EV_CH_E_CNTXT_11]		= &reg_ev_ch_e_cntxt_11,
	[EV_CH_E_CNTXT_12]		= &reg_ev_ch_e_cntxt_12,
	[EV_CH_E_CNTXT_13]		= &reg_ev_ch_e_cntxt_13,
	[EV_CH_E_SCRATCH_0]		= &reg_ev_ch_e_scratch_0,
	[EV_CH_E_SCRATCH_1]		= &reg_ev_ch_e_scratch_1,
	[CH_C_DOORBELL_0]		= &reg_ch_c_doorbell_0,
	[EV_CH_E_DOORBELL_0]		= &reg_ev_ch_e_doorbell_0,
	[GSI_STATUS]			= &reg_gsi_status,
	[CH_CMD]			= &reg_ch_cmd,
	[EV_CH_CMD]			= &reg_ev_ch_cmd,
	[GENERIC_CMD]			= &reg_generic_cmd,
	[HW_PARAM_2]			= &reg_hw_param_2,
	[CNTXT_TYPE_IRQ]		= &reg_cntxt_type_irq,
	[CNTXT_TYPE_IRQ_MSK]		= &reg_cntxt_type_irq_msk,
	[CNTXT_SRC_CH_IRQ]		= &reg_cntxt_src_ch_irq,
	[CNTXT_SRC_EV_CH_IRQ]		= &reg_cntxt_src_ev_ch_irq,
	[CNTXT_SRC_CH_IRQ_MSK]		= &reg_cntxt_src_ch_irq_msk,
	[CNTXT_SRC_EV_CH_IRQ_MSK]	= &reg_cntxt_src_ev_ch_irq_msk,
	[CNTXT_SRC_CH_IRQ_CLR]		= &reg_cntxt_src_ch_irq_clr,
	[CNTXT_SRC_EV_CH_IRQ_CLR]	= &reg_cntxt_src_ev_ch_irq_clr,
	[CNTXT_SRC_IEOB_IRQ]		= &reg_cntxt_src_ieob_irq,
	[CNTXT_SRC_IEOB_IRQ_MSK]	= &reg_cntxt_src_ieob_irq_msk,
	[CNTXT_SRC_IEOB_IRQ_CLR]	= &reg_cntxt_src_ieob_irq_clr,
	[CNTXT_GLOB_IRQ_STTS]		= &reg_cntxt_glob_irq_stts,
	[CNTXT_GLOB_IRQ_EN]		= &reg_cntxt_glob_irq_en,
	[CNTXT_GLOB_IRQ_CLR]		= &reg_cntxt_glob_irq_clr,
	[CNTXT_GSI_IRQ_STTS]		= &reg_cntxt_gsi_irq_stts,
	[CNTXT_GSI_IRQ_EN]		= &reg_cntxt_gsi_irq_en,
	[CNTXT_GSI_IRQ_CLR]		= &reg_cntxt_gsi_irq_clr,
	[CNTXT_INTSET]			= &reg_cntxt_intset,
	[ERROR_LOG]			= &reg_error_log,
	[ERROR_LOG_CLR]			= &reg_error_log_clr,
	[CNTXT_SCRATCH_0]		= &reg_cntxt_scratch_0,
};

const struct regs gsi_regs_v3_5_1 = {
	.reg_count	= ARRAY_SIZE(reg_array),
	.reg		= reg_array,
};
Commit	Line	Data
465d1bc9 AE	1	// SPDX-License-Identifier: GPL-2.0
	2
	3	/* Copyright (C) 2023 Linaro Ltd. */
	4
	5	#include <linux/types.h>
	6
	7	#include "../gsi.h"
	8	#include "../reg.h"
	9	#include "../gsi_reg.h"
	10
465d1bc9 AE	11	REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
	12	0x0000c020 + 0x1000 * GSI_EE_AP);
	13
	14	REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
	15	0x0000c024 + 0x1000 * GSI_EE_AP);
	16
330ce9d3 AE	17	static const u32 reg_ch_c_cntxt_0_fmask[] = {
	18	[CHTYPE_PROTOCOL] = GENMASK(2, 0),
	19	[CHTYPE_DIR] = BIT(3),
	20	[CH_EE] = GENMASK(7, 4),
	21	[CHID] = GENMASK(12, 8),
	22	/* Bit 13 reserved */
	23	[ERINDEX] = GENMASK(18, 14),
	24	/* Bit 19 reserved */
	25	[CHSTATE] = GENMASK(23, 20),
	26	[ELEMENT_SIZE] = GENMASK(31, 24),
	27	};
	28
	29	REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
	30	0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
	31
	32	static const u32 reg_ch_c_cntxt_1_fmask[] = {
	33	[CH_R_LENGTH] = GENMASK(15, 0),
	34	/* Bits 16-31 reserved */
	35	};
465d1bc9	36
330ce9d3 AE	37	REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
330ce9d3 AE	38	0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
465d1bc9 AE	39
	40	REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
	41
	42	REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
	43
f50ca7ce AE	44	static const u32 reg_ch_c_qos_fmask[] = {
	45	[WRR_WEIGHT] = GENMASK(3, 0),
	46	/* Bits 4-7 reserved */
	47	[MAX_PREFETCH] = BIT(8),
	48	[USE_DB_ENG] = BIT(9),
	49	/* Bits 10-31 reserved */
	50	};
	51
	52	REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
465d1bc9	53
3f3741c9 AE	54	static const u32 reg_error_log_fmask[] = {
	55	[ERR_ARG3] = GENMASK(3, 0),
	56	[ERR_ARG2] = GENMASK(7, 4),
	57	[ERR_ARG1] = GENMASK(11, 8),
	58	[ERR_CODE] = GENMASK(15, 12),
	59	/* Bits 16-18 reserved */
	60	[ERR_VIRT_IDX] = GENMASK(23, 19),
	61	[ERR_TYPE] = GENMASK(27, 24),
	62	[ERR_EE] = GENMASK(31, 28),
	63	};
	64
465d1bc9 AE	65	REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
	66	0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
	67
	68	REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
	69	0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
	70
	71	REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
	72	0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
	73
	74	REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
	75	0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
	76
edc6158b AE	77	static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
	78	[EV_CHTYPE] = GENMASK(3, 0),
	79	[EV_EE] = GENMASK(7, 4),
	80	[EV_EVCHID] = GENMASK(15, 8),
	81	[EV_INTYPE] = BIT(16),
	82	/* Bits 17-19 reserved */
	83	[EV_CHSTATE] = GENMASK(23, 20),
	84	[EV_ELEMENT_SIZE] = GENMASK(31, 24),
	85	};
	86
	87	REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
	88	0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
465d1bc9 AE	89
	90	REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
	91	0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
	92
	93	REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
	94	0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
	95
	96	REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
	97	0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
	98
	99	REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
	100	0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
	101
edc6158b AE	102	static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
	103	[EV_MODT] = GENMASK(15, 0),
	104	[EV_MODC] = GENMASK(23, 16),
	105	[EV_MOD_CNT] = GENMASK(31, 24),
	106	};
	107
	108	REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
	109	0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
465d1bc9 AE	110
	111	REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
	112	0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
	113
	114	REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
	115	0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
	116
	117	REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
	118	0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
	119
	120	REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
	121	0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
	122
	123	REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
	124	0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
	125
	126	REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
	127	0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
	128
	129	REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
	130	0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
	131
	132	REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
	133	0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
	134
	135	REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
	136	0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
	137
3f3741c9 AE	138	static const u32 reg_gsi_status_fmask[] = {
	139	[ENABLED] = BIT(0),
	140	/* Bits 1-31 reserved */
	141	};
	142
	143	REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);
	144
	145	static const u32 reg_ch_cmd_fmask[] = {
	146	[CH_CHID] = GENMASK(7, 0),
59b12b1d	147	/* Bits 8-23 reserved */
3f3741c9 AE	148	[CH_OPCODE] = GENMASK(31, 24),
	149	};
	150
	151	REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);
	152
	153	static const u32 reg_ev_ch_cmd_fmask[] = {
	154	[EV_CHID] = GENMASK(7, 0),
59b12b1d	155	/* Bits 8-23 reserved */
3f3741c9 AE	156	[EV_OPCODE] = GENMASK(31, 24),
	157	};
	158
	159	REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);
5791a73c	160
3f3741c9 AE	161	static const u32 reg_generic_cmd_fmask[] = {
	162	[GENERIC_OPCODE] = GENMASK(4, 0),
	163	[GENERIC_CHID] = GENMASK(9, 5),
	164	[GENERIC_EE] = GENMASK(13, 10),
	165	/* Bits 14-31 reserved */
	166	};
5791a73c	167
3f3741c9	168	REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);
5791a73c	169
3f3741c9 AE	170	static const u32 reg_hw_param_2_fmask[] = {
	171	[IRAM_SIZE] = GENMASK(2, 0),
	172	[NUM_CH_PER_EE] = GENMASK(7, 3),
	173	[NUM_EV_PER_EE] = GENMASK(12, 8),
	174	[GSI_CH_PEND_TRANSLATE] = BIT(13),
	175	[GSI_CH_FULL_LOGIC] = BIT(14),
	176	/* Bits 15-31 reserved */
	177	};
5791a73c	178
3f3741c9	179	REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP);
5791a73c	180
465d1bc9 AE	181	REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
	182
	183	REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
	184
	185	REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
	186
	187	REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
	188
	189	REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
	190	0x0001f098 + 0x4000 * GSI_EE_AP);
	191
	192	REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
	193	0x0001f09c + 0x4000 * GSI_EE_AP);
	194
	195	REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
	196	0x0001f0a0 + 0x4000 * GSI_EE_AP);
	197
	198	REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
	199	0x0001f0a4 + 0x4000 * GSI_EE_AP);
	200
	201	REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
	202
	203	REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
	204	0x0001f0b8 + 0x4000 * GSI_EE_AP);
	205
	206	REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
	207	0x0001f0c0 + 0x4000 * GSI_EE_AP);
	208
	209	REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
	210
	211	REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
	212
	213	REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
	214
	215	REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
	216
	217	REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
	218
	219	REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
	220
3f3741c9 AE	221	static const u32 reg_cntxt_intset_fmask[] = {
	222	[INTYPE] = BIT(0)
	223	/* Bits 1-31 reserved */
	224	};
	225
	226	REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
	227
59b12b1d AE	228	REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);
	229
	230	REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
	231
3f3741c9 AE	232	static const u32 reg_cntxt_scratch_0_fmask[] = {
	233	[INTER_EE_RESULT] = GENMASK(2, 0),
	234	/* Bits 3-4 reserved */
	235	[GENERIC_EE_RESULT] = GENMASK(7, 5),
	236	/* Bits 8-31 reserved */
	237	};
465d1bc9	238
3f3741c9	239	REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
465d1bc9 AE	240
	241	static const struct reg *reg_array[] = {
	242	[INTER_EE_SRC_CH_IRQ_MSK] = &reg_inter_ee_src_ch_irq_msk,
	243	[INTER_EE_SRC_EV_CH_IRQ_MSK] = &reg_inter_ee_src_ev_ch_irq_msk,
	244	[CH_C_CNTXT_0] = &reg_ch_c_cntxt_0,
	245	[CH_C_CNTXT_1] = &reg_ch_c_cntxt_1,
	246	[CH_C_CNTXT_2] = &reg_ch_c_cntxt_2,
	247	[CH_C_CNTXT_3] = &reg_ch_c_cntxt_3,
	248	[CH_C_QOS] = &reg_ch_c_qos,
	249	[CH_C_SCRATCH_0] = &reg_ch_c_scratch_0,
	250	[CH_C_SCRATCH_1] = &reg_ch_c_scratch_1,
	251	[CH_C_SCRATCH_2] = &reg_ch_c_scratch_2,
	252	[CH_C_SCRATCH_3] = &reg_ch_c_scratch_3,
	253	[EV_CH_E_CNTXT_0] = &reg_ev_ch_e_cntxt_0,
	254	[EV_CH_E_CNTXT_1] = &reg_ev_ch_e_cntxt_1,
	255	[EV_CH_E_CNTXT_2] = &reg_ev_ch_e_cntxt_2,
	256	[EV_CH_E_CNTXT_3] = &reg_ev_ch_e_cntxt_3,
	257	[EV_CH_E_CNTXT_4] = &reg_ev_ch_e_cntxt_4,
	258	[EV_CH_E_CNTXT_8] = &reg_ev_ch_e_cntxt_8,
	259	[EV_CH_E_CNTXT_9] = &reg_ev_ch_e_cntxt_9,
	260	[EV_CH_E_CNTXT_10] = &reg_ev_ch_e_cntxt_10,
	261	[EV_CH_E_CNTXT_11] = &reg_ev_ch_e_cntxt_11,
	262	[EV_CH_E_CNTXT_12] = &reg_ev_ch_e_cntxt_12,
	263	[EV_CH_E_CNTXT_13] = &reg_ev_ch_e_cntxt_13,
	264	[EV_CH_E_SCRATCH_0] = &reg_ev_ch_e_scratch_0,
	265	[EV_CH_E_SCRATCH_1] = &reg_ev_ch_e_scratch_1,
	266	[CH_C_DOORBELL_0] = &reg_ch_c_doorbell_0,
	267	[EV_CH_E_DOORBELL_0] = &reg_ev_ch_e_doorbell_0,
5791a73c AE	268	[GSI_STATUS] = &reg_gsi_status,
	269	[CH_CMD] = &reg_ch_cmd,
	270	[EV_CH_CMD] = &reg_ev_ch_cmd,
	271	[GENERIC_CMD] = &reg_generic_cmd,
	272	[HW_PARAM_2] = &reg_hw_param_2,
465d1bc9 AE	273	[CNTXT_TYPE_IRQ] = &reg_cntxt_type_irq,
	274	[CNTXT_TYPE_IRQ_MSK] = &reg_cntxt_type_irq_msk,
	275	[CNTXT_SRC_CH_IRQ] = &reg_cntxt_src_ch_irq,
	276	[CNTXT_SRC_EV_CH_IRQ] = &reg_cntxt_src_ev_ch_irq,
	277	[CNTXT_SRC_CH_IRQ_MSK] = &reg_cntxt_src_ch_irq_msk,
	278	[CNTXT_SRC_EV_CH_IRQ_MSK] = &reg_cntxt_src_ev_ch_irq_msk,
	279	[CNTXT_SRC_CH_IRQ_CLR] = &reg_cntxt_src_ch_irq_clr,
	280	[CNTXT_SRC_EV_CH_IRQ_CLR] = &reg_cntxt_src_ev_ch_irq_clr,
	281	[CNTXT_SRC_IEOB_IRQ] = &reg_cntxt_src_ieob_irq,
	282	[CNTXT_SRC_IEOB_IRQ_MSK] = &reg_cntxt_src_ieob_irq_msk,
	283	[CNTXT_SRC_IEOB_IRQ_CLR] = &reg_cntxt_src_ieob_irq_clr,
	284	[CNTXT_GLOB_IRQ_STTS] = &reg_cntxt_glob_irq_stts,
	285	[CNTXT_GLOB_IRQ_EN] = &reg_cntxt_glob_irq_en,
	286	[CNTXT_GLOB_IRQ_CLR] = &reg_cntxt_glob_irq_clr,
	287	[CNTXT_GSI_IRQ_STTS] = &reg_cntxt_gsi_irq_stts,
	288	[CNTXT_GSI_IRQ_EN] = &reg_cntxt_gsi_irq_en,
	289	[CNTXT_GSI_IRQ_CLR] = &reg_cntxt_gsi_irq_clr,
	290	[CNTXT_INTSET] = &reg_cntxt_intset,
5791a73c AE	291	[ERROR_LOG] = &reg_error_log,
5791a73c AE	292	[ERROR_LOG_CLR] = &reg_error_log_clr,
465d1bc9 AE	293	[CNTXT_SCRATCH_0] = &reg_cntxt_scratch_0,
	294	};
	295
	296	const struct regs gsi_regs_v3_5_1 = {
	297	.reg_count = ARRAY_SIZE(reg_array),
	298	.reg = reg_array,
	299	};