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2b9feef2 AE |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | ||
3 | /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. | |
8e7c89d8 | 4 | * Copyright (C) 2018-2023 Linaro Ltd. |
2b9feef2 AE |
5 | */ |
6 | ||
7 | #include <linux/types.h> | |
8 | #include <linux/kernel.h> | |
9 | #include <linux/bits.h> | |
10 | #include <linux/bitops.h> | |
11 | #include <linux/bitfield.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/build_bug.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | ||
17 | #include "ipa.h" | |
18 | #include "ipa_version.h" | |
19 | #include "ipa_endpoint.h" | |
20 | #include "ipa_table.h" | |
21 | #include "ipa_reg.h" | |
22 | #include "ipa_mem.h" | |
23 | #include "ipa_cmd.h" | |
24 | #include "gsi.h" | |
25 | #include "gsi_trans.h" | |
26 | ||
27 | /** | |
28 | * DOC: IPA Filter and Route Tables | |
29 | * | |
4ea29143 AE |
30 | * The IPA has tables defined in its local (IPA-resident) memory that define |
31 | * filter and routing rules. An entry in either of these tables is a little | |
32 | * endian 64-bit "slot" that holds the address of a rule definition. (The | |
33 | * size of these slots is 64 bits regardless of the host DMA address size.) | |
34 | * | |
bd552493 AE |
35 | * Separate tables (both filter and route) are used for IPv4 and IPv6. There |
36 | * is normally another set of "hashed" filter and route tables, which are | |
4ea29143 AE |
37 | * used with a hash of message metadata. Hashed operation is not supported |
38 | * by all IPA hardware (IPA v4.2 doesn't support hashed tables). | |
39 | * | |
40 | * Rules can be in local memory or in DRAM (system memory). The offset of | |
41 | * an object (such as a route or filter table) in IPA-resident memory must | |
42 | * 128-byte aligned. An object in system memory (such as a route or filter | |
43 | * rule) must be at an 8-byte aligned address. We currently only place | |
44 | * route or filter rules in system memory. | |
45 | * | |
2b9feef2 AE |
46 | * A rule consists of a contiguous block of 32-bit values terminated with |
47 | * 32 zero bits. A special "zero entry" rule consisting of 64 zero bits | |
48 | * represents "no filtering" or "no routing," and is the reset value for | |
4ea29143 | 49 | * filter or route table rules. |
2b9feef2 AE |
50 | * |
51 | * Each filter rule is associated with an AP or modem TX endpoint, though | |
4ea29143 | 52 | * not all TX endpoints support filtering. The first 64-bit slot in a |
2b9feef2 | 53 | * filter table is a bitmap indicating which endpoints have entries in |
bd552493 AE |
54 | * the table. Each set bit in this bitmap indicates the presence of the |
55 | * address of a filter rule in the memory following the bitmap. Until IPA | |
56 | * v5.0, the low-order bit (bit 0) in this bitmap represents a special | |
57 | * global filter, which applies to all traffic. Otherwise the position of | |
58 | * each set bit represents an endpoint for which a filter rule is defined. | |
59 | * | |
60 | * The global rule is not used in current code, and support for it is | |
61 | * removed starting at IPA v5.0. For IPA v5.0+, the endpoint bitmap | |
62 | * position defines the endpoint ID--i.e. if bit 1 is set in the endpoint | |
63 | * bitmap, endpoint 1 has a filter rule. Older versions of IPA represent | |
64 | * the presence of a filter rule for endpoint X by bit (X + 1) being set. | |
65 | * I.e., bit 1 set indicates the presence of a filter rule for endpoint 0, | |
66 | * and bit 3 set means there is a filter rule present for endpoint 2. | |
67 | * | |
68 | * Each filter table entry has the address of a set of equations that | |
69 | * implement a filter rule. So following the endpoint bitmap there | |
70 | * will be such an address/entry for each endpoint with a set bit in | |
71 | * the bitmap. | |
2b9feef2 AE |
72 | * |
73 | * The AP initializes all entries in a filter table to refer to a "zero" | |
bd552493 AE |
74 | * rule. Once initialized, the modem and AP update the entries for |
75 | * endpoints they "own" directly. Currently the AP does not use the IPA | |
76 | * filtering functionality. | |
77 | * | |
78 | * This diagram shows an example of a filter table with an endpoint | |
79 | * bitmap as defined prior to IPA v5.0. | |
2b9feef2 AE |
80 | * |
81 | * IPA Filter Table | |
82 | * ---------------------- | |
83 | * endpoint bitmap | 0x0000000000000048 | Bits 3 and 6 set (endpoints 2 and 5) | |
84 | * |--------------------| | |
85 | * 1st endpoint | 0x000123456789abc0 | DMA address for modem endpoint 2 rule | |
86 | * |--------------------| | |
87 | * 2nd endpoint | 0x000123456789abf0 | DMA address for AP endpoint 5 rule | |
88 | * |--------------------| | |
89 | * (unused) | | (Unused space in filter table) | |
90 | * |--------------------| | |
91 | * . . . | |
92 | * |--------------------| | |
93 | * (unused) | | (Unused space in filter table) | |
94 | * ---------------------- | |
95 | * | |
96 | * The set of available route rules is divided about equally between the AP | |
97 | * and modem. The AP initializes all entries in a route table to refer to | |
98 | * a "zero entry". Once initialized, the modem and AP are responsible for | |
99 | * updating their own entries. All entries in a route table are usable, | |
100 | * though the AP currently does not use the IPA routing functionality. | |
101 | * | |
102 | * IPA Route Table | |
103 | * ---------------------- | |
104 | * 1st modem route | 0x0001234500001100 | DMA address for first route rule | |
105 | * |--------------------| | |
106 | * 2nd modem route | 0x0001234500001140 | DMA address for second route rule | |
107 | * |--------------------| | |
108 | * . . . | |
109 | * |--------------------| | |
110 | * Last modem route| 0x0001234500002280 | DMA address for Nth route rule | |
111 | * |--------------------| | |
112 | * 1st AP route | 0x0001234500001100 | DMA address for route rule (N+1) | |
113 | * |--------------------| | |
114 | * 2nd AP route | 0x0001234500001140 | DMA address for next route rule | |
115 | * |--------------------| | |
116 | * . . . | |
117 | * |--------------------| | |
118 | * Last AP route | 0x0001234500002280 | DMA address for last route rule | |
119 | * ---------------------- | |
120 | */ | |
121 | ||
2b9feef2 AE |
122 | /* Filter or route rules consist of a set of 32-bit values followed by a |
123 | * 32-bit all-zero rule list terminator. The "zero rule" is simply an | |
124 | * all-zero rule followed by the list terminator. | |
125 | */ | |
126 | #define IPA_ZERO_RULE_SIZE (2 * sizeof(__le32)) | |
127 | ||
2b9feef2 AE |
128 | /* Check things that can be validated at build time. */ |
129 | static void ipa_table_validate_build(void) | |
130 | { | |
d2fd2311 AE |
131 | /* Filter and route tables contain DMA addresses that refer |
132 | * to filter or route rules. But the size of a table entry | |
133 | * is 64 bits regardless of what the size of an AP DMA address | |
134 | * is. A fixed constant defines the size of an entry, and | |
135 | * code in ipa_table_init() uses a pointer to __le64 to | |
136 | * initialize tables. | |
2b9feef2 | 137 | */ |
4ea29143 | 138 | BUILD_BUG_ON(sizeof(dma_addr_t) > sizeof(__le64)); |
2b9feef2 AE |
139 | |
140 | /* A "zero rule" is used to represent no filtering or no routing. | |
141 | * It is a 64-bit block of zeroed memory. Code in ipa_table_init() | |
142 | * assumes that it can be written using a pointer to __le64. | |
143 | */ | |
144 | BUILD_BUG_ON(IPA_ZERO_RULE_SIZE != sizeof(__le64)); | |
cf139196 | 145 | } |
2b9feef2 | 146 | |
cf139196 AE |
147 | static const struct ipa_mem * |
148 | ipa_table_mem(struct ipa *ipa, bool filter, bool hashed, bool ipv6) | |
149 | { | |
150 | enum ipa_mem_id mem_id; | |
151 | ||
152 | mem_id = filter ? hashed ? ipv6 ? IPA_MEM_V6_FILTER_HASHED | |
153 | : IPA_MEM_V4_FILTER_HASHED | |
154 | : ipv6 ? IPA_MEM_V6_FILTER | |
155 | : IPA_MEM_V4_FILTER | |
156 | : hashed ? ipv6 ? IPA_MEM_V6_ROUTE_HASHED | |
157 | : IPA_MEM_V4_ROUTE_HASHED | |
158 | : ipv6 ? IPA_MEM_V6_ROUTE | |
159 | : IPA_MEM_V4_ROUTE; | |
160 | ||
161 | return ipa_mem_find(ipa, mem_id); | |
2b9feef2 AE |
162 | } |
163 | ||
0f97fbd4 | 164 | bool ipa_filtered_valid(struct ipa *ipa, u64 filtered) |
2b9feef2 AE |
165 | { |
166 | struct device *dev = &ipa->pdev->dev; | |
167 | u32 count; | |
168 | ||
0f97fbd4 | 169 | if (!filtered) { |
2b9feef2 AE |
170 | dev_err(dev, "at least one filtering endpoint is required\n"); |
171 | ||
172 | return false; | |
173 | } | |
174 | ||
0f97fbd4 | 175 | count = hweight64(filtered); |
f787d848 | 176 | if (count > ipa->filter_count) { |
0f97fbd4 | 177 | dev_err(dev, "too many filtering endpoints (%u > %u)\n", |
f787d848 | 178 | count, ipa->filter_count); |
2b9feef2 AE |
179 | |
180 | return false; | |
181 | } | |
182 | ||
183 | return true; | |
184 | } | |
185 | ||
2b9feef2 AE |
186 | /* Zero entry count means no table, so just return a 0 address */ |
187 | static dma_addr_t ipa_table_addr(struct ipa *ipa, bool filter_mask, u16 count) | |
188 | { | |
189 | u32 skip; | |
190 | ||
191 | if (!count) | |
192 | return 0; | |
193 | ||
f787d848 | 194 | WARN_ON(count > max_t(u32, ipa->filter_count, ipa->route_count)); |
2b9feef2 AE |
195 | |
196 | /* Skip over the zero rule and possibly the filter mask */ | |
197 | skip = filter_mask ? 1 : 2; | |
198 | ||
199 | return ipa->table_addr + skip * sizeof(*ipa->table_virt); | |
200 | } | |
201 | ||
202 | static void ipa_table_reset_add(struct gsi_trans *trans, bool filter, | |
6337b147 | 203 | bool hashed, bool ipv6, u16 first, u16 count) |
2b9feef2 AE |
204 | { |
205 | struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); | |
6337b147 | 206 | const struct ipa_mem *mem; |
2b9feef2 AE |
207 | dma_addr_t addr; |
208 | u32 offset; | |
209 | u16 size; | |
210 | ||
6337b147 AE |
211 | /* Nothing to do if the memory region is doesn't exist or is empty */ |
212 | mem = ipa_table_mem(ipa, filter, hashed, ipv6); | |
213 | if (!mem || !mem->size) | |
2b9feef2 AE |
214 | return; |
215 | ||
216 | if (filter) | |
217 | first++; /* skip over bitmap */ | |
218 | ||
4ea29143 AE |
219 | offset = mem->offset + first * sizeof(__le64); |
220 | size = count * sizeof(__le64); | |
2b9feef2 AE |
221 | addr = ipa_table_addr(ipa, false, count); |
222 | ||
223 | ipa_cmd_dma_shared_mem_add(trans, offset, size, addr, true); | |
224 | } | |
225 | ||
226 | /* Reset entries in a single filter table belonging to either the AP or | |
227 | * modem to refer to the zero entry. The memory region supplied will be | |
228 | * for the IPv4 and IPv6 non-hashed and hashed filter tables. | |
229 | */ | |
230 | static int | |
6337b147 | 231 | ipa_filter_reset_table(struct ipa *ipa, bool hashed, bool ipv6, bool modem) |
2b9feef2 | 232 | { |
0f97fbd4 | 233 | u64 ep_mask = ipa->filtered; |
2b9feef2 AE |
234 | struct gsi_trans *trans; |
235 | enum gsi_ee_id ee_id; | |
236 | ||
0f97fbd4 | 237 | trans = ipa_cmd_trans_alloc(ipa, hweight64(ep_mask)); |
2b9feef2 AE |
238 | if (!trans) { |
239 | dev_err(&ipa->pdev->dev, | |
240 | "no transaction for %s filter reset\n", | |
241 | modem ? "modem" : "AP"); | |
242 | return -EBUSY; | |
243 | } | |
244 | ||
245 | ee_id = modem ? GSI_EE_MODEM : GSI_EE_AP; | |
246 | while (ep_mask) { | |
247 | u32 endpoint_id = __ffs(ep_mask); | |
248 | struct ipa_endpoint *endpoint; | |
249 | ||
250 | ep_mask ^= BIT(endpoint_id); | |
251 | ||
252 | endpoint = &ipa->endpoint[endpoint_id]; | |
253 | if (endpoint->ee_id != ee_id) | |
254 | continue; | |
255 | ||
6337b147 | 256 | ipa_table_reset_add(trans, true, hashed, ipv6, endpoint_id, 1); |
2b9feef2 AE |
257 | } |
258 | ||
259 | gsi_trans_commit_wait(trans); | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | /* Theoretically, each filter table could have more filter slots to | |
265 | * update than the maximum number of commands in a transaction. So | |
266 | * we do each table separately. | |
267 | */ | |
268 | static int ipa_filter_reset(struct ipa *ipa, bool modem) | |
269 | { | |
270 | int ret; | |
271 | ||
6337b147 | 272 | ret = ipa_filter_reset_table(ipa, false, false, modem); |
2b9feef2 AE |
273 | if (ret) |
274 | return ret; | |
275 | ||
6337b147 | 276 | ret = ipa_filter_reset_table(ipa, true, false, modem); |
2b9feef2 AE |
277 | if (ret) |
278 | return ret; | |
279 | ||
6337b147 | 280 | ret = ipa_filter_reset_table(ipa, false, true, modem); |
2b9feef2 AE |
281 | if (ret) |
282 | return ret; | |
6337b147 | 283 | ret = ipa_filter_reset_table(ipa, true, true, modem); |
2b9feef2 AE |
284 | |
285 | return ret; | |
286 | } | |
287 | ||
288 | /* The AP routes and modem routes are each contiguous within the | |
289 | * table. We can update each table with a single command, and we | |
290 | * won't exceed the per-transaction command limit. | |
291 | * */ | |
292 | static int ipa_route_reset(struct ipa *ipa, bool modem) | |
293 | { | |
8defab8b | 294 | u32 modem_route_count = ipa->modem_route_count; |
2b9feef2 AE |
295 | struct gsi_trans *trans; |
296 | u16 first; | |
297 | u16 count; | |
298 | ||
299 | trans = ipa_cmd_trans_alloc(ipa, 4); | |
300 | if (!trans) { | |
301 | dev_err(&ipa->pdev->dev, | |
302 | "no transaction for %s route reset\n", | |
303 | modem ? "modem" : "AP"); | |
304 | return -EBUSY; | |
305 | } | |
306 | ||
307 | if (modem) { | |
fb4014ac | 308 | first = 0; |
8defab8b | 309 | count = modem_route_count; |
2b9feef2 | 310 | } else { |
8defab8b AE |
311 | first = modem_route_count; |
312 | count = ipa->route_count - modem_route_count; | |
2b9feef2 AE |
313 | } |
314 | ||
6337b147 AE |
315 | ipa_table_reset_add(trans, false, false, false, first, count); |
316 | ipa_table_reset_add(trans, false, true, false, first, count); | |
2b9feef2 | 317 | |
6337b147 AE |
318 | ipa_table_reset_add(trans, false, false, true, first, count); |
319 | ipa_table_reset_add(trans, false, true, true, first, count); | |
2b9feef2 AE |
320 | |
321 | gsi_trans_commit_wait(trans); | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
326 | void ipa_table_reset(struct ipa *ipa, bool modem) | |
327 | { | |
328 | struct device *dev = &ipa->pdev->dev; | |
329 | const char *ee_name; | |
330 | int ret; | |
331 | ||
332 | ee_name = modem ? "modem" : "AP"; | |
333 | ||
334 | /* Report errors, but reset filter and route tables */ | |
335 | ret = ipa_filter_reset(ipa, modem); | |
336 | if (ret) | |
337 | dev_err(dev, "error %d resetting filter table for %s\n", | |
338 | ret, ee_name); | |
339 | ||
340 | ret = ipa_route_reset(ipa, modem); | |
341 | if (ret) | |
342 | dev_err(dev, "error %d resetting route table for %s\n", | |
343 | ret, ee_name); | |
344 | } | |
345 | ||
346 | int ipa_table_hash_flush(struct ipa *ipa) | |
347 | { | |
2b9feef2 | 348 | struct gsi_trans *trans; |
81772e44 | 349 | const struct reg *reg; |
6a244b75 | 350 | u32 offset; |
2b9feef2 AE |
351 | u32 val; |
352 | ||
a266ad6b | 353 | if (!ipa_table_hash_support(ipa)) |
2b9feef2 AE |
354 | return 0; |
355 | ||
356 | trans = ipa_cmd_trans_alloc(ipa, 1); | |
357 | if (!trans) { | |
358 | dev_err(&ipa->pdev->dev, "no transaction for hash flush\n"); | |
359 | return -EBUSY; | |
360 | } | |
361 | ||
8e7c89d8 AE |
362 | if (ipa->version < IPA_VERSION_5_0) { |
363 | reg = ipa_reg(ipa, FILT_ROUT_HASH_FLUSH); | |
364 | offset = ipa_reg_offset(reg); | |
6a244b75 | 365 | |
8e7c89d8 AE |
366 | val = ipa_reg_bit(reg, IPV6_ROUTER_HASH); |
367 | val |= ipa_reg_bit(reg, IPV6_FILTER_HASH); | |
368 | val |= ipa_reg_bit(reg, IPV4_ROUTER_HASH); | |
369 | val |= ipa_reg_bit(reg, IPV4_FILTER_HASH); | |
370 | } else { | |
371 | reg = ipa_reg(ipa, FILT_ROUT_CACHE_FLUSH); | |
372 | offset = ipa_reg_offset(reg); | |
373 | ||
374 | /* IPA v5.0+ uses a unified cache (both IPv4 and IPv6) */ | |
375 | val = ipa_reg_bit(reg, ROUTER_CACHE); | |
376 | val |= ipa_reg_bit(reg, FILTER_CACHE); | |
377 | } | |
2b9feef2 AE |
378 | |
379 | ipa_cmd_register_write_add(trans, offset, val, val, false); | |
380 | ||
381 | gsi_trans_commit_wait(trans); | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
5cb76899 | 386 | static void ipa_table_init_add(struct gsi_trans *trans, bool filter, bool ipv6) |
2b9feef2 AE |
387 | { |
388 | struct ipa *ipa = container_of(trans->gsi, struct ipa, gsi); | |
5cb76899 AE |
389 | const struct ipa_mem *hash_mem; |
390 | enum ipa_cmd_opcode opcode; | |
391 | const struct ipa_mem *mem; | |
2b9feef2 AE |
392 | dma_addr_t hash_addr; |
393 | dma_addr_t addr; | |
15b4f993 | 394 | u32 hash_offset; |
dc901505 | 395 | u32 zero_offset; |
2b9feef2 | 396 | u16 hash_count; |
dc901505 | 397 | u32 zero_size; |
2b9feef2 AE |
398 | u16 hash_size; |
399 | u16 count; | |
400 | u16 size; | |
401 | ||
5cb76899 AE |
402 | opcode = filter ? ipv6 ? IPA_CMD_IP_V6_FILTER_INIT |
403 | : IPA_CMD_IP_V4_FILTER_INIT | |
404 | : ipv6 ? IPA_CMD_IP_V6_ROUTING_INIT | |
405 | : IPA_CMD_IP_V4_ROUTING_INIT; | |
406 | ||
15b4f993 | 407 | /* The non-hashed region will exist (see ipa_table_mem_valid()) */ |
5cb76899 AE |
408 | mem = ipa_table_mem(ipa, filter, false, ipv6); |
409 | hash_mem = ipa_table_mem(ipa, filter, true, ipv6); | |
15b4f993 | 410 | hash_offset = hash_mem ? hash_mem->offset : 0; |
5cb76899 | 411 | |
dc901505 | 412 | /* Compute the number of table entries to initialize */ |
2b9feef2 | 413 | if (filter) { |
dc901505 AE |
414 | /* The number of filtering endpoints determines number of |
415 | * entries in the filter table; we also add one more "slot" | |
416 | * to hold the bitmap itself. The size of the hashed filter | |
417 | * table is either the same as the non-hashed one, or zero. | |
418 | */ | |
0f97fbd4 | 419 | count = 1 + hweight64(ipa->filtered); |
5cb76899 | 420 | hash_count = hash_mem && hash_mem->size ? count : 0; |
2b9feef2 | 421 | } else { |
dc901505 AE |
422 | /* The size of a route table region determines the number |
423 | * of entries it has. | |
424 | */ | |
4ea29143 | 425 | count = mem->size / sizeof(__le64); |
15b4f993 | 426 | hash_count = hash_mem ? hash_mem->size / sizeof(__le64) : 0; |
2b9feef2 | 427 | } |
4ea29143 AE |
428 | size = count * sizeof(__le64); |
429 | hash_size = hash_count * sizeof(__le64); | |
2b9feef2 AE |
430 | |
431 | addr = ipa_table_addr(ipa, filter, count); | |
432 | hash_addr = ipa_table_addr(ipa, filter, hash_count); | |
433 | ||
434 | ipa_cmd_table_init_add(trans, opcode, size, mem->offset, addr, | |
15b4f993 | 435 | hash_size, hash_offset, hash_addr); |
dc901505 AE |
436 | if (!filter) |
437 | return; | |
438 | ||
439 | /* Zero the unused space in the filter table */ | |
440 | zero_offset = mem->offset + size; | |
441 | zero_size = mem->size - size; | |
442 | ipa_cmd_dma_shared_mem_add(trans, zero_offset, zero_size, | |
443 | ipa->zero_addr, true); | |
444 | if (!hash_size) | |
445 | return; | |
446 | ||
447 | /* Zero the unused space in the hashed filter table */ | |
15b4f993 | 448 | zero_offset = hash_offset + hash_size; |
dc901505 AE |
449 | zero_size = hash_mem->size - hash_size; |
450 | ipa_cmd_dma_shared_mem_add(trans, zero_offset, zero_size, | |
451 | ipa->zero_addr, true); | |
2b9feef2 AE |
452 | } |
453 | ||
454 | int ipa_table_setup(struct ipa *ipa) | |
455 | { | |
456 | struct gsi_trans *trans; | |
457 | ||
dc901505 AE |
458 | /* We will need at most 8 TREs: |
459 | * - IPv4: | |
460 | * - One for route table initialization (non-hashed and hashed) | |
461 | * - One for filter table initialization (non-hashed and hashed) | |
462 | * - One to zero unused entries in the non-hashed filter table | |
463 | * - One to zero unused entries in the hashed filter table | |
464 | * - IPv6: | |
465 | * - One for route table initialization (non-hashed and hashed) | |
466 | * - One for filter table initialization (non-hashed and hashed) | |
467 | * - One to zero unused entries in the non-hashed filter table | |
468 | * - One to zero unused entries in the hashed filter table | |
469 | * All platforms support at least 8 TREs in a transaction. | |
470 | */ | |
471 | trans = ipa_cmd_trans_alloc(ipa, 8); | |
2b9feef2 AE |
472 | if (!trans) { |
473 | dev_err(&ipa->pdev->dev, "no transaction for table setup\n"); | |
474 | return -EBUSY; | |
475 | } | |
476 | ||
5cb76899 AE |
477 | ipa_table_init_add(trans, false, false); |
478 | ipa_table_init_add(trans, false, true); | |
479 | ipa_table_init_add(trans, true, false); | |
480 | ipa_table_init_add(trans, true, true); | |
2b9feef2 AE |
481 | |
482 | gsi_trans_commit_wait(trans); | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
2b9feef2 AE |
487 | /** |
488 | * ipa_filter_tuple_zero() - Zero an endpoint's hashed filter tuple | |
e3eea08e | 489 | * @endpoint: Endpoint whose filter hash tuple should be zeroed |
2b9feef2 AE |
490 | * |
491 | * Endpoint must be for the AP (not modem) and support filtering. Updates | |
492 | * the filter hash values without changing route ones. | |
493 | */ | |
494 | static void ipa_filter_tuple_zero(struct ipa_endpoint *endpoint) | |
495 | { | |
496 | u32 endpoint_id = endpoint->endpoint_id; | |
6bfb7538 | 497 | struct ipa *ipa = endpoint->ipa; |
81772e44 | 498 | const struct reg *reg; |
2b9feef2 AE |
499 | u32 offset; |
500 | u32 val; | |
501 | ||
a08cedc3 AE |
502 | if (ipa->version < IPA_VERSION_5_0) { |
503 | reg = ipa_reg(ipa, ENDP_FILTER_ROUTER_HSH_CFG); | |
504 | ||
505 | offset = ipa_reg_n_offset(reg, endpoint_id); | |
506 | val = ioread32(endpoint->ipa->reg_virt + offset); | |
2b9feef2 | 507 | |
a08cedc3 AE |
508 | /* Zero all filter-related fields, preserving the rest */ |
509 | val &= ~ipa_reg_fmask(reg, FILTER_HASH_MSK_ALL); | |
510 | } else { | |
511 | /* IPA v5.0 separates filter and router cache configuration */ | |
512 | reg = ipa_reg(ipa, ENDP_FILTER_CACHE_CFG); | |
513 | offset = ipa_reg_n_offset(reg, endpoint_id); | |
2b9feef2 | 514 | |
a08cedc3 AE |
515 | /* Zero all filter-related fields */ |
516 | val = 0; | |
517 | } | |
2b9feef2 AE |
518 | |
519 | iowrite32(val, endpoint->ipa->reg_virt + offset); | |
520 | } | |
521 | ||
74858b63 | 522 | /* Configure a hashed filter table; there is no ipa_filter_deconfig() */ |
2b9feef2 AE |
523 | static void ipa_filter_config(struct ipa *ipa, bool modem) |
524 | { | |
525 | enum gsi_ee_id ee_id = modem ? GSI_EE_MODEM : GSI_EE_AP; | |
0f97fbd4 | 526 | u64 ep_mask = ipa->filtered; |
2b9feef2 | 527 | |
a266ad6b | 528 | if (!ipa_table_hash_support(ipa)) |
2b9feef2 AE |
529 | return; |
530 | ||
531 | while (ep_mask) { | |
532 | u32 endpoint_id = __ffs(ep_mask); | |
533 | struct ipa_endpoint *endpoint; | |
534 | ||
535 | ep_mask ^= BIT(endpoint_id); | |
536 | ||
537 | endpoint = &ipa->endpoint[endpoint_id]; | |
538 | if (endpoint->ee_id == ee_id) | |
539 | ipa_filter_tuple_zero(endpoint); | |
540 | } | |
541 | } | |
542 | ||
8defab8b | 543 | static bool ipa_route_id_modem(struct ipa *ipa, u32 route_id) |
2b9feef2 | 544 | { |
8defab8b | 545 | return route_id < ipa->modem_route_count; |
2b9feef2 AE |
546 | } |
547 | ||
548 | /** | |
549 | * ipa_route_tuple_zero() - Zero a hashed route table entry tuple | |
e3eea08e | 550 | * @ipa: IPA pointer |
2b9feef2 AE |
551 | * @route_id: Route table entry whose hash tuple should be zeroed |
552 | * | |
553 | * Updates the route hash values without changing filter ones. | |
554 | */ | |
555 | static void ipa_route_tuple_zero(struct ipa *ipa, u32 route_id) | |
556 | { | |
81772e44 | 557 | const struct reg *reg; |
6bfb7538 | 558 | u32 offset; |
2b9feef2 AE |
559 | u32 val; |
560 | ||
a08cedc3 AE |
561 | if (ipa->version < IPA_VERSION_5_0) { |
562 | reg = ipa_reg(ipa, ENDP_FILTER_ROUTER_HSH_CFG); | |
563 | offset = ipa_reg_n_offset(reg, route_id); | |
564 | ||
565 | val = ioread32(ipa->reg_virt + offset); | |
6bfb7538 | 566 | |
a08cedc3 AE |
567 | /* Zero all route-related fields, preserving the rest */ |
568 | val &= ~ipa_reg_fmask(reg, ROUTER_HASH_MSK_ALL); | |
569 | } else { | |
570 | /* IPA v5.0 separates filter and router cache configuration */ | |
571 | reg = ipa_reg(ipa, ENDP_ROUTER_CACHE_CFG); | |
572 | offset = ipa_reg_n_offset(reg, route_id); | |
2b9feef2 | 573 | |
a08cedc3 AE |
574 | /* Zero all route-related fields */ |
575 | val = 0; | |
576 | } | |
2b9feef2 AE |
577 | |
578 | iowrite32(val, ipa->reg_virt + offset); | |
579 | } | |
580 | ||
74858b63 | 581 | /* Configure a hashed route table; there is no ipa_route_deconfig() */ |
2b9feef2 AE |
582 | static void ipa_route_config(struct ipa *ipa, bool modem) |
583 | { | |
584 | u32 route_id; | |
585 | ||
a266ad6b | 586 | if (!ipa_table_hash_support(ipa)) |
2b9feef2 AE |
587 | return; |
588 | ||
fc094058 | 589 | for (route_id = 0; route_id < ipa->route_count; route_id++) |
8defab8b | 590 | if (ipa_route_id_modem(ipa, route_id) == modem) |
2b9feef2 AE |
591 | ipa_route_tuple_zero(ipa, route_id); |
592 | } | |
593 | ||
74858b63 | 594 | /* Configure a filter and route tables; there is no ipa_table_deconfig() */ |
2b9feef2 AE |
595 | void ipa_table_config(struct ipa *ipa) |
596 | { | |
597 | ipa_filter_config(ipa, false); | |
598 | ipa_filter_config(ipa, true); | |
599 | ipa_route_config(ipa, false); | |
600 | ipa_route_config(ipa, true); | |
601 | } | |
602 | ||
fc094058 AE |
603 | /* Verify the sizes of all IPA table filter or routing table memory regions |
604 | * are valid. If valid, this records the size of the routing table. | |
605 | */ | |
8defab8b | 606 | bool ipa_table_mem_valid(struct ipa *ipa, bool filter) |
cf139196 AE |
607 | { |
608 | bool hash_support = ipa_table_hash_support(ipa); | |
cf139196 AE |
609 | const struct ipa_mem *mem_hashed; |
610 | const struct ipa_mem *mem_ipv4; | |
611 | const struct ipa_mem *mem_ipv6; | |
612 | u32 count; | |
613 | ||
614 | /* IPv4 and IPv6 non-hashed tables are expected to be defined and | |
615 | * have the same size. Both must have at least two entries (and | |
616 | * would normally have more than that). | |
617 | */ | |
618 | mem_ipv4 = ipa_table_mem(ipa, filter, false, false); | |
619 | if (!mem_ipv4) | |
620 | return false; | |
621 | ||
622 | mem_ipv6 = ipa_table_mem(ipa, filter, false, true); | |
623 | if (!mem_ipv6) | |
624 | return false; | |
625 | ||
626 | if (mem_ipv4->size != mem_ipv6->size) | |
627 | return false; | |
628 | ||
f787d848 | 629 | /* Compute and record the number of entries for each table type */ |
0439e674 AE |
630 | count = mem_ipv4->size / sizeof(__le64); |
631 | if (count < 2) | |
632 | return false; | |
f787d848 AE |
633 | if (filter) |
634 | ipa->filter_count = count - 1; /* Filter map in first entry */ | |
635 | else | |
0439e674 | 636 | ipa->route_count = count; |
fc094058 | 637 | |
5444b0ea AE |
638 | /* Table offset and size must fit in TABLE_INIT command fields */ |
639 | if (!ipa_cmd_table_init_valid(ipa, mem_ipv4, !filter)) | |
640 | return false; | |
641 | ||
cf139196 | 642 | /* Make sure the regions are big enough */ |
cf139196 AE |
643 | if (filter) { |
644 | /* Filter tables must able to hold the endpoint bitmap plus | |
645 | * an entry for each endpoint that supports filtering | |
646 | */ | |
0f97fbd4 | 647 | if (count < 1 + hweight64(ipa->filtered)) |
cf139196 AE |
648 | return false; |
649 | } else { | |
650 | /* Routing tables must be able to hold all modem entries, | |
651 | * plus at least one entry for the AP. | |
652 | */ | |
8defab8b | 653 | if (count < ipa->modem_route_count + 1) |
cf139196 AE |
654 | return false; |
655 | } | |
656 | ||
657 | /* If hashing is supported, hashed tables are expected to be defined, | |
658 | * and have the same size as non-hashed tables. If hashing is not | |
659 | * supported, hashed tables are expected to have zero size (or not | |
660 | * be defined). | |
661 | */ | |
662 | mem_hashed = ipa_table_mem(ipa, filter, true, false); | |
663 | if (hash_support) { | |
664 | if (!mem_hashed || mem_hashed->size != mem_ipv4->size) | |
665 | return false; | |
666 | } else { | |
667 | if (mem_hashed && mem_hashed->size) | |
668 | return false; | |
669 | } | |
670 | ||
671 | /* Same check for IPv6 tables */ | |
672 | mem_hashed = ipa_table_mem(ipa, filter, true, true); | |
673 | if (hash_support) { | |
674 | if (!mem_hashed || mem_hashed->size != mem_ipv6->size) | |
675 | return false; | |
676 | } else { | |
677 | if (mem_hashed && mem_hashed->size) | |
678 | return false; | |
679 | } | |
680 | ||
681 | return true; | |
682 | } | |
683 | ||
684 | /* Initialize a coherent DMA allocation containing initialized filter and | |
2b9feef2 AE |
685 | * route table data. This is used when initializing or resetting the IPA |
686 | * filter or route table. | |
687 | * | |
688 | * The first entry in a filter table contains a bitmap indicating which | |
689 | * endpoints contain entries in the table. In addition to that first entry, | |
f787d848 | 690 | * there is a fixed maximum number of entries that follow. Filter table |
2b9feef2 AE |
691 | * entries are 64 bits wide, and (other than the bitmap) contain the DMA |
692 | * address of a filter rule. A "zero rule" indicates no filtering, and | |
693 | * consists of 64 bits of zeroes. When a filter table is initialized (or | |
694 | * reset) its entries are made to refer to the zero rule. | |
695 | * | |
696 | * Each entry in a route table is the DMA address of a routing rule. For | |
697 | * routing there is also a 64-bit "zero rule" that means no routing, and | |
698 | * when a route table is initialized or reset, its entries are made to refer | |
699 | * to the zero rule. The zero rule is shared for route and filter tables. | |
700 | * | |
2b9feef2 AE |
701 | * +-------------------+ |
702 | * --> | zero rule | | |
703 | * / |-------------------| | |
704 | * | | filter mask | | |
705 | * |\ |-------------------| | |
706 | * | ---- zero rule address | \ | |
707 | * |\ |-------------------| | | |
f787d848 | 708 | * | ---- zero rule address | | Max IPA filter count |
fc094058 | 709 | * | |-------------------| > or IPA route count, |
2b9feef2 AE |
710 | * | ... | whichever is greater |
711 | * \ |-------------------| | | |
712 | * ---- zero rule address | / | |
713 | * +-------------------+ | |
714 | */ | |
715 | int ipa_table_init(struct ipa *ipa) | |
716 | { | |
2b9feef2 AE |
717 | struct device *dev = &ipa->pdev->dev; |
718 | dma_addr_t addr; | |
719 | __le64 le_addr; | |
720 | __le64 *virt; | |
721 | size_t size; | |
fc094058 | 722 | u32 count; |
2b9feef2 AE |
723 | |
724 | ipa_table_validate_build(); | |
725 | ||
f787d848 | 726 | count = max_t(u32, ipa->filter_count, ipa->route_count); |
fc094058 | 727 | |
19aaf72c AE |
728 | /* The IPA hardware requires route and filter table rules to be |
729 | * aligned on a 128-byte boundary. We put the "zero rule" at the | |
730 | * base of the table area allocated here. The DMA address returned | |
731 | * by dma_alloc_coherent() is guaranteed to be a power-of-2 number | |
732 | * of pages, which satisfies the rule alignment requirement. | |
733 | */ | |
4ea29143 | 734 | size = IPA_ZERO_RULE_SIZE + (1 + count) * sizeof(__le64); |
2b9feef2 AE |
735 | virt = dma_alloc_coherent(dev, size, &addr, GFP_KERNEL); |
736 | if (!virt) | |
737 | return -ENOMEM; | |
738 | ||
739 | ipa->table_virt = virt; | |
740 | ipa->table_addr = addr; | |
741 | ||
742 | /* First slot is the zero rule */ | |
743 | *virt++ = 0; | |
744 | ||
bd552493 AE |
745 | /* Next is the filter table bitmap. The "soft" bitmap value might |
746 | * need to be converted to the hardware representation by shifting | |
747 | * it left one position. Prior to IPA v5.0, bit 0 repesents global | |
748 | * filtering, which is possible but not used. IPA v5.0+ eliminated | |
749 | * that option, so there's no shifting required. | |
2b9feef2 | 750 | */ |
bd552493 | 751 | if (ipa->version < IPA_VERSION_5_0) |
0f97fbd4 | 752 | *virt++ = cpu_to_le64(ipa->filtered << 1); |
bd552493 | 753 | else |
0f97fbd4 | 754 | *virt++ = cpu_to_le64(ipa->filtered); |
2b9feef2 AE |
755 | |
756 | /* All the rest contain the DMA address of the zero rule */ | |
757 | le_addr = cpu_to_le64(addr); | |
758 | while (count--) | |
759 | *virt++ = le_addr; | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
764 | void ipa_table_exit(struct ipa *ipa) | |
765 | { | |
f787d848 | 766 | u32 count = max_t(u32, 1 + ipa->filter_count, ipa->route_count); |
2b9feef2 AE |
767 | struct device *dev = &ipa->pdev->dev; |
768 | size_t size; | |
769 | ||
4ea29143 | 770 | size = IPA_ZERO_RULE_SIZE + (1 + count) * sizeof(__le64); |
2b9feef2 AE |
771 | |
772 | dma_free_coherent(dev, size, ipa->table_virt, ipa->table_addr); | |
773 | ipa->table_addr = 0; | |
774 | ipa->table_virt = NULL; | |
775 | } |