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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/types.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/vmalloc.h> | |
32 | #include <linux/pagemap.h> | |
33 | #include <linux/netdevice.h> | |
9d5c8243 AK |
34 | #include <linux/ipv6.h> |
35 | #include <net/checksum.h> | |
36 | #include <net/ip6_checksum.h> | |
c6cb090b | 37 | #include <linux/net_tstamp.h> |
9d5c8243 AK |
38 | #include <linux/mii.h> |
39 | #include <linux/ethtool.h> | |
40 | #include <linux/if_vlan.h> | |
41 | #include <linux/pci.h> | |
c54106bb | 42 | #include <linux/pci-aspm.h> |
9d5c8243 AK |
43 | #include <linux/delay.h> |
44 | #include <linux/interrupt.h> | |
45 | #include <linux/if_ether.h> | |
40a914fa | 46 | #include <linux/aer.h> |
421e02f0 | 47 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
48 | #include <linux/dca.h> |
49 | #endif | |
9d5c8243 AK |
50 | #include "igb.h" |
51 | ||
55cac248 | 52 | #define DRV_VERSION "2.1.0-k2" |
9d5c8243 AK |
53 | char igb_driver_name[] = "igb"; |
54 | char igb_driver_version[] = DRV_VERSION; | |
55 | static const char igb_driver_string[] = | |
56 | "Intel(R) Gigabit Ethernet Network Driver"; | |
86d5d38f | 57 | static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation."; |
9d5c8243 | 58 | |
9d5c8243 AK |
59 | static const struct e1000_info *igb_info_tbl[] = { |
60 | [board_82575] = &e1000_82575_info, | |
61 | }; | |
62 | ||
63 | static struct pci_device_id igb_pci_tbl[] = { | |
55cac248 AD |
64 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, |
65 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, | |
66 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, | |
67 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, | |
68 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, | |
2d064c06 | 69 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, |
9eb2341d | 70 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, |
747d49ba | 71 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, |
2d064c06 AD |
72 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, |
73 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, | |
4703bf73 | 74 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, |
c8ea5ea9 | 75 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, |
9d5c8243 AK |
76 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, |
77 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, | |
78 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, | |
79 | /* required last entry */ | |
80 | {0, } | |
81 | }; | |
82 | ||
83 | MODULE_DEVICE_TABLE(pci, igb_pci_tbl); | |
84 | ||
85 | void igb_reset(struct igb_adapter *); | |
86 | static int igb_setup_all_tx_resources(struct igb_adapter *); | |
87 | static int igb_setup_all_rx_resources(struct igb_adapter *); | |
88 | static void igb_free_all_tx_resources(struct igb_adapter *); | |
89 | static void igb_free_all_rx_resources(struct igb_adapter *); | |
06cf2666 | 90 | static void igb_setup_mrqc(struct igb_adapter *); |
9d5c8243 AK |
91 | void igb_update_stats(struct igb_adapter *); |
92 | static int igb_probe(struct pci_dev *, const struct pci_device_id *); | |
93 | static void __devexit igb_remove(struct pci_dev *pdev); | |
94 | static int igb_sw_init(struct igb_adapter *); | |
95 | static int igb_open(struct net_device *); | |
96 | static int igb_close(struct net_device *); | |
97 | static void igb_configure_tx(struct igb_adapter *); | |
98 | static void igb_configure_rx(struct igb_adapter *); | |
9d5c8243 AK |
99 | static void igb_clean_all_tx_rings(struct igb_adapter *); |
100 | static void igb_clean_all_rx_rings(struct igb_adapter *); | |
3b644cf6 MW |
101 | static void igb_clean_tx_ring(struct igb_ring *); |
102 | static void igb_clean_rx_ring(struct igb_ring *); | |
ff41f8dc | 103 | static void igb_set_rx_mode(struct net_device *); |
9d5c8243 AK |
104 | static void igb_update_phy_info(unsigned long); |
105 | static void igb_watchdog(unsigned long); | |
106 | static void igb_watchdog_task(struct work_struct *); | |
b1a436c3 | 107 | static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *); |
9d5c8243 AK |
108 | static struct net_device_stats *igb_get_stats(struct net_device *); |
109 | static int igb_change_mtu(struct net_device *, int); | |
110 | static int igb_set_mac(struct net_device *, void *); | |
68d480c4 | 111 | static void igb_set_uta(struct igb_adapter *adapter); |
9d5c8243 AK |
112 | static irqreturn_t igb_intr(int irq, void *); |
113 | static irqreturn_t igb_intr_msi(int irq, void *); | |
114 | static irqreturn_t igb_msix_other(int irq, void *); | |
047e0030 | 115 | static irqreturn_t igb_msix_ring(int irq, void *); |
421e02f0 | 116 | #ifdef CONFIG_IGB_DCA |
047e0030 | 117 | static void igb_update_dca(struct igb_q_vector *); |
fe4506b6 | 118 | static void igb_setup_dca(struct igb_adapter *); |
421e02f0 | 119 | #endif /* CONFIG_IGB_DCA */ |
047e0030 | 120 | static bool igb_clean_tx_irq(struct igb_q_vector *); |
661086df | 121 | static int igb_poll(struct napi_struct *, int); |
047e0030 | 122 | static bool igb_clean_rx_irq_adv(struct igb_q_vector *, int *, int); |
9d5c8243 AK |
123 | static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); |
124 | static void igb_tx_timeout(struct net_device *); | |
125 | static void igb_reset_task(struct work_struct *); | |
126 | static void igb_vlan_rx_register(struct net_device *, struct vlan_group *); | |
127 | static void igb_vlan_rx_add_vid(struct net_device *, u16); | |
128 | static void igb_vlan_rx_kill_vid(struct net_device *, u16); | |
129 | static void igb_restore_vlan(struct igb_adapter *); | |
26ad9178 | 130 | static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); |
4ae196df AD |
131 | static void igb_ping_all_vfs(struct igb_adapter *); |
132 | static void igb_msg_task(struct igb_adapter *); | |
4ae196df | 133 | static void igb_vmm_control(struct igb_adapter *); |
f2ca0dbe | 134 | static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); |
4ae196df | 135 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter); |
9d5c8243 | 136 | |
9d5c8243 | 137 | #ifdef CONFIG_PM |
3fe7c4c9 | 138 | static int igb_suspend(struct pci_dev *, pm_message_t); |
9d5c8243 AK |
139 | static int igb_resume(struct pci_dev *); |
140 | #endif | |
141 | static void igb_shutdown(struct pci_dev *); | |
421e02f0 | 142 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
143 | static int igb_notify_dca(struct notifier_block *, unsigned long, void *); |
144 | static struct notifier_block dca_notifier = { | |
145 | .notifier_call = igb_notify_dca, | |
146 | .next = NULL, | |
147 | .priority = 0 | |
148 | }; | |
149 | #endif | |
9d5c8243 AK |
150 | #ifdef CONFIG_NET_POLL_CONTROLLER |
151 | /* for netdump / net console */ | |
152 | static void igb_netpoll(struct net_device *); | |
153 | #endif | |
37680117 | 154 | #ifdef CONFIG_PCI_IOV |
2a3abf6d AD |
155 | static unsigned int max_vfs = 0; |
156 | module_param(max_vfs, uint, 0); | |
157 | MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " | |
158 | "per physical function"); | |
159 | #endif /* CONFIG_PCI_IOV */ | |
160 | ||
9d5c8243 AK |
161 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *, |
162 | pci_channel_state_t); | |
163 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); | |
164 | static void igb_io_resume(struct pci_dev *); | |
165 | ||
166 | static struct pci_error_handlers igb_err_handler = { | |
167 | .error_detected = igb_io_error_detected, | |
168 | .slot_reset = igb_io_slot_reset, | |
169 | .resume = igb_io_resume, | |
170 | }; | |
171 | ||
172 | ||
173 | static struct pci_driver igb_driver = { | |
174 | .name = igb_driver_name, | |
175 | .id_table = igb_pci_tbl, | |
176 | .probe = igb_probe, | |
177 | .remove = __devexit_p(igb_remove), | |
178 | #ifdef CONFIG_PM | |
179 | /* Power Managment Hooks */ | |
180 | .suspend = igb_suspend, | |
181 | .resume = igb_resume, | |
182 | #endif | |
183 | .shutdown = igb_shutdown, | |
184 | .err_handler = &igb_err_handler | |
185 | }; | |
186 | ||
187 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); | |
188 | MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); | |
189 | MODULE_LICENSE("GPL"); | |
190 | MODULE_VERSION(DRV_VERSION); | |
191 | ||
38c845c7 PO |
192 | /** |
193 | * igb_read_clock - read raw cycle counter (to be used by time counter) | |
194 | */ | |
195 | static cycle_t igb_read_clock(const struct cyclecounter *tc) | |
196 | { | |
197 | struct igb_adapter *adapter = | |
198 | container_of(tc, struct igb_adapter, cycles); | |
199 | struct e1000_hw *hw = &adapter->hw; | |
c5b9bd5e AD |
200 | u64 stamp = 0; |
201 | int shift = 0; | |
38c845c7 | 202 | |
55cac248 AD |
203 | /* |
204 | * The timestamp latches on lowest register read. For the 82580 | |
205 | * the lowest register is SYSTIMR instead of SYSTIML. However we never | |
206 | * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it. | |
207 | */ | |
208 | if (hw->mac.type == e1000_82580) { | |
209 | stamp = rd32(E1000_SYSTIMR) >> 8; | |
210 | shift = IGB_82580_TSYNC_SHIFT; | |
211 | } | |
212 | ||
c5b9bd5e AD |
213 | stamp |= (u64)rd32(E1000_SYSTIML) << shift; |
214 | stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32); | |
38c845c7 PO |
215 | return stamp; |
216 | } | |
217 | ||
9d5c8243 AK |
218 | #ifdef DEBUG |
219 | /** | |
220 | * igb_get_hw_dev_name - return device name string | |
221 | * used by hardware layer to print debugging information | |
222 | **/ | |
223 | char *igb_get_hw_dev_name(struct e1000_hw *hw) | |
224 | { | |
225 | struct igb_adapter *adapter = hw->back; | |
226 | return adapter->netdev->name; | |
227 | } | |
38c845c7 PO |
228 | |
229 | /** | |
230 | * igb_get_time_str - format current NIC and system time as string | |
231 | */ | |
232 | static char *igb_get_time_str(struct igb_adapter *adapter, | |
233 | char buffer[160]) | |
234 | { | |
235 | cycle_t hw = adapter->cycles.read(&adapter->cycles); | |
236 | struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock)); | |
237 | struct timespec sys; | |
238 | struct timespec delta; | |
239 | getnstimeofday(&sys); | |
240 | ||
241 | delta = timespec_sub(nic, sys); | |
242 | ||
243 | sprintf(buffer, | |
33af6bcc PO |
244 | "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns", |
245 | hw, | |
38c845c7 PO |
246 | (long)nic.tv_sec, nic.tv_nsec, |
247 | (long)sys.tv_sec, sys.tv_nsec, | |
248 | (long)delta.tv_sec, delta.tv_nsec); | |
249 | ||
250 | return buffer; | |
251 | } | |
9d5c8243 AK |
252 | #endif |
253 | ||
254 | /** | |
255 | * igb_init_module - Driver Registration Routine | |
256 | * | |
257 | * igb_init_module is the first routine called when the driver is | |
258 | * loaded. All it does is register with the PCI subsystem. | |
259 | **/ | |
260 | static int __init igb_init_module(void) | |
261 | { | |
262 | int ret; | |
263 | printk(KERN_INFO "%s - version %s\n", | |
264 | igb_driver_string, igb_driver_version); | |
265 | ||
266 | printk(KERN_INFO "%s\n", igb_copyright); | |
267 | ||
421e02f0 | 268 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
269 | dca_register_notify(&dca_notifier); |
270 | #endif | |
bbd98fe4 | 271 | ret = pci_register_driver(&igb_driver); |
9d5c8243 AK |
272 | return ret; |
273 | } | |
274 | ||
275 | module_init(igb_init_module); | |
276 | ||
277 | /** | |
278 | * igb_exit_module - Driver Exit Cleanup Routine | |
279 | * | |
280 | * igb_exit_module is called just before the driver is removed | |
281 | * from memory. | |
282 | **/ | |
283 | static void __exit igb_exit_module(void) | |
284 | { | |
421e02f0 | 285 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
286 | dca_unregister_notify(&dca_notifier); |
287 | #endif | |
9d5c8243 AK |
288 | pci_unregister_driver(&igb_driver); |
289 | } | |
290 | ||
291 | module_exit(igb_exit_module); | |
292 | ||
26bc19ec AD |
293 | #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) |
294 | /** | |
295 | * igb_cache_ring_register - Descriptor ring to register mapping | |
296 | * @adapter: board private structure to initialize | |
297 | * | |
298 | * Once we know the feature-set enabled for the device, we'll cache | |
299 | * the register offset the descriptor ring is assigned to. | |
300 | **/ | |
301 | static void igb_cache_ring_register(struct igb_adapter *adapter) | |
302 | { | |
ee1b9f06 | 303 | int i = 0, j = 0; |
047e0030 | 304 | u32 rbase_offset = adapter->vfs_allocated_count; |
26bc19ec AD |
305 | |
306 | switch (adapter->hw.mac.type) { | |
307 | case e1000_82576: | |
308 | /* The queues are allocated for virtualization such that VF 0 | |
309 | * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. | |
310 | * In order to avoid collision we start at the first free queue | |
311 | * and continue consuming queues in the same sequence | |
312 | */ | |
ee1b9f06 | 313 | if (adapter->vfs_allocated_count) { |
a99955fc | 314 | for (; i < adapter->rss_queues; i++) |
ee1b9f06 AD |
315 | adapter->rx_ring[i].reg_idx = rbase_offset + |
316 | Q_IDX_82576(i); | |
a99955fc | 317 | for (; j < adapter->rss_queues; j++) |
ee1b9f06 AD |
318 | adapter->tx_ring[j].reg_idx = rbase_offset + |
319 | Q_IDX_82576(j); | |
320 | } | |
26bc19ec | 321 | case e1000_82575: |
55cac248 | 322 | case e1000_82580: |
26bc19ec | 323 | default: |
ee1b9f06 AD |
324 | for (; i < adapter->num_rx_queues; i++) |
325 | adapter->rx_ring[i].reg_idx = rbase_offset + i; | |
326 | for (; j < adapter->num_tx_queues; j++) | |
327 | adapter->tx_ring[j].reg_idx = rbase_offset + j; | |
26bc19ec AD |
328 | break; |
329 | } | |
330 | } | |
331 | ||
047e0030 AD |
332 | static void igb_free_queues(struct igb_adapter *adapter) |
333 | { | |
334 | kfree(adapter->tx_ring); | |
335 | kfree(adapter->rx_ring); | |
336 | ||
337 | adapter->tx_ring = NULL; | |
338 | adapter->rx_ring = NULL; | |
339 | ||
340 | adapter->num_rx_queues = 0; | |
341 | adapter->num_tx_queues = 0; | |
342 | } | |
343 | ||
9d5c8243 AK |
344 | /** |
345 | * igb_alloc_queues - Allocate memory for all rings | |
346 | * @adapter: board private structure to initialize | |
347 | * | |
348 | * We allocate one ring per queue at run-time since we don't know the | |
349 | * number of queues at compile-time. | |
350 | **/ | |
351 | static int igb_alloc_queues(struct igb_adapter *adapter) | |
352 | { | |
353 | int i; | |
354 | ||
355 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
356 | sizeof(struct igb_ring), GFP_KERNEL); | |
357 | if (!adapter->tx_ring) | |
047e0030 | 358 | goto err; |
9d5c8243 AK |
359 | |
360 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
361 | sizeof(struct igb_ring), GFP_KERNEL); | |
047e0030 AD |
362 | if (!adapter->rx_ring) |
363 | goto err; | |
6eb5a7f1 | 364 | |
661086df PWJ |
365 | for (i = 0; i < adapter->num_tx_queues; i++) { |
366 | struct igb_ring *ring = &(adapter->tx_ring[i]); | |
68fd9910 | 367 | ring->count = adapter->tx_ring_count; |
661086df | 368 | ring->queue_index = i; |
80785298 | 369 | ring->pdev = adapter->pdev; |
e694e964 | 370 | ring->netdev = adapter->netdev; |
85ad76b2 AD |
371 | /* For 82575, context index must be unique per ring. */ |
372 | if (adapter->hw.mac.type == e1000_82575) | |
373 | ring->flags = IGB_RING_FLAG_TX_CTX_IDX; | |
661086df | 374 | } |
85ad76b2 | 375 | |
9d5c8243 AK |
376 | for (i = 0; i < adapter->num_rx_queues; i++) { |
377 | struct igb_ring *ring = &(adapter->rx_ring[i]); | |
68fd9910 | 378 | ring->count = adapter->rx_ring_count; |
844290e5 | 379 | ring->queue_index = i; |
80785298 | 380 | ring->pdev = adapter->pdev; |
e694e964 | 381 | ring->netdev = adapter->netdev; |
4c844851 | 382 | ring->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
85ad76b2 AD |
383 | ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */ |
384 | /* set flag indicating ring supports SCTP checksum offload */ | |
385 | if (adapter->hw.mac.type >= e1000_82576) | |
386 | ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM; | |
9d5c8243 | 387 | } |
26bc19ec AD |
388 | |
389 | igb_cache_ring_register(adapter); | |
9d5c8243 | 390 | |
047e0030 | 391 | return 0; |
a88f10ec | 392 | |
047e0030 AD |
393 | err: |
394 | igb_free_queues(adapter); | |
d1a8c9e1 | 395 | |
047e0030 | 396 | return -ENOMEM; |
a88f10ec AD |
397 | } |
398 | ||
9d5c8243 | 399 | #define IGB_N0_QUEUE -1 |
047e0030 | 400 | static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) |
9d5c8243 AK |
401 | { |
402 | u32 msixbm = 0; | |
047e0030 | 403 | struct igb_adapter *adapter = q_vector->adapter; |
9d5c8243 | 404 | struct e1000_hw *hw = &adapter->hw; |
2d064c06 | 405 | u32 ivar, index; |
047e0030 AD |
406 | int rx_queue = IGB_N0_QUEUE; |
407 | int tx_queue = IGB_N0_QUEUE; | |
408 | ||
409 | if (q_vector->rx_ring) | |
410 | rx_queue = q_vector->rx_ring->reg_idx; | |
411 | if (q_vector->tx_ring) | |
412 | tx_queue = q_vector->tx_ring->reg_idx; | |
2d064c06 AD |
413 | |
414 | switch (hw->mac.type) { | |
415 | case e1000_82575: | |
9d5c8243 AK |
416 | /* The 82575 assigns vectors using a bitmask, which matches the |
417 | bitmask for the EICR/EIMS/EIMC registers. To assign one | |
418 | or more queues to a vector, we write the appropriate bits | |
419 | into the MSIXBM register for that vector. */ | |
047e0030 | 420 | if (rx_queue > IGB_N0_QUEUE) |
9d5c8243 | 421 | msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; |
047e0030 | 422 | if (tx_queue > IGB_N0_QUEUE) |
9d5c8243 | 423 | msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; |
9d5c8243 | 424 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); |
047e0030 | 425 | q_vector->eims_value = msixbm; |
2d064c06 AD |
426 | break; |
427 | case e1000_82576: | |
26bc19ec | 428 | /* 82576 uses a table-based method for assigning vectors. |
2d064c06 AD |
429 | Each queue has a single entry in the table to which we write |
430 | a vector number along with a "valid" bit. Sadly, the layout | |
431 | of the table is somewhat counterintuitive. */ | |
432 | if (rx_queue > IGB_N0_QUEUE) { | |
047e0030 | 433 | index = (rx_queue & 0x7); |
2d064c06 | 434 | ivar = array_rd32(E1000_IVAR0, index); |
047e0030 | 435 | if (rx_queue < 8) { |
26bc19ec AD |
436 | /* vector goes into low byte of register */ |
437 | ivar = ivar & 0xFFFFFF00; | |
438 | ivar |= msix_vector | E1000_IVAR_VALID; | |
047e0030 AD |
439 | } else { |
440 | /* vector goes into third byte of register */ | |
441 | ivar = ivar & 0xFF00FFFF; | |
442 | ivar |= (msix_vector | E1000_IVAR_VALID) << 16; | |
2d064c06 | 443 | } |
2d064c06 AD |
444 | array_wr32(E1000_IVAR0, index, ivar); |
445 | } | |
446 | if (tx_queue > IGB_N0_QUEUE) { | |
047e0030 | 447 | index = (tx_queue & 0x7); |
2d064c06 | 448 | ivar = array_rd32(E1000_IVAR0, index); |
047e0030 | 449 | if (tx_queue < 8) { |
26bc19ec AD |
450 | /* vector goes into second byte of register */ |
451 | ivar = ivar & 0xFFFF00FF; | |
452 | ivar |= (msix_vector | E1000_IVAR_VALID) << 8; | |
047e0030 AD |
453 | } else { |
454 | /* vector goes into high byte of register */ | |
455 | ivar = ivar & 0x00FFFFFF; | |
456 | ivar |= (msix_vector | E1000_IVAR_VALID) << 24; | |
2d064c06 | 457 | } |
2d064c06 AD |
458 | array_wr32(E1000_IVAR0, index, ivar); |
459 | } | |
047e0030 | 460 | q_vector->eims_value = 1 << msix_vector; |
2d064c06 | 461 | break; |
55cac248 AD |
462 | case e1000_82580: |
463 | /* 82580 uses the same table-based approach as 82576 but has fewer | |
464 | entries as a result we carry over for queues greater than 4. */ | |
465 | if (rx_queue > IGB_N0_QUEUE) { | |
466 | index = (rx_queue >> 1); | |
467 | ivar = array_rd32(E1000_IVAR0, index); | |
468 | if (rx_queue & 0x1) { | |
469 | /* vector goes into third byte of register */ | |
470 | ivar = ivar & 0xFF00FFFF; | |
471 | ivar |= (msix_vector | E1000_IVAR_VALID) << 16; | |
472 | } else { | |
473 | /* vector goes into low byte of register */ | |
474 | ivar = ivar & 0xFFFFFF00; | |
475 | ivar |= msix_vector | E1000_IVAR_VALID; | |
476 | } | |
477 | array_wr32(E1000_IVAR0, index, ivar); | |
478 | } | |
479 | if (tx_queue > IGB_N0_QUEUE) { | |
480 | index = (tx_queue >> 1); | |
481 | ivar = array_rd32(E1000_IVAR0, index); | |
482 | if (tx_queue & 0x1) { | |
483 | /* vector goes into high byte of register */ | |
484 | ivar = ivar & 0x00FFFFFF; | |
485 | ivar |= (msix_vector | E1000_IVAR_VALID) << 24; | |
486 | } else { | |
487 | /* vector goes into second byte of register */ | |
488 | ivar = ivar & 0xFFFF00FF; | |
489 | ivar |= (msix_vector | E1000_IVAR_VALID) << 8; | |
490 | } | |
491 | array_wr32(E1000_IVAR0, index, ivar); | |
492 | } | |
493 | q_vector->eims_value = 1 << msix_vector; | |
494 | break; | |
2d064c06 AD |
495 | default: |
496 | BUG(); | |
497 | break; | |
498 | } | |
9d5c8243 AK |
499 | } |
500 | ||
501 | /** | |
502 | * igb_configure_msix - Configure MSI-X hardware | |
503 | * | |
504 | * igb_configure_msix sets up the hardware to properly | |
505 | * generate MSI-X interrupts. | |
506 | **/ | |
507 | static void igb_configure_msix(struct igb_adapter *adapter) | |
508 | { | |
509 | u32 tmp; | |
510 | int i, vector = 0; | |
511 | struct e1000_hw *hw = &adapter->hw; | |
512 | ||
513 | adapter->eims_enable_mask = 0; | |
9d5c8243 AK |
514 | |
515 | /* set vector for other causes, i.e. link changes */ | |
2d064c06 AD |
516 | switch (hw->mac.type) { |
517 | case e1000_82575: | |
9d5c8243 AK |
518 | tmp = rd32(E1000_CTRL_EXT); |
519 | /* enable MSI-X PBA support*/ | |
520 | tmp |= E1000_CTRL_EXT_PBA_CLR; | |
521 | ||
522 | /* Auto-Mask interrupts upon ICR read. */ | |
523 | tmp |= E1000_CTRL_EXT_EIAME; | |
524 | tmp |= E1000_CTRL_EXT_IRCA; | |
525 | ||
526 | wr32(E1000_CTRL_EXT, tmp); | |
047e0030 AD |
527 | |
528 | /* enable msix_other interrupt */ | |
529 | array_wr32(E1000_MSIXBM(0), vector++, | |
530 | E1000_EIMS_OTHER); | |
844290e5 | 531 | adapter->eims_other = E1000_EIMS_OTHER; |
9d5c8243 | 532 | |
2d064c06 AD |
533 | break; |
534 | ||
535 | case e1000_82576: | |
55cac248 | 536 | case e1000_82580: |
047e0030 AD |
537 | /* Turn on MSI-X capability first, or our settings |
538 | * won't stick. And it will take days to debug. */ | |
539 | wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | | |
540 | E1000_GPIE_PBA | E1000_GPIE_EIAME | | |
541 | E1000_GPIE_NSICR); | |
542 | ||
543 | /* enable msix_other interrupt */ | |
544 | adapter->eims_other = 1 << vector; | |
2d064c06 | 545 | tmp = (vector++ | E1000_IVAR_VALID) << 8; |
2d064c06 | 546 | |
047e0030 | 547 | wr32(E1000_IVAR_MISC, tmp); |
2d064c06 AD |
548 | break; |
549 | default: | |
550 | /* do nothing, since nothing else supports MSI-X */ | |
551 | break; | |
552 | } /* switch (hw->mac.type) */ | |
047e0030 AD |
553 | |
554 | adapter->eims_enable_mask |= adapter->eims_other; | |
555 | ||
556 | for (i = 0; i < adapter->num_q_vectors; i++) { | |
557 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
558 | igb_assign_vector(q_vector, vector++); | |
559 | adapter->eims_enable_mask |= q_vector->eims_value; | |
560 | } | |
561 | ||
9d5c8243 AK |
562 | wrfl(); |
563 | } | |
564 | ||
565 | /** | |
566 | * igb_request_msix - Initialize MSI-X interrupts | |
567 | * | |
568 | * igb_request_msix allocates MSI-X vectors and requests interrupts from the | |
569 | * kernel. | |
570 | **/ | |
571 | static int igb_request_msix(struct igb_adapter *adapter) | |
572 | { | |
573 | struct net_device *netdev = adapter->netdev; | |
047e0030 | 574 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
575 | int i, err = 0, vector = 0; |
576 | ||
047e0030 | 577 | err = request_irq(adapter->msix_entries[vector].vector, |
a0607fd3 | 578 | igb_msix_other, 0, netdev->name, adapter); |
047e0030 AD |
579 | if (err) |
580 | goto out; | |
581 | vector++; | |
582 | ||
583 | for (i = 0; i < adapter->num_q_vectors; i++) { | |
584 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
585 | ||
586 | q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); | |
587 | ||
588 | if (q_vector->rx_ring && q_vector->tx_ring) | |
589 | sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, | |
590 | q_vector->rx_ring->queue_index); | |
591 | else if (q_vector->tx_ring) | |
592 | sprintf(q_vector->name, "%s-tx-%u", netdev->name, | |
593 | q_vector->tx_ring->queue_index); | |
594 | else if (q_vector->rx_ring) | |
595 | sprintf(q_vector->name, "%s-rx-%u", netdev->name, | |
596 | q_vector->rx_ring->queue_index); | |
9d5c8243 | 597 | else |
047e0030 AD |
598 | sprintf(q_vector->name, "%s-unused", netdev->name); |
599 | ||
9d5c8243 | 600 | err = request_irq(adapter->msix_entries[vector].vector, |
a0607fd3 | 601 | igb_msix_ring, 0, q_vector->name, |
047e0030 | 602 | q_vector); |
9d5c8243 AK |
603 | if (err) |
604 | goto out; | |
9d5c8243 AK |
605 | vector++; |
606 | } | |
607 | ||
9d5c8243 AK |
608 | igb_configure_msix(adapter); |
609 | return 0; | |
610 | out: | |
611 | return err; | |
612 | } | |
613 | ||
614 | static void igb_reset_interrupt_capability(struct igb_adapter *adapter) | |
615 | { | |
616 | if (adapter->msix_entries) { | |
617 | pci_disable_msix(adapter->pdev); | |
618 | kfree(adapter->msix_entries); | |
619 | adapter->msix_entries = NULL; | |
047e0030 | 620 | } else if (adapter->flags & IGB_FLAG_HAS_MSI) { |
9d5c8243 | 621 | pci_disable_msi(adapter->pdev); |
047e0030 | 622 | } |
9d5c8243 AK |
623 | } |
624 | ||
047e0030 AD |
625 | /** |
626 | * igb_free_q_vectors - Free memory allocated for interrupt vectors | |
627 | * @adapter: board private structure to initialize | |
628 | * | |
629 | * This function frees the memory allocated to the q_vectors. In addition if | |
630 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
631 | * to freeing the q_vector. | |
632 | **/ | |
633 | static void igb_free_q_vectors(struct igb_adapter *adapter) | |
634 | { | |
635 | int v_idx; | |
636 | ||
637 | for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { | |
638 | struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; | |
639 | adapter->q_vector[v_idx] = NULL; | |
640 | netif_napi_del(&q_vector->napi); | |
641 | kfree(q_vector); | |
642 | } | |
643 | adapter->num_q_vectors = 0; | |
644 | } | |
645 | ||
646 | /** | |
647 | * igb_clear_interrupt_scheme - reset the device to a state of no interrupts | |
648 | * | |
649 | * This function resets the device so that it has 0 rx queues, tx queues, and | |
650 | * MSI-X interrupts allocated. | |
651 | */ | |
652 | static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) | |
653 | { | |
654 | igb_free_queues(adapter); | |
655 | igb_free_q_vectors(adapter); | |
656 | igb_reset_interrupt_capability(adapter); | |
657 | } | |
9d5c8243 AK |
658 | |
659 | /** | |
660 | * igb_set_interrupt_capability - set MSI or MSI-X if supported | |
661 | * | |
662 | * Attempt to configure interrupts using the best available | |
663 | * capabilities of the hardware and kernel. | |
664 | **/ | |
665 | static void igb_set_interrupt_capability(struct igb_adapter *adapter) | |
666 | { | |
667 | int err; | |
668 | int numvecs, i; | |
669 | ||
83b7180d | 670 | /* Number of supported queues. */ |
a99955fc AD |
671 | adapter->num_rx_queues = adapter->rss_queues; |
672 | adapter->num_tx_queues = adapter->rss_queues; | |
83b7180d | 673 | |
047e0030 AD |
674 | /* start with one vector for every rx queue */ |
675 | numvecs = adapter->num_rx_queues; | |
676 | ||
677 | /* if tx handler is seperate add 1 for every tx queue */ | |
a99955fc AD |
678 | if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) |
679 | numvecs += adapter->num_tx_queues; | |
047e0030 AD |
680 | |
681 | /* store the number of vectors reserved for queues */ | |
682 | adapter->num_q_vectors = numvecs; | |
683 | ||
684 | /* add 1 vector for link status interrupts */ | |
685 | numvecs++; | |
9d5c8243 AK |
686 | adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), |
687 | GFP_KERNEL); | |
688 | if (!adapter->msix_entries) | |
689 | goto msi_only; | |
690 | ||
691 | for (i = 0; i < numvecs; i++) | |
692 | adapter->msix_entries[i].entry = i; | |
693 | ||
694 | err = pci_enable_msix(adapter->pdev, | |
695 | adapter->msix_entries, | |
696 | numvecs); | |
697 | if (err == 0) | |
34a20e89 | 698 | goto out; |
9d5c8243 AK |
699 | |
700 | igb_reset_interrupt_capability(adapter); | |
701 | ||
702 | /* If we can't do MSI-X, try MSI */ | |
703 | msi_only: | |
2a3abf6d AD |
704 | #ifdef CONFIG_PCI_IOV |
705 | /* disable SR-IOV for non MSI-X configurations */ | |
706 | if (adapter->vf_data) { | |
707 | struct e1000_hw *hw = &adapter->hw; | |
708 | /* disable iov and allow time for transactions to clear */ | |
709 | pci_disable_sriov(adapter->pdev); | |
710 | msleep(500); | |
711 | ||
712 | kfree(adapter->vf_data); | |
713 | adapter->vf_data = NULL; | |
714 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
715 | msleep(100); | |
716 | dev_info(&adapter->pdev->dev, "IOV Disabled\n"); | |
717 | } | |
718 | #endif | |
4fc82adf | 719 | adapter->vfs_allocated_count = 0; |
a99955fc | 720 | adapter->rss_queues = 1; |
4fc82adf | 721 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; |
9d5c8243 | 722 | adapter->num_rx_queues = 1; |
661086df | 723 | adapter->num_tx_queues = 1; |
047e0030 | 724 | adapter->num_q_vectors = 1; |
9d5c8243 | 725 | if (!pci_enable_msi(adapter->pdev)) |
7dfc16fa | 726 | adapter->flags |= IGB_FLAG_HAS_MSI; |
34a20e89 | 727 | out: |
661086df | 728 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ |
fd2ea0a7 | 729 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; |
9d5c8243 AK |
730 | return; |
731 | } | |
732 | ||
047e0030 AD |
733 | /** |
734 | * igb_alloc_q_vectors - Allocate memory for interrupt vectors | |
735 | * @adapter: board private structure to initialize | |
736 | * | |
737 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
738 | * return -ENOMEM. | |
739 | **/ | |
740 | static int igb_alloc_q_vectors(struct igb_adapter *adapter) | |
741 | { | |
742 | struct igb_q_vector *q_vector; | |
743 | struct e1000_hw *hw = &adapter->hw; | |
744 | int v_idx; | |
745 | ||
746 | for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { | |
747 | q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL); | |
748 | if (!q_vector) | |
749 | goto err_out; | |
750 | q_vector->adapter = adapter; | |
751 | q_vector->itr_shift = (hw->mac.type == e1000_82575) ? 16 : 0; | |
752 | q_vector->itr_register = hw->hw_addr + E1000_EITR(0); | |
753 | q_vector->itr_val = IGB_START_ITR; | |
754 | q_vector->set_itr = 1; | |
755 | netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64); | |
756 | adapter->q_vector[v_idx] = q_vector; | |
757 | } | |
758 | return 0; | |
759 | ||
760 | err_out: | |
761 | while (v_idx) { | |
762 | v_idx--; | |
763 | q_vector = adapter->q_vector[v_idx]; | |
764 | netif_napi_del(&q_vector->napi); | |
765 | kfree(q_vector); | |
766 | adapter->q_vector[v_idx] = NULL; | |
767 | } | |
768 | return -ENOMEM; | |
769 | } | |
770 | ||
771 | static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter, | |
772 | int ring_idx, int v_idx) | |
773 | { | |
774 | struct igb_q_vector *q_vector; | |
775 | ||
776 | q_vector = adapter->q_vector[v_idx]; | |
777 | q_vector->rx_ring = &adapter->rx_ring[ring_idx]; | |
778 | q_vector->rx_ring->q_vector = q_vector; | |
4fc82adf AD |
779 | q_vector->itr_val = adapter->rx_itr_setting; |
780 | if (q_vector->itr_val && q_vector->itr_val <= 3) | |
781 | q_vector->itr_val = IGB_START_ITR; | |
047e0030 AD |
782 | } |
783 | ||
784 | static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter, | |
785 | int ring_idx, int v_idx) | |
786 | { | |
787 | struct igb_q_vector *q_vector; | |
788 | ||
789 | q_vector = adapter->q_vector[v_idx]; | |
790 | q_vector->tx_ring = &adapter->tx_ring[ring_idx]; | |
791 | q_vector->tx_ring->q_vector = q_vector; | |
4fc82adf AD |
792 | q_vector->itr_val = adapter->tx_itr_setting; |
793 | if (q_vector->itr_val && q_vector->itr_val <= 3) | |
794 | q_vector->itr_val = IGB_START_ITR; | |
047e0030 AD |
795 | } |
796 | ||
797 | /** | |
798 | * igb_map_ring_to_vector - maps allocated queues to vectors | |
799 | * | |
800 | * This function maps the recently allocated queues to vectors. | |
801 | **/ | |
802 | static int igb_map_ring_to_vector(struct igb_adapter *adapter) | |
803 | { | |
804 | int i; | |
805 | int v_idx = 0; | |
806 | ||
807 | if ((adapter->num_q_vectors < adapter->num_rx_queues) || | |
808 | (adapter->num_q_vectors < adapter->num_tx_queues)) | |
809 | return -ENOMEM; | |
810 | ||
811 | if (adapter->num_q_vectors >= | |
812 | (adapter->num_rx_queues + adapter->num_tx_queues)) { | |
813 | for (i = 0; i < adapter->num_rx_queues; i++) | |
814 | igb_map_rx_ring_to_vector(adapter, i, v_idx++); | |
815 | for (i = 0; i < adapter->num_tx_queues; i++) | |
816 | igb_map_tx_ring_to_vector(adapter, i, v_idx++); | |
817 | } else { | |
818 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
819 | if (i < adapter->num_tx_queues) | |
820 | igb_map_tx_ring_to_vector(adapter, i, v_idx); | |
821 | igb_map_rx_ring_to_vector(adapter, i, v_idx++); | |
822 | } | |
823 | for (; i < adapter->num_tx_queues; i++) | |
824 | igb_map_tx_ring_to_vector(adapter, i, v_idx++); | |
825 | } | |
826 | return 0; | |
827 | } | |
828 | ||
829 | /** | |
830 | * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors | |
831 | * | |
832 | * This function initializes the interrupts and allocates all of the queues. | |
833 | **/ | |
834 | static int igb_init_interrupt_scheme(struct igb_adapter *adapter) | |
835 | { | |
836 | struct pci_dev *pdev = adapter->pdev; | |
837 | int err; | |
838 | ||
839 | igb_set_interrupt_capability(adapter); | |
840 | ||
841 | err = igb_alloc_q_vectors(adapter); | |
842 | if (err) { | |
843 | dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); | |
844 | goto err_alloc_q_vectors; | |
845 | } | |
846 | ||
847 | err = igb_alloc_queues(adapter); | |
848 | if (err) { | |
849 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | |
850 | goto err_alloc_queues; | |
851 | } | |
852 | ||
853 | err = igb_map_ring_to_vector(adapter); | |
854 | if (err) { | |
855 | dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n"); | |
856 | goto err_map_queues; | |
857 | } | |
858 | ||
859 | ||
860 | return 0; | |
861 | err_map_queues: | |
862 | igb_free_queues(adapter); | |
863 | err_alloc_queues: | |
864 | igb_free_q_vectors(adapter); | |
865 | err_alloc_q_vectors: | |
866 | igb_reset_interrupt_capability(adapter); | |
867 | return err; | |
868 | } | |
869 | ||
9d5c8243 AK |
870 | /** |
871 | * igb_request_irq - initialize interrupts | |
872 | * | |
873 | * Attempts to configure interrupts using the best available | |
874 | * capabilities of the hardware and kernel. | |
875 | **/ | |
876 | static int igb_request_irq(struct igb_adapter *adapter) | |
877 | { | |
878 | struct net_device *netdev = adapter->netdev; | |
047e0030 | 879 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
880 | struct e1000_hw *hw = &adapter->hw; |
881 | int err = 0; | |
882 | ||
883 | if (adapter->msix_entries) { | |
884 | err = igb_request_msix(adapter); | |
844290e5 | 885 | if (!err) |
9d5c8243 | 886 | goto request_done; |
9d5c8243 | 887 | /* fall back to MSI */ |
047e0030 | 888 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 | 889 | if (!pci_enable_msi(adapter->pdev)) |
7dfc16fa | 890 | adapter->flags |= IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
891 | igb_free_all_tx_resources(adapter); |
892 | igb_free_all_rx_resources(adapter); | |
047e0030 | 893 | adapter->num_tx_queues = 1; |
9d5c8243 | 894 | adapter->num_rx_queues = 1; |
047e0030 AD |
895 | adapter->num_q_vectors = 1; |
896 | err = igb_alloc_q_vectors(adapter); | |
897 | if (err) { | |
898 | dev_err(&pdev->dev, | |
899 | "Unable to allocate memory for vectors\n"); | |
900 | goto request_done; | |
901 | } | |
902 | err = igb_alloc_queues(adapter); | |
903 | if (err) { | |
904 | dev_err(&pdev->dev, | |
905 | "Unable to allocate memory for queues\n"); | |
906 | igb_free_q_vectors(adapter); | |
907 | goto request_done; | |
908 | } | |
909 | igb_setup_all_tx_resources(adapter); | |
910 | igb_setup_all_rx_resources(adapter); | |
844290e5 | 911 | } else { |
2d064c06 AD |
912 | switch (hw->mac.type) { |
913 | case e1000_82575: | |
914 | wr32(E1000_MSIXBM(0), | |
047e0030 AD |
915 | (E1000_EICR_RX_QUEUE0 | |
916 | E1000_EICR_TX_QUEUE0 | | |
917 | E1000_EIMS_OTHER)); | |
2d064c06 | 918 | break; |
55cac248 | 919 | case e1000_82580: |
2d064c06 AD |
920 | case e1000_82576: |
921 | wr32(E1000_IVAR0, E1000_IVAR_VALID); | |
922 | break; | |
923 | default: | |
924 | break; | |
925 | } | |
9d5c8243 | 926 | } |
844290e5 | 927 | |
7dfc16fa | 928 | if (adapter->flags & IGB_FLAG_HAS_MSI) { |
a0607fd3 | 929 | err = request_irq(adapter->pdev->irq, igb_intr_msi, 0, |
047e0030 | 930 | netdev->name, adapter); |
9d5c8243 AK |
931 | if (!err) |
932 | goto request_done; | |
047e0030 | 933 | |
9d5c8243 AK |
934 | /* fall back to legacy interrupts */ |
935 | igb_reset_interrupt_capability(adapter); | |
7dfc16fa | 936 | adapter->flags &= ~IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
937 | } |
938 | ||
a0607fd3 | 939 | err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED, |
047e0030 | 940 | netdev->name, adapter); |
9d5c8243 | 941 | |
6cb5e577 | 942 | if (err) |
9d5c8243 AK |
943 | dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n", |
944 | err); | |
9d5c8243 AK |
945 | |
946 | request_done: | |
947 | return err; | |
948 | } | |
949 | ||
950 | static void igb_free_irq(struct igb_adapter *adapter) | |
951 | { | |
9d5c8243 AK |
952 | if (adapter->msix_entries) { |
953 | int vector = 0, i; | |
954 | ||
047e0030 | 955 | free_irq(adapter->msix_entries[vector++].vector, adapter); |
9d5c8243 | 956 | |
047e0030 AD |
957 | for (i = 0; i < adapter->num_q_vectors; i++) { |
958 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
959 | free_irq(adapter->msix_entries[vector++].vector, | |
960 | q_vector); | |
961 | } | |
962 | } else { | |
963 | free_irq(adapter->pdev->irq, adapter); | |
9d5c8243 | 964 | } |
9d5c8243 AK |
965 | } |
966 | ||
967 | /** | |
968 | * igb_irq_disable - Mask off interrupt generation on the NIC | |
969 | * @adapter: board private structure | |
970 | **/ | |
971 | static void igb_irq_disable(struct igb_adapter *adapter) | |
972 | { | |
973 | struct e1000_hw *hw = &adapter->hw; | |
974 | ||
25568a53 AD |
975 | /* |
976 | * we need to be careful when disabling interrupts. The VFs are also | |
977 | * mapped into these registers and so clearing the bits can cause | |
978 | * issues on the VF drivers so we only need to clear what we set | |
979 | */ | |
9d5c8243 | 980 | if (adapter->msix_entries) { |
2dfd1212 AD |
981 | u32 regval = rd32(E1000_EIAM); |
982 | wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); | |
983 | wr32(E1000_EIMC, adapter->eims_enable_mask); | |
984 | regval = rd32(E1000_EIAC); | |
985 | wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); | |
9d5c8243 | 986 | } |
844290e5 PW |
987 | |
988 | wr32(E1000_IAM, 0); | |
9d5c8243 AK |
989 | wr32(E1000_IMC, ~0); |
990 | wrfl(); | |
991 | synchronize_irq(adapter->pdev->irq); | |
992 | } | |
993 | ||
994 | /** | |
995 | * igb_irq_enable - Enable default interrupt generation settings | |
996 | * @adapter: board private structure | |
997 | **/ | |
998 | static void igb_irq_enable(struct igb_adapter *adapter) | |
999 | { | |
1000 | struct e1000_hw *hw = &adapter->hw; | |
1001 | ||
1002 | if (adapter->msix_entries) { | |
25568a53 | 1003 | u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC; |
2dfd1212 AD |
1004 | u32 regval = rd32(E1000_EIAC); |
1005 | wr32(E1000_EIAC, regval | adapter->eims_enable_mask); | |
1006 | regval = rd32(E1000_EIAM); | |
1007 | wr32(E1000_EIAM, regval | adapter->eims_enable_mask); | |
844290e5 | 1008 | wr32(E1000_EIMS, adapter->eims_enable_mask); |
25568a53 | 1009 | if (adapter->vfs_allocated_count) { |
4ae196df | 1010 | wr32(E1000_MBVFIMR, 0xFF); |
25568a53 AD |
1011 | ims |= E1000_IMS_VMMB; |
1012 | } | |
55cac248 AD |
1013 | if (adapter->hw.mac.type == e1000_82580) |
1014 | ims |= E1000_IMS_DRSTA; | |
1015 | ||
25568a53 | 1016 | wr32(E1000_IMS, ims); |
844290e5 | 1017 | } else { |
55cac248 AD |
1018 | wr32(E1000_IMS, IMS_ENABLE_MASK | |
1019 | E1000_IMS_DRSTA); | |
1020 | wr32(E1000_IAM, IMS_ENABLE_MASK | | |
1021 | E1000_IMS_DRSTA); | |
844290e5 | 1022 | } |
9d5c8243 AK |
1023 | } |
1024 | ||
1025 | static void igb_update_mng_vlan(struct igb_adapter *adapter) | |
1026 | { | |
51466239 | 1027 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
1028 | u16 vid = adapter->hw.mng_cookie.vlan_id; |
1029 | u16 old_vid = adapter->mng_vlan_id; | |
51466239 AD |
1030 | |
1031 | if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { | |
1032 | /* add VID to filter table */ | |
1033 | igb_vfta_set(hw, vid, true); | |
1034 | adapter->mng_vlan_id = vid; | |
1035 | } else { | |
1036 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
1037 | } | |
1038 | ||
1039 | if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && | |
1040 | (vid != old_vid) && | |
1041 | !vlan_group_get_device(adapter->vlgrp, old_vid)) { | |
1042 | /* remove VID from filter table */ | |
1043 | igb_vfta_set(hw, old_vid, false); | |
9d5c8243 AK |
1044 | } |
1045 | } | |
1046 | ||
1047 | /** | |
1048 | * igb_release_hw_control - release control of the h/w to f/w | |
1049 | * @adapter: address of board private structure | |
1050 | * | |
1051 | * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. | |
1052 | * For ASF and Pass Through versions of f/w this means that the | |
1053 | * driver is no longer loaded. | |
1054 | * | |
1055 | **/ | |
1056 | static void igb_release_hw_control(struct igb_adapter *adapter) | |
1057 | { | |
1058 | struct e1000_hw *hw = &adapter->hw; | |
1059 | u32 ctrl_ext; | |
1060 | ||
1061 | /* Let firmware take over control of h/w */ | |
1062 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
1063 | wr32(E1000_CTRL_EXT, | |
1064 | ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); | |
1065 | } | |
1066 | ||
9d5c8243 AK |
1067 | /** |
1068 | * igb_get_hw_control - get control of the h/w from f/w | |
1069 | * @adapter: address of board private structure | |
1070 | * | |
1071 | * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. | |
1072 | * For ASF and Pass Through versions of f/w this means that | |
1073 | * the driver is loaded. | |
1074 | * | |
1075 | **/ | |
1076 | static void igb_get_hw_control(struct igb_adapter *adapter) | |
1077 | { | |
1078 | struct e1000_hw *hw = &adapter->hw; | |
1079 | u32 ctrl_ext; | |
1080 | ||
1081 | /* Let firmware know the driver has taken over */ | |
1082 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
1083 | wr32(E1000_CTRL_EXT, | |
1084 | ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); | |
1085 | } | |
1086 | ||
9d5c8243 AK |
1087 | /** |
1088 | * igb_configure - configure the hardware for RX and TX | |
1089 | * @adapter: private board structure | |
1090 | **/ | |
1091 | static void igb_configure(struct igb_adapter *adapter) | |
1092 | { | |
1093 | struct net_device *netdev = adapter->netdev; | |
1094 | int i; | |
1095 | ||
1096 | igb_get_hw_control(adapter); | |
ff41f8dc | 1097 | igb_set_rx_mode(netdev); |
9d5c8243 AK |
1098 | |
1099 | igb_restore_vlan(adapter); | |
9d5c8243 | 1100 | |
85b430b4 | 1101 | igb_setup_tctl(adapter); |
06cf2666 | 1102 | igb_setup_mrqc(adapter); |
9d5c8243 | 1103 | igb_setup_rctl(adapter); |
85b430b4 AD |
1104 | |
1105 | igb_configure_tx(adapter); | |
9d5c8243 | 1106 | igb_configure_rx(adapter); |
662d7205 AD |
1107 | |
1108 | igb_rx_fifo_flush_82575(&adapter->hw); | |
1109 | ||
c493ea45 | 1110 | /* call igb_desc_unused which always leaves |
9d5c8243 AK |
1111 | * at least 1 descriptor unused to make sure |
1112 | * next_to_use != next_to_clean */ | |
1113 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1114 | struct igb_ring *ring = &adapter->rx_ring[i]; | |
c493ea45 | 1115 | igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring)); |
9d5c8243 AK |
1116 | } |
1117 | ||
1118 | ||
1119 | adapter->tx_queue_len = netdev->tx_queue_len; | |
1120 | } | |
1121 | ||
1122 | ||
1123 | /** | |
1124 | * igb_up - Open the interface and prepare it to handle traffic | |
1125 | * @adapter: board private structure | |
1126 | **/ | |
9d5c8243 AK |
1127 | int igb_up(struct igb_adapter *adapter) |
1128 | { | |
1129 | struct e1000_hw *hw = &adapter->hw; | |
1130 | int i; | |
1131 | ||
1132 | /* hardware has been reset, we need to reload some things */ | |
1133 | igb_configure(adapter); | |
1134 | ||
1135 | clear_bit(__IGB_DOWN, &adapter->state); | |
1136 | ||
047e0030 AD |
1137 | for (i = 0; i < adapter->num_q_vectors; i++) { |
1138 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
1139 | napi_enable(&q_vector->napi); | |
1140 | } | |
844290e5 | 1141 | if (adapter->msix_entries) |
9d5c8243 | 1142 | igb_configure_msix(adapter); |
9d5c8243 AK |
1143 | |
1144 | /* Clear any pending interrupts. */ | |
1145 | rd32(E1000_ICR); | |
1146 | igb_irq_enable(adapter); | |
1147 | ||
d4960307 AD |
1148 | /* notify VFs that reset has been completed */ |
1149 | if (adapter->vfs_allocated_count) { | |
1150 | u32 reg_data = rd32(E1000_CTRL_EXT); | |
1151 | reg_data |= E1000_CTRL_EXT_PFRSTD; | |
1152 | wr32(E1000_CTRL_EXT, reg_data); | |
1153 | } | |
1154 | ||
4cb9be7a JB |
1155 | netif_tx_start_all_queues(adapter->netdev); |
1156 | ||
25568a53 AD |
1157 | /* start the watchdog. */ |
1158 | hw->mac.get_link_status = 1; | |
1159 | schedule_work(&adapter->watchdog_task); | |
1160 | ||
9d5c8243 AK |
1161 | return 0; |
1162 | } | |
1163 | ||
1164 | void igb_down(struct igb_adapter *adapter) | |
1165 | { | |
9d5c8243 | 1166 | struct net_device *netdev = adapter->netdev; |
330a6d6a | 1167 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
1168 | u32 tctl, rctl; |
1169 | int i; | |
1170 | ||
1171 | /* signal that we're down so the interrupt handler does not | |
1172 | * reschedule our watchdog timer */ | |
1173 | set_bit(__IGB_DOWN, &adapter->state); | |
1174 | ||
1175 | /* disable receives in the hardware */ | |
1176 | rctl = rd32(E1000_RCTL); | |
1177 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | |
1178 | /* flush and sleep below */ | |
1179 | ||
fd2ea0a7 | 1180 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
1181 | |
1182 | /* disable transmits in the hardware */ | |
1183 | tctl = rd32(E1000_TCTL); | |
1184 | tctl &= ~E1000_TCTL_EN; | |
1185 | wr32(E1000_TCTL, tctl); | |
1186 | /* flush both disables and wait for them to finish */ | |
1187 | wrfl(); | |
1188 | msleep(10); | |
1189 | ||
047e0030 AD |
1190 | for (i = 0; i < adapter->num_q_vectors; i++) { |
1191 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
1192 | napi_disable(&q_vector->napi); | |
1193 | } | |
9d5c8243 | 1194 | |
9d5c8243 AK |
1195 | igb_irq_disable(adapter); |
1196 | ||
1197 | del_timer_sync(&adapter->watchdog_timer); | |
1198 | del_timer_sync(&adapter->phy_info_timer); | |
1199 | ||
1200 | netdev->tx_queue_len = adapter->tx_queue_len; | |
1201 | netif_carrier_off(netdev); | |
04fe6358 AD |
1202 | |
1203 | /* record the stats before reset*/ | |
1204 | igb_update_stats(adapter); | |
1205 | ||
9d5c8243 AK |
1206 | adapter->link_speed = 0; |
1207 | adapter->link_duplex = 0; | |
1208 | ||
3023682e JK |
1209 | if (!pci_channel_offline(adapter->pdev)) |
1210 | igb_reset(adapter); | |
9d5c8243 AK |
1211 | igb_clean_all_tx_rings(adapter); |
1212 | igb_clean_all_rx_rings(adapter); | |
7e0e99ef AD |
1213 | #ifdef CONFIG_IGB_DCA |
1214 | ||
1215 | /* since we reset the hardware DCA settings were cleared */ | |
1216 | igb_setup_dca(adapter); | |
1217 | #endif | |
9d5c8243 AK |
1218 | } |
1219 | ||
1220 | void igb_reinit_locked(struct igb_adapter *adapter) | |
1221 | { | |
1222 | WARN_ON(in_interrupt()); | |
1223 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
1224 | msleep(1); | |
1225 | igb_down(adapter); | |
1226 | igb_up(adapter); | |
1227 | clear_bit(__IGB_RESETTING, &adapter->state); | |
1228 | } | |
1229 | ||
1230 | void igb_reset(struct igb_adapter *adapter) | |
1231 | { | |
090b1795 | 1232 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 | 1233 | struct e1000_hw *hw = &adapter->hw; |
2d064c06 AD |
1234 | struct e1000_mac_info *mac = &hw->mac; |
1235 | struct e1000_fc_info *fc = &hw->fc; | |
9d5c8243 AK |
1236 | u32 pba = 0, tx_space, min_tx_space, min_rx_space; |
1237 | u16 hwm; | |
1238 | ||
1239 | /* Repartition Pba for greater than 9k mtu | |
1240 | * To take effect CTRL.RST is required. | |
1241 | */ | |
fa4dfae0 | 1242 | switch (mac->type) { |
55cac248 AD |
1243 | case e1000_82580: |
1244 | pba = rd32(E1000_RXPBS); | |
1245 | pba = igb_rxpbs_adjust_82580(pba); | |
1246 | break; | |
fa4dfae0 | 1247 | case e1000_82576: |
d249be54 AD |
1248 | pba = rd32(E1000_RXPBS); |
1249 | pba &= E1000_RXPBS_SIZE_MASK_82576; | |
fa4dfae0 AD |
1250 | break; |
1251 | case e1000_82575: | |
1252 | default: | |
1253 | pba = E1000_PBA_34K; | |
1254 | break; | |
2d064c06 | 1255 | } |
9d5c8243 | 1256 | |
2d064c06 AD |
1257 | if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && |
1258 | (mac->type < e1000_82576)) { | |
9d5c8243 AK |
1259 | /* adjust PBA for jumbo frames */ |
1260 | wr32(E1000_PBA, pba); | |
1261 | ||
1262 | /* To maintain wire speed transmits, the Tx FIFO should be | |
1263 | * large enough to accommodate two full transmit packets, | |
1264 | * rounded up to the next 1KB and expressed in KB. Likewise, | |
1265 | * the Rx FIFO should be large enough to accommodate at least | |
1266 | * one full receive packet and is similarly rounded up and | |
1267 | * expressed in KB. */ | |
1268 | pba = rd32(E1000_PBA); | |
1269 | /* upper 16 bits has Tx packet buffer allocation size in KB */ | |
1270 | tx_space = pba >> 16; | |
1271 | /* lower 16 bits has Rx packet buffer allocation size in KB */ | |
1272 | pba &= 0xffff; | |
1273 | /* the tx fifo also stores 16 bytes of information about the tx | |
1274 | * but don't include ethernet FCS because hardware appends it */ | |
1275 | min_tx_space = (adapter->max_frame_size + | |
85e8d004 | 1276 | sizeof(union e1000_adv_tx_desc) - |
9d5c8243 AK |
1277 | ETH_FCS_LEN) * 2; |
1278 | min_tx_space = ALIGN(min_tx_space, 1024); | |
1279 | min_tx_space >>= 10; | |
1280 | /* software strips receive CRC, so leave room for it */ | |
1281 | min_rx_space = adapter->max_frame_size; | |
1282 | min_rx_space = ALIGN(min_rx_space, 1024); | |
1283 | min_rx_space >>= 10; | |
1284 | ||
1285 | /* If current Tx allocation is less than the min Tx FIFO size, | |
1286 | * and the min Tx FIFO size is less than the current Rx FIFO | |
1287 | * allocation, take space away from current Rx allocation */ | |
1288 | if (tx_space < min_tx_space && | |
1289 | ((min_tx_space - tx_space) < pba)) { | |
1290 | pba = pba - (min_tx_space - tx_space); | |
1291 | ||
1292 | /* if short on rx space, rx wins and must trump tx | |
1293 | * adjustment */ | |
1294 | if (pba < min_rx_space) | |
1295 | pba = min_rx_space; | |
1296 | } | |
2d064c06 | 1297 | wr32(E1000_PBA, pba); |
9d5c8243 | 1298 | } |
9d5c8243 AK |
1299 | |
1300 | /* flow control settings */ | |
1301 | /* The high water mark must be low enough to fit one full frame | |
1302 | * (or the size used for early receive) above it in the Rx FIFO. | |
1303 | * Set it to the lower of: | |
1304 | * - 90% of the Rx FIFO size, or | |
1305 | * - the full Rx FIFO size minus one full frame */ | |
1306 | hwm = min(((pba << 10) * 9 / 10), | |
2d064c06 | 1307 | ((pba << 10) - 2 * adapter->max_frame_size)); |
9d5c8243 | 1308 | |
2d064c06 AD |
1309 | if (mac->type < e1000_82576) { |
1310 | fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */ | |
1311 | fc->low_water = fc->high_water - 8; | |
1312 | } else { | |
1313 | fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ | |
1314 | fc->low_water = fc->high_water - 16; | |
1315 | } | |
9d5c8243 AK |
1316 | fc->pause_time = 0xFFFF; |
1317 | fc->send_xon = 1; | |
0cce119a | 1318 | fc->current_mode = fc->requested_mode; |
9d5c8243 | 1319 | |
4ae196df AD |
1320 | /* disable receive for all VFs and wait one second */ |
1321 | if (adapter->vfs_allocated_count) { | |
1322 | int i; | |
1323 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) | |
f2ca0dbe | 1324 | adapter->vf_data[i].flags = 0; |
4ae196df AD |
1325 | |
1326 | /* ping all the active vfs to let them know we are going down */ | |
f2ca0dbe | 1327 | igb_ping_all_vfs(adapter); |
4ae196df AD |
1328 | |
1329 | /* disable transmits and receives */ | |
1330 | wr32(E1000_VFRE, 0); | |
1331 | wr32(E1000_VFTE, 0); | |
1332 | } | |
1333 | ||
9d5c8243 | 1334 | /* Allow time for pending master requests to run */ |
330a6d6a | 1335 | hw->mac.ops.reset_hw(hw); |
9d5c8243 AK |
1336 | wr32(E1000_WUC, 0); |
1337 | ||
330a6d6a | 1338 | if (hw->mac.ops.init_hw(hw)) |
090b1795 | 1339 | dev_err(&pdev->dev, "Hardware Error\n"); |
9d5c8243 | 1340 | |
55cac248 AD |
1341 | if (hw->mac.type == e1000_82580) { |
1342 | u32 reg = rd32(E1000_PCIEMISC); | |
1343 | wr32(E1000_PCIEMISC, | |
1344 | reg & ~E1000_PCIEMISC_LX_DECISION); | |
1345 | } | |
9d5c8243 AK |
1346 | igb_update_mng_vlan(adapter); |
1347 | ||
1348 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | |
1349 | wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); | |
1350 | ||
330a6d6a AD |
1351 | igb_reset_adaptive(hw); |
1352 | igb_get_phy_info(hw); | |
9d5c8243 AK |
1353 | } |
1354 | ||
2e5c6922 | 1355 | static const struct net_device_ops igb_netdev_ops = { |
559e9c49 | 1356 | .ndo_open = igb_open, |
2e5c6922 | 1357 | .ndo_stop = igb_close, |
00829823 | 1358 | .ndo_start_xmit = igb_xmit_frame_adv, |
2e5c6922 | 1359 | .ndo_get_stats = igb_get_stats, |
ff41f8dc AD |
1360 | .ndo_set_rx_mode = igb_set_rx_mode, |
1361 | .ndo_set_multicast_list = igb_set_rx_mode, | |
2e5c6922 SH |
1362 | .ndo_set_mac_address = igb_set_mac, |
1363 | .ndo_change_mtu = igb_change_mtu, | |
1364 | .ndo_do_ioctl = igb_ioctl, | |
1365 | .ndo_tx_timeout = igb_tx_timeout, | |
1366 | .ndo_validate_addr = eth_validate_addr, | |
1367 | .ndo_vlan_rx_register = igb_vlan_rx_register, | |
1368 | .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, | |
1369 | .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, | |
1370 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1371 | .ndo_poll_controller = igb_netpoll, | |
1372 | #endif | |
1373 | }; | |
1374 | ||
9d5c8243 AK |
1375 | /** |
1376 | * igb_probe - Device Initialization Routine | |
1377 | * @pdev: PCI device information struct | |
1378 | * @ent: entry in igb_pci_tbl | |
1379 | * | |
1380 | * Returns 0 on success, negative on failure | |
1381 | * | |
1382 | * igb_probe initializes an adapter identified by a pci_dev structure. | |
1383 | * The OS initialization, configuring of the adapter private structure, | |
1384 | * and a hardware reset occur. | |
1385 | **/ | |
1386 | static int __devinit igb_probe(struct pci_dev *pdev, | |
1387 | const struct pci_device_id *ent) | |
1388 | { | |
1389 | struct net_device *netdev; | |
1390 | struct igb_adapter *adapter; | |
1391 | struct e1000_hw *hw; | |
4337e993 AD |
1392 | u16 eeprom_data = 0; |
1393 | static int global_quad_port_a; /* global quad port a indication */ | |
9d5c8243 AK |
1394 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; |
1395 | unsigned long mmio_start, mmio_len; | |
2d6a5e95 | 1396 | int err, pci_using_dac; |
9d5c8243 AK |
1397 | u16 eeprom_apme_mask = IGB_EEPROM_APME; |
1398 | u32 part_num; | |
1399 | ||
aed5dec3 | 1400 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
1401 | if (err) |
1402 | return err; | |
1403 | ||
1404 | pci_using_dac = 0; | |
6a35528a | 1405 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
9d5c8243 | 1406 | if (!err) { |
6a35528a | 1407 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
9d5c8243 AK |
1408 | if (!err) |
1409 | pci_using_dac = 1; | |
1410 | } else { | |
284901a9 | 1411 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
9d5c8243 | 1412 | if (err) { |
284901a9 | 1413 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
9d5c8243 AK |
1414 | if (err) { |
1415 | dev_err(&pdev->dev, "No usable DMA " | |
1416 | "configuration, aborting\n"); | |
1417 | goto err_dma; | |
1418 | } | |
1419 | } | |
1420 | } | |
1421 | ||
aed5dec3 AD |
1422 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
1423 | IORESOURCE_MEM), | |
1424 | igb_driver_name); | |
9d5c8243 AK |
1425 | if (err) |
1426 | goto err_pci_reg; | |
1427 | ||
19d5afd4 | 1428 | pci_enable_pcie_error_reporting(pdev); |
40a914fa | 1429 | |
9d5c8243 | 1430 | pci_set_master(pdev); |
c682fc23 | 1431 | pci_save_state(pdev); |
9d5c8243 AK |
1432 | |
1433 | err = -ENOMEM; | |
1bfaf07b AD |
1434 | netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), |
1435 | IGB_ABS_MAX_TX_QUEUES); | |
9d5c8243 AK |
1436 | if (!netdev) |
1437 | goto err_alloc_etherdev; | |
1438 | ||
1439 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
1440 | ||
1441 | pci_set_drvdata(pdev, netdev); | |
1442 | adapter = netdev_priv(netdev); | |
1443 | adapter->netdev = netdev; | |
1444 | adapter->pdev = pdev; | |
1445 | hw = &adapter->hw; | |
1446 | hw->back = adapter; | |
1447 | adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE; | |
1448 | ||
1449 | mmio_start = pci_resource_start(pdev, 0); | |
1450 | mmio_len = pci_resource_len(pdev, 0); | |
1451 | ||
1452 | err = -EIO; | |
28b0759c AD |
1453 | hw->hw_addr = ioremap(mmio_start, mmio_len); |
1454 | if (!hw->hw_addr) | |
9d5c8243 AK |
1455 | goto err_ioremap; |
1456 | ||
2e5c6922 | 1457 | netdev->netdev_ops = &igb_netdev_ops; |
9d5c8243 | 1458 | igb_set_ethtool_ops(netdev); |
9d5c8243 | 1459 | netdev->watchdog_timeo = 5 * HZ; |
9d5c8243 AK |
1460 | |
1461 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); | |
1462 | ||
1463 | netdev->mem_start = mmio_start; | |
1464 | netdev->mem_end = mmio_start + mmio_len; | |
1465 | ||
9d5c8243 AK |
1466 | /* PCI config space info */ |
1467 | hw->vendor_id = pdev->vendor; | |
1468 | hw->device_id = pdev->device; | |
1469 | hw->revision_id = pdev->revision; | |
1470 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
1471 | hw->subsystem_device_id = pdev->subsystem_device; | |
1472 | ||
9d5c8243 AK |
1473 | /* Copy the default MAC, PHY and NVM function pointers */ |
1474 | memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); | |
1475 | memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); | |
1476 | memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); | |
1477 | /* Initialize skew-specific constants */ | |
1478 | err = ei->get_invariants(hw); | |
1479 | if (err) | |
450c87c8 | 1480 | goto err_sw_init; |
9d5c8243 | 1481 | |
450c87c8 | 1482 | /* setup the private structure */ |
9d5c8243 AK |
1483 | err = igb_sw_init(adapter); |
1484 | if (err) | |
1485 | goto err_sw_init; | |
1486 | ||
1487 | igb_get_bus_info_pcie(hw); | |
1488 | ||
1489 | hw->phy.autoneg_wait_to_complete = false; | |
1490 | hw->mac.adaptive_ifs = true; | |
1491 | ||
1492 | /* Copper options */ | |
1493 | if (hw->phy.media_type == e1000_media_type_copper) { | |
1494 | hw->phy.mdix = AUTO_ALL_MODES; | |
1495 | hw->phy.disable_polarity_correction = false; | |
1496 | hw->phy.ms_type = e1000_ms_hw_default; | |
1497 | } | |
1498 | ||
1499 | if (igb_check_reset_block(hw)) | |
1500 | dev_info(&pdev->dev, | |
1501 | "PHY reset is blocked due to SOL/IDER session.\n"); | |
1502 | ||
1503 | netdev->features = NETIF_F_SG | | |
7d8eb29e | 1504 | NETIF_F_IP_CSUM | |
9d5c8243 AK |
1505 | NETIF_F_HW_VLAN_TX | |
1506 | NETIF_F_HW_VLAN_RX | | |
1507 | NETIF_F_HW_VLAN_FILTER; | |
1508 | ||
7d8eb29e | 1509 | netdev->features |= NETIF_F_IPV6_CSUM; |
9d5c8243 | 1510 | netdev->features |= NETIF_F_TSO; |
9d5c8243 | 1511 | netdev->features |= NETIF_F_TSO6; |
5c0999b7 | 1512 | netdev->features |= NETIF_F_GRO; |
d3352520 | 1513 | |
48f29ffc JK |
1514 | netdev->vlan_features |= NETIF_F_TSO; |
1515 | netdev->vlan_features |= NETIF_F_TSO6; | |
7d8eb29e | 1516 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 1517 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
48f29ffc JK |
1518 | netdev->vlan_features |= NETIF_F_SG; |
1519 | ||
9d5c8243 AK |
1520 | if (pci_using_dac) |
1521 | netdev->features |= NETIF_F_HIGHDMA; | |
1522 | ||
5b043fb0 | 1523 | if (hw->mac.type >= e1000_82576) |
b9473560 JB |
1524 | netdev->features |= NETIF_F_SCTP_CSUM; |
1525 | ||
330a6d6a | 1526 | adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); |
9d5c8243 AK |
1527 | |
1528 | /* before reading the NVM, reset the controller to put the device in a | |
1529 | * known good starting state */ | |
1530 | hw->mac.ops.reset_hw(hw); | |
1531 | ||
1532 | /* make sure the NVM is good */ | |
1533 | if (igb_validate_nvm_checksum(hw) < 0) { | |
1534 | dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); | |
1535 | err = -EIO; | |
1536 | goto err_eeprom; | |
1537 | } | |
1538 | ||
1539 | /* copy the MAC address out of the NVM */ | |
1540 | if (hw->mac.ops.read_mac_addr(hw)) | |
1541 | dev_err(&pdev->dev, "NVM Read Error\n"); | |
1542 | ||
1543 | memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); | |
1544 | memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); | |
1545 | ||
1546 | if (!is_valid_ether_addr(netdev->perm_addr)) { | |
1547 | dev_err(&pdev->dev, "Invalid MAC Address\n"); | |
1548 | err = -EIO; | |
1549 | goto err_eeprom; | |
1550 | } | |
1551 | ||
0e340485 AD |
1552 | setup_timer(&adapter->watchdog_timer, &igb_watchdog, |
1553 | (unsigned long) adapter); | |
1554 | setup_timer(&adapter->phy_info_timer, &igb_update_phy_info, | |
1555 | (unsigned long) adapter); | |
9d5c8243 AK |
1556 | |
1557 | INIT_WORK(&adapter->reset_task, igb_reset_task); | |
1558 | INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); | |
1559 | ||
450c87c8 | 1560 | /* Initialize link properties that are user-changeable */ |
9d5c8243 AK |
1561 | adapter->fc_autoneg = true; |
1562 | hw->mac.autoneg = true; | |
1563 | hw->phy.autoneg_advertised = 0x2f; | |
1564 | ||
0cce119a AD |
1565 | hw->fc.requested_mode = e1000_fc_default; |
1566 | hw->fc.current_mode = e1000_fc_default; | |
9d5c8243 | 1567 | |
9d5c8243 AK |
1568 | igb_validate_mdi_setting(hw); |
1569 | ||
9d5c8243 AK |
1570 | /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM, |
1571 | * enable the ACPI Magic Packet filter | |
1572 | */ | |
1573 | ||
a2cf8b6c | 1574 | if (hw->bus.func == 0) |
312c75ae | 1575 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); |
55cac248 AD |
1576 | else if (hw->mac.type == e1000_82580) |
1577 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + | |
1578 | NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, | |
1579 | &eeprom_data); | |
a2cf8b6c AD |
1580 | else if (hw->bus.func == 1) |
1581 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); | |
9d5c8243 AK |
1582 | |
1583 | if (eeprom_data & eeprom_apme_mask) | |
1584 | adapter->eeprom_wol |= E1000_WUFC_MAG; | |
1585 | ||
1586 | /* now that we have the eeprom settings, apply the special cases where | |
1587 | * the eeprom may be wrong or the board simply won't support wake on | |
1588 | * lan on a particular port */ | |
1589 | switch (pdev->device) { | |
1590 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
1591 | adapter->eeprom_wol = 0; | |
1592 | break; | |
1593 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
2d064c06 AD |
1594 | case E1000_DEV_ID_82576_FIBER: |
1595 | case E1000_DEV_ID_82576_SERDES: | |
9d5c8243 AK |
1596 | /* Wake events only supported on port A for dual fiber |
1597 | * regardless of eeprom setting */ | |
1598 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) | |
1599 | adapter->eeprom_wol = 0; | |
1600 | break; | |
c8ea5ea9 AD |
1601 | case E1000_DEV_ID_82576_QUAD_COPPER: |
1602 | /* if quad port adapter, disable WoL on all but port A */ | |
1603 | if (global_quad_port_a != 0) | |
1604 | adapter->eeprom_wol = 0; | |
1605 | else | |
1606 | adapter->flags |= IGB_FLAG_QUAD_PORT_A; | |
1607 | /* Reset for multiple quad port adapters */ | |
1608 | if (++global_quad_port_a == 4) | |
1609 | global_quad_port_a = 0; | |
1610 | break; | |
9d5c8243 AK |
1611 | } |
1612 | ||
1613 | /* initialize the wol settings based on the eeprom settings */ | |
1614 | adapter->wol = adapter->eeprom_wol; | |
e1b86d84 | 1615 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
9d5c8243 AK |
1616 | |
1617 | /* reset the hardware with the new settings */ | |
1618 | igb_reset(adapter); | |
1619 | ||
1620 | /* let the f/w know that the h/w is now under the control of the | |
1621 | * driver. */ | |
1622 | igb_get_hw_control(adapter); | |
1623 | ||
9d5c8243 AK |
1624 | strcpy(netdev->name, "eth%d"); |
1625 | err = register_netdev(netdev); | |
1626 | if (err) | |
1627 | goto err_register; | |
1628 | ||
b168dfc5 JB |
1629 | /* carrier off reporting is important to ethtool even BEFORE open */ |
1630 | netif_carrier_off(netdev); | |
1631 | ||
421e02f0 | 1632 | #ifdef CONFIG_IGB_DCA |
bbd98fe4 | 1633 | if (dca_add_requester(&pdev->dev) == 0) { |
7dfc16fa | 1634 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
fe4506b6 | 1635 | dev_info(&pdev->dev, "DCA enabled\n"); |
fe4506b6 JC |
1636 | igb_setup_dca(adapter); |
1637 | } | |
fe4506b6 | 1638 | |
38c845c7 | 1639 | #endif |
9d5c8243 AK |
1640 | dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); |
1641 | /* print bus type/speed/width info */ | |
7c510e4b | 1642 | dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", |
9d5c8243 | 1643 | netdev->name, |
559e9c49 AD |
1644 | ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : |
1645 | "unknown"), | |
59c3de89 AD |
1646 | ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : |
1647 | (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" : | |
1648 | (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" : | |
1649 | "unknown"), | |
7c510e4b | 1650 | netdev->dev_addr); |
9d5c8243 AK |
1651 | |
1652 | igb_read_part_num(hw, &part_num); | |
1653 | dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name, | |
1654 | (part_num >> 8), (part_num & 0xff)); | |
1655 | ||
1656 | dev_info(&pdev->dev, | |
1657 | "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", | |
1658 | adapter->msix_entries ? "MSI-X" : | |
7dfc16fa | 1659 | (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", |
9d5c8243 AK |
1660 | adapter->num_rx_queues, adapter->num_tx_queues); |
1661 | ||
9d5c8243 AK |
1662 | return 0; |
1663 | ||
1664 | err_register: | |
1665 | igb_release_hw_control(adapter); | |
1666 | err_eeprom: | |
1667 | if (!igb_check_reset_block(hw)) | |
f5f4cf08 | 1668 | igb_reset_phy(hw); |
9d5c8243 AK |
1669 | |
1670 | if (hw->flash_address) | |
1671 | iounmap(hw->flash_address); | |
9d5c8243 | 1672 | err_sw_init: |
047e0030 | 1673 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 AK |
1674 | iounmap(hw->hw_addr); |
1675 | err_ioremap: | |
1676 | free_netdev(netdev); | |
1677 | err_alloc_etherdev: | |
559e9c49 AD |
1678 | pci_release_selected_regions(pdev, |
1679 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9d5c8243 AK |
1680 | err_pci_reg: |
1681 | err_dma: | |
1682 | pci_disable_device(pdev); | |
1683 | return err; | |
1684 | } | |
1685 | ||
1686 | /** | |
1687 | * igb_remove - Device Removal Routine | |
1688 | * @pdev: PCI device information struct | |
1689 | * | |
1690 | * igb_remove is called by the PCI subsystem to alert the driver | |
1691 | * that it should release a PCI device. The could be caused by a | |
1692 | * Hot-Plug event, or because the driver is going to be removed from | |
1693 | * memory. | |
1694 | **/ | |
1695 | static void __devexit igb_remove(struct pci_dev *pdev) | |
1696 | { | |
1697 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1698 | struct igb_adapter *adapter = netdev_priv(netdev); | |
fe4506b6 | 1699 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
1700 | |
1701 | /* flush_scheduled work may reschedule our watchdog task, so | |
1702 | * explicitly disable watchdog tasks from being rescheduled */ | |
1703 | set_bit(__IGB_DOWN, &adapter->state); | |
1704 | del_timer_sync(&adapter->watchdog_timer); | |
1705 | del_timer_sync(&adapter->phy_info_timer); | |
1706 | ||
1707 | flush_scheduled_work(); | |
1708 | ||
421e02f0 | 1709 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 1710 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 JC |
1711 | dev_info(&pdev->dev, "DCA disabled\n"); |
1712 | dca_remove_requester(&pdev->dev); | |
7dfc16fa | 1713 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 1714 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
1715 | } |
1716 | #endif | |
1717 | ||
9d5c8243 AK |
1718 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
1719 | * would have already happened in close and is redundant. */ | |
1720 | igb_release_hw_control(adapter); | |
1721 | ||
1722 | unregister_netdev(netdev); | |
1723 | ||
330a6d6a AD |
1724 | if (!igb_check_reset_block(hw)) |
1725 | igb_reset_phy(hw); | |
9d5c8243 | 1726 | |
047e0030 | 1727 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 | 1728 | |
37680117 AD |
1729 | #ifdef CONFIG_PCI_IOV |
1730 | /* reclaim resources allocated to VFs */ | |
1731 | if (adapter->vf_data) { | |
1732 | /* disable iov and allow time for transactions to clear */ | |
1733 | pci_disable_sriov(pdev); | |
1734 | msleep(500); | |
1735 | ||
1736 | kfree(adapter->vf_data); | |
1737 | adapter->vf_data = NULL; | |
1738 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
1739 | msleep(100); | |
1740 | dev_info(&pdev->dev, "IOV Disabled\n"); | |
1741 | } | |
1742 | #endif | |
559e9c49 | 1743 | |
28b0759c AD |
1744 | iounmap(hw->hw_addr); |
1745 | if (hw->flash_address) | |
1746 | iounmap(hw->flash_address); | |
559e9c49 AD |
1747 | pci_release_selected_regions(pdev, |
1748 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9d5c8243 AK |
1749 | |
1750 | free_netdev(netdev); | |
1751 | ||
19d5afd4 | 1752 | pci_disable_pcie_error_reporting(pdev); |
40a914fa | 1753 | |
9d5c8243 AK |
1754 | pci_disable_device(pdev); |
1755 | } | |
1756 | ||
a6b623e0 AD |
1757 | /** |
1758 | * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space | |
1759 | * @adapter: board private structure to initialize | |
1760 | * | |
1761 | * This function initializes the vf specific data storage and then attempts to | |
1762 | * allocate the VFs. The reason for ordering it this way is because it is much | |
1763 | * mor expensive time wise to disable SR-IOV than it is to allocate and free | |
1764 | * the memory for the VFs. | |
1765 | **/ | |
1766 | static void __devinit igb_probe_vfs(struct igb_adapter * adapter) | |
1767 | { | |
1768 | #ifdef CONFIG_PCI_IOV | |
1769 | struct pci_dev *pdev = adapter->pdev; | |
1770 | ||
1771 | if (adapter->vfs_allocated_count > 7) | |
1772 | adapter->vfs_allocated_count = 7; | |
1773 | ||
1774 | if (adapter->vfs_allocated_count) { | |
1775 | adapter->vf_data = kcalloc(adapter->vfs_allocated_count, | |
1776 | sizeof(struct vf_data_storage), | |
1777 | GFP_KERNEL); | |
1778 | /* if allocation failed then we do not support SR-IOV */ | |
1779 | if (!adapter->vf_data) { | |
1780 | adapter->vfs_allocated_count = 0; | |
1781 | dev_err(&pdev->dev, "Unable to allocate memory for VF " | |
1782 | "Data Storage\n"); | |
1783 | } | |
1784 | } | |
1785 | ||
1786 | if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) { | |
1787 | kfree(adapter->vf_data); | |
1788 | adapter->vf_data = NULL; | |
1789 | #endif /* CONFIG_PCI_IOV */ | |
1790 | adapter->vfs_allocated_count = 0; | |
1791 | #ifdef CONFIG_PCI_IOV | |
1792 | } else { | |
1793 | unsigned char mac_addr[ETH_ALEN]; | |
1794 | int i; | |
1795 | dev_info(&pdev->dev, "%d vfs allocated\n", | |
1796 | adapter->vfs_allocated_count); | |
1797 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
1798 | random_ether_addr(mac_addr); | |
1799 | igb_set_vf_mac(adapter, i, mac_addr); | |
1800 | } | |
1801 | } | |
1802 | #endif /* CONFIG_PCI_IOV */ | |
1803 | } | |
1804 | ||
115f459a AD |
1805 | |
1806 | /** | |
1807 | * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp | |
1808 | * @adapter: board private structure to initialize | |
1809 | * | |
1810 | * igb_init_hw_timer initializes the function pointer and values for the hw | |
1811 | * timer found in hardware. | |
1812 | **/ | |
1813 | static void igb_init_hw_timer(struct igb_adapter *adapter) | |
1814 | { | |
1815 | struct e1000_hw *hw = &adapter->hw; | |
1816 | ||
1817 | switch (hw->mac.type) { | |
55cac248 AD |
1818 | case e1000_82580: |
1819 | memset(&adapter->cycles, 0, sizeof(adapter->cycles)); | |
1820 | adapter->cycles.read = igb_read_clock; | |
1821 | adapter->cycles.mask = CLOCKSOURCE_MASK(64); | |
1822 | adapter->cycles.mult = 1; | |
1823 | /* | |
1824 | * The 82580 timesync updates the system timer every 8ns by 8ns | |
1825 | * and the value cannot be shifted. Instead we need to shift | |
1826 | * the registers to generate a 64bit timer value. As a result | |
1827 | * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by | |
1828 | * 24 in order to generate a larger value for synchronization. | |
1829 | */ | |
1830 | adapter->cycles.shift = IGB_82580_TSYNC_SHIFT; | |
1831 | /* disable system timer temporarily by setting bit 31 */ | |
1832 | wr32(E1000_TSAUXC, 0x80000000); | |
1833 | wrfl(); | |
1834 | ||
1835 | /* Set registers so that rollover occurs soon to test this. */ | |
1836 | wr32(E1000_SYSTIMR, 0x00000000); | |
1837 | wr32(E1000_SYSTIML, 0x80000000); | |
1838 | wr32(E1000_SYSTIMH, 0x000000FF); | |
1839 | wrfl(); | |
1840 | ||
1841 | /* enable system timer by clearing bit 31 */ | |
1842 | wr32(E1000_TSAUXC, 0x0); | |
1843 | wrfl(); | |
1844 | ||
1845 | timecounter_init(&adapter->clock, | |
1846 | &adapter->cycles, | |
1847 | ktime_to_ns(ktime_get_real())); | |
1848 | /* | |
1849 | * Synchronize our NIC clock against system wall clock. NIC | |
1850 | * time stamp reading requires ~3us per sample, each sample | |
1851 | * was pretty stable even under load => only require 10 | |
1852 | * samples for each offset comparison. | |
1853 | */ | |
1854 | memset(&adapter->compare, 0, sizeof(adapter->compare)); | |
1855 | adapter->compare.source = &adapter->clock; | |
1856 | adapter->compare.target = ktime_get_real; | |
1857 | adapter->compare.num_samples = 10; | |
1858 | timecompare_update(&adapter->compare, 0); | |
1859 | break; | |
115f459a AD |
1860 | case e1000_82576: |
1861 | /* | |
1862 | * Initialize hardware timer: we keep it running just in case | |
1863 | * that some program needs it later on. | |
1864 | */ | |
1865 | memset(&adapter->cycles, 0, sizeof(adapter->cycles)); | |
1866 | adapter->cycles.read = igb_read_clock; | |
1867 | adapter->cycles.mask = CLOCKSOURCE_MASK(64); | |
1868 | adapter->cycles.mult = 1; | |
1869 | /** | |
1870 | * Scale the NIC clock cycle by a large factor so that | |
1871 | * relatively small clock corrections can be added or | |
1872 | * substracted at each clock tick. The drawbacks of a large | |
1873 | * factor are a) that the clock register overflows more quickly | |
1874 | * (not such a big deal) and b) that the increment per tick has | |
1875 | * to fit into 24 bits. As a result we need to use a shift of | |
1876 | * 19 so we can fit a value of 16 into the TIMINCA register. | |
1877 | */ | |
1878 | adapter->cycles.shift = IGB_82576_TSYNC_SHIFT; | |
1879 | wr32(E1000_TIMINCA, | |
1880 | (1 << E1000_TIMINCA_16NS_SHIFT) | | |
1881 | (16 << IGB_82576_TSYNC_SHIFT)); | |
1882 | ||
1883 | /* Set registers so that rollover occurs soon to test this. */ | |
1884 | wr32(E1000_SYSTIML, 0x00000000); | |
1885 | wr32(E1000_SYSTIMH, 0xFF800000); | |
1886 | wrfl(); | |
1887 | ||
1888 | timecounter_init(&adapter->clock, | |
1889 | &adapter->cycles, | |
1890 | ktime_to_ns(ktime_get_real())); | |
1891 | /* | |
1892 | * Synchronize our NIC clock against system wall clock. NIC | |
1893 | * time stamp reading requires ~3us per sample, each sample | |
1894 | * was pretty stable even under load => only require 10 | |
1895 | * samples for each offset comparison. | |
1896 | */ | |
1897 | memset(&adapter->compare, 0, sizeof(adapter->compare)); | |
1898 | adapter->compare.source = &adapter->clock; | |
1899 | adapter->compare.target = ktime_get_real; | |
1900 | adapter->compare.num_samples = 10; | |
1901 | timecompare_update(&adapter->compare, 0); | |
1902 | break; | |
1903 | case e1000_82575: | |
1904 | /* 82575 does not support timesync */ | |
1905 | default: | |
1906 | break; | |
1907 | } | |
1908 | ||
1909 | } | |
1910 | ||
9d5c8243 AK |
1911 | /** |
1912 | * igb_sw_init - Initialize general software structures (struct igb_adapter) | |
1913 | * @adapter: board private structure to initialize | |
1914 | * | |
1915 | * igb_sw_init initializes the Adapter private data structure. | |
1916 | * Fields are initialized based on PCI device information and | |
1917 | * OS network device settings (MTU size). | |
1918 | **/ | |
1919 | static int __devinit igb_sw_init(struct igb_adapter *adapter) | |
1920 | { | |
1921 | struct e1000_hw *hw = &adapter->hw; | |
1922 | struct net_device *netdev = adapter->netdev; | |
1923 | struct pci_dev *pdev = adapter->pdev; | |
1924 | ||
1925 | pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); | |
1926 | ||
68fd9910 AD |
1927 | adapter->tx_ring_count = IGB_DEFAULT_TXD; |
1928 | adapter->rx_ring_count = IGB_DEFAULT_RXD; | |
4fc82adf AD |
1929 | adapter->rx_itr_setting = IGB_DEFAULT_ITR; |
1930 | adapter->tx_itr_setting = IGB_DEFAULT_ITR; | |
1931 | ||
9d5c8243 AK |
1932 | adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
1933 | adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; | |
1934 | ||
a6b623e0 AD |
1935 | #ifdef CONFIG_PCI_IOV |
1936 | if (hw->mac.type == e1000_82576) | |
1937 | adapter->vfs_allocated_count = max_vfs; | |
1938 | ||
1939 | #endif /* CONFIG_PCI_IOV */ | |
a99955fc AD |
1940 | adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus()); |
1941 | ||
1942 | /* | |
1943 | * if rss_queues > 4 or vfs are going to be allocated with rss_queues | |
1944 | * then we should combine the queues into a queue pair in order to | |
1945 | * conserve interrupts due to limited supply | |
1946 | */ | |
1947 | if ((adapter->rss_queues > 4) || | |
1948 | ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6))) | |
1949 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; | |
1950 | ||
a6b623e0 | 1951 | /* This call may decrease the number of queues */ |
047e0030 | 1952 | if (igb_init_interrupt_scheme(adapter)) { |
9d5c8243 AK |
1953 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
1954 | return -ENOMEM; | |
1955 | } | |
1956 | ||
115f459a | 1957 | igb_init_hw_timer(adapter); |
a6b623e0 AD |
1958 | igb_probe_vfs(adapter); |
1959 | ||
9d5c8243 AK |
1960 | /* Explicitly disable IRQ since the NIC can be in any state. */ |
1961 | igb_irq_disable(adapter); | |
1962 | ||
1963 | set_bit(__IGB_DOWN, &adapter->state); | |
1964 | return 0; | |
1965 | } | |
1966 | ||
1967 | /** | |
1968 | * igb_open - Called when a network interface is made active | |
1969 | * @netdev: network interface device structure | |
1970 | * | |
1971 | * Returns 0 on success, negative value on failure | |
1972 | * | |
1973 | * The open entry point is called when a network interface is made | |
1974 | * active by the system (IFF_UP). At this point all resources needed | |
1975 | * for transmit and receive operations are allocated, the interrupt | |
1976 | * handler is registered with the OS, the watchdog timer is started, | |
1977 | * and the stack is notified that the interface is ready. | |
1978 | **/ | |
1979 | static int igb_open(struct net_device *netdev) | |
1980 | { | |
1981 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1982 | struct e1000_hw *hw = &adapter->hw; | |
1983 | int err; | |
1984 | int i; | |
1985 | ||
1986 | /* disallow open during test */ | |
1987 | if (test_bit(__IGB_TESTING, &adapter->state)) | |
1988 | return -EBUSY; | |
1989 | ||
b168dfc5 JB |
1990 | netif_carrier_off(netdev); |
1991 | ||
9d5c8243 AK |
1992 | /* allocate transmit descriptors */ |
1993 | err = igb_setup_all_tx_resources(adapter); | |
1994 | if (err) | |
1995 | goto err_setup_tx; | |
1996 | ||
1997 | /* allocate receive descriptors */ | |
1998 | err = igb_setup_all_rx_resources(adapter); | |
1999 | if (err) | |
2000 | goto err_setup_rx; | |
2001 | ||
2002 | /* e1000_power_up_phy(adapter); */ | |
2003 | ||
9d5c8243 AK |
2004 | /* before we allocate an interrupt, we must be ready to handle it. |
2005 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt | |
2006 | * as soon as we call pci_request_irq, so we have to setup our | |
2007 | * clean_rx handler before we do so. */ | |
2008 | igb_configure(adapter); | |
2009 | ||
2010 | err = igb_request_irq(adapter); | |
2011 | if (err) | |
2012 | goto err_req_irq; | |
2013 | ||
2014 | /* From here on the code is the same as igb_up() */ | |
2015 | clear_bit(__IGB_DOWN, &adapter->state); | |
2016 | ||
047e0030 AD |
2017 | for (i = 0; i < adapter->num_q_vectors; i++) { |
2018 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
2019 | napi_enable(&q_vector->napi); | |
2020 | } | |
9d5c8243 AK |
2021 | |
2022 | /* Clear any pending interrupts. */ | |
2023 | rd32(E1000_ICR); | |
844290e5 PW |
2024 | |
2025 | igb_irq_enable(adapter); | |
2026 | ||
d4960307 AD |
2027 | /* notify VFs that reset has been completed */ |
2028 | if (adapter->vfs_allocated_count) { | |
2029 | u32 reg_data = rd32(E1000_CTRL_EXT); | |
2030 | reg_data |= E1000_CTRL_EXT_PFRSTD; | |
2031 | wr32(E1000_CTRL_EXT, reg_data); | |
2032 | } | |
2033 | ||
d55b53ff JK |
2034 | netif_tx_start_all_queues(netdev); |
2035 | ||
25568a53 AD |
2036 | /* start the watchdog. */ |
2037 | hw->mac.get_link_status = 1; | |
2038 | schedule_work(&adapter->watchdog_task); | |
9d5c8243 AK |
2039 | |
2040 | return 0; | |
2041 | ||
2042 | err_req_irq: | |
2043 | igb_release_hw_control(adapter); | |
2044 | /* e1000_power_down_phy(adapter); */ | |
2045 | igb_free_all_rx_resources(adapter); | |
2046 | err_setup_rx: | |
2047 | igb_free_all_tx_resources(adapter); | |
2048 | err_setup_tx: | |
2049 | igb_reset(adapter); | |
2050 | ||
2051 | return err; | |
2052 | } | |
2053 | ||
2054 | /** | |
2055 | * igb_close - Disables a network interface | |
2056 | * @netdev: network interface device structure | |
2057 | * | |
2058 | * Returns 0, this is not allowed to fail | |
2059 | * | |
2060 | * The close entry point is called when an interface is de-activated | |
2061 | * by the OS. The hardware is still under the driver's control, but | |
2062 | * needs to be disabled. A global MAC reset is issued to stop the | |
2063 | * hardware, and all transmit and receive resources are freed. | |
2064 | **/ | |
2065 | static int igb_close(struct net_device *netdev) | |
2066 | { | |
2067 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2068 | ||
2069 | WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); | |
2070 | igb_down(adapter); | |
2071 | ||
2072 | igb_free_irq(adapter); | |
2073 | ||
2074 | igb_free_all_tx_resources(adapter); | |
2075 | igb_free_all_rx_resources(adapter); | |
2076 | ||
9d5c8243 AK |
2077 | return 0; |
2078 | } | |
2079 | ||
2080 | /** | |
2081 | * igb_setup_tx_resources - allocate Tx resources (Descriptors) | |
9d5c8243 AK |
2082 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
2083 | * | |
2084 | * Return 0 on success, negative on failure | |
2085 | **/ | |
80785298 | 2086 | int igb_setup_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 2087 | { |
80785298 | 2088 | struct pci_dev *pdev = tx_ring->pdev; |
9d5c8243 AK |
2089 | int size; |
2090 | ||
2091 | size = sizeof(struct igb_buffer) * tx_ring->count; | |
2092 | tx_ring->buffer_info = vmalloc(size); | |
2093 | if (!tx_ring->buffer_info) | |
2094 | goto err; | |
2095 | memset(tx_ring->buffer_info, 0, size); | |
2096 | ||
2097 | /* round up to nearest 4K */ | |
85e8d004 | 2098 | tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); |
9d5c8243 AK |
2099 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
2100 | ||
439705e1 AD |
2101 | tx_ring->desc = pci_alloc_consistent(pdev, |
2102 | tx_ring->size, | |
9d5c8243 AK |
2103 | &tx_ring->dma); |
2104 | ||
2105 | if (!tx_ring->desc) | |
2106 | goto err; | |
2107 | ||
9d5c8243 AK |
2108 | tx_ring->next_to_use = 0; |
2109 | tx_ring->next_to_clean = 0; | |
9d5c8243 AK |
2110 | return 0; |
2111 | ||
2112 | err: | |
2113 | vfree(tx_ring->buffer_info); | |
047e0030 | 2114 | dev_err(&pdev->dev, |
9d5c8243 AK |
2115 | "Unable to allocate memory for the transmit descriptor ring\n"); |
2116 | return -ENOMEM; | |
2117 | } | |
2118 | ||
2119 | /** | |
2120 | * igb_setup_all_tx_resources - wrapper to allocate Tx resources | |
2121 | * (Descriptors) for all queues | |
2122 | * @adapter: board private structure | |
2123 | * | |
2124 | * Return 0 on success, negative on failure | |
2125 | **/ | |
2126 | static int igb_setup_all_tx_resources(struct igb_adapter *adapter) | |
2127 | { | |
439705e1 | 2128 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2129 | int i, err = 0; |
2130 | ||
2131 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
80785298 | 2132 | err = igb_setup_tx_resources(&adapter->tx_ring[i]); |
9d5c8243 | 2133 | if (err) { |
439705e1 | 2134 | dev_err(&pdev->dev, |
9d5c8243 AK |
2135 | "Allocation for Tx Queue %u failed\n", i); |
2136 | for (i--; i >= 0; i--) | |
3b644cf6 | 2137 | igb_free_tx_resources(&adapter->tx_ring[i]); |
9d5c8243 AK |
2138 | break; |
2139 | } | |
2140 | } | |
2141 | ||
a99955fc | 2142 | for (i = 0; i < IGB_ABS_MAX_TX_QUEUES; i++) { |
439705e1 | 2143 | int r_idx = i % adapter->num_tx_queues; |
661086df | 2144 | adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx]; |
eebbbdba | 2145 | } |
9d5c8243 AK |
2146 | return err; |
2147 | } | |
2148 | ||
2149 | /** | |
85b430b4 AD |
2150 | * igb_setup_tctl - configure the transmit control registers |
2151 | * @adapter: Board private structure | |
9d5c8243 | 2152 | **/ |
d7ee5b3a | 2153 | void igb_setup_tctl(struct igb_adapter *adapter) |
9d5c8243 | 2154 | { |
9d5c8243 AK |
2155 | struct e1000_hw *hw = &adapter->hw; |
2156 | u32 tctl; | |
9d5c8243 | 2157 | |
85b430b4 AD |
2158 | /* disable queue 0 which is enabled by default on 82575 and 82576 */ |
2159 | wr32(E1000_TXDCTL(0), 0); | |
9d5c8243 AK |
2160 | |
2161 | /* Program the Transmit Control Register */ | |
9d5c8243 AK |
2162 | tctl = rd32(E1000_TCTL); |
2163 | tctl &= ~E1000_TCTL_CT; | |
2164 | tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | | |
2165 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | |
2166 | ||
2167 | igb_config_collision_dist(hw); | |
2168 | ||
9d5c8243 AK |
2169 | /* Enable transmits */ |
2170 | tctl |= E1000_TCTL_EN; | |
2171 | ||
2172 | wr32(E1000_TCTL, tctl); | |
2173 | } | |
2174 | ||
85b430b4 AD |
2175 | /** |
2176 | * igb_configure_tx_ring - Configure transmit ring after Reset | |
2177 | * @adapter: board private structure | |
2178 | * @ring: tx ring to configure | |
2179 | * | |
2180 | * Configure a transmit ring after a reset. | |
2181 | **/ | |
d7ee5b3a AD |
2182 | void igb_configure_tx_ring(struct igb_adapter *adapter, |
2183 | struct igb_ring *ring) | |
85b430b4 AD |
2184 | { |
2185 | struct e1000_hw *hw = &adapter->hw; | |
2186 | u32 txdctl; | |
2187 | u64 tdba = ring->dma; | |
2188 | int reg_idx = ring->reg_idx; | |
2189 | ||
2190 | /* disable the queue */ | |
2191 | txdctl = rd32(E1000_TXDCTL(reg_idx)); | |
2192 | wr32(E1000_TXDCTL(reg_idx), | |
2193 | txdctl & ~E1000_TXDCTL_QUEUE_ENABLE); | |
2194 | wrfl(); | |
2195 | mdelay(10); | |
2196 | ||
2197 | wr32(E1000_TDLEN(reg_idx), | |
2198 | ring->count * sizeof(union e1000_adv_tx_desc)); | |
2199 | wr32(E1000_TDBAL(reg_idx), | |
2200 | tdba & 0x00000000ffffffffULL); | |
2201 | wr32(E1000_TDBAH(reg_idx), tdba >> 32); | |
2202 | ||
fce99e34 AD |
2203 | ring->head = hw->hw_addr + E1000_TDH(reg_idx); |
2204 | ring->tail = hw->hw_addr + E1000_TDT(reg_idx); | |
2205 | writel(0, ring->head); | |
2206 | writel(0, ring->tail); | |
85b430b4 AD |
2207 | |
2208 | txdctl |= IGB_TX_PTHRESH; | |
2209 | txdctl |= IGB_TX_HTHRESH << 8; | |
2210 | txdctl |= IGB_TX_WTHRESH << 16; | |
2211 | ||
2212 | txdctl |= E1000_TXDCTL_QUEUE_ENABLE; | |
2213 | wr32(E1000_TXDCTL(reg_idx), txdctl); | |
2214 | } | |
2215 | ||
2216 | /** | |
2217 | * igb_configure_tx - Configure transmit Unit after Reset | |
2218 | * @adapter: board private structure | |
2219 | * | |
2220 | * Configure the Tx unit of the MAC after a reset. | |
2221 | **/ | |
2222 | static void igb_configure_tx(struct igb_adapter *adapter) | |
2223 | { | |
2224 | int i; | |
2225 | ||
2226 | for (i = 0; i < adapter->num_tx_queues; i++) | |
2227 | igb_configure_tx_ring(adapter, &adapter->tx_ring[i]); | |
85b430b4 AD |
2228 | } |
2229 | ||
9d5c8243 AK |
2230 | /** |
2231 | * igb_setup_rx_resources - allocate Rx resources (Descriptors) | |
9d5c8243 AK |
2232 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
2233 | * | |
2234 | * Returns 0 on success, negative on failure | |
2235 | **/ | |
80785298 | 2236 | int igb_setup_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 2237 | { |
80785298 | 2238 | struct pci_dev *pdev = rx_ring->pdev; |
9d5c8243 AK |
2239 | int size, desc_len; |
2240 | ||
2241 | size = sizeof(struct igb_buffer) * rx_ring->count; | |
2242 | rx_ring->buffer_info = vmalloc(size); | |
2243 | if (!rx_ring->buffer_info) | |
2244 | goto err; | |
2245 | memset(rx_ring->buffer_info, 0, size); | |
2246 | ||
2247 | desc_len = sizeof(union e1000_adv_rx_desc); | |
2248 | ||
2249 | /* Round up to nearest 4K */ | |
2250 | rx_ring->size = rx_ring->count * desc_len; | |
2251 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
2252 | ||
2253 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, | |
2254 | &rx_ring->dma); | |
2255 | ||
2256 | if (!rx_ring->desc) | |
2257 | goto err; | |
2258 | ||
2259 | rx_ring->next_to_clean = 0; | |
2260 | rx_ring->next_to_use = 0; | |
9d5c8243 | 2261 | |
9d5c8243 AK |
2262 | return 0; |
2263 | ||
2264 | err: | |
2265 | vfree(rx_ring->buffer_info); | |
439705e1 | 2266 | rx_ring->buffer_info = NULL; |
80785298 | 2267 | dev_err(&pdev->dev, "Unable to allocate memory for " |
9d5c8243 AK |
2268 | "the receive descriptor ring\n"); |
2269 | return -ENOMEM; | |
2270 | } | |
2271 | ||
2272 | /** | |
2273 | * igb_setup_all_rx_resources - wrapper to allocate Rx resources | |
2274 | * (Descriptors) for all queues | |
2275 | * @adapter: board private structure | |
2276 | * | |
2277 | * Return 0 on success, negative on failure | |
2278 | **/ | |
2279 | static int igb_setup_all_rx_resources(struct igb_adapter *adapter) | |
2280 | { | |
439705e1 | 2281 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2282 | int i, err = 0; |
2283 | ||
2284 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
80785298 | 2285 | err = igb_setup_rx_resources(&adapter->rx_ring[i]); |
9d5c8243 | 2286 | if (err) { |
439705e1 | 2287 | dev_err(&pdev->dev, |
9d5c8243 AK |
2288 | "Allocation for Rx Queue %u failed\n", i); |
2289 | for (i--; i >= 0; i--) | |
3b644cf6 | 2290 | igb_free_rx_resources(&adapter->rx_ring[i]); |
9d5c8243 AK |
2291 | break; |
2292 | } | |
2293 | } | |
2294 | ||
2295 | return err; | |
2296 | } | |
2297 | ||
06cf2666 AD |
2298 | /** |
2299 | * igb_setup_mrqc - configure the multiple receive queue control registers | |
2300 | * @adapter: Board private structure | |
2301 | **/ | |
2302 | static void igb_setup_mrqc(struct igb_adapter *adapter) | |
2303 | { | |
2304 | struct e1000_hw *hw = &adapter->hw; | |
2305 | u32 mrqc, rxcsum; | |
2306 | u32 j, num_rx_queues, shift = 0, shift2 = 0; | |
2307 | union e1000_reta { | |
2308 | u32 dword; | |
2309 | u8 bytes[4]; | |
2310 | } reta; | |
2311 | static const u8 rsshash[40] = { | |
2312 | 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67, | |
2313 | 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb, | |
2314 | 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, | |
2315 | 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa }; | |
2316 | ||
2317 | /* Fill out hash function seeds */ | |
2318 | for (j = 0; j < 10; j++) { | |
2319 | u32 rsskey = rsshash[(j * 4)]; | |
2320 | rsskey |= rsshash[(j * 4) + 1] << 8; | |
2321 | rsskey |= rsshash[(j * 4) + 2] << 16; | |
2322 | rsskey |= rsshash[(j * 4) + 3] << 24; | |
2323 | array_wr32(E1000_RSSRK(0), j, rsskey); | |
2324 | } | |
2325 | ||
a99955fc | 2326 | num_rx_queues = adapter->rss_queues; |
06cf2666 AD |
2327 | |
2328 | if (adapter->vfs_allocated_count) { | |
2329 | /* 82575 and 82576 supports 2 RSS queues for VMDq */ | |
2330 | switch (hw->mac.type) { | |
55cac248 AD |
2331 | case e1000_82580: |
2332 | num_rx_queues = 1; | |
2333 | shift = 0; | |
2334 | break; | |
06cf2666 AD |
2335 | case e1000_82576: |
2336 | shift = 3; | |
2337 | num_rx_queues = 2; | |
2338 | break; | |
2339 | case e1000_82575: | |
2340 | shift = 2; | |
2341 | shift2 = 6; | |
2342 | default: | |
2343 | break; | |
2344 | } | |
2345 | } else { | |
2346 | if (hw->mac.type == e1000_82575) | |
2347 | shift = 6; | |
2348 | } | |
2349 | ||
2350 | for (j = 0; j < (32 * 4); j++) { | |
2351 | reta.bytes[j & 3] = (j % num_rx_queues) << shift; | |
2352 | if (shift2) | |
2353 | reta.bytes[j & 3] |= num_rx_queues << shift2; | |
2354 | if ((j & 3) == 3) | |
2355 | wr32(E1000_RETA(j >> 2), reta.dword); | |
2356 | } | |
2357 | ||
2358 | /* | |
2359 | * Disable raw packet checksumming so that RSS hash is placed in | |
2360 | * descriptor on writeback. No need to enable TCP/UDP/IP checksum | |
2361 | * offloads as they are enabled by default | |
2362 | */ | |
2363 | rxcsum = rd32(E1000_RXCSUM); | |
2364 | rxcsum |= E1000_RXCSUM_PCSD; | |
2365 | ||
2366 | if (adapter->hw.mac.type >= e1000_82576) | |
2367 | /* Enable Receive Checksum Offload for SCTP */ | |
2368 | rxcsum |= E1000_RXCSUM_CRCOFL; | |
2369 | ||
2370 | /* Don't need to set TUOFL or IPOFL, they default to 1 */ | |
2371 | wr32(E1000_RXCSUM, rxcsum); | |
2372 | ||
2373 | /* If VMDq is enabled then we set the appropriate mode for that, else | |
2374 | * we default to RSS so that an RSS hash is calculated per packet even | |
2375 | * if we are only using one queue */ | |
2376 | if (adapter->vfs_allocated_count) { | |
2377 | if (hw->mac.type > e1000_82575) { | |
2378 | /* Set the default pool for the PF's first queue */ | |
2379 | u32 vtctl = rd32(E1000_VT_CTL); | |
2380 | vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | | |
2381 | E1000_VT_CTL_DISABLE_DEF_POOL); | |
2382 | vtctl |= adapter->vfs_allocated_count << | |
2383 | E1000_VT_CTL_DEFAULT_POOL_SHIFT; | |
2384 | wr32(E1000_VT_CTL, vtctl); | |
2385 | } | |
a99955fc | 2386 | if (adapter->rss_queues > 1) |
06cf2666 AD |
2387 | mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q; |
2388 | else | |
2389 | mrqc = E1000_MRQC_ENABLE_VMDQ; | |
2390 | } else { | |
2391 | mrqc = E1000_MRQC_ENABLE_RSS_4Q; | |
2392 | } | |
2393 | igb_vmm_control(adapter); | |
2394 | ||
2395 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | | |
2396 | E1000_MRQC_RSS_FIELD_IPV4_TCP); | |
2397 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | | |
2398 | E1000_MRQC_RSS_FIELD_IPV6_TCP); | |
2399 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP | | |
2400 | E1000_MRQC_RSS_FIELD_IPV6_UDP); | |
2401 | mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | | |
2402 | E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); | |
2403 | ||
2404 | wr32(E1000_MRQC, mrqc); | |
2405 | } | |
2406 | ||
9d5c8243 AK |
2407 | /** |
2408 | * igb_setup_rctl - configure the receive control registers | |
2409 | * @adapter: Board private structure | |
2410 | **/ | |
d7ee5b3a | 2411 | void igb_setup_rctl(struct igb_adapter *adapter) |
9d5c8243 AK |
2412 | { |
2413 | struct e1000_hw *hw = &adapter->hw; | |
2414 | u32 rctl; | |
9d5c8243 AK |
2415 | |
2416 | rctl = rd32(E1000_RCTL); | |
2417 | ||
2418 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); | |
69d728ba | 2419 | rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); |
9d5c8243 | 2420 | |
69d728ba | 2421 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | |
28b0759c | 2422 | (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); |
9d5c8243 | 2423 | |
87cb7e8c AK |
2424 | /* |
2425 | * enable stripping of CRC. It's unlikely this will break BMC | |
2426 | * redirection as it did with e1000. Newer features require | |
2427 | * that the HW strips the CRC. | |
73cd78f1 | 2428 | */ |
87cb7e8c | 2429 | rctl |= E1000_RCTL_SECRC; |
9d5c8243 | 2430 | |
559e9c49 | 2431 | /* disable store bad packets and clear size bits. */ |
ec54d7d6 | 2432 | rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); |
9d5c8243 | 2433 | |
6ec43fe6 AD |
2434 | /* enable LPE to prevent packets larger than max_frame_size */ |
2435 | rctl |= E1000_RCTL_LPE; | |
9d5c8243 | 2436 | |
952f72a8 AD |
2437 | /* disable queue 0 to prevent tail write w/o re-config */ |
2438 | wr32(E1000_RXDCTL(0), 0); | |
9d5c8243 | 2439 | |
e1739522 AD |
2440 | /* Attention!!! For SR-IOV PF driver operations you must enable |
2441 | * queue drop for all VF and PF queues to prevent head of line blocking | |
2442 | * if an un-trusted VF does not provide descriptors to hardware. | |
2443 | */ | |
2444 | if (adapter->vfs_allocated_count) { | |
e1739522 AD |
2445 | /* set all queue drop enable bits */ |
2446 | wr32(E1000_QDE, ALL_QUEUES); | |
e1739522 AD |
2447 | } |
2448 | ||
9d5c8243 AK |
2449 | wr32(E1000_RCTL, rctl); |
2450 | } | |
2451 | ||
7d5753f0 AD |
2452 | static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, |
2453 | int vfn) | |
2454 | { | |
2455 | struct e1000_hw *hw = &adapter->hw; | |
2456 | u32 vmolr; | |
2457 | ||
2458 | /* if it isn't the PF check to see if VFs are enabled and | |
2459 | * increase the size to support vlan tags */ | |
2460 | if (vfn < adapter->vfs_allocated_count && | |
2461 | adapter->vf_data[vfn].vlans_enabled) | |
2462 | size += VLAN_TAG_SIZE; | |
2463 | ||
2464 | vmolr = rd32(E1000_VMOLR(vfn)); | |
2465 | vmolr &= ~E1000_VMOLR_RLPML_MASK; | |
2466 | vmolr |= size | E1000_VMOLR_LPE; | |
2467 | wr32(E1000_VMOLR(vfn), vmolr); | |
2468 | ||
2469 | return 0; | |
2470 | } | |
2471 | ||
e1739522 AD |
2472 | /** |
2473 | * igb_rlpml_set - set maximum receive packet size | |
2474 | * @adapter: board private structure | |
2475 | * | |
2476 | * Configure maximum receivable packet size. | |
2477 | **/ | |
2478 | static void igb_rlpml_set(struct igb_adapter *adapter) | |
2479 | { | |
2480 | u32 max_frame_size = adapter->max_frame_size; | |
2481 | struct e1000_hw *hw = &adapter->hw; | |
2482 | u16 pf_id = adapter->vfs_allocated_count; | |
2483 | ||
2484 | if (adapter->vlgrp) | |
2485 | max_frame_size += VLAN_TAG_SIZE; | |
2486 | ||
2487 | /* if vfs are enabled we set RLPML to the largest possible request | |
2488 | * size and set the VMOLR RLPML to the size we need */ | |
2489 | if (pf_id) { | |
2490 | igb_set_vf_rlpml(adapter, max_frame_size, pf_id); | |
7d5753f0 | 2491 | max_frame_size = MAX_JUMBO_FRAME_SIZE; |
e1739522 AD |
2492 | } |
2493 | ||
2494 | wr32(E1000_RLPML, max_frame_size); | |
2495 | } | |
2496 | ||
7d5753f0 AD |
2497 | static inline void igb_set_vmolr(struct igb_adapter *adapter, int vfn) |
2498 | { | |
2499 | struct e1000_hw *hw = &adapter->hw; | |
2500 | u32 vmolr; | |
2501 | ||
2502 | /* | |
2503 | * This register exists only on 82576 and newer so if we are older then | |
2504 | * we should exit and do nothing | |
2505 | */ | |
2506 | if (hw->mac.type < e1000_82576) | |
2507 | return; | |
2508 | ||
2509 | vmolr = rd32(E1000_VMOLR(vfn)); | |
2510 | vmolr |= E1000_VMOLR_AUPE | /* Accept untagged packets */ | |
2511 | E1000_VMOLR_STRVLAN; /* Strip vlan tags */ | |
2512 | ||
2513 | /* clear all bits that might not be set */ | |
2514 | vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); | |
2515 | ||
a99955fc | 2516 | if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) |
7d5753f0 AD |
2517 | vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ |
2518 | /* | |
2519 | * for VMDq only allow the VFs and pool 0 to accept broadcast and | |
2520 | * multicast packets | |
2521 | */ | |
2522 | if (vfn <= adapter->vfs_allocated_count) | |
2523 | vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ | |
2524 | ||
2525 | wr32(E1000_VMOLR(vfn), vmolr); | |
2526 | } | |
2527 | ||
85b430b4 AD |
2528 | /** |
2529 | * igb_configure_rx_ring - Configure a receive ring after Reset | |
2530 | * @adapter: board private structure | |
2531 | * @ring: receive ring to be configured | |
2532 | * | |
2533 | * Configure the Rx unit of the MAC after a reset. | |
2534 | **/ | |
d7ee5b3a AD |
2535 | void igb_configure_rx_ring(struct igb_adapter *adapter, |
2536 | struct igb_ring *ring) | |
85b430b4 AD |
2537 | { |
2538 | struct e1000_hw *hw = &adapter->hw; | |
2539 | u64 rdba = ring->dma; | |
2540 | int reg_idx = ring->reg_idx; | |
952f72a8 | 2541 | u32 srrctl, rxdctl; |
85b430b4 AD |
2542 | |
2543 | /* disable the queue */ | |
2544 | rxdctl = rd32(E1000_RXDCTL(reg_idx)); | |
2545 | wr32(E1000_RXDCTL(reg_idx), | |
2546 | rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE); | |
2547 | ||
2548 | /* Set DMA base address registers */ | |
2549 | wr32(E1000_RDBAL(reg_idx), | |
2550 | rdba & 0x00000000ffffffffULL); | |
2551 | wr32(E1000_RDBAH(reg_idx), rdba >> 32); | |
2552 | wr32(E1000_RDLEN(reg_idx), | |
2553 | ring->count * sizeof(union e1000_adv_rx_desc)); | |
2554 | ||
2555 | /* initialize head and tail */ | |
fce99e34 AD |
2556 | ring->head = hw->hw_addr + E1000_RDH(reg_idx); |
2557 | ring->tail = hw->hw_addr + E1000_RDT(reg_idx); | |
2558 | writel(0, ring->head); | |
2559 | writel(0, ring->tail); | |
85b430b4 | 2560 | |
952f72a8 | 2561 | /* set descriptor configuration */ |
4c844851 AD |
2562 | if (ring->rx_buffer_len < IGB_RXBUFFER_1024) { |
2563 | srrctl = ALIGN(ring->rx_buffer_len, 64) << | |
952f72a8 AD |
2564 | E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; |
2565 | #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384 | |
2566 | srrctl |= IGB_RXBUFFER_16384 >> | |
2567 | E1000_SRRCTL_BSIZEPKT_SHIFT; | |
2568 | #else | |
2569 | srrctl |= (PAGE_SIZE / 2) >> | |
2570 | E1000_SRRCTL_BSIZEPKT_SHIFT; | |
2571 | #endif | |
2572 | srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; | |
2573 | } else { | |
4c844851 | 2574 | srrctl = ALIGN(ring->rx_buffer_len, 1024) >> |
952f72a8 AD |
2575 | E1000_SRRCTL_BSIZEPKT_SHIFT; |
2576 | srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; | |
2577 | } | |
2578 | ||
2579 | wr32(E1000_SRRCTL(reg_idx), srrctl); | |
2580 | ||
7d5753f0 AD |
2581 | /* set filtering for VMDQ pools */ |
2582 | igb_set_vmolr(adapter, reg_idx & 0x7); | |
2583 | ||
85b430b4 AD |
2584 | /* enable receive descriptor fetching */ |
2585 | rxdctl = rd32(E1000_RXDCTL(reg_idx)); | |
2586 | rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; | |
2587 | rxdctl &= 0xFFF00000; | |
2588 | rxdctl |= IGB_RX_PTHRESH; | |
2589 | rxdctl |= IGB_RX_HTHRESH << 8; | |
2590 | rxdctl |= IGB_RX_WTHRESH << 16; | |
2591 | wr32(E1000_RXDCTL(reg_idx), rxdctl); | |
2592 | } | |
2593 | ||
9d5c8243 AK |
2594 | /** |
2595 | * igb_configure_rx - Configure receive Unit after Reset | |
2596 | * @adapter: board private structure | |
2597 | * | |
2598 | * Configure the Rx unit of the MAC after a reset. | |
2599 | **/ | |
2600 | static void igb_configure_rx(struct igb_adapter *adapter) | |
2601 | { | |
9107584e | 2602 | int i; |
9d5c8243 | 2603 | |
68d480c4 AD |
2604 | /* set UTA to appropriate mode */ |
2605 | igb_set_uta(adapter); | |
2606 | ||
26ad9178 AD |
2607 | /* set the correct pool for the PF default MAC address in entry 0 */ |
2608 | igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, | |
2609 | adapter->vfs_allocated_count); | |
2610 | ||
06cf2666 AD |
2611 | /* Setup the HW Rx Head and Tail Descriptor Pointers and |
2612 | * the Base and Length of the Rx Descriptor Ring */ | |
2613 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2614 | igb_configure_rx_ring(adapter, &adapter->rx_ring[i]); | |
9d5c8243 AK |
2615 | } |
2616 | ||
2617 | /** | |
2618 | * igb_free_tx_resources - Free Tx Resources per Queue | |
9d5c8243 AK |
2619 | * @tx_ring: Tx descriptor ring for a specific queue |
2620 | * | |
2621 | * Free all transmit software resources | |
2622 | **/ | |
68fd9910 | 2623 | void igb_free_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 2624 | { |
3b644cf6 | 2625 | igb_clean_tx_ring(tx_ring); |
9d5c8243 AK |
2626 | |
2627 | vfree(tx_ring->buffer_info); | |
2628 | tx_ring->buffer_info = NULL; | |
2629 | ||
439705e1 AD |
2630 | /* if not set, then don't free */ |
2631 | if (!tx_ring->desc) | |
2632 | return; | |
2633 | ||
80785298 AD |
2634 | pci_free_consistent(tx_ring->pdev, tx_ring->size, |
2635 | tx_ring->desc, tx_ring->dma); | |
9d5c8243 AK |
2636 | |
2637 | tx_ring->desc = NULL; | |
2638 | } | |
2639 | ||
2640 | /** | |
2641 | * igb_free_all_tx_resources - Free Tx Resources for All Queues | |
2642 | * @adapter: board private structure | |
2643 | * | |
2644 | * Free all transmit software resources | |
2645 | **/ | |
2646 | static void igb_free_all_tx_resources(struct igb_adapter *adapter) | |
2647 | { | |
2648 | int i; | |
2649 | ||
2650 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3b644cf6 | 2651 | igb_free_tx_resources(&adapter->tx_ring[i]); |
9d5c8243 AK |
2652 | } |
2653 | ||
b1a436c3 AD |
2654 | void igb_unmap_and_free_tx_resource(struct igb_ring *tx_ring, |
2655 | struct igb_buffer *buffer_info) | |
9d5c8243 | 2656 | { |
65689fef | 2657 | buffer_info->dma = 0; |
9d5c8243 | 2658 | if (buffer_info->skb) { |
80785298 AD |
2659 | skb_dma_unmap(&tx_ring->pdev->dev, |
2660 | buffer_info->skb, | |
65689fef | 2661 | DMA_TO_DEVICE); |
9d5c8243 AK |
2662 | dev_kfree_skb_any(buffer_info->skb); |
2663 | buffer_info->skb = NULL; | |
2664 | } | |
2665 | buffer_info->time_stamp = 0; | |
2666 | /* buffer_info must be completely set up in the transmit path */ | |
2667 | } | |
2668 | ||
2669 | /** | |
2670 | * igb_clean_tx_ring - Free Tx Buffers | |
9d5c8243 AK |
2671 | * @tx_ring: ring to be cleaned |
2672 | **/ | |
3b644cf6 | 2673 | static void igb_clean_tx_ring(struct igb_ring *tx_ring) |
9d5c8243 AK |
2674 | { |
2675 | struct igb_buffer *buffer_info; | |
2676 | unsigned long size; | |
2677 | unsigned int i; | |
2678 | ||
2679 | if (!tx_ring->buffer_info) | |
2680 | return; | |
2681 | /* Free all the Tx ring sk_buffs */ | |
2682 | ||
2683 | for (i = 0; i < tx_ring->count; i++) { | |
2684 | buffer_info = &tx_ring->buffer_info[i]; | |
80785298 | 2685 | igb_unmap_and_free_tx_resource(tx_ring, buffer_info); |
9d5c8243 AK |
2686 | } |
2687 | ||
2688 | size = sizeof(struct igb_buffer) * tx_ring->count; | |
2689 | memset(tx_ring->buffer_info, 0, size); | |
2690 | ||
2691 | /* Zero out the descriptor ring */ | |
9d5c8243 AK |
2692 | memset(tx_ring->desc, 0, tx_ring->size); |
2693 | ||
2694 | tx_ring->next_to_use = 0; | |
2695 | tx_ring->next_to_clean = 0; | |
9d5c8243 AK |
2696 | } |
2697 | ||
2698 | /** | |
2699 | * igb_clean_all_tx_rings - Free Tx Buffers for all queues | |
2700 | * @adapter: board private structure | |
2701 | **/ | |
2702 | static void igb_clean_all_tx_rings(struct igb_adapter *adapter) | |
2703 | { | |
2704 | int i; | |
2705 | ||
2706 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3b644cf6 | 2707 | igb_clean_tx_ring(&adapter->tx_ring[i]); |
9d5c8243 AK |
2708 | } |
2709 | ||
2710 | /** | |
2711 | * igb_free_rx_resources - Free Rx Resources | |
9d5c8243 AK |
2712 | * @rx_ring: ring to clean the resources from |
2713 | * | |
2714 | * Free all receive software resources | |
2715 | **/ | |
68fd9910 | 2716 | void igb_free_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 2717 | { |
3b644cf6 | 2718 | igb_clean_rx_ring(rx_ring); |
9d5c8243 AK |
2719 | |
2720 | vfree(rx_ring->buffer_info); | |
2721 | rx_ring->buffer_info = NULL; | |
2722 | ||
439705e1 AD |
2723 | /* if not set, then don't free */ |
2724 | if (!rx_ring->desc) | |
2725 | return; | |
2726 | ||
80785298 AD |
2727 | pci_free_consistent(rx_ring->pdev, rx_ring->size, |
2728 | rx_ring->desc, rx_ring->dma); | |
9d5c8243 AK |
2729 | |
2730 | rx_ring->desc = NULL; | |
2731 | } | |
2732 | ||
2733 | /** | |
2734 | * igb_free_all_rx_resources - Free Rx Resources for All Queues | |
2735 | * @adapter: board private structure | |
2736 | * | |
2737 | * Free all receive software resources | |
2738 | **/ | |
2739 | static void igb_free_all_rx_resources(struct igb_adapter *adapter) | |
2740 | { | |
2741 | int i; | |
2742 | ||
2743 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3b644cf6 | 2744 | igb_free_rx_resources(&adapter->rx_ring[i]); |
9d5c8243 AK |
2745 | } |
2746 | ||
2747 | /** | |
2748 | * igb_clean_rx_ring - Free Rx Buffers per Queue | |
9d5c8243 AK |
2749 | * @rx_ring: ring to free buffers from |
2750 | **/ | |
3b644cf6 | 2751 | static void igb_clean_rx_ring(struct igb_ring *rx_ring) |
9d5c8243 AK |
2752 | { |
2753 | struct igb_buffer *buffer_info; | |
9d5c8243 AK |
2754 | unsigned long size; |
2755 | unsigned int i; | |
2756 | ||
2757 | if (!rx_ring->buffer_info) | |
2758 | return; | |
439705e1 | 2759 | |
9d5c8243 AK |
2760 | /* Free all the Rx ring sk_buffs */ |
2761 | for (i = 0; i < rx_ring->count; i++) { | |
2762 | buffer_info = &rx_ring->buffer_info[i]; | |
2763 | if (buffer_info->dma) { | |
80785298 AD |
2764 | pci_unmap_single(rx_ring->pdev, |
2765 | buffer_info->dma, | |
4c844851 | 2766 | rx_ring->rx_buffer_len, |
6ec43fe6 | 2767 | PCI_DMA_FROMDEVICE); |
9d5c8243 AK |
2768 | buffer_info->dma = 0; |
2769 | } | |
2770 | ||
2771 | if (buffer_info->skb) { | |
2772 | dev_kfree_skb(buffer_info->skb); | |
2773 | buffer_info->skb = NULL; | |
2774 | } | |
6ec43fe6 | 2775 | if (buffer_info->page_dma) { |
80785298 AD |
2776 | pci_unmap_page(rx_ring->pdev, |
2777 | buffer_info->page_dma, | |
6ec43fe6 AD |
2778 | PAGE_SIZE / 2, |
2779 | PCI_DMA_FROMDEVICE); | |
2780 | buffer_info->page_dma = 0; | |
2781 | } | |
9d5c8243 | 2782 | if (buffer_info->page) { |
9d5c8243 AK |
2783 | put_page(buffer_info->page); |
2784 | buffer_info->page = NULL; | |
bf36c1a0 | 2785 | buffer_info->page_offset = 0; |
9d5c8243 AK |
2786 | } |
2787 | } | |
2788 | ||
9d5c8243 AK |
2789 | size = sizeof(struct igb_buffer) * rx_ring->count; |
2790 | memset(rx_ring->buffer_info, 0, size); | |
2791 | ||
2792 | /* Zero out the descriptor ring */ | |
2793 | memset(rx_ring->desc, 0, rx_ring->size); | |
2794 | ||
2795 | rx_ring->next_to_clean = 0; | |
2796 | rx_ring->next_to_use = 0; | |
9d5c8243 AK |
2797 | } |
2798 | ||
2799 | /** | |
2800 | * igb_clean_all_rx_rings - Free Rx Buffers for all queues | |
2801 | * @adapter: board private structure | |
2802 | **/ | |
2803 | static void igb_clean_all_rx_rings(struct igb_adapter *adapter) | |
2804 | { | |
2805 | int i; | |
2806 | ||
2807 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3b644cf6 | 2808 | igb_clean_rx_ring(&adapter->rx_ring[i]); |
9d5c8243 AK |
2809 | } |
2810 | ||
2811 | /** | |
2812 | * igb_set_mac - Change the Ethernet Address of the NIC | |
2813 | * @netdev: network interface device structure | |
2814 | * @p: pointer to an address structure | |
2815 | * | |
2816 | * Returns 0 on success, negative on failure | |
2817 | **/ | |
2818 | static int igb_set_mac(struct net_device *netdev, void *p) | |
2819 | { | |
2820 | struct igb_adapter *adapter = netdev_priv(netdev); | |
28b0759c | 2821 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
2822 | struct sockaddr *addr = p; |
2823 | ||
2824 | if (!is_valid_ether_addr(addr->sa_data)) | |
2825 | return -EADDRNOTAVAIL; | |
2826 | ||
2827 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
28b0759c | 2828 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9d5c8243 | 2829 | |
26ad9178 AD |
2830 | /* set the correct pool for the new PF MAC address in entry 0 */ |
2831 | igb_rar_set_qsel(adapter, hw->mac.addr, 0, | |
2832 | adapter->vfs_allocated_count); | |
e1739522 | 2833 | |
9d5c8243 AK |
2834 | return 0; |
2835 | } | |
2836 | ||
2837 | /** | |
68d480c4 | 2838 | * igb_write_mc_addr_list - write multicast addresses to MTA |
9d5c8243 AK |
2839 | * @netdev: network interface device structure |
2840 | * | |
68d480c4 AD |
2841 | * Writes multicast address list to the MTA hash table. |
2842 | * Returns: -ENOMEM on failure | |
2843 | * 0 on no addresses written | |
2844 | * X on writing X addresses to MTA | |
9d5c8243 | 2845 | **/ |
68d480c4 | 2846 | static int igb_write_mc_addr_list(struct net_device *netdev) |
9d5c8243 AK |
2847 | { |
2848 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2849 | struct e1000_hw *hw = &adapter->hw; | |
ff41f8dc | 2850 | struct dev_mc_list *mc_ptr = netdev->mc_list; |
68d480c4 AD |
2851 | u8 *mta_list; |
2852 | u32 vmolr = 0; | |
9d5c8243 AK |
2853 | int i; |
2854 | ||
68d480c4 AD |
2855 | if (!netdev->mc_count) { |
2856 | /* nothing to program, so clear mc list */ | |
2857 | igb_update_mc_addr_list(hw, NULL, 0); | |
2858 | igb_restore_vf_multicasts(adapter); | |
2859 | return 0; | |
2860 | } | |
9d5c8243 | 2861 | |
68d480c4 AD |
2862 | mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC); |
2863 | if (!mta_list) | |
2864 | return -ENOMEM; | |
ff41f8dc | 2865 | |
68d480c4 AD |
2866 | /* set vmolr receive overflow multicast bit */ |
2867 | vmolr |= E1000_VMOLR_ROMPE; | |
2868 | ||
2869 | /* The shared function expects a packed array of only addresses. */ | |
2870 | mc_ptr = netdev->mc_list; | |
2871 | ||
2872 | for (i = 0; i < netdev->mc_count; i++) { | |
2873 | if (!mc_ptr) | |
2874 | break; | |
2875 | memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN); | |
2876 | mc_ptr = mc_ptr->next; | |
746b9f02 | 2877 | } |
68d480c4 AD |
2878 | igb_update_mc_addr_list(hw, mta_list, i); |
2879 | kfree(mta_list); | |
2880 | ||
2881 | return netdev->mc_count; | |
2882 | } | |
2883 | ||
2884 | /** | |
2885 | * igb_write_uc_addr_list - write unicast addresses to RAR table | |
2886 | * @netdev: network interface device structure | |
2887 | * | |
2888 | * Writes unicast address list to the RAR table. | |
2889 | * Returns: -ENOMEM on failure/insufficient address space | |
2890 | * 0 on no addresses written | |
2891 | * X on writing X addresses to the RAR table | |
2892 | **/ | |
2893 | static int igb_write_uc_addr_list(struct net_device *netdev) | |
2894 | { | |
2895 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2896 | struct e1000_hw *hw = &adapter->hw; | |
2897 | unsigned int vfn = adapter->vfs_allocated_count; | |
2898 | unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); | |
2899 | int count = 0; | |
2900 | ||
2901 | /* return ENOMEM indicating insufficient memory for addresses */ | |
2902 | if (netdev->uc.count > rar_entries) | |
2903 | return -ENOMEM; | |
9d5c8243 | 2904 | |
ff41f8dc AD |
2905 | if (netdev->uc.count && rar_entries) { |
2906 | struct netdev_hw_addr *ha; | |
2907 | list_for_each_entry(ha, &netdev->uc.list, list) { | |
2908 | if (!rar_entries) | |
2909 | break; | |
26ad9178 AD |
2910 | igb_rar_set_qsel(adapter, ha->addr, |
2911 | rar_entries--, | |
68d480c4 AD |
2912 | vfn); |
2913 | count++; | |
ff41f8dc AD |
2914 | } |
2915 | } | |
2916 | /* write the addresses in reverse order to avoid write combining */ | |
2917 | for (; rar_entries > 0 ; rar_entries--) { | |
2918 | wr32(E1000_RAH(rar_entries), 0); | |
2919 | wr32(E1000_RAL(rar_entries), 0); | |
2920 | } | |
2921 | wrfl(); | |
2922 | ||
68d480c4 AD |
2923 | return count; |
2924 | } | |
2925 | ||
2926 | /** | |
2927 | * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set | |
2928 | * @netdev: network interface device structure | |
2929 | * | |
2930 | * The set_rx_mode entry point is called whenever the unicast or multicast | |
2931 | * address lists or the network interface flags are updated. This routine is | |
2932 | * responsible for configuring the hardware for proper unicast, multicast, | |
2933 | * promiscuous mode, and all-multi behavior. | |
2934 | **/ | |
2935 | static void igb_set_rx_mode(struct net_device *netdev) | |
2936 | { | |
2937 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2938 | struct e1000_hw *hw = &adapter->hw; | |
2939 | unsigned int vfn = adapter->vfs_allocated_count; | |
2940 | u32 rctl, vmolr = 0; | |
2941 | int count; | |
2942 | ||
2943 | /* Check for Promiscuous and All Multicast modes */ | |
2944 | rctl = rd32(E1000_RCTL); | |
2945 | ||
2946 | /* clear the effected bits */ | |
2947 | rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); | |
2948 | ||
2949 | if (netdev->flags & IFF_PROMISC) { | |
2950 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); | |
2951 | vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); | |
2952 | } else { | |
2953 | if (netdev->flags & IFF_ALLMULTI) { | |
2954 | rctl |= E1000_RCTL_MPE; | |
2955 | vmolr |= E1000_VMOLR_MPME; | |
2956 | } else { | |
2957 | /* | |
2958 | * Write addresses to the MTA, if the attempt fails | |
2959 | * then we should just turn on promiscous mode so | |
2960 | * that we can at least receive multicast traffic | |
2961 | */ | |
2962 | count = igb_write_mc_addr_list(netdev); | |
2963 | if (count < 0) { | |
2964 | rctl |= E1000_RCTL_MPE; | |
2965 | vmolr |= E1000_VMOLR_MPME; | |
2966 | } else if (count) { | |
2967 | vmolr |= E1000_VMOLR_ROMPE; | |
2968 | } | |
2969 | } | |
2970 | /* | |
2971 | * Write addresses to available RAR registers, if there is not | |
2972 | * sufficient space to store all the addresses then enable | |
2973 | * unicast promiscous mode | |
2974 | */ | |
2975 | count = igb_write_uc_addr_list(netdev); | |
2976 | if (count < 0) { | |
2977 | rctl |= E1000_RCTL_UPE; | |
2978 | vmolr |= E1000_VMOLR_ROPE; | |
2979 | } | |
2980 | rctl |= E1000_RCTL_VFE; | |
28fc06f5 | 2981 | } |
68d480c4 | 2982 | wr32(E1000_RCTL, rctl); |
28fc06f5 | 2983 | |
68d480c4 AD |
2984 | /* |
2985 | * In order to support SR-IOV and eventually VMDq it is necessary to set | |
2986 | * the VMOLR to enable the appropriate modes. Without this workaround | |
2987 | * we will have issues with VLAN tag stripping not being done for frames | |
2988 | * that are only arriving because we are the default pool | |
2989 | */ | |
2990 | if (hw->mac.type < e1000_82576) | |
28fc06f5 | 2991 | return; |
9d5c8243 | 2992 | |
68d480c4 AD |
2993 | vmolr |= rd32(E1000_VMOLR(vfn)) & |
2994 | ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); | |
2995 | wr32(E1000_VMOLR(vfn), vmolr); | |
28fc06f5 | 2996 | igb_restore_vf_multicasts(adapter); |
9d5c8243 AK |
2997 | } |
2998 | ||
2999 | /* Need to wait a few seconds after link up to get diagnostic information from | |
3000 | * the phy */ | |
3001 | static void igb_update_phy_info(unsigned long data) | |
3002 | { | |
3003 | struct igb_adapter *adapter = (struct igb_adapter *) data; | |
f5f4cf08 | 3004 | igb_get_phy_info(&adapter->hw); |
9d5c8243 AK |
3005 | } |
3006 | ||
4d6b725e AD |
3007 | /** |
3008 | * igb_has_link - check shared code for link and determine up/down | |
3009 | * @adapter: pointer to driver private info | |
3010 | **/ | |
3011 | static bool igb_has_link(struct igb_adapter *adapter) | |
3012 | { | |
3013 | struct e1000_hw *hw = &adapter->hw; | |
3014 | bool link_active = false; | |
3015 | s32 ret_val = 0; | |
3016 | ||
3017 | /* get_link_status is set on LSC (link status) interrupt or | |
3018 | * rx sequence error interrupt. get_link_status will stay | |
3019 | * false until the e1000_check_for_link establishes link | |
3020 | * for copper adapters ONLY | |
3021 | */ | |
3022 | switch (hw->phy.media_type) { | |
3023 | case e1000_media_type_copper: | |
3024 | if (hw->mac.get_link_status) { | |
3025 | ret_val = hw->mac.ops.check_for_link(hw); | |
3026 | link_active = !hw->mac.get_link_status; | |
3027 | } else { | |
3028 | link_active = true; | |
3029 | } | |
3030 | break; | |
4d6b725e AD |
3031 | case e1000_media_type_internal_serdes: |
3032 | ret_val = hw->mac.ops.check_for_link(hw); | |
3033 | link_active = hw->mac.serdes_has_link; | |
3034 | break; | |
3035 | default: | |
3036 | case e1000_media_type_unknown: | |
3037 | break; | |
3038 | } | |
3039 | ||
3040 | return link_active; | |
3041 | } | |
3042 | ||
9d5c8243 AK |
3043 | /** |
3044 | * igb_watchdog - Timer Call-back | |
3045 | * @data: pointer to adapter cast into an unsigned long | |
3046 | **/ | |
3047 | static void igb_watchdog(unsigned long data) | |
3048 | { | |
3049 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
3050 | /* Do the rest outside of interrupt context */ | |
3051 | schedule_work(&adapter->watchdog_task); | |
3052 | } | |
3053 | ||
3054 | static void igb_watchdog_task(struct work_struct *work) | |
3055 | { | |
3056 | struct igb_adapter *adapter = container_of(work, | |
559e9c49 AD |
3057 | struct igb_adapter, |
3058 | watchdog_task); | |
9d5c8243 | 3059 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 3060 | struct net_device *netdev = adapter->netdev; |
9d5c8243 | 3061 | u32 link; |
7a6ea550 | 3062 | int i; |
9d5c8243 | 3063 | |
4d6b725e | 3064 | link = igb_has_link(adapter); |
9d5c8243 AK |
3065 | if (link) { |
3066 | if (!netif_carrier_ok(netdev)) { | |
3067 | u32 ctrl; | |
330a6d6a AD |
3068 | hw->mac.ops.get_speed_and_duplex(hw, |
3069 | &adapter->link_speed, | |
3070 | &adapter->link_duplex); | |
9d5c8243 AK |
3071 | |
3072 | ctrl = rd32(E1000_CTRL); | |
527d47c1 AD |
3073 | /* Links status message must follow this format */ |
3074 | printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, " | |
9d5c8243 | 3075 | "Flow Control: %s\n", |
559e9c49 AD |
3076 | netdev->name, |
3077 | adapter->link_speed, | |
3078 | adapter->link_duplex == FULL_DUPLEX ? | |
9d5c8243 | 3079 | "Full Duplex" : "Half Duplex", |
559e9c49 AD |
3080 | ((ctrl & E1000_CTRL_TFCE) && |
3081 | (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" : | |
3082 | ((ctrl & E1000_CTRL_RFCE) ? "RX" : | |
3083 | ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None"))); | |
9d5c8243 AK |
3084 | |
3085 | /* tweak tx_queue_len according to speed/duplex and | |
3086 | * adjust the timeout factor */ | |
3087 | netdev->tx_queue_len = adapter->tx_queue_len; | |
3088 | adapter->tx_timeout_factor = 1; | |
3089 | switch (adapter->link_speed) { | |
3090 | case SPEED_10: | |
3091 | netdev->tx_queue_len = 10; | |
3092 | adapter->tx_timeout_factor = 14; | |
3093 | break; | |
3094 | case SPEED_100: | |
3095 | netdev->tx_queue_len = 100; | |
3096 | /* maybe add some timeout factor ? */ | |
3097 | break; | |
3098 | } | |
3099 | ||
3100 | netif_carrier_on(netdev); | |
9d5c8243 | 3101 | |
4ae196df AD |
3102 | igb_ping_all_vfs(adapter); |
3103 | ||
4b1a9877 | 3104 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
3105 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
3106 | mod_timer(&adapter->phy_info_timer, | |
3107 | round_jiffies(jiffies + 2 * HZ)); | |
3108 | } | |
3109 | } else { | |
3110 | if (netif_carrier_ok(netdev)) { | |
3111 | adapter->link_speed = 0; | |
3112 | adapter->link_duplex = 0; | |
527d47c1 AD |
3113 | /* Links status message must follow this format */ |
3114 | printk(KERN_INFO "igb: %s NIC Link is Down\n", | |
3115 | netdev->name); | |
9d5c8243 | 3116 | netif_carrier_off(netdev); |
4b1a9877 | 3117 | |
4ae196df AD |
3118 | igb_ping_all_vfs(adapter); |
3119 | ||
4b1a9877 | 3120 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
3121 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
3122 | mod_timer(&adapter->phy_info_timer, | |
3123 | round_jiffies(jiffies + 2 * HZ)); | |
3124 | } | |
3125 | } | |
3126 | ||
9d5c8243 | 3127 | igb_update_stats(adapter); |
645a3abd | 3128 | igb_update_adaptive(hw); |
9d5c8243 | 3129 | |
dbabb065 AD |
3130 | for (i = 0; i < adapter->num_tx_queues; i++) { |
3131 | struct igb_ring *tx_ring = &adapter->tx_ring[i]; | |
3132 | if (!netif_carrier_ok(netdev)) { | |
9d5c8243 AK |
3133 | /* We've lost link, so the controller stops DMA, |
3134 | * but we've got queued Tx work that's never going | |
3135 | * to get done, so reset controller to flush Tx. | |
3136 | * (Do the reset outside of interrupt context). */ | |
dbabb065 AD |
3137 | if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { |
3138 | adapter->tx_timeout_count++; | |
3139 | schedule_work(&adapter->reset_task); | |
3140 | /* return immediately since reset is imminent */ | |
3141 | return; | |
3142 | } | |
9d5c8243 | 3143 | } |
9d5c8243 | 3144 | |
dbabb065 AD |
3145 | /* Force detection of hung controller every watchdog period */ |
3146 | tx_ring->detect_tx_hung = true; | |
3147 | } | |
f7ba205e | 3148 | |
9d5c8243 | 3149 | /* Cause software interrupt to ensure rx ring is cleaned */ |
7a6ea550 | 3150 | if (adapter->msix_entries) { |
047e0030 AD |
3151 | u32 eics = 0; |
3152 | for (i = 0; i < adapter->num_q_vectors; i++) { | |
3153 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
3154 | eics |= q_vector->eims_value; | |
3155 | } | |
7a6ea550 AD |
3156 | wr32(E1000_EICS, eics); |
3157 | } else { | |
3158 | wr32(E1000_ICS, E1000_ICS_RXDMT0); | |
3159 | } | |
9d5c8243 | 3160 | |
9d5c8243 AK |
3161 | /* Reset the timer */ |
3162 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3163 | mod_timer(&adapter->watchdog_timer, | |
3164 | round_jiffies(jiffies + 2 * HZ)); | |
3165 | } | |
3166 | ||
3167 | enum latency_range { | |
3168 | lowest_latency = 0, | |
3169 | low_latency = 1, | |
3170 | bulk_latency = 2, | |
3171 | latency_invalid = 255 | |
3172 | }; | |
3173 | ||
6eb5a7f1 AD |
3174 | /** |
3175 | * igb_update_ring_itr - update the dynamic ITR value based on packet size | |
3176 | * | |
3177 | * Stores a new ITR value based on strictly on packet size. This | |
3178 | * algorithm is less sophisticated than that used in igb_update_itr, | |
3179 | * due to the difficulty of synchronizing statistics across multiple | |
3180 | * receive rings. The divisors and thresholds used by this fuction | |
3181 | * were determined based on theoretical maximum wire speed and testing | |
3182 | * data, in order to minimize response time while increasing bulk | |
3183 | * throughput. | |
3184 | * This functionality is controlled by the InterruptThrottleRate module | |
3185 | * parameter (see igb_param.c) | |
3186 | * NOTE: This function is called only when operating in a multiqueue | |
3187 | * receive environment. | |
047e0030 | 3188 | * @q_vector: pointer to q_vector |
6eb5a7f1 | 3189 | **/ |
047e0030 | 3190 | static void igb_update_ring_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 3191 | { |
047e0030 | 3192 | int new_val = q_vector->itr_val; |
6eb5a7f1 | 3193 | int avg_wire_size = 0; |
047e0030 | 3194 | struct igb_adapter *adapter = q_vector->adapter; |
9d5c8243 | 3195 | |
6eb5a7f1 AD |
3196 | /* For non-gigabit speeds, just fix the interrupt rate at 4000 |
3197 | * ints/sec - ITR timer value of 120 ticks. | |
3198 | */ | |
3199 | if (adapter->link_speed != SPEED_1000) { | |
047e0030 | 3200 | new_val = 976; |
6eb5a7f1 | 3201 | goto set_itr_val; |
9d5c8243 | 3202 | } |
047e0030 AD |
3203 | |
3204 | if (q_vector->rx_ring && q_vector->rx_ring->total_packets) { | |
3205 | struct igb_ring *ring = q_vector->rx_ring; | |
3206 | avg_wire_size = ring->total_bytes / ring->total_packets; | |
3207 | } | |
3208 | ||
3209 | if (q_vector->tx_ring && q_vector->tx_ring->total_packets) { | |
3210 | struct igb_ring *ring = q_vector->tx_ring; | |
3211 | avg_wire_size = max_t(u32, avg_wire_size, | |
3212 | (ring->total_bytes / | |
3213 | ring->total_packets)); | |
3214 | } | |
3215 | ||
3216 | /* if avg_wire_size isn't set no work was done */ | |
3217 | if (!avg_wire_size) | |
3218 | goto clear_counts; | |
9d5c8243 | 3219 | |
6eb5a7f1 AD |
3220 | /* Add 24 bytes to size to account for CRC, preamble, and gap */ |
3221 | avg_wire_size += 24; | |
3222 | ||
3223 | /* Don't starve jumbo frames */ | |
3224 | avg_wire_size = min(avg_wire_size, 3000); | |
9d5c8243 | 3225 | |
6eb5a7f1 AD |
3226 | /* Give a little boost to mid-size frames */ |
3227 | if ((avg_wire_size > 300) && (avg_wire_size < 1200)) | |
3228 | new_val = avg_wire_size / 3; | |
3229 | else | |
3230 | new_val = avg_wire_size / 2; | |
9d5c8243 | 3231 | |
6eb5a7f1 | 3232 | set_itr_val: |
047e0030 AD |
3233 | if (new_val != q_vector->itr_val) { |
3234 | q_vector->itr_val = new_val; | |
3235 | q_vector->set_itr = 1; | |
9d5c8243 | 3236 | } |
6eb5a7f1 | 3237 | clear_counts: |
047e0030 AD |
3238 | if (q_vector->rx_ring) { |
3239 | q_vector->rx_ring->total_bytes = 0; | |
3240 | q_vector->rx_ring->total_packets = 0; | |
3241 | } | |
3242 | if (q_vector->tx_ring) { | |
3243 | q_vector->tx_ring->total_bytes = 0; | |
3244 | q_vector->tx_ring->total_packets = 0; | |
3245 | } | |
9d5c8243 AK |
3246 | } |
3247 | ||
3248 | /** | |
3249 | * igb_update_itr - update the dynamic ITR value based on statistics | |
3250 | * Stores a new ITR value based on packets and byte | |
3251 | * counts during the last interrupt. The advantage of per interrupt | |
3252 | * computation is faster updates and more accurate ITR for the current | |
3253 | * traffic pattern. Constants in this function were computed | |
3254 | * based on theoretical maximum wire speed and thresholds were set based | |
3255 | * on testing data as well as attempting to minimize response time | |
3256 | * while increasing bulk throughput. | |
3257 | * this functionality is controlled by the InterruptThrottleRate module | |
3258 | * parameter (see igb_param.c) | |
3259 | * NOTE: These calculations are only valid when operating in a single- | |
3260 | * queue environment. | |
3261 | * @adapter: pointer to adapter | |
047e0030 | 3262 | * @itr_setting: current q_vector->itr_val |
9d5c8243 AK |
3263 | * @packets: the number of packets during this measurement interval |
3264 | * @bytes: the number of bytes during this measurement interval | |
3265 | **/ | |
3266 | static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting, | |
3267 | int packets, int bytes) | |
3268 | { | |
3269 | unsigned int retval = itr_setting; | |
3270 | ||
3271 | if (packets == 0) | |
3272 | goto update_itr_done; | |
3273 | ||
3274 | switch (itr_setting) { | |
3275 | case lowest_latency: | |
3276 | /* handle TSO and jumbo frames */ | |
3277 | if (bytes/packets > 8000) | |
3278 | retval = bulk_latency; | |
3279 | else if ((packets < 5) && (bytes > 512)) | |
3280 | retval = low_latency; | |
3281 | break; | |
3282 | case low_latency: /* 50 usec aka 20000 ints/s */ | |
3283 | if (bytes > 10000) { | |
3284 | /* this if handles the TSO accounting */ | |
3285 | if (bytes/packets > 8000) { | |
3286 | retval = bulk_latency; | |
3287 | } else if ((packets < 10) || ((bytes/packets) > 1200)) { | |
3288 | retval = bulk_latency; | |
3289 | } else if ((packets > 35)) { | |
3290 | retval = lowest_latency; | |
3291 | } | |
3292 | } else if (bytes/packets > 2000) { | |
3293 | retval = bulk_latency; | |
3294 | } else if (packets <= 2 && bytes < 512) { | |
3295 | retval = lowest_latency; | |
3296 | } | |
3297 | break; | |
3298 | case bulk_latency: /* 250 usec aka 4000 ints/s */ | |
3299 | if (bytes > 25000) { | |
3300 | if (packets > 35) | |
3301 | retval = low_latency; | |
1e5c3d21 | 3302 | } else if (bytes < 1500) { |
9d5c8243 AK |
3303 | retval = low_latency; |
3304 | } | |
3305 | break; | |
3306 | } | |
3307 | ||
3308 | update_itr_done: | |
3309 | return retval; | |
3310 | } | |
3311 | ||
6eb5a7f1 | 3312 | static void igb_set_itr(struct igb_adapter *adapter) |
9d5c8243 | 3313 | { |
047e0030 | 3314 | struct igb_q_vector *q_vector = adapter->q_vector[0]; |
9d5c8243 | 3315 | u16 current_itr; |
047e0030 | 3316 | u32 new_itr = q_vector->itr_val; |
9d5c8243 AK |
3317 | |
3318 | /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ | |
3319 | if (adapter->link_speed != SPEED_1000) { | |
3320 | current_itr = 0; | |
3321 | new_itr = 4000; | |
3322 | goto set_itr_now; | |
3323 | } | |
3324 | ||
3325 | adapter->rx_itr = igb_update_itr(adapter, | |
3326 | adapter->rx_itr, | |
3327 | adapter->rx_ring->total_packets, | |
3328 | adapter->rx_ring->total_bytes); | |
9d5c8243 | 3329 | |
047e0030 AD |
3330 | adapter->tx_itr = igb_update_itr(adapter, |
3331 | adapter->tx_itr, | |
3332 | adapter->tx_ring->total_packets, | |
3333 | adapter->tx_ring->total_bytes); | |
3334 | current_itr = max(adapter->rx_itr, adapter->tx_itr); | |
9d5c8243 | 3335 | |
6eb5a7f1 | 3336 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
4fc82adf | 3337 | if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency) |
6eb5a7f1 AD |
3338 | current_itr = low_latency; |
3339 | ||
9d5c8243 AK |
3340 | switch (current_itr) { |
3341 | /* counts and packets in update_itr are dependent on these numbers */ | |
3342 | case lowest_latency: | |
78b1f607 | 3343 | new_itr = 56; /* aka 70,000 ints/sec */ |
9d5c8243 AK |
3344 | break; |
3345 | case low_latency: | |
78b1f607 | 3346 | new_itr = 196; /* aka 20,000 ints/sec */ |
9d5c8243 AK |
3347 | break; |
3348 | case bulk_latency: | |
78b1f607 | 3349 | new_itr = 980; /* aka 4,000 ints/sec */ |
9d5c8243 AK |
3350 | break; |
3351 | default: | |
3352 | break; | |
3353 | } | |
3354 | ||
3355 | set_itr_now: | |
6eb5a7f1 AD |
3356 | adapter->rx_ring->total_bytes = 0; |
3357 | adapter->rx_ring->total_packets = 0; | |
047e0030 AD |
3358 | adapter->tx_ring->total_bytes = 0; |
3359 | adapter->tx_ring->total_packets = 0; | |
6eb5a7f1 | 3360 | |
047e0030 | 3361 | if (new_itr != q_vector->itr_val) { |
9d5c8243 AK |
3362 | /* this attempts to bias the interrupt rate towards Bulk |
3363 | * by adding intermediate steps when interrupt rate is | |
3364 | * increasing */ | |
047e0030 AD |
3365 | new_itr = new_itr > q_vector->itr_val ? |
3366 | max((new_itr * q_vector->itr_val) / | |
3367 | (new_itr + (q_vector->itr_val >> 2)), | |
3368 | new_itr) : | |
9d5c8243 AK |
3369 | new_itr; |
3370 | /* Don't write the value here; it resets the adapter's | |
3371 | * internal timer, and causes us to delay far longer than | |
3372 | * we should between interrupts. Instead, we write the ITR | |
3373 | * value at the beginning of the next interrupt so the timing | |
3374 | * ends up being correct. | |
3375 | */ | |
047e0030 AD |
3376 | q_vector->itr_val = new_itr; |
3377 | q_vector->set_itr = 1; | |
9d5c8243 AK |
3378 | } |
3379 | ||
3380 | return; | |
3381 | } | |
3382 | ||
9d5c8243 AK |
3383 | #define IGB_TX_FLAGS_CSUM 0x00000001 |
3384 | #define IGB_TX_FLAGS_VLAN 0x00000002 | |
3385 | #define IGB_TX_FLAGS_TSO 0x00000004 | |
3386 | #define IGB_TX_FLAGS_IPV4 0x00000008 | |
cdfd01fc AD |
3387 | #define IGB_TX_FLAGS_TSTAMP 0x00000010 |
3388 | #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 | |
3389 | #define IGB_TX_FLAGS_VLAN_SHIFT 16 | |
9d5c8243 | 3390 | |
85ad76b2 | 3391 | static inline int igb_tso_adv(struct igb_ring *tx_ring, |
9d5c8243 AK |
3392 | struct sk_buff *skb, u32 tx_flags, u8 *hdr_len) |
3393 | { | |
3394 | struct e1000_adv_tx_context_desc *context_desc; | |
3395 | unsigned int i; | |
3396 | int err; | |
3397 | struct igb_buffer *buffer_info; | |
3398 | u32 info = 0, tu_cmd = 0; | |
3399 | u32 mss_l4len_idx, l4len; | |
3400 | *hdr_len = 0; | |
3401 | ||
3402 | if (skb_header_cloned(skb)) { | |
3403 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
3404 | if (err) | |
3405 | return err; | |
3406 | } | |
3407 | ||
3408 | l4len = tcp_hdrlen(skb); | |
3409 | *hdr_len += l4len; | |
3410 | ||
3411 | if (skb->protocol == htons(ETH_P_IP)) { | |
3412 | struct iphdr *iph = ip_hdr(skb); | |
3413 | iph->tot_len = 0; | |
3414 | iph->check = 0; | |
3415 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
3416 | iph->daddr, 0, | |
3417 | IPPROTO_TCP, | |
3418 | 0); | |
3419 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | |
3420 | ipv6_hdr(skb)->payload_len = 0; | |
3421 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
3422 | &ipv6_hdr(skb)->daddr, | |
3423 | 0, IPPROTO_TCP, 0); | |
3424 | } | |
3425 | ||
3426 | i = tx_ring->next_to_use; | |
3427 | ||
3428 | buffer_info = &tx_ring->buffer_info[i]; | |
3429 | context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i); | |
3430 | /* VLAN MACLEN IPLEN */ | |
3431 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
3432 | info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK); | |
3433 | info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); | |
3434 | *hdr_len += skb_network_offset(skb); | |
3435 | info |= skb_network_header_len(skb); | |
3436 | *hdr_len += skb_network_header_len(skb); | |
3437 | context_desc->vlan_macip_lens = cpu_to_le32(info); | |
3438 | ||
3439 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
3440 | tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT); | |
3441 | ||
3442 | if (skb->protocol == htons(ETH_P_IP)) | |
3443 | tu_cmd |= E1000_ADVTXD_TUCMD_IPV4; | |
3444 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
3445 | ||
3446 | context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); | |
3447 | ||
3448 | /* MSS L4LEN IDX */ | |
3449 | mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT); | |
3450 | mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT); | |
3451 | ||
73cd78f1 | 3452 | /* For 82575, context index must be unique per ring. */ |
85ad76b2 AD |
3453 | if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) |
3454 | mss_l4len_idx |= tx_ring->reg_idx << 4; | |
9d5c8243 AK |
3455 | |
3456 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
3457 | context_desc->seqnum_seed = 0; | |
3458 | ||
3459 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 3460 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
3461 | buffer_info->dma = 0; |
3462 | i++; | |
3463 | if (i == tx_ring->count) | |
3464 | i = 0; | |
3465 | ||
3466 | tx_ring->next_to_use = i; | |
3467 | ||
3468 | return true; | |
3469 | } | |
3470 | ||
85ad76b2 AD |
3471 | static inline bool igb_tx_csum_adv(struct igb_ring *tx_ring, |
3472 | struct sk_buff *skb, u32 tx_flags) | |
9d5c8243 AK |
3473 | { |
3474 | struct e1000_adv_tx_context_desc *context_desc; | |
80785298 | 3475 | struct pci_dev *pdev = tx_ring->pdev; |
9d5c8243 AK |
3476 | struct igb_buffer *buffer_info; |
3477 | u32 info = 0, tu_cmd = 0; | |
80785298 | 3478 | unsigned int i; |
9d5c8243 AK |
3479 | |
3480 | if ((skb->ip_summed == CHECKSUM_PARTIAL) || | |
3481 | (tx_flags & IGB_TX_FLAGS_VLAN)) { | |
3482 | i = tx_ring->next_to_use; | |
3483 | buffer_info = &tx_ring->buffer_info[i]; | |
3484 | context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i); | |
3485 | ||
3486 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
3487 | info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK); | |
cdfd01fc | 3488 | |
9d5c8243 AK |
3489 | info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT); |
3490 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
3491 | info |= skb_network_header_len(skb); | |
3492 | ||
3493 | context_desc->vlan_macip_lens = cpu_to_le32(info); | |
3494 | ||
3495 | tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT); | |
3496 | ||
3497 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
fa4a7ef3 AJ |
3498 | __be16 protocol; |
3499 | ||
3500 | if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) { | |
3501 | const struct vlan_ethhdr *vhdr = | |
3502 | (const struct vlan_ethhdr*)skb->data; | |
3503 | ||
3504 | protocol = vhdr->h_vlan_encapsulated_proto; | |
3505 | } else { | |
3506 | protocol = skb->protocol; | |
3507 | } | |
3508 | ||
3509 | switch (protocol) { | |
09640e63 | 3510 | case cpu_to_be16(ETH_P_IP): |
9d5c8243 | 3511 | tu_cmd |= E1000_ADVTXD_TUCMD_IPV4; |
44b0cda3 MW |
3512 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
3513 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
b9473560 JB |
3514 | else if (ip_hdr(skb)->protocol == IPPROTO_SCTP) |
3515 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; | |
44b0cda3 | 3516 | break; |
09640e63 | 3517 | case cpu_to_be16(ETH_P_IPV6): |
44b0cda3 MW |
3518 | /* XXX what about other V6 headers?? */ |
3519 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
3520 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
b9473560 JB |
3521 | else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP) |
3522 | tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; | |
44b0cda3 MW |
3523 | break; |
3524 | default: | |
3525 | if (unlikely(net_ratelimit())) | |
80785298 | 3526 | dev_warn(&pdev->dev, |
44b0cda3 MW |
3527 | "partial checksum but proto=%x!\n", |
3528 | skb->protocol); | |
3529 | break; | |
3530 | } | |
9d5c8243 AK |
3531 | } |
3532 | ||
3533 | context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd); | |
3534 | context_desc->seqnum_seed = 0; | |
85ad76b2 | 3535 | if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) |
7dfc16fa | 3536 | context_desc->mss_l4len_idx = |
85ad76b2 | 3537 | cpu_to_le32(tx_ring->reg_idx << 4); |
9d5c8243 AK |
3538 | |
3539 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 3540 | buffer_info->next_to_watch = i; |
9d5c8243 AK |
3541 | buffer_info->dma = 0; |
3542 | ||
3543 | i++; | |
3544 | if (i == tx_ring->count) | |
3545 | i = 0; | |
3546 | tx_ring->next_to_use = i; | |
3547 | ||
3548 | return true; | |
3549 | } | |
9d5c8243 AK |
3550 | return false; |
3551 | } | |
3552 | ||
3553 | #define IGB_MAX_TXD_PWR 16 | |
3554 | #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) | |
3555 | ||
80785298 | 3556 | static inline int igb_tx_map_adv(struct igb_ring *tx_ring, struct sk_buff *skb, |
0e014cb1 | 3557 | unsigned int first) |
9d5c8243 AK |
3558 | { |
3559 | struct igb_buffer *buffer_info; | |
80785298 | 3560 | struct pci_dev *pdev = tx_ring->pdev; |
9d5c8243 AK |
3561 | unsigned int len = skb_headlen(skb); |
3562 | unsigned int count = 0, i; | |
3563 | unsigned int f; | |
65689fef | 3564 | dma_addr_t *map; |
9d5c8243 AK |
3565 | |
3566 | i = tx_ring->next_to_use; | |
3567 | ||
80785298 AD |
3568 | if (skb_dma_map(&pdev->dev, skb, DMA_TO_DEVICE)) { |
3569 | dev_err(&pdev->dev, "TX DMA map failed\n"); | |
65689fef AD |
3570 | return 0; |
3571 | } | |
3572 | ||
3573 | map = skb_shinfo(skb)->dma_maps; | |
3574 | ||
9d5c8243 AK |
3575 | buffer_info = &tx_ring->buffer_info[i]; |
3576 | BUG_ON(len >= IGB_MAX_DATA_PER_TXD); | |
3577 | buffer_info->length = len; | |
3578 | /* set time_stamp *before* dma to help avoid a possible race */ | |
3579 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 3580 | buffer_info->next_to_watch = i; |
042a53a9 | 3581 | buffer_info->dma = skb_shinfo(skb)->dma_head; |
9d5c8243 AK |
3582 | |
3583 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) { | |
3584 | struct skb_frag_struct *frag; | |
3585 | ||
65689fef AD |
3586 | i++; |
3587 | if (i == tx_ring->count) | |
3588 | i = 0; | |
3589 | ||
9d5c8243 AK |
3590 | frag = &skb_shinfo(skb)->frags[f]; |
3591 | len = frag->size; | |
3592 | ||
3593 | buffer_info = &tx_ring->buffer_info[i]; | |
3594 | BUG_ON(len >= IGB_MAX_DATA_PER_TXD); | |
3595 | buffer_info->length = len; | |
3596 | buffer_info->time_stamp = jiffies; | |
0e014cb1 | 3597 | buffer_info->next_to_watch = i; |
65689fef | 3598 | buffer_info->dma = map[count]; |
9d5c8243 | 3599 | count++; |
9d5c8243 AK |
3600 | } |
3601 | ||
9d5c8243 | 3602 | tx_ring->buffer_info[i].skb = skb; |
0e014cb1 | 3603 | tx_ring->buffer_info[first].next_to_watch = i; |
9d5c8243 | 3604 | |
cdfd01fc | 3605 | return ++count; |
9d5c8243 AK |
3606 | } |
3607 | ||
85ad76b2 | 3608 | static inline void igb_tx_queue_adv(struct igb_ring *tx_ring, |
9d5c8243 AK |
3609 | int tx_flags, int count, u32 paylen, |
3610 | u8 hdr_len) | |
3611 | { | |
cdfd01fc | 3612 | union e1000_adv_tx_desc *tx_desc; |
9d5c8243 AK |
3613 | struct igb_buffer *buffer_info; |
3614 | u32 olinfo_status = 0, cmd_type_len; | |
cdfd01fc | 3615 | unsigned int i = tx_ring->next_to_use; |
9d5c8243 AK |
3616 | |
3617 | cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS | | |
3618 | E1000_ADVTXD_DCMD_DEXT); | |
3619 | ||
3620 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
3621 | cmd_type_len |= E1000_ADVTXD_DCMD_VLE; | |
3622 | ||
33af6bcc PO |
3623 | if (tx_flags & IGB_TX_FLAGS_TSTAMP) |
3624 | cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP; | |
3625 | ||
9d5c8243 AK |
3626 | if (tx_flags & IGB_TX_FLAGS_TSO) { |
3627 | cmd_type_len |= E1000_ADVTXD_DCMD_TSE; | |
3628 | ||
3629 | /* insert tcp checksum */ | |
3630 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; | |
3631 | ||
3632 | /* insert ip checksum */ | |
3633 | if (tx_flags & IGB_TX_FLAGS_IPV4) | |
3634 | olinfo_status |= E1000_TXD_POPTS_IXSM << 8; | |
3635 | ||
3636 | } else if (tx_flags & IGB_TX_FLAGS_CSUM) { | |
3637 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; | |
3638 | } | |
3639 | ||
85ad76b2 AD |
3640 | if ((tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) && |
3641 | (tx_flags & (IGB_TX_FLAGS_CSUM | | |
3642 | IGB_TX_FLAGS_TSO | | |
7dfc16fa | 3643 | IGB_TX_FLAGS_VLAN))) |
85ad76b2 | 3644 | olinfo_status |= tx_ring->reg_idx << 4; |
9d5c8243 AK |
3645 | |
3646 | olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT); | |
3647 | ||
cdfd01fc | 3648 | do { |
9d5c8243 AK |
3649 | buffer_info = &tx_ring->buffer_info[i]; |
3650 | tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); | |
3651 | tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); | |
3652 | tx_desc->read.cmd_type_len = | |
3653 | cpu_to_le32(cmd_type_len | buffer_info->length); | |
3654 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); | |
cdfd01fc | 3655 | count--; |
9d5c8243 AK |
3656 | i++; |
3657 | if (i == tx_ring->count) | |
3658 | i = 0; | |
cdfd01fc | 3659 | } while (count > 0); |
9d5c8243 | 3660 | |
85ad76b2 | 3661 | tx_desc->read.cmd_type_len |= cpu_to_le32(IGB_ADVTXD_DCMD); |
9d5c8243 AK |
3662 | /* Force memory writes to complete before letting h/w |
3663 | * know there are new descriptors to fetch. (Only | |
3664 | * applicable for weak-ordered memory model archs, | |
3665 | * such as IA-64). */ | |
3666 | wmb(); | |
3667 | ||
3668 | tx_ring->next_to_use = i; | |
fce99e34 | 3669 | writel(i, tx_ring->tail); |
9d5c8243 AK |
3670 | /* we need this if more than one processor can write to our tail |
3671 | * at a time, it syncronizes IO on IA64/Altix systems */ | |
3672 | mmiowb(); | |
3673 | } | |
3674 | ||
e694e964 | 3675 | static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size) |
9d5c8243 | 3676 | { |
e694e964 AD |
3677 | struct net_device *netdev = tx_ring->netdev; |
3678 | ||
661086df | 3679 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
661086df | 3680 | |
9d5c8243 AK |
3681 | /* Herbert's original patch had: |
3682 | * smp_mb__after_netif_stop_queue(); | |
3683 | * but since that doesn't exist yet, just open code it. */ | |
3684 | smp_mb(); | |
3685 | ||
3686 | /* We need to check again in a case another CPU has just | |
3687 | * made room available. */ | |
c493ea45 | 3688 | if (igb_desc_unused(tx_ring) < size) |
9d5c8243 AK |
3689 | return -EBUSY; |
3690 | ||
3691 | /* A reprieve! */ | |
661086df | 3692 | netif_wake_subqueue(netdev, tx_ring->queue_index); |
04a5fcaa | 3693 | tx_ring->tx_stats.restart_queue++; |
9d5c8243 AK |
3694 | return 0; |
3695 | } | |
3696 | ||
e694e964 | 3697 | static int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size) |
9d5c8243 | 3698 | { |
c493ea45 | 3699 | if (igb_desc_unused(tx_ring) >= size) |
9d5c8243 | 3700 | return 0; |
e694e964 | 3701 | return __igb_maybe_stop_tx(tx_ring, size); |
9d5c8243 AK |
3702 | } |
3703 | ||
b1a436c3 AD |
3704 | netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb, |
3705 | struct igb_ring *tx_ring) | |
9d5c8243 | 3706 | { |
e694e964 | 3707 | struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); |
0e014cb1 | 3708 | unsigned int first; |
9d5c8243 | 3709 | unsigned int tx_flags = 0; |
9d5c8243 | 3710 | u8 hdr_len = 0; |
cdfd01fc | 3711 | int tso = 0, count; |
c5b9bd5e | 3712 | union skb_shared_tx *shtx = skb_tx(skb); |
9d5c8243 | 3713 | |
9d5c8243 AK |
3714 | /* need: 1 descriptor per page, |
3715 | * + 2 desc gap to keep tail from touching head, | |
3716 | * + 1 desc for skb->data, | |
3717 | * + 1 desc for context descriptor, | |
3718 | * otherwise try next time */ | |
e694e964 | 3719 | if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) { |
9d5c8243 | 3720 | /* this is a hard error */ |
9d5c8243 AK |
3721 | return NETDEV_TX_BUSY; |
3722 | } | |
33af6bcc | 3723 | |
33af6bcc PO |
3724 | if (unlikely(shtx->hardware)) { |
3725 | shtx->in_progress = 1; | |
3726 | tx_flags |= IGB_TX_FLAGS_TSTAMP; | |
33af6bcc | 3727 | } |
9d5c8243 | 3728 | |
cdfd01fc | 3729 | if (vlan_tx_tag_present(skb) && adapter->vlgrp) { |
9d5c8243 AK |
3730 | tx_flags |= IGB_TX_FLAGS_VLAN; |
3731 | tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); | |
3732 | } | |
3733 | ||
661086df PWJ |
3734 | if (skb->protocol == htons(ETH_P_IP)) |
3735 | tx_flags |= IGB_TX_FLAGS_IPV4; | |
3736 | ||
0e014cb1 | 3737 | first = tx_ring->next_to_use; |
85ad76b2 AD |
3738 | if (skb_is_gso(skb)) { |
3739 | tso = igb_tso_adv(tx_ring, skb, tx_flags, &hdr_len); | |
cdfd01fc | 3740 | |
85ad76b2 AD |
3741 | if (tso < 0) { |
3742 | dev_kfree_skb_any(skb); | |
3743 | return NETDEV_TX_OK; | |
3744 | } | |
9d5c8243 AK |
3745 | } |
3746 | ||
3747 | if (tso) | |
3748 | tx_flags |= IGB_TX_FLAGS_TSO; | |
85ad76b2 | 3749 | else if (igb_tx_csum_adv(tx_ring, skb, tx_flags) && |
bc1cbd34 AD |
3750 | (skb->ip_summed == CHECKSUM_PARTIAL)) |
3751 | tx_flags |= IGB_TX_FLAGS_CSUM; | |
9d5c8243 | 3752 | |
65689fef | 3753 | /* |
cdfd01fc | 3754 | * count reflects descriptors mapped, if 0 or less then mapping error |
65689fef AD |
3755 | * has occured and we need to rewind the descriptor queue |
3756 | */ | |
80785298 | 3757 | count = igb_tx_map_adv(tx_ring, skb, first); |
cdfd01fc | 3758 | if (count <= 0) { |
65689fef AD |
3759 | dev_kfree_skb_any(skb); |
3760 | tx_ring->buffer_info[first].time_stamp = 0; | |
3761 | tx_ring->next_to_use = first; | |
85ad76b2 | 3762 | return NETDEV_TX_OK; |
65689fef | 3763 | } |
9d5c8243 | 3764 | |
85ad76b2 AD |
3765 | igb_tx_queue_adv(tx_ring, tx_flags, count, skb->len, hdr_len); |
3766 | ||
3767 | /* Make sure there is space in the ring for the next send. */ | |
e694e964 | 3768 | igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4); |
85ad76b2 | 3769 | |
9d5c8243 AK |
3770 | return NETDEV_TX_OK; |
3771 | } | |
3772 | ||
3b29a56d SH |
3773 | static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb, |
3774 | struct net_device *netdev) | |
9d5c8243 AK |
3775 | { |
3776 | struct igb_adapter *adapter = netdev_priv(netdev); | |
661086df | 3777 | struct igb_ring *tx_ring; |
661086df | 3778 | int r_idx = 0; |
b1a436c3 AD |
3779 | |
3780 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
3781 | dev_kfree_skb_any(skb); | |
3782 | return NETDEV_TX_OK; | |
3783 | } | |
3784 | ||
3785 | if (skb->len <= 0) { | |
3786 | dev_kfree_skb_any(skb); | |
3787 | return NETDEV_TX_OK; | |
3788 | } | |
3789 | ||
1bfaf07b | 3790 | r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1); |
661086df | 3791 | tx_ring = adapter->multi_tx_table[r_idx]; |
9d5c8243 AK |
3792 | |
3793 | /* This goes back to the question of how to logically map a tx queue | |
3794 | * to a flow. Right now, performance is impacted slightly negatively | |
3795 | * if using multiple tx queues. If the stack breaks away from a | |
3796 | * single qdisc implementation, we can look at this again. */ | |
e694e964 | 3797 | return igb_xmit_frame_ring_adv(skb, tx_ring); |
9d5c8243 AK |
3798 | } |
3799 | ||
3800 | /** | |
3801 | * igb_tx_timeout - Respond to a Tx Hang | |
3802 | * @netdev: network interface device structure | |
3803 | **/ | |
3804 | static void igb_tx_timeout(struct net_device *netdev) | |
3805 | { | |
3806 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3807 | struct e1000_hw *hw = &adapter->hw; | |
3808 | ||
3809 | /* Do the reset outside of interrupt context */ | |
3810 | adapter->tx_timeout_count++; | |
f7ba205e | 3811 | |
55cac248 AD |
3812 | if (hw->mac.type == e1000_82580) |
3813 | hw->dev_spec._82575.global_device_reset = true; | |
3814 | ||
9d5c8243 | 3815 | schedule_work(&adapter->reset_task); |
265de409 AD |
3816 | wr32(E1000_EICS, |
3817 | (adapter->eims_enable_mask & ~adapter->eims_other)); | |
9d5c8243 AK |
3818 | } |
3819 | ||
3820 | static void igb_reset_task(struct work_struct *work) | |
3821 | { | |
3822 | struct igb_adapter *adapter; | |
3823 | adapter = container_of(work, struct igb_adapter, reset_task); | |
3824 | ||
3825 | igb_reinit_locked(adapter); | |
3826 | } | |
3827 | ||
3828 | /** | |
3829 | * igb_get_stats - Get System Network Statistics | |
3830 | * @netdev: network interface device structure | |
3831 | * | |
3832 | * Returns the address of the device statistics structure. | |
3833 | * The statistics are actually updated from the timer callback. | |
3834 | **/ | |
73cd78f1 | 3835 | static struct net_device_stats *igb_get_stats(struct net_device *netdev) |
9d5c8243 | 3836 | { |
9d5c8243 | 3837 | /* only return the current stats */ |
8d24e933 | 3838 | return &netdev->stats; |
9d5c8243 AK |
3839 | } |
3840 | ||
3841 | /** | |
3842 | * igb_change_mtu - Change the Maximum Transfer Unit | |
3843 | * @netdev: network interface device structure | |
3844 | * @new_mtu: new value for maximum frame size | |
3845 | * | |
3846 | * Returns 0 on success, negative on failure | |
3847 | **/ | |
3848 | static int igb_change_mtu(struct net_device *netdev, int new_mtu) | |
3849 | { | |
3850 | struct igb_adapter *adapter = netdev_priv(netdev); | |
090b1795 | 3851 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 | 3852 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; |
4c844851 | 3853 | u32 rx_buffer_len, i; |
9d5c8243 | 3854 | |
c809d227 | 3855 | if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { |
090b1795 | 3856 | dev_err(&pdev->dev, "Invalid MTU setting\n"); |
9d5c8243 AK |
3857 | return -EINVAL; |
3858 | } | |
3859 | ||
9d5c8243 | 3860 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { |
090b1795 | 3861 | dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); |
9d5c8243 AK |
3862 | return -EINVAL; |
3863 | } | |
3864 | ||
3865 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
3866 | msleep(1); | |
73cd78f1 | 3867 | |
9d5c8243 AK |
3868 | /* igb_down has a dependency on max_frame_size */ |
3869 | adapter->max_frame_size = max_frame; | |
559e9c49 | 3870 | |
9d5c8243 AK |
3871 | /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN |
3872 | * means we reserve 2 more, this pushes us to allocate from the next | |
3873 | * larger slab size. | |
3874 | * i.e. RXBUFFER_2048 --> size-4096 slab | |
3875 | */ | |
3876 | ||
7d95b717 | 3877 | if (max_frame <= IGB_RXBUFFER_1024) |
4c844851 | 3878 | rx_buffer_len = IGB_RXBUFFER_1024; |
6ec43fe6 | 3879 | else if (max_frame <= MAXIMUM_ETHERNET_VLAN_SIZE) |
4c844851 | 3880 | rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
6ec43fe6 | 3881 | else |
4c844851 AD |
3882 | rx_buffer_len = IGB_RXBUFFER_128; |
3883 | ||
3884 | if (netif_running(netdev)) | |
3885 | igb_down(adapter); | |
9d5c8243 | 3886 | |
090b1795 | 3887 | dev_info(&pdev->dev, "changing MTU from %d to %d\n", |
9d5c8243 AK |
3888 | netdev->mtu, new_mtu); |
3889 | netdev->mtu = new_mtu; | |
3890 | ||
4c844851 AD |
3891 | for (i = 0; i < adapter->num_rx_queues; i++) |
3892 | adapter->rx_ring[i].rx_buffer_len = rx_buffer_len; | |
3893 | ||
9d5c8243 AK |
3894 | if (netif_running(netdev)) |
3895 | igb_up(adapter); | |
3896 | else | |
3897 | igb_reset(adapter); | |
3898 | ||
3899 | clear_bit(__IGB_RESETTING, &adapter->state); | |
3900 | ||
3901 | return 0; | |
3902 | } | |
3903 | ||
3904 | /** | |
3905 | * igb_update_stats - Update the board statistics counters | |
3906 | * @adapter: board private structure | |
3907 | **/ | |
3908 | ||
3909 | void igb_update_stats(struct igb_adapter *adapter) | |
3910 | { | |
128e45eb | 3911 | struct net_device_stats *net_stats = igb_get_stats(adapter->netdev); |
9d5c8243 AK |
3912 | struct e1000_hw *hw = &adapter->hw; |
3913 | struct pci_dev *pdev = adapter->pdev; | |
3f9c0164 | 3914 | u32 rnbc; |
9d5c8243 | 3915 | u16 phy_tmp; |
3f9c0164 AD |
3916 | int i; |
3917 | u64 bytes, packets; | |
9d5c8243 AK |
3918 | |
3919 | #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF | |
3920 | ||
3921 | /* | |
3922 | * Prevent stats update while adapter is being reset, or if the pci | |
3923 | * connection is down. | |
3924 | */ | |
3925 | if (adapter->link_speed == 0) | |
3926 | return; | |
3927 | if (pci_channel_offline(pdev)) | |
3928 | return; | |
3929 | ||
3f9c0164 AD |
3930 | bytes = 0; |
3931 | packets = 0; | |
3932 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3933 | u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF; | |
3934 | adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp; | |
128e45eb | 3935 | net_stats->rx_fifo_errors += rqdpc_tmp; |
3f9c0164 AD |
3936 | bytes += adapter->rx_ring[i].rx_stats.bytes; |
3937 | packets += adapter->rx_ring[i].rx_stats.packets; | |
3938 | } | |
3939 | ||
128e45eb AD |
3940 | net_stats->rx_bytes = bytes; |
3941 | net_stats->rx_packets = packets; | |
3f9c0164 AD |
3942 | |
3943 | bytes = 0; | |
3944 | packets = 0; | |
3945 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3946 | bytes += adapter->tx_ring[i].tx_stats.bytes; | |
3947 | packets += adapter->tx_ring[i].tx_stats.packets; | |
3948 | } | |
128e45eb AD |
3949 | net_stats->tx_bytes = bytes; |
3950 | net_stats->tx_packets = packets; | |
3f9c0164 AD |
3951 | |
3952 | /* read stats registers */ | |
9d5c8243 AK |
3953 | adapter->stats.crcerrs += rd32(E1000_CRCERRS); |
3954 | adapter->stats.gprc += rd32(E1000_GPRC); | |
3955 | adapter->stats.gorc += rd32(E1000_GORCL); | |
3956 | rd32(E1000_GORCH); /* clear GORCL */ | |
3957 | adapter->stats.bprc += rd32(E1000_BPRC); | |
3958 | adapter->stats.mprc += rd32(E1000_MPRC); | |
3959 | adapter->stats.roc += rd32(E1000_ROC); | |
3960 | ||
3961 | adapter->stats.prc64 += rd32(E1000_PRC64); | |
3962 | adapter->stats.prc127 += rd32(E1000_PRC127); | |
3963 | adapter->stats.prc255 += rd32(E1000_PRC255); | |
3964 | adapter->stats.prc511 += rd32(E1000_PRC511); | |
3965 | adapter->stats.prc1023 += rd32(E1000_PRC1023); | |
3966 | adapter->stats.prc1522 += rd32(E1000_PRC1522); | |
3967 | adapter->stats.symerrs += rd32(E1000_SYMERRS); | |
3968 | adapter->stats.sec += rd32(E1000_SEC); | |
3969 | ||
3970 | adapter->stats.mpc += rd32(E1000_MPC); | |
3971 | adapter->stats.scc += rd32(E1000_SCC); | |
3972 | adapter->stats.ecol += rd32(E1000_ECOL); | |
3973 | adapter->stats.mcc += rd32(E1000_MCC); | |
3974 | adapter->stats.latecol += rd32(E1000_LATECOL); | |
3975 | adapter->stats.dc += rd32(E1000_DC); | |
3976 | adapter->stats.rlec += rd32(E1000_RLEC); | |
3977 | adapter->stats.xonrxc += rd32(E1000_XONRXC); | |
3978 | adapter->stats.xontxc += rd32(E1000_XONTXC); | |
3979 | adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); | |
3980 | adapter->stats.xofftxc += rd32(E1000_XOFFTXC); | |
3981 | adapter->stats.fcruc += rd32(E1000_FCRUC); | |
3982 | adapter->stats.gptc += rd32(E1000_GPTC); | |
3983 | adapter->stats.gotc += rd32(E1000_GOTCL); | |
3984 | rd32(E1000_GOTCH); /* clear GOTCL */ | |
3f9c0164 AD |
3985 | rnbc = rd32(E1000_RNBC); |
3986 | adapter->stats.rnbc += rnbc; | |
128e45eb | 3987 | net_stats->rx_fifo_errors += rnbc; |
9d5c8243 AK |
3988 | adapter->stats.ruc += rd32(E1000_RUC); |
3989 | adapter->stats.rfc += rd32(E1000_RFC); | |
3990 | adapter->stats.rjc += rd32(E1000_RJC); | |
3991 | adapter->stats.tor += rd32(E1000_TORH); | |
3992 | adapter->stats.tot += rd32(E1000_TOTH); | |
3993 | adapter->stats.tpr += rd32(E1000_TPR); | |
3994 | ||
3995 | adapter->stats.ptc64 += rd32(E1000_PTC64); | |
3996 | adapter->stats.ptc127 += rd32(E1000_PTC127); | |
3997 | adapter->stats.ptc255 += rd32(E1000_PTC255); | |
3998 | adapter->stats.ptc511 += rd32(E1000_PTC511); | |
3999 | adapter->stats.ptc1023 += rd32(E1000_PTC1023); | |
4000 | adapter->stats.ptc1522 += rd32(E1000_PTC1522); | |
4001 | ||
4002 | adapter->stats.mptc += rd32(E1000_MPTC); | |
4003 | adapter->stats.bptc += rd32(E1000_BPTC); | |
4004 | ||
4005 | /* used for adaptive IFS */ | |
9d5c8243 AK |
4006 | hw->mac.tx_packet_delta = rd32(E1000_TPT); |
4007 | adapter->stats.tpt += hw->mac.tx_packet_delta; | |
4008 | hw->mac.collision_delta = rd32(E1000_COLC); | |
4009 | adapter->stats.colc += hw->mac.collision_delta; | |
4010 | ||
4011 | adapter->stats.algnerrc += rd32(E1000_ALGNERRC); | |
4012 | adapter->stats.rxerrc += rd32(E1000_RXERRC); | |
4013 | adapter->stats.tncrs += rd32(E1000_TNCRS); | |
4014 | adapter->stats.tsctc += rd32(E1000_TSCTC); | |
4015 | adapter->stats.tsctfc += rd32(E1000_TSCTFC); | |
4016 | ||
4017 | adapter->stats.iac += rd32(E1000_IAC); | |
4018 | adapter->stats.icrxoc += rd32(E1000_ICRXOC); | |
4019 | adapter->stats.icrxptc += rd32(E1000_ICRXPTC); | |
4020 | adapter->stats.icrxatc += rd32(E1000_ICRXATC); | |
4021 | adapter->stats.ictxptc += rd32(E1000_ICTXPTC); | |
4022 | adapter->stats.ictxatc += rd32(E1000_ICTXATC); | |
4023 | adapter->stats.ictxqec += rd32(E1000_ICTXQEC); | |
4024 | adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); | |
4025 | adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); | |
4026 | ||
4027 | /* Fill out the OS statistics structure */ | |
128e45eb AD |
4028 | net_stats->multicast = adapter->stats.mprc; |
4029 | net_stats->collisions = adapter->stats.colc; | |
9d5c8243 AK |
4030 | |
4031 | /* Rx Errors */ | |
4032 | ||
4033 | /* RLEC on some newer hardware can be incorrect so build | |
8c0ab70a | 4034 | * our own version based on RUC and ROC */ |
128e45eb | 4035 | net_stats->rx_errors = adapter->stats.rxerrc + |
9d5c8243 AK |
4036 | adapter->stats.crcerrs + adapter->stats.algnerrc + |
4037 | adapter->stats.ruc + adapter->stats.roc + | |
4038 | adapter->stats.cexterr; | |
128e45eb AD |
4039 | net_stats->rx_length_errors = adapter->stats.ruc + |
4040 | adapter->stats.roc; | |
4041 | net_stats->rx_crc_errors = adapter->stats.crcerrs; | |
4042 | net_stats->rx_frame_errors = adapter->stats.algnerrc; | |
4043 | net_stats->rx_missed_errors = adapter->stats.mpc; | |
9d5c8243 AK |
4044 | |
4045 | /* Tx Errors */ | |
128e45eb AD |
4046 | net_stats->tx_errors = adapter->stats.ecol + |
4047 | adapter->stats.latecol; | |
4048 | net_stats->tx_aborted_errors = adapter->stats.ecol; | |
4049 | net_stats->tx_window_errors = adapter->stats.latecol; | |
4050 | net_stats->tx_carrier_errors = adapter->stats.tncrs; | |
9d5c8243 AK |
4051 | |
4052 | /* Tx Dropped needs to be maintained elsewhere */ | |
4053 | ||
4054 | /* Phy Stats */ | |
4055 | if (hw->phy.media_type == e1000_media_type_copper) { | |
4056 | if ((adapter->link_speed == SPEED_1000) && | |
73cd78f1 | 4057 | (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { |
9d5c8243 AK |
4058 | phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; |
4059 | adapter->phy_stats.idle_errors += phy_tmp; | |
4060 | } | |
4061 | } | |
4062 | ||
4063 | /* Management Stats */ | |
4064 | adapter->stats.mgptc += rd32(E1000_MGTPTC); | |
4065 | adapter->stats.mgprc += rd32(E1000_MGTPRC); | |
4066 | adapter->stats.mgpdc += rd32(E1000_MGTPDC); | |
4067 | } | |
4068 | ||
9d5c8243 AK |
4069 | static irqreturn_t igb_msix_other(int irq, void *data) |
4070 | { | |
047e0030 | 4071 | struct igb_adapter *adapter = data; |
9d5c8243 | 4072 | struct e1000_hw *hw = &adapter->hw; |
844290e5 | 4073 | u32 icr = rd32(E1000_ICR); |
844290e5 | 4074 | /* reading ICR causes bit 31 of EICR to be cleared */ |
dda0e083 | 4075 | |
047e0030 | 4076 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
4077 | /* HW is reporting DMA is out of sync */ |
4078 | adapter->stats.doosync++; | |
4079 | } | |
eebbbdba | 4080 | |
4ae196df AD |
4081 | /* Check for a mailbox event */ |
4082 | if (icr & E1000_ICR_VMMB) | |
4083 | igb_msg_task(adapter); | |
4084 | ||
4085 | if (icr & E1000_ICR_LSC) { | |
4086 | hw->mac.get_link_status = 1; | |
4087 | /* guard against interrupt when we're going down */ | |
4088 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4089 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
4090 | } | |
4091 | ||
25568a53 AD |
4092 | if (adapter->vfs_allocated_count) |
4093 | wr32(E1000_IMS, E1000_IMS_LSC | | |
4094 | E1000_IMS_VMMB | | |
4095 | E1000_IMS_DOUTSYNC); | |
4096 | else | |
4097 | wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC); | |
844290e5 | 4098 | wr32(E1000_EIMS, adapter->eims_other); |
9d5c8243 AK |
4099 | |
4100 | return IRQ_HANDLED; | |
4101 | } | |
4102 | ||
047e0030 | 4103 | static void igb_write_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 4104 | { |
047e0030 | 4105 | u32 itr_val = q_vector->itr_val & 0x7FFC; |
9d5c8243 | 4106 | |
047e0030 AD |
4107 | if (!q_vector->set_itr) |
4108 | return; | |
73cd78f1 | 4109 | |
047e0030 AD |
4110 | if (!itr_val) |
4111 | itr_val = 0x4; | |
661086df | 4112 | |
047e0030 AD |
4113 | if (q_vector->itr_shift) |
4114 | itr_val |= itr_val << q_vector->itr_shift; | |
661086df | 4115 | else |
047e0030 | 4116 | itr_val |= 0x8000000; |
661086df | 4117 | |
047e0030 AD |
4118 | writel(itr_val, q_vector->itr_register); |
4119 | q_vector->set_itr = 0; | |
6eb5a7f1 AD |
4120 | } |
4121 | ||
047e0030 | 4122 | static irqreturn_t igb_msix_ring(int irq, void *data) |
9d5c8243 | 4123 | { |
047e0030 | 4124 | struct igb_q_vector *q_vector = data; |
9d5c8243 | 4125 | |
047e0030 AD |
4126 | /* Write the ITR value calculated from the previous interrupt. */ |
4127 | igb_write_itr(q_vector); | |
9d5c8243 | 4128 | |
047e0030 | 4129 | napi_schedule(&q_vector->napi); |
844290e5 | 4130 | |
047e0030 | 4131 | return IRQ_HANDLED; |
fe4506b6 JC |
4132 | } |
4133 | ||
421e02f0 | 4134 | #ifdef CONFIG_IGB_DCA |
047e0030 | 4135 | static void igb_update_dca(struct igb_q_vector *q_vector) |
fe4506b6 | 4136 | { |
047e0030 | 4137 | struct igb_adapter *adapter = q_vector->adapter; |
fe4506b6 JC |
4138 | struct e1000_hw *hw = &adapter->hw; |
4139 | int cpu = get_cpu(); | |
fe4506b6 | 4140 | |
047e0030 AD |
4141 | if (q_vector->cpu == cpu) |
4142 | goto out_no_update; | |
4143 | ||
4144 | if (q_vector->tx_ring) { | |
4145 | int q = q_vector->tx_ring->reg_idx; | |
4146 | u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q)); | |
4147 | if (hw->mac.type == e1000_82575) { | |
4148 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK; | |
4149 | dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
2d064c06 | 4150 | } else { |
047e0030 AD |
4151 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576; |
4152 | dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << | |
4153 | E1000_DCA_TXCTRL_CPUID_SHIFT; | |
4154 | } | |
4155 | dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN; | |
4156 | wr32(E1000_DCA_TXCTRL(q), dca_txctrl); | |
4157 | } | |
4158 | if (q_vector->rx_ring) { | |
4159 | int q = q_vector->rx_ring->reg_idx; | |
4160 | u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q)); | |
4161 | if (hw->mac.type == e1000_82575) { | |
2d064c06 | 4162 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK; |
92be7917 | 4163 | dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); |
047e0030 AD |
4164 | } else { |
4165 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576; | |
4166 | dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << | |
4167 | E1000_DCA_RXCTRL_CPUID_SHIFT; | |
2d064c06 | 4168 | } |
fe4506b6 JC |
4169 | dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN; |
4170 | dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN; | |
4171 | dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN; | |
4172 | wr32(E1000_DCA_RXCTRL(q), dca_rxctrl); | |
fe4506b6 | 4173 | } |
047e0030 AD |
4174 | q_vector->cpu = cpu; |
4175 | out_no_update: | |
fe4506b6 JC |
4176 | put_cpu(); |
4177 | } | |
4178 | ||
4179 | static void igb_setup_dca(struct igb_adapter *adapter) | |
4180 | { | |
7e0e99ef | 4181 | struct e1000_hw *hw = &adapter->hw; |
fe4506b6 JC |
4182 | int i; |
4183 | ||
7dfc16fa | 4184 | if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) |
fe4506b6 JC |
4185 | return; |
4186 | ||
7e0e99ef AD |
4187 | /* Always use CB2 mode, difference is masked in the CB driver. */ |
4188 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); | |
4189 | ||
047e0030 AD |
4190 | for (i = 0; i < adapter->num_q_vectors; i++) { |
4191 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
4192 | q_vector->cpu = -1; | |
4193 | igb_update_dca(q_vector); | |
fe4506b6 JC |
4194 | } |
4195 | } | |
4196 | ||
4197 | static int __igb_notify_dca(struct device *dev, void *data) | |
4198 | { | |
4199 | struct net_device *netdev = dev_get_drvdata(dev); | |
4200 | struct igb_adapter *adapter = netdev_priv(netdev); | |
090b1795 | 4201 | struct pci_dev *pdev = adapter->pdev; |
fe4506b6 JC |
4202 | struct e1000_hw *hw = &adapter->hw; |
4203 | unsigned long event = *(unsigned long *)data; | |
4204 | ||
4205 | switch (event) { | |
4206 | case DCA_PROVIDER_ADD: | |
4207 | /* if already enabled, don't do it again */ | |
7dfc16fa | 4208 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 | 4209 | break; |
fe4506b6 | 4210 | if (dca_add_requester(dev) == 0) { |
bbd98fe4 | 4211 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
090b1795 | 4212 | dev_info(&pdev->dev, "DCA enabled\n"); |
fe4506b6 JC |
4213 | igb_setup_dca(adapter); |
4214 | break; | |
4215 | } | |
4216 | /* Fall Through since DCA is disabled. */ | |
4217 | case DCA_PROVIDER_REMOVE: | |
7dfc16fa | 4218 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 | 4219 | /* without this a class_device is left |
047e0030 | 4220 | * hanging around in the sysfs model */ |
fe4506b6 | 4221 | dca_remove_requester(dev); |
090b1795 | 4222 | dev_info(&pdev->dev, "DCA disabled\n"); |
7dfc16fa | 4223 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 4224 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
4225 | } |
4226 | break; | |
4227 | } | |
bbd98fe4 | 4228 | |
fe4506b6 | 4229 | return 0; |
9d5c8243 AK |
4230 | } |
4231 | ||
fe4506b6 JC |
4232 | static int igb_notify_dca(struct notifier_block *nb, unsigned long event, |
4233 | void *p) | |
4234 | { | |
4235 | int ret_val; | |
4236 | ||
4237 | ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, | |
4238 | __igb_notify_dca); | |
4239 | ||
4240 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
4241 | } | |
421e02f0 | 4242 | #endif /* CONFIG_IGB_DCA */ |
9d5c8243 | 4243 | |
4ae196df AD |
4244 | static void igb_ping_all_vfs(struct igb_adapter *adapter) |
4245 | { | |
4246 | struct e1000_hw *hw = &adapter->hw; | |
4247 | u32 ping; | |
4248 | int i; | |
4249 | ||
4250 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) { | |
4251 | ping = E1000_PF_CONTROL_MSG; | |
f2ca0dbe | 4252 | if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) |
4ae196df AD |
4253 | ping |= E1000_VT_MSGTYPE_CTS; |
4254 | igb_write_mbx(hw, &ping, 1, i); | |
4255 | } | |
4256 | } | |
4257 | ||
7d5753f0 AD |
4258 | static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) |
4259 | { | |
4260 | struct e1000_hw *hw = &adapter->hw; | |
4261 | u32 vmolr = rd32(E1000_VMOLR(vf)); | |
4262 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | |
4263 | ||
4264 | vf_data->flags |= ~(IGB_VF_FLAG_UNI_PROMISC | | |
4265 | IGB_VF_FLAG_MULTI_PROMISC); | |
4266 | vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); | |
4267 | ||
4268 | if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { | |
4269 | vmolr |= E1000_VMOLR_MPME; | |
4270 | *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; | |
4271 | } else { | |
4272 | /* | |
4273 | * if we have hashes and we are clearing a multicast promisc | |
4274 | * flag we need to write the hashes to the MTA as this step | |
4275 | * was previously skipped | |
4276 | */ | |
4277 | if (vf_data->num_vf_mc_hashes > 30) { | |
4278 | vmolr |= E1000_VMOLR_MPME; | |
4279 | } else if (vf_data->num_vf_mc_hashes) { | |
4280 | int j; | |
4281 | vmolr |= E1000_VMOLR_ROMPE; | |
4282 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | |
4283 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | |
4284 | } | |
4285 | } | |
4286 | ||
4287 | wr32(E1000_VMOLR(vf), vmolr); | |
4288 | ||
4289 | /* there are flags left unprocessed, likely not supported */ | |
4290 | if (*msgbuf & E1000_VT_MSGINFO_MASK) | |
4291 | return -EINVAL; | |
4292 | ||
4293 | return 0; | |
4294 | ||
4295 | } | |
4296 | ||
4ae196df AD |
4297 | static int igb_set_vf_multicasts(struct igb_adapter *adapter, |
4298 | u32 *msgbuf, u32 vf) | |
4299 | { | |
4300 | int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; | |
4301 | u16 *hash_list = (u16 *)&msgbuf[1]; | |
4302 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | |
4303 | int i; | |
4304 | ||
7d5753f0 | 4305 | /* salt away the number of multicast addresses assigned |
4ae196df AD |
4306 | * to this VF for later use to restore when the PF multi cast |
4307 | * list changes | |
4308 | */ | |
4309 | vf_data->num_vf_mc_hashes = n; | |
4310 | ||
7d5753f0 AD |
4311 | /* only up to 30 hash values supported */ |
4312 | if (n > 30) | |
4313 | n = 30; | |
4314 | ||
4315 | /* store the hashes for later use */ | |
4ae196df | 4316 | for (i = 0; i < n; i++) |
a419aef8 | 4317 | vf_data->vf_mc_hashes[i] = hash_list[i]; |
4ae196df AD |
4318 | |
4319 | /* Flush and reset the mta with the new values */ | |
ff41f8dc | 4320 | igb_set_rx_mode(adapter->netdev); |
4ae196df AD |
4321 | |
4322 | return 0; | |
4323 | } | |
4324 | ||
4325 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter) | |
4326 | { | |
4327 | struct e1000_hw *hw = &adapter->hw; | |
4328 | struct vf_data_storage *vf_data; | |
4329 | int i, j; | |
4330 | ||
4331 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
7d5753f0 AD |
4332 | u32 vmolr = rd32(E1000_VMOLR(i)); |
4333 | vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); | |
4334 | ||
4ae196df | 4335 | vf_data = &adapter->vf_data[i]; |
7d5753f0 AD |
4336 | |
4337 | if ((vf_data->num_vf_mc_hashes > 30) || | |
4338 | (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { | |
4339 | vmolr |= E1000_VMOLR_MPME; | |
4340 | } else if (vf_data->num_vf_mc_hashes) { | |
4341 | vmolr |= E1000_VMOLR_ROMPE; | |
4342 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | |
4343 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | |
4344 | } | |
4345 | wr32(E1000_VMOLR(i), vmolr); | |
4ae196df AD |
4346 | } |
4347 | } | |
4348 | ||
4349 | static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) | |
4350 | { | |
4351 | struct e1000_hw *hw = &adapter->hw; | |
4352 | u32 pool_mask, reg, vid; | |
4353 | int i; | |
4354 | ||
4355 | pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
4356 | ||
4357 | /* Find the vlan filter for this id */ | |
4358 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
4359 | reg = rd32(E1000_VLVF(i)); | |
4360 | ||
4361 | /* remove the vf from the pool */ | |
4362 | reg &= ~pool_mask; | |
4363 | ||
4364 | /* if pool is empty then remove entry from vfta */ | |
4365 | if (!(reg & E1000_VLVF_POOLSEL_MASK) && | |
4366 | (reg & E1000_VLVF_VLANID_ENABLE)) { | |
4367 | reg = 0; | |
4368 | vid = reg & E1000_VLVF_VLANID_MASK; | |
4369 | igb_vfta_set(hw, vid, false); | |
4370 | } | |
4371 | ||
4372 | wr32(E1000_VLVF(i), reg); | |
4373 | } | |
ae641bdc AD |
4374 | |
4375 | adapter->vf_data[vf].vlans_enabled = 0; | |
4ae196df AD |
4376 | } |
4377 | ||
4378 | static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) | |
4379 | { | |
4380 | struct e1000_hw *hw = &adapter->hw; | |
4381 | u32 reg, i; | |
4382 | ||
51466239 AD |
4383 | /* The vlvf table only exists on 82576 hardware and newer */ |
4384 | if (hw->mac.type < e1000_82576) | |
4385 | return -1; | |
4386 | ||
4387 | /* we only need to do this if VMDq is enabled */ | |
4ae196df AD |
4388 | if (!adapter->vfs_allocated_count) |
4389 | return -1; | |
4390 | ||
4391 | /* Find the vlan filter for this id */ | |
4392 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
4393 | reg = rd32(E1000_VLVF(i)); | |
4394 | if ((reg & E1000_VLVF_VLANID_ENABLE) && | |
4395 | vid == (reg & E1000_VLVF_VLANID_MASK)) | |
4396 | break; | |
4397 | } | |
4398 | ||
4399 | if (add) { | |
4400 | if (i == E1000_VLVF_ARRAY_SIZE) { | |
4401 | /* Did not find a matching VLAN ID entry that was | |
4402 | * enabled. Search for a free filter entry, i.e. | |
4403 | * one without the enable bit set | |
4404 | */ | |
4405 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
4406 | reg = rd32(E1000_VLVF(i)); | |
4407 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) | |
4408 | break; | |
4409 | } | |
4410 | } | |
4411 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
4412 | /* Found an enabled/available entry */ | |
4413 | reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
4414 | ||
4415 | /* if !enabled we need to set this up in vfta */ | |
4416 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) { | |
51466239 AD |
4417 | /* add VID to filter table */ |
4418 | igb_vfta_set(hw, vid, true); | |
4ae196df AD |
4419 | reg |= E1000_VLVF_VLANID_ENABLE; |
4420 | } | |
cad6d05f AD |
4421 | reg &= ~E1000_VLVF_VLANID_MASK; |
4422 | reg |= vid; | |
4ae196df | 4423 | wr32(E1000_VLVF(i), reg); |
ae641bdc AD |
4424 | |
4425 | /* do not modify RLPML for PF devices */ | |
4426 | if (vf >= adapter->vfs_allocated_count) | |
4427 | return 0; | |
4428 | ||
4429 | if (!adapter->vf_data[vf].vlans_enabled) { | |
4430 | u32 size; | |
4431 | reg = rd32(E1000_VMOLR(vf)); | |
4432 | size = reg & E1000_VMOLR_RLPML_MASK; | |
4433 | size += 4; | |
4434 | reg &= ~E1000_VMOLR_RLPML_MASK; | |
4435 | reg |= size; | |
4436 | wr32(E1000_VMOLR(vf), reg); | |
4437 | } | |
ae641bdc | 4438 | |
51466239 | 4439 | adapter->vf_data[vf].vlans_enabled++; |
4ae196df AD |
4440 | return 0; |
4441 | } | |
4442 | } else { | |
4443 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
4444 | /* remove vf from the pool */ | |
4445 | reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); | |
4446 | /* if pool is empty then remove entry from vfta */ | |
4447 | if (!(reg & E1000_VLVF_POOLSEL_MASK)) { | |
4448 | reg = 0; | |
4449 | igb_vfta_set(hw, vid, false); | |
4450 | } | |
4451 | wr32(E1000_VLVF(i), reg); | |
ae641bdc AD |
4452 | |
4453 | /* do not modify RLPML for PF devices */ | |
4454 | if (vf >= adapter->vfs_allocated_count) | |
4455 | return 0; | |
4456 | ||
4457 | adapter->vf_data[vf].vlans_enabled--; | |
4458 | if (!adapter->vf_data[vf].vlans_enabled) { | |
4459 | u32 size; | |
4460 | reg = rd32(E1000_VMOLR(vf)); | |
4461 | size = reg & E1000_VMOLR_RLPML_MASK; | |
4462 | size -= 4; | |
4463 | reg &= ~E1000_VMOLR_RLPML_MASK; | |
4464 | reg |= size; | |
4465 | wr32(E1000_VMOLR(vf), reg); | |
4466 | } | |
4ae196df AD |
4467 | return 0; |
4468 | } | |
4469 | } | |
4470 | return -1; | |
4471 | } | |
4472 | ||
4473 | static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) | |
4474 | { | |
4475 | int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; | |
4476 | int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); | |
4477 | ||
4478 | return igb_vlvf_set(adapter, vid, add, vf); | |
4479 | } | |
4480 | ||
f2ca0dbe | 4481 | static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) |
4ae196df | 4482 | { |
f2ca0dbe AD |
4483 | /* clear all flags */ |
4484 | adapter->vf_data[vf].flags = 0; | |
4485 | adapter->vf_data[vf].last_nack = jiffies; | |
4ae196df AD |
4486 | |
4487 | /* reset offloads to defaults */ | |
7d5753f0 | 4488 | igb_set_vmolr(adapter, vf); |
4ae196df AD |
4489 | |
4490 | /* reset vlans for device */ | |
4491 | igb_clear_vf_vfta(adapter, vf); | |
4492 | ||
4493 | /* reset multicast table array for vf */ | |
4494 | adapter->vf_data[vf].num_vf_mc_hashes = 0; | |
4495 | ||
4496 | /* Flush and reset the mta with the new values */ | |
ff41f8dc | 4497 | igb_set_rx_mode(adapter->netdev); |
4ae196df AD |
4498 | } |
4499 | ||
f2ca0dbe AD |
4500 | static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) |
4501 | { | |
4502 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | |
4503 | ||
4504 | /* generate a new mac address as we were hotplug removed/added */ | |
4505 | random_ether_addr(vf_mac); | |
4506 | ||
4507 | /* process remaining reset events */ | |
4508 | igb_vf_reset(adapter, vf); | |
4509 | } | |
4510 | ||
4511 | static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) | |
4ae196df AD |
4512 | { |
4513 | struct e1000_hw *hw = &adapter->hw; | |
4514 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | |
ff41f8dc | 4515 | int rar_entry = hw->mac.rar_entry_count - (vf + 1); |
4ae196df AD |
4516 | u32 reg, msgbuf[3]; |
4517 | u8 *addr = (u8 *)(&msgbuf[1]); | |
4518 | ||
4519 | /* process all the same items cleared in a function level reset */ | |
f2ca0dbe | 4520 | igb_vf_reset(adapter, vf); |
4ae196df AD |
4521 | |
4522 | /* set vf mac address */ | |
26ad9178 | 4523 | igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); |
4ae196df AD |
4524 | |
4525 | /* enable transmit and receive for vf */ | |
4526 | reg = rd32(E1000_VFTE); | |
4527 | wr32(E1000_VFTE, reg | (1 << vf)); | |
4528 | reg = rd32(E1000_VFRE); | |
4529 | wr32(E1000_VFRE, reg | (1 << vf)); | |
4530 | ||
f2ca0dbe | 4531 | adapter->vf_data[vf].flags = IGB_VF_FLAG_CTS; |
4ae196df AD |
4532 | |
4533 | /* reply to reset with ack and vf mac address */ | |
4534 | msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; | |
4535 | memcpy(addr, vf_mac, 6); | |
4536 | igb_write_mbx(hw, msgbuf, 3, vf); | |
4537 | } | |
4538 | ||
4539 | static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) | |
4540 | { | |
f2ca0dbe AD |
4541 | unsigned char *addr = (char *)&msg[1]; |
4542 | int err = -1; | |
4ae196df | 4543 | |
f2ca0dbe AD |
4544 | if (is_valid_ether_addr(addr)) |
4545 | err = igb_set_vf_mac(adapter, vf, addr); | |
4ae196df | 4546 | |
f2ca0dbe | 4547 | return err; |
4ae196df AD |
4548 | } |
4549 | ||
4550 | static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) | |
4551 | { | |
4552 | struct e1000_hw *hw = &adapter->hw; | |
f2ca0dbe | 4553 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
4ae196df AD |
4554 | u32 msg = E1000_VT_MSGTYPE_NACK; |
4555 | ||
4556 | /* if device isn't clear to send it shouldn't be reading either */ | |
f2ca0dbe AD |
4557 | if (!(vf_data->flags & IGB_VF_FLAG_CTS) && |
4558 | time_after(jiffies, vf_data->last_nack + (2 * HZ))) { | |
4ae196df | 4559 | igb_write_mbx(hw, &msg, 1, vf); |
f2ca0dbe | 4560 | vf_data->last_nack = jiffies; |
4ae196df AD |
4561 | } |
4562 | } | |
4563 | ||
f2ca0dbe | 4564 | static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) |
4ae196df | 4565 | { |
f2ca0dbe AD |
4566 | struct pci_dev *pdev = adapter->pdev; |
4567 | u32 msgbuf[E1000_VFMAILBOX_SIZE]; | |
4ae196df | 4568 | struct e1000_hw *hw = &adapter->hw; |
f2ca0dbe | 4569 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
4ae196df AD |
4570 | s32 retval; |
4571 | ||
f2ca0dbe | 4572 | retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); |
4ae196df AD |
4573 | |
4574 | if (retval) | |
f2ca0dbe | 4575 | dev_err(&pdev->dev, "Error receiving message from VF\n"); |
4ae196df AD |
4576 | |
4577 | /* this is a message we already processed, do nothing */ | |
4578 | if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) | |
f2ca0dbe | 4579 | return; |
4ae196df AD |
4580 | |
4581 | /* | |
4582 | * until the vf completes a reset it should not be | |
4583 | * allowed to start any configuration. | |
4584 | */ | |
4585 | ||
4586 | if (msgbuf[0] == E1000_VF_RESET) { | |
4587 | igb_vf_reset_msg(adapter, vf); | |
f2ca0dbe | 4588 | return; |
4ae196df AD |
4589 | } |
4590 | ||
f2ca0dbe AD |
4591 | if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { |
4592 | msgbuf[0] = E1000_VT_MSGTYPE_NACK; | |
4593 | if (time_after(jiffies, vf_data->last_nack + (2 * HZ))) { | |
4594 | igb_write_mbx(hw, msgbuf, 1, vf); | |
4595 | vf_data->last_nack = jiffies; | |
4596 | } | |
4597 | return; | |
4ae196df AD |
4598 | } |
4599 | ||
4600 | switch ((msgbuf[0] & 0xFFFF)) { | |
4601 | case E1000_VF_SET_MAC_ADDR: | |
4602 | retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); | |
4603 | break; | |
7d5753f0 AD |
4604 | case E1000_VF_SET_PROMISC: |
4605 | retval = igb_set_vf_promisc(adapter, msgbuf, vf); | |
4606 | break; | |
4ae196df AD |
4607 | case E1000_VF_SET_MULTICAST: |
4608 | retval = igb_set_vf_multicasts(adapter, msgbuf, vf); | |
4609 | break; | |
4610 | case E1000_VF_SET_LPE: | |
4611 | retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); | |
4612 | break; | |
4613 | case E1000_VF_SET_VLAN: | |
4614 | retval = igb_set_vf_vlan(adapter, msgbuf, vf); | |
4615 | break; | |
4616 | default: | |
090b1795 | 4617 | dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); |
4ae196df AD |
4618 | retval = -1; |
4619 | break; | |
4620 | } | |
4621 | ||
4622 | /* notify the VF of the results of what it sent us */ | |
4623 | if (retval) | |
4624 | msgbuf[0] |= E1000_VT_MSGTYPE_NACK; | |
4625 | else | |
4626 | msgbuf[0] |= E1000_VT_MSGTYPE_ACK; | |
4627 | ||
4628 | msgbuf[0] |= E1000_VT_MSGTYPE_CTS; | |
4629 | ||
4630 | igb_write_mbx(hw, msgbuf, 1, vf); | |
f2ca0dbe | 4631 | } |
4ae196df | 4632 | |
f2ca0dbe AD |
4633 | static void igb_msg_task(struct igb_adapter *adapter) |
4634 | { | |
4635 | struct e1000_hw *hw = &adapter->hw; | |
4636 | u32 vf; | |
4637 | ||
4638 | for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { | |
4639 | /* process any reset requests */ | |
4640 | if (!igb_check_for_rst(hw, vf)) | |
4641 | igb_vf_reset_event(adapter, vf); | |
4642 | ||
4643 | /* process any messages pending */ | |
4644 | if (!igb_check_for_msg(hw, vf)) | |
4645 | igb_rcv_msg_from_vf(adapter, vf); | |
4646 | ||
4647 | /* process any acks */ | |
4648 | if (!igb_check_for_ack(hw, vf)) | |
4649 | igb_rcv_ack_from_vf(adapter, vf); | |
4650 | } | |
4ae196df AD |
4651 | } |
4652 | ||
68d480c4 AD |
4653 | /** |
4654 | * igb_set_uta - Set unicast filter table address | |
4655 | * @adapter: board private structure | |
4656 | * | |
4657 | * The unicast table address is a register array of 32-bit registers. | |
4658 | * The table is meant to be used in a way similar to how the MTA is used | |
4659 | * however due to certain limitations in the hardware it is necessary to | |
4660 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscous | |
4661 | * enable bit to allow vlan tag stripping when promiscous mode is enabled | |
4662 | **/ | |
4663 | static void igb_set_uta(struct igb_adapter *adapter) | |
4664 | { | |
4665 | struct e1000_hw *hw = &adapter->hw; | |
4666 | int i; | |
4667 | ||
4668 | /* The UTA table only exists on 82576 hardware and newer */ | |
4669 | if (hw->mac.type < e1000_82576) | |
4670 | return; | |
4671 | ||
4672 | /* we only need to do this if VMDq is enabled */ | |
4673 | if (!adapter->vfs_allocated_count) | |
4674 | return; | |
4675 | ||
4676 | for (i = 0; i < hw->mac.uta_reg_count; i++) | |
4677 | array_wr32(E1000_UTA, i, ~0); | |
4678 | } | |
4679 | ||
9d5c8243 AK |
4680 | /** |
4681 | * igb_intr_msi - Interrupt Handler | |
4682 | * @irq: interrupt number | |
4683 | * @data: pointer to a network interface device structure | |
4684 | **/ | |
4685 | static irqreturn_t igb_intr_msi(int irq, void *data) | |
4686 | { | |
047e0030 AD |
4687 | struct igb_adapter *adapter = data; |
4688 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | |
9d5c8243 AK |
4689 | struct e1000_hw *hw = &adapter->hw; |
4690 | /* read ICR disables interrupts using IAM */ | |
4691 | u32 icr = rd32(E1000_ICR); | |
4692 | ||
047e0030 | 4693 | igb_write_itr(q_vector); |
9d5c8243 | 4694 | |
047e0030 | 4695 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
4696 | /* HW is reporting DMA is out of sync */ |
4697 | adapter->stats.doosync++; | |
4698 | } | |
4699 | ||
9d5c8243 AK |
4700 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
4701 | hw->mac.get_link_status = 1; | |
4702 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4703 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
4704 | } | |
4705 | ||
047e0030 | 4706 | napi_schedule(&q_vector->napi); |
9d5c8243 AK |
4707 | |
4708 | return IRQ_HANDLED; | |
4709 | } | |
4710 | ||
4711 | /** | |
4a3c6433 | 4712 | * igb_intr - Legacy Interrupt Handler |
9d5c8243 AK |
4713 | * @irq: interrupt number |
4714 | * @data: pointer to a network interface device structure | |
4715 | **/ | |
4716 | static irqreturn_t igb_intr(int irq, void *data) | |
4717 | { | |
047e0030 AD |
4718 | struct igb_adapter *adapter = data; |
4719 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | |
9d5c8243 AK |
4720 | struct e1000_hw *hw = &adapter->hw; |
4721 | /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No | |
4722 | * need for the IMC write */ | |
4723 | u32 icr = rd32(E1000_ICR); | |
9d5c8243 AK |
4724 | if (!icr) |
4725 | return IRQ_NONE; /* Not our interrupt */ | |
4726 | ||
047e0030 | 4727 | igb_write_itr(q_vector); |
9d5c8243 AK |
4728 | |
4729 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is | |
4730 | * not set, then the adapter didn't send an interrupt */ | |
4731 | if (!(icr & E1000_ICR_INT_ASSERTED)) | |
4732 | return IRQ_NONE; | |
4733 | ||
047e0030 | 4734 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
4735 | /* HW is reporting DMA is out of sync */ |
4736 | adapter->stats.doosync++; | |
4737 | } | |
4738 | ||
9d5c8243 AK |
4739 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
4740 | hw->mac.get_link_status = 1; | |
4741 | /* guard against interrupt when we're going down */ | |
4742 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4743 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
4744 | } | |
4745 | ||
047e0030 | 4746 | napi_schedule(&q_vector->napi); |
9d5c8243 AK |
4747 | |
4748 | return IRQ_HANDLED; | |
4749 | } | |
4750 | ||
047e0030 | 4751 | static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector) |
9d5c8243 | 4752 | { |
047e0030 | 4753 | struct igb_adapter *adapter = q_vector->adapter; |
46544258 | 4754 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 4755 | |
4fc82adf AD |
4756 | if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) || |
4757 | (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) { | |
047e0030 | 4758 | if (!adapter->msix_entries) |
6eb5a7f1 | 4759 | igb_set_itr(adapter); |
46544258 | 4760 | else |
047e0030 | 4761 | igb_update_ring_itr(q_vector); |
9d5c8243 AK |
4762 | } |
4763 | ||
46544258 AD |
4764 | if (!test_bit(__IGB_DOWN, &adapter->state)) { |
4765 | if (adapter->msix_entries) | |
047e0030 | 4766 | wr32(E1000_EIMS, q_vector->eims_value); |
46544258 AD |
4767 | else |
4768 | igb_irq_enable(adapter); | |
4769 | } | |
9d5c8243 AK |
4770 | } |
4771 | ||
46544258 AD |
4772 | /** |
4773 | * igb_poll - NAPI Rx polling callback | |
4774 | * @napi: napi polling structure | |
4775 | * @budget: count of how many packets we should handle | |
4776 | **/ | |
4777 | static int igb_poll(struct napi_struct *napi, int budget) | |
9d5c8243 | 4778 | { |
047e0030 AD |
4779 | struct igb_q_vector *q_vector = container_of(napi, |
4780 | struct igb_q_vector, | |
4781 | napi); | |
4782 | int tx_clean_complete = 1, work_done = 0; | |
9d5c8243 | 4783 | |
421e02f0 | 4784 | #ifdef CONFIG_IGB_DCA |
047e0030 AD |
4785 | if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) |
4786 | igb_update_dca(q_vector); | |
fe4506b6 | 4787 | #endif |
047e0030 AD |
4788 | if (q_vector->tx_ring) |
4789 | tx_clean_complete = igb_clean_tx_irq(q_vector); | |
9d5c8243 | 4790 | |
047e0030 AD |
4791 | if (q_vector->rx_ring) |
4792 | igb_clean_rx_irq_adv(q_vector, &work_done, budget); | |
4793 | ||
4794 | if (!tx_clean_complete) | |
4795 | work_done = budget; | |
46544258 | 4796 | |
9d5c8243 | 4797 | /* If not enough Rx work done, exit the polling mode */ |
5e6d5b17 | 4798 | if (work_done < budget) { |
288379f0 | 4799 | napi_complete(napi); |
047e0030 | 4800 | igb_ring_irq_enable(q_vector); |
9d5c8243 AK |
4801 | } |
4802 | ||
46544258 | 4803 | return work_done; |
9d5c8243 | 4804 | } |
6d8126f9 | 4805 | |
33af6bcc | 4806 | /** |
c5b9bd5e | 4807 | * igb_systim_to_hwtstamp - convert system time value to hw timestamp |
33af6bcc | 4808 | * @adapter: board private structure |
c5b9bd5e AD |
4809 | * @shhwtstamps: timestamp structure to update |
4810 | * @regval: unsigned 64bit system time value. | |
4811 | * | |
4812 | * We need to convert the system time value stored in the RX/TXSTMP registers | |
4813 | * into a hwtstamp which can be used by the upper level timestamping functions | |
4814 | */ | |
4815 | static void igb_systim_to_hwtstamp(struct igb_adapter *adapter, | |
4816 | struct skb_shared_hwtstamps *shhwtstamps, | |
4817 | u64 regval) | |
4818 | { | |
4819 | u64 ns; | |
4820 | ||
55cac248 AD |
4821 | /* |
4822 | * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to | |
4823 | * 24 to match clock shift we setup earlier. | |
4824 | */ | |
4825 | if (adapter->hw.mac.type == e1000_82580) | |
4826 | regval <<= IGB_82580_TSYNC_SHIFT; | |
4827 | ||
c5b9bd5e AD |
4828 | ns = timecounter_cyc2time(&adapter->clock, regval); |
4829 | timecompare_update(&adapter->compare, ns); | |
4830 | memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); | |
4831 | shhwtstamps->hwtstamp = ns_to_ktime(ns); | |
4832 | shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns); | |
4833 | } | |
4834 | ||
4835 | /** | |
4836 | * igb_tx_hwtstamp - utility function which checks for TX time stamp | |
4837 | * @q_vector: pointer to q_vector containing needed info | |
33af6bcc PO |
4838 | * @skb: packet that was just sent |
4839 | * | |
4840 | * If we were asked to do hardware stamping and such a time stamp is | |
4841 | * available, then it must have been for this skb here because we only | |
4842 | * allow only one such packet into the queue. | |
4843 | */ | |
c5b9bd5e | 4844 | static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb) |
33af6bcc | 4845 | { |
c5b9bd5e | 4846 | struct igb_adapter *adapter = q_vector->adapter; |
33af6bcc PO |
4847 | union skb_shared_tx *shtx = skb_tx(skb); |
4848 | struct e1000_hw *hw = &adapter->hw; | |
c5b9bd5e AD |
4849 | struct skb_shared_hwtstamps shhwtstamps; |
4850 | u64 regval; | |
33af6bcc | 4851 | |
c5b9bd5e AD |
4852 | /* if skb does not support hw timestamp or TX stamp not valid exit */ |
4853 | if (likely(!shtx->hardware) || | |
4854 | !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID)) | |
4855 | return; | |
4856 | ||
4857 | regval = rd32(E1000_TXSTMPL); | |
4858 | regval |= (u64)rd32(E1000_TXSTMPH) << 32; | |
4859 | ||
4860 | igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval); | |
4861 | skb_tstamp_tx(skb, &shhwtstamps); | |
33af6bcc PO |
4862 | } |
4863 | ||
9d5c8243 AK |
4864 | /** |
4865 | * igb_clean_tx_irq - Reclaim resources after transmit completes | |
047e0030 | 4866 | * @q_vector: pointer to q_vector containing needed info |
9d5c8243 AK |
4867 | * returns true if ring is completely cleaned |
4868 | **/ | |
047e0030 | 4869 | static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) |
9d5c8243 | 4870 | { |
047e0030 AD |
4871 | struct igb_adapter *adapter = q_vector->adapter; |
4872 | struct igb_ring *tx_ring = q_vector->tx_ring; | |
e694e964 | 4873 | struct net_device *netdev = tx_ring->netdev; |
0e014cb1 | 4874 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
4875 | struct igb_buffer *buffer_info; |
4876 | struct sk_buff *skb; | |
0e014cb1 | 4877 | union e1000_adv_tx_desc *tx_desc, *eop_desc; |
9d5c8243 | 4878 | unsigned int total_bytes = 0, total_packets = 0; |
0e014cb1 AD |
4879 | unsigned int i, eop, count = 0; |
4880 | bool cleaned = false; | |
9d5c8243 | 4881 | |
9d5c8243 | 4882 | i = tx_ring->next_to_clean; |
0e014cb1 AD |
4883 | eop = tx_ring->buffer_info[i].next_to_watch; |
4884 | eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop); | |
4885 | ||
4886 | while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) && | |
4887 | (count < tx_ring->count)) { | |
4888 | for (cleaned = false; !cleaned; count++) { | |
4889 | tx_desc = E1000_TX_DESC_ADV(*tx_ring, i); | |
9d5c8243 | 4890 | buffer_info = &tx_ring->buffer_info[i]; |
0e014cb1 | 4891 | cleaned = (i == eop); |
9d5c8243 AK |
4892 | skb = buffer_info->skb; |
4893 | ||
4894 | if (skb) { | |
4895 | unsigned int segs, bytecount; | |
4896 | /* gso_segs is currently only valid for tcp */ | |
4897 | segs = skb_shinfo(skb)->gso_segs ?: 1; | |
4898 | /* multiply data chunks by size of headers */ | |
4899 | bytecount = ((segs - 1) * skb_headlen(skb)) + | |
4900 | skb->len; | |
4901 | total_packets += segs; | |
4902 | total_bytes += bytecount; | |
33af6bcc | 4903 | |
c5b9bd5e | 4904 | igb_tx_hwtstamp(q_vector, skb); |
9d5c8243 AK |
4905 | } |
4906 | ||
80785298 | 4907 | igb_unmap_and_free_tx_resource(tx_ring, buffer_info); |
0e014cb1 | 4908 | tx_desc->wb.status = 0; |
9d5c8243 AK |
4909 | |
4910 | i++; | |
4911 | if (i == tx_ring->count) | |
4912 | i = 0; | |
9d5c8243 | 4913 | } |
0e014cb1 AD |
4914 | eop = tx_ring->buffer_info[i].next_to_watch; |
4915 | eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop); | |
4916 | } | |
4917 | ||
9d5c8243 AK |
4918 | tx_ring->next_to_clean = i; |
4919 | ||
fc7d345d | 4920 | if (unlikely(count && |
9d5c8243 | 4921 | netif_carrier_ok(netdev) && |
c493ea45 | 4922 | igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) { |
9d5c8243 AK |
4923 | /* Make sure that anybody stopping the queue after this |
4924 | * sees the new next_to_clean. | |
4925 | */ | |
4926 | smp_mb(); | |
661086df PWJ |
4927 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
4928 | !(test_bit(__IGB_DOWN, &adapter->state))) { | |
4929 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
04a5fcaa | 4930 | tx_ring->tx_stats.restart_queue++; |
661086df | 4931 | } |
9d5c8243 AK |
4932 | } |
4933 | ||
4934 | if (tx_ring->detect_tx_hung) { | |
4935 | /* Detect a transmit hang in hardware, this serializes the | |
4936 | * check with the clearing of time_stamp and movement of i */ | |
4937 | tx_ring->detect_tx_hung = false; | |
4938 | if (tx_ring->buffer_info[i].time_stamp && | |
4939 | time_after(jiffies, tx_ring->buffer_info[i].time_stamp + | |
4940 | (adapter->tx_timeout_factor * HZ)) | |
4941 | && !(rd32(E1000_STATUS) & | |
4942 | E1000_STATUS_TXOFF)) { | |
4943 | ||
9d5c8243 | 4944 | /* detected Tx unit hang */ |
80785298 | 4945 | dev_err(&tx_ring->pdev->dev, |
9d5c8243 | 4946 | "Detected Tx Unit Hang\n" |
2d064c06 | 4947 | " Tx Queue <%d>\n" |
9d5c8243 AK |
4948 | " TDH <%x>\n" |
4949 | " TDT <%x>\n" | |
4950 | " next_to_use <%x>\n" | |
4951 | " next_to_clean <%x>\n" | |
9d5c8243 AK |
4952 | "buffer_info[next_to_clean]\n" |
4953 | " time_stamp <%lx>\n" | |
0e014cb1 | 4954 | " next_to_watch <%x>\n" |
9d5c8243 AK |
4955 | " jiffies <%lx>\n" |
4956 | " desc.status <%x>\n", | |
2d064c06 | 4957 | tx_ring->queue_index, |
fce99e34 AD |
4958 | readl(tx_ring->head), |
4959 | readl(tx_ring->tail), | |
9d5c8243 AK |
4960 | tx_ring->next_to_use, |
4961 | tx_ring->next_to_clean, | |
f7ba205e | 4962 | tx_ring->buffer_info[eop].time_stamp, |
0e014cb1 | 4963 | eop, |
9d5c8243 | 4964 | jiffies, |
0e014cb1 | 4965 | eop_desc->wb.status); |
661086df | 4966 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
9d5c8243 AK |
4967 | } |
4968 | } | |
4969 | tx_ring->total_bytes += total_bytes; | |
4970 | tx_ring->total_packets += total_packets; | |
e21ed353 AD |
4971 | tx_ring->tx_stats.bytes += total_bytes; |
4972 | tx_ring->tx_stats.packets += total_packets; | |
0e014cb1 | 4973 | return (count < tx_ring->count); |
9d5c8243 AK |
4974 | } |
4975 | ||
9d5c8243 AK |
4976 | /** |
4977 | * igb_receive_skb - helper function to handle rx indications | |
047e0030 AD |
4978 | * @q_vector: structure containing interrupt and ring information |
4979 | * @skb: packet to send up | |
4980 | * @vlan_tag: vlan tag for packet | |
9d5c8243 | 4981 | **/ |
047e0030 AD |
4982 | static void igb_receive_skb(struct igb_q_vector *q_vector, |
4983 | struct sk_buff *skb, | |
4984 | u16 vlan_tag) | |
4985 | { | |
4986 | struct igb_adapter *adapter = q_vector->adapter; | |
4987 | ||
4988 | if (vlan_tag) | |
4989 | vlan_gro_receive(&q_vector->napi, adapter->vlgrp, | |
4990 | vlan_tag, skb); | |
182ff8df | 4991 | else |
047e0030 | 4992 | napi_gro_receive(&q_vector->napi, skb); |
9d5c8243 AK |
4993 | } |
4994 | ||
04a5fcaa | 4995 | static inline void igb_rx_checksum_adv(struct igb_ring *ring, |
9d5c8243 AK |
4996 | u32 status_err, struct sk_buff *skb) |
4997 | { | |
4998 | skb->ip_summed = CHECKSUM_NONE; | |
4999 | ||
5000 | /* Ignore Checksum bit is set or checksum is disabled through ethtool */ | |
85ad76b2 AD |
5001 | if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) || |
5002 | (status_err & E1000_RXD_STAT_IXSM)) | |
9d5c8243 | 5003 | return; |
85ad76b2 | 5004 | |
9d5c8243 AK |
5005 | /* TCP/UDP checksum error bit is set */ |
5006 | if (status_err & | |
5007 | (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) { | |
b9473560 JB |
5008 | /* |
5009 | * work around errata with sctp packets where the TCPE aka | |
5010 | * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) | |
5011 | * packets, (aka let the stack check the crc32c) | |
5012 | */ | |
85ad76b2 AD |
5013 | if ((skb->len == 60) && |
5014 | (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM)) | |
04a5fcaa | 5015 | ring->rx_stats.csum_err++; |
85ad76b2 | 5016 | |
9d5c8243 | 5017 | /* let the stack verify checksum errors */ |
9d5c8243 AK |
5018 | return; |
5019 | } | |
5020 | /* It must be a TCP or UDP packet with a valid checksum */ | |
5021 | if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) | |
5022 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
5023 | ||
85ad76b2 | 5024 | dev_dbg(&ring->pdev->dev, "cksum success: bits %08X\n", status_err); |
9d5c8243 AK |
5025 | } |
5026 | ||
c5b9bd5e AD |
5027 | static inline void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr, |
5028 | struct sk_buff *skb) | |
5029 | { | |
5030 | struct igb_adapter *adapter = q_vector->adapter; | |
5031 | struct e1000_hw *hw = &adapter->hw; | |
5032 | u64 regval; | |
5033 | ||
5034 | /* | |
5035 | * If this bit is set, then the RX registers contain the time stamp. No | |
5036 | * other packet will be time stamped until we read these registers, so | |
5037 | * read the registers to make them available again. Because only one | |
5038 | * packet can be time stamped at a time, we know that the register | |
5039 | * values must belong to this one here and therefore we don't need to | |
5040 | * compare any of the additional attributes stored for it. | |
5041 | * | |
5042 | * If nothing went wrong, then it should have a skb_shared_tx that we | |
5043 | * can turn into a skb_shared_hwtstamps. | |
5044 | */ | |
5045 | if (likely(!(staterr & E1000_RXDADV_STAT_TS))) | |
5046 | return; | |
5047 | if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) | |
5048 | return; | |
5049 | ||
5050 | regval = rd32(E1000_RXSTMPL); | |
5051 | regval |= (u64)rd32(E1000_RXSTMPH) << 32; | |
5052 | ||
5053 | igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); | |
5054 | } | |
4c844851 | 5055 | static inline u16 igb_get_hlen(struct igb_ring *rx_ring, |
2d94d8ab AD |
5056 | union e1000_adv_rx_desc *rx_desc) |
5057 | { | |
5058 | /* HW will not DMA in data larger than the given buffer, even if it | |
5059 | * parses the (NFS, of course) header to be larger. In that case, it | |
5060 | * fills the header buffer and spills the rest into the page. | |
5061 | */ | |
5062 | u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) & | |
5063 | E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT; | |
4c844851 AD |
5064 | if (hlen > rx_ring->rx_buffer_len) |
5065 | hlen = rx_ring->rx_buffer_len; | |
2d94d8ab AD |
5066 | return hlen; |
5067 | } | |
5068 | ||
047e0030 AD |
5069 | static bool igb_clean_rx_irq_adv(struct igb_q_vector *q_vector, |
5070 | int *work_done, int budget) | |
9d5c8243 | 5071 | { |
047e0030 | 5072 | struct igb_ring *rx_ring = q_vector->rx_ring; |
e694e964 | 5073 | struct net_device *netdev = rx_ring->netdev; |
80785298 | 5074 | struct pci_dev *pdev = rx_ring->pdev; |
9d5c8243 AK |
5075 | union e1000_adv_rx_desc *rx_desc , *next_rxd; |
5076 | struct igb_buffer *buffer_info , *next_buffer; | |
5077 | struct sk_buff *skb; | |
9d5c8243 AK |
5078 | bool cleaned = false; |
5079 | int cleaned_count = 0; | |
d1eff350 | 5080 | int current_node = numa_node_id(); |
9d5c8243 | 5081 | unsigned int total_bytes = 0, total_packets = 0; |
73cd78f1 | 5082 | unsigned int i; |
2d94d8ab AD |
5083 | u32 staterr; |
5084 | u16 length; | |
047e0030 | 5085 | u16 vlan_tag; |
9d5c8243 AK |
5086 | |
5087 | i = rx_ring->next_to_clean; | |
69d3ca53 | 5088 | buffer_info = &rx_ring->buffer_info[i]; |
9d5c8243 AK |
5089 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); |
5090 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
5091 | ||
5092 | while (staterr & E1000_RXD_STAT_DD) { | |
5093 | if (*work_done >= budget) | |
5094 | break; | |
5095 | (*work_done)++; | |
9d5c8243 | 5096 | |
69d3ca53 AD |
5097 | skb = buffer_info->skb; |
5098 | prefetch(skb->data - NET_IP_ALIGN); | |
5099 | buffer_info->skb = NULL; | |
5100 | ||
5101 | i++; | |
5102 | if (i == rx_ring->count) | |
5103 | i = 0; | |
42d0781a | 5104 | |
69d3ca53 AD |
5105 | next_rxd = E1000_RX_DESC_ADV(*rx_ring, i); |
5106 | prefetch(next_rxd); | |
5107 | next_buffer = &rx_ring->buffer_info[i]; | |
9d5c8243 AK |
5108 | |
5109 | length = le16_to_cpu(rx_desc->wb.upper.length); | |
5110 | cleaned = true; | |
5111 | cleaned_count++; | |
5112 | ||
2d94d8ab | 5113 | if (buffer_info->dma) { |
bf36c1a0 | 5114 | pci_unmap_single(pdev, buffer_info->dma, |
4c844851 | 5115 | rx_ring->rx_buffer_len, |
bf36c1a0 | 5116 | PCI_DMA_FROMDEVICE); |
91615f76 | 5117 | buffer_info->dma = 0; |
4c844851 | 5118 | if (rx_ring->rx_buffer_len >= IGB_RXBUFFER_1024) { |
6ec43fe6 AD |
5119 | skb_put(skb, length); |
5120 | goto send_up; | |
5121 | } | |
4c844851 | 5122 | skb_put(skb, igb_get_hlen(rx_ring, rx_desc)); |
bf36c1a0 AD |
5123 | } |
5124 | ||
5125 | if (length) { | |
9d5c8243 | 5126 | pci_unmap_page(pdev, buffer_info->page_dma, |
bf36c1a0 | 5127 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9d5c8243 | 5128 | buffer_info->page_dma = 0; |
bf36c1a0 AD |
5129 | |
5130 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++, | |
5131 | buffer_info->page, | |
5132 | buffer_info->page_offset, | |
5133 | length); | |
5134 | ||
d1eff350 AD |
5135 | if ((page_count(buffer_info->page) != 1) || |
5136 | (page_to_nid(buffer_info->page) != current_node)) | |
bf36c1a0 AD |
5137 | buffer_info->page = NULL; |
5138 | else | |
5139 | get_page(buffer_info->page); | |
9d5c8243 AK |
5140 | |
5141 | skb->len += length; | |
5142 | skb->data_len += length; | |
bf36c1a0 | 5143 | skb->truesize += length; |
9d5c8243 | 5144 | } |
9d5c8243 | 5145 | |
bf36c1a0 | 5146 | if (!(staterr & E1000_RXD_STAT_EOP)) { |
b2d56536 AD |
5147 | buffer_info->skb = next_buffer->skb; |
5148 | buffer_info->dma = next_buffer->dma; | |
5149 | next_buffer->skb = skb; | |
5150 | next_buffer->dma = 0; | |
bf36c1a0 AD |
5151 | goto next_desc; |
5152 | } | |
69d3ca53 | 5153 | send_up: |
9d5c8243 AK |
5154 | if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) { |
5155 | dev_kfree_skb_irq(skb); | |
5156 | goto next_desc; | |
5157 | } | |
9d5c8243 | 5158 | |
c5b9bd5e | 5159 | igb_rx_hwtstamp(q_vector, staterr, skb); |
9d5c8243 AK |
5160 | total_bytes += skb->len; |
5161 | total_packets++; | |
5162 | ||
85ad76b2 | 5163 | igb_rx_checksum_adv(rx_ring, staterr, skb); |
9d5c8243 AK |
5164 | |
5165 | skb->protocol = eth_type_trans(skb, netdev); | |
047e0030 AD |
5166 | skb_record_rx_queue(skb, rx_ring->queue_index); |
5167 | ||
5168 | vlan_tag = ((staterr & E1000_RXD_STAT_VP) ? | |
5169 | le16_to_cpu(rx_desc->wb.upper.vlan) : 0); | |
9d5c8243 | 5170 | |
047e0030 | 5171 | igb_receive_skb(q_vector, skb, vlan_tag); |
9d5c8243 | 5172 | |
9d5c8243 AK |
5173 | next_desc: |
5174 | rx_desc->wb.upper.status_error = 0; | |
5175 | ||
5176 | /* return some buffers to hardware, one at a time is too slow */ | |
5177 | if (cleaned_count >= IGB_RX_BUFFER_WRITE) { | |
3b644cf6 | 5178 | igb_alloc_rx_buffers_adv(rx_ring, cleaned_count); |
9d5c8243 AK |
5179 | cleaned_count = 0; |
5180 | } | |
5181 | ||
5182 | /* use prefetched values */ | |
5183 | rx_desc = next_rxd; | |
5184 | buffer_info = next_buffer; | |
9d5c8243 AK |
5185 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
5186 | } | |
bf36c1a0 | 5187 | |
9d5c8243 | 5188 | rx_ring->next_to_clean = i; |
c493ea45 | 5189 | cleaned_count = igb_desc_unused(rx_ring); |
9d5c8243 AK |
5190 | |
5191 | if (cleaned_count) | |
3b644cf6 | 5192 | igb_alloc_rx_buffers_adv(rx_ring, cleaned_count); |
9d5c8243 AK |
5193 | |
5194 | rx_ring->total_packets += total_packets; | |
5195 | rx_ring->total_bytes += total_bytes; | |
5196 | rx_ring->rx_stats.packets += total_packets; | |
5197 | rx_ring->rx_stats.bytes += total_bytes; | |
9d5c8243 AK |
5198 | return cleaned; |
5199 | } | |
5200 | ||
9d5c8243 AK |
5201 | /** |
5202 | * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split | |
5203 | * @adapter: address of board private structure | |
5204 | **/ | |
d7ee5b3a | 5205 | void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring, int cleaned_count) |
9d5c8243 | 5206 | { |
e694e964 | 5207 | struct net_device *netdev = rx_ring->netdev; |
9d5c8243 AK |
5208 | union e1000_adv_rx_desc *rx_desc; |
5209 | struct igb_buffer *buffer_info; | |
5210 | struct sk_buff *skb; | |
5211 | unsigned int i; | |
db761762 | 5212 | int bufsz; |
9d5c8243 AK |
5213 | |
5214 | i = rx_ring->next_to_use; | |
5215 | buffer_info = &rx_ring->buffer_info[i]; | |
5216 | ||
4c844851 | 5217 | bufsz = rx_ring->rx_buffer_len; |
db761762 | 5218 | |
9d5c8243 AK |
5219 | while (cleaned_count--) { |
5220 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, i); | |
5221 | ||
6ec43fe6 | 5222 | if ((bufsz < IGB_RXBUFFER_1024) && !buffer_info->page_dma) { |
9d5c8243 | 5223 | if (!buffer_info->page) { |
42d0781a | 5224 | buffer_info->page = netdev_alloc_page(netdev); |
bf36c1a0 | 5225 | if (!buffer_info->page) { |
04a5fcaa | 5226 | rx_ring->rx_stats.alloc_failed++; |
bf36c1a0 AD |
5227 | goto no_buffers; |
5228 | } | |
5229 | buffer_info->page_offset = 0; | |
5230 | } else { | |
5231 | buffer_info->page_offset ^= PAGE_SIZE / 2; | |
9d5c8243 AK |
5232 | } |
5233 | buffer_info->page_dma = | |
80785298 | 5234 | pci_map_page(rx_ring->pdev, buffer_info->page, |
bf36c1a0 AD |
5235 | buffer_info->page_offset, |
5236 | PAGE_SIZE / 2, | |
9d5c8243 | 5237 | PCI_DMA_FROMDEVICE); |
42d0781a AD |
5238 | if (pci_dma_mapping_error(rx_ring->pdev, |
5239 | buffer_info->page_dma)) { | |
5240 | buffer_info->page_dma = 0; | |
5241 | rx_ring->rx_stats.alloc_failed++; | |
5242 | goto no_buffers; | |
5243 | } | |
9d5c8243 AK |
5244 | } |
5245 | ||
42d0781a AD |
5246 | skb = buffer_info->skb; |
5247 | if (!skb) { | |
89d71a66 | 5248 | skb = netdev_alloc_skb_ip_align(netdev, bufsz); |
9d5c8243 | 5249 | if (!skb) { |
04a5fcaa | 5250 | rx_ring->rx_stats.alloc_failed++; |
9d5c8243 AK |
5251 | goto no_buffers; |
5252 | } | |
5253 | ||
9d5c8243 | 5254 | buffer_info->skb = skb; |
42d0781a AD |
5255 | } |
5256 | if (!buffer_info->dma) { | |
80785298 AD |
5257 | buffer_info->dma = pci_map_single(rx_ring->pdev, |
5258 | skb->data, | |
9d5c8243 AK |
5259 | bufsz, |
5260 | PCI_DMA_FROMDEVICE); | |
42d0781a AD |
5261 | if (pci_dma_mapping_error(rx_ring->pdev, |
5262 | buffer_info->dma)) { | |
5263 | buffer_info->dma = 0; | |
5264 | rx_ring->rx_stats.alloc_failed++; | |
5265 | goto no_buffers; | |
5266 | } | |
9d5c8243 AK |
5267 | } |
5268 | /* Refresh the desc even if buffer_addrs didn't change because | |
5269 | * each write-back erases this info. */ | |
6ec43fe6 | 5270 | if (bufsz < IGB_RXBUFFER_1024) { |
9d5c8243 AK |
5271 | rx_desc->read.pkt_addr = |
5272 | cpu_to_le64(buffer_info->page_dma); | |
5273 | rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma); | |
5274 | } else { | |
42d0781a | 5275 | rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma); |
9d5c8243 AK |
5276 | rx_desc->read.hdr_addr = 0; |
5277 | } | |
5278 | ||
5279 | i++; | |
5280 | if (i == rx_ring->count) | |
5281 | i = 0; | |
5282 | buffer_info = &rx_ring->buffer_info[i]; | |
5283 | } | |
5284 | ||
5285 | no_buffers: | |
5286 | if (rx_ring->next_to_use != i) { | |
5287 | rx_ring->next_to_use = i; | |
5288 | if (i == 0) | |
5289 | i = (rx_ring->count - 1); | |
5290 | else | |
5291 | i--; | |
5292 | ||
5293 | /* Force memory writes to complete before letting h/w | |
5294 | * know there are new descriptors to fetch. (Only | |
5295 | * applicable for weak-ordered memory model archs, | |
5296 | * such as IA-64). */ | |
5297 | wmb(); | |
fce99e34 | 5298 | writel(i, rx_ring->tail); |
9d5c8243 AK |
5299 | } |
5300 | } | |
5301 | ||
5302 | /** | |
5303 | * igb_mii_ioctl - | |
5304 | * @netdev: | |
5305 | * @ifreq: | |
5306 | * @cmd: | |
5307 | **/ | |
5308 | static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
5309 | { | |
5310 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5311 | struct mii_ioctl_data *data = if_mii(ifr); | |
5312 | ||
5313 | if (adapter->hw.phy.media_type != e1000_media_type_copper) | |
5314 | return -EOPNOTSUPP; | |
5315 | ||
5316 | switch (cmd) { | |
5317 | case SIOCGMIIPHY: | |
5318 | data->phy_id = adapter->hw.phy.addr; | |
5319 | break; | |
5320 | case SIOCGMIIREG: | |
f5f4cf08 AD |
5321 | if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, |
5322 | &data->val_out)) | |
9d5c8243 AK |
5323 | return -EIO; |
5324 | break; | |
5325 | case SIOCSMIIREG: | |
5326 | default: | |
5327 | return -EOPNOTSUPP; | |
5328 | } | |
5329 | return 0; | |
5330 | } | |
5331 | ||
c6cb090b PO |
5332 | /** |
5333 | * igb_hwtstamp_ioctl - control hardware time stamping | |
5334 | * @netdev: | |
5335 | * @ifreq: | |
5336 | * @cmd: | |
5337 | * | |
33af6bcc PO |
5338 | * Outgoing time stamping can be enabled and disabled. Play nice and |
5339 | * disable it when requested, although it shouldn't case any overhead | |
5340 | * when no packet needs it. At most one packet in the queue may be | |
5341 | * marked for time stamping, otherwise it would be impossible to tell | |
5342 | * for sure to which packet the hardware time stamp belongs. | |
5343 | * | |
5344 | * Incoming time stamping has to be configured via the hardware | |
5345 | * filters. Not all combinations are supported, in particular event | |
5346 | * type has to be specified. Matching the kind of event packet is | |
5347 | * not supported, with the exception of "all V2 events regardless of | |
5348 | * level 2 or 4". | |
5349 | * | |
c6cb090b PO |
5350 | **/ |
5351 | static int igb_hwtstamp_ioctl(struct net_device *netdev, | |
5352 | struct ifreq *ifr, int cmd) | |
5353 | { | |
33af6bcc PO |
5354 | struct igb_adapter *adapter = netdev_priv(netdev); |
5355 | struct e1000_hw *hw = &adapter->hw; | |
c6cb090b | 5356 | struct hwtstamp_config config; |
c5b9bd5e AD |
5357 | u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; |
5358 | u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
33af6bcc | 5359 | u32 tsync_rx_cfg = 0; |
c5b9bd5e AD |
5360 | bool is_l4 = false; |
5361 | bool is_l2 = false; | |
33af6bcc | 5362 | u32 regval; |
c6cb090b PO |
5363 | |
5364 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
5365 | return -EFAULT; | |
5366 | ||
5367 | /* reserved for future extensions */ | |
5368 | if (config.flags) | |
5369 | return -EINVAL; | |
5370 | ||
33af6bcc PO |
5371 | switch (config.tx_type) { |
5372 | case HWTSTAMP_TX_OFF: | |
c5b9bd5e | 5373 | tsync_tx_ctl = 0; |
33af6bcc | 5374 | case HWTSTAMP_TX_ON: |
33af6bcc PO |
5375 | break; |
5376 | default: | |
5377 | return -ERANGE; | |
5378 | } | |
5379 | ||
5380 | switch (config.rx_filter) { | |
5381 | case HWTSTAMP_FILTER_NONE: | |
c5b9bd5e | 5382 | tsync_rx_ctl = 0; |
33af6bcc PO |
5383 | break; |
5384 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
5385 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
5386 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
5387 | case HWTSTAMP_FILTER_ALL: | |
5388 | /* | |
5389 | * register TSYNCRXCFG must be set, therefore it is not | |
5390 | * possible to time stamp both Sync and Delay_Req messages | |
5391 | * => fall back to time stamping all packets | |
5392 | */ | |
c5b9bd5e | 5393 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; |
33af6bcc PO |
5394 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
5395 | break; | |
5396 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
c5b9bd5e | 5397 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; |
33af6bcc | 5398 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; |
c5b9bd5e | 5399 | is_l4 = true; |
33af6bcc PO |
5400 | break; |
5401 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
c5b9bd5e | 5402 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; |
33af6bcc | 5403 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; |
c5b9bd5e | 5404 | is_l4 = true; |
33af6bcc PO |
5405 | break; |
5406 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
5407 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
c5b9bd5e | 5408 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; |
33af6bcc | 5409 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE; |
c5b9bd5e AD |
5410 | is_l2 = true; |
5411 | is_l4 = true; | |
33af6bcc PO |
5412 | config.rx_filter = HWTSTAMP_FILTER_SOME; |
5413 | break; | |
5414 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
5415 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
c5b9bd5e | 5416 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; |
33af6bcc | 5417 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE; |
c5b9bd5e AD |
5418 | is_l2 = true; |
5419 | is_l4 = true; | |
33af6bcc PO |
5420 | config.rx_filter = HWTSTAMP_FILTER_SOME; |
5421 | break; | |
5422 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
5423 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
5424 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
c5b9bd5e | 5425 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; |
33af6bcc | 5426 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
c5b9bd5e | 5427 | is_l2 = true; |
33af6bcc PO |
5428 | break; |
5429 | default: | |
5430 | return -ERANGE; | |
5431 | } | |
5432 | ||
c5b9bd5e AD |
5433 | if (hw->mac.type == e1000_82575) { |
5434 | if (tsync_rx_ctl | tsync_tx_ctl) | |
5435 | return -EINVAL; | |
5436 | return 0; | |
5437 | } | |
5438 | ||
33af6bcc PO |
5439 | /* enable/disable TX */ |
5440 | regval = rd32(E1000_TSYNCTXCTL); | |
c5b9bd5e AD |
5441 | regval &= ~E1000_TSYNCTXCTL_ENABLED; |
5442 | regval |= tsync_tx_ctl; | |
33af6bcc PO |
5443 | wr32(E1000_TSYNCTXCTL, regval); |
5444 | ||
c5b9bd5e | 5445 | /* enable/disable RX */ |
33af6bcc | 5446 | regval = rd32(E1000_TSYNCRXCTL); |
c5b9bd5e AD |
5447 | regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); |
5448 | regval |= tsync_rx_ctl; | |
33af6bcc | 5449 | wr32(E1000_TSYNCRXCTL, regval); |
33af6bcc | 5450 | |
c5b9bd5e AD |
5451 | /* define which PTP packets are time stamped */ |
5452 | wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); | |
33af6bcc | 5453 | |
c5b9bd5e AD |
5454 | /* define ethertype filter for timestamped packets */ |
5455 | if (is_l2) | |
5456 | wr32(E1000_ETQF(3), | |
5457 | (E1000_ETQF_FILTER_ENABLE | /* enable filter */ | |
5458 | E1000_ETQF_1588 | /* enable timestamping */ | |
5459 | ETH_P_1588)); /* 1588 eth protocol type */ | |
5460 | else | |
5461 | wr32(E1000_ETQF(3), 0); | |
5462 | ||
5463 | #define PTP_PORT 319 | |
5464 | /* L4 Queue Filter[3]: filter by destination port and protocol */ | |
5465 | if (is_l4) { | |
5466 | u32 ftqf = (IPPROTO_UDP /* UDP */ | |
5467 | | E1000_FTQF_VF_BP /* VF not compared */ | |
5468 | | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ | |
5469 | | E1000_FTQF_MASK); /* mask all inputs */ | |
5470 | ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ | |
5471 | ||
5472 | wr32(E1000_IMIR(3), htons(PTP_PORT)); | |
5473 | wr32(E1000_IMIREXT(3), | |
5474 | (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); | |
5475 | if (hw->mac.type == e1000_82576) { | |
5476 | /* enable source port check */ | |
5477 | wr32(E1000_SPQF(3), htons(PTP_PORT)); | |
5478 | ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; | |
5479 | } | |
5480 | wr32(E1000_FTQF(3), ftqf); | |
5481 | } else { | |
5482 | wr32(E1000_FTQF(3), E1000_FTQF_MASK); | |
5483 | } | |
33af6bcc PO |
5484 | wrfl(); |
5485 | ||
5486 | adapter->hwtstamp_config = config; | |
5487 | ||
5488 | /* clear TX/RX time stamp registers, just to be sure */ | |
5489 | regval = rd32(E1000_TXSTMPH); | |
5490 | regval = rd32(E1000_RXSTMPH); | |
c6cb090b | 5491 | |
33af6bcc PO |
5492 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? |
5493 | -EFAULT : 0; | |
c6cb090b PO |
5494 | } |
5495 | ||
9d5c8243 AK |
5496 | /** |
5497 | * igb_ioctl - | |
5498 | * @netdev: | |
5499 | * @ifreq: | |
5500 | * @cmd: | |
5501 | **/ | |
5502 | static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
5503 | { | |
5504 | switch (cmd) { | |
5505 | case SIOCGMIIPHY: | |
5506 | case SIOCGMIIREG: | |
5507 | case SIOCSMIIREG: | |
5508 | return igb_mii_ioctl(netdev, ifr, cmd); | |
c6cb090b PO |
5509 | case SIOCSHWTSTAMP: |
5510 | return igb_hwtstamp_ioctl(netdev, ifr, cmd); | |
9d5c8243 AK |
5511 | default: |
5512 | return -EOPNOTSUPP; | |
5513 | } | |
5514 | } | |
5515 | ||
009bc06e AD |
5516 | s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) |
5517 | { | |
5518 | struct igb_adapter *adapter = hw->back; | |
5519 | u16 cap_offset; | |
5520 | ||
5521 | cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); | |
5522 | if (!cap_offset) | |
5523 | return -E1000_ERR_CONFIG; | |
5524 | ||
5525 | pci_read_config_word(adapter->pdev, cap_offset + reg, value); | |
5526 | ||
5527 | return 0; | |
5528 | } | |
5529 | ||
5530 | s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) | |
5531 | { | |
5532 | struct igb_adapter *adapter = hw->back; | |
5533 | u16 cap_offset; | |
5534 | ||
5535 | cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); | |
5536 | if (!cap_offset) | |
5537 | return -E1000_ERR_CONFIG; | |
5538 | ||
5539 | pci_write_config_word(adapter->pdev, cap_offset + reg, *value); | |
5540 | ||
5541 | return 0; | |
5542 | } | |
5543 | ||
9d5c8243 AK |
5544 | static void igb_vlan_rx_register(struct net_device *netdev, |
5545 | struct vlan_group *grp) | |
5546 | { | |
5547 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5548 | struct e1000_hw *hw = &adapter->hw; | |
5549 | u32 ctrl, rctl; | |
5550 | ||
5551 | igb_irq_disable(adapter); | |
5552 | adapter->vlgrp = grp; | |
5553 | ||
5554 | if (grp) { | |
5555 | /* enable VLAN tag insert/strip */ | |
5556 | ctrl = rd32(E1000_CTRL); | |
5557 | ctrl |= E1000_CTRL_VME; | |
5558 | wr32(E1000_CTRL, ctrl); | |
5559 | ||
51466239 | 5560 | /* Disable CFI check */ |
9d5c8243 | 5561 | rctl = rd32(E1000_RCTL); |
9d5c8243 AK |
5562 | rctl &= ~E1000_RCTL_CFIEN; |
5563 | wr32(E1000_RCTL, rctl); | |
9d5c8243 AK |
5564 | } else { |
5565 | /* disable VLAN tag insert/strip */ | |
5566 | ctrl = rd32(E1000_CTRL); | |
5567 | ctrl &= ~E1000_CTRL_VME; | |
5568 | wr32(E1000_CTRL, ctrl); | |
9d5c8243 AK |
5569 | } |
5570 | ||
e1739522 AD |
5571 | igb_rlpml_set(adapter); |
5572 | ||
9d5c8243 AK |
5573 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
5574 | igb_irq_enable(adapter); | |
5575 | } | |
5576 | ||
5577 | static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid) | |
5578 | { | |
5579 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5580 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 5581 | int pf_id = adapter->vfs_allocated_count; |
9d5c8243 | 5582 | |
51466239 AD |
5583 | /* attempt to add filter to vlvf array */ |
5584 | igb_vlvf_set(adapter, vid, true, pf_id); | |
4ae196df | 5585 | |
51466239 AD |
5586 | /* add the filter since PF can receive vlans w/o entry in vlvf */ |
5587 | igb_vfta_set(hw, vid, true); | |
9d5c8243 AK |
5588 | } |
5589 | ||
5590 | static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
5591 | { | |
5592 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5593 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 5594 | int pf_id = adapter->vfs_allocated_count; |
51466239 | 5595 | s32 err; |
9d5c8243 AK |
5596 | |
5597 | igb_irq_disable(adapter); | |
5598 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
5599 | ||
5600 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5601 | igb_irq_enable(adapter); | |
5602 | ||
51466239 AD |
5603 | /* remove vlan from VLVF table array */ |
5604 | err = igb_vlvf_set(adapter, vid, false, pf_id); | |
9d5c8243 | 5605 | |
51466239 AD |
5606 | /* if vid was not present in VLVF just remove it from table */ |
5607 | if (err) | |
4ae196df | 5608 | igb_vfta_set(hw, vid, false); |
9d5c8243 AK |
5609 | } |
5610 | ||
5611 | static void igb_restore_vlan(struct igb_adapter *adapter) | |
5612 | { | |
5613 | igb_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
5614 | ||
5615 | if (adapter->vlgrp) { | |
5616 | u16 vid; | |
5617 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
5618 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
5619 | continue; | |
5620 | igb_vlan_rx_add_vid(adapter->netdev, vid); | |
5621 | } | |
5622 | } | |
5623 | } | |
5624 | ||
5625 | int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx) | |
5626 | { | |
090b1795 | 5627 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
5628 | struct e1000_mac_info *mac = &adapter->hw.mac; |
5629 | ||
5630 | mac->autoneg = 0; | |
5631 | ||
9d5c8243 AK |
5632 | switch (spddplx) { |
5633 | case SPEED_10 + DUPLEX_HALF: | |
5634 | mac->forced_speed_duplex = ADVERTISE_10_HALF; | |
5635 | break; | |
5636 | case SPEED_10 + DUPLEX_FULL: | |
5637 | mac->forced_speed_duplex = ADVERTISE_10_FULL; | |
5638 | break; | |
5639 | case SPEED_100 + DUPLEX_HALF: | |
5640 | mac->forced_speed_duplex = ADVERTISE_100_HALF; | |
5641 | break; | |
5642 | case SPEED_100 + DUPLEX_FULL: | |
5643 | mac->forced_speed_duplex = ADVERTISE_100_FULL; | |
5644 | break; | |
5645 | case SPEED_1000 + DUPLEX_FULL: | |
5646 | mac->autoneg = 1; | |
5647 | adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; | |
5648 | break; | |
5649 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ | |
5650 | default: | |
090b1795 | 5651 | dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); |
9d5c8243 AK |
5652 | return -EINVAL; |
5653 | } | |
5654 | return 0; | |
5655 | } | |
5656 | ||
3fe7c4c9 | 5657 | static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake) |
9d5c8243 AK |
5658 | { |
5659 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5660 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5661 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 | 5662 | u32 ctrl, rctl, status; |
9d5c8243 AK |
5663 | u32 wufc = adapter->wol; |
5664 | #ifdef CONFIG_PM | |
5665 | int retval = 0; | |
5666 | #endif | |
5667 | ||
5668 | netif_device_detach(netdev); | |
5669 | ||
a88f10ec AD |
5670 | if (netif_running(netdev)) |
5671 | igb_close(netdev); | |
5672 | ||
047e0030 | 5673 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 AK |
5674 | |
5675 | #ifdef CONFIG_PM | |
5676 | retval = pci_save_state(pdev); | |
5677 | if (retval) | |
5678 | return retval; | |
5679 | #endif | |
5680 | ||
5681 | status = rd32(E1000_STATUS); | |
5682 | if (status & E1000_STATUS_LU) | |
5683 | wufc &= ~E1000_WUFC_LNKC; | |
5684 | ||
5685 | if (wufc) { | |
5686 | igb_setup_rctl(adapter); | |
ff41f8dc | 5687 | igb_set_rx_mode(netdev); |
9d5c8243 AK |
5688 | |
5689 | /* turn on all-multi mode if wake on multicast is enabled */ | |
5690 | if (wufc & E1000_WUFC_MC) { | |
5691 | rctl = rd32(E1000_RCTL); | |
5692 | rctl |= E1000_RCTL_MPE; | |
5693 | wr32(E1000_RCTL, rctl); | |
5694 | } | |
5695 | ||
5696 | ctrl = rd32(E1000_CTRL); | |
5697 | /* advertise wake from D3Cold */ | |
5698 | #define E1000_CTRL_ADVD3WUC 0x00100000 | |
5699 | /* phy power management enable */ | |
5700 | #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 | |
5701 | ctrl |= E1000_CTRL_ADVD3WUC; | |
5702 | wr32(E1000_CTRL, ctrl); | |
5703 | ||
9d5c8243 | 5704 | /* Allow time for pending master requests to run */ |
330a6d6a | 5705 | igb_disable_pcie_master(hw); |
9d5c8243 AK |
5706 | |
5707 | wr32(E1000_WUC, E1000_WUC_PME_EN); | |
5708 | wr32(E1000_WUFC, wufc); | |
9d5c8243 AK |
5709 | } else { |
5710 | wr32(E1000_WUC, 0); | |
5711 | wr32(E1000_WUFC, 0); | |
9d5c8243 AK |
5712 | } |
5713 | ||
3fe7c4c9 RW |
5714 | *enable_wake = wufc || adapter->en_mng_pt; |
5715 | if (!*enable_wake) | |
2fb02a26 | 5716 | igb_shutdown_serdes_link_82575(hw); |
9d5c8243 AK |
5717 | |
5718 | /* Release control of h/w to f/w. If f/w is AMT enabled, this | |
5719 | * would have already happened in close and is redundant. */ | |
5720 | igb_release_hw_control(adapter); | |
5721 | ||
5722 | pci_disable_device(pdev); | |
5723 | ||
9d5c8243 AK |
5724 | return 0; |
5725 | } | |
5726 | ||
5727 | #ifdef CONFIG_PM | |
3fe7c4c9 RW |
5728 | static int igb_suspend(struct pci_dev *pdev, pm_message_t state) |
5729 | { | |
5730 | int retval; | |
5731 | bool wake; | |
5732 | ||
5733 | retval = __igb_shutdown(pdev, &wake); | |
5734 | if (retval) | |
5735 | return retval; | |
5736 | ||
5737 | if (wake) { | |
5738 | pci_prepare_to_sleep(pdev); | |
5739 | } else { | |
5740 | pci_wake_from_d3(pdev, false); | |
5741 | pci_set_power_state(pdev, PCI_D3hot); | |
5742 | } | |
5743 | ||
5744 | return 0; | |
5745 | } | |
5746 | ||
9d5c8243 AK |
5747 | static int igb_resume(struct pci_dev *pdev) |
5748 | { | |
5749 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5750 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5751 | struct e1000_hw *hw = &adapter->hw; | |
5752 | u32 err; | |
5753 | ||
5754 | pci_set_power_state(pdev, PCI_D0); | |
5755 | pci_restore_state(pdev); | |
42bfd33a | 5756 | |
aed5dec3 | 5757 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
5758 | if (err) { |
5759 | dev_err(&pdev->dev, | |
5760 | "igb: Cannot enable PCI device from suspend\n"); | |
5761 | return err; | |
5762 | } | |
5763 | pci_set_master(pdev); | |
5764 | ||
5765 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
5766 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
5767 | ||
047e0030 | 5768 | if (igb_init_interrupt_scheme(adapter)) { |
a88f10ec AD |
5769 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
5770 | return -ENOMEM; | |
9d5c8243 AK |
5771 | } |
5772 | ||
5773 | /* e1000_power_up_phy(adapter); */ | |
5774 | ||
5775 | igb_reset(adapter); | |
a8564f03 AD |
5776 | |
5777 | /* let the f/w know that the h/w is now under the control of the | |
5778 | * driver. */ | |
5779 | igb_get_hw_control(adapter); | |
5780 | ||
9d5c8243 AK |
5781 | wr32(E1000_WUS, ~0); |
5782 | ||
a88f10ec AD |
5783 | if (netif_running(netdev)) { |
5784 | err = igb_open(netdev); | |
5785 | if (err) | |
5786 | return err; | |
5787 | } | |
9d5c8243 AK |
5788 | |
5789 | netif_device_attach(netdev); | |
5790 | ||
9d5c8243 AK |
5791 | return 0; |
5792 | } | |
5793 | #endif | |
5794 | ||
5795 | static void igb_shutdown(struct pci_dev *pdev) | |
5796 | { | |
3fe7c4c9 RW |
5797 | bool wake; |
5798 | ||
5799 | __igb_shutdown(pdev, &wake); | |
5800 | ||
5801 | if (system_state == SYSTEM_POWER_OFF) { | |
5802 | pci_wake_from_d3(pdev, wake); | |
5803 | pci_set_power_state(pdev, PCI_D3hot); | |
5804 | } | |
9d5c8243 AK |
5805 | } |
5806 | ||
5807 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
5808 | /* | |
5809 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
5810 | * without having to re-enable interrupts. It's not called while | |
5811 | * the interrupt routine is executing. | |
5812 | */ | |
5813 | static void igb_netpoll(struct net_device *netdev) | |
5814 | { | |
5815 | struct igb_adapter *adapter = netdev_priv(netdev); | |
eebbbdba | 5816 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 5817 | int i; |
9d5c8243 | 5818 | |
eebbbdba | 5819 | if (!adapter->msix_entries) { |
047e0030 | 5820 | struct igb_q_vector *q_vector = adapter->q_vector[0]; |
eebbbdba | 5821 | igb_irq_disable(adapter); |
047e0030 | 5822 | napi_schedule(&q_vector->napi); |
eebbbdba AD |
5823 | return; |
5824 | } | |
9d5c8243 | 5825 | |
047e0030 AD |
5826 | for (i = 0; i < adapter->num_q_vectors; i++) { |
5827 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
5828 | wr32(E1000_EIMC, q_vector->eims_value); | |
5829 | napi_schedule(&q_vector->napi); | |
eebbbdba | 5830 | } |
9d5c8243 AK |
5831 | } |
5832 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
5833 | ||
5834 | /** | |
5835 | * igb_io_error_detected - called when PCI error is detected | |
5836 | * @pdev: Pointer to PCI device | |
5837 | * @state: The current pci connection state | |
5838 | * | |
5839 | * This function is called after a PCI bus error affecting | |
5840 | * this device has been detected. | |
5841 | */ | |
5842 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, | |
5843 | pci_channel_state_t state) | |
5844 | { | |
5845 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5846 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5847 | ||
5848 | netif_device_detach(netdev); | |
5849 | ||
59ed6eec AD |
5850 | if (state == pci_channel_io_perm_failure) |
5851 | return PCI_ERS_RESULT_DISCONNECT; | |
5852 | ||
9d5c8243 AK |
5853 | if (netif_running(netdev)) |
5854 | igb_down(adapter); | |
5855 | pci_disable_device(pdev); | |
5856 | ||
5857 | /* Request a slot slot reset. */ | |
5858 | return PCI_ERS_RESULT_NEED_RESET; | |
5859 | } | |
5860 | ||
5861 | /** | |
5862 | * igb_io_slot_reset - called after the pci bus has been reset. | |
5863 | * @pdev: Pointer to PCI device | |
5864 | * | |
5865 | * Restart the card from scratch, as if from a cold-boot. Implementation | |
5866 | * resembles the first-half of the igb_resume routine. | |
5867 | */ | |
5868 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) | |
5869 | { | |
5870 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5871 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5872 | struct e1000_hw *hw = &adapter->hw; | |
40a914fa | 5873 | pci_ers_result_t result; |
42bfd33a | 5874 | int err; |
9d5c8243 | 5875 | |
aed5dec3 | 5876 | if (pci_enable_device_mem(pdev)) { |
9d5c8243 AK |
5877 | dev_err(&pdev->dev, |
5878 | "Cannot re-enable PCI device after reset.\n"); | |
40a914fa AD |
5879 | result = PCI_ERS_RESULT_DISCONNECT; |
5880 | } else { | |
5881 | pci_set_master(pdev); | |
5882 | pci_restore_state(pdev); | |
9d5c8243 | 5883 | |
40a914fa AD |
5884 | pci_enable_wake(pdev, PCI_D3hot, 0); |
5885 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9d5c8243 | 5886 | |
40a914fa AD |
5887 | igb_reset(adapter); |
5888 | wr32(E1000_WUS, ~0); | |
5889 | result = PCI_ERS_RESULT_RECOVERED; | |
5890 | } | |
9d5c8243 | 5891 | |
ea943d41 JK |
5892 | err = pci_cleanup_aer_uncorrect_error_status(pdev); |
5893 | if (err) { | |
5894 | dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status " | |
5895 | "failed 0x%0x\n", err); | |
5896 | /* non-fatal, continue */ | |
5897 | } | |
40a914fa AD |
5898 | |
5899 | return result; | |
9d5c8243 AK |
5900 | } |
5901 | ||
5902 | /** | |
5903 | * igb_io_resume - called when traffic can start flowing again. | |
5904 | * @pdev: Pointer to PCI device | |
5905 | * | |
5906 | * This callback is called when the error recovery driver tells us that | |
5907 | * its OK to resume normal operation. Implementation resembles the | |
5908 | * second-half of the igb_resume routine. | |
5909 | */ | |
5910 | static void igb_io_resume(struct pci_dev *pdev) | |
5911 | { | |
5912 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5913 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5914 | ||
9d5c8243 AK |
5915 | if (netif_running(netdev)) { |
5916 | if (igb_up(adapter)) { | |
5917 | dev_err(&pdev->dev, "igb_up failed after reset\n"); | |
5918 | return; | |
5919 | } | |
5920 | } | |
5921 | ||
5922 | netif_device_attach(netdev); | |
5923 | ||
5924 | /* let the f/w know that the h/w is now under the control of the | |
5925 | * driver. */ | |
5926 | igb_get_hw_control(adapter); | |
9d5c8243 AK |
5927 | } |
5928 | ||
26ad9178 AD |
5929 | static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, |
5930 | u8 qsel) | |
5931 | { | |
5932 | u32 rar_low, rar_high; | |
5933 | struct e1000_hw *hw = &adapter->hw; | |
5934 | ||
5935 | /* HW expects these in little endian so we reverse the byte order | |
5936 | * from network order (big endian) to little endian | |
5937 | */ | |
5938 | rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | | |
5939 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); | |
5940 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); | |
5941 | ||
5942 | /* Indicate to hardware the Address is Valid. */ | |
5943 | rar_high |= E1000_RAH_AV; | |
5944 | ||
5945 | if (hw->mac.type == e1000_82575) | |
5946 | rar_high |= E1000_RAH_POOL_1 * qsel; | |
5947 | else | |
5948 | rar_high |= E1000_RAH_POOL_1 << qsel; | |
5949 | ||
5950 | wr32(E1000_RAL(index), rar_low); | |
5951 | wrfl(); | |
5952 | wr32(E1000_RAH(index), rar_high); | |
5953 | wrfl(); | |
5954 | } | |
5955 | ||
4ae196df AD |
5956 | static int igb_set_vf_mac(struct igb_adapter *adapter, |
5957 | int vf, unsigned char *mac_addr) | |
5958 | { | |
5959 | struct e1000_hw *hw = &adapter->hw; | |
ff41f8dc AD |
5960 | /* VF MAC addresses start at end of receive addresses and moves |
5961 | * torwards the first, as a result a collision should not be possible */ | |
5962 | int rar_entry = hw->mac.rar_entry_count - (vf + 1); | |
4ae196df | 5963 | |
37680117 | 5964 | memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); |
4ae196df | 5965 | |
26ad9178 | 5966 | igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); |
4ae196df AD |
5967 | |
5968 | return 0; | |
5969 | } | |
5970 | ||
5971 | static void igb_vmm_control(struct igb_adapter *adapter) | |
5972 | { | |
5973 | struct e1000_hw *hw = &adapter->hw; | |
10d8e907 | 5974 | u32 reg; |
4ae196df | 5975 | |
d4960307 AD |
5976 | /* replication is not supported for 82575 */ |
5977 | if (hw->mac.type == e1000_82575) | |
4ae196df AD |
5978 | return; |
5979 | ||
10d8e907 AD |
5980 | /* enable replication vlan tag stripping */ |
5981 | reg = rd32(E1000_RPLOLR); | |
5982 | reg |= E1000_RPLOLR_STRVLAN; | |
5983 | wr32(E1000_RPLOLR, reg); | |
5984 | ||
5985 | /* notify HW that the MAC is adding vlan tags */ | |
5986 | reg = rd32(E1000_DTXCTL); | |
5987 | reg |= E1000_DTXCTL_VLAN_ADDED; | |
5988 | wr32(E1000_DTXCTL, reg); | |
5989 | ||
d4960307 AD |
5990 | if (adapter->vfs_allocated_count) { |
5991 | igb_vmdq_set_loopback_pf(hw, true); | |
5992 | igb_vmdq_set_replication_pf(hw, true); | |
5993 | } else { | |
5994 | igb_vmdq_set_loopback_pf(hw, false); | |
5995 | igb_vmdq_set_replication_pf(hw, false); | |
5996 | } | |
4ae196df AD |
5997 | } |
5998 | ||
9d5c8243 | 5999 | /* igb_main.c */ |