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igb: add support for another dual port 82576 non-security nic
[linux-2.6-block.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
2d064c06
AD		 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
71 /* required last entry */
72 {0, }
73};
74
75MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
76
77void igb_reset(struct igb_adapter *);
78static int igb_setup_all_tx_resources(struct igb_adapter *);
79static int igb_setup_all_rx_resources(struct igb_adapter *);
80static void igb_free_all_tx_resources(struct igb_adapter *);
81static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 82void igb_update_stats(struct igb_adapter *);
83static int igb_probe(struct pci_dev *, const struct pci_device_id *);
84static void __devexit igb_remove(struct pci_dev *pdev);
85static int igb_sw_init(struct igb_adapter *);
86static int igb_open(struct net_device *);
87static int igb_close(struct net_device *);
88static void igb_configure_tx(struct igb_adapter *);
89static void igb_configure_rx(struct igb_adapter *);
90static void igb_setup_rctl(struct igb_adapter *);
91static void igb_clean_all_tx_rings(struct igb_adapter *);
92static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 93static void igb_clean_tx_ring(struct igb_ring *);
94static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 95static void igb_set_multi(struct net_device *);
96static void igb_update_phy_info(unsigned long);
97static void igb_watchdog(unsigned long);
98static void igb_watchdog_task(struct work_struct *);
99static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
100 struct igb_ring *);
101static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
102static struct net_device_stats *igb_get_stats(struct net_device *);
103static int igb_change_mtu(struct net_device *, int);
104static int igb_set_mac(struct net_device *, void *);
105static irqreturn_t igb_intr(int irq, void *);
106static irqreturn_t igb_intr_msi(int irq, void *);
107static irqreturn_t igb_msix_other(int irq, void *);
108static irqreturn_t igb_msix_rx(int irq, void *);
109static irqreturn_t igb_msix_tx(int irq, void *);
421e02f0 110#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 111static void igb_update_rx_dca(struct igb_ring *);
112static void igb_update_tx_dca(struct igb_ring *);
113static void igb_setup_dca(struct igb_adapter *);
421e02f0 114#endif /* CONFIG_IGB_DCA */
3b644cf6 115static bool igb_clean_tx_irq(struct igb_ring *);
661086df 116static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 117static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
118static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 119static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
120static void igb_tx_timeout(struct net_device *);
121static void igb_reset_task(struct work_struct *);
122static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
123static void igb_vlan_rx_add_vid(struct net_device *, u16);
124static void igb_vlan_rx_kill_vid(struct net_device *, u16);
125static void igb_restore_vlan(struct igb_adapter *);
4ae196df
AD		 126static void igb_ping_all_vfs(struct igb_adapter *);
127static void igb_msg_task(struct igb_adapter *);
128static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
e1739522
AD		 129static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
130static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
4ae196df 131static void igb_vmm_control(struct igb_adapter *);
e1739522 132static inline void igb_set_vmolr(struct e1000_hw *, int);
4ae196df
AD		 133static inline int igb_set_vf_rlpml(struct igb_adapter *, int, int);
134static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
135static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
9d5c8243
AK		 136
137static int igb_suspend(struct pci_dev *, pm_message_t);
138#ifdef CONFIG_PM
139static int igb_resume(struct pci_dev *);
140#endif
141static void igb_shutdown(struct pci_dev *);
421e02f0 142#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 143static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
144static struct notifier_block dca_notifier = {
145 .notifier_call = igb_notify_dca,
146 .next = NULL,
147 .priority = 0
148};
149#endif
9d5c8243
AK		 150#ifdef CONFIG_NET_POLL_CONTROLLER
151/* for netdump / net console */
152static void igb_netpoll(struct net_device *);
153#endif
154
37680117
AD		 155#ifdef CONFIG_PCI_IOV
156static ssize_t igb_set_num_vfs(struct device *, struct device_attribute *,
157 const char *, size_t);
158static ssize_t igb_show_num_vfs(struct device *, struct device_attribute *,
159 char *);
160DEVICE_ATTR(num_vfs, S_IRUGO | S_IWUSR, igb_show_num_vfs, igb_set_num_vfs);
161#endif
9d5c8243
AK		 162static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
163 pci_channel_state_t);
164static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
165static void igb_io_resume(struct pci_dev *);
166
167static struct pci_error_handlers igb_err_handler = {
168 .error_detected = igb_io_error_detected,
169 .slot_reset = igb_io_slot_reset,
170 .resume = igb_io_resume,
171};
172
173
174static struct pci_driver igb_driver = {
175 .name = igb_driver_name,
176 .id_table = igb_pci_tbl,
177 .probe = igb_probe,
178 .remove = __devexit_p(igb_remove),
179#ifdef CONFIG_PM
180 /* Power Managment Hooks */
181 .suspend = igb_suspend,
182 .resume = igb_resume,
183#endif
184 .shutdown = igb_shutdown,
185 .err_handler = &igb_err_handler
186};
187
7dfc16fa
AD		 188static int global_quad_port_a; /* global quad port a indication */
189
9d5c8243
AK		 190MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
191MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
192MODULE_LICENSE("GPL");
193MODULE_VERSION(DRV_VERSION);
194
38c845c7
PO		 195/**
196 * Scale the NIC clock cycle by a large factor so that
197 * relatively small clock corrections can be added or
198 * substracted at each clock tick. The drawbacks of a
199 * large factor are a) that the clock register overflows
200 * more quickly (not such a big deal) and b) that the
201 * increment per tick has to fit into 24 bits.
202 *
203 * Note that
204 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
205 * IGB_TSYNC_SCALE
206 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
207 *
208 * The base scale factor is intentionally a power of two
209 * so that the division in %struct timecounter can be done with
210 * a shift.
211 */
212#define IGB_TSYNC_SHIFT (19)
213#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
214
215/**
216 * The duration of one clock cycle of the NIC.
217 *
218 * @todo This hard-coded value is part of the specification and might change
219 * in future hardware revisions. Add revision check.
220 */
221#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
222
223#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
224# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
225#endif
226
227/**
228 * igb_read_clock - read raw cycle counter (to be used by time counter)
229 */
230static cycle_t igb_read_clock(const struct cyclecounter *tc)
231{
232 struct igb_adapter *adapter =
233 container_of(tc, struct igb_adapter, cycles);
234 struct e1000_hw *hw = &adapter->hw;
235 u64 stamp;
236
237 stamp = rd32(E1000_SYSTIML);
238 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
239
240 return stamp;
241}
242
9d5c8243
AK		 243#ifdef DEBUG
244/**
245 * igb_get_hw_dev_name - return device name string
246 * used by hardware layer to print debugging information
247 **/
248char *igb_get_hw_dev_name(struct e1000_hw *hw)
249{
250 struct igb_adapter *adapter = hw->back;
251 return adapter->netdev->name;
252}
38c845c7
PO		 253
254/**
255 * igb_get_time_str - format current NIC and system time as string
256 */
257static char *igb_get_time_str(struct igb_adapter *adapter,
258 char buffer[160])
259{
260 cycle_t hw = adapter->cycles.read(&adapter->cycles);
261 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
262 struct timespec sys;
263 struct timespec delta;
264 getnstimeofday(&sys);
265
266 delta = timespec_sub(nic, sys);
267
268 sprintf(buffer,
33af6bcc
PO		 269 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
270 hw,
38c845c7
PO		 271 (long)nic.tv_sec, nic.tv_nsec,
272 (long)sys.tv_sec, sys.tv_nsec,
273 (long)delta.tv_sec, delta.tv_nsec);
274
275 return buffer;
276}
9d5c8243
AK		 277#endif
278
279/**
280 * igb_init_module - Driver Registration Routine
281 *
282 * igb_init_module is the first routine called when the driver is
283 * loaded. All it does is register with the PCI subsystem.
284 **/
285static int __init igb_init_module(void)
286{
287 int ret;
288 printk(KERN_INFO "%s - version %s\n",
289 igb_driver_string, igb_driver_version);
290
291 printk(KERN_INFO "%s\n", igb_copyright);
292
7dfc16fa
AD		 293 global_quad_port_a = 0;
294
421e02f0 295#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 296 dca_register_notify(&dca_notifier);
297#endif
bbd98fe4
AD		 298
299 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 300 return ret;
301}
302
303module_init(igb_init_module);
304
305/**
306 * igb_exit_module - Driver Exit Cleanup Routine
307 *
308 * igb_exit_module is called just before the driver is removed
309 * from memory.
310 **/
311static void __exit igb_exit_module(void)
312{
421e02f0 313#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 314 dca_unregister_notify(&dca_notifier);
315#endif
9d5c8243
AK		 316 pci_unregister_driver(&igb_driver);
317}
318
319module_exit(igb_exit_module);
320
26bc19ec
AD		 321#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
322/**
323 * igb_cache_ring_register - Descriptor ring to register mapping
324 * @adapter: board private structure to initialize
325 *
326 * Once we know the feature-set enabled for the device, we'll cache
327 * the register offset the descriptor ring is assigned to.
328 **/
329static void igb_cache_ring_register(struct igb_adapter *adapter)
330{
331 int i;
1bfaf07b 332 unsigned int rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 333
334 switch (adapter->hw.mac.type) {
335 case e1000_82576:
336 /* The queues are allocated for virtualization such that VF 0
337 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
338 * In order to avoid collision we start at the first free queue
339 * and continue consuming queues in the same sequence
340 */
341 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 342 adapter->rx_ring[i].reg_idx = rbase_offset +
343 Q_IDX_82576(i);
26bc19ec 344 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 345 adapter->tx_ring[i].reg_idx = rbase_offset +
346 Q_IDX_82576(i);
26bc19ec
AD		 347 break;
348 case e1000_82575:
349 default:
350 for (i = 0; i < adapter->num_rx_queues; i++)
351 adapter->rx_ring[i].reg_idx = i;
352 for (i = 0; i < adapter->num_tx_queues; i++)
353 adapter->tx_ring[i].reg_idx = i;
354 break;
355 }
356}
357
9d5c8243
AK		 358/**
359 * igb_alloc_queues - Allocate memory for all rings
360 * @adapter: board private structure to initialize
361 *
362 * We allocate one ring per queue at run-time since we don't know the
363 * number of queues at compile-time.
364 **/
365static int igb_alloc_queues(struct igb_adapter *adapter)
366{
367 int i;
368
369 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
370 sizeof(struct igb_ring), GFP_KERNEL);
371 if (!adapter->tx_ring)
372 return -ENOMEM;
373
374 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
375 sizeof(struct igb_ring), GFP_KERNEL);
376 if (!adapter->rx_ring) {
377 kfree(adapter->tx_ring);
378 return -ENOMEM;
379 }
380
6eb5a7f1
AD		 381 adapter->rx_ring->buddy = adapter->tx_ring;
382
661086df
PWJ		 383 for (i = 0; i < adapter->num_tx_queues; i++) {
384 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 385 ring->count = adapter->tx_ring_count;
661086df
PWJ		 386 ring->adapter = adapter;
387 ring->queue_index = i;
388 }
9d5c8243
AK		 389 for (i = 0; i < adapter->num_rx_queues; i++) {
390 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 391 ring->count = adapter->rx_ring_count;
9d5c8243 392 ring->adapter = adapter;
844290e5 393 ring->queue_index = i;
9d5c8243
AK		 394 ring->itr_register = E1000_ITR;
395
844290e5 396 /* set a default napi handler for each rx_ring */
661086df 397 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 398 }
26bc19ec
AD		 399
400 igb_cache_ring_register(adapter);
9d5c8243
AK		 401 return 0;
402}
403
a88f10ec
AD		 404static void igb_free_queues(struct igb_adapter *adapter)
405{
406 int i;
407
408 for (i = 0; i < adapter->num_rx_queues; i++)
409 netif_napi_del(&adapter->rx_ring[i].napi);
410
411 kfree(adapter->tx_ring);
412 kfree(adapter->rx_ring);
413}
414
9d5c8243
AK		 415#define IGB_N0_QUEUE -1
416static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
417 int tx_queue, int msix_vector)
418{
419 u32 msixbm = 0;
420 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 421 u32 ivar, index;
422
423 switch (hw->mac.type) {
424 case e1000_82575:
9d5c8243
AK		 425 /* The 82575 assigns vectors using a bitmask, which matches the
426 bitmask for the EICR/EIMS/EIMC registers. To assign one
427 or more queues to a vector, we write the appropriate bits
428 into the MSIXBM register for that vector. */
429 if (rx_queue > IGB_N0_QUEUE) {
430 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
431 adapter->rx_ring[rx_queue].eims_value = msixbm;
432 }
433 if (tx_queue > IGB_N0_QUEUE) {
434 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
435 adapter->tx_ring[tx_queue].eims_value =
436 E1000_EICR_TX_QUEUE0 << tx_queue;
437 }
438 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 439 break;
440 case e1000_82576:
26bc19ec 441 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 442 Each queue has a single entry in the table to which we write
443 a vector number along with a "valid" bit. Sadly, the layout
444 of the table is somewhat counterintuitive. */
445 if (rx_queue > IGB_N0_QUEUE) {
1bfaf07b 446 index = (rx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 447 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 448 if (rx_queue & 0x1) {
2d064c06
AD		 449 /* vector goes into third byte of register */
450 ivar = ivar & 0xFF00FFFF;
451 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 452 } else {
453 /* vector goes into low byte of register */
454 ivar = ivar & 0xFFFFFF00;
455 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 456 }
457 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
458 array_wr32(E1000_IVAR0, index, ivar);
459 }
460 if (tx_queue > IGB_N0_QUEUE) {
1bfaf07b 461 index = (tx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 462 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 463 if (tx_queue & 0x1) {
2d064c06
AD		 464 /* vector goes into high byte of register */
465 ivar = ivar & 0x00FFFFFF;
466 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 467 } else {
468 /* vector goes into second byte of register */
469 ivar = ivar & 0xFFFF00FF;
470 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 471 }
472 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
473 array_wr32(E1000_IVAR0, index, ivar);
474 }
475 break;
476 default:
477 BUG();
478 break;
479 }
9d5c8243
AK		 480}
481
482/**
483 * igb_configure_msix - Configure MSI-X hardware
484 *
485 * igb_configure_msix sets up the hardware to properly
486 * generate MSI-X interrupts.
487 **/
488static void igb_configure_msix(struct igb_adapter *adapter)
489{
490 u32 tmp;
491 int i, vector = 0;
492 struct e1000_hw *hw = &adapter->hw;
493
494 adapter->eims_enable_mask = 0;
2d064c06
AD		 495 if (hw->mac.type == e1000_82576)
496 /* Turn on MSI-X capability first, or our settings
497 * won't stick. And it will take days to debug. */
498 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 499 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 500 E1000_GPIE_NSICR);
9d5c8243
AK		 501
502 for (i = 0; i < adapter->num_tx_queues; i++) {
503 struct igb_ring *tx_ring = &adapter->tx_ring[i];
504 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
505 adapter->eims_enable_mask |= tx_ring->eims_value;
506 if (tx_ring->itr_val)
6eb5a7f1 507 writel(tx_ring->itr_val,
9d5c8243
AK		 508 hw->hw_addr + tx_ring->itr_register);
509 else
510 writel(1, hw->hw_addr + tx_ring->itr_register);
511 }
512
513 for (i = 0; i < adapter->num_rx_queues; i++) {
514 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 515 rx_ring->buddy = NULL;
9d5c8243
AK		 516 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
517 adapter->eims_enable_mask |= rx_ring->eims_value;
518 if (rx_ring->itr_val)
6eb5a7f1 519 writel(rx_ring->itr_val,
9d5c8243
AK		 520 hw->hw_addr + rx_ring->itr_register);
521 else
522 writel(1, hw->hw_addr + rx_ring->itr_register);
523 }
524
525
526 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 527 switch (hw->mac.type) {
528 case e1000_82575:
9d5c8243
AK		 529 array_wr32(E1000_MSIXBM(0), vector++,
530 E1000_EIMS_OTHER);
531
9d5c8243
AK		 532 tmp = rd32(E1000_CTRL_EXT);
533 /* enable MSI-X PBA support*/
534 tmp |= E1000_CTRL_EXT_PBA_CLR;
535
536 /* Auto-Mask interrupts upon ICR read. */
537 tmp |= E1000_CTRL_EXT_EIAME;
538 tmp |= E1000_CTRL_EXT_IRCA;
539
540 wr32(E1000_CTRL_EXT, tmp);
541 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 542 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 543
2d064c06
AD		 544 break;
545
546 case e1000_82576:
547 tmp = (vector++ | E1000_IVAR_VALID) << 8;
548 wr32(E1000_IVAR_MISC, tmp);
549
550 adapter->eims_enable_mask = (1 << (vector)) - 1;
551 adapter->eims_other = 1 << (vector - 1);
552 break;
553 default:
554 /* do nothing, since nothing else supports MSI-X */
555 break;
556 } /* switch (hw->mac.type) */
9d5c8243
AK		 557 wrfl();
558}
559
560/**
561 * igb_request_msix - Initialize MSI-X interrupts
562 *
563 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
564 * kernel.
565 **/
566static int igb_request_msix(struct igb_adapter *adapter)
567{
568 struct net_device *netdev = adapter->netdev;
569 int i, err = 0, vector = 0;
570
571 vector = 0;
572
573 for (i = 0; i < adapter->num_tx_queues; i++) {
574 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 575 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 576 err = request_irq(adapter->msix_entries[vector].vector,
577 &igb_msix_tx, 0, ring->name,
578 &(adapter->tx_ring[i]));
579 if (err)
580 goto out;
581 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 582 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 583 vector++;
584 }
585 for (i = 0; i < adapter->num_rx_queues; i++) {
586 struct igb_ring *ring = &(adapter->rx_ring[i]);
587 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 588 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 589 else
590 memcpy(ring->name, netdev->name, IFNAMSIZ);
591 err = request_irq(adapter->msix_entries[vector].vector,
592 &igb_msix_rx, 0, ring->name,
593 &(adapter->rx_ring[i]));
594 if (err)
595 goto out;
596 ring->itr_register = E1000_EITR(0) + (vector << 2);
597 ring->itr_val = adapter->itr;
598 vector++;
599 }
600
601 err = request_irq(adapter->msix_entries[vector].vector,
602 &igb_msix_other, 0, netdev->name, netdev);
603 if (err)
604 goto out;
605
9d5c8243
AK		 606 igb_configure_msix(adapter);
607 return 0;
608out:
609 return err;
610}
611
612static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
613{
614 if (adapter->msix_entries) {
615 pci_disable_msix(adapter->pdev);
616 kfree(adapter->msix_entries);
617 adapter->msix_entries = NULL;
7dfc16fa 618 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 619 pci_disable_msi(adapter->pdev);
620 return;
621}
622
623
624/**
625 * igb_set_interrupt_capability - set MSI or MSI-X if supported
626 *
627 * Attempt to configure interrupts using the best available
628 * capabilities of the hardware and kernel.
629 **/
630static void igb_set_interrupt_capability(struct igb_adapter *adapter)
631{
632 int err;
633 int numvecs, i;
634
83b7180d
AD		 635 /* Number of supported queues. */
636 /* Having more queues than CPUs doesn't make sense. */
637 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
638 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
639
9d5c8243
AK		 640 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
641 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
642 GFP_KERNEL);
643 if (!adapter->msix_entries)
644 goto msi_only;
645
646 for (i = 0; i < numvecs; i++)
647 adapter->msix_entries[i].entry = i;
648
649 err = pci_enable_msix(adapter->pdev,
650 adapter->msix_entries,
651 numvecs);
652 if (err == 0)
34a20e89 653 goto out;
9d5c8243
AK		 654
655 igb_reset_interrupt_capability(adapter);
656
657 /* If we can't do MSI-X, try MSI */
658msi_only:
659 adapter->num_rx_queues = 1;
661086df 660 adapter->num_tx_queues = 1;
9d5c8243 661 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 662 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 663out:
661086df 664 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 665 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 666 return;
667}
668
669/**
670 * igb_request_irq - initialize interrupts
671 *
672 * Attempts to configure interrupts using the best available
673 * capabilities of the hardware and kernel.
674 **/
675static int igb_request_irq(struct igb_adapter *adapter)
676{
677 struct net_device *netdev = adapter->netdev;
678 struct e1000_hw *hw = &adapter->hw;
679 int err = 0;
680
681 if (adapter->msix_entries) {
682 err = igb_request_msix(adapter);
844290e5 683 if (!err)
9d5c8243 684 goto request_done;
9d5c8243
AK		 685 /* fall back to MSI */
686 igb_reset_interrupt_capability(adapter);
687 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 688 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 689 igb_free_all_tx_resources(adapter);
690 igb_free_all_rx_resources(adapter);
691 adapter->num_rx_queues = 1;
692 igb_alloc_queues(adapter);
844290e5 693 } else {
2d064c06
AD		 694 switch (hw->mac.type) {
695 case e1000_82575:
696 wr32(E1000_MSIXBM(0),
697 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
698 break;
699 case e1000_82576:
700 wr32(E1000_IVAR0, E1000_IVAR_VALID);
701 break;
702 default:
703 break;
704 }
9d5c8243 705 }
844290e5 706
7dfc16fa 707 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 708 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
709 netdev->name, netdev);
710 if (!err)
711 goto request_done;
712 /* fall back to legacy interrupts */
713 igb_reset_interrupt_capability(adapter);
7dfc16fa 714 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 715 }
716
717 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
718 netdev->name, netdev);
719
6cb5e577 720 if (err)
9d5c8243
AK		 721 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
722 err);
9d5c8243
AK		 723
724request_done:
725 return err;
726}
727
728static void igb_free_irq(struct igb_adapter *adapter)
729{
730 struct net_device *netdev = adapter->netdev;
731
732 if (adapter->msix_entries) {
733 int vector = 0, i;
734
735 for (i = 0; i < adapter->num_tx_queues; i++)
736 free_irq(adapter->msix_entries[vector++].vector,
737 &(adapter->tx_ring[i]));
738 for (i = 0; i < adapter->num_rx_queues; i++)
739 free_irq(adapter->msix_entries[vector++].vector,
740 &(adapter->rx_ring[i]));
741
742 free_irq(adapter->msix_entries[vector++].vector, netdev);
743 return;
744 }
745
746 free_irq(adapter->pdev->irq, netdev);
747}
748
749/**
750 * igb_irq_disable - Mask off interrupt generation on the NIC
751 * @adapter: board private structure
752 **/
753static void igb_irq_disable(struct igb_adapter *adapter)
754{
755 struct e1000_hw *hw = &adapter->hw;
756
757 if (adapter->msix_entries) {
844290e5 758 wr32(E1000_EIAM, 0);
9d5c8243
AK		 759 wr32(E1000_EIMC, ~0);
760 wr32(E1000_EIAC, 0);
761 }
844290e5
PW		 762
763 wr32(E1000_IAM, 0);
9d5c8243
AK		 764 wr32(E1000_IMC, ~0);
765 wrfl();
766 synchronize_irq(adapter->pdev->irq);
767}
768
769/**
770 * igb_irq_enable - Enable default interrupt generation settings
771 * @adapter: board private structure
772 **/
773static void igb_irq_enable(struct igb_adapter *adapter)
774{
775 struct e1000_hw *hw = &adapter->hw;
776
777 if (adapter->msix_entries) {
844290e5
PW		 778 wr32(E1000_EIAC, adapter->eims_enable_mask);
779 wr32(E1000_EIAM, adapter->eims_enable_mask);
780 wr32(E1000_EIMS, adapter->eims_enable_mask);
4ae196df
AD		 781 if (adapter->vfs_allocated_count)
782 wr32(E1000_MBVFIMR, 0xFF);
783 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
784 E1000_IMS_DOUTSYNC));
844290e5
PW		 785 } else {
786 wr32(E1000_IMS, IMS_ENABLE_MASK);
787 wr32(E1000_IAM, IMS_ENABLE_MASK);
788 }
9d5c8243
AK		 789}
790
791static void igb_update_mng_vlan(struct igb_adapter *adapter)
792{
793 struct net_device *netdev = adapter->netdev;
794 u16 vid = adapter->hw.mng_cookie.vlan_id;
795 u16 old_vid = adapter->mng_vlan_id;
796 if (adapter->vlgrp) {
797 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
798 if (adapter->hw.mng_cookie.status &
799 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
800 igb_vlan_rx_add_vid(netdev, vid);
801 adapter->mng_vlan_id = vid;
802 } else
803 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
804
805 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
806 (vid != old_vid) &&
807 !vlan_group_get_device(adapter->vlgrp, old_vid))
808 igb_vlan_rx_kill_vid(netdev, old_vid);
809 } else
810 adapter->mng_vlan_id = vid;
811 }
812}
813
814/**
815 * igb_release_hw_control - release control of the h/w to f/w
816 * @adapter: address of board private structure
817 *
818 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
819 * For ASF and Pass Through versions of f/w this means that the
820 * driver is no longer loaded.
821 *
822 **/
823static void igb_release_hw_control(struct igb_adapter *adapter)
824{
825 struct e1000_hw *hw = &adapter->hw;
826 u32 ctrl_ext;
827
828 /* Let firmware take over control of h/w */
829 ctrl_ext = rd32(E1000_CTRL_EXT);
830 wr32(E1000_CTRL_EXT,
831 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
832}
833
834
835/**
836 * igb_get_hw_control - get control of the h/w from f/w
837 * @adapter: address of board private structure
838 *
839 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
840 * For ASF and Pass Through versions of f/w this means that
841 * the driver is loaded.
842 *
843 **/
844static void igb_get_hw_control(struct igb_adapter *adapter)
845{
846 struct e1000_hw *hw = &adapter->hw;
847 u32 ctrl_ext;
848
849 /* Let firmware know the driver has taken over */
850 ctrl_ext = rd32(E1000_CTRL_EXT);
851 wr32(E1000_CTRL_EXT,
852 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
853}
854
9d5c8243
AK		 855/**
856 * igb_configure - configure the hardware for RX and TX
857 * @adapter: private board structure
858 **/
859static void igb_configure(struct igb_adapter *adapter)
860{
861 struct net_device *netdev = adapter->netdev;
862 int i;
863
864 igb_get_hw_control(adapter);
865 igb_set_multi(netdev);
866
867 igb_restore_vlan(adapter);
9d5c8243
AK		 868
869 igb_configure_tx(adapter);
870 igb_setup_rctl(adapter);
871 igb_configure_rx(adapter);
662d7205
AD		 872
873 igb_rx_fifo_flush_82575(&adapter->hw);
874
9d5c8243
AK		 875 /* call IGB_DESC_UNUSED which always leaves
876 * at least 1 descriptor unused to make sure
877 * next_to_use != next_to_clean */
878 for (i = 0; i < adapter->num_rx_queues; i++) {
879 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 880 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 881 }
882
883
884 adapter->tx_queue_len = netdev->tx_queue_len;
885}
886
887
888/**
889 * igb_up - Open the interface and prepare it to handle traffic
890 * @adapter: board private structure
891 **/
892
893int igb_up(struct igb_adapter *adapter)
894{
895 struct e1000_hw *hw = &adapter->hw;
896 int i;
897
898 /* hardware has been reset, we need to reload some things */
899 igb_configure(adapter);
900
901 clear_bit(__IGB_DOWN, &adapter->state);
902
844290e5
PW		 903 for (i = 0; i < adapter->num_rx_queues; i++)
904 napi_enable(&adapter->rx_ring[i].napi);
905 if (adapter->msix_entries)
9d5c8243 906 igb_configure_msix(adapter);
9d5c8243 907
4ae196df 908 igb_vmm_control(adapter);
e1739522
AD		 909 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
910 igb_set_vmolr(hw, adapter->vfs_allocated_count);
911
9d5c8243
AK		 912 /* Clear any pending interrupts. */
913 rd32(E1000_ICR);
914 igb_irq_enable(adapter);
915
916 /* Fire a link change interrupt to start the watchdog. */
917 wr32(E1000_ICS, E1000_ICS_LSC);
918 return 0;
919}
920
921void igb_down(struct igb_adapter *adapter)
922{
923 struct e1000_hw *hw = &adapter->hw;
924 struct net_device *netdev = adapter->netdev;
925 u32 tctl, rctl;
926 int i;
927
928 /* signal that we're down so the interrupt handler does not
929 * reschedule our watchdog timer */
930 set_bit(__IGB_DOWN, &adapter->state);
931
932 /* disable receives in the hardware */
933 rctl = rd32(E1000_RCTL);
934 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
935 /* flush and sleep below */
936
fd2ea0a7 937 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 938
939 /* disable transmits in the hardware */
940 tctl = rd32(E1000_TCTL);
941 tctl &= ~E1000_TCTL_EN;
942 wr32(E1000_TCTL, tctl);
943 /* flush both disables and wait for them to finish */
944 wrfl();
945 msleep(10);
946
844290e5
PW		 947 for (i = 0; i < adapter->num_rx_queues; i++)
948 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 949
9d5c8243
AK		 950 igb_irq_disable(adapter);
951
952 del_timer_sync(&adapter->watchdog_timer);
953 del_timer_sync(&adapter->phy_info_timer);
954
955 netdev->tx_queue_len = adapter->tx_queue_len;
956 netif_carrier_off(netdev);
04fe6358
AD		 957
958 /* record the stats before reset*/
959 igb_update_stats(adapter);
960
9d5c8243
AK		 961 adapter->link_speed = 0;
962 adapter->link_duplex = 0;
963
3023682e
JK		 964 if (!pci_channel_offline(adapter->pdev))
965 igb_reset(adapter);
9d5c8243
AK		 966 igb_clean_all_tx_rings(adapter);
967 igb_clean_all_rx_rings(adapter);
968}
969
970void igb_reinit_locked(struct igb_adapter *adapter)
971{
972 WARN_ON(in_interrupt());
973 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
974 msleep(1);
975 igb_down(adapter);
976 igb_up(adapter);
977 clear_bit(__IGB_RESETTING, &adapter->state);
978}
979
980void igb_reset(struct igb_adapter *adapter)
981{
982 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 983 struct e1000_mac_info *mac = &hw->mac;
984 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 985 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
986 u16 hwm;
987
988 /* Repartition Pba for greater than 9k mtu
989 * To take effect CTRL.RST is required.
990 */
fa4dfae0
AD		 991 switch (mac->type) {
992 case e1000_82576:
2d064c06 993 pba = E1000_PBA_64K;
fa4dfae0
AD		 994 break;
995 case e1000_82575:
996 default:
997 pba = E1000_PBA_34K;
998 break;
2d064c06 999 }
9d5c8243 1000
2d064c06
AD		 1001 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1002 (mac->type < e1000_82576)) {
9d5c8243
AK		 1003 /* adjust PBA for jumbo frames */
1004 wr32(E1000_PBA, pba);
1005
1006 /* To maintain wire speed transmits, the Tx FIFO should be
1007 * large enough to accommodate two full transmit packets,
1008 * rounded up to the next 1KB and expressed in KB. Likewise,
1009 * the Rx FIFO should be large enough to accommodate at least
1010 * one full receive packet and is similarly rounded up and
1011 * expressed in KB. */
1012 pba = rd32(E1000_PBA);
1013 /* upper 16 bits has Tx packet buffer allocation size in KB */
1014 tx_space = pba >> 16;
1015 /* lower 16 bits has Rx packet buffer allocation size in KB */
1016 pba &= 0xffff;
1017 /* the tx fifo also stores 16 bytes of information about the tx
1018 * but don't include ethernet FCS because hardware appends it */
1019 min_tx_space = (adapter->max_frame_size +
85e8d004 1020 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1021 ETH_FCS_LEN) * 2;
1022 min_tx_space = ALIGN(min_tx_space, 1024);
1023 min_tx_space >>= 10;
1024 /* software strips receive CRC, so leave room for it */
1025 min_rx_space = adapter->max_frame_size;
1026 min_rx_space = ALIGN(min_rx_space, 1024);
1027 min_rx_space >>= 10;
1028
1029 /* If current Tx allocation is less than the min Tx FIFO size,
1030 * and the min Tx FIFO size is less than the current Rx FIFO
1031 * allocation, take space away from current Rx allocation */
1032 if (tx_space < min_tx_space &&
1033 ((min_tx_space - tx_space) < pba)) {
1034 pba = pba - (min_tx_space - tx_space);
1035
1036 /* if short on rx space, rx wins and must trump tx
1037 * adjustment */
1038 if (pba < min_rx_space)
1039 pba = min_rx_space;
1040 }
2d064c06 1041 wr32(E1000_PBA, pba);
9d5c8243 1042 }
9d5c8243
AK		 1043
1044 /* flow control settings */
1045 /* The high water mark must be low enough to fit one full frame
1046 * (or the size used for early receive) above it in the Rx FIFO.
1047 * Set it to the lower of:
1048 * - 90% of the Rx FIFO size, or
1049 * - the full Rx FIFO size minus one full frame */
1050 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1051 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1052
2d064c06
AD		 1053 if (mac->type < e1000_82576) {
1054 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1055 fc->low_water = fc->high_water - 8;
1056 } else {
1057 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1058 fc->low_water = fc->high_water - 16;
1059 }
9d5c8243
AK		 1060 fc->pause_time = 0xFFFF;
1061 fc->send_xon = 1;
1062 fc->type = fc->original_type;
1063
4ae196df
AD		 1064 /* disable receive for all VFs and wait one second */
1065 if (adapter->vfs_allocated_count) {
1066 int i;
1067 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1068 adapter->vf_data[i].clear_to_send = false;
1069
1070 /* ping all the active vfs to let them know we are going down */
1071 igb_ping_all_vfs(adapter);
1072
1073 /* disable transmits and receives */
1074 wr32(E1000_VFRE, 0);
1075 wr32(E1000_VFTE, 0);
1076 }
1077
9d5c8243
AK		 1078 /* Allow time for pending master requests to run */
1079 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1080 wr32(E1000_WUC, 0);
1081
1082 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1083 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1084
1085 igb_update_mng_vlan(adapter);
1086
1087 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1088 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1089
1090 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1091 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1092}
1093
2e5c6922
SH		 1094static const struct net_device_ops igb_netdev_ops = {
1095 .ndo_open = igb_open,
1096 .ndo_stop = igb_close,
00829823 1097 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 1098 .ndo_get_stats = igb_get_stats,
1099 .ndo_set_multicast_list = igb_set_multi,
1100 .ndo_set_mac_address = igb_set_mac,
1101 .ndo_change_mtu = igb_change_mtu,
1102 .ndo_do_ioctl = igb_ioctl,
1103 .ndo_tx_timeout = igb_tx_timeout,
1104 .ndo_validate_addr = eth_validate_addr,
1105 .ndo_vlan_rx_register = igb_vlan_rx_register,
1106 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1107 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1108#ifdef CONFIG_NET_POLL_CONTROLLER
1109 .ndo_poll_controller = igb_netpoll,
1110#endif
1111};
1112
9d5c8243
AK		 1113/**
1114 * igb_probe - Device Initialization Routine
1115 * @pdev: PCI device information struct
1116 * @ent: entry in igb_pci_tbl
1117 *
1118 * Returns 0 on success, negative on failure
1119 *
1120 * igb_probe initializes an adapter identified by a pci_dev structure.
1121 * The OS initialization, configuring of the adapter private structure,
1122 * and a hardware reset occur.
1123 **/
1124static int __devinit igb_probe(struct pci_dev *pdev,
1125 const struct pci_device_id *ent)
1126{
1127 struct net_device *netdev;
1128 struct igb_adapter *adapter;
1129 struct e1000_hw *hw;
c54106bb 1130 struct pci_dev *us_dev;
9d5c8243
AK		 1131 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1132 unsigned long mmio_start, mmio_len;
450c87c8 1133 int err, pci_using_dac, pos;
c54106bb 1134 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 1135 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1136 u32 part_num;
1137
aed5dec3 1138 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1139 if (err)
1140 return err;
1141
1142 pci_using_dac = 0;
1143 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1144 if (!err) {
1145 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1146 if (!err)
1147 pci_using_dac = 1;
1148 } else {
1149 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1150 if (err) {
1151 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1152 if (err) {
1153 dev_err(&pdev->dev, "No usable DMA "
1154 "configuration, aborting\n");
1155 goto err_dma;
1156 }
1157 }
1158 }
1159
c54106bb
AD		 1160 /* 82575 requires that the pci-e link partner disable the L0s state */
1161 switch (pdev->device) {
1162 case E1000_DEV_ID_82575EB_COPPER:
1163 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1164 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1165 us_dev = pdev->bus->self;
1166 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1167 if (pos) {
1168 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1169 &state);
1170 state &= ~PCIE_LINK_STATE_L0S;
1171 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1172 state);
ac450208
BH		 1173 dev_info(&pdev->dev,
1174 "Disabling ASPM L0s upstream switch port %s\n",
1175 pci_name(us_dev));
c54106bb
AD		 1176 }
1177 default:
1178 break;
1179 }
1180
aed5dec3
AD		 1181 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1182 IORESOURCE_MEM),
1183 igb_driver_name);
9d5c8243
AK		 1184 if (err)
1185 goto err_pci_reg;
1186
ea943d41
JK		 1187 err = pci_enable_pcie_error_reporting(pdev);
1188 if (err) {
1189 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1190 "0x%x\n", err);
1191 /* non-fatal, continue */
1192 }
40a914fa 1193
9d5c8243 1194 pci_set_master(pdev);
c682fc23 1195 pci_save_state(pdev);
9d5c8243
AK		 1196
1197 err = -ENOMEM;
1bfaf07b
AD		 1198 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1199 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1200 if (!netdev)
1201 goto err_alloc_etherdev;
1202
1203 SET_NETDEV_DEV(netdev, &pdev->dev);
1204
1205 pci_set_drvdata(pdev, netdev);
1206 adapter = netdev_priv(netdev);
1207 adapter->netdev = netdev;
1208 adapter->pdev = pdev;
1209 hw = &adapter->hw;
1210 hw->back = adapter;
1211 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1212
1213 mmio_start = pci_resource_start(pdev, 0);
1214 mmio_len = pci_resource_len(pdev, 0);
1215
1216 err = -EIO;
28b0759c
AD		 1217 hw->hw_addr = ioremap(mmio_start, mmio_len);
1218 if (!hw->hw_addr)
9d5c8243
AK		 1219 goto err_ioremap;
1220
2e5c6922 1221 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1222 igb_set_ethtool_ops(netdev);
9d5c8243 1223 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1224
1225 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1226
1227 netdev->mem_start = mmio_start;
1228 netdev->mem_end = mmio_start + mmio_len;
1229
9d5c8243
AK		 1230 /* PCI config space info */
1231 hw->vendor_id = pdev->vendor;
1232 hw->device_id = pdev->device;
1233 hw->revision_id = pdev->revision;
1234 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1235 hw->subsystem_device_id = pdev->subsystem_device;
1236
1237 /* setup the private structure */
1238 hw->back = adapter;
1239 /* Copy the default MAC, PHY and NVM function pointers */
1240 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1241 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1242 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1243 /* Initialize skew-specific constants */
1244 err = ei->get_invariants(hw);
1245 if (err)
450c87c8 1246 goto err_sw_init;
9d5c8243 1247
450c87c8 1248 /* setup the private structure */
9d5c8243
AK		 1249 err = igb_sw_init(adapter);
1250 if (err)
1251 goto err_sw_init;
1252
1253 igb_get_bus_info_pcie(hw);
1254
7dfc16fa
AD		 1255 /* set flags */
1256 switch (hw->mac.type) {
7dfc16fa 1257 case e1000_82575:
7dfc16fa
AD		 1258 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1259 break;
bbd98fe4 1260 case e1000_82576:
7dfc16fa
AD		 1261 default:
1262 break;
1263 }
1264
9d5c8243
AK		 1265 hw->phy.autoneg_wait_to_complete = false;
1266 hw->mac.adaptive_ifs = true;
1267
1268 /* Copper options */
1269 if (hw->phy.media_type == e1000_media_type_copper) {
1270 hw->phy.mdix = AUTO_ALL_MODES;
1271 hw->phy.disable_polarity_correction = false;
1272 hw->phy.ms_type = e1000_ms_hw_default;
1273 }
1274
1275 if (igb_check_reset_block(hw))
1276 dev_info(&pdev->dev,
1277 "PHY reset is blocked due to SOL/IDER session.\n");
1278
1279 netdev->features = NETIF_F_SG |
7d8eb29e 1280 NETIF_F_IP_CSUM |
9d5c8243
AK		 1281 NETIF_F_HW_VLAN_TX |
1282 NETIF_F_HW_VLAN_RX |
1283 NETIF_F_HW_VLAN_FILTER;
1284
7d8eb29e 1285 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1286 netdev->features |= NETIF_F_TSO;
9d5c8243 1287 netdev->features |= NETIF_F_TSO6;
48f29ffc 1288
5c0999b7 1289 netdev->features |= NETIF_F_GRO;
d3352520 1290
48f29ffc
JK		 1291 netdev->vlan_features |= NETIF_F_TSO;
1292 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1293 netdev->vlan_features |= NETIF_F_IP_CSUM;
48f29ffc
JK		 1294 netdev->vlan_features |= NETIF_F_SG;
1295
9d5c8243
AK		 1296 if (pci_using_dac)
1297 netdev->features |= NETIF_F_HIGHDMA;
1298
9d5c8243
AK		 1299 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1300
1301 /* before reading the NVM, reset the controller to put the device in a
1302 * known good starting state */
1303 hw->mac.ops.reset_hw(hw);
1304
1305 /* make sure the NVM is good */
1306 if (igb_validate_nvm_checksum(hw) < 0) {
1307 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1308 err = -EIO;
1309 goto err_eeprom;
1310 }
1311
1312 /* copy the MAC address out of the NVM */
1313 if (hw->mac.ops.read_mac_addr(hw))
1314 dev_err(&pdev->dev, "NVM Read Error\n");
1315
1316 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1317 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1318
1319 if (!is_valid_ether_addr(netdev->perm_addr)) {
1320 dev_err(&pdev->dev, "Invalid MAC Address\n");
1321 err = -EIO;
1322 goto err_eeprom;
1323 }
1324
1325 init_timer(&adapter->watchdog_timer);
1326 adapter->watchdog_timer.function = &igb_watchdog;
1327 adapter->watchdog_timer.data = (unsigned long) adapter;
1328
1329 init_timer(&adapter->phy_info_timer);
1330 adapter->phy_info_timer.function = &igb_update_phy_info;
1331 adapter->phy_info_timer.data = (unsigned long) adapter;
1332
1333 INIT_WORK(&adapter->reset_task, igb_reset_task);
1334 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1335
450c87c8 1336 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1337 adapter->fc_autoneg = true;
1338 hw->mac.autoneg = true;
1339 hw->phy.autoneg_advertised = 0x2f;
1340
1341 hw->fc.original_type = e1000_fc_default;
1342 hw->fc.type = e1000_fc_default;
1343
cbd347ad 1344 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1345 adapter->itr = IGB_START_ITR;
1346
1347 igb_validate_mdi_setting(hw);
1348
1349 adapter->rx_csum = 1;
1350
1351 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1352 * enable the ACPI Magic Packet filter
1353 */
1354
a2cf8b6c 1355 if (hw->bus.func == 0)
312c75ae 1356 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
a2cf8b6c
AD		 1357 else if (hw->bus.func == 1)
1358 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1359
1360 if (eeprom_data & eeprom_apme_mask)
1361 adapter->eeprom_wol |= E1000_WUFC_MAG;
1362
1363 /* now that we have the eeprom settings, apply the special cases where
1364 * the eeprom may be wrong or the board simply won't support wake on
1365 * lan on a particular port */
1366 switch (pdev->device) {
1367 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1368 adapter->eeprom_wol = 0;
1369 break;
1370 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1371 case E1000_DEV_ID_82576_FIBER:
1372 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1373 /* Wake events only supported on port A for dual fiber
1374 * regardless of eeprom setting */
1375 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1376 adapter->eeprom_wol = 0;
1377 break;
1378 }
1379
1380 /* initialize the wol settings based on the eeprom settings */
1381 adapter->wol = adapter->eeprom_wol;
e1b86d84 1382 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1383
1384 /* reset the hardware with the new settings */
1385 igb_reset(adapter);
1386
1387 /* let the f/w know that the h/w is now under the control of the
1388 * driver. */
1389 igb_get_hw_control(adapter);
1390
1391 /* tell the stack to leave us alone until igb_open() is called */
1392 netif_carrier_off(netdev);
fd2ea0a7 1393 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1394
1395 strcpy(netdev->name, "eth%d");
1396 err = register_netdev(netdev);
1397 if (err)
1398 goto err_register;
1399
37680117
AD		 1400#ifdef CONFIG_PCI_IOV
1401 /* since iov functionality isn't critical to base device function we
1402 * can accept failure. If it fails we don't allow iov to be enabled */
1403 if (hw->mac.type == e1000_82576) {
1404 err = pci_enable_sriov(pdev, 0);
1405 if (!err)
1406 err = device_create_file(&netdev->dev,
1407 &dev_attr_num_vfs);
1408 if (err)
1409 dev_err(&pdev->dev, "Failed to initialize IOV\n");
1410 }
1411
1412#endif
421e02f0 1413#ifdef CONFIG_IGB_DCA
bbd98fe4 1414 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1415 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1416 dev_info(&pdev->dev, "DCA enabled\n");
1417 /* Always use CB2 mode, difference is masked
1418 * in the CB driver. */
cbd347ad 1419 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6
JC		 1420 igb_setup_dca(adapter);
1421 }
1422#endif
1423
38c845c7
PO		 1424 /*
1425 * Initialize hardware timer: we keep it running just in case
1426 * that some program needs it later on.
1427 */
1428 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1429 adapter->cycles.read = igb_read_clock;
1430 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1431 adapter->cycles.mult = 1;
1432 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1433 wr32(E1000_TIMINCA,
1434 (1<<24) |
1435 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1436#if 0
1437 /*
1438 * Avoid rollover while we initialize by resetting the time counter.
1439 */
1440 wr32(E1000_SYSTIML, 0x00000000);
1441 wr32(E1000_SYSTIMH, 0x00000000);
1442#else
1443 /*
1444 * Set registers so that rollover occurs soon to test this.
1445 */
1446 wr32(E1000_SYSTIML, 0x00000000);
1447 wr32(E1000_SYSTIMH, 0xFF800000);
1448#endif
1449 wrfl();
1450 timecounter_init(&adapter->clock,
1451 &adapter->cycles,
1452 ktime_to_ns(ktime_get_real()));
1453
33af6bcc
PO		 1454 /*
1455 * Synchronize our NIC clock against system wall clock. NIC
1456 * time stamp reading requires ~3us per sample, each sample
1457 * was pretty stable even under load => only require 10
1458 * samples for each offset comparison.
1459 */
1460 memset(&adapter->compare, 0, sizeof(adapter->compare));
1461 adapter->compare.source = &adapter->clock;
1462 adapter->compare.target = ktime_get_real;
1463 adapter->compare.num_samples = 10;
1464 timecompare_update(&adapter->compare, 0);
1465
38c845c7
PO		 1466#ifdef DEBUG
1467 {
1468 char buffer[160];
1469 printk(KERN_DEBUG
1470 "igb: %s: hw %p initialized timer\n",
1471 igb_get_time_str(adapter, buffer),
1472 &adapter->hw);
1473 }
1474#endif
1475
9d5c8243
AK		 1476 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1477 /* print bus type/speed/width info */
7c510e4b 1478 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1479 netdev->name,
1480 ((hw->bus.speed == e1000_bus_speed_2500)
1481 ? "2.5Gb/s" : "unknown"),
1482 ((hw->bus.width == e1000_bus_width_pcie_x4)
1483 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1484 ? "Width x1" : "unknown"),
7c510e4b 1485 netdev->dev_addr);
9d5c8243
AK		 1486
1487 igb_read_part_num(hw, &part_num);
1488 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1489 (part_num >> 8), (part_num & 0xff));
1490
1491 dev_info(&pdev->dev,
1492 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1493 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1494 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1495 adapter->num_rx_queues, adapter->num_tx_queues);
1496
9d5c8243
AK		 1497 return 0;
1498
1499err_register:
1500 igb_release_hw_control(adapter);
1501err_eeprom:
1502 if (!igb_check_reset_block(hw))
f5f4cf08 1503 igb_reset_phy(hw);
9d5c8243
AK		 1504
1505 if (hw->flash_address)
1506 iounmap(hw->flash_address);
1507
a88f10ec 1508 igb_free_queues(adapter);
9d5c8243 1509err_sw_init:
9d5c8243
AK		 1510 iounmap(hw->hw_addr);
1511err_ioremap:
1512 free_netdev(netdev);
1513err_alloc_etherdev:
aed5dec3
AD		 1514 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1515 IORESOURCE_MEM));
9d5c8243
AK		 1516err_pci_reg:
1517err_dma:
1518 pci_disable_device(pdev);
1519 return err;
1520}
1521
1522/**
1523 * igb_remove - Device Removal Routine
1524 * @pdev: PCI device information struct
1525 *
1526 * igb_remove is called by the PCI subsystem to alert the driver
1527 * that it should release a PCI device. The could be caused by a
1528 * Hot-Plug event, or because the driver is going to be removed from
1529 * memory.
1530 **/
1531static void __devexit igb_remove(struct pci_dev *pdev)
1532{
1533 struct net_device *netdev = pci_get_drvdata(pdev);
1534 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1535 struct e1000_hw *hw = &adapter->hw;
ea943d41 1536 int err;
9d5c8243
AK		 1537
1538 /* flush_scheduled work may reschedule our watchdog task, so
1539 * explicitly disable watchdog tasks from being rescheduled */
1540 set_bit(__IGB_DOWN, &adapter->state);
1541 del_timer_sync(&adapter->watchdog_timer);
1542 del_timer_sync(&adapter->phy_info_timer);
1543
1544 flush_scheduled_work();
1545
421e02f0 1546#ifdef CONFIG_IGB_DCA
7dfc16fa 1547 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1548 dev_info(&pdev->dev, "DCA disabled\n");
1549 dca_remove_requester(&pdev->dev);
7dfc16fa 1550 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1551 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1552 }
1553#endif
1554
9d5c8243
AK		 1555 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1556 * would have already happened in close and is redundant. */
1557 igb_release_hw_control(adapter);
1558
1559 unregister_netdev(netdev);
1560
f5f4cf08
AD		 1561 if (!igb_check_reset_block(&adapter->hw))
1562 igb_reset_phy(&adapter->hw);
9d5c8243 1563
9d5c8243
AK		 1564 igb_reset_interrupt_capability(adapter);
1565
a88f10ec 1566 igb_free_queues(adapter);
9d5c8243 1567
37680117
AD		 1568#ifdef CONFIG_PCI_IOV
1569 /* reclaim resources allocated to VFs */
1570 if (adapter->vf_data) {
1571 /* disable iov and allow time for transactions to clear */
1572 pci_disable_sriov(pdev);
1573 msleep(500);
1574
1575 kfree(adapter->vf_data);
1576 adapter->vf_data = NULL;
1577 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1578 msleep(100);
1579 dev_info(&pdev->dev, "IOV Disabled\n");
1580 }
1581#endif
28b0759c
AD		 1582 iounmap(hw->hw_addr);
1583 if (hw->flash_address)
1584 iounmap(hw->flash_address);
aed5dec3
AD		 1585 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1586 IORESOURCE_MEM));
9d5c8243
AK		 1587
1588 free_netdev(netdev);
1589
ea943d41
JK		 1590 err = pci_disable_pcie_error_reporting(pdev);
1591 if (err)
1592 dev_err(&pdev->dev,
1593 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1594
9d5c8243
AK		 1595 pci_disable_device(pdev);
1596}
1597
1598/**
1599 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1600 * @adapter: board private structure to initialize
1601 *
1602 * igb_sw_init initializes the Adapter private data structure.
1603 * Fields are initialized based on PCI device information and
1604 * OS network device settings (MTU size).
1605 **/
1606static int __devinit igb_sw_init(struct igb_adapter *adapter)
1607{
1608 struct e1000_hw *hw = &adapter->hw;
1609 struct net_device *netdev = adapter->netdev;
1610 struct pci_dev *pdev = adapter->pdev;
1611
1612 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1613
68fd9910
AD		 1614 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1615 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1616 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1617 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1618 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1619 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1620
661086df
PWJ		 1621 /* This call may decrease the number of queues depending on
1622 * interrupt mode. */
9d5c8243
AK		 1623 igb_set_interrupt_capability(adapter);
1624
1625 if (igb_alloc_queues(adapter)) {
1626 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1627 return -ENOMEM;
1628 }
1629
1630 /* Explicitly disable IRQ since the NIC can be in any state. */
1631 igb_irq_disable(adapter);
1632
1633 set_bit(__IGB_DOWN, &adapter->state);
1634 return 0;
1635}
1636
1637/**
1638 * igb_open - Called when a network interface is made active
1639 * @netdev: network interface device structure
1640 *
1641 * Returns 0 on success, negative value on failure
1642 *
1643 * The open entry point is called when a network interface is made
1644 * active by the system (IFF_UP). At this point all resources needed
1645 * for transmit and receive operations are allocated, the interrupt
1646 * handler is registered with the OS, the watchdog timer is started,
1647 * and the stack is notified that the interface is ready.
1648 **/
1649static int igb_open(struct net_device *netdev)
1650{
1651 struct igb_adapter *adapter = netdev_priv(netdev);
1652 struct e1000_hw *hw = &adapter->hw;
1653 int err;
1654 int i;
1655
1656 /* disallow open during test */
1657 if (test_bit(__IGB_TESTING, &adapter->state))
1658 return -EBUSY;
1659
1660 /* allocate transmit descriptors */
1661 err = igb_setup_all_tx_resources(adapter);
1662 if (err)
1663 goto err_setup_tx;
1664
1665 /* allocate receive descriptors */
1666 err = igb_setup_all_rx_resources(adapter);
1667 if (err)
1668 goto err_setup_rx;
1669
1670 /* e1000_power_up_phy(adapter); */
1671
1672 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1673 if ((adapter->hw.mng_cookie.status &
1674 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1675 igb_update_mng_vlan(adapter);
1676
1677 /* before we allocate an interrupt, we must be ready to handle it.
1678 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1679 * as soon as we call pci_request_irq, so we have to setup our
1680 * clean_rx handler before we do so. */
1681 igb_configure(adapter);
1682
4ae196df 1683 igb_vmm_control(adapter);
e1739522
AD		 1684 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1685 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1686
9d5c8243
AK		 1687 err = igb_request_irq(adapter);
1688 if (err)
1689 goto err_req_irq;
1690
1691 /* From here on the code is the same as igb_up() */
1692 clear_bit(__IGB_DOWN, &adapter->state);
1693
844290e5
PW		 1694 for (i = 0; i < adapter->num_rx_queues; i++)
1695 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1696
1697 /* Clear any pending interrupts. */
1698 rd32(E1000_ICR);
844290e5
PW		 1699
1700 igb_irq_enable(adapter);
1701
d55b53ff
JK		 1702 netif_tx_start_all_queues(netdev);
1703
9d5c8243
AK		 1704 /* Fire a link status change interrupt to start the watchdog. */
1705 wr32(E1000_ICS, E1000_ICS_LSC);
1706
1707 return 0;
1708
1709err_req_irq:
1710 igb_release_hw_control(adapter);
1711 /* e1000_power_down_phy(adapter); */
1712 igb_free_all_rx_resources(adapter);
1713err_setup_rx:
1714 igb_free_all_tx_resources(adapter);
1715err_setup_tx:
1716 igb_reset(adapter);
1717
1718 return err;
1719}
1720
1721/**
1722 * igb_close - Disables a network interface
1723 * @netdev: network interface device structure
1724 *
1725 * Returns 0, this is not allowed to fail
1726 *
1727 * The close entry point is called when an interface is de-activated
1728 * by the OS. The hardware is still under the driver's control, but
1729 * needs to be disabled. A global MAC reset is issued to stop the
1730 * hardware, and all transmit and receive resources are freed.
1731 **/
1732static int igb_close(struct net_device *netdev)
1733{
1734 struct igb_adapter *adapter = netdev_priv(netdev);
1735
1736 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1737 igb_down(adapter);
1738
1739 igb_free_irq(adapter);
1740
1741 igb_free_all_tx_resources(adapter);
1742 igb_free_all_rx_resources(adapter);
1743
1744 /* kill manageability vlan ID if supported, but not if a vlan with
1745 * the same ID is registered on the host OS (let 8021q kill it) */
1746 if ((adapter->hw.mng_cookie.status &
1747 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1748 !(adapter->vlgrp &&
1749 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1750 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1751
1752 return 0;
1753}
1754
1755/**
1756 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1757 * @adapter: board private structure
1758 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1759 *
1760 * Return 0 on success, negative on failure
1761 **/
9d5c8243
AK		 1762int igb_setup_tx_resources(struct igb_adapter *adapter,
1763 struct igb_ring *tx_ring)
1764{
1765 struct pci_dev *pdev = adapter->pdev;
1766 int size;
1767
1768 size = sizeof(struct igb_buffer) * tx_ring->count;
1769 tx_ring->buffer_info = vmalloc(size);
1770 if (!tx_ring->buffer_info)
1771 goto err;
1772 memset(tx_ring->buffer_info, 0, size);
1773
1774 /* round up to nearest 4K */
85e8d004 1775 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 1776 tx_ring->size = ALIGN(tx_ring->size, 4096);
1777
1778 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1779 &tx_ring->dma);
1780
1781 if (!tx_ring->desc)
1782 goto err;
1783
1784 tx_ring->adapter = adapter;
1785 tx_ring->next_to_use = 0;
1786 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1787 return 0;
1788
1789err:
1790 vfree(tx_ring->buffer_info);
1791 dev_err(&adapter->pdev->dev,
1792 "Unable to allocate memory for the transmit descriptor ring\n");
1793 return -ENOMEM;
1794}
1795
1796/**
1797 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1798 * (Descriptors) for all queues
1799 * @adapter: board private structure
1800 *
1801 * Return 0 on success, negative on failure
1802 **/
1803static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1804{
1805 int i, err = 0;
661086df 1806 int r_idx;
9d5c8243
AK		 1807
1808 for (i = 0; i < adapter->num_tx_queues; i++) {
1809 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1810 if (err) {
1811 dev_err(&adapter->pdev->dev,
1812 "Allocation for Tx Queue %u failed\n", i);
1813 for (i--; i >= 0; i--)
3b644cf6 1814 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1815 break;
1816 }
1817 }
1818
661086df
PWJ		 1819 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1820 r_idx = i % adapter->num_tx_queues;
1821 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1822 }
9d5c8243
AK		 1823 return err;
1824}
1825
1826/**
1827 * igb_configure_tx - Configure transmit Unit after Reset
1828 * @adapter: board private structure
1829 *
1830 * Configure the Tx unit of the MAC after a reset.
1831 **/
1832static void igb_configure_tx(struct igb_adapter *adapter)
1833{
0e014cb1 1834 u64 tdba;
9d5c8243
AK		 1835 struct e1000_hw *hw = &adapter->hw;
1836 u32 tctl;
1837 u32 txdctl, txctrl;
26bc19ec 1838 int i, j;
9d5c8243
AK		 1839
1840 for (i = 0; i < adapter->num_tx_queues; i++) {
73cd78f1 1841 struct igb_ring *ring = &adapter->tx_ring[i];
26bc19ec
AD		 1842 j = ring->reg_idx;
1843 wr32(E1000_TDLEN(j),
85e8d004 1844 ring->count * sizeof(union e1000_adv_tx_desc));
9d5c8243 1845 tdba = ring->dma;
26bc19ec 1846 wr32(E1000_TDBAL(j),
73cd78f1 1847 tdba & 0x00000000ffffffffULL);
26bc19ec 1848 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1849
26bc19ec
AD		 1850 ring->head = E1000_TDH(j);
1851 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1852 writel(0, hw->hw_addr + ring->tail);
1853 writel(0, hw->hw_addr + ring->head);
26bc19ec 1854 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1855 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1856 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1857
1858 /* Turn off Relaxed Ordering on head write-backs. The
1859 * writebacks MUST be delivered in order or it will
1860 * completely screw up our bookeeping.
1861 */
26bc19ec 1862 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1863 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1864 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1865 }
1866
e1739522
AD		 1867 /* disable queue 0 to prevent tail bump w/o re-configuration */
1868 if (adapter->vfs_allocated_count)
1869 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 1870
1871 /* Program the Transmit Control Register */
9d5c8243
AK		 1872 tctl = rd32(E1000_TCTL);
1873 tctl &= ~E1000_TCTL_CT;
1874 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1875 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1876
1877 igb_config_collision_dist(hw);
1878
1879 /* Setup Transmit Descriptor Settings for eop descriptor */
1880 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1881
1882 /* Enable transmits */
1883 tctl |= E1000_TCTL_EN;
1884
1885 wr32(E1000_TCTL, tctl);
1886}
1887
1888/**
1889 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1890 * @adapter: board private structure
1891 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1892 *
1893 * Returns 0 on success, negative on failure
1894 **/
9d5c8243
AK		 1895int igb_setup_rx_resources(struct igb_adapter *adapter,
1896 struct igb_ring *rx_ring)
1897{
1898 struct pci_dev *pdev = adapter->pdev;
1899 int size, desc_len;
1900
1901 size = sizeof(struct igb_buffer) * rx_ring->count;
1902 rx_ring->buffer_info = vmalloc(size);
1903 if (!rx_ring->buffer_info)
1904 goto err;
1905 memset(rx_ring->buffer_info, 0, size);
1906
1907 desc_len = sizeof(union e1000_adv_rx_desc);
1908
1909 /* Round up to nearest 4K */
1910 rx_ring->size = rx_ring->count * desc_len;
1911 rx_ring->size = ALIGN(rx_ring->size, 4096);
1912
1913 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1914 &rx_ring->dma);
1915
1916 if (!rx_ring->desc)
1917 goto err;
1918
1919 rx_ring->next_to_clean = 0;
1920 rx_ring->next_to_use = 0;
9d5c8243
AK		 1921
1922 rx_ring->adapter = adapter;
9d5c8243
AK		 1923
1924 return 0;
1925
1926err:
1927 vfree(rx_ring->buffer_info);
1928 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1929 "the receive descriptor ring\n");
1930 return -ENOMEM;
1931}
1932
1933/**
1934 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1935 * (Descriptors) for all queues
1936 * @adapter: board private structure
1937 *
1938 * Return 0 on success, negative on failure
1939 **/
1940static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1941{
1942 int i, err = 0;
1943
1944 for (i = 0; i < adapter->num_rx_queues; i++) {
1945 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1946 if (err) {
1947 dev_err(&adapter->pdev->dev,
1948 "Allocation for Rx Queue %u failed\n", i);
1949 for (i--; i >= 0; i--)
3b644cf6 1950 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1951 break;
1952 }
1953 }
1954
1955 return err;
1956}
1957
1958/**
1959 * igb_setup_rctl - configure the receive control registers
1960 * @adapter: Board private structure
1961 **/
1962static void igb_setup_rctl(struct igb_adapter *adapter)
1963{
1964 struct e1000_hw *hw = &adapter->hw;
1965 u32 rctl;
1966 u32 srrctl = 0;
26bc19ec 1967 int i, j;
9d5c8243
AK		 1968
1969 rctl = rd32(E1000_RCTL);
1970
1971 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1972 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1973
69d728ba 1974 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 1975 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 1976
87cb7e8c
AK		 1977 /*
1978 * enable stripping of CRC. It's unlikely this will break BMC
1979 * redirection as it did with e1000. Newer features require
1980 * that the HW strips the CRC.
73cd78f1 1981 */
87cb7e8c 1982 rctl |= E1000_RCTL_SECRC;
9d5c8243 1983
9b07f3d3 1984 /*
ec54d7d6 1985 * disable store bad packets and clear size bits.
9b07f3d3 1986 */
ec54d7d6 1987 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 1988
ec54d7d6 1989 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 1990 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 1991
1992 /* Setup buffer sizes */
1993 switch (adapter->rx_buffer_len) {
1994 case IGB_RXBUFFER_256:
1995 rctl |= E1000_RCTL_SZ_256;
1996 break;
1997 case IGB_RXBUFFER_512:
1998 rctl |= E1000_RCTL_SZ_512;
1999 break;
2000 default:
2001 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2002 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2003 break;
9d5c8243
AK		 2004 }
2005
2006 /* 82575 and greater support packet-split where the protocol
2007 * header is placed in skb->data and the packet data is
2008 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2009 * In the case of a non-split, skb->data is linearly filled,
2010 * followed by the page buffers. Therefore, skb->data is
2011 * sized to hold the largest protocol header.
2012 */
2013 /* allocations using alloc_page take too long for regular MTU
2014 * so only enable packet split for jumbo frames */
ec54d7d6 2015 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 2016 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 2017 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 2018 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 2019 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2020 } else {
2021 adapter->rx_ps_hdr_size = 0;
2022 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2023 }
2024
e1739522
AD		 2025 /* Attention!!! For SR-IOV PF driver operations you must enable
2026 * queue drop for all VF and PF queues to prevent head of line blocking
2027 * if an un-trusted VF does not provide descriptors to hardware.
2028 */
2029 if (adapter->vfs_allocated_count) {
2030 u32 vmolr;
2031
2032 j = adapter->rx_ring[0].reg_idx;
2033
2034 /* set all queue drop enable bits */
2035 wr32(E1000_QDE, ALL_QUEUES);
2036 srrctl |= E1000_SRRCTL_DROP_EN;
2037
2038 /* disable queue 0 to prevent tail write w/o re-config */
2039 wr32(E1000_RXDCTL(0), 0);
2040
2041 vmolr = rd32(E1000_VMOLR(j));
2042 if (rctl & E1000_RCTL_LPE)
2043 vmolr |= E1000_VMOLR_LPE;
2044 if (adapter->num_rx_queues > 0)
2045 vmolr |= E1000_VMOLR_RSSE;
2046 wr32(E1000_VMOLR(j), vmolr);
2047 }
2048
26bc19ec
AD		 2049 for (i = 0; i < adapter->num_rx_queues; i++) {
2050 j = adapter->rx_ring[i].reg_idx;
2051 wr32(E1000_SRRCTL(j), srrctl);
2052 }
9d5c8243
AK		 2053
2054 wr32(E1000_RCTL, rctl);
2055}
2056
e1739522
AD		 2057/**
2058 * igb_rlpml_set - set maximum receive packet size
2059 * @adapter: board private structure
2060 *
2061 * Configure maximum receivable packet size.
2062 **/
2063static void igb_rlpml_set(struct igb_adapter *adapter)
2064{
2065 u32 max_frame_size = adapter->max_frame_size;
2066 struct e1000_hw *hw = &adapter->hw;
2067 u16 pf_id = adapter->vfs_allocated_count;
2068
2069 if (adapter->vlgrp)
2070 max_frame_size += VLAN_TAG_SIZE;
2071
2072 /* if vfs are enabled we set RLPML to the largest possible request
2073 * size and set the VMOLR RLPML to the size we need */
2074 if (pf_id) {
2075 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2076 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2077 }
2078
2079 wr32(E1000_RLPML, max_frame_size);
2080}
2081
2082/**
2083 * igb_configure_vt_default_pool - Configure VT default pool
2084 * @adapter: board private structure
2085 *
2086 * Configure the default pool
2087 **/
2088static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2089{
2090 struct e1000_hw *hw = &adapter->hw;
2091 u16 pf_id = adapter->vfs_allocated_count;
2092 u32 vtctl;
2093
2094 /* not in sr-iov mode - do nothing */
2095 if (!pf_id)
2096 return;
2097
2098 vtctl = rd32(E1000_VT_CTL);
2099 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2100 E1000_VT_CTL_DISABLE_DEF_POOL);
2101 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2102 wr32(E1000_VT_CTL, vtctl);
2103}
2104
9d5c8243
AK		 2105/**
2106 * igb_configure_rx - Configure receive Unit after Reset
2107 * @adapter: board private structure
2108 *
2109 * Configure the Rx unit of the MAC after a reset.
2110 **/
2111static void igb_configure_rx(struct igb_adapter *adapter)
2112{
2113 u64 rdba;
2114 struct e1000_hw *hw = &adapter->hw;
2115 u32 rctl, rxcsum;
2116 u32 rxdctl;
9107584e 2117 int i;
9d5c8243
AK		 2118
2119 /* disable receives while setting up the descriptors */
2120 rctl = rd32(E1000_RCTL);
2121 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2122 wrfl();
2123 mdelay(10);
2124
2125 if (adapter->itr_setting > 3)
6eb5a7f1 2126 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 2127
2128 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2129 * the Base and Length of the Rx Descriptor Ring */
2130 for (i = 0; i < adapter->num_rx_queues; i++) {
73cd78f1 2131 struct igb_ring *ring = &adapter->rx_ring[i];
9107584e 2132 int j = ring->reg_idx;
9d5c8243 2133 rdba = ring->dma;
26bc19ec 2134 wr32(E1000_RDBAL(j),
73cd78f1 2135 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 2136 wr32(E1000_RDBAH(j), rdba >> 32);
2137 wr32(E1000_RDLEN(j),
73cd78f1 2138 ring->count * sizeof(union e1000_adv_rx_desc));
9d5c8243 2139
26bc19ec
AD		 2140 ring->head = E1000_RDH(j);
2141 ring->tail = E1000_RDT(j);
9d5c8243
AK		 2142 writel(0, hw->hw_addr + ring->tail);
2143 writel(0, hw->hw_addr + ring->head);
2144
26bc19ec 2145 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 2146 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2147 rxdctl &= 0xFFF00000;
2148 rxdctl |= IGB_RX_PTHRESH;
2149 rxdctl |= IGB_RX_HTHRESH << 8;
2150 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 2151 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 2152 }
2153
2154 if (adapter->num_rx_queues > 1) {
2155 u32 random[10];
2156 u32 mrqc;
2157 u32 j, shift;
2158 union e1000_reta {
2159 u32 dword;
2160 u8 bytes[4];
2161 } reta;
2162
2163 get_random_bytes(&random[0], 40);
2164
2d064c06
AD		 2165 if (hw->mac.type >= e1000_82576)
2166 shift = 0;
2167 else
2168 shift = 6;
9d5c8243
AK		 2169 for (j = 0; j < (32 * 4); j++) {
2170 reta.bytes[j & 3] =
26bc19ec 2171 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2172 if ((j & 3) == 3)
2173 writel(reta.dword,
2174 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2175 }
e1739522
AD		 2176 if (adapter->vfs_allocated_count)
2177 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2178 else
2179 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
9d5c8243
AK		 2180
2181 /* Fill out hash function seeds */
2182 for (j = 0; j < 10; j++)
2183 array_wr32(E1000_RSSRK(0), j, random[j]);
2184
2185 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2186 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2187 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2188 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2189 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2190 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2191 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2192 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2193
2194
2195 wr32(E1000_MRQC, mrqc);
2196
2197 /* Multiqueue and raw packet checksumming are mutually
2198 * exclusive. Note that this not the same as TCP/IP
2199 * checksumming, which works fine. */
2200 rxcsum = rd32(E1000_RXCSUM);
2201 rxcsum |= E1000_RXCSUM_PCSD;
2202 wr32(E1000_RXCSUM, rxcsum);
2203 } else {
e1739522
AD		 2204 /* Enable multi-queue for sr-iov */
2205 if (adapter->vfs_allocated_count)
2206 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
9d5c8243
AK		 2207 /* Enable Receive Checksum Offload for TCP and UDP */
2208 rxcsum = rd32(E1000_RXCSUM);
56fbbb4e
AD		 2209 if (adapter->rx_csum)
2210 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE;
2211 else
2212 rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE);
2213
9d5c8243
AK		 2214 wr32(E1000_RXCSUM, rxcsum);
2215 }
2216
e1739522
AD		 2217 /* Set the default pool for the PF's first queue */
2218 igb_configure_vt_default_pool(adapter);
2219
2220 igb_rlpml_set(adapter);
9d5c8243
AK		 2221
2222 /* Enable Receives */
2223 wr32(E1000_RCTL, rctl);
2224}
2225
2226/**
2227 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2228 * @tx_ring: Tx descriptor ring for a specific queue
2229 *
2230 * Free all transmit software resources
2231 **/
68fd9910 2232void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2233{
3b644cf6 2234 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2235
3b644cf6 2236 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2237
2238 vfree(tx_ring->buffer_info);
2239 tx_ring->buffer_info = NULL;
2240
2241 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2242
2243 tx_ring->desc = NULL;
2244}
2245
2246/**
2247 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2248 * @adapter: board private structure
2249 *
2250 * Free all transmit software resources
2251 **/
2252static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2253{
2254 int i;
2255
2256 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2257 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2258}
2259
2260static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2261 struct igb_buffer *buffer_info)
2262{
2263 if (buffer_info->dma) {
2264 pci_unmap_page(adapter->pdev,
2265 buffer_info->dma,
2266 buffer_info->length,
2267 PCI_DMA_TODEVICE);
2268 buffer_info->dma = 0;
2269 }
2270 if (buffer_info->skb) {
2271 dev_kfree_skb_any(buffer_info->skb);
2272 buffer_info->skb = NULL;
2273 }
2274 buffer_info->time_stamp = 0;
73cd78f1 2275 buffer_info->next_to_watch = 0;
9d5c8243
AK		 2276 /* buffer_info must be completely set up in the transmit path */
2277}
2278
2279/**
2280 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2281 * @tx_ring: ring to be cleaned
2282 **/
3b644cf6 2283static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2284{
3b644cf6 2285 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2286 struct igb_buffer *buffer_info;
2287 unsigned long size;
2288 unsigned int i;
2289
2290 if (!tx_ring->buffer_info)
2291 return;
2292 /* Free all the Tx ring sk_buffs */
2293
2294 for (i = 0; i < tx_ring->count; i++) {
2295 buffer_info = &tx_ring->buffer_info[i];
2296 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2297 }
2298
2299 size = sizeof(struct igb_buffer) * tx_ring->count;
2300 memset(tx_ring->buffer_info, 0, size);
2301
2302 /* Zero out the descriptor ring */
2303
2304 memset(tx_ring->desc, 0, tx_ring->size);
2305
2306 tx_ring->next_to_use = 0;
2307 tx_ring->next_to_clean = 0;
2308
2309 writel(0, adapter->hw.hw_addr + tx_ring->head);
2310 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2311}
2312
2313/**
2314 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2315 * @adapter: board private structure
2316 **/
2317static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2318{
2319 int i;
2320
2321 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2322 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2323}
2324
2325/**
2326 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2327 * @rx_ring: ring to clean the resources from
2328 *
2329 * Free all receive software resources
2330 **/
68fd9910 2331void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2332{
3b644cf6 2333 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2334
3b644cf6 2335 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2336
2337 vfree(rx_ring->buffer_info);
2338 rx_ring->buffer_info = NULL;
2339
2340 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2341
2342 rx_ring->desc = NULL;
2343}
2344
2345/**
2346 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2347 * @adapter: board private structure
2348 *
2349 * Free all receive software resources
2350 **/
2351static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2352{
2353 int i;
2354
2355 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2356 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2357}
2358
2359/**
2360 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2361 * @rx_ring: ring to free buffers from
2362 **/
3b644cf6 2363static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2364{
3b644cf6 2365 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2366 struct igb_buffer *buffer_info;
2367 struct pci_dev *pdev = adapter->pdev;
2368 unsigned long size;
2369 unsigned int i;
2370
2371 if (!rx_ring->buffer_info)
2372 return;
2373 /* Free all the Rx ring sk_buffs */
2374 for (i = 0; i < rx_ring->count; i++) {
2375 buffer_info = &rx_ring->buffer_info[i];
2376 if (buffer_info->dma) {
2377 if (adapter->rx_ps_hdr_size)
2378 pci_unmap_single(pdev, buffer_info->dma,
2379 adapter->rx_ps_hdr_size,
2380 PCI_DMA_FROMDEVICE);
2381 else
2382 pci_unmap_single(pdev, buffer_info->dma,
2383 adapter->rx_buffer_len,
2384 PCI_DMA_FROMDEVICE);
2385 buffer_info->dma = 0;
2386 }
2387
2388 if (buffer_info->skb) {
2389 dev_kfree_skb(buffer_info->skb);
2390 buffer_info->skb = NULL;
2391 }
2392 if (buffer_info->page) {
bf36c1a0
AD		 2393 if (buffer_info->page_dma)
2394 pci_unmap_page(pdev, buffer_info->page_dma,
2395 PAGE_SIZE / 2,
2396 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2397 put_page(buffer_info->page);
2398 buffer_info->page = NULL;
2399 buffer_info->page_dma = 0;
bf36c1a0 2400 buffer_info->page_offset = 0;
9d5c8243
AK		 2401 }
2402 }
2403
9d5c8243
AK		 2404 size = sizeof(struct igb_buffer) * rx_ring->count;
2405 memset(rx_ring->buffer_info, 0, size);
2406
2407 /* Zero out the descriptor ring */
2408 memset(rx_ring->desc, 0, rx_ring->size);
2409
2410 rx_ring->next_to_clean = 0;
2411 rx_ring->next_to_use = 0;
2412
2413 writel(0, adapter->hw.hw_addr + rx_ring->head);
2414 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2415}
2416
2417/**
2418 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2419 * @adapter: board private structure
2420 **/
2421static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2422{
2423 int i;
2424
2425 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2426 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2427}
2428
2429/**
2430 * igb_set_mac - Change the Ethernet Address of the NIC
2431 * @netdev: network interface device structure
2432 * @p: pointer to an address structure
2433 *
2434 * Returns 0 on success, negative on failure
2435 **/
2436static int igb_set_mac(struct net_device *netdev, void *p)
2437{
2438 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2439 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2440 struct sockaddr *addr = p;
2441
2442 if (!is_valid_ether_addr(addr->sa_data))
2443 return -EADDRNOTAVAIL;
2444
2445 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2446 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2447
28b0759c 2448 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
9d5c8243 2449
e1739522
AD		 2450 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2451
9d5c8243
AK		 2452 return 0;
2453}
2454
2455/**
2456 * igb_set_multi - Multicast and Promiscuous mode set
2457 * @netdev: network interface device structure
2458 *
2459 * The set_multi entry point is called whenever the multicast address
2460 * list or the network interface flags are updated. This routine is
2461 * responsible for configuring the hardware for proper multicast,
2462 * promiscuous mode, and all-multi behavior.
2463 **/
2464static void igb_set_multi(struct net_device *netdev)
2465{
2466 struct igb_adapter *adapter = netdev_priv(netdev);
2467 struct e1000_hw *hw = &adapter->hw;
2468 struct e1000_mac_info *mac = &hw->mac;
2469 struct dev_mc_list *mc_ptr;
2470 u8 *mta_list;
2471 u32 rctl;
2472 int i;
2473
2474 /* Check for Promiscuous and All Multicast modes */
2475
2476 rctl = rd32(E1000_RCTL);
2477
746b9f02 2478 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2479 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2480 rctl &= ~E1000_RCTL_VFE;
2481 } else {
2482 if (netdev->flags & IFF_ALLMULTI) {
2483 rctl |= E1000_RCTL_MPE;
2484 rctl &= ~E1000_RCTL_UPE;
2485 } else
2486 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2487 rctl |= E1000_RCTL_VFE;
746b9f02 2488 }
9d5c8243
AK		 2489 wr32(E1000_RCTL, rctl);
2490
2491 if (!netdev->mc_count) {
2492 /* nothing to program, so clear mc list */
8a900862
AD		 2493 igb_update_mc_addr_list(hw, NULL, 0, 1,
2494 mac->rar_entry_count);
9d5c8243
AK		 2495 return;
2496 }
2497
2498 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2499 if (!mta_list)
2500 return;
2501
2502 /* The shared function expects a packed array of only addresses. */
2503 mc_ptr = netdev->mc_list;
2504
2505 for (i = 0; i < netdev->mc_count; i++) {
2506 if (!mc_ptr)
2507 break;
2508 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2509 mc_ptr = mc_ptr->next;
2510 }
e1739522
AD		 2511 igb_update_mc_addr_list(hw, mta_list, i,
2512 adapter->vfs_allocated_count + 1,
2513 mac->rar_entry_count);
2514
2515 igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
4ae196df
AD		 2516 igb_restore_vf_multicasts(adapter);
2517
9d5c8243
AK		 2518 kfree(mta_list);
2519}
2520
2521/* Need to wait a few seconds after link up to get diagnostic information from
2522 * the phy */
2523static void igb_update_phy_info(unsigned long data)
2524{
2525 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2526 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2527}
2528
4d6b725e
AD		 2529/**
2530 * igb_has_link - check shared code for link and determine up/down
2531 * @adapter: pointer to driver private info
2532 **/
2533static bool igb_has_link(struct igb_adapter *adapter)
2534{
2535 struct e1000_hw *hw = &adapter->hw;
2536 bool link_active = false;
2537 s32 ret_val = 0;
2538
2539 /* get_link_status is set on LSC (link status) interrupt or
2540 * rx sequence error interrupt. get_link_status will stay
2541 * false until the e1000_check_for_link establishes link
2542 * for copper adapters ONLY
2543 */
2544 switch (hw->phy.media_type) {
2545 case e1000_media_type_copper:
2546 if (hw->mac.get_link_status) {
2547 ret_val = hw->mac.ops.check_for_link(hw);
2548 link_active = !hw->mac.get_link_status;
2549 } else {
2550 link_active = true;
2551 }
2552 break;
2553 case e1000_media_type_fiber:
2554 ret_val = hw->mac.ops.check_for_link(hw);
2555 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2556 break;
2557 case e1000_media_type_internal_serdes:
2558 ret_val = hw->mac.ops.check_for_link(hw);
2559 link_active = hw->mac.serdes_has_link;
2560 break;
2561 default:
2562 case e1000_media_type_unknown:
2563 break;
2564 }
2565
2566 return link_active;
2567}
2568
9d5c8243
AK		 2569/**
2570 * igb_watchdog - Timer Call-back
2571 * @data: pointer to adapter cast into an unsigned long
2572 **/
2573static void igb_watchdog(unsigned long data)
2574{
2575 struct igb_adapter *adapter = (struct igb_adapter *)data;
2576 /* Do the rest outside of interrupt context */
2577 schedule_work(&adapter->watchdog_task);
2578}
2579
2580static void igb_watchdog_task(struct work_struct *work)
2581{
2582 struct igb_adapter *adapter = container_of(work,
2583 struct igb_adapter, watchdog_task);
2584 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2585 struct net_device *netdev = adapter->netdev;
2586 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2587 u32 link;
7a6ea550 2588 u32 eics = 0;
7a6ea550 2589 int i;
9d5c8243 2590
4d6b725e
AD		 2591 link = igb_has_link(adapter);
2592 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2593 goto link_up;
2594
9d5c8243
AK		 2595 if (link) {
2596 if (!netif_carrier_ok(netdev)) {
2597 u32 ctrl;
2598 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2599 &adapter->link_speed,
2600 &adapter->link_duplex);
2601
2602 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2603 /* Links status message must follow this format */
2604 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2605 "Flow Control: %s\n",
527d47c1 2606 netdev->name,
9d5c8243
AK		 2607 adapter->link_speed,
2608 adapter->link_duplex == FULL_DUPLEX ?
2609 "Full Duplex" : "Half Duplex",
2610 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2611 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2612 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2613 E1000_CTRL_TFCE) ? "TX" : "None")));
2614
2615 /* tweak tx_queue_len according to speed/duplex and
2616 * adjust the timeout factor */
2617 netdev->tx_queue_len = adapter->tx_queue_len;
2618 adapter->tx_timeout_factor = 1;
2619 switch (adapter->link_speed) {
2620 case SPEED_10:
2621 netdev->tx_queue_len = 10;
2622 adapter->tx_timeout_factor = 14;
2623 break;
2624 case SPEED_100:
2625 netdev->tx_queue_len = 100;
2626 /* maybe add some timeout factor ? */
2627 break;
2628 }
2629
2630 netif_carrier_on(netdev);
fd2ea0a7 2631 netif_tx_wake_all_queues(netdev);
9d5c8243 2632
4ae196df
AD		 2633 igb_ping_all_vfs(adapter);
2634
4b1a9877 2635 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2636 if (!test_bit(__IGB_DOWN, &adapter->state))
2637 mod_timer(&adapter->phy_info_timer,
2638 round_jiffies(jiffies + 2 * HZ));
2639 }
2640 } else {
2641 if (netif_carrier_ok(netdev)) {
2642 adapter->link_speed = 0;
2643 adapter->link_duplex = 0;
527d47c1
AD		 2644 /* Links status message must follow this format */
2645 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2646 netdev->name);
9d5c8243 2647 netif_carrier_off(netdev);
fd2ea0a7 2648 netif_tx_stop_all_queues(netdev);
4b1a9877 2649
4ae196df
AD		 2650 igb_ping_all_vfs(adapter);
2651
4b1a9877 2652 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2653 if (!test_bit(__IGB_DOWN, &adapter->state))
2654 mod_timer(&adapter->phy_info_timer,
2655 round_jiffies(jiffies + 2 * HZ));
2656 }
2657 }
2658
2659link_up:
2660 igb_update_stats(adapter);
2661
4b1a9877 2662 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2663 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2664 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2665 adapter->colc_old = adapter->stats.colc;
2666
2667 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2668 adapter->gorc_old = adapter->stats.gorc;
2669 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2670 adapter->gotc_old = adapter->stats.gotc;
2671
2672 igb_update_adaptive(&adapter->hw);
2673
2674 if (!netif_carrier_ok(netdev)) {
2675 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2676 /* We've lost link, so the controller stops DMA,
2677 * but we've got queued Tx work that's never going
2678 * to get done, so reset controller to flush Tx.
2679 * (Do the reset outside of interrupt context). */
2680 adapter->tx_timeout_count++;
2681 schedule_work(&adapter->reset_task);
2682 }
2683 }
2684
2685 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2686 if (adapter->msix_entries) {
2687 for (i = 0; i < adapter->num_rx_queues; i++)
2688 eics |= adapter->rx_ring[i].eims_value;
2689 wr32(E1000_EICS, eics);
2690 } else {
2691 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2692 }
9d5c8243
AK		 2693
2694 /* Force detection of hung controller every watchdog period */
2695 tx_ring->detect_tx_hung = true;
2696
2697 /* Reset the timer */
2698 if (!test_bit(__IGB_DOWN, &adapter->state))
2699 mod_timer(&adapter->watchdog_timer,
2700 round_jiffies(jiffies + 2 * HZ));
2701}
2702
2703enum latency_range {
2704 lowest_latency = 0,
2705 low_latency = 1,
2706 bulk_latency = 2,
2707 latency_invalid = 255
2708};
2709
2710
6eb5a7f1
AD		 2711/**
2712 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2713 *
2714 * Stores a new ITR value based on strictly on packet size. This
2715 * algorithm is less sophisticated than that used in igb_update_itr,
2716 * due to the difficulty of synchronizing statistics across multiple
2717 * receive rings. The divisors and thresholds used by this fuction
2718 * were determined based on theoretical maximum wire speed and testing
2719 * data, in order to minimize response time while increasing bulk
2720 * throughput.
2721 * This functionality is controlled by the InterruptThrottleRate module
2722 * parameter (see igb_param.c)
2723 * NOTE: This function is called only when operating in a multiqueue
2724 * receive environment.
2725 * @rx_ring: pointer to ring
2726 **/
2727static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2728{
6eb5a7f1
AD		 2729 int new_val = rx_ring->itr_val;
2730 int avg_wire_size = 0;
2731 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2732
6eb5a7f1
AD		 2733 if (!rx_ring->total_packets)
2734 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2735
6eb5a7f1
AD		 2736 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2737 * ints/sec - ITR timer value of 120 ticks.
2738 */
2739 if (adapter->link_speed != SPEED_1000) {
2740 new_val = 120;
2741 goto set_itr_val;
9d5c8243 2742 }
6eb5a7f1 2743 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2744
6eb5a7f1
AD		 2745 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2746 avg_wire_size += 24;
2747
2748 /* Don't starve jumbo frames */
2749 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2750
6eb5a7f1
AD		 2751 /* Give a little boost to mid-size frames */
2752 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2753 new_val = avg_wire_size / 3;
2754 else
2755 new_val = avg_wire_size / 2;
9d5c8243 2756
6eb5a7f1 2757set_itr_val:
9d5c8243
AK		 2758 if (new_val != rx_ring->itr_val) {
2759 rx_ring->itr_val = new_val;
6eb5a7f1 2760 rx_ring->set_itr = 1;
9d5c8243 2761 }
6eb5a7f1
AD		 2762clear_counts:
2763 rx_ring->total_bytes = 0;
2764 rx_ring->total_packets = 0;
9d5c8243
AK		 2765}
2766
2767/**
2768 * igb_update_itr - update the dynamic ITR value based on statistics
2769 * Stores a new ITR value based on packets and byte
2770 * counts during the last interrupt. The advantage of per interrupt
2771 * computation is faster updates and more accurate ITR for the current
2772 * traffic pattern. Constants in this function were computed
2773 * based on theoretical maximum wire speed and thresholds were set based
2774 * on testing data as well as attempting to minimize response time
2775 * while increasing bulk throughput.
2776 * this functionality is controlled by the InterruptThrottleRate module
2777 * parameter (see igb_param.c)
2778 * NOTE: These calculations are only valid when operating in a single-
2779 * queue environment.
2780 * @adapter: pointer to adapter
2781 * @itr_setting: current adapter->itr
2782 * @packets: the number of packets during this measurement interval
2783 * @bytes: the number of bytes during this measurement interval
2784 **/
2785static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2786 int packets, int bytes)
2787{
2788 unsigned int retval = itr_setting;
2789
2790 if (packets == 0)
2791 goto update_itr_done;
2792
2793 switch (itr_setting) {
2794 case lowest_latency:
2795 /* handle TSO and jumbo frames */
2796 if (bytes/packets > 8000)
2797 retval = bulk_latency;
2798 else if ((packets < 5) && (bytes > 512))
2799 retval = low_latency;
2800 break;
2801 case low_latency: /* 50 usec aka 20000 ints/s */
2802 if (bytes > 10000) {
2803 /* this if handles the TSO accounting */
2804 if (bytes/packets > 8000) {
2805 retval = bulk_latency;
2806 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2807 retval = bulk_latency;
2808 } else if ((packets > 35)) {
2809 retval = lowest_latency;
2810 }
2811 } else if (bytes/packets > 2000) {
2812 retval = bulk_latency;
2813 } else if (packets <= 2 && bytes < 512) {
2814 retval = lowest_latency;
2815 }
2816 break;
2817 case bulk_latency: /* 250 usec aka 4000 ints/s */
2818 if (bytes > 25000) {
2819 if (packets > 35)
2820 retval = low_latency;
1e5c3d21 2821 } else if (bytes < 1500) {
9d5c8243
AK		 2822 retval = low_latency;
2823 }
2824 break;
2825 }
2826
2827update_itr_done:
2828 return retval;
2829}
2830
6eb5a7f1 2831static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2832{
2833 u16 current_itr;
2834 u32 new_itr = adapter->itr;
2835
2836 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2837 if (adapter->link_speed != SPEED_1000) {
2838 current_itr = 0;
2839 new_itr = 4000;
2840 goto set_itr_now;
2841 }
2842
2843 adapter->rx_itr = igb_update_itr(adapter,
2844 adapter->rx_itr,
2845 adapter->rx_ring->total_packets,
2846 adapter->rx_ring->total_bytes);
9d5c8243 2847
6eb5a7f1 2848 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2849 adapter->tx_itr = igb_update_itr(adapter,
2850 adapter->tx_itr,
2851 adapter->tx_ring->total_packets,
2852 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2853 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2854 } else {
2855 current_itr = adapter->rx_itr;
2856 }
2857
6eb5a7f1 2858 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 2859 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 2860 current_itr = low_latency;
2861
9d5c8243
AK		 2862 switch (current_itr) {
2863 /* counts and packets in update_itr are dependent on these numbers */
2864 case lowest_latency:
2865 new_itr = 70000;
2866 break;
2867 case low_latency:
2868 new_itr = 20000; /* aka hwitr = ~200 */
2869 break;
2870 case bulk_latency:
2871 new_itr = 4000;
2872 break;
2873 default:
2874 break;
2875 }
2876
2877set_itr_now:
6eb5a7f1
AD		 2878 adapter->rx_ring->total_bytes = 0;
2879 adapter->rx_ring->total_packets = 0;
2880 if (adapter->rx_ring->buddy) {
2881 adapter->rx_ring->buddy->total_bytes = 0;
2882 adapter->rx_ring->buddy->total_packets = 0;
2883 }
2884
9d5c8243
AK		 2885 if (new_itr != adapter->itr) {
2886 /* this attempts to bias the interrupt rate towards Bulk
2887 * by adding intermediate steps when interrupt rate is
2888 * increasing */
2889 new_itr = new_itr > adapter->itr ?
2890 min(adapter->itr + (new_itr >> 2), new_itr) :
2891 new_itr;
2892 /* Don't write the value here; it resets the adapter's
2893 * internal timer, and causes us to delay far longer than
2894 * we should between interrupts. Instead, we write the ITR
2895 * value at the beginning of the next interrupt so the timing
2896 * ends up being correct.
2897 */
2898 adapter->itr = new_itr;
6eb5a7f1
AD		 2899 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2900 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2901 }
2902
2903 return;
2904}
2905
2906
2907#define IGB_TX_FLAGS_CSUM 0x00000001
2908#define IGB_TX_FLAGS_VLAN 0x00000002
2909#define IGB_TX_FLAGS_TSO 0x00000004
2910#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 2911#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 2912#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2913#define IGB_TX_FLAGS_VLAN_SHIFT 16
2914
2915static inline int igb_tso_adv(struct igb_adapter *adapter,
2916 struct igb_ring *tx_ring,
2917 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2918{
2919 struct e1000_adv_tx_context_desc *context_desc;
2920 unsigned int i;
2921 int err;
2922 struct igb_buffer *buffer_info;
2923 u32 info = 0, tu_cmd = 0;
2924 u32 mss_l4len_idx, l4len;
2925 *hdr_len = 0;
2926
2927 if (skb_header_cloned(skb)) {
2928 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2929 if (err)
2930 return err;
2931 }
2932
2933 l4len = tcp_hdrlen(skb);
2934 *hdr_len += l4len;
2935
2936 if (skb->protocol == htons(ETH_P_IP)) {
2937 struct iphdr *iph = ip_hdr(skb);
2938 iph->tot_len = 0;
2939 iph->check = 0;
2940 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2941 iph->daddr, 0,
2942 IPPROTO_TCP,
2943 0);
2944 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2945 ipv6_hdr(skb)->payload_len = 0;
2946 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2947 &ipv6_hdr(skb)->daddr,
2948 0, IPPROTO_TCP, 0);
2949 }
2950
2951 i = tx_ring->next_to_use;
2952
2953 buffer_info = &tx_ring->buffer_info[i];
2954 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2955 /* VLAN MACLEN IPLEN */
2956 if (tx_flags & IGB_TX_FLAGS_VLAN)
2957 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2958 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2959 *hdr_len += skb_network_offset(skb);
2960 info |= skb_network_header_len(skb);
2961 *hdr_len += skb_network_header_len(skb);
2962 context_desc->vlan_macip_lens = cpu_to_le32(info);
2963
2964 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2965 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2966
2967 if (skb->protocol == htons(ETH_P_IP))
2968 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2969 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2970
2971 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2972
2973 /* MSS L4LEN IDX */
2974 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2975 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2976
73cd78f1 2977 /* For 82575, context index must be unique per ring. */
7dfc16fa
AD		 2978 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2979 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2980
2981 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2982 context_desc->seqnum_seed = 0;
2983
2984 buffer_info->time_stamp = jiffies;
0e014cb1 2985 buffer_info->next_to_watch = i;
9d5c8243
AK		 2986 buffer_info->dma = 0;
2987 i++;
2988 if (i == tx_ring->count)
2989 i = 0;
2990
2991 tx_ring->next_to_use = i;
2992
2993 return true;
2994}
2995
2996static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2997 struct igb_ring *tx_ring,
2998 struct sk_buff *skb, u32 tx_flags)
2999{
3000 struct e1000_adv_tx_context_desc *context_desc;
3001 unsigned int i;
3002 struct igb_buffer *buffer_info;
3003 u32 info = 0, tu_cmd = 0;
3004
3005 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3006 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3007 i = tx_ring->next_to_use;
3008 buffer_info = &tx_ring->buffer_info[i];
3009 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3010
3011 if (tx_flags & IGB_TX_FLAGS_VLAN)
3012 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3013 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3014 if (skb->ip_summed == CHECKSUM_PARTIAL)
3015 info |= skb_network_header_len(skb);
3016
3017 context_desc->vlan_macip_lens = cpu_to_le32(info);
3018
3019 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3020
3021 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3 3022 switch (skb->protocol) {
09640e63 3023 case cpu_to_be16(ETH_P_IP):
9d5c8243 3024 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3025 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3026 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3027 break;
09640e63 3028 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3029 /* XXX what about other V6 headers?? */
3030 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3031 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3032 break;
3033 default:
3034 if (unlikely(net_ratelimit()))
3035 dev_warn(&adapter->pdev->dev,
3036 "partial checksum but proto=%x!\n",
3037 skb->protocol);
3038 break;
3039 }
9d5c8243
AK		 3040 }
3041
3042 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3043 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 3044 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3045 context_desc->mss_l4len_idx =
3046 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 3047 else
3048 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 3049
3050 buffer_info->time_stamp = jiffies;
0e014cb1 3051 buffer_info->next_to_watch = i;
9d5c8243
AK		 3052 buffer_info->dma = 0;
3053
3054 i++;
3055 if (i == tx_ring->count)
3056 i = 0;
3057 tx_ring->next_to_use = i;
3058
3059 return true;
3060 }
9d5c8243
AK		 3061 return false;
3062}
3063
3064#define IGB_MAX_TXD_PWR 16
3065#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3066
3067static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 3068 struct igb_ring *tx_ring, struct sk_buff *skb,
3069 unsigned int first)
9d5c8243
AK		 3070{
3071 struct igb_buffer *buffer_info;
3072 unsigned int len = skb_headlen(skb);
3073 unsigned int count = 0, i;
3074 unsigned int f;
3075
3076 i = tx_ring->next_to_use;
3077
3078 buffer_info = &tx_ring->buffer_info[i];
3079 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3080 buffer_info->length = len;
3081 /* set time_stamp *before* dma to help avoid a possible race */
3082 buffer_info->time_stamp = jiffies;
0e014cb1 3083 buffer_info->next_to_watch = i;
9d5c8243
AK		 3084 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
3085 PCI_DMA_TODEVICE);
3086 count++;
3087 i++;
3088 if (i == tx_ring->count)
3089 i = 0;
3090
3091 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3092 struct skb_frag_struct *frag;
3093
3094 frag = &skb_shinfo(skb)->frags[f];
3095 len = frag->size;
3096
3097 buffer_info = &tx_ring->buffer_info[i];
3098 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3099 buffer_info->length = len;
3100 buffer_info->time_stamp = jiffies;
0e014cb1 3101 buffer_info->next_to_watch = i;
9d5c8243
AK		 3102 buffer_info->dma = pci_map_page(adapter->pdev,
3103 frag->page,
3104 frag->page_offset,
3105 len,
3106 PCI_DMA_TODEVICE);
3107
3108 count++;
3109 i++;
3110 if (i == tx_ring->count)
3111 i = 0;
3112 }
3113
0e014cb1 3114 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
9d5c8243 3115 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3116 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243
AK		 3117
3118 return count;
3119}
3120
3121static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3122 struct igb_ring *tx_ring,
3123 int tx_flags, int count, u32 paylen,
3124 u8 hdr_len)
3125{
3126 union e1000_adv_tx_desc *tx_desc = NULL;
3127 struct igb_buffer *buffer_info;
3128 u32 olinfo_status = 0, cmd_type_len;
3129 unsigned int i;
3130
3131 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3132 E1000_ADVTXD_DCMD_DEXT);
3133
3134 if (tx_flags & IGB_TX_FLAGS_VLAN)
3135 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3136
33af6bcc
PO		 3137 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3138 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3139
9d5c8243
AK		 3140 if (tx_flags & IGB_TX_FLAGS_TSO) {
3141 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3142
3143 /* insert tcp checksum */
3144 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3145
3146 /* insert ip checksum */
3147 if (tx_flags & IGB_TX_FLAGS_IPV4)
3148 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3149
3150 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3151 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3152 }
3153
7dfc16fa
AD		 3154 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3155 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3156 IGB_TX_FLAGS_VLAN)))
661086df 3157 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 3158
3159 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3160
3161 i = tx_ring->next_to_use;
3162 while (count--) {
3163 buffer_info = &tx_ring->buffer_info[i];
3164 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3165 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3166 tx_desc->read.cmd_type_len =
3167 cpu_to_le32(cmd_type_len | buffer_info->length);
3168 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3169 i++;
3170 if (i == tx_ring->count)
3171 i = 0;
3172 }
3173
3174 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3175 /* Force memory writes to complete before letting h/w
3176 * know there are new descriptors to fetch. (Only
3177 * applicable for weak-ordered memory model archs,
3178 * such as IA-64). */
3179 wmb();
3180
3181 tx_ring->next_to_use = i;
3182 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3183 /* we need this if more than one processor can write to our tail
3184 * at a time, it syncronizes IO on IA64/Altix systems */
3185 mmiowb();
3186}
3187
3188static int __igb_maybe_stop_tx(struct net_device *netdev,
3189 struct igb_ring *tx_ring, int size)
3190{
3191 struct igb_adapter *adapter = netdev_priv(netdev);
3192
661086df 3193 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3194
9d5c8243
AK		 3195 /* Herbert's original patch had:
3196 * smp_mb__after_netif_stop_queue();
3197 * but since that doesn't exist yet, just open code it. */
3198 smp_mb();
3199
3200 /* We need to check again in a case another CPU has just
3201 * made room available. */
3202 if (IGB_DESC_UNUSED(tx_ring) < size)
3203 return -EBUSY;
3204
3205 /* A reprieve! */
661086df 3206 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3207 ++adapter->restart_queue;
3208 return 0;
3209}
3210
3211static int igb_maybe_stop_tx(struct net_device *netdev,
3212 struct igb_ring *tx_ring, int size)
3213{
3214 if (IGB_DESC_UNUSED(tx_ring) >= size)
3215 return 0;
3216 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3217}
3218
9d5c8243
AK		 3219static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3220 struct net_device *netdev,
3221 struct igb_ring *tx_ring)
3222{
3223 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3224 unsigned int first;
9d5c8243 3225 unsigned int tx_flags = 0;
9d5c8243
AK		 3226 u8 hdr_len = 0;
3227 int tso = 0;
33af6bcc 3228 union skb_shared_tx *shtx;
9d5c8243 3229
9d5c8243
AK		 3230 if (test_bit(__IGB_DOWN, &adapter->state)) {
3231 dev_kfree_skb_any(skb);
3232 return NETDEV_TX_OK;
3233 }
3234
3235 if (skb->len <= 0) {
3236 dev_kfree_skb_any(skb);
3237 return NETDEV_TX_OK;
3238 }
3239
9d5c8243
AK		 3240 /* need: 1 descriptor per page,
3241 * + 2 desc gap to keep tail from touching head,
3242 * + 1 desc for skb->data,
3243 * + 1 desc for context descriptor,
3244 * otherwise try next time */
3245 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3246 /* this is a hard error */
9d5c8243
AK		 3247 return NETDEV_TX_BUSY;
3248 }
33af6bcc
PO		 3249
3250 /*
3251 * TODO: check that there currently is no other packet with
3252 * time stamping in the queue
3253 *
3254 * When doing time stamping, keep the connection to the socket
3255 * a while longer: it is still needed by skb_hwtstamp_tx(),
3256 * called either in igb_tx_hwtstamp() or by our caller when
3257 * doing software time stamping.
3258 */
3259 shtx = skb_tx(skb);
3260 if (unlikely(shtx->hardware)) {
3261 shtx->in_progress = 1;
3262 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3263 }
9d5c8243
AK		 3264
3265 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3266 tx_flags |= IGB_TX_FLAGS_VLAN;
3267 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3268 }
3269
661086df
PWJ		 3270 if (skb->protocol == htons(ETH_P_IP))
3271 tx_flags |= IGB_TX_FLAGS_IPV4;
3272
0e014cb1 3273 first = tx_ring->next_to_use;
9d5c8243
AK		 3274 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3275 &hdr_len) : 0;
3276
3277 if (tso < 0) {
3278 dev_kfree_skb_any(skb);
9d5c8243
AK		 3279 return NETDEV_TX_OK;
3280 }
3281
3282 if (tso)
3283 tx_flags |= IGB_TX_FLAGS_TSO;
bc1cbd34
AD		 3284 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3285 (skb->ip_summed == CHECKSUM_PARTIAL))
3286 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3287
9d5c8243 3288 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
0e014cb1 3289 igb_tx_map_adv(adapter, tx_ring, skb, first),
9d5c8243
AK		 3290 skb->len, hdr_len);
3291
3292 netdev->trans_start = jiffies;
3293
3294 /* Make sure there is space in the ring for the next send. */
3295 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3296
9d5c8243
AK		 3297 return NETDEV_TX_OK;
3298}
3299
3300static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3301{
3302 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3303 struct igb_ring *tx_ring;
3304
661086df 3305 int r_idx = 0;
1bfaf07b 3306 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3307 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3308
3309 /* This goes back to the question of how to logically map a tx queue
3310 * to a flow. Right now, performance is impacted slightly negatively
3311 * if using multiple tx queues. If the stack breaks away from a
3312 * single qdisc implementation, we can look at this again. */
3313 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3314}
3315
3316/**
3317 * igb_tx_timeout - Respond to a Tx Hang
3318 * @netdev: network interface device structure
3319 **/
3320static void igb_tx_timeout(struct net_device *netdev)
3321{
3322 struct igb_adapter *adapter = netdev_priv(netdev);
3323 struct e1000_hw *hw = &adapter->hw;
3324
3325 /* Do the reset outside of interrupt context */
3326 adapter->tx_timeout_count++;
3327 schedule_work(&adapter->reset_task);
265de409
AD		 3328 wr32(E1000_EICS,
3329 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3330}
3331
3332static void igb_reset_task(struct work_struct *work)
3333{
3334 struct igb_adapter *adapter;
3335 adapter = container_of(work, struct igb_adapter, reset_task);
3336
3337 igb_reinit_locked(adapter);
3338}
3339
3340/**
3341 * igb_get_stats - Get System Network Statistics
3342 * @netdev: network interface device structure
3343 *
3344 * Returns the address of the device statistics structure.
3345 * The statistics are actually updated from the timer callback.
3346 **/
73cd78f1 3347static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243
AK		 3348{
3349 struct igb_adapter *adapter = netdev_priv(netdev);
3350
3351 /* only return the current stats */
3352 return &adapter->net_stats;
3353}
3354
3355/**
3356 * igb_change_mtu - Change the Maximum Transfer Unit
3357 * @netdev: network interface device structure
3358 * @new_mtu: new value for maximum frame size
3359 *
3360 * Returns 0 on success, negative on failure
3361 **/
3362static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3363{
3364 struct igb_adapter *adapter = netdev_priv(netdev);
3365 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3366
3367 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3368 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3369 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3370 return -EINVAL;
3371 }
3372
9d5c8243
AK		 3373 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3374 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3375 return -EINVAL;
3376 }
3377
3378 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3379 msleep(1);
73cd78f1 3380
9d5c8243
AK		 3381 /* igb_down has a dependency on max_frame_size */
3382 adapter->max_frame_size = max_frame;
3383 if (netif_running(netdev))
3384 igb_down(adapter);
3385
3386 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3387 * means we reserve 2 more, this pushes us to allocate from the next
3388 * larger slab size.
3389 * i.e. RXBUFFER_2048 --> size-4096 slab
3390 */
3391
3392 if (max_frame <= IGB_RXBUFFER_256)
3393 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3394 else if (max_frame <= IGB_RXBUFFER_512)
3395 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3396 else if (max_frame <= IGB_RXBUFFER_1024)
3397 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3398 else if (max_frame <= IGB_RXBUFFER_2048)
3399 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3400 else
bf36c1a0
AD		 3401#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3402 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3403#else
3404 adapter->rx_buffer_len = PAGE_SIZE / 2;
3405#endif
e1739522
AD		 3406
3407 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3408 if (adapter->vfs_allocated_count &&
3409 (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3410 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3411
9d5c8243
AK		 3412 /* adjust allocation if LPE protects us, and we aren't using SBP */
3413 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3414 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3415 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3416
3417 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3418 netdev->mtu, new_mtu);
3419 netdev->mtu = new_mtu;
3420
3421 if (netif_running(netdev))
3422 igb_up(adapter);
3423 else
3424 igb_reset(adapter);
3425
3426 clear_bit(__IGB_RESETTING, &adapter->state);
3427
3428 return 0;
3429}
3430
3431/**
3432 * igb_update_stats - Update the board statistics counters
3433 * @adapter: board private structure
3434 **/
3435
3436void igb_update_stats(struct igb_adapter *adapter)
3437{
3438 struct e1000_hw *hw = &adapter->hw;
3439 struct pci_dev *pdev = adapter->pdev;
3440 u16 phy_tmp;
3441
3442#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3443
3444 /*
3445 * Prevent stats update while adapter is being reset, or if the pci
3446 * connection is down.
3447 */
3448 if (adapter->link_speed == 0)
3449 return;
3450 if (pci_channel_offline(pdev))
3451 return;
3452
3453 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3454 adapter->stats.gprc += rd32(E1000_GPRC);
3455 adapter->stats.gorc += rd32(E1000_GORCL);
3456 rd32(E1000_GORCH); /* clear GORCL */
3457 adapter->stats.bprc += rd32(E1000_BPRC);
3458 adapter->stats.mprc += rd32(E1000_MPRC);
3459 adapter->stats.roc += rd32(E1000_ROC);
3460
3461 adapter->stats.prc64 += rd32(E1000_PRC64);
3462 adapter->stats.prc127 += rd32(E1000_PRC127);
3463 adapter->stats.prc255 += rd32(E1000_PRC255);
3464 adapter->stats.prc511 += rd32(E1000_PRC511);
3465 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3466 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3467 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3468 adapter->stats.sec += rd32(E1000_SEC);
3469
3470 adapter->stats.mpc += rd32(E1000_MPC);
3471 adapter->stats.scc += rd32(E1000_SCC);
3472 adapter->stats.ecol += rd32(E1000_ECOL);
3473 adapter->stats.mcc += rd32(E1000_MCC);
3474 adapter->stats.latecol += rd32(E1000_LATECOL);
3475 adapter->stats.dc += rd32(E1000_DC);
3476 adapter->stats.rlec += rd32(E1000_RLEC);
3477 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3478 adapter->stats.xontxc += rd32(E1000_XONTXC);
3479 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3480 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3481 adapter->stats.fcruc += rd32(E1000_FCRUC);
3482 adapter->stats.gptc += rd32(E1000_GPTC);
3483 adapter->stats.gotc += rd32(E1000_GOTCL);
3484 rd32(E1000_GOTCH); /* clear GOTCL */
3485 adapter->stats.rnbc += rd32(E1000_RNBC);
3486 adapter->stats.ruc += rd32(E1000_RUC);
3487 adapter->stats.rfc += rd32(E1000_RFC);
3488 adapter->stats.rjc += rd32(E1000_RJC);
3489 adapter->stats.tor += rd32(E1000_TORH);
3490 adapter->stats.tot += rd32(E1000_TOTH);
3491 adapter->stats.tpr += rd32(E1000_TPR);
3492
3493 adapter->stats.ptc64 += rd32(E1000_PTC64);
3494 adapter->stats.ptc127 += rd32(E1000_PTC127);
3495 adapter->stats.ptc255 += rd32(E1000_PTC255);
3496 adapter->stats.ptc511 += rd32(E1000_PTC511);
3497 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3498 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3499
3500 adapter->stats.mptc += rd32(E1000_MPTC);
3501 adapter->stats.bptc += rd32(E1000_BPTC);
3502
3503 /* used for adaptive IFS */
3504
3505 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3506 adapter->stats.tpt += hw->mac.tx_packet_delta;
3507 hw->mac.collision_delta = rd32(E1000_COLC);
3508 adapter->stats.colc += hw->mac.collision_delta;
3509
3510 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3511 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3512 adapter->stats.tncrs += rd32(E1000_TNCRS);
3513 adapter->stats.tsctc += rd32(E1000_TSCTC);
3514 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3515
3516 adapter->stats.iac += rd32(E1000_IAC);
3517 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3518 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3519 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3520 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3521 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3522 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3523 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3524 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3525
3526 /* Fill out the OS statistics structure */
3527 adapter->net_stats.multicast = adapter->stats.mprc;
3528 adapter->net_stats.collisions = adapter->stats.colc;
3529
3530 /* Rx Errors */
3531
3532 /* RLEC on some newer hardware can be incorrect so build
3533 * our own version based on RUC and ROC */
3534 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3535 adapter->stats.crcerrs + adapter->stats.algnerrc +
3536 adapter->stats.ruc + adapter->stats.roc +
3537 adapter->stats.cexterr;
3538 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3539 adapter->stats.roc;
3540 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3541 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3542 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3543
3544 /* Tx Errors */
3545 adapter->net_stats.tx_errors = adapter->stats.ecol +
3546 adapter->stats.latecol;
3547 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3548 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3549 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3550
3551 /* Tx Dropped needs to be maintained elsewhere */
3552
3553 /* Phy Stats */
3554 if (hw->phy.media_type == e1000_media_type_copper) {
3555 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3556 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3557 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3558 adapter->phy_stats.idle_errors += phy_tmp;
3559 }
3560 }
3561
3562 /* Management Stats */
3563 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3564 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3565 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3566}
3567
9d5c8243
AK		 3568static irqreturn_t igb_msix_other(int irq, void *data)
3569{
3570 struct net_device *netdev = data;
3571 struct igb_adapter *adapter = netdev_priv(netdev);
3572 struct e1000_hw *hw = &adapter->hw;
844290e5 3573 u32 icr = rd32(E1000_ICR);
9d5c8243 3574
844290e5 3575 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3576
3577 if(icr & E1000_ICR_DOUTSYNC) {
3578 /* HW is reporting DMA is out of sync */
3579 adapter->stats.doosync++;
3580 }
eebbbdba 3581
4ae196df
AD		 3582 /* Check for a mailbox event */
3583 if (icr & E1000_ICR_VMMB)
3584 igb_msg_task(adapter);
3585
3586 if (icr & E1000_ICR_LSC) {
3587 hw->mac.get_link_status = 1;
3588 /* guard against interrupt when we're going down */
3589 if (!test_bit(__IGB_DOWN, &adapter->state))
3590 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3591 }
3592
3593 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
844290e5 3594 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3595
3596 return IRQ_HANDLED;
3597}
3598
3599static irqreturn_t igb_msix_tx(int irq, void *data)
3600{
3601 struct igb_ring *tx_ring = data;
3602 struct igb_adapter *adapter = tx_ring->adapter;
3603 struct e1000_hw *hw = &adapter->hw;
3604
421e02f0 3605#ifdef CONFIG_IGB_DCA
7dfc16fa 3606 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3607 igb_update_tx_dca(tx_ring);
3608#endif
73cd78f1 3609
9d5c8243
AK		 3610 tx_ring->total_bytes = 0;
3611 tx_ring->total_packets = 0;
661086df
PWJ		 3612
3613 /* auto mask will automatically reenable the interrupt when we write
3614 * EICS */
3b644cf6 3615 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3616 /* Ring was not completely cleaned, so fire another interrupt */
3617 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3618 else
9d5c8243 3619 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3620
9d5c8243
AK		 3621 return IRQ_HANDLED;
3622}
3623
6eb5a7f1
AD		 3624static void igb_write_itr(struct igb_ring *ring)
3625{
3626 struct e1000_hw *hw = &ring->adapter->hw;
3627 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3628 switch (hw->mac.type) {
3629 case e1000_82576:
73cd78f1 3630 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3631 0x80000000);
3632 break;
3633 default:
73cd78f1 3634 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3635 (ring->itr_val << 16));
3636 break;
3637 }
3638 ring->set_itr = 0;
3639 }
3640}
3641
9d5c8243
AK		 3642static irqreturn_t igb_msix_rx(int irq, void *data)
3643{
3644 struct igb_ring *rx_ring = data;
9d5c8243 3645
844290e5
PW		 3646 /* Write the ITR value calculated at the end of the
3647 * previous interrupt.
3648 */
9d5c8243 3649
6eb5a7f1 3650 igb_write_itr(rx_ring);
9d5c8243 3651
288379f0
BH		 3652 if (napi_schedule_prep(&rx_ring->napi))
3653 __napi_schedule(&rx_ring->napi);
844290e5 3654
421e02f0 3655#ifdef CONFIG_IGB_DCA
8d253320 3656 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3657 igb_update_rx_dca(rx_ring);
3658#endif
3659 return IRQ_HANDLED;
3660}
3661
421e02f0 3662#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3663static void igb_update_rx_dca(struct igb_ring *rx_ring)
3664{
3665 u32 dca_rxctrl;
3666 struct igb_adapter *adapter = rx_ring->adapter;
3667 struct e1000_hw *hw = &adapter->hw;
3668 int cpu = get_cpu();
26bc19ec 3669 int q = rx_ring->reg_idx;
fe4506b6
JC		 3670
3671 if (rx_ring->cpu != cpu) {
3672 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3673 if (hw->mac.type == e1000_82576) {
3674 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
92be7917 3675 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3676 E1000_DCA_RXCTRL_CPUID_SHIFT;
3677 } else {
3678 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 3679 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3680 }
fe4506b6
JC		 3681 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3682 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3683 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3684 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3685 rx_ring->cpu = cpu;
3686 }
3687 put_cpu();
3688}
3689
3690static void igb_update_tx_dca(struct igb_ring *tx_ring)
3691{
3692 u32 dca_txctrl;
3693 struct igb_adapter *adapter = tx_ring->adapter;
3694 struct e1000_hw *hw = &adapter->hw;
3695 int cpu = get_cpu();
26bc19ec 3696 int q = tx_ring->reg_idx;
fe4506b6
JC		 3697
3698 if (tx_ring->cpu != cpu) {
3699 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3700 if (hw->mac.type == e1000_82576) {
3701 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
92be7917 3702 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3703 E1000_DCA_TXCTRL_CPUID_SHIFT;
3704 } else {
3705 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
92be7917 3706 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3707 }
fe4506b6
JC		 3708 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3709 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3710 tx_ring->cpu = cpu;
3711 }
3712 put_cpu();
3713}
3714
3715static void igb_setup_dca(struct igb_adapter *adapter)
3716{
3717 int i;
3718
7dfc16fa 3719 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3720 return;
3721
3722 for (i = 0; i < adapter->num_tx_queues; i++) {
3723 adapter->tx_ring[i].cpu = -1;
3724 igb_update_tx_dca(&adapter->tx_ring[i]);
3725 }
3726 for (i = 0; i < adapter->num_rx_queues; i++) {
3727 adapter->rx_ring[i].cpu = -1;
3728 igb_update_rx_dca(&adapter->rx_ring[i]);
3729 }
3730}
3731
3732static int __igb_notify_dca(struct device *dev, void *data)
3733{
3734 struct net_device *netdev = dev_get_drvdata(dev);
3735 struct igb_adapter *adapter = netdev_priv(netdev);
3736 struct e1000_hw *hw = &adapter->hw;
3737 unsigned long event = *(unsigned long *)data;
3738
3739 switch (event) {
3740 case DCA_PROVIDER_ADD:
3741 /* if already enabled, don't do it again */
7dfc16fa 3742 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3743 break;
fe4506b6
JC		 3744 /* Always use CB2 mode, difference is masked
3745 * in the CB driver. */
cbd347ad 3746 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 3747 if (dca_add_requester(dev) == 0) {
bbd98fe4 3748 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3749 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3750 igb_setup_dca(adapter);
3751 break;
3752 }
3753 /* Fall Through since DCA is disabled. */
3754 case DCA_PROVIDER_REMOVE:
7dfc16fa 3755 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3756 /* without this a class_device is left
3757 * hanging around in the sysfs model */
3758 dca_remove_requester(dev);
3759 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3760 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 3761 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 3762 }
3763 break;
3764 }
bbd98fe4 3765
fe4506b6 3766 return 0;
9d5c8243
AK		 3767}
3768
fe4506b6
JC		 3769static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3770 void *p)
3771{
3772 int ret_val;
3773
3774 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3775 __igb_notify_dca);
3776
3777 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3778}
421e02f0 3779#endif /* CONFIG_IGB_DCA */
9d5c8243 3780
4ae196df
AD		 3781static void igb_ping_all_vfs(struct igb_adapter *adapter)
3782{
3783 struct e1000_hw *hw = &adapter->hw;
3784 u32 ping;
3785 int i;
3786
3787 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3788 ping = E1000_PF_CONTROL_MSG;
3789 if (adapter->vf_data[i].clear_to_send)
3790 ping |= E1000_VT_MSGTYPE_CTS;
3791 igb_write_mbx(hw, &ping, 1, i);
3792 }
3793}
3794
3795static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3796 u32 *msgbuf, u32 vf)
3797{
3798 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3799 u16 *hash_list = (u16 *)&msgbuf[1];
3800 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3801 int i;
3802
3803 /* only up to 30 hash values supported */
3804 if (n > 30)
3805 n = 30;
3806
3807 /* salt away the number of multi cast addresses assigned
3808 * to this VF for later use to restore when the PF multi cast
3809 * list changes
3810 */
3811 vf_data->num_vf_mc_hashes = n;
3812
3813 /* VFs are limited to using the MTA hash table for their multicast
3814 * addresses */
3815 for (i = 0; i < n; i++)
3816 vf_data->vf_mc_hashes[i] = hash_list[i];;
3817
3818 /* Flush and reset the mta with the new values */
3819 igb_set_multi(adapter->netdev);
3820
3821 return 0;
3822}
3823
3824static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3825{
3826 struct e1000_hw *hw = &adapter->hw;
3827 struct vf_data_storage *vf_data;
3828 int i, j;
3829
3830 for (i = 0; i < adapter->vfs_allocated_count; i++) {
3831 vf_data = &adapter->vf_data[i];
75f4f382 3832 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4ae196df
AD		 3833 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3834 }
3835}
3836
3837static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3838{
3839 struct e1000_hw *hw = &adapter->hw;
3840 u32 pool_mask, reg, vid;
3841 int i;
3842
3843 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3844
3845 /* Find the vlan filter for this id */
3846 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3847 reg = rd32(E1000_VLVF(i));
3848
3849 /* remove the vf from the pool */
3850 reg &= ~pool_mask;
3851
3852 /* if pool is empty then remove entry from vfta */
3853 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3854 (reg & E1000_VLVF_VLANID_ENABLE)) {
3855 reg = 0;
3856 vid = reg & E1000_VLVF_VLANID_MASK;
3857 igb_vfta_set(hw, vid, false);
3858 }
3859
3860 wr32(E1000_VLVF(i), reg);
3861 }
3862}
3863
3864static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3865{
3866 struct e1000_hw *hw = &adapter->hw;
3867 u32 reg, i;
3868
3869 /* It is an error to call this function when VFs are not enabled */
3870 if (!adapter->vfs_allocated_count)
3871 return -1;
3872
3873 /* Find the vlan filter for this id */
3874 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3875 reg = rd32(E1000_VLVF(i));
3876 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3877 vid == (reg & E1000_VLVF_VLANID_MASK))
3878 break;
3879 }
3880
3881 if (add) {
3882 if (i == E1000_VLVF_ARRAY_SIZE) {
3883 /* Did not find a matching VLAN ID entry that was
3884 * enabled. Search for a free filter entry, i.e.
3885 * one without the enable bit set
3886 */
3887 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3888 reg = rd32(E1000_VLVF(i));
3889 if (!(reg & E1000_VLVF_VLANID_ENABLE))
3890 break;
3891 }
3892 }
3893 if (i < E1000_VLVF_ARRAY_SIZE) {
3894 /* Found an enabled/available entry */
3895 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3896
3897 /* if !enabled we need to set this up in vfta */
3898 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
cad6d05f
AD		 3899 /* add VID to filter table, if bit already set
3900 * PF must have added it outside of table */
3901 if (igb_vfta_set(hw, vid, true))
3902 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
3903 adapter->vfs_allocated_count);
4ae196df
AD		 3904 reg |= E1000_VLVF_VLANID_ENABLE;
3905 }
cad6d05f
AD		 3906 reg &= ~E1000_VLVF_VLANID_MASK;
3907 reg |= vid;
4ae196df
AD		 3908
3909 wr32(E1000_VLVF(i), reg);
3910 return 0;
3911 }
3912 } else {
3913 if (i < E1000_VLVF_ARRAY_SIZE) {
3914 /* remove vf from the pool */
3915 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
3916 /* if pool is empty then remove entry from vfta */
3917 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
3918 reg = 0;
3919 igb_vfta_set(hw, vid, false);
3920 }
3921 wr32(E1000_VLVF(i), reg);
3922 return 0;
3923 }
3924 }
3925 return -1;
3926}
3927
3928static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
3929{
3930 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3931 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
3932
3933 return igb_vlvf_set(adapter, vid, add, vf);
3934}
3935
3936static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
3937{
3938 struct e1000_hw *hw = &adapter->hw;
3939
3940 /* disable mailbox functionality for vf */
3941 adapter->vf_data[vf].clear_to_send = false;
3942
3943 /* reset offloads to defaults */
3944 igb_set_vmolr(hw, vf);
3945
3946 /* reset vlans for device */
3947 igb_clear_vf_vfta(adapter, vf);
3948
3949 /* reset multicast table array for vf */
3950 adapter->vf_data[vf].num_vf_mc_hashes = 0;
3951
3952 /* Flush and reset the mta with the new values */
3953 igb_set_multi(adapter->netdev);
3954}
3955
3956static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
3957{
3958 struct e1000_hw *hw = &adapter->hw;
3959 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
3960 u32 reg, msgbuf[3];
3961 u8 *addr = (u8 *)(&msgbuf[1]);
3962
3963 /* process all the same items cleared in a function level reset */
3964 igb_vf_reset_event(adapter, vf);
3965
3966 /* set vf mac address */
3967 igb_rar_set(hw, vf_mac, vf + 1);
3968 igb_set_rah_pool(hw, vf, vf + 1);
3969
3970 /* enable transmit and receive for vf */
3971 reg = rd32(E1000_VFTE);
3972 wr32(E1000_VFTE, reg | (1 << vf));
3973 reg = rd32(E1000_VFRE);
3974 wr32(E1000_VFRE, reg | (1 << vf));
3975
3976 /* enable mailbox functionality for vf */
3977 adapter->vf_data[vf].clear_to_send = true;
3978
3979 /* reply to reset with ack and vf mac address */
3980 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
3981 memcpy(addr, vf_mac, 6);
3982 igb_write_mbx(hw, msgbuf, 3, vf);
3983}
3984
3985static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
3986{
3987 unsigned char *addr = (char *)&msg[1];
3988 int err = -1;
3989
3990 if (is_valid_ether_addr(addr))
3991 err = igb_set_vf_mac(adapter, vf, addr);
3992
3993 return err;
3994
3995}
3996
3997static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
3998{
3999 struct e1000_hw *hw = &adapter->hw;
4000 u32 msg = E1000_VT_MSGTYPE_NACK;
4001
4002 /* if device isn't clear to send it shouldn't be reading either */
4003 if (!adapter->vf_data[vf].clear_to_send)
4004 igb_write_mbx(hw, &msg, 1, vf);
4005}
4006
4007
4008static void igb_msg_task(struct igb_adapter *adapter)
4009{
4010 struct e1000_hw *hw = &adapter->hw;
4011 u32 vf;
4012
4013 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4014 /* process any reset requests */
4015 if (!igb_check_for_rst(hw, vf)) {
4016 adapter->vf_data[vf].clear_to_send = false;
4017 igb_vf_reset_event(adapter, vf);
4018 }
4019
4020 /* process any messages pending */
4021 if (!igb_check_for_msg(hw, vf))
4022 igb_rcv_msg_from_vf(adapter, vf);
4023
4024 /* process any acks */
4025 if (!igb_check_for_ack(hw, vf))
4026 igb_rcv_ack_from_vf(adapter, vf);
4027
4028 }
4029}
4030
4031static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4032{
4033 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4034 u32 msgbuf[mbx_size];
4035 struct e1000_hw *hw = &adapter->hw;
4036 s32 retval;
4037
4038 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4039
4040 if (retval)
4041 dev_err(&adapter->pdev->dev,
4042 "Error receiving message from VF\n");
4043
4044 /* this is a message we already processed, do nothing */
4045 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4046 return retval;
4047
4048 /*
4049 * until the vf completes a reset it should not be
4050 * allowed to start any configuration.
4051 */
4052
4053 if (msgbuf[0] == E1000_VF_RESET) {
4054 igb_vf_reset_msg(adapter, vf);
4055
4056 return retval;
4057 }
4058
4059 if (!adapter->vf_data[vf].clear_to_send) {
4060 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4061 igb_write_mbx(hw, msgbuf, 1, vf);
4062 return retval;
4063 }
4064
4065 switch ((msgbuf[0] & 0xFFFF)) {
4066 case E1000_VF_SET_MAC_ADDR:
4067 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4068 break;
4069 case E1000_VF_SET_MULTICAST:
4070 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4071 break;
4072 case E1000_VF_SET_LPE:
4073 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4074 break;
4075 case E1000_VF_SET_VLAN:
4076 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4077 break;
4078 default:
4079 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4080 retval = -1;
4081 break;
4082 }
4083
4084 /* notify the VF of the results of what it sent us */
4085 if (retval)
4086 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4087 else
4088 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4089
4090 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4091
4092 igb_write_mbx(hw, msgbuf, 1, vf);
4093
4094 return retval;
4095}
4096
9d5c8243
AK		 4097/**
4098 * igb_intr_msi - Interrupt Handler
4099 * @irq: interrupt number
4100 * @data: pointer to a network interface device structure
4101 **/
4102static irqreturn_t igb_intr_msi(int irq, void *data)
4103{
4104 struct net_device *netdev = data;
4105 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4106 struct e1000_hw *hw = &adapter->hw;
4107 /* read ICR disables interrupts using IAM */
4108 u32 icr = rd32(E1000_ICR);
4109
6eb5a7f1 4110 igb_write_itr(adapter->rx_ring);
9d5c8243 4111
dda0e083
AD		 4112 if(icr & E1000_ICR_DOUTSYNC) {
4113 /* HW is reporting DMA is out of sync */
4114 adapter->stats.doosync++;
4115 }
4116
9d5c8243
AK		 4117 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4118 hw->mac.get_link_status = 1;
4119 if (!test_bit(__IGB_DOWN, &adapter->state))
4120 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4121 }
4122
288379f0 4123 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4124
4125 return IRQ_HANDLED;
4126}
4127
4128/**
4a3c6433 4129 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4130 * @irq: interrupt number
4131 * @data: pointer to a network interface device structure
4132 **/
4133static irqreturn_t igb_intr(int irq, void *data)
4134{
4135 struct net_device *netdev = data;
4136 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4137 struct e1000_hw *hw = &adapter->hw;
4138 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4139 * need for the IMC write */
4140 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4141 if (!icr)
4142 return IRQ_NONE; /* Not our interrupt */
4143
6eb5a7f1 4144 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 4145
4146 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4147 * not set, then the adapter didn't send an interrupt */
4148 if (!(icr & E1000_ICR_INT_ASSERTED))
4149 return IRQ_NONE;
4150
dda0e083
AD		 4151 if(icr & E1000_ICR_DOUTSYNC) {
4152 /* HW is reporting DMA is out of sync */
4153 adapter->stats.doosync++;
4154 }
4155
9d5c8243
AK		 4156 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4157 hw->mac.get_link_status = 1;
4158 /* guard against interrupt when we're going down */
4159 if (!test_bit(__IGB_DOWN, &adapter->state))
4160 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4161 }
4162
288379f0 4163 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4164
4165 return IRQ_HANDLED;
4166}
4167
46544258 4168static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
9d5c8243 4169{
661086df 4170 struct igb_adapter *adapter = rx_ring->adapter;
46544258 4171 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4172
46544258
AD		 4173 if (adapter->itr_setting & 3) {
4174 if (adapter->num_rx_queues == 1)
6eb5a7f1 4175 igb_set_itr(adapter);
46544258
AD		 4176 else
4177 igb_update_ring_itr(rx_ring);
9d5c8243
AK		 4178 }
4179
46544258
AD		 4180 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4181 if (adapter->msix_entries)
4182 wr32(E1000_EIMS, rx_ring->eims_value);
4183 else
4184 igb_irq_enable(adapter);
4185 }
9d5c8243
AK		 4186}
4187
46544258
AD		 4188/**
4189 * igb_poll - NAPI Rx polling callback
4190 * @napi: napi polling structure
4191 * @budget: count of how many packets we should handle
4192 **/
4193static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243
AK		 4194{
4195 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
9d5c8243
AK		 4196 int work_done = 0;
4197
421e02f0 4198#ifdef CONFIG_IGB_DCA
bd38e5d1 4199 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 4200 igb_update_rx_dca(rx_ring);
4201#endif
3b644cf6 4202 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243 4203
46544258
AD		 4204 if (rx_ring->buddy) {
4205#ifdef CONFIG_IGB_DCA
bd38e5d1 4206 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
46544258
AD		 4207 igb_update_tx_dca(rx_ring->buddy);
4208#endif
4209 if (!igb_clean_tx_irq(rx_ring->buddy))
4210 work_done = budget;
4211 }
4212
9d5c8243 4213 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4214 if (work_done < budget) {
288379f0 4215 napi_complete(napi);
46544258 4216 igb_rx_irq_enable(rx_ring);
9d5c8243
AK		 4217 }
4218
46544258 4219 return work_done;
9d5c8243 4220}
6d8126f9 4221
33af6bcc
PO		 4222/**
4223 * igb_hwtstamp - utility function which checks for TX time stamp
4224 * @adapter: board private structure
4225 * @skb: packet that was just sent
4226 *
4227 * If we were asked to do hardware stamping and such a time stamp is
4228 * available, then it must have been for this skb here because we only
4229 * allow only one such packet into the queue.
4230 */
4231static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4232{
4233 union skb_shared_tx *shtx = skb_tx(skb);
4234 struct e1000_hw *hw = &adapter->hw;
4235
4236 if (unlikely(shtx->hardware)) {
4237 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4238 if (valid) {
4239 u64 regval = rd32(E1000_TXSTMPL);
4240 u64 ns;
4241 struct skb_shared_hwtstamps shhwtstamps;
4242
4243 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4244 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4245 ns = timecounter_cyc2time(&adapter->clock,
4246 regval);
4247 timecompare_update(&adapter->compare, ns);
4248 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4249 shhwtstamps.syststamp =
4250 timecompare_transform(&adapter->compare, ns);
4251 skb_tstamp_tx(skb, &shhwtstamps);
4252 }
33af6bcc
PO		 4253 }
4254}
4255
9d5c8243
AK		 4256/**
4257 * igb_clean_tx_irq - Reclaim resources after transmit completes
4258 * @adapter: board private structure
4259 * returns true if ring is completely cleaned
4260 **/
3b644cf6 4261static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 4262{
3b644cf6 4263 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 4264 struct net_device *netdev = adapter->netdev;
0e014cb1 4265 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4266 struct igb_buffer *buffer_info;
4267 struct sk_buff *skb;
0e014cb1 4268 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4269 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4270 unsigned int i, eop, count = 0;
4271 bool cleaned = false;
9d5c8243 4272
9d5c8243 4273 i = tx_ring->next_to_clean;
0e014cb1
AD		 4274 eop = tx_ring->buffer_info[i].next_to_watch;
4275 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4276
4277 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4278 (count < tx_ring->count)) {
4279 for (cleaned = false; !cleaned; count++) {
4280 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4281 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4282 cleaned = (i == eop);
9d5c8243
AK		 4283 skb = buffer_info->skb;
4284
4285 if (skb) {
4286 unsigned int segs, bytecount;
4287 /* gso_segs is currently only valid for tcp */
4288 segs = skb_shinfo(skb)->gso_segs ?: 1;
4289 /* multiply data chunks by size of headers */
4290 bytecount = ((segs - 1) * skb_headlen(skb)) +
4291 skb->len;
4292 total_packets += segs;
4293 total_bytes += bytecount;
33af6bcc
PO		 4294
4295 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 4296 }
4297
4298 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 4299 tx_desc->wb.status = 0;
9d5c8243
AK		 4300
4301 i++;
4302 if (i == tx_ring->count)
4303 i = 0;
9d5c8243 4304 }
0e014cb1
AD		 4305 eop = tx_ring->buffer_info[i].next_to_watch;
4306 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4307 }
4308
9d5c8243
AK		 4309 tx_ring->next_to_clean = i;
4310
fc7d345d 4311 if (unlikely(count &&
9d5c8243
AK		 4312 netif_carrier_ok(netdev) &&
4313 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4314 /* Make sure that anybody stopping the queue after this
4315 * sees the new next_to_clean.
4316 */
4317 smp_mb();
661086df
PWJ		 4318 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4319 !(test_bit(__IGB_DOWN, &adapter->state))) {
4320 netif_wake_subqueue(netdev, tx_ring->queue_index);
4321 ++adapter->restart_queue;
4322 }
9d5c8243
AK		 4323 }
4324
4325 if (tx_ring->detect_tx_hung) {
4326 /* Detect a transmit hang in hardware, this serializes the
4327 * check with the clearing of time_stamp and movement of i */
4328 tx_ring->detect_tx_hung = false;
4329 if (tx_ring->buffer_info[i].time_stamp &&
4330 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4331 (adapter->tx_timeout_factor * HZ))
4332 && !(rd32(E1000_STATUS) &
4333 E1000_STATUS_TXOFF)) {
4334
9d5c8243
AK		 4335 /* detected Tx unit hang */
4336 dev_err(&adapter->pdev->dev,
4337 "Detected Tx Unit Hang\n"
2d064c06 4338 " Tx Queue <%d>\n"
9d5c8243
AK		 4339 " TDH <%x>\n"
4340 " TDT <%x>\n"
4341 " next_to_use <%x>\n"
4342 " next_to_clean <%x>\n"
9d5c8243
AK		 4343 "buffer_info[next_to_clean]\n"
4344 " time_stamp <%lx>\n"
0e014cb1 4345 " next_to_watch <%x>\n"
9d5c8243
AK		 4346 " jiffies <%lx>\n"
4347 " desc.status <%x>\n",
2d064c06 4348 tx_ring->queue_index,
9d5c8243
AK		 4349 readl(adapter->hw.hw_addr + tx_ring->head),
4350 readl(adapter->hw.hw_addr + tx_ring->tail),
4351 tx_ring->next_to_use,
4352 tx_ring->next_to_clean,
9d5c8243 4353 tx_ring->buffer_info[i].time_stamp,
0e014cb1 4354 eop,
9d5c8243 4355 jiffies,
0e014cb1 4356 eop_desc->wb.status);
661086df 4357 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 4358 }
4359 }
4360 tx_ring->total_bytes += total_bytes;
4361 tx_ring->total_packets += total_packets;
e21ed353
AD		 4362 tx_ring->tx_stats.bytes += total_bytes;
4363 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 4364 adapter->net_stats.tx_bytes += total_bytes;
4365 adapter->net_stats.tx_packets += total_packets;
0e014cb1 4366 return (count < tx_ring->count);
9d5c8243
AK		 4367}
4368
9d5c8243
AK		 4369/**
4370 * igb_receive_skb - helper function to handle rx indications
eebbbdba 4371 * @ring: pointer to receive ring receving this packet
9d5c8243 4372 * @status: descriptor status field as written by hardware
73cd78f1 4373 * @rx_desc: receive descriptor containing vlan and type information.
9d5c8243
AK		 4374 * @skb: pointer to sk_buff to be indicated to stack
4375 **/
d3352520
AD		 4376static void igb_receive_skb(struct igb_ring *ring, u8 status,
4377 union e1000_adv_rx_desc * rx_desc,
4378 struct sk_buff *skb)
4379{
4380 struct igb_adapter * adapter = ring->adapter;
4381 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4382
0c8dfc83 4383 skb_record_rx_queue(skb, ring->queue_index);
5c0999b7 4384 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
d3352520 4385 if (vlan_extracted)
5c0999b7
HX		 4386 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4387 le16_to_cpu(rx_desc->wb.upper.vlan),
4388 skb);
d3352520 4389 else
5c0999b7 4390 napi_gro_receive(&ring->napi, skb);
d3352520 4391 } else {
d3352520
AD		 4392 if (vlan_extracted)
4393 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
4394 le16_to_cpu(rx_desc->wb.upper.vlan));
4395 else
d3352520 4396 netif_receive_skb(skb);
d3352520 4397 }
9d5c8243
AK		 4398}
4399
9d5c8243
AK		 4400static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4401 u32 status_err, struct sk_buff *skb)
4402{
4403 skb->ip_summed = CHECKSUM_NONE;
4404
4405 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4406 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
4407 return;
4408 /* TCP/UDP checksum error bit is set */
4409 if (status_err &
4410 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4411 /* let the stack verify checksum errors */
4412 adapter->hw_csum_err++;
4413 return;
4414 }
4415 /* It must be a TCP or UDP packet with a valid checksum */
4416 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4417 skb->ip_summed = CHECKSUM_UNNECESSARY;
4418
4419 adapter->hw_csum_good++;
4420}
4421
3b644cf6
MW		 4422static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4423 int *work_done, int budget)
9d5c8243 4424{
3b644cf6 4425 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 4426 struct net_device *netdev = adapter->netdev;
33af6bcc 4427 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4428 struct pci_dev *pdev = adapter->pdev;
4429 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4430 struct igb_buffer *buffer_info , *next_buffer;
4431 struct sk_buff *skb;
9d5c8243
AK		 4432 bool cleaned = false;
4433 int cleaned_count = 0;
4434 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1
AD		 4435 unsigned int i;
4436 u32 length, hlen, staterr;
9d5c8243
AK		 4437
4438 i = rx_ring->next_to_clean;
69d3ca53 4439 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4440 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4441 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4442
4443 while (staterr & E1000_RXD_STAT_DD) {
4444 if (*work_done >= budget)
4445 break;
4446 (*work_done)++;
9d5c8243 4447
69d3ca53
AD		 4448 skb = buffer_info->skb;
4449 prefetch(skb->data - NET_IP_ALIGN);
4450 buffer_info->skb = NULL;
4451
4452 i++;
4453 if (i == rx_ring->count)
4454 i = 0;
4455 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4456 prefetch(next_rxd);
4457 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4458
4459 length = le16_to_cpu(rx_desc->wb.upper.length);
4460 cleaned = true;
4461 cleaned_count++;
4462
bf36c1a0
AD		 4463 if (!adapter->rx_ps_hdr_size) {
4464 pci_unmap_single(pdev, buffer_info->dma,
4465 adapter->rx_buffer_len +
4466 NET_IP_ALIGN,
4467 PCI_DMA_FROMDEVICE);
4468 skb_put(skb, length);
4469 goto send_up;
9d5c8243
AK		 4470 }
4471
69d3ca53
AD		 4472 /* HW will not DMA in data larger than the given buffer, even
4473 * if it parses the (NFS, of course) header to be larger. In
4474 * that case, it fills the header buffer and spills the rest
4475 * into the page.
4476 */
4477 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4478 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4479 if (hlen > adapter->rx_ps_hdr_size)
4480 hlen = adapter->rx_ps_hdr_size;
4481
bf36c1a0
AD		 4482 if (!skb_shinfo(skb)->nr_frags) {
4483 pci_unmap_single(pdev, buffer_info->dma,
73cd78f1 4484 adapter->rx_ps_hdr_size + NET_IP_ALIGN,
bf36c1a0
AD		 4485 PCI_DMA_FROMDEVICE);
4486 skb_put(skb, hlen);
4487 }
4488
4489 if (length) {
9d5c8243 4490 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4491 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4492 buffer_info->page_dma = 0;
bf36c1a0
AD		 4493
4494 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4495 buffer_info->page,
4496 buffer_info->page_offset,
4497 length);
4498
4499 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4500 (page_count(buffer_info->page) != 1))
4501 buffer_info->page = NULL;
4502 else
4503 get_page(buffer_info->page);
9d5c8243
AK		 4504
4505 skb->len += length;
4506 skb->data_len += length;
9d5c8243 4507
bf36c1a0 4508 skb->truesize += length;
9d5c8243 4509 }
9d5c8243 4510
bf36c1a0 4511 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4512 buffer_info->skb = next_buffer->skb;
4513 buffer_info->dma = next_buffer->dma;
4514 next_buffer->skb = skb;
4515 next_buffer->dma = 0;
bf36c1a0
AD		 4516 goto next_desc;
4517 }
69d3ca53 4518send_up:
33af6bcc
PO		 4519 /*
4520 * If this bit is set, then the RX registers contain
4521 * the time stamp. No other packet will be time
4522 * stamped until we read these registers, so read the
4523 * registers to make them available again. Because
4524 * only one packet can be time stamped at a time, we
4525 * know that the register values must belong to this
4526 * one here and therefore we don't need to compare
4527 * any of the additional attributes stored for it.
4528 *
4529 * If nothing went wrong, then it should have a
4530 * skb_shared_tx that we can turn into a
4531 * skb_shared_hwtstamps.
4532 *
4533 * TODO: can time stamping be triggered (thus locking
4534 * the registers) without the packet reaching this point
4535 * here? In that case RX time stamping would get stuck.
4536 *
4537 * TODO: in "time stamp all packets" mode this bit is
4538 * not set. Need a global flag for this mode and then
4539 * always read the registers. Cannot be done without
4540 * a race condition.
4541 */
4542 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4543 u64 regval;
4544 u64 ns;
4545 struct skb_shared_hwtstamps *shhwtstamps =
4546 skb_hwtstamps(skb);
4547
4548 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4549 "igb: no RX time stamp available for time stamped packet");
4550 regval = rd32(E1000_RXSTMPL);
4551 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4552 ns = timecounter_cyc2time(&adapter->clock, regval);
4553 timecompare_update(&adapter->compare, ns);
4554 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4555 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4556 shhwtstamps->syststamp =
4557 timecompare_transform(&adapter->compare, ns);
4558 }
4559
9d5c8243
AK		 4560 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4561 dev_kfree_skb_irq(skb);
4562 goto next_desc;
4563 }
9d5c8243
AK		 4564
4565 total_bytes += skb->len;
4566 total_packets++;
4567
4568 igb_rx_checksum_adv(adapter, staterr, skb);
4569
4570 skb->protocol = eth_type_trans(skb, netdev);
4571
d3352520 4572 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 4573
9d5c8243
AK		 4574next_desc:
4575 rx_desc->wb.upper.status_error = 0;
4576
4577 /* return some buffers to hardware, one at a time is too slow */
4578 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4579 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4580 cleaned_count = 0;
4581 }
4582
4583 /* use prefetched values */
4584 rx_desc = next_rxd;
4585 buffer_info = next_buffer;
9d5c8243
AK		 4586 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4587 }
bf36c1a0 4588
9d5c8243
AK		 4589 rx_ring->next_to_clean = i;
4590 cleaned_count = IGB_DESC_UNUSED(rx_ring);
4591
4592 if (cleaned_count)
3b644cf6 4593 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4594
4595 rx_ring->total_packets += total_packets;
4596 rx_ring->total_bytes += total_bytes;
4597 rx_ring->rx_stats.packets += total_packets;
4598 rx_ring->rx_stats.bytes += total_bytes;
4599 adapter->net_stats.rx_bytes += total_bytes;
4600 adapter->net_stats.rx_packets += total_packets;
4601 return cleaned;
4602}
4603
9d5c8243
AK		 4604/**
4605 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4606 * @adapter: address of board private structure
4607 **/
3b644cf6 4608static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 4609 int cleaned_count)
4610{
3b644cf6 4611 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4612 struct net_device *netdev = adapter->netdev;
4613 struct pci_dev *pdev = adapter->pdev;
4614 union e1000_adv_rx_desc *rx_desc;
4615 struct igb_buffer *buffer_info;
4616 struct sk_buff *skb;
4617 unsigned int i;
db761762 4618 int bufsz;
9d5c8243
AK		 4619
4620 i = rx_ring->next_to_use;
4621 buffer_info = &rx_ring->buffer_info[i];
4622
db761762
AD		 4623 if (adapter->rx_ps_hdr_size)
4624 bufsz = adapter->rx_ps_hdr_size;
4625 else
4626 bufsz = adapter->rx_buffer_len;
4627 bufsz += NET_IP_ALIGN;
4628
9d5c8243
AK		 4629 while (cleaned_count--) {
4630 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4631
bf36c1a0 4632 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4633 if (!buffer_info->page) {
bf36c1a0
AD		 4634 buffer_info->page = alloc_page(GFP_ATOMIC);
4635 if (!buffer_info->page) {
4636 adapter->alloc_rx_buff_failed++;
4637 goto no_buffers;
4638 }
4639 buffer_info->page_offset = 0;
4640 } else {
4641 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4642 }
4643 buffer_info->page_dma =
db761762 4644 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 4645 buffer_info->page_offset,
4646 PAGE_SIZE / 2,
9d5c8243
AK		 4647 PCI_DMA_FROMDEVICE);
4648 }
4649
4650 if (!buffer_info->skb) {
9d5c8243 4651 skb = netdev_alloc_skb(netdev, bufsz);
9d5c8243
AK		 4652 if (!skb) {
4653 adapter->alloc_rx_buff_failed++;
4654 goto no_buffers;
4655 }
4656
4657 /* Make buffer alignment 2 beyond a 16 byte boundary
4658 * this will result in a 16 byte aligned IP header after
4659 * the 14 byte MAC header is removed
4660 */
4661 skb_reserve(skb, NET_IP_ALIGN);
4662
4663 buffer_info->skb = skb;
4664 buffer_info->dma = pci_map_single(pdev, skb->data,
4665 bufsz,
4666 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4667 }
4668 /* Refresh the desc even if buffer_addrs didn't change because
4669 * each write-back erases this info. */
4670 if (adapter->rx_ps_hdr_size) {
4671 rx_desc->read.pkt_addr =
4672 cpu_to_le64(buffer_info->page_dma);
4673 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4674 } else {
4675 rx_desc->read.pkt_addr =
4676 cpu_to_le64(buffer_info->dma);
4677 rx_desc->read.hdr_addr = 0;
4678 }
4679
4680 i++;
4681 if (i == rx_ring->count)
4682 i = 0;
4683 buffer_info = &rx_ring->buffer_info[i];
4684 }
4685
4686no_buffers:
4687 if (rx_ring->next_to_use != i) {
4688 rx_ring->next_to_use = i;
4689 if (i == 0)
4690 i = (rx_ring->count - 1);
4691 else
4692 i--;
4693
4694 /* Force memory writes to complete before letting h/w
4695 * know there are new descriptors to fetch. (Only
4696 * applicable for weak-ordered memory model archs,
4697 * such as IA-64). */
4698 wmb();
4699 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4700 }
4701}
4702
4703/**
4704 * igb_mii_ioctl -
4705 * @netdev:
4706 * @ifreq:
4707 * @cmd:
4708 **/
4709static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4710{
4711 struct igb_adapter *adapter = netdev_priv(netdev);
4712 struct mii_ioctl_data *data = if_mii(ifr);
4713
4714 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4715 return -EOPNOTSUPP;
4716
4717 switch (cmd) {
4718 case SIOCGMIIPHY:
4719 data->phy_id = adapter->hw.phy.addr;
4720 break;
4721 case SIOCGMIIREG:
4722 if (!capable(CAP_NET_ADMIN))
4723 return -EPERM;
f5f4cf08
AD		 4724 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4725 &data->val_out))
9d5c8243
AK		 4726 return -EIO;
4727 break;
4728 case SIOCSMIIREG:
4729 default:
4730 return -EOPNOTSUPP;
4731 }
4732 return 0;
4733}
4734
c6cb090b
PO		 4735/**
4736 * igb_hwtstamp_ioctl - control hardware time stamping
4737 * @netdev:
4738 * @ifreq:
4739 * @cmd:
4740 *
33af6bcc
PO		 4741 * Outgoing time stamping can be enabled and disabled. Play nice and
4742 * disable it when requested, although it shouldn't case any overhead
4743 * when no packet needs it. At most one packet in the queue may be
4744 * marked for time stamping, otherwise it would be impossible to tell
4745 * for sure to which packet the hardware time stamp belongs.
4746 *
4747 * Incoming time stamping has to be configured via the hardware
4748 * filters. Not all combinations are supported, in particular event
4749 * type has to be specified. Matching the kind of event packet is
4750 * not supported, with the exception of "all V2 events regardless of
4751 * level 2 or 4".
4752 *
c6cb090b
PO		 4753 **/
4754static int igb_hwtstamp_ioctl(struct net_device *netdev,
4755 struct ifreq *ifr, int cmd)
4756{
33af6bcc
PO		 4757 struct igb_adapter *adapter = netdev_priv(netdev);
4758 struct e1000_hw *hw = &adapter->hw;
c6cb090b 4759 struct hwtstamp_config config;
33af6bcc
PO		 4760 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4761 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4762 u32 tsync_rx_ctl_type = 0;
4763 u32 tsync_rx_cfg = 0;
4764 int is_l4 = 0;
4765 int is_l2 = 0;
4766 short port = 319; /* PTP */
4767 u32 regval;
c6cb090b
PO		 4768
4769 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4770 return -EFAULT;
4771
4772 /* reserved for future extensions */
4773 if (config.flags)
4774 return -EINVAL;
4775
33af6bcc
PO		 4776 switch (config.tx_type) {
4777 case HWTSTAMP_TX_OFF:
4778 tsync_tx_ctl_bit = 0;
4779 break;
4780 case HWTSTAMP_TX_ON:
4781 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4782 break;
4783 default:
4784 return -ERANGE;
4785 }
4786
4787 switch (config.rx_filter) {
4788 case HWTSTAMP_FILTER_NONE:
4789 tsync_rx_ctl_bit = 0;
4790 break;
4791 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4792 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4793 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4794 case HWTSTAMP_FILTER_ALL:
4795 /*
4796 * register TSYNCRXCFG must be set, therefore it is not
4797 * possible to time stamp both Sync and Delay_Req messages
4798 * => fall back to time stamping all packets
4799 */
4800 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4801 config.rx_filter = HWTSTAMP_FILTER_ALL;
4802 break;
4803 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4804 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4805 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4806 is_l4 = 1;
4807 break;
4808 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4809 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4810 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4811 is_l4 = 1;
4812 break;
4813 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4814 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4815 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4816 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4817 is_l2 = 1;
4818 is_l4 = 1;
4819 config.rx_filter = HWTSTAMP_FILTER_SOME;
4820 break;
4821 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4822 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4823 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4824 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4825 is_l2 = 1;
4826 is_l4 = 1;
4827 config.rx_filter = HWTSTAMP_FILTER_SOME;
4828 break;
4829 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4830 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4831 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4832 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4833 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4834 is_l2 = 1;
4835 break;
4836 default:
4837 return -ERANGE;
4838 }
4839
4840 /* enable/disable TX */
4841 regval = rd32(E1000_TSYNCTXCTL);
4842 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4843 wr32(E1000_TSYNCTXCTL, regval);
4844
4845 /* enable/disable RX, define which PTP packets are time stamped */
4846 regval = rd32(E1000_TSYNCRXCTL);
4847 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4848 regval = (regval & ~0xE) | tsync_rx_ctl_type;
4849 wr32(E1000_TSYNCRXCTL, regval);
4850 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4851
4852 /*
4853 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4854 * (Ethertype to filter on)
4855 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4856 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4857 */
4858 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4859
4860 /* L4 Queue Filter[0]: only filter by source and destination port */
4861 wr32(E1000_SPQF0, htons(port));
4862 wr32(E1000_IMIREXT(0), is_l4 ?
4863 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4864 wr32(E1000_IMIR(0), is_l4 ?
4865 (htons(port)
4866 | (0<<16) /* immediate interrupt disabled */
4867 | 0 /* (1<<17) bit cleared: do not bypass
4868 destination port check */)
4869 : 0);
4870 wr32(E1000_FTQF0, is_l4 ?
4871 (0x11 /* UDP */
4872 | (1<<15) /* VF not compared */
4873 | (1<<27) /* Enable Timestamping */
4874 | (7<<28) /* only source port filter enabled,
4875 source/target address and protocol
4876 masked */)
4877 : ((1<<15) | (15<<28) /* all mask bits set = filter not
4878 enabled */));
4879
4880 wrfl();
4881
4882 adapter->hwtstamp_config = config;
4883
4884 /* clear TX/RX time stamp registers, just to be sure */
4885 regval = rd32(E1000_TXSTMPH);
4886 regval = rd32(E1000_RXSTMPH);
c6cb090b 4887
33af6bcc
PO		 4888 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4889 -EFAULT : 0;
c6cb090b
PO		 4890}
4891
9d5c8243
AK		 4892/**
4893 * igb_ioctl -
4894 * @netdev:
4895 * @ifreq:
4896 * @cmd:
4897 **/
4898static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4899{
4900 switch (cmd) {
4901 case SIOCGMIIPHY:
4902 case SIOCGMIIREG:
4903 case SIOCSMIIREG:
4904 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 4905 case SIOCSHWTSTAMP:
4906 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 4907 default:
4908 return -EOPNOTSUPP;
4909 }
4910}
4911
4912static void igb_vlan_rx_register(struct net_device *netdev,
4913 struct vlan_group *grp)
4914{
4915 struct igb_adapter *adapter = netdev_priv(netdev);
4916 struct e1000_hw *hw = &adapter->hw;
4917 u32 ctrl, rctl;
4918
4919 igb_irq_disable(adapter);
4920 adapter->vlgrp = grp;
4921
4922 if (grp) {
4923 /* enable VLAN tag insert/strip */
4924 ctrl = rd32(E1000_CTRL);
4925 ctrl |= E1000_CTRL_VME;
4926 wr32(E1000_CTRL, ctrl);
4927
4928 /* enable VLAN receive filtering */
4929 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4930 rctl &= ~E1000_RCTL_CFIEN;
4931 wr32(E1000_RCTL, rctl);
4932 igb_update_mng_vlan(adapter);
9d5c8243
AK		 4933 } else {
4934 /* disable VLAN tag insert/strip */
4935 ctrl = rd32(E1000_CTRL);
4936 ctrl &= ~E1000_CTRL_VME;
4937 wr32(E1000_CTRL, ctrl);
4938
9d5c8243
AK		 4939 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4940 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4941 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4942 }
9d5c8243
AK		 4943 }
4944
e1739522
AD		 4945 igb_rlpml_set(adapter);
4946
9d5c8243
AK		 4947 if (!test_bit(__IGB_DOWN, &adapter->state))
4948 igb_irq_enable(adapter);
4949}
4950
4951static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4952{
4953 struct igb_adapter *adapter = netdev_priv(netdev);
4954 struct e1000_hw *hw = &adapter->hw;
4ae196df 4955 int pf_id = adapter->vfs_allocated_count;
9d5c8243 4956
28b0759c 4957 if ((hw->mng_cookie.status &
9d5c8243
AK		 4958 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4959 (vid == adapter->mng_vlan_id))
4960 return;
4ae196df
AD		 4961
4962 /* add vid to vlvf if sr-iov is enabled,
4963 * if that fails add directly to filter table */
4964 if (igb_vlvf_set(adapter, vid, true, pf_id))
4965 igb_vfta_set(hw, vid, true);
4966
9d5c8243
AK		 4967}
4968
4969static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4970{
4971 struct igb_adapter *adapter = netdev_priv(netdev);
4972 struct e1000_hw *hw = &adapter->hw;
4ae196df 4973 int pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 4974
4975 igb_irq_disable(adapter);
4976 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4977
4978 if (!test_bit(__IGB_DOWN, &adapter->state))
4979 igb_irq_enable(adapter);
4980
4981 if ((adapter->hw.mng_cookie.status &
4982 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4983 (vid == adapter->mng_vlan_id)) {
4984 /* release control to f/w */
4985 igb_release_hw_control(adapter);
4986 return;
4987 }
4988
4ae196df
AD		 4989 /* remove vid from vlvf if sr-iov is enabled,
4990 * if not in vlvf remove from vfta */
4991 if (igb_vlvf_set(adapter, vid, false, pf_id))
4992 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 4993}
4994
4995static void igb_restore_vlan(struct igb_adapter *adapter)
4996{
4997 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4998
4999 if (adapter->vlgrp) {
5000 u16 vid;
5001 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5002 if (!vlan_group_get_device(adapter->vlgrp, vid))
5003 continue;
5004 igb_vlan_rx_add_vid(adapter->netdev, vid);
5005 }
5006 }
5007}
5008
5009int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5010{
5011 struct e1000_mac_info *mac = &adapter->hw.mac;
5012
5013 mac->autoneg = 0;
5014
5015 /* Fiber NICs only allow 1000 gbps Full duplex */
5016 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
5017 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5018 dev_err(&adapter->pdev->dev,
5019 "Unsupported Speed/Duplex configuration\n");
5020 return -EINVAL;
5021 }
5022
5023 switch (spddplx) {
5024 case SPEED_10 + DUPLEX_HALF:
5025 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5026 break;
5027 case SPEED_10 + DUPLEX_FULL:
5028 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5029 break;
5030 case SPEED_100 + DUPLEX_HALF:
5031 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5032 break;
5033 case SPEED_100 + DUPLEX_FULL:
5034 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5035 break;
5036 case SPEED_1000 + DUPLEX_FULL:
5037 mac->autoneg = 1;
5038 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5039 break;
5040 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5041 default:
5042 dev_err(&adapter->pdev->dev,
5043 "Unsupported Speed/Duplex configuration\n");
5044 return -EINVAL;
5045 }
5046 return 0;
5047}
5048
9d5c8243
AK		 5049static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5050{
5051 struct net_device *netdev = pci_get_drvdata(pdev);
5052 struct igb_adapter *adapter = netdev_priv(netdev);
5053 struct e1000_hw *hw = &adapter->hw;
2d064c06 5054 u32 ctrl, rctl, status;
9d5c8243
AK		 5055 u32 wufc = adapter->wol;
5056#ifdef CONFIG_PM
5057 int retval = 0;
5058#endif
5059
5060 netif_device_detach(netdev);
5061
a88f10ec
AD		 5062 if (netif_running(netdev))
5063 igb_close(netdev);
5064
5065 igb_reset_interrupt_capability(adapter);
5066
5067 igb_free_queues(adapter);
9d5c8243
AK		 5068
5069#ifdef CONFIG_PM
5070 retval = pci_save_state(pdev);
5071 if (retval)
5072 return retval;
5073#endif
5074
5075 status = rd32(E1000_STATUS);
5076 if (status & E1000_STATUS_LU)
5077 wufc &= ~E1000_WUFC_LNKC;
5078
5079 if (wufc) {
5080 igb_setup_rctl(adapter);
5081 igb_set_multi(netdev);
5082
5083 /* turn on all-multi mode if wake on multicast is enabled */
5084 if (wufc & E1000_WUFC_MC) {
5085 rctl = rd32(E1000_RCTL);
5086 rctl |= E1000_RCTL_MPE;
5087 wr32(E1000_RCTL, rctl);
5088 }
5089
5090 ctrl = rd32(E1000_CTRL);
5091 /* advertise wake from D3Cold */
5092 #define E1000_CTRL_ADVD3WUC 0x00100000
5093 /* phy power management enable */
5094 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5095 ctrl |= E1000_CTRL_ADVD3WUC;
5096 wr32(E1000_CTRL, ctrl);
5097
9d5c8243
AK		 5098 /* Allow time for pending master requests to run */
5099 igb_disable_pcie_master(&adapter->hw);
5100
5101 wr32(E1000_WUC, E1000_WUC_PME_EN);
5102 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5103 } else {
5104 wr32(E1000_WUC, 0);
5105 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5106 }
5107
2d064c06
AD		 5108 /* make sure adapter isn't asleep if manageability/wol is enabled */
5109 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 5110 pci_enable_wake(pdev, PCI_D3hot, 1);
5111 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 5112 } else {
5113 igb_shutdown_fiber_serdes_link_82575(hw);
5114 pci_enable_wake(pdev, PCI_D3hot, 0);
5115 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 5116 }
5117
5118 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5119 * would have already happened in close and is redundant. */
5120 igb_release_hw_control(adapter);
5121
5122 pci_disable_device(pdev);
5123
5124 pci_set_power_state(pdev, pci_choose_state(pdev, state));
5125
5126 return 0;
5127}
5128
5129#ifdef CONFIG_PM
5130static int igb_resume(struct pci_dev *pdev)
5131{
5132 struct net_device *netdev = pci_get_drvdata(pdev);
5133 struct igb_adapter *adapter = netdev_priv(netdev);
5134 struct e1000_hw *hw = &adapter->hw;
5135 u32 err;
5136
5137 pci_set_power_state(pdev, PCI_D0);
5138 pci_restore_state(pdev);
42bfd33a 5139
aed5dec3 5140 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5141 if (err) {
5142 dev_err(&pdev->dev,
5143 "igb: Cannot enable PCI device from suspend\n");
5144 return err;
5145 }
5146 pci_set_master(pdev);
5147
5148 pci_enable_wake(pdev, PCI_D3hot, 0);
5149 pci_enable_wake(pdev, PCI_D3cold, 0);
5150
a88f10ec
AD		 5151 igb_set_interrupt_capability(adapter);
5152
5153 if (igb_alloc_queues(adapter)) {
5154 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5155 return -ENOMEM;
9d5c8243
AK		 5156 }
5157
5158 /* e1000_power_up_phy(adapter); */
5159
5160 igb_reset(adapter);
a8564f03
AD		 5161
5162 /* let the f/w know that the h/w is now under the control of the
5163 * driver. */
5164 igb_get_hw_control(adapter);
5165
9d5c8243
AK		 5166 wr32(E1000_WUS, ~0);
5167
a88f10ec
AD		 5168 if (netif_running(netdev)) {
5169 err = igb_open(netdev);
5170 if (err)
5171 return err;
5172 }
9d5c8243
AK		 5173
5174 netif_device_attach(netdev);
5175
9d5c8243
AK		 5176 return 0;
5177}
5178#endif
5179
5180static void igb_shutdown(struct pci_dev *pdev)
5181{
5182 igb_suspend(pdev, PMSG_SUSPEND);
5183}
5184
5185#ifdef CONFIG_NET_POLL_CONTROLLER
5186/*
5187 * Polling 'interrupt' - used by things like netconsole to send skbs
5188 * without having to re-enable interrupts. It's not called while
5189 * the interrupt routine is executing.
5190 */
5191static void igb_netpoll(struct net_device *netdev)
5192{
5193 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5194 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5195 int i;
9d5c8243 5196
eebbbdba
AD		 5197 if (!adapter->msix_entries) {
5198 igb_irq_disable(adapter);
5199 napi_schedule(&adapter->rx_ring[0].napi);
5200 return;
5201 }
9d5c8243 5202
eebbbdba
AD		 5203 for (i = 0; i < adapter->num_tx_queues; i++) {
5204 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5205 wr32(E1000_EIMC, tx_ring->eims_value);
5206 igb_clean_tx_irq(tx_ring);
5207 wr32(E1000_EIMS, tx_ring->eims_value);
5208 }
9d5c8243 5209
eebbbdba
AD		 5210 for (i = 0; i < adapter->num_rx_queues; i++) {
5211 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5212 wr32(E1000_EIMC, rx_ring->eims_value);
5213 napi_schedule(&rx_ring->napi);
5214 }
9d5c8243
AK		 5215}
5216#endif /* CONFIG_NET_POLL_CONTROLLER */
5217
5218/**
5219 * igb_io_error_detected - called when PCI error is detected
5220 * @pdev: Pointer to PCI device
5221 * @state: The current pci connection state
5222 *
5223 * This function is called after a PCI bus error affecting
5224 * this device has been detected.
5225 */
5226static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5227 pci_channel_state_t state)
5228{
5229 struct net_device *netdev = pci_get_drvdata(pdev);
5230 struct igb_adapter *adapter = netdev_priv(netdev);
5231
5232 netif_device_detach(netdev);
5233
5234 if (netif_running(netdev))
5235 igb_down(adapter);
5236 pci_disable_device(pdev);
5237
5238 /* Request a slot slot reset. */
5239 return PCI_ERS_RESULT_NEED_RESET;
5240}
5241
5242/**
5243 * igb_io_slot_reset - called after the pci bus has been reset.
5244 * @pdev: Pointer to PCI device
5245 *
5246 * Restart the card from scratch, as if from a cold-boot. Implementation
5247 * resembles the first-half of the igb_resume routine.
5248 */
5249static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5250{
5251 struct net_device *netdev = pci_get_drvdata(pdev);
5252 struct igb_adapter *adapter = netdev_priv(netdev);
5253 struct e1000_hw *hw = &adapter->hw;
40a914fa 5254 pci_ers_result_t result;
42bfd33a 5255 int err;
9d5c8243 5256
aed5dec3 5257 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5258 dev_err(&pdev->dev,
5259 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5260 result = PCI_ERS_RESULT_DISCONNECT;
5261 } else {
5262 pci_set_master(pdev);
5263 pci_restore_state(pdev);
9d5c8243 5264
40a914fa
AD		 5265 pci_enable_wake(pdev, PCI_D3hot, 0);
5266 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5267
40a914fa
AD		 5268 igb_reset(adapter);
5269 wr32(E1000_WUS, ~0);
5270 result = PCI_ERS_RESULT_RECOVERED;
5271 }
9d5c8243 5272
ea943d41
JK		 5273 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5274 if (err) {
5275 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5276 "failed 0x%0x\n", err);
5277 /* non-fatal, continue */
5278 }
40a914fa
AD		 5279
5280 return result;
9d5c8243
AK		 5281}
5282
5283/**
5284 * igb_io_resume - called when traffic can start flowing again.
5285 * @pdev: Pointer to PCI device
5286 *
5287 * This callback is called when the error recovery driver tells us that
5288 * its OK to resume normal operation. Implementation resembles the
5289 * second-half of the igb_resume routine.
5290 */
5291static void igb_io_resume(struct pci_dev *pdev)
5292{
5293 struct net_device *netdev = pci_get_drvdata(pdev);
5294 struct igb_adapter *adapter = netdev_priv(netdev);
5295
9d5c8243
AK		 5296 if (netif_running(netdev)) {
5297 if (igb_up(adapter)) {
5298 dev_err(&pdev->dev, "igb_up failed after reset\n");
5299 return;
5300 }
5301 }
5302
5303 netif_device_attach(netdev);
5304
5305 /* let the f/w know that the h/w is now under the control of the
5306 * driver. */
5307 igb_get_hw_control(adapter);
9d5c8243
AK		 5308}
5309
e1739522
AD		 5310static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
5311{
5312 u32 reg_data;
5313
5314 reg_data = rd32(E1000_VMOLR(vfn));
5315 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
5316 E1000_VMOLR_ROPE | /* Accept packets matched in UTA */
5317 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
5318 E1000_VMOLR_AUPE | /* Accept untagged packets */
5319 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
5320 wr32(E1000_VMOLR(vfn), reg_data);
5321}
5322
4ae196df
AD		 5323static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
5324 int vfn)
e1739522
AD		 5325{
5326 struct e1000_hw *hw = &adapter->hw;
5327 u32 vmolr;
5328
5329 vmolr = rd32(E1000_VMOLR(vfn));
5330 vmolr &= ~E1000_VMOLR_RLPML_MASK;
5331 vmolr |= size | E1000_VMOLR_LPE;
5332 wr32(E1000_VMOLR(vfn), vmolr);
4ae196df
AD		 5333
5334 return 0;
e1739522
AD		 5335}
5336
5337static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
5338{
5339 u32 reg_data;
5340
5341 reg_data = rd32(E1000_RAH(entry));
5342 reg_data &= ~E1000_RAH_POOL_MASK;
5343 reg_data |= E1000_RAH_POOL_1 << pool;;
5344 wr32(E1000_RAH(entry), reg_data);
5345}
5346
5347static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5348 int entry_count, u16 total_rar_filters)
5349{
5350 struct e1000_hw *hw = &adapter->hw;
5351 int i = adapter->vfs_allocated_count + 1;
5352
5353 if ((i + entry_count) < total_rar_filters)
5354 total_rar_filters = i + entry_count;
5355
5356 for (; i < total_rar_filters; i++)
5357 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5358}
5359
4ae196df
AD		 5360static int igb_set_vf_mac(struct igb_adapter *adapter,
5361 int vf, unsigned char *mac_addr)
5362{
5363 struct e1000_hw *hw = &adapter->hw;
5364 int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5365
5366 igb_rar_set(hw, mac_addr, rar_entry);
5367
37680117 5368 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df
AD		 5369
5370 igb_set_rah_pool(hw, vf, rar_entry);
5371
5372 return 0;
5373}
5374
5375static void igb_vmm_control(struct igb_adapter *adapter)
5376{
5377 struct e1000_hw *hw = &adapter->hw;
5378 u32 reg_data;
5379
5380 if (!adapter->vfs_allocated_count)
5381 return;
5382
5383 /* VF's need PF reset indication before they
5384 * can send/receive mail */
5385 reg_data = rd32(E1000_CTRL_EXT);
5386 reg_data |= E1000_CTRL_EXT_PFRSTD;
5387 wr32(E1000_CTRL_EXT, reg_data);
5388
5389 igb_vmdq_set_loopback_pf(hw, true);
5390 igb_vmdq_set_replication_pf(hw, true);
5391}
5392
37680117
AD		 5393#ifdef CONFIG_PCI_IOV
5394static ssize_t igb_show_num_vfs(struct device *dev,
5395 struct device_attribute *attr, char *buf)
5396{
5397 struct igb_adapter *adapter = netdev_priv(to_net_dev(dev));
5398
5399 return sprintf(buf, "%d\n", adapter->vfs_allocated_count);
5400}
5401
5402static ssize_t igb_set_num_vfs(struct device *dev,
5403 struct device_attribute *attr,
5404 const char *buf, size_t count)
5405{
5406 struct net_device *netdev = to_net_dev(dev);
5407 struct igb_adapter *adapter = netdev_priv(netdev);
5408 struct e1000_hw *hw = &adapter->hw;
5409 struct pci_dev *pdev = adapter->pdev;
5410 unsigned int num_vfs, i;
5411 unsigned char mac_addr[ETH_ALEN];
5412 int err;
5413
5414 sscanf(buf, "%u", &num_vfs);
5415
5416 if (num_vfs > 7)
5417 num_vfs = 7;
5418
5419 /* value unchanged do nothing */
5420 if (num_vfs == adapter->vfs_allocated_count)
5421 return count;
5422
5423 if (netdev->flags & IFF_UP)
5424 igb_close(netdev);
5425
5426 igb_reset_interrupt_capability(adapter);
5427 igb_free_queues(adapter);
5428 adapter->tx_ring = NULL;
5429 adapter->rx_ring = NULL;
5430 adapter->vfs_allocated_count = 0;
5431
5432 /* reclaim resources allocated to VFs since we are changing count */
5433 if (adapter->vf_data) {
5434 /* disable iov and allow time for transactions to clear */
5435 pci_disable_sriov(pdev);
5436 msleep(500);
5437
5438 kfree(adapter->vf_data);
5439 adapter->vf_data = NULL;
5440 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
5441 msleep(100);
5442 dev_info(&pdev->dev, "IOV Disabled\n");
5443 }
5444
5445 if (num_vfs) {
5446 adapter->vf_data = kcalloc(num_vfs,
5447 sizeof(struct vf_data_storage),
5448 GFP_KERNEL);
5449 if (!adapter->vf_data) {
5450 dev_err(&pdev->dev, "Could not allocate VF private "
5451 "data - IOV enable failed\n");
5452 } else {
5453 err = pci_enable_sriov(pdev, num_vfs);
5454 if (!err) {
5455 adapter->vfs_allocated_count = num_vfs;
5456 dev_info(&pdev->dev, "%d vfs allocated\n", num_vfs);
5457 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5458 random_ether_addr(mac_addr);
5459 igb_set_vf_mac(adapter, i, mac_addr);
5460 }
5461 } else {
5462 kfree(adapter->vf_data);
5463 adapter->vf_data = NULL;
5464 }
5465 }
5466 }
5467
5468 igb_set_interrupt_capability(adapter);
5469 igb_alloc_queues(adapter);
5470 igb_reset(adapter);
5471
5472 if (netdev->flags & IFF_UP)
5473 igb_open(netdev);
5474
5475 return count;
5476}
5477#endif /* CONFIG_PCI_IOV */
9d5c8243 5478/* igb_main.c */
Linux 6.x block layer and io_uring tree(s)