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igb: switch to new dca API
[linux-block.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
70 /* required last entry */
71 {0, }
72};
73
74MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
75
76void igb_reset(struct igb_adapter *);
77static int igb_setup_all_tx_resources(struct igb_adapter *);
78static int igb_setup_all_rx_resources(struct igb_adapter *);
79static void igb_free_all_tx_resources(struct igb_adapter *);
80static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 81void igb_update_stats(struct igb_adapter *);
82static int igb_probe(struct pci_dev *, const struct pci_device_id *);
83static void __devexit igb_remove(struct pci_dev *pdev);
84static int igb_sw_init(struct igb_adapter *);
85static int igb_open(struct net_device *);
86static int igb_close(struct net_device *);
87static void igb_configure_tx(struct igb_adapter *);
88static void igb_configure_rx(struct igb_adapter *);
89static void igb_setup_rctl(struct igb_adapter *);
90static void igb_clean_all_tx_rings(struct igb_adapter *);
91static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 92static void igb_clean_tx_ring(struct igb_ring *);
93static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 94static void igb_set_multi(struct net_device *);
95static void igb_update_phy_info(unsigned long);
96static void igb_watchdog(unsigned long);
97static void igb_watchdog_task(struct work_struct *);
98static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
99 struct igb_ring *);
100static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
101static struct net_device_stats *igb_get_stats(struct net_device *);
102static int igb_change_mtu(struct net_device *, int);
103static int igb_set_mac(struct net_device *, void *);
104static irqreturn_t igb_intr(int irq, void *);
105static irqreturn_t igb_intr_msi(int irq, void *);
106static irqreturn_t igb_msix_other(int irq, void *);
107static irqreturn_t igb_msix_rx(int irq, void *);
108static irqreturn_t igb_msix_tx(int irq, void *);
421e02f0 109#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 110static void igb_update_rx_dca(struct igb_ring *);
111static void igb_update_tx_dca(struct igb_ring *);
112static void igb_setup_dca(struct igb_adapter *);
421e02f0 113#endif /* CONFIG_IGB_DCA */
3b644cf6 114static bool igb_clean_tx_irq(struct igb_ring *);
661086df 115static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 116static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
117static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 118static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
119static void igb_tx_timeout(struct net_device *);
120static void igb_reset_task(struct work_struct *);
121static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
122static void igb_vlan_rx_add_vid(struct net_device *, u16);
123static void igb_vlan_rx_kill_vid(struct net_device *, u16);
124static void igb_restore_vlan(struct igb_adapter *);
4ae196df
AD		 125static void igb_ping_all_vfs(struct igb_adapter *);
126static void igb_msg_task(struct igb_adapter *);
127static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
e1739522
AD		 128static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
129static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
4ae196df 130static void igb_vmm_control(struct igb_adapter *);
e1739522 131static inline void igb_set_vmolr(struct e1000_hw *, int);
4ae196df
AD		 132static inline int igb_set_vf_rlpml(struct igb_adapter *, int, int);
133static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
134static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
9d5c8243
AK		 135
136static int igb_suspend(struct pci_dev *, pm_message_t);
137#ifdef CONFIG_PM
138static int igb_resume(struct pci_dev *);
139#endif
140static void igb_shutdown(struct pci_dev *);
421e02f0 141#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 142static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
143static struct notifier_block dca_notifier = {
144 .notifier_call = igb_notify_dca,
145 .next = NULL,
146 .priority = 0
147};
148#endif
9d5c8243
AK		 149#ifdef CONFIG_NET_POLL_CONTROLLER
150/* for netdump / net console */
151static void igb_netpoll(struct net_device *);
152#endif
153
37680117
AD		 154#ifdef CONFIG_PCI_IOV
155static ssize_t igb_set_num_vfs(struct device *, struct device_attribute *,
156 const char *, size_t);
157static ssize_t igb_show_num_vfs(struct device *, struct device_attribute *,
158 char *);
159DEVICE_ATTR(num_vfs, S_IRUGO | S_IWUSR, igb_show_num_vfs, igb_set_num_vfs);
160#endif
9d5c8243
AK		 161static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
162 pci_channel_state_t);
163static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
164static void igb_io_resume(struct pci_dev *);
165
166static struct pci_error_handlers igb_err_handler = {
167 .error_detected = igb_io_error_detected,
168 .slot_reset = igb_io_slot_reset,
169 .resume = igb_io_resume,
170};
171
172
173static struct pci_driver igb_driver = {
174 .name = igb_driver_name,
175 .id_table = igb_pci_tbl,
176 .probe = igb_probe,
177 .remove = __devexit_p(igb_remove),
178#ifdef CONFIG_PM
179 /* Power Managment Hooks */
180 .suspend = igb_suspend,
181 .resume = igb_resume,
182#endif
183 .shutdown = igb_shutdown,
184 .err_handler = &igb_err_handler
185};
186
7dfc16fa
AD		 187static int global_quad_port_a; /* global quad port a indication */
188
9d5c8243
AK		 189MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
190MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
191MODULE_LICENSE("GPL");
192MODULE_VERSION(DRV_VERSION);
193
38c845c7
PO		 194/**
195 * Scale the NIC clock cycle by a large factor so that
196 * relatively small clock corrections can be added or
197 * substracted at each clock tick. The drawbacks of a
198 * large factor are a) that the clock register overflows
199 * more quickly (not such a big deal) and b) that the
200 * increment per tick has to fit into 24 bits.
201 *
202 * Note that
203 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
204 * IGB_TSYNC_SCALE
205 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
206 *
207 * The base scale factor is intentionally a power of two
208 * so that the division in %struct timecounter can be done with
209 * a shift.
210 */
211#define IGB_TSYNC_SHIFT (19)
212#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
213
214/**
215 * The duration of one clock cycle of the NIC.
216 *
217 * @todo This hard-coded value is part of the specification and might change
218 * in future hardware revisions. Add revision check.
219 */
220#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
221
222#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
223# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
224#endif
225
226/**
227 * igb_read_clock - read raw cycle counter (to be used by time counter)
228 */
229static cycle_t igb_read_clock(const struct cyclecounter *tc)
230{
231 struct igb_adapter *adapter =
232 container_of(tc, struct igb_adapter, cycles);
233 struct e1000_hw *hw = &adapter->hw;
234 u64 stamp;
235
236 stamp = rd32(E1000_SYSTIML);
237 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
238
239 return stamp;
240}
241
9d5c8243
AK		 242#ifdef DEBUG
243/**
244 * igb_get_hw_dev_name - return device name string
245 * used by hardware layer to print debugging information
246 **/
247char *igb_get_hw_dev_name(struct e1000_hw *hw)
248{
249 struct igb_adapter *adapter = hw->back;
250 return adapter->netdev->name;
251}
38c845c7
PO		 252
253/**
254 * igb_get_time_str - format current NIC and system time as string
255 */
256static char *igb_get_time_str(struct igb_adapter *adapter,
257 char buffer[160])
258{
259 cycle_t hw = adapter->cycles.read(&adapter->cycles);
260 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
261 struct timespec sys;
262 struct timespec delta;
263 getnstimeofday(&sys);
264
265 delta = timespec_sub(nic, sys);
266
267 sprintf(buffer,
33af6bcc
PO		 268 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
269 hw,
38c845c7
PO		 270 (long)nic.tv_sec, nic.tv_nsec,
271 (long)sys.tv_sec, sys.tv_nsec,
272 (long)delta.tv_sec, delta.tv_nsec);
273
274 return buffer;
275}
9d5c8243
AK		 276#endif
277
278/**
279 * igb_init_module - Driver Registration Routine
280 *
281 * igb_init_module is the first routine called when the driver is
282 * loaded. All it does is register with the PCI subsystem.
283 **/
284static int __init igb_init_module(void)
285{
286 int ret;
287 printk(KERN_INFO "%s - version %s\n",
288 igb_driver_string, igb_driver_version);
289
290 printk(KERN_INFO "%s\n", igb_copyright);
291
7dfc16fa
AD		 292 global_quad_port_a = 0;
293
421e02f0 294#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 295 dca_register_notify(&dca_notifier);
296#endif
bbd98fe4
AD		 297
298 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 299 return ret;
300}
301
302module_init(igb_init_module);
303
304/**
305 * igb_exit_module - Driver Exit Cleanup Routine
306 *
307 * igb_exit_module is called just before the driver is removed
308 * from memory.
309 **/
310static void __exit igb_exit_module(void)
311{
421e02f0 312#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 313 dca_unregister_notify(&dca_notifier);
314#endif
9d5c8243
AK		 315 pci_unregister_driver(&igb_driver);
316}
317
318module_exit(igb_exit_module);
319
26bc19ec
AD		 320#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
321/**
322 * igb_cache_ring_register - Descriptor ring to register mapping
323 * @adapter: board private structure to initialize
324 *
325 * Once we know the feature-set enabled for the device, we'll cache
326 * the register offset the descriptor ring is assigned to.
327 **/
328static void igb_cache_ring_register(struct igb_adapter *adapter)
329{
330 int i;
1bfaf07b 331 unsigned int rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 332
333 switch (adapter->hw.mac.type) {
334 case e1000_82576:
335 /* The queues are allocated for virtualization such that VF 0
336 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
337 * In order to avoid collision we start at the first free queue
338 * and continue consuming queues in the same sequence
339 */
340 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 341 adapter->rx_ring[i].reg_idx = rbase_offset +
342 Q_IDX_82576(i);
26bc19ec 343 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 344 adapter->tx_ring[i].reg_idx = rbase_offset +
345 Q_IDX_82576(i);
26bc19ec
AD		 346 break;
347 case e1000_82575:
348 default:
349 for (i = 0; i < adapter->num_rx_queues; i++)
350 adapter->rx_ring[i].reg_idx = i;
351 for (i = 0; i < adapter->num_tx_queues; i++)
352 adapter->tx_ring[i].reg_idx = i;
353 break;
354 }
355}
356
9d5c8243
AK		 357/**
358 * igb_alloc_queues - Allocate memory for all rings
359 * @adapter: board private structure to initialize
360 *
361 * We allocate one ring per queue at run-time since we don't know the
362 * number of queues at compile-time.
363 **/
364static int igb_alloc_queues(struct igb_adapter *adapter)
365{
366 int i;
367
368 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
369 sizeof(struct igb_ring), GFP_KERNEL);
370 if (!adapter->tx_ring)
371 return -ENOMEM;
372
373 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
374 sizeof(struct igb_ring), GFP_KERNEL);
375 if (!adapter->rx_ring) {
376 kfree(adapter->tx_ring);
377 return -ENOMEM;
378 }
379
6eb5a7f1
AD		 380 adapter->rx_ring->buddy = adapter->tx_ring;
381
661086df
PWJ		 382 for (i = 0; i < adapter->num_tx_queues; i++) {
383 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 384 ring->count = adapter->tx_ring_count;
661086df
PWJ		 385 ring->adapter = adapter;
386 ring->queue_index = i;
387 }
9d5c8243
AK		 388 for (i = 0; i < adapter->num_rx_queues; i++) {
389 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 390 ring->count = adapter->rx_ring_count;
9d5c8243 391 ring->adapter = adapter;
844290e5 392 ring->queue_index = i;
9d5c8243
AK		 393 ring->itr_register = E1000_ITR;
394
844290e5 395 /* set a default napi handler for each rx_ring */
661086df 396 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 397 }
26bc19ec
AD		 398
399 igb_cache_ring_register(adapter);
9d5c8243
AK		 400 return 0;
401}
402
a88f10ec
AD		 403static void igb_free_queues(struct igb_adapter *adapter)
404{
405 int i;
406
407 for (i = 0; i < adapter->num_rx_queues; i++)
408 netif_napi_del(&adapter->rx_ring[i].napi);
409
410 kfree(adapter->tx_ring);
411 kfree(adapter->rx_ring);
412}
413
9d5c8243
AK		 414#define IGB_N0_QUEUE -1
415static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
416 int tx_queue, int msix_vector)
417{
418 u32 msixbm = 0;
419 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 420 u32 ivar, index;
421
422 switch (hw->mac.type) {
423 case e1000_82575:
9d5c8243
AK		 424 /* The 82575 assigns vectors using a bitmask, which matches the
425 bitmask for the EICR/EIMS/EIMC registers. To assign one
426 or more queues to a vector, we write the appropriate bits
427 into the MSIXBM register for that vector. */
428 if (rx_queue > IGB_N0_QUEUE) {
429 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
430 adapter->rx_ring[rx_queue].eims_value = msixbm;
431 }
432 if (tx_queue > IGB_N0_QUEUE) {
433 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
434 adapter->tx_ring[tx_queue].eims_value =
435 E1000_EICR_TX_QUEUE0 << tx_queue;
436 }
437 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 438 break;
439 case e1000_82576:
26bc19ec 440 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 441 Each queue has a single entry in the table to which we write
442 a vector number along with a "valid" bit. Sadly, the layout
443 of the table is somewhat counterintuitive. */
444 if (rx_queue > IGB_N0_QUEUE) {
1bfaf07b 445 index = (rx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 446 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 447 if (rx_queue & 0x1) {
2d064c06
AD		 448 /* vector goes into third byte of register */
449 ivar = ivar & 0xFF00FFFF;
450 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 451 } else {
452 /* vector goes into low byte of register */
453 ivar = ivar & 0xFFFFFF00;
454 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 455 }
456 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
457 array_wr32(E1000_IVAR0, index, ivar);
458 }
459 if (tx_queue > IGB_N0_QUEUE) {
1bfaf07b 460 index = (tx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 461 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 462 if (tx_queue & 0x1) {
2d064c06
AD		 463 /* vector goes into high byte of register */
464 ivar = ivar & 0x00FFFFFF;
465 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 466 } else {
467 /* vector goes into second byte of register */
468 ivar = ivar & 0xFFFF00FF;
469 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 470 }
471 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
472 array_wr32(E1000_IVAR0, index, ivar);
473 }
474 break;
475 default:
476 BUG();
477 break;
478 }
9d5c8243
AK		 479}
480
481/**
482 * igb_configure_msix - Configure MSI-X hardware
483 *
484 * igb_configure_msix sets up the hardware to properly
485 * generate MSI-X interrupts.
486 **/
487static void igb_configure_msix(struct igb_adapter *adapter)
488{
489 u32 tmp;
490 int i, vector = 0;
491 struct e1000_hw *hw = &adapter->hw;
492
493 adapter->eims_enable_mask = 0;
2d064c06
AD		 494 if (hw->mac.type == e1000_82576)
495 /* Turn on MSI-X capability first, or our settings
496 * won't stick. And it will take days to debug. */
497 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 498 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 499 E1000_GPIE_NSICR);
9d5c8243
AK		 500
501 for (i = 0; i < adapter->num_tx_queues; i++) {
502 struct igb_ring *tx_ring = &adapter->tx_ring[i];
503 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
504 adapter->eims_enable_mask |= tx_ring->eims_value;
505 if (tx_ring->itr_val)
6eb5a7f1 506 writel(tx_ring->itr_val,
9d5c8243
AK		 507 hw->hw_addr + tx_ring->itr_register);
508 else
509 writel(1, hw->hw_addr + tx_ring->itr_register);
510 }
511
512 for (i = 0; i < adapter->num_rx_queues; i++) {
513 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 514 rx_ring->buddy = NULL;
9d5c8243
AK		 515 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
516 adapter->eims_enable_mask |= rx_ring->eims_value;
517 if (rx_ring->itr_val)
6eb5a7f1 518 writel(rx_ring->itr_val,
9d5c8243
AK		 519 hw->hw_addr + rx_ring->itr_register);
520 else
521 writel(1, hw->hw_addr + rx_ring->itr_register);
522 }
523
524
525 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 526 switch (hw->mac.type) {
527 case e1000_82575:
9d5c8243
AK		 528 array_wr32(E1000_MSIXBM(0), vector++,
529 E1000_EIMS_OTHER);
530
9d5c8243
AK		 531 tmp = rd32(E1000_CTRL_EXT);
532 /* enable MSI-X PBA support*/
533 tmp |= E1000_CTRL_EXT_PBA_CLR;
534
535 /* Auto-Mask interrupts upon ICR read. */
536 tmp |= E1000_CTRL_EXT_EIAME;
537 tmp |= E1000_CTRL_EXT_IRCA;
538
539 wr32(E1000_CTRL_EXT, tmp);
540 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 541 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 542
2d064c06
AD		 543 break;
544
545 case e1000_82576:
546 tmp = (vector++ | E1000_IVAR_VALID) << 8;
547 wr32(E1000_IVAR_MISC, tmp);
548
549 adapter->eims_enable_mask = (1 << (vector)) - 1;
550 adapter->eims_other = 1 << (vector - 1);
551 break;
552 default:
553 /* do nothing, since nothing else supports MSI-X */
554 break;
555 } /* switch (hw->mac.type) */
9d5c8243
AK		 556 wrfl();
557}
558
559/**
560 * igb_request_msix - Initialize MSI-X interrupts
561 *
562 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
563 * kernel.
564 **/
565static int igb_request_msix(struct igb_adapter *adapter)
566{
567 struct net_device *netdev = adapter->netdev;
568 int i, err = 0, vector = 0;
569
570 vector = 0;
571
572 for (i = 0; i < adapter->num_tx_queues; i++) {
573 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 574 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 575 err = request_irq(adapter->msix_entries[vector].vector,
576 &igb_msix_tx, 0, ring->name,
577 &(adapter->tx_ring[i]));
578 if (err)
579 goto out;
580 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 581 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 582 vector++;
583 }
584 for (i = 0; i < adapter->num_rx_queues; i++) {
585 struct igb_ring *ring = &(adapter->rx_ring[i]);
586 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 587 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 588 else
589 memcpy(ring->name, netdev->name, IFNAMSIZ);
590 err = request_irq(adapter->msix_entries[vector].vector,
591 &igb_msix_rx, 0, ring->name,
592 &(adapter->rx_ring[i]));
593 if (err)
594 goto out;
595 ring->itr_register = E1000_EITR(0) + (vector << 2);
596 ring->itr_val = adapter->itr;
597 vector++;
598 }
599
600 err = request_irq(adapter->msix_entries[vector].vector,
601 &igb_msix_other, 0, netdev->name, netdev);
602 if (err)
603 goto out;
604
9d5c8243
AK		 605 igb_configure_msix(adapter);
606 return 0;
607out:
608 return err;
609}
610
611static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
612{
613 if (adapter->msix_entries) {
614 pci_disable_msix(adapter->pdev);
615 kfree(adapter->msix_entries);
616 adapter->msix_entries = NULL;
7dfc16fa 617 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 618 pci_disable_msi(adapter->pdev);
619 return;
620}
621
622
623/**
624 * igb_set_interrupt_capability - set MSI or MSI-X if supported
625 *
626 * Attempt to configure interrupts using the best available
627 * capabilities of the hardware and kernel.
628 **/
629static void igb_set_interrupt_capability(struct igb_adapter *adapter)
630{
631 int err;
632 int numvecs, i;
633
83b7180d
AD		 634 /* Number of supported queues. */
635 /* Having more queues than CPUs doesn't make sense. */
636 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
637 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
638
9d5c8243
AK		 639 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
640 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
641 GFP_KERNEL);
642 if (!adapter->msix_entries)
643 goto msi_only;
644
645 for (i = 0; i < numvecs; i++)
646 adapter->msix_entries[i].entry = i;
647
648 err = pci_enable_msix(adapter->pdev,
649 adapter->msix_entries,
650 numvecs);
651 if (err == 0)
34a20e89 652 goto out;
9d5c8243
AK		 653
654 igb_reset_interrupt_capability(adapter);
655
656 /* If we can't do MSI-X, try MSI */
657msi_only:
658 adapter->num_rx_queues = 1;
661086df 659 adapter->num_tx_queues = 1;
9d5c8243 660 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 661 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 662out:
661086df 663 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 664 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 665 return;
666}
667
668/**
669 * igb_request_irq - initialize interrupts
670 *
671 * Attempts to configure interrupts using the best available
672 * capabilities of the hardware and kernel.
673 **/
674static int igb_request_irq(struct igb_adapter *adapter)
675{
676 struct net_device *netdev = adapter->netdev;
677 struct e1000_hw *hw = &adapter->hw;
678 int err = 0;
679
680 if (adapter->msix_entries) {
681 err = igb_request_msix(adapter);
844290e5 682 if (!err)
9d5c8243 683 goto request_done;
9d5c8243
AK		 684 /* fall back to MSI */
685 igb_reset_interrupt_capability(adapter);
686 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 687 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 688 igb_free_all_tx_resources(adapter);
689 igb_free_all_rx_resources(adapter);
690 adapter->num_rx_queues = 1;
691 igb_alloc_queues(adapter);
844290e5 692 } else {
2d064c06
AD		 693 switch (hw->mac.type) {
694 case e1000_82575:
695 wr32(E1000_MSIXBM(0),
696 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
697 break;
698 case e1000_82576:
699 wr32(E1000_IVAR0, E1000_IVAR_VALID);
700 break;
701 default:
702 break;
703 }
9d5c8243 704 }
844290e5 705
7dfc16fa 706 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 707 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
708 netdev->name, netdev);
709 if (!err)
710 goto request_done;
711 /* fall back to legacy interrupts */
712 igb_reset_interrupt_capability(adapter);
7dfc16fa 713 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 714 }
715
716 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
717 netdev->name, netdev);
718
6cb5e577 719 if (err)
9d5c8243
AK		 720 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
721 err);
9d5c8243
AK		 722
723request_done:
724 return err;
725}
726
727static void igb_free_irq(struct igb_adapter *adapter)
728{
729 struct net_device *netdev = adapter->netdev;
730
731 if (adapter->msix_entries) {
732 int vector = 0, i;
733
734 for (i = 0; i < adapter->num_tx_queues; i++)
735 free_irq(adapter->msix_entries[vector++].vector,
736 &(adapter->tx_ring[i]));
737 for (i = 0; i < adapter->num_rx_queues; i++)
738 free_irq(adapter->msix_entries[vector++].vector,
739 &(adapter->rx_ring[i]));
740
741 free_irq(adapter->msix_entries[vector++].vector, netdev);
742 return;
743 }
744
745 free_irq(adapter->pdev->irq, netdev);
746}
747
748/**
749 * igb_irq_disable - Mask off interrupt generation on the NIC
750 * @adapter: board private structure
751 **/
752static void igb_irq_disable(struct igb_adapter *adapter)
753{
754 struct e1000_hw *hw = &adapter->hw;
755
756 if (adapter->msix_entries) {
844290e5 757 wr32(E1000_EIAM, 0);
9d5c8243
AK		 758 wr32(E1000_EIMC, ~0);
759 wr32(E1000_EIAC, 0);
760 }
844290e5
PW		 761
762 wr32(E1000_IAM, 0);
9d5c8243
AK		 763 wr32(E1000_IMC, ~0);
764 wrfl();
765 synchronize_irq(adapter->pdev->irq);
766}
767
768/**
769 * igb_irq_enable - Enable default interrupt generation settings
770 * @adapter: board private structure
771 **/
772static void igb_irq_enable(struct igb_adapter *adapter)
773{
774 struct e1000_hw *hw = &adapter->hw;
775
776 if (adapter->msix_entries) {
844290e5
PW		 777 wr32(E1000_EIAC, adapter->eims_enable_mask);
778 wr32(E1000_EIAM, adapter->eims_enable_mask);
779 wr32(E1000_EIMS, adapter->eims_enable_mask);
4ae196df
AD		 780 if (adapter->vfs_allocated_count)
781 wr32(E1000_MBVFIMR, 0xFF);
782 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
783 E1000_IMS_DOUTSYNC));
844290e5
PW		 784 } else {
785 wr32(E1000_IMS, IMS_ENABLE_MASK);
786 wr32(E1000_IAM, IMS_ENABLE_MASK);
787 }
9d5c8243
AK		 788}
789
790static void igb_update_mng_vlan(struct igb_adapter *adapter)
791{
792 struct net_device *netdev = adapter->netdev;
793 u16 vid = adapter->hw.mng_cookie.vlan_id;
794 u16 old_vid = adapter->mng_vlan_id;
795 if (adapter->vlgrp) {
796 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
797 if (adapter->hw.mng_cookie.status &
798 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
799 igb_vlan_rx_add_vid(netdev, vid);
800 adapter->mng_vlan_id = vid;
801 } else
802 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
803
804 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
805 (vid != old_vid) &&
806 !vlan_group_get_device(adapter->vlgrp, old_vid))
807 igb_vlan_rx_kill_vid(netdev, old_vid);
808 } else
809 adapter->mng_vlan_id = vid;
810 }
811}
812
813/**
814 * igb_release_hw_control - release control of the h/w to f/w
815 * @adapter: address of board private structure
816 *
817 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
818 * For ASF and Pass Through versions of f/w this means that the
819 * driver is no longer loaded.
820 *
821 **/
822static void igb_release_hw_control(struct igb_adapter *adapter)
823{
824 struct e1000_hw *hw = &adapter->hw;
825 u32 ctrl_ext;
826
827 /* Let firmware take over control of h/w */
828 ctrl_ext = rd32(E1000_CTRL_EXT);
829 wr32(E1000_CTRL_EXT,
830 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
831}
832
833
834/**
835 * igb_get_hw_control - get control of the h/w from f/w
836 * @adapter: address of board private structure
837 *
838 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
839 * For ASF and Pass Through versions of f/w this means that
840 * the driver is loaded.
841 *
842 **/
843static void igb_get_hw_control(struct igb_adapter *adapter)
844{
845 struct e1000_hw *hw = &adapter->hw;
846 u32 ctrl_ext;
847
848 /* Let firmware know the driver has taken over */
849 ctrl_ext = rd32(E1000_CTRL_EXT);
850 wr32(E1000_CTRL_EXT,
851 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
852}
853
9d5c8243
AK		 854/**
855 * igb_configure - configure the hardware for RX and TX
856 * @adapter: private board structure
857 **/
858static void igb_configure(struct igb_adapter *adapter)
859{
860 struct net_device *netdev = adapter->netdev;
861 int i;
862
863 igb_get_hw_control(adapter);
864 igb_set_multi(netdev);
865
866 igb_restore_vlan(adapter);
9d5c8243
AK		 867
868 igb_configure_tx(adapter);
869 igb_setup_rctl(adapter);
870 igb_configure_rx(adapter);
662d7205
AD		 871
872 igb_rx_fifo_flush_82575(&adapter->hw);
873
9d5c8243
AK		 874 /* call IGB_DESC_UNUSED which always leaves
875 * at least 1 descriptor unused to make sure
876 * next_to_use != next_to_clean */
877 for (i = 0; i < adapter->num_rx_queues; i++) {
878 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 879 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 880 }
881
882
883 adapter->tx_queue_len = netdev->tx_queue_len;
884}
885
886
887/**
888 * igb_up - Open the interface and prepare it to handle traffic
889 * @adapter: board private structure
890 **/
891
892int igb_up(struct igb_adapter *adapter)
893{
894 struct e1000_hw *hw = &adapter->hw;
895 int i;
896
897 /* hardware has been reset, we need to reload some things */
898 igb_configure(adapter);
899
900 clear_bit(__IGB_DOWN, &adapter->state);
901
844290e5
PW		 902 for (i = 0; i < adapter->num_rx_queues; i++)
903 napi_enable(&adapter->rx_ring[i].napi);
904 if (adapter->msix_entries)
9d5c8243 905 igb_configure_msix(adapter);
9d5c8243 906
4ae196df 907 igb_vmm_control(adapter);
e1739522
AD		 908 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
909 igb_set_vmolr(hw, adapter->vfs_allocated_count);
910
9d5c8243
AK		 911 /* Clear any pending interrupts. */
912 rd32(E1000_ICR);
913 igb_irq_enable(adapter);
914
915 /* Fire a link change interrupt to start the watchdog. */
916 wr32(E1000_ICS, E1000_ICS_LSC);
917 return 0;
918}
919
920void igb_down(struct igb_adapter *adapter)
921{
922 struct e1000_hw *hw = &adapter->hw;
923 struct net_device *netdev = adapter->netdev;
924 u32 tctl, rctl;
925 int i;
926
927 /* signal that we're down so the interrupt handler does not
928 * reschedule our watchdog timer */
929 set_bit(__IGB_DOWN, &adapter->state);
930
931 /* disable receives in the hardware */
932 rctl = rd32(E1000_RCTL);
933 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
934 /* flush and sleep below */
935
fd2ea0a7 936 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 937
938 /* disable transmits in the hardware */
939 tctl = rd32(E1000_TCTL);
940 tctl &= ~E1000_TCTL_EN;
941 wr32(E1000_TCTL, tctl);
942 /* flush both disables and wait for them to finish */
943 wrfl();
944 msleep(10);
945
844290e5
PW		 946 for (i = 0; i < adapter->num_rx_queues; i++)
947 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 948
9d5c8243
AK		 949 igb_irq_disable(adapter);
950
951 del_timer_sync(&adapter->watchdog_timer);
952 del_timer_sync(&adapter->phy_info_timer);
953
954 netdev->tx_queue_len = adapter->tx_queue_len;
955 netif_carrier_off(netdev);
04fe6358
AD		 956
957 /* record the stats before reset*/
958 igb_update_stats(adapter);
959
9d5c8243
AK		 960 adapter->link_speed = 0;
961 adapter->link_duplex = 0;
962
3023682e
JK		 963 if (!pci_channel_offline(adapter->pdev))
964 igb_reset(adapter);
9d5c8243
AK		 965 igb_clean_all_tx_rings(adapter);
966 igb_clean_all_rx_rings(adapter);
967}
968
969void igb_reinit_locked(struct igb_adapter *adapter)
970{
971 WARN_ON(in_interrupt());
972 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
973 msleep(1);
974 igb_down(adapter);
975 igb_up(adapter);
976 clear_bit(__IGB_RESETTING, &adapter->state);
977}
978
979void igb_reset(struct igb_adapter *adapter)
980{
981 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 982 struct e1000_mac_info *mac = &hw->mac;
983 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 984 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
985 u16 hwm;
986
987 /* Repartition Pba for greater than 9k mtu
988 * To take effect CTRL.RST is required.
989 */
fa4dfae0
AD		 990 switch (mac->type) {
991 case e1000_82576:
2d064c06 992 pba = E1000_PBA_64K;
fa4dfae0
AD		 993 break;
994 case e1000_82575:
995 default:
996 pba = E1000_PBA_34K;
997 break;
2d064c06 998 }
9d5c8243 999
2d064c06
AD		 1000 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1001 (mac->type < e1000_82576)) {
9d5c8243
AK		 1002 /* adjust PBA for jumbo frames */
1003 wr32(E1000_PBA, pba);
1004
1005 /* To maintain wire speed transmits, the Tx FIFO should be
1006 * large enough to accommodate two full transmit packets,
1007 * rounded up to the next 1KB and expressed in KB. Likewise,
1008 * the Rx FIFO should be large enough to accommodate at least
1009 * one full receive packet and is similarly rounded up and
1010 * expressed in KB. */
1011 pba = rd32(E1000_PBA);
1012 /* upper 16 bits has Tx packet buffer allocation size in KB */
1013 tx_space = pba >> 16;
1014 /* lower 16 bits has Rx packet buffer allocation size in KB */
1015 pba &= 0xffff;
1016 /* the tx fifo also stores 16 bytes of information about the tx
1017 * but don't include ethernet FCS because hardware appends it */
1018 min_tx_space = (adapter->max_frame_size +
85e8d004 1019 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1020 ETH_FCS_LEN) * 2;
1021 min_tx_space = ALIGN(min_tx_space, 1024);
1022 min_tx_space >>= 10;
1023 /* software strips receive CRC, so leave room for it */
1024 min_rx_space = adapter->max_frame_size;
1025 min_rx_space = ALIGN(min_rx_space, 1024);
1026 min_rx_space >>= 10;
1027
1028 /* If current Tx allocation is less than the min Tx FIFO size,
1029 * and the min Tx FIFO size is less than the current Rx FIFO
1030 * allocation, take space away from current Rx allocation */
1031 if (tx_space < min_tx_space &&
1032 ((min_tx_space - tx_space) < pba)) {
1033 pba = pba - (min_tx_space - tx_space);
1034
1035 /* if short on rx space, rx wins and must trump tx
1036 * adjustment */
1037 if (pba < min_rx_space)
1038 pba = min_rx_space;
1039 }
2d064c06 1040 wr32(E1000_PBA, pba);
9d5c8243 1041 }
9d5c8243
AK		 1042
1043 /* flow control settings */
1044 /* The high water mark must be low enough to fit one full frame
1045 * (or the size used for early receive) above it in the Rx FIFO.
1046 * Set it to the lower of:
1047 * - 90% of the Rx FIFO size, or
1048 * - the full Rx FIFO size minus one full frame */
1049 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1050 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1051
2d064c06
AD		 1052 if (mac->type < e1000_82576) {
1053 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1054 fc->low_water = fc->high_water - 8;
1055 } else {
1056 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1057 fc->low_water = fc->high_water - 16;
1058 }
9d5c8243
AK		 1059 fc->pause_time = 0xFFFF;
1060 fc->send_xon = 1;
1061 fc->type = fc->original_type;
1062
4ae196df
AD		 1063 /* disable receive for all VFs and wait one second */
1064 if (adapter->vfs_allocated_count) {
1065 int i;
1066 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1067 adapter->vf_data[i].clear_to_send = false;
1068
1069 /* ping all the active vfs to let them know we are going down */
1070 igb_ping_all_vfs(adapter);
1071
1072 /* disable transmits and receives */
1073 wr32(E1000_VFRE, 0);
1074 wr32(E1000_VFTE, 0);
1075 }
1076
9d5c8243
AK		 1077 /* Allow time for pending master requests to run */
1078 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1079 wr32(E1000_WUC, 0);
1080
1081 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1082 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1083
1084 igb_update_mng_vlan(adapter);
1085
1086 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1087 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1088
1089 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1090 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1091}
1092
2e5c6922
SH		 1093static const struct net_device_ops igb_netdev_ops = {
1094 .ndo_open = igb_open,
1095 .ndo_stop = igb_close,
00829823 1096 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 1097 .ndo_get_stats = igb_get_stats,
1098 .ndo_set_multicast_list = igb_set_multi,
1099 .ndo_set_mac_address = igb_set_mac,
1100 .ndo_change_mtu = igb_change_mtu,
1101 .ndo_do_ioctl = igb_ioctl,
1102 .ndo_tx_timeout = igb_tx_timeout,
1103 .ndo_validate_addr = eth_validate_addr,
1104 .ndo_vlan_rx_register = igb_vlan_rx_register,
1105 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1106 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1107#ifdef CONFIG_NET_POLL_CONTROLLER
1108 .ndo_poll_controller = igb_netpoll,
1109#endif
1110};
1111
9d5c8243
AK		 1112/**
1113 * igb_probe - Device Initialization Routine
1114 * @pdev: PCI device information struct
1115 * @ent: entry in igb_pci_tbl
1116 *
1117 * Returns 0 on success, negative on failure
1118 *
1119 * igb_probe initializes an adapter identified by a pci_dev structure.
1120 * The OS initialization, configuring of the adapter private structure,
1121 * and a hardware reset occur.
1122 **/
1123static int __devinit igb_probe(struct pci_dev *pdev,
1124 const struct pci_device_id *ent)
1125{
1126 struct net_device *netdev;
1127 struct igb_adapter *adapter;
1128 struct e1000_hw *hw;
c54106bb 1129 struct pci_dev *us_dev;
9d5c8243
AK		 1130 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1131 unsigned long mmio_start, mmio_len;
450c87c8 1132 int err, pci_using_dac, pos;
c54106bb 1133 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 1134 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1135 u32 part_num;
1136
aed5dec3 1137 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1138 if (err)
1139 return err;
1140
1141 pci_using_dac = 0;
1142 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1143 if (!err) {
1144 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1145 if (!err)
1146 pci_using_dac = 1;
1147 } else {
1148 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1149 if (err) {
1150 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1151 if (err) {
1152 dev_err(&pdev->dev, "No usable DMA "
1153 "configuration, aborting\n");
1154 goto err_dma;
1155 }
1156 }
1157 }
1158
c54106bb
AD		 1159 /* 82575 requires that the pci-e link partner disable the L0s state */
1160 switch (pdev->device) {
1161 case E1000_DEV_ID_82575EB_COPPER:
1162 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1163 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1164 us_dev = pdev->bus->self;
1165 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1166 if (pos) {
1167 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1168 &state);
1169 state &= ~PCIE_LINK_STATE_L0S;
1170 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1171 state);
ac450208
BH		 1172 dev_info(&pdev->dev,
1173 "Disabling ASPM L0s upstream switch port %s\n",
1174 pci_name(us_dev));
c54106bb
AD		 1175 }
1176 default:
1177 break;
1178 }
1179
aed5dec3
AD		 1180 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1181 IORESOURCE_MEM),
1182 igb_driver_name);
9d5c8243
AK		 1183 if (err)
1184 goto err_pci_reg;
1185
ea943d41
JK		 1186 err = pci_enable_pcie_error_reporting(pdev);
1187 if (err) {
1188 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1189 "0x%x\n", err);
1190 /* non-fatal, continue */
1191 }
40a914fa 1192
9d5c8243 1193 pci_set_master(pdev);
c682fc23 1194 pci_save_state(pdev);
9d5c8243
AK		 1195
1196 err = -ENOMEM;
1bfaf07b
AD		 1197 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1198 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1199 if (!netdev)
1200 goto err_alloc_etherdev;
1201
1202 SET_NETDEV_DEV(netdev, &pdev->dev);
1203
1204 pci_set_drvdata(pdev, netdev);
1205 adapter = netdev_priv(netdev);
1206 adapter->netdev = netdev;
1207 adapter->pdev = pdev;
1208 hw = &adapter->hw;
1209 hw->back = adapter;
1210 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1211
1212 mmio_start = pci_resource_start(pdev, 0);
1213 mmio_len = pci_resource_len(pdev, 0);
1214
1215 err = -EIO;
28b0759c
AD		 1216 hw->hw_addr = ioremap(mmio_start, mmio_len);
1217 if (!hw->hw_addr)
9d5c8243
AK		 1218 goto err_ioremap;
1219
2e5c6922 1220 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1221 igb_set_ethtool_ops(netdev);
9d5c8243 1222 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1223
1224 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1225
1226 netdev->mem_start = mmio_start;
1227 netdev->mem_end = mmio_start + mmio_len;
1228
9d5c8243
AK		 1229 /* PCI config space info */
1230 hw->vendor_id = pdev->vendor;
1231 hw->device_id = pdev->device;
1232 hw->revision_id = pdev->revision;
1233 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1234 hw->subsystem_device_id = pdev->subsystem_device;
1235
1236 /* setup the private structure */
1237 hw->back = adapter;
1238 /* Copy the default MAC, PHY and NVM function pointers */
1239 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1240 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1241 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1242 /* Initialize skew-specific constants */
1243 err = ei->get_invariants(hw);
1244 if (err)
450c87c8 1245 goto err_sw_init;
9d5c8243 1246
450c87c8 1247 /* setup the private structure */
9d5c8243
AK		 1248 err = igb_sw_init(adapter);
1249 if (err)
1250 goto err_sw_init;
1251
1252 igb_get_bus_info_pcie(hw);
1253
7dfc16fa
AD		 1254 /* set flags */
1255 switch (hw->mac.type) {
7dfc16fa 1256 case e1000_82575:
7dfc16fa
AD		 1257 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1258 break;
bbd98fe4 1259 case e1000_82576:
7dfc16fa
AD		 1260 default:
1261 break;
1262 }
1263
9d5c8243
AK		 1264 hw->phy.autoneg_wait_to_complete = false;
1265 hw->mac.adaptive_ifs = true;
1266
1267 /* Copper options */
1268 if (hw->phy.media_type == e1000_media_type_copper) {
1269 hw->phy.mdix = AUTO_ALL_MODES;
1270 hw->phy.disable_polarity_correction = false;
1271 hw->phy.ms_type = e1000_ms_hw_default;
1272 }
1273
1274 if (igb_check_reset_block(hw))
1275 dev_info(&pdev->dev,
1276 "PHY reset is blocked due to SOL/IDER session.\n");
1277
1278 netdev->features = NETIF_F_SG |
7d8eb29e 1279 NETIF_F_IP_CSUM |
9d5c8243
AK		 1280 NETIF_F_HW_VLAN_TX |
1281 NETIF_F_HW_VLAN_RX |
1282 NETIF_F_HW_VLAN_FILTER;
1283
7d8eb29e 1284 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1285 netdev->features |= NETIF_F_TSO;
9d5c8243 1286 netdev->features |= NETIF_F_TSO6;
48f29ffc 1287
5c0999b7 1288 netdev->features |= NETIF_F_GRO;
d3352520 1289
48f29ffc
JK		 1290 netdev->vlan_features |= NETIF_F_TSO;
1291 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1292 netdev->vlan_features |= NETIF_F_IP_CSUM;
48f29ffc
JK		 1293 netdev->vlan_features |= NETIF_F_SG;
1294
9d5c8243
AK		 1295 if (pci_using_dac)
1296 netdev->features |= NETIF_F_HIGHDMA;
1297
9d5c8243
AK		 1298 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1299
1300 /* before reading the NVM, reset the controller to put the device in a
1301 * known good starting state */
1302 hw->mac.ops.reset_hw(hw);
1303
1304 /* make sure the NVM is good */
1305 if (igb_validate_nvm_checksum(hw) < 0) {
1306 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1307 err = -EIO;
1308 goto err_eeprom;
1309 }
1310
1311 /* copy the MAC address out of the NVM */
1312 if (hw->mac.ops.read_mac_addr(hw))
1313 dev_err(&pdev->dev, "NVM Read Error\n");
1314
1315 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1316 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1317
1318 if (!is_valid_ether_addr(netdev->perm_addr)) {
1319 dev_err(&pdev->dev, "Invalid MAC Address\n");
1320 err = -EIO;
1321 goto err_eeprom;
1322 }
1323
1324 init_timer(&adapter->watchdog_timer);
1325 adapter->watchdog_timer.function = &igb_watchdog;
1326 adapter->watchdog_timer.data = (unsigned long) adapter;
1327
1328 init_timer(&adapter->phy_info_timer);
1329 adapter->phy_info_timer.function = &igb_update_phy_info;
1330 adapter->phy_info_timer.data = (unsigned long) adapter;
1331
1332 INIT_WORK(&adapter->reset_task, igb_reset_task);
1333 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1334
450c87c8 1335 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1336 adapter->fc_autoneg = true;
1337 hw->mac.autoneg = true;
1338 hw->phy.autoneg_advertised = 0x2f;
1339
1340 hw->fc.original_type = e1000_fc_default;
1341 hw->fc.type = e1000_fc_default;
1342
cbd347ad 1343 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1344 adapter->itr = IGB_START_ITR;
1345
1346 igb_validate_mdi_setting(hw);
1347
1348 adapter->rx_csum = 1;
1349
1350 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1351 * enable the ACPI Magic Packet filter
1352 */
1353
1354 if (hw->bus.func == 0 ||
1355 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
312c75ae 1356 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
9d5c8243
AK		 1357
1358 if (eeprom_data & eeprom_apme_mask)
1359 adapter->eeprom_wol |= E1000_WUFC_MAG;
1360
1361 /* now that we have the eeprom settings, apply the special cases where
1362 * the eeprom may be wrong or the board simply won't support wake on
1363 * lan on a particular port */
1364 switch (pdev->device) {
1365 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1366 adapter->eeprom_wol = 0;
1367 break;
1368 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1369 case E1000_DEV_ID_82576_FIBER:
1370 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1371 /* Wake events only supported on port A for dual fiber
1372 * regardless of eeprom setting */
1373 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1374 adapter->eeprom_wol = 0;
1375 break;
1376 }
1377
1378 /* initialize the wol settings based on the eeprom settings */
1379 adapter->wol = adapter->eeprom_wol;
e1b86d84 1380 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1381
1382 /* reset the hardware with the new settings */
1383 igb_reset(adapter);
1384
1385 /* let the f/w know that the h/w is now under the control of the
1386 * driver. */
1387 igb_get_hw_control(adapter);
1388
1389 /* tell the stack to leave us alone until igb_open() is called */
1390 netif_carrier_off(netdev);
fd2ea0a7 1391 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1392
1393 strcpy(netdev->name, "eth%d");
1394 err = register_netdev(netdev);
1395 if (err)
1396 goto err_register;
1397
37680117
AD		 1398#ifdef CONFIG_PCI_IOV
1399 /* since iov functionality isn't critical to base device function we
1400 * can accept failure. If it fails we don't allow iov to be enabled */
1401 if (hw->mac.type == e1000_82576) {
1402 err = pci_enable_sriov(pdev, 0);
1403 if (!err)
1404 err = device_create_file(&netdev->dev,
1405 &dev_attr_num_vfs);
1406 if (err)
1407 dev_err(&pdev->dev, "Failed to initialize IOV\n");
1408 }
1409
1410#endif
421e02f0 1411#ifdef CONFIG_IGB_DCA
bbd98fe4 1412 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1413 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1414 dev_info(&pdev->dev, "DCA enabled\n");
1415 /* Always use CB2 mode, difference is masked
1416 * in the CB driver. */
cbd347ad 1417 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6
JC		 1418 igb_setup_dca(adapter);
1419 }
1420#endif
1421
38c845c7
PO		 1422 /*
1423 * Initialize hardware timer: we keep it running just in case
1424 * that some program needs it later on.
1425 */
1426 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1427 adapter->cycles.read = igb_read_clock;
1428 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1429 adapter->cycles.mult = 1;
1430 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1431 wr32(E1000_TIMINCA,
1432 (1<<24) |
1433 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1434#if 0
1435 /*
1436 * Avoid rollover while we initialize by resetting the time counter.
1437 */
1438 wr32(E1000_SYSTIML, 0x00000000);
1439 wr32(E1000_SYSTIMH, 0x00000000);
1440#else
1441 /*
1442 * Set registers so that rollover occurs soon to test this.
1443 */
1444 wr32(E1000_SYSTIML, 0x00000000);
1445 wr32(E1000_SYSTIMH, 0xFF800000);
1446#endif
1447 wrfl();
1448 timecounter_init(&adapter->clock,
1449 &adapter->cycles,
1450 ktime_to_ns(ktime_get_real()));
1451
33af6bcc
PO		 1452 /*
1453 * Synchronize our NIC clock against system wall clock. NIC
1454 * time stamp reading requires ~3us per sample, each sample
1455 * was pretty stable even under load => only require 10
1456 * samples for each offset comparison.
1457 */
1458 memset(&adapter->compare, 0, sizeof(adapter->compare));
1459 adapter->compare.source = &adapter->clock;
1460 adapter->compare.target = ktime_get_real;
1461 adapter->compare.num_samples = 10;
1462 timecompare_update(&adapter->compare, 0);
1463
38c845c7
PO		 1464#ifdef DEBUG
1465 {
1466 char buffer[160];
1467 printk(KERN_DEBUG
1468 "igb: %s: hw %p initialized timer\n",
1469 igb_get_time_str(adapter, buffer),
1470 &adapter->hw);
1471 }
1472#endif
1473
9d5c8243
AK		 1474 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1475 /* print bus type/speed/width info */
7c510e4b 1476 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1477 netdev->name,
1478 ((hw->bus.speed == e1000_bus_speed_2500)
1479 ? "2.5Gb/s" : "unknown"),
1480 ((hw->bus.width == e1000_bus_width_pcie_x4)
1481 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1482 ? "Width x1" : "unknown"),
7c510e4b 1483 netdev->dev_addr);
9d5c8243
AK		 1484
1485 igb_read_part_num(hw, &part_num);
1486 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1487 (part_num >> 8), (part_num & 0xff));
1488
1489 dev_info(&pdev->dev,
1490 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1491 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1492 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1493 adapter->num_rx_queues, adapter->num_tx_queues);
1494
9d5c8243
AK		 1495 return 0;
1496
1497err_register:
1498 igb_release_hw_control(adapter);
1499err_eeprom:
1500 if (!igb_check_reset_block(hw))
f5f4cf08 1501 igb_reset_phy(hw);
9d5c8243
AK		 1502
1503 if (hw->flash_address)
1504 iounmap(hw->flash_address);
1505
a88f10ec 1506 igb_free_queues(adapter);
9d5c8243 1507err_sw_init:
9d5c8243
AK		 1508 iounmap(hw->hw_addr);
1509err_ioremap:
1510 free_netdev(netdev);
1511err_alloc_etherdev:
aed5dec3
AD		 1512 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1513 IORESOURCE_MEM));
9d5c8243
AK		 1514err_pci_reg:
1515err_dma:
1516 pci_disable_device(pdev);
1517 return err;
1518}
1519
1520/**
1521 * igb_remove - Device Removal Routine
1522 * @pdev: PCI device information struct
1523 *
1524 * igb_remove is called by the PCI subsystem to alert the driver
1525 * that it should release a PCI device. The could be caused by a
1526 * Hot-Plug event, or because the driver is going to be removed from
1527 * memory.
1528 **/
1529static void __devexit igb_remove(struct pci_dev *pdev)
1530{
1531 struct net_device *netdev = pci_get_drvdata(pdev);
1532 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1533 struct e1000_hw *hw = &adapter->hw;
ea943d41 1534 int err;
9d5c8243
AK		 1535
1536 /* flush_scheduled work may reschedule our watchdog task, so
1537 * explicitly disable watchdog tasks from being rescheduled */
1538 set_bit(__IGB_DOWN, &adapter->state);
1539 del_timer_sync(&adapter->watchdog_timer);
1540 del_timer_sync(&adapter->phy_info_timer);
1541
1542 flush_scheduled_work();
1543
421e02f0 1544#ifdef CONFIG_IGB_DCA
7dfc16fa 1545 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1546 dev_info(&pdev->dev, "DCA disabled\n");
1547 dca_remove_requester(&pdev->dev);
7dfc16fa 1548 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1549 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1550 }
1551#endif
1552
9d5c8243
AK		 1553 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1554 * would have already happened in close and is redundant. */
1555 igb_release_hw_control(adapter);
1556
1557 unregister_netdev(netdev);
1558
f5f4cf08
AD		 1559 if (!igb_check_reset_block(&adapter->hw))
1560 igb_reset_phy(&adapter->hw);
9d5c8243 1561
9d5c8243
AK		 1562 igb_reset_interrupt_capability(adapter);
1563
a88f10ec 1564 igb_free_queues(adapter);
9d5c8243 1565
37680117
AD		 1566#ifdef CONFIG_PCI_IOV
1567 /* reclaim resources allocated to VFs */
1568 if (adapter->vf_data) {
1569 /* disable iov and allow time for transactions to clear */
1570 pci_disable_sriov(pdev);
1571 msleep(500);
1572
1573 kfree(adapter->vf_data);
1574 adapter->vf_data = NULL;
1575 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1576 msleep(100);
1577 dev_info(&pdev->dev, "IOV Disabled\n");
1578 }
1579#endif
28b0759c
AD		 1580 iounmap(hw->hw_addr);
1581 if (hw->flash_address)
1582 iounmap(hw->flash_address);
aed5dec3
AD		 1583 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1584 IORESOURCE_MEM));
9d5c8243
AK		 1585
1586 free_netdev(netdev);
1587
ea943d41
JK		 1588 err = pci_disable_pcie_error_reporting(pdev);
1589 if (err)
1590 dev_err(&pdev->dev,
1591 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1592
9d5c8243
AK		 1593 pci_disable_device(pdev);
1594}
1595
1596/**
1597 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1598 * @adapter: board private structure to initialize
1599 *
1600 * igb_sw_init initializes the Adapter private data structure.
1601 * Fields are initialized based on PCI device information and
1602 * OS network device settings (MTU size).
1603 **/
1604static int __devinit igb_sw_init(struct igb_adapter *adapter)
1605{
1606 struct e1000_hw *hw = &adapter->hw;
1607 struct net_device *netdev = adapter->netdev;
1608 struct pci_dev *pdev = adapter->pdev;
1609
1610 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1611
68fd9910
AD		 1612 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1613 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1614 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1615 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1616 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1617 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1618
661086df
PWJ		 1619 /* This call may decrease the number of queues depending on
1620 * interrupt mode. */
9d5c8243
AK		 1621 igb_set_interrupt_capability(adapter);
1622
1623 if (igb_alloc_queues(adapter)) {
1624 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1625 return -ENOMEM;
1626 }
1627
1628 /* Explicitly disable IRQ since the NIC can be in any state. */
1629 igb_irq_disable(adapter);
1630
1631 set_bit(__IGB_DOWN, &adapter->state);
1632 return 0;
1633}
1634
1635/**
1636 * igb_open - Called when a network interface is made active
1637 * @netdev: network interface device structure
1638 *
1639 * Returns 0 on success, negative value on failure
1640 *
1641 * The open entry point is called when a network interface is made
1642 * active by the system (IFF_UP). At this point all resources needed
1643 * for transmit and receive operations are allocated, the interrupt
1644 * handler is registered with the OS, the watchdog timer is started,
1645 * and the stack is notified that the interface is ready.
1646 **/
1647static int igb_open(struct net_device *netdev)
1648{
1649 struct igb_adapter *adapter = netdev_priv(netdev);
1650 struct e1000_hw *hw = &adapter->hw;
1651 int err;
1652 int i;
1653
1654 /* disallow open during test */
1655 if (test_bit(__IGB_TESTING, &adapter->state))
1656 return -EBUSY;
1657
1658 /* allocate transmit descriptors */
1659 err = igb_setup_all_tx_resources(adapter);
1660 if (err)
1661 goto err_setup_tx;
1662
1663 /* allocate receive descriptors */
1664 err = igb_setup_all_rx_resources(adapter);
1665 if (err)
1666 goto err_setup_rx;
1667
1668 /* e1000_power_up_phy(adapter); */
1669
1670 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1671 if ((adapter->hw.mng_cookie.status &
1672 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1673 igb_update_mng_vlan(adapter);
1674
1675 /* before we allocate an interrupt, we must be ready to handle it.
1676 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1677 * as soon as we call pci_request_irq, so we have to setup our
1678 * clean_rx handler before we do so. */
1679 igb_configure(adapter);
1680
4ae196df 1681 igb_vmm_control(adapter);
e1739522
AD		 1682 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1683 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1684
9d5c8243
AK		 1685 err = igb_request_irq(adapter);
1686 if (err)
1687 goto err_req_irq;
1688
1689 /* From here on the code is the same as igb_up() */
1690 clear_bit(__IGB_DOWN, &adapter->state);
1691
844290e5
PW		 1692 for (i = 0; i < adapter->num_rx_queues; i++)
1693 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1694
1695 /* Clear any pending interrupts. */
1696 rd32(E1000_ICR);
844290e5
PW		 1697
1698 igb_irq_enable(adapter);
1699
d55b53ff
JK		 1700 netif_tx_start_all_queues(netdev);
1701
9d5c8243
AK		 1702 /* Fire a link status change interrupt to start the watchdog. */
1703 wr32(E1000_ICS, E1000_ICS_LSC);
1704
1705 return 0;
1706
1707err_req_irq:
1708 igb_release_hw_control(adapter);
1709 /* e1000_power_down_phy(adapter); */
1710 igb_free_all_rx_resources(adapter);
1711err_setup_rx:
1712 igb_free_all_tx_resources(adapter);
1713err_setup_tx:
1714 igb_reset(adapter);
1715
1716 return err;
1717}
1718
1719/**
1720 * igb_close - Disables a network interface
1721 * @netdev: network interface device structure
1722 *
1723 * Returns 0, this is not allowed to fail
1724 *
1725 * The close entry point is called when an interface is de-activated
1726 * by the OS. The hardware is still under the driver's control, but
1727 * needs to be disabled. A global MAC reset is issued to stop the
1728 * hardware, and all transmit and receive resources are freed.
1729 **/
1730static int igb_close(struct net_device *netdev)
1731{
1732 struct igb_adapter *adapter = netdev_priv(netdev);
1733
1734 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1735 igb_down(adapter);
1736
1737 igb_free_irq(adapter);
1738
1739 igb_free_all_tx_resources(adapter);
1740 igb_free_all_rx_resources(adapter);
1741
1742 /* kill manageability vlan ID if supported, but not if a vlan with
1743 * the same ID is registered on the host OS (let 8021q kill it) */
1744 if ((adapter->hw.mng_cookie.status &
1745 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1746 !(adapter->vlgrp &&
1747 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1748 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1749
1750 return 0;
1751}
1752
1753/**
1754 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1755 * @adapter: board private structure
1756 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1757 *
1758 * Return 0 on success, negative on failure
1759 **/
9d5c8243
AK		 1760int igb_setup_tx_resources(struct igb_adapter *adapter,
1761 struct igb_ring *tx_ring)
1762{
1763 struct pci_dev *pdev = adapter->pdev;
1764 int size;
1765
1766 size = sizeof(struct igb_buffer) * tx_ring->count;
1767 tx_ring->buffer_info = vmalloc(size);
1768 if (!tx_ring->buffer_info)
1769 goto err;
1770 memset(tx_ring->buffer_info, 0, size);
1771
1772 /* round up to nearest 4K */
85e8d004 1773 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 1774 tx_ring->size = ALIGN(tx_ring->size, 4096);
1775
1776 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1777 &tx_ring->dma);
1778
1779 if (!tx_ring->desc)
1780 goto err;
1781
1782 tx_ring->adapter = adapter;
1783 tx_ring->next_to_use = 0;
1784 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1785 return 0;
1786
1787err:
1788 vfree(tx_ring->buffer_info);
1789 dev_err(&adapter->pdev->dev,
1790 "Unable to allocate memory for the transmit descriptor ring\n");
1791 return -ENOMEM;
1792}
1793
1794/**
1795 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1796 * (Descriptors) for all queues
1797 * @adapter: board private structure
1798 *
1799 * Return 0 on success, negative on failure
1800 **/
1801static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1802{
1803 int i, err = 0;
661086df 1804 int r_idx;
9d5c8243
AK		 1805
1806 for (i = 0; i < adapter->num_tx_queues; i++) {
1807 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1808 if (err) {
1809 dev_err(&adapter->pdev->dev,
1810 "Allocation for Tx Queue %u failed\n", i);
1811 for (i--; i >= 0; i--)
3b644cf6 1812 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1813 break;
1814 }
1815 }
1816
661086df
PWJ		 1817 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1818 r_idx = i % adapter->num_tx_queues;
1819 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1820 }
9d5c8243
AK		 1821 return err;
1822}
1823
1824/**
1825 * igb_configure_tx - Configure transmit Unit after Reset
1826 * @adapter: board private structure
1827 *
1828 * Configure the Tx unit of the MAC after a reset.
1829 **/
1830static void igb_configure_tx(struct igb_adapter *adapter)
1831{
0e014cb1 1832 u64 tdba;
9d5c8243
AK		 1833 struct e1000_hw *hw = &adapter->hw;
1834 u32 tctl;
1835 u32 txdctl, txctrl;
26bc19ec 1836 int i, j;
9d5c8243
AK		 1837
1838 for (i = 0; i < adapter->num_tx_queues; i++) {
73cd78f1 1839 struct igb_ring *ring = &adapter->tx_ring[i];
26bc19ec
AD		 1840 j = ring->reg_idx;
1841 wr32(E1000_TDLEN(j),
85e8d004 1842 ring->count * sizeof(union e1000_adv_tx_desc));
9d5c8243 1843 tdba = ring->dma;
26bc19ec 1844 wr32(E1000_TDBAL(j),
73cd78f1 1845 tdba & 0x00000000ffffffffULL);
26bc19ec 1846 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1847
26bc19ec
AD		 1848 ring->head = E1000_TDH(j);
1849 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1850 writel(0, hw->hw_addr + ring->tail);
1851 writel(0, hw->hw_addr + ring->head);
26bc19ec 1852 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1853 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1854 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1855
1856 /* Turn off Relaxed Ordering on head write-backs. The
1857 * writebacks MUST be delivered in order or it will
1858 * completely screw up our bookeeping.
1859 */
26bc19ec 1860 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1861 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1862 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1863 }
1864
e1739522
AD		 1865 /* disable queue 0 to prevent tail bump w/o re-configuration */
1866 if (adapter->vfs_allocated_count)
1867 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 1868
1869 /* Program the Transmit Control Register */
9d5c8243
AK		 1870 tctl = rd32(E1000_TCTL);
1871 tctl &= ~E1000_TCTL_CT;
1872 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1873 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1874
1875 igb_config_collision_dist(hw);
1876
1877 /* Setup Transmit Descriptor Settings for eop descriptor */
1878 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1879
1880 /* Enable transmits */
1881 tctl |= E1000_TCTL_EN;
1882
1883 wr32(E1000_TCTL, tctl);
1884}
1885
1886/**
1887 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1888 * @adapter: board private structure
1889 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1890 *
1891 * Returns 0 on success, negative on failure
1892 **/
9d5c8243
AK		 1893int igb_setup_rx_resources(struct igb_adapter *adapter,
1894 struct igb_ring *rx_ring)
1895{
1896 struct pci_dev *pdev = adapter->pdev;
1897 int size, desc_len;
1898
1899 size = sizeof(struct igb_buffer) * rx_ring->count;
1900 rx_ring->buffer_info = vmalloc(size);
1901 if (!rx_ring->buffer_info)
1902 goto err;
1903 memset(rx_ring->buffer_info, 0, size);
1904
1905 desc_len = sizeof(union e1000_adv_rx_desc);
1906
1907 /* Round up to nearest 4K */
1908 rx_ring->size = rx_ring->count * desc_len;
1909 rx_ring->size = ALIGN(rx_ring->size, 4096);
1910
1911 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1912 &rx_ring->dma);
1913
1914 if (!rx_ring->desc)
1915 goto err;
1916
1917 rx_ring->next_to_clean = 0;
1918 rx_ring->next_to_use = 0;
9d5c8243
AK		 1919
1920 rx_ring->adapter = adapter;
9d5c8243
AK		 1921
1922 return 0;
1923
1924err:
1925 vfree(rx_ring->buffer_info);
1926 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1927 "the receive descriptor ring\n");
1928 return -ENOMEM;
1929}
1930
1931/**
1932 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1933 * (Descriptors) for all queues
1934 * @adapter: board private structure
1935 *
1936 * Return 0 on success, negative on failure
1937 **/
1938static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1939{
1940 int i, err = 0;
1941
1942 for (i = 0; i < adapter->num_rx_queues; i++) {
1943 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1944 if (err) {
1945 dev_err(&adapter->pdev->dev,
1946 "Allocation for Rx Queue %u failed\n", i);
1947 for (i--; i >= 0; i--)
3b644cf6 1948 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1949 break;
1950 }
1951 }
1952
1953 return err;
1954}
1955
1956/**
1957 * igb_setup_rctl - configure the receive control registers
1958 * @adapter: Board private structure
1959 **/
1960static void igb_setup_rctl(struct igb_adapter *adapter)
1961{
1962 struct e1000_hw *hw = &adapter->hw;
1963 u32 rctl;
1964 u32 srrctl = 0;
26bc19ec 1965 int i, j;
9d5c8243
AK		 1966
1967 rctl = rd32(E1000_RCTL);
1968
1969 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1970 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1971
69d728ba 1972 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 1973 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 1974
87cb7e8c
AK		 1975 /*
1976 * enable stripping of CRC. It's unlikely this will break BMC
1977 * redirection as it did with e1000. Newer features require
1978 * that the HW strips the CRC.
73cd78f1 1979 */
87cb7e8c 1980 rctl |= E1000_RCTL_SECRC;
9d5c8243 1981
9b07f3d3 1982 /*
ec54d7d6 1983 * disable store bad packets and clear size bits.
9b07f3d3 1984 */
ec54d7d6 1985 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 1986
ec54d7d6 1987 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 1988 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 1989
1990 /* Setup buffer sizes */
1991 switch (adapter->rx_buffer_len) {
1992 case IGB_RXBUFFER_256:
1993 rctl |= E1000_RCTL_SZ_256;
1994 break;
1995 case IGB_RXBUFFER_512:
1996 rctl |= E1000_RCTL_SZ_512;
1997 break;
1998 default:
1999 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2000 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2001 break;
9d5c8243
AK		 2002 }
2003
2004 /* 82575 and greater support packet-split where the protocol
2005 * header is placed in skb->data and the packet data is
2006 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2007 * In the case of a non-split, skb->data is linearly filled,
2008 * followed by the page buffers. Therefore, skb->data is
2009 * sized to hold the largest protocol header.
2010 */
2011 /* allocations using alloc_page take too long for regular MTU
2012 * so only enable packet split for jumbo frames */
ec54d7d6 2013 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 2014 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 2015 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 2016 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 2017 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2018 } else {
2019 adapter->rx_ps_hdr_size = 0;
2020 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2021 }
2022
e1739522
AD		 2023 /* Attention!!! For SR-IOV PF driver operations you must enable
2024 * queue drop for all VF and PF queues to prevent head of line blocking
2025 * if an un-trusted VF does not provide descriptors to hardware.
2026 */
2027 if (adapter->vfs_allocated_count) {
2028 u32 vmolr;
2029
2030 j = adapter->rx_ring[0].reg_idx;
2031
2032 /* set all queue drop enable bits */
2033 wr32(E1000_QDE, ALL_QUEUES);
2034 srrctl |= E1000_SRRCTL_DROP_EN;
2035
2036 /* disable queue 0 to prevent tail write w/o re-config */
2037 wr32(E1000_RXDCTL(0), 0);
2038
2039 vmolr = rd32(E1000_VMOLR(j));
2040 if (rctl & E1000_RCTL_LPE)
2041 vmolr |= E1000_VMOLR_LPE;
2042 if (adapter->num_rx_queues > 0)
2043 vmolr |= E1000_VMOLR_RSSE;
2044 wr32(E1000_VMOLR(j), vmolr);
2045 }
2046
26bc19ec
AD		 2047 for (i = 0; i < adapter->num_rx_queues; i++) {
2048 j = adapter->rx_ring[i].reg_idx;
2049 wr32(E1000_SRRCTL(j), srrctl);
2050 }
9d5c8243
AK		 2051
2052 wr32(E1000_RCTL, rctl);
2053}
2054
e1739522
AD		 2055/**
2056 * igb_rlpml_set - set maximum receive packet size
2057 * @adapter: board private structure
2058 *
2059 * Configure maximum receivable packet size.
2060 **/
2061static void igb_rlpml_set(struct igb_adapter *adapter)
2062{
2063 u32 max_frame_size = adapter->max_frame_size;
2064 struct e1000_hw *hw = &adapter->hw;
2065 u16 pf_id = adapter->vfs_allocated_count;
2066
2067 if (adapter->vlgrp)
2068 max_frame_size += VLAN_TAG_SIZE;
2069
2070 /* if vfs are enabled we set RLPML to the largest possible request
2071 * size and set the VMOLR RLPML to the size we need */
2072 if (pf_id) {
2073 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2074 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2075 }
2076
2077 wr32(E1000_RLPML, max_frame_size);
2078}
2079
2080/**
2081 * igb_configure_vt_default_pool - Configure VT default pool
2082 * @adapter: board private structure
2083 *
2084 * Configure the default pool
2085 **/
2086static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2087{
2088 struct e1000_hw *hw = &adapter->hw;
2089 u16 pf_id = adapter->vfs_allocated_count;
2090 u32 vtctl;
2091
2092 /* not in sr-iov mode - do nothing */
2093 if (!pf_id)
2094 return;
2095
2096 vtctl = rd32(E1000_VT_CTL);
2097 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2098 E1000_VT_CTL_DISABLE_DEF_POOL);
2099 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2100 wr32(E1000_VT_CTL, vtctl);
2101}
2102
9d5c8243
AK		 2103/**
2104 * igb_configure_rx - Configure receive Unit after Reset
2105 * @adapter: board private structure
2106 *
2107 * Configure the Rx unit of the MAC after a reset.
2108 **/
2109static void igb_configure_rx(struct igb_adapter *adapter)
2110{
2111 u64 rdba;
2112 struct e1000_hw *hw = &adapter->hw;
2113 u32 rctl, rxcsum;
2114 u32 rxdctl;
9107584e 2115 int i;
9d5c8243
AK		 2116
2117 /* disable receives while setting up the descriptors */
2118 rctl = rd32(E1000_RCTL);
2119 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2120 wrfl();
2121 mdelay(10);
2122
2123 if (adapter->itr_setting > 3)
6eb5a7f1 2124 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 2125
2126 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2127 * the Base and Length of the Rx Descriptor Ring */
2128 for (i = 0; i < adapter->num_rx_queues; i++) {
73cd78f1 2129 struct igb_ring *ring = &adapter->rx_ring[i];
9107584e 2130 int j = ring->reg_idx;
9d5c8243 2131 rdba = ring->dma;
26bc19ec 2132 wr32(E1000_RDBAL(j),
73cd78f1 2133 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 2134 wr32(E1000_RDBAH(j), rdba >> 32);
2135 wr32(E1000_RDLEN(j),
73cd78f1 2136 ring->count * sizeof(union e1000_adv_rx_desc));
9d5c8243 2137
26bc19ec
AD		 2138 ring->head = E1000_RDH(j);
2139 ring->tail = E1000_RDT(j);
9d5c8243
AK		 2140 writel(0, hw->hw_addr + ring->tail);
2141 writel(0, hw->hw_addr + ring->head);
2142
26bc19ec 2143 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 2144 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2145 rxdctl &= 0xFFF00000;
2146 rxdctl |= IGB_RX_PTHRESH;
2147 rxdctl |= IGB_RX_HTHRESH << 8;
2148 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 2149 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 2150 }
2151
2152 if (adapter->num_rx_queues > 1) {
2153 u32 random[10];
2154 u32 mrqc;
2155 u32 j, shift;
2156 union e1000_reta {
2157 u32 dword;
2158 u8 bytes[4];
2159 } reta;
2160
2161 get_random_bytes(&random[0], 40);
2162
2d064c06
AD		 2163 if (hw->mac.type >= e1000_82576)
2164 shift = 0;
2165 else
2166 shift = 6;
9d5c8243
AK		 2167 for (j = 0; j < (32 * 4); j++) {
2168 reta.bytes[j & 3] =
26bc19ec 2169 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2170 if ((j & 3) == 3)
2171 writel(reta.dword,
2172 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2173 }
e1739522
AD		 2174 if (adapter->vfs_allocated_count)
2175 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2176 else
2177 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
9d5c8243
AK		 2178
2179 /* Fill out hash function seeds */
2180 for (j = 0; j < 10; j++)
2181 array_wr32(E1000_RSSRK(0), j, random[j]);
2182
2183 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2184 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2185 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2186 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2187 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2188 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2189 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2190 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2191
2192
2193 wr32(E1000_MRQC, mrqc);
2194
2195 /* Multiqueue and raw packet checksumming are mutually
2196 * exclusive. Note that this not the same as TCP/IP
2197 * checksumming, which works fine. */
2198 rxcsum = rd32(E1000_RXCSUM);
2199 rxcsum |= E1000_RXCSUM_PCSD;
2200 wr32(E1000_RXCSUM, rxcsum);
2201 } else {
e1739522
AD		 2202 /* Enable multi-queue for sr-iov */
2203 if (adapter->vfs_allocated_count)
2204 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
9d5c8243
AK		 2205 /* Enable Receive Checksum Offload for TCP and UDP */
2206 rxcsum = rd32(E1000_RXCSUM);
56fbbb4e
AD		 2207 if (adapter->rx_csum)
2208 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE;
2209 else
2210 rxcsum &= ~(E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE);
2211
9d5c8243
AK		 2212 wr32(E1000_RXCSUM, rxcsum);
2213 }
2214
e1739522
AD		 2215 /* Set the default pool for the PF's first queue */
2216 igb_configure_vt_default_pool(adapter);
2217
2218 igb_rlpml_set(adapter);
9d5c8243
AK		 2219
2220 /* Enable Receives */
2221 wr32(E1000_RCTL, rctl);
2222}
2223
2224/**
2225 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2226 * @tx_ring: Tx descriptor ring for a specific queue
2227 *
2228 * Free all transmit software resources
2229 **/
68fd9910 2230void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2231{
3b644cf6 2232 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2233
3b644cf6 2234 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2235
2236 vfree(tx_ring->buffer_info);
2237 tx_ring->buffer_info = NULL;
2238
2239 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2240
2241 tx_ring->desc = NULL;
2242}
2243
2244/**
2245 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2246 * @adapter: board private structure
2247 *
2248 * Free all transmit software resources
2249 **/
2250static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2251{
2252 int i;
2253
2254 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2255 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2256}
2257
2258static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2259 struct igb_buffer *buffer_info)
2260{
2261 if (buffer_info->dma) {
2262 pci_unmap_page(adapter->pdev,
2263 buffer_info->dma,
2264 buffer_info->length,
2265 PCI_DMA_TODEVICE);
2266 buffer_info->dma = 0;
2267 }
2268 if (buffer_info->skb) {
2269 dev_kfree_skb_any(buffer_info->skb);
2270 buffer_info->skb = NULL;
2271 }
2272 buffer_info->time_stamp = 0;
73cd78f1 2273 buffer_info->next_to_watch = 0;
9d5c8243
AK		 2274 /* buffer_info must be completely set up in the transmit path */
2275}
2276
2277/**
2278 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2279 * @tx_ring: ring to be cleaned
2280 **/
3b644cf6 2281static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2282{
3b644cf6 2283 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2284 struct igb_buffer *buffer_info;
2285 unsigned long size;
2286 unsigned int i;
2287
2288 if (!tx_ring->buffer_info)
2289 return;
2290 /* Free all the Tx ring sk_buffs */
2291
2292 for (i = 0; i < tx_ring->count; i++) {
2293 buffer_info = &tx_ring->buffer_info[i];
2294 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2295 }
2296
2297 size = sizeof(struct igb_buffer) * tx_ring->count;
2298 memset(tx_ring->buffer_info, 0, size);
2299
2300 /* Zero out the descriptor ring */
2301
2302 memset(tx_ring->desc, 0, tx_ring->size);
2303
2304 tx_ring->next_to_use = 0;
2305 tx_ring->next_to_clean = 0;
2306
2307 writel(0, adapter->hw.hw_addr + tx_ring->head);
2308 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2309}
2310
2311/**
2312 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2313 * @adapter: board private structure
2314 **/
2315static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2316{
2317 int i;
2318
2319 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2320 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2321}
2322
2323/**
2324 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2325 * @rx_ring: ring to clean the resources from
2326 *
2327 * Free all receive software resources
2328 **/
68fd9910 2329void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2330{
3b644cf6 2331 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2332
3b644cf6 2333 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2334
2335 vfree(rx_ring->buffer_info);
2336 rx_ring->buffer_info = NULL;
2337
2338 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2339
2340 rx_ring->desc = NULL;
2341}
2342
2343/**
2344 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2345 * @adapter: board private structure
2346 *
2347 * Free all receive software resources
2348 **/
2349static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2350{
2351 int i;
2352
2353 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2354 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2355}
2356
2357/**
2358 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2359 * @rx_ring: ring to free buffers from
2360 **/
3b644cf6 2361static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2362{
3b644cf6 2363 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2364 struct igb_buffer *buffer_info;
2365 struct pci_dev *pdev = adapter->pdev;
2366 unsigned long size;
2367 unsigned int i;
2368
2369 if (!rx_ring->buffer_info)
2370 return;
2371 /* Free all the Rx ring sk_buffs */
2372 for (i = 0; i < rx_ring->count; i++) {
2373 buffer_info = &rx_ring->buffer_info[i];
2374 if (buffer_info->dma) {
2375 if (adapter->rx_ps_hdr_size)
2376 pci_unmap_single(pdev, buffer_info->dma,
2377 adapter->rx_ps_hdr_size,
2378 PCI_DMA_FROMDEVICE);
2379 else
2380 pci_unmap_single(pdev, buffer_info->dma,
2381 adapter->rx_buffer_len,
2382 PCI_DMA_FROMDEVICE);
2383 buffer_info->dma = 0;
2384 }
2385
2386 if (buffer_info->skb) {
2387 dev_kfree_skb(buffer_info->skb);
2388 buffer_info->skb = NULL;
2389 }
2390 if (buffer_info->page) {
bf36c1a0
AD		 2391 if (buffer_info->page_dma)
2392 pci_unmap_page(pdev, buffer_info->page_dma,
2393 PAGE_SIZE / 2,
2394 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2395 put_page(buffer_info->page);
2396 buffer_info->page = NULL;
2397 buffer_info->page_dma = 0;
bf36c1a0 2398 buffer_info->page_offset = 0;
9d5c8243
AK		 2399 }
2400 }
2401
9d5c8243
AK		 2402 size = sizeof(struct igb_buffer) * rx_ring->count;
2403 memset(rx_ring->buffer_info, 0, size);
2404
2405 /* Zero out the descriptor ring */
2406 memset(rx_ring->desc, 0, rx_ring->size);
2407
2408 rx_ring->next_to_clean = 0;
2409 rx_ring->next_to_use = 0;
2410
2411 writel(0, adapter->hw.hw_addr + rx_ring->head);
2412 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2413}
2414
2415/**
2416 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2417 * @adapter: board private structure
2418 **/
2419static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2420{
2421 int i;
2422
2423 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2424 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2425}
2426
2427/**
2428 * igb_set_mac - Change the Ethernet Address of the NIC
2429 * @netdev: network interface device structure
2430 * @p: pointer to an address structure
2431 *
2432 * Returns 0 on success, negative on failure
2433 **/
2434static int igb_set_mac(struct net_device *netdev, void *p)
2435{
2436 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2437 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2438 struct sockaddr *addr = p;
2439
2440 if (!is_valid_ether_addr(addr->sa_data))
2441 return -EADDRNOTAVAIL;
2442
2443 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2444 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2445
28b0759c 2446 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
9d5c8243 2447
e1739522
AD		 2448 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2449
9d5c8243
AK		 2450 return 0;
2451}
2452
2453/**
2454 * igb_set_multi - Multicast and Promiscuous mode set
2455 * @netdev: network interface device structure
2456 *
2457 * The set_multi entry point is called whenever the multicast address
2458 * list or the network interface flags are updated. This routine is
2459 * responsible for configuring the hardware for proper multicast,
2460 * promiscuous mode, and all-multi behavior.
2461 **/
2462static void igb_set_multi(struct net_device *netdev)
2463{
2464 struct igb_adapter *adapter = netdev_priv(netdev);
2465 struct e1000_hw *hw = &adapter->hw;
2466 struct e1000_mac_info *mac = &hw->mac;
2467 struct dev_mc_list *mc_ptr;
2468 u8 *mta_list;
2469 u32 rctl;
2470 int i;
2471
2472 /* Check for Promiscuous and All Multicast modes */
2473
2474 rctl = rd32(E1000_RCTL);
2475
746b9f02 2476 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2477 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2478 rctl &= ~E1000_RCTL_VFE;
2479 } else {
2480 if (netdev->flags & IFF_ALLMULTI) {
2481 rctl |= E1000_RCTL_MPE;
2482 rctl &= ~E1000_RCTL_UPE;
2483 } else
2484 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2485 rctl |= E1000_RCTL_VFE;
746b9f02 2486 }
9d5c8243
AK		 2487 wr32(E1000_RCTL, rctl);
2488
2489 if (!netdev->mc_count) {
2490 /* nothing to program, so clear mc list */
8a900862
AD		 2491 igb_update_mc_addr_list(hw, NULL, 0, 1,
2492 mac->rar_entry_count);
9d5c8243
AK		 2493 return;
2494 }
2495
2496 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2497 if (!mta_list)
2498 return;
2499
2500 /* The shared function expects a packed array of only addresses. */
2501 mc_ptr = netdev->mc_list;
2502
2503 for (i = 0; i < netdev->mc_count; i++) {
2504 if (!mc_ptr)
2505 break;
2506 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2507 mc_ptr = mc_ptr->next;
2508 }
e1739522
AD		 2509 igb_update_mc_addr_list(hw, mta_list, i,
2510 adapter->vfs_allocated_count + 1,
2511 mac->rar_entry_count);
2512
2513 igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
4ae196df
AD		 2514 igb_restore_vf_multicasts(adapter);
2515
9d5c8243
AK		 2516 kfree(mta_list);
2517}
2518
2519/* Need to wait a few seconds after link up to get diagnostic information from
2520 * the phy */
2521static void igb_update_phy_info(unsigned long data)
2522{
2523 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2524 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2525}
2526
4d6b725e
AD		 2527/**
2528 * igb_has_link - check shared code for link and determine up/down
2529 * @adapter: pointer to driver private info
2530 **/
2531static bool igb_has_link(struct igb_adapter *adapter)
2532{
2533 struct e1000_hw *hw = &adapter->hw;
2534 bool link_active = false;
2535 s32 ret_val = 0;
2536
2537 /* get_link_status is set on LSC (link status) interrupt or
2538 * rx sequence error interrupt. get_link_status will stay
2539 * false until the e1000_check_for_link establishes link
2540 * for copper adapters ONLY
2541 */
2542 switch (hw->phy.media_type) {
2543 case e1000_media_type_copper:
2544 if (hw->mac.get_link_status) {
2545 ret_val = hw->mac.ops.check_for_link(hw);
2546 link_active = !hw->mac.get_link_status;
2547 } else {
2548 link_active = true;
2549 }
2550 break;
2551 case e1000_media_type_fiber:
2552 ret_val = hw->mac.ops.check_for_link(hw);
2553 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2554 break;
2555 case e1000_media_type_internal_serdes:
2556 ret_val = hw->mac.ops.check_for_link(hw);
2557 link_active = hw->mac.serdes_has_link;
2558 break;
2559 default:
2560 case e1000_media_type_unknown:
2561 break;
2562 }
2563
2564 return link_active;
2565}
2566
9d5c8243
AK		 2567/**
2568 * igb_watchdog - Timer Call-back
2569 * @data: pointer to adapter cast into an unsigned long
2570 **/
2571static void igb_watchdog(unsigned long data)
2572{
2573 struct igb_adapter *adapter = (struct igb_adapter *)data;
2574 /* Do the rest outside of interrupt context */
2575 schedule_work(&adapter->watchdog_task);
2576}
2577
2578static void igb_watchdog_task(struct work_struct *work)
2579{
2580 struct igb_adapter *adapter = container_of(work,
2581 struct igb_adapter, watchdog_task);
2582 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2583 struct net_device *netdev = adapter->netdev;
2584 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2585 u32 link;
7a6ea550 2586 u32 eics = 0;
7a6ea550 2587 int i;
9d5c8243 2588
4d6b725e
AD		 2589 link = igb_has_link(adapter);
2590 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2591 goto link_up;
2592
9d5c8243
AK		 2593 if (link) {
2594 if (!netif_carrier_ok(netdev)) {
2595 u32 ctrl;
2596 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2597 &adapter->link_speed,
2598 &adapter->link_duplex);
2599
2600 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2601 /* Links status message must follow this format */
2602 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2603 "Flow Control: %s\n",
527d47c1 2604 netdev->name,
9d5c8243
AK		 2605 adapter->link_speed,
2606 adapter->link_duplex == FULL_DUPLEX ?
2607 "Full Duplex" : "Half Duplex",
2608 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2609 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2610 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2611 E1000_CTRL_TFCE) ? "TX" : "None")));
2612
2613 /* tweak tx_queue_len according to speed/duplex and
2614 * adjust the timeout factor */
2615 netdev->tx_queue_len = adapter->tx_queue_len;
2616 adapter->tx_timeout_factor = 1;
2617 switch (adapter->link_speed) {
2618 case SPEED_10:
2619 netdev->tx_queue_len = 10;
2620 adapter->tx_timeout_factor = 14;
2621 break;
2622 case SPEED_100:
2623 netdev->tx_queue_len = 100;
2624 /* maybe add some timeout factor ? */
2625 break;
2626 }
2627
2628 netif_carrier_on(netdev);
fd2ea0a7 2629 netif_tx_wake_all_queues(netdev);
9d5c8243 2630
4ae196df
AD		 2631 igb_ping_all_vfs(adapter);
2632
4b1a9877 2633 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2634 if (!test_bit(__IGB_DOWN, &adapter->state))
2635 mod_timer(&adapter->phy_info_timer,
2636 round_jiffies(jiffies + 2 * HZ));
2637 }
2638 } else {
2639 if (netif_carrier_ok(netdev)) {
2640 adapter->link_speed = 0;
2641 adapter->link_duplex = 0;
527d47c1
AD		 2642 /* Links status message must follow this format */
2643 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2644 netdev->name);
9d5c8243 2645 netif_carrier_off(netdev);
fd2ea0a7 2646 netif_tx_stop_all_queues(netdev);
4b1a9877 2647
4ae196df
AD		 2648 igb_ping_all_vfs(adapter);
2649
4b1a9877 2650 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2651 if (!test_bit(__IGB_DOWN, &adapter->state))
2652 mod_timer(&adapter->phy_info_timer,
2653 round_jiffies(jiffies + 2 * HZ));
2654 }
2655 }
2656
2657link_up:
2658 igb_update_stats(adapter);
2659
4b1a9877 2660 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2661 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2662 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2663 adapter->colc_old = adapter->stats.colc;
2664
2665 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2666 adapter->gorc_old = adapter->stats.gorc;
2667 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2668 adapter->gotc_old = adapter->stats.gotc;
2669
2670 igb_update_adaptive(&adapter->hw);
2671
2672 if (!netif_carrier_ok(netdev)) {
2673 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2674 /* We've lost link, so the controller stops DMA,
2675 * but we've got queued Tx work that's never going
2676 * to get done, so reset controller to flush Tx.
2677 * (Do the reset outside of interrupt context). */
2678 adapter->tx_timeout_count++;
2679 schedule_work(&adapter->reset_task);
2680 }
2681 }
2682
2683 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2684 if (adapter->msix_entries) {
2685 for (i = 0; i < adapter->num_rx_queues; i++)
2686 eics |= adapter->rx_ring[i].eims_value;
2687 wr32(E1000_EICS, eics);
2688 } else {
2689 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2690 }
9d5c8243
AK		 2691
2692 /* Force detection of hung controller every watchdog period */
2693 tx_ring->detect_tx_hung = true;
2694
2695 /* Reset the timer */
2696 if (!test_bit(__IGB_DOWN, &adapter->state))
2697 mod_timer(&adapter->watchdog_timer,
2698 round_jiffies(jiffies + 2 * HZ));
2699}
2700
2701enum latency_range {
2702 lowest_latency = 0,
2703 low_latency = 1,
2704 bulk_latency = 2,
2705 latency_invalid = 255
2706};
2707
2708
6eb5a7f1
AD		 2709/**
2710 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2711 *
2712 * Stores a new ITR value based on strictly on packet size. This
2713 * algorithm is less sophisticated than that used in igb_update_itr,
2714 * due to the difficulty of synchronizing statistics across multiple
2715 * receive rings. The divisors and thresholds used by this fuction
2716 * were determined based on theoretical maximum wire speed and testing
2717 * data, in order to minimize response time while increasing bulk
2718 * throughput.
2719 * This functionality is controlled by the InterruptThrottleRate module
2720 * parameter (see igb_param.c)
2721 * NOTE: This function is called only when operating in a multiqueue
2722 * receive environment.
2723 * @rx_ring: pointer to ring
2724 **/
2725static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2726{
6eb5a7f1
AD		 2727 int new_val = rx_ring->itr_val;
2728 int avg_wire_size = 0;
2729 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2730
6eb5a7f1
AD		 2731 if (!rx_ring->total_packets)
2732 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2733
6eb5a7f1
AD		 2734 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2735 * ints/sec - ITR timer value of 120 ticks.
2736 */
2737 if (adapter->link_speed != SPEED_1000) {
2738 new_val = 120;
2739 goto set_itr_val;
9d5c8243 2740 }
6eb5a7f1 2741 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2742
6eb5a7f1
AD		 2743 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2744 avg_wire_size += 24;
2745
2746 /* Don't starve jumbo frames */
2747 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2748
6eb5a7f1
AD		 2749 /* Give a little boost to mid-size frames */
2750 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2751 new_val = avg_wire_size / 3;
2752 else
2753 new_val = avg_wire_size / 2;
9d5c8243 2754
6eb5a7f1 2755set_itr_val:
9d5c8243
AK		 2756 if (new_val != rx_ring->itr_val) {
2757 rx_ring->itr_val = new_val;
6eb5a7f1 2758 rx_ring->set_itr = 1;
9d5c8243 2759 }
6eb5a7f1
AD		 2760clear_counts:
2761 rx_ring->total_bytes = 0;
2762 rx_ring->total_packets = 0;
9d5c8243
AK		 2763}
2764
2765/**
2766 * igb_update_itr - update the dynamic ITR value based on statistics
2767 * Stores a new ITR value based on packets and byte
2768 * counts during the last interrupt. The advantage of per interrupt
2769 * computation is faster updates and more accurate ITR for the current
2770 * traffic pattern. Constants in this function were computed
2771 * based on theoretical maximum wire speed and thresholds were set based
2772 * on testing data as well as attempting to minimize response time
2773 * while increasing bulk throughput.
2774 * this functionality is controlled by the InterruptThrottleRate module
2775 * parameter (see igb_param.c)
2776 * NOTE: These calculations are only valid when operating in a single-
2777 * queue environment.
2778 * @adapter: pointer to adapter
2779 * @itr_setting: current adapter->itr
2780 * @packets: the number of packets during this measurement interval
2781 * @bytes: the number of bytes during this measurement interval
2782 **/
2783static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2784 int packets, int bytes)
2785{
2786 unsigned int retval = itr_setting;
2787
2788 if (packets == 0)
2789 goto update_itr_done;
2790
2791 switch (itr_setting) {
2792 case lowest_latency:
2793 /* handle TSO and jumbo frames */
2794 if (bytes/packets > 8000)
2795 retval = bulk_latency;
2796 else if ((packets < 5) && (bytes > 512))
2797 retval = low_latency;
2798 break;
2799 case low_latency: /* 50 usec aka 20000 ints/s */
2800 if (bytes > 10000) {
2801 /* this if handles the TSO accounting */
2802 if (bytes/packets > 8000) {
2803 retval = bulk_latency;
2804 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2805 retval = bulk_latency;
2806 } else if ((packets > 35)) {
2807 retval = lowest_latency;
2808 }
2809 } else if (bytes/packets > 2000) {
2810 retval = bulk_latency;
2811 } else if (packets <= 2 && bytes < 512) {
2812 retval = lowest_latency;
2813 }
2814 break;
2815 case bulk_latency: /* 250 usec aka 4000 ints/s */
2816 if (bytes > 25000) {
2817 if (packets > 35)
2818 retval = low_latency;
1e5c3d21 2819 } else if (bytes < 1500) {
9d5c8243
AK		 2820 retval = low_latency;
2821 }
2822 break;
2823 }
2824
2825update_itr_done:
2826 return retval;
2827}
2828
6eb5a7f1 2829static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2830{
2831 u16 current_itr;
2832 u32 new_itr = adapter->itr;
2833
2834 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2835 if (adapter->link_speed != SPEED_1000) {
2836 current_itr = 0;
2837 new_itr = 4000;
2838 goto set_itr_now;
2839 }
2840
2841 adapter->rx_itr = igb_update_itr(adapter,
2842 adapter->rx_itr,
2843 adapter->rx_ring->total_packets,
2844 adapter->rx_ring->total_bytes);
9d5c8243 2845
6eb5a7f1 2846 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2847 adapter->tx_itr = igb_update_itr(adapter,
2848 adapter->tx_itr,
2849 adapter->tx_ring->total_packets,
2850 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2851 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2852 } else {
2853 current_itr = adapter->rx_itr;
2854 }
2855
6eb5a7f1 2856 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 2857 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 2858 current_itr = low_latency;
2859
9d5c8243
AK		 2860 switch (current_itr) {
2861 /* counts and packets in update_itr are dependent on these numbers */
2862 case lowest_latency:
2863 new_itr = 70000;
2864 break;
2865 case low_latency:
2866 new_itr = 20000; /* aka hwitr = ~200 */
2867 break;
2868 case bulk_latency:
2869 new_itr = 4000;
2870 break;
2871 default:
2872 break;
2873 }
2874
2875set_itr_now:
6eb5a7f1
AD		 2876 adapter->rx_ring->total_bytes = 0;
2877 adapter->rx_ring->total_packets = 0;
2878 if (adapter->rx_ring->buddy) {
2879 adapter->rx_ring->buddy->total_bytes = 0;
2880 adapter->rx_ring->buddy->total_packets = 0;
2881 }
2882
9d5c8243
AK		 2883 if (new_itr != adapter->itr) {
2884 /* this attempts to bias the interrupt rate towards Bulk
2885 * by adding intermediate steps when interrupt rate is
2886 * increasing */
2887 new_itr = new_itr > adapter->itr ?
2888 min(adapter->itr + (new_itr >> 2), new_itr) :
2889 new_itr;
2890 /* Don't write the value here; it resets the adapter's
2891 * internal timer, and causes us to delay far longer than
2892 * we should between interrupts. Instead, we write the ITR
2893 * value at the beginning of the next interrupt so the timing
2894 * ends up being correct.
2895 */
2896 adapter->itr = new_itr;
6eb5a7f1
AD		 2897 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2898 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2899 }
2900
2901 return;
2902}
2903
2904
2905#define IGB_TX_FLAGS_CSUM 0x00000001
2906#define IGB_TX_FLAGS_VLAN 0x00000002
2907#define IGB_TX_FLAGS_TSO 0x00000004
2908#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 2909#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 2910#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2911#define IGB_TX_FLAGS_VLAN_SHIFT 16
2912
2913static inline int igb_tso_adv(struct igb_adapter *adapter,
2914 struct igb_ring *tx_ring,
2915 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2916{
2917 struct e1000_adv_tx_context_desc *context_desc;
2918 unsigned int i;
2919 int err;
2920 struct igb_buffer *buffer_info;
2921 u32 info = 0, tu_cmd = 0;
2922 u32 mss_l4len_idx, l4len;
2923 *hdr_len = 0;
2924
2925 if (skb_header_cloned(skb)) {
2926 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2927 if (err)
2928 return err;
2929 }
2930
2931 l4len = tcp_hdrlen(skb);
2932 *hdr_len += l4len;
2933
2934 if (skb->protocol == htons(ETH_P_IP)) {
2935 struct iphdr *iph = ip_hdr(skb);
2936 iph->tot_len = 0;
2937 iph->check = 0;
2938 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2939 iph->daddr, 0,
2940 IPPROTO_TCP,
2941 0);
2942 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2943 ipv6_hdr(skb)->payload_len = 0;
2944 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2945 &ipv6_hdr(skb)->daddr,
2946 0, IPPROTO_TCP, 0);
2947 }
2948
2949 i = tx_ring->next_to_use;
2950
2951 buffer_info = &tx_ring->buffer_info[i];
2952 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2953 /* VLAN MACLEN IPLEN */
2954 if (tx_flags & IGB_TX_FLAGS_VLAN)
2955 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2956 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2957 *hdr_len += skb_network_offset(skb);
2958 info |= skb_network_header_len(skb);
2959 *hdr_len += skb_network_header_len(skb);
2960 context_desc->vlan_macip_lens = cpu_to_le32(info);
2961
2962 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2963 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2964
2965 if (skb->protocol == htons(ETH_P_IP))
2966 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2967 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2968
2969 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2970
2971 /* MSS L4LEN IDX */
2972 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2973 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2974
73cd78f1 2975 /* For 82575, context index must be unique per ring. */
7dfc16fa
AD		 2976 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2977 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2978
2979 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2980 context_desc->seqnum_seed = 0;
2981
2982 buffer_info->time_stamp = jiffies;
0e014cb1 2983 buffer_info->next_to_watch = i;
9d5c8243
AK		 2984 buffer_info->dma = 0;
2985 i++;
2986 if (i == tx_ring->count)
2987 i = 0;
2988
2989 tx_ring->next_to_use = i;
2990
2991 return true;
2992}
2993
2994static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2995 struct igb_ring *tx_ring,
2996 struct sk_buff *skb, u32 tx_flags)
2997{
2998 struct e1000_adv_tx_context_desc *context_desc;
2999 unsigned int i;
3000 struct igb_buffer *buffer_info;
3001 u32 info = 0, tu_cmd = 0;
3002
3003 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3004 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3005 i = tx_ring->next_to_use;
3006 buffer_info = &tx_ring->buffer_info[i];
3007 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3008
3009 if (tx_flags & IGB_TX_FLAGS_VLAN)
3010 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3011 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3012 if (skb->ip_summed == CHECKSUM_PARTIAL)
3013 info |= skb_network_header_len(skb);
3014
3015 context_desc->vlan_macip_lens = cpu_to_le32(info);
3016
3017 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3018
3019 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3 3020 switch (skb->protocol) {
09640e63 3021 case cpu_to_be16(ETH_P_IP):
9d5c8243 3022 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3023 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3024 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3025 break;
09640e63 3026 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3027 /* XXX what about other V6 headers?? */
3028 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3029 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3030 break;
3031 default:
3032 if (unlikely(net_ratelimit()))
3033 dev_warn(&adapter->pdev->dev,
3034 "partial checksum but proto=%x!\n",
3035 skb->protocol);
3036 break;
3037 }
9d5c8243
AK		 3038 }
3039
3040 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3041 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 3042 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3043 context_desc->mss_l4len_idx =
3044 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 3045 else
3046 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 3047
3048 buffer_info->time_stamp = jiffies;
0e014cb1 3049 buffer_info->next_to_watch = i;
9d5c8243
AK		 3050 buffer_info->dma = 0;
3051
3052 i++;
3053 if (i == tx_ring->count)
3054 i = 0;
3055 tx_ring->next_to_use = i;
3056
3057 return true;
3058 }
9d5c8243
AK		 3059 return false;
3060}
3061
3062#define IGB_MAX_TXD_PWR 16
3063#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3064
3065static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 3066 struct igb_ring *tx_ring, struct sk_buff *skb,
3067 unsigned int first)
9d5c8243
AK		 3068{
3069 struct igb_buffer *buffer_info;
3070 unsigned int len = skb_headlen(skb);
3071 unsigned int count = 0, i;
3072 unsigned int f;
3073
3074 i = tx_ring->next_to_use;
3075
3076 buffer_info = &tx_ring->buffer_info[i];
3077 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3078 buffer_info->length = len;
3079 /* set time_stamp *before* dma to help avoid a possible race */
3080 buffer_info->time_stamp = jiffies;
0e014cb1 3081 buffer_info->next_to_watch = i;
9d5c8243
AK		 3082 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
3083 PCI_DMA_TODEVICE);
3084 count++;
3085 i++;
3086 if (i == tx_ring->count)
3087 i = 0;
3088
3089 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3090 struct skb_frag_struct *frag;
3091
3092 frag = &skb_shinfo(skb)->frags[f];
3093 len = frag->size;
3094
3095 buffer_info = &tx_ring->buffer_info[i];
3096 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3097 buffer_info->length = len;
3098 buffer_info->time_stamp = jiffies;
0e014cb1 3099 buffer_info->next_to_watch = i;
9d5c8243
AK		 3100 buffer_info->dma = pci_map_page(adapter->pdev,
3101 frag->page,
3102 frag->page_offset,
3103 len,
3104 PCI_DMA_TODEVICE);
3105
3106 count++;
3107 i++;
3108 if (i == tx_ring->count)
3109 i = 0;
3110 }
3111
0e014cb1 3112 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
9d5c8243 3113 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3114 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243
AK		 3115
3116 return count;
3117}
3118
3119static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3120 struct igb_ring *tx_ring,
3121 int tx_flags, int count, u32 paylen,
3122 u8 hdr_len)
3123{
3124 union e1000_adv_tx_desc *tx_desc = NULL;
3125 struct igb_buffer *buffer_info;
3126 u32 olinfo_status = 0, cmd_type_len;
3127 unsigned int i;
3128
3129 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3130 E1000_ADVTXD_DCMD_DEXT);
3131
3132 if (tx_flags & IGB_TX_FLAGS_VLAN)
3133 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3134
33af6bcc
PO		 3135 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3136 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3137
9d5c8243
AK		 3138 if (tx_flags & IGB_TX_FLAGS_TSO) {
3139 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3140
3141 /* insert tcp checksum */
3142 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3143
3144 /* insert ip checksum */
3145 if (tx_flags & IGB_TX_FLAGS_IPV4)
3146 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3147
3148 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3149 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3150 }
3151
7dfc16fa
AD		 3152 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3153 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3154 IGB_TX_FLAGS_VLAN)))
661086df 3155 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 3156
3157 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3158
3159 i = tx_ring->next_to_use;
3160 while (count--) {
3161 buffer_info = &tx_ring->buffer_info[i];
3162 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3163 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3164 tx_desc->read.cmd_type_len =
3165 cpu_to_le32(cmd_type_len | buffer_info->length);
3166 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3167 i++;
3168 if (i == tx_ring->count)
3169 i = 0;
3170 }
3171
3172 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3173 /* Force memory writes to complete before letting h/w
3174 * know there are new descriptors to fetch. (Only
3175 * applicable for weak-ordered memory model archs,
3176 * such as IA-64). */
3177 wmb();
3178
3179 tx_ring->next_to_use = i;
3180 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3181 /* we need this if more than one processor can write to our tail
3182 * at a time, it syncronizes IO on IA64/Altix systems */
3183 mmiowb();
3184}
3185
3186static int __igb_maybe_stop_tx(struct net_device *netdev,
3187 struct igb_ring *tx_ring, int size)
3188{
3189 struct igb_adapter *adapter = netdev_priv(netdev);
3190
661086df 3191 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3192
9d5c8243
AK		 3193 /* Herbert's original patch had:
3194 * smp_mb__after_netif_stop_queue();
3195 * but since that doesn't exist yet, just open code it. */
3196 smp_mb();
3197
3198 /* We need to check again in a case another CPU has just
3199 * made room available. */
3200 if (IGB_DESC_UNUSED(tx_ring) < size)
3201 return -EBUSY;
3202
3203 /* A reprieve! */
661086df 3204 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3205 ++adapter->restart_queue;
3206 return 0;
3207}
3208
3209static int igb_maybe_stop_tx(struct net_device *netdev,
3210 struct igb_ring *tx_ring, int size)
3211{
3212 if (IGB_DESC_UNUSED(tx_ring) >= size)
3213 return 0;
3214 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3215}
3216
9d5c8243
AK		 3217static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3218 struct net_device *netdev,
3219 struct igb_ring *tx_ring)
3220{
3221 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3222 unsigned int first;
9d5c8243 3223 unsigned int tx_flags = 0;
9d5c8243
AK		 3224 u8 hdr_len = 0;
3225 int tso = 0;
33af6bcc 3226 union skb_shared_tx *shtx;
9d5c8243 3227
9d5c8243
AK		 3228 if (test_bit(__IGB_DOWN, &adapter->state)) {
3229 dev_kfree_skb_any(skb);
3230 return NETDEV_TX_OK;
3231 }
3232
3233 if (skb->len <= 0) {
3234 dev_kfree_skb_any(skb);
3235 return NETDEV_TX_OK;
3236 }
3237
9d5c8243
AK		 3238 /* need: 1 descriptor per page,
3239 * + 2 desc gap to keep tail from touching head,
3240 * + 1 desc for skb->data,
3241 * + 1 desc for context descriptor,
3242 * otherwise try next time */
3243 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3244 /* this is a hard error */
9d5c8243
AK		 3245 return NETDEV_TX_BUSY;
3246 }
33af6bcc
PO		 3247
3248 /*
3249 * TODO: check that there currently is no other packet with
3250 * time stamping in the queue
3251 *
3252 * When doing time stamping, keep the connection to the socket
3253 * a while longer: it is still needed by skb_hwtstamp_tx(),
3254 * called either in igb_tx_hwtstamp() or by our caller when
3255 * doing software time stamping.
3256 */
3257 shtx = skb_tx(skb);
3258 if (unlikely(shtx->hardware)) {
3259 shtx->in_progress = 1;
3260 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3261 }
9d5c8243
AK		 3262
3263 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3264 tx_flags |= IGB_TX_FLAGS_VLAN;
3265 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3266 }
3267
661086df
PWJ		 3268 if (skb->protocol == htons(ETH_P_IP))
3269 tx_flags |= IGB_TX_FLAGS_IPV4;
3270
0e014cb1 3271 first = tx_ring->next_to_use;
9d5c8243
AK		 3272 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3273 &hdr_len) : 0;
3274
3275 if (tso < 0) {
3276 dev_kfree_skb_any(skb);
9d5c8243
AK		 3277 return NETDEV_TX_OK;
3278 }
3279
3280 if (tso)
3281 tx_flags |= IGB_TX_FLAGS_TSO;
bc1cbd34
AD		 3282 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3283 (skb->ip_summed == CHECKSUM_PARTIAL))
3284 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3285
9d5c8243 3286 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
0e014cb1 3287 igb_tx_map_adv(adapter, tx_ring, skb, first),
9d5c8243
AK		 3288 skb->len, hdr_len);
3289
3290 netdev->trans_start = jiffies;
3291
3292 /* Make sure there is space in the ring for the next send. */
3293 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3294
9d5c8243
AK		 3295 return NETDEV_TX_OK;
3296}
3297
3298static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3299{
3300 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3301 struct igb_ring *tx_ring;
3302
661086df 3303 int r_idx = 0;
1bfaf07b 3304 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3305 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3306
3307 /* This goes back to the question of how to logically map a tx queue
3308 * to a flow. Right now, performance is impacted slightly negatively
3309 * if using multiple tx queues. If the stack breaks away from a
3310 * single qdisc implementation, we can look at this again. */
3311 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3312}
3313
3314/**
3315 * igb_tx_timeout - Respond to a Tx Hang
3316 * @netdev: network interface device structure
3317 **/
3318static void igb_tx_timeout(struct net_device *netdev)
3319{
3320 struct igb_adapter *adapter = netdev_priv(netdev);
3321 struct e1000_hw *hw = &adapter->hw;
3322
3323 /* Do the reset outside of interrupt context */
3324 adapter->tx_timeout_count++;
3325 schedule_work(&adapter->reset_task);
265de409
AD		 3326 wr32(E1000_EICS,
3327 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3328}
3329
3330static void igb_reset_task(struct work_struct *work)
3331{
3332 struct igb_adapter *adapter;
3333 adapter = container_of(work, struct igb_adapter, reset_task);
3334
3335 igb_reinit_locked(adapter);
3336}
3337
3338/**
3339 * igb_get_stats - Get System Network Statistics
3340 * @netdev: network interface device structure
3341 *
3342 * Returns the address of the device statistics structure.
3343 * The statistics are actually updated from the timer callback.
3344 **/
73cd78f1 3345static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243
AK		 3346{
3347 struct igb_adapter *adapter = netdev_priv(netdev);
3348
3349 /* only return the current stats */
3350 return &adapter->net_stats;
3351}
3352
3353/**
3354 * igb_change_mtu - Change the Maximum Transfer Unit
3355 * @netdev: network interface device structure
3356 * @new_mtu: new value for maximum frame size
3357 *
3358 * Returns 0 on success, negative on failure
3359 **/
3360static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3361{
3362 struct igb_adapter *adapter = netdev_priv(netdev);
3363 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3364
3365 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3366 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3367 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3368 return -EINVAL;
3369 }
3370
9d5c8243
AK		 3371 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3372 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3373 return -EINVAL;
3374 }
3375
3376 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3377 msleep(1);
73cd78f1 3378
9d5c8243
AK		 3379 /* igb_down has a dependency on max_frame_size */
3380 adapter->max_frame_size = max_frame;
3381 if (netif_running(netdev))
3382 igb_down(adapter);
3383
3384 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3385 * means we reserve 2 more, this pushes us to allocate from the next
3386 * larger slab size.
3387 * i.e. RXBUFFER_2048 --> size-4096 slab
3388 */
3389
3390 if (max_frame <= IGB_RXBUFFER_256)
3391 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3392 else if (max_frame <= IGB_RXBUFFER_512)
3393 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3394 else if (max_frame <= IGB_RXBUFFER_1024)
3395 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3396 else if (max_frame <= IGB_RXBUFFER_2048)
3397 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3398 else
bf36c1a0
AD		 3399#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3400 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3401#else
3402 adapter->rx_buffer_len = PAGE_SIZE / 2;
3403#endif
e1739522
AD		 3404
3405 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3406 if (adapter->vfs_allocated_count &&
3407 (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3408 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3409
9d5c8243
AK		 3410 /* adjust allocation if LPE protects us, and we aren't using SBP */
3411 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3412 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3413 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3414
3415 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3416 netdev->mtu, new_mtu);
3417 netdev->mtu = new_mtu;
3418
3419 if (netif_running(netdev))
3420 igb_up(adapter);
3421 else
3422 igb_reset(adapter);
3423
3424 clear_bit(__IGB_RESETTING, &adapter->state);
3425
3426 return 0;
3427}
3428
3429/**
3430 * igb_update_stats - Update the board statistics counters
3431 * @adapter: board private structure
3432 **/
3433
3434void igb_update_stats(struct igb_adapter *adapter)
3435{
3436 struct e1000_hw *hw = &adapter->hw;
3437 struct pci_dev *pdev = adapter->pdev;
3438 u16 phy_tmp;
3439
3440#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3441
3442 /*
3443 * Prevent stats update while adapter is being reset, or if the pci
3444 * connection is down.
3445 */
3446 if (adapter->link_speed == 0)
3447 return;
3448 if (pci_channel_offline(pdev))
3449 return;
3450
3451 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3452 adapter->stats.gprc += rd32(E1000_GPRC);
3453 adapter->stats.gorc += rd32(E1000_GORCL);
3454 rd32(E1000_GORCH); /* clear GORCL */
3455 adapter->stats.bprc += rd32(E1000_BPRC);
3456 adapter->stats.mprc += rd32(E1000_MPRC);
3457 adapter->stats.roc += rd32(E1000_ROC);
3458
3459 adapter->stats.prc64 += rd32(E1000_PRC64);
3460 adapter->stats.prc127 += rd32(E1000_PRC127);
3461 adapter->stats.prc255 += rd32(E1000_PRC255);
3462 adapter->stats.prc511 += rd32(E1000_PRC511);
3463 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3464 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3465 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3466 adapter->stats.sec += rd32(E1000_SEC);
3467
3468 adapter->stats.mpc += rd32(E1000_MPC);
3469 adapter->stats.scc += rd32(E1000_SCC);
3470 adapter->stats.ecol += rd32(E1000_ECOL);
3471 adapter->stats.mcc += rd32(E1000_MCC);
3472 adapter->stats.latecol += rd32(E1000_LATECOL);
3473 adapter->stats.dc += rd32(E1000_DC);
3474 adapter->stats.rlec += rd32(E1000_RLEC);
3475 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3476 adapter->stats.xontxc += rd32(E1000_XONTXC);
3477 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3478 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3479 adapter->stats.fcruc += rd32(E1000_FCRUC);
3480 adapter->stats.gptc += rd32(E1000_GPTC);
3481 adapter->stats.gotc += rd32(E1000_GOTCL);
3482 rd32(E1000_GOTCH); /* clear GOTCL */
3483 adapter->stats.rnbc += rd32(E1000_RNBC);
3484 adapter->stats.ruc += rd32(E1000_RUC);
3485 adapter->stats.rfc += rd32(E1000_RFC);
3486 adapter->stats.rjc += rd32(E1000_RJC);
3487 adapter->stats.tor += rd32(E1000_TORH);
3488 adapter->stats.tot += rd32(E1000_TOTH);
3489 adapter->stats.tpr += rd32(E1000_TPR);
3490
3491 adapter->stats.ptc64 += rd32(E1000_PTC64);
3492 adapter->stats.ptc127 += rd32(E1000_PTC127);
3493 adapter->stats.ptc255 += rd32(E1000_PTC255);
3494 adapter->stats.ptc511 += rd32(E1000_PTC511);
3495 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3496 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3497
3498 adapter->stats.mptc += rd32(E1000_MPTC);
3499 adapter->stats.bptc += rd32(E1000_BPTC);
3500
3501 /* used for adaptive IFS */
3502
3503 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3504 adapter->stats.tpt += hw->mac.tx_packet_delta;
3505 hw->mac.collision_delta = rd32(E1000_COLC);
3506 adapter->stats.colc += hw->mac.collision_delta;
3507
3508 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3509 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3510 adapter->stats.tncrs += rd32(E1000_TNCRS);
3511 adapter->stats.tsctc += rd32(E1000_TSCTC);
3512 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3513
3514 adapter->stats.iac += rd32(E1000_IAC);
3515 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3516 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3517 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3518 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3519 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3520 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3521 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3522 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3523
3524 /* Fill out the OS statistics structure */
3525 adapter->net_stats.multicast = adapter->stats.mprc;
3526 adapter->net_stats.collisions = adapter->stats.colc;
3527
3528 /* Rx Errors */
3529
3530 /* RLEC on some newer hardware can be incorrect so build
3531 * our own version based on RUC and ROC */
3532 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3533 adapter->stats.crcerrs + adapter->stats.algnerrc +
3534 adapter->stats.ruc + adapter->stats.roc +
3535 adapter->stats.cexterr;
3536 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3537 adapter->stats.roc;
3538 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3539 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3540 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3541
3542 /* Tx Errors */
3543 adapter->net_stats.tx_errors = adapter->stats.ecol +
3544 adapter->stats.latecol;
3545 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3546 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3547 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3548
3549 /* Tx Dropped needs to be maintained elsewhere */
3550
3551 /* Phy Stats */
3552 if (hw->phy.media_type == e1000_media_type_copper) {
3553 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3554 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3555 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3556 adapter->phy_stats.idle_errors += phy_tmp;
3557 }
3558 }
3559
3560 /* Management Stats */
3561 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3562 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3563 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3564}
3565
9d5c8243
AK		 3566static irqreturn_t igb_msix_other(int irq, void *data)
3567{
3568 struct net_device *netdev = data;
3569 struct igb_adapter *adapter = netdev_priv(netdev);
3570 struct e1000_hw *hw = &adapter->hw;
844290e5 3571 u32 icr = rd32(E1000_ICR);
9d5c8243 3572
844290e5 3573 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3574
3575 if(icr & E1000_ICR_DOUTSYNC) {
3576 /* HW is reporting DMA is out of sync */
3577 adapter->stats.doosync++;
3578 }
eebbbdba 3579
4ae196df
AD		 3580 /* Check for a mailbox event */
3581 if (icr & E1000_ICR_VMMB)
3582 igb_msg_task(adapter);
3583
3584 if (icr & E1000_ICR_LSC) {
3585 hw->mac.get_link_status = 1;
3586 /* guard against interrupt when we're going down */
3587 if (!test_bit(__IGB_DOWN, &adapter->state))
3588 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3589 }
3590
3591 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
844290e5 3592 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3593
3594 return IRQ_HANDLED;
3595}
3596
3597static irqreturn_t igb_msix_tx(int irq, void *data)
3598{
3599 struct igb_ring *tx_ring = data;
3600 struct igb_adapter *adapter = tx_ring->adapter;
3601 struct e1000_hw *hw = &adapter->hw;
3602
421e02f0 3603#ifdef CONFIG_IGB_DCA
7dfc16fa 3604 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3605 igb_update_tx_dca(tx_ring);
3606#endif
73cd78f1 3607
9d5c8243
AK		 3608 tx_ring->total_bytes = 0;
3609 tx_ring->total_packets = 0;
661086df
PWJ		 3610
3611 /* auto mask will automatically reenable the interrupt when we write
3612 * EICS */
3b644cf6 3613 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3614 /* Ring was not completely cleaned, so fire another interrupt */
3615 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3616 else
9d5c8243 3617 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3618
9d5c8243
AK		 3619 return IRQ_HANDLED;
3620}
3621
6eb5a7f1
AD		 3622static void igb_write_itr(struct igb_ring *ring)
3623{
3624 struct e1000_hw *hw = &ring->adapter->hw;
3625 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3626 switch (hw->mac.type) {
3627 case e1000_82576:
73cd78f1 3628 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3629 0x80000000);
3630 break;
3631 default:
73cd78f1 3632 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3633 (ring->itr_val << 16));
3634 break;
3635 }
3636 ring->set_itr = 0;
3637 }
3638}
3639
9d5c8243
AK		 3640static irqreturn_t igb_msix_rx(int irq, void *data)
3641{
3642 struct igb_ring *rx_ring = data;
9d5c8243 3643
844290e5
PW		 3644 /* Write the ITR value calculated at the end of the
3645 * previous interrupt.
3646 */
9d5c8243 3647
6eb5a7f1 3648 igb_write_itr(rx_ring);
9d5c8243 3649
288379f0
BH		 3650 if (napi_schedule_prep(&rx_ring->napi))
3651 __napi_schedule(&rx_ring->napi);
844290e5 3652
421e02f0 3653#ifdef CONFIG_IGB_DCA
8d253320 3654 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3655 igb_update_rx_dca(rx_ring);
3656#endif
3657 return IRQ_HANDLED;
3658}
3659
421e02f0 3660#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3661static void igb_update_rx_dca(struct igb_ring *rx_ring)
3662{
3663 u32 dca_rxctrl;
3664 struct igb_adapter *adapter = rx_ring->adapter;
3665 struct e1000_hw *hw = &adapter->hw;
3666 int cpu = get_cpu();
26bc19ec 3667 int q = rx_ring->reg_idx;
fe4506b6
JC		 3668
3669 if (rx_ring->cpu != cpu) {
3670 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3671 if (hw->mac.type == e1000_82576) {
3672 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
92be7917 3673 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3674 E1000_DCA_RXCTRL_CPUID_SHIFT;
3675 } else {
3676 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 3677 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3678 }
fe4506b6
JC		 3679 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3680 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3681 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3682 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3683 rx_ring->cpu = cpu;
3684 }
3685 put_cpu();
3686}
3687
3688static void igb_update_tx_dca(struct igb_ring *tx_ring)
3689{
3690 u32 dca_txctrl;
3691 struct igb_adapter *adapter = tx_ring->adapter;
3692 struct e1000_hw *hw = &adapter->hw;
3693 int cpu = get_cpu();
26bc19ec 3694 int q = tx_ring->reg_idx;
fe4506b6
JC		 3695
3696 if (tx_ring->cpu != cpu) {
3697 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3698 if (hw->mac.type == e1000_82576) {
3699 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
92be7917 3700 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3701 E1000_DCA_TXCTRL_CPUID_SHIFT;
3702 } else {
3703 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
92be7917 3704 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3705 }
fe4506b6
JC		 3706 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3707 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3708 tx_ring->cpu = cpu;
3709 }
3710 put_cpu();
3711}
3712
3713static void igb_setup_dca(struct igb_adapter *adapter)
3714{
3715 int i;
3716
7dfc16fa 3717 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3718 return;
3719
3720 for (i = 0; i < adapter->num_tx_queues; i++) {
3721 adapter->tx_ring[i].cpu = -1;
3722 igb_update_tx_dca(&adapter->tx_ring[i]);
3723 }
3724 for (i = 0; i < adapter->num_rx_queues; i++) {
3725 adapter->rx_ring[i].cpu = -1;
3726 igb_update_rx_dca(&adapter->rx_ring[i]);
3727 }
3728}
3729
3730static int __igb_notify_dca(struct device *dev, void *data)
3731{
3732 struct net_device *netdev = dev_get_drvdata(dev);
3733 struct igb_adapter *adapter = netdev_priv(netdev);
3734 struct e1000_hw *hw = &adapter->hw;
3735 unsigned long event = *(unsigned long *)data;
3736
3737 switch (event) {
3738 case DCA_PROVIDER_ADD:
3739 /* if already enabled, don't do it again */
7dfc16fa 3740 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3741 break;
fe4506b6
JC		 3742 /* Always use CB2 mode, difference is masked
3743 * in the CB driver. */
cbd347ad 3744 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 3745 if (dca_add_requester(dev) == 0) {
bbd98fe4 3746 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3747 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3748 igb_setup_dca(adapter);
3749 break;
3750 }
3751 /* Fall Through since DCA is disabled. */
3752 case DCA_PROVIDER_REMOVE:
7dfc16fa 3753 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3754 /* without this a class_device is left
3755 * hanging around in the sysfs model */
3756 dca_remove_requester(dev);
3757 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3758 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 3759 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 3760 }
3761 break;
3762 }
bbd98fe4 3763
fe4506b6 3764 return 0;
9d5c8243
AK		 3765}
3766
fe4506b6
JC		 3767static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3768 void *p)
3769{
3770 int ret_val;
3771
3772 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3773 __igb_notify_dca);
3774
3775 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3776}
421e02f0 3777#endif /* CONFIG_IGB_DCA */
9d5c8243 3778
4ae196df
AD		 3779static void igb_ping_all_vfs(struct igb_adapter *adapter)
3780{
3781 struct e1000_hw *hw = &adapter->hw;
3782 u32 ping;
3783 int i;
3784
3785 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3786 ping = E1000_PF_CONTROL_MSG;
3787 if (adapter->vf_data[i].clear_to_send)
3788 ping |= E1000_VT_MSGTYPE_CTS;
3789 igb_write_mbx(hw, &ping, 1, i);
3790 }
3791}
3792
3793static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3794 u32 *msgbuf, u32 vf)
3795{
3796 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3797 u16 *hash_list = (u16 *)&msgbuf[1];
3798 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3799 int i;
3800
3801 /* only up to 30 hash values supported */
3802 if (n > 30)
3803 n = 30;
3804
3805 /* salt away the number of multi cast addresses assigned
3806 * to this VF for later use to restore when the PF multi cast
3807 * list changes
3808 */
3809 vf_data->num_vf_mc_hashes = n;
3810
3811 /* VFs are limited to using the MTA hash table for their multicast
3812 * addresses */
3813 for (i = 0; i < n; i++)
3814 vf_data->vf_mc_hashes[i] = hash_list[i];;
3815
3816 /* Flush and reset the mta with the new values */
3817 igb_set_multi(adapter->netdev);
3818
3819 return 0;
3820}
3821
3822static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3823{
3824 struct e1000_hw *hw = &adapter->hw;
3825 struct vf_data_storage *vf_data;
3826 int i, j;
3827
3828 for (i = 0; i < adapter->vfs_allocated_count; i++) {
3829 vf_data = &adapter->vf_data[i];
3830 for (j = 0; j < vf_data[i].num_vf_mc_hashes; j++)
3831 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3832 }
3833}
3834
3835static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3836{
3837 struct e1000_hw *hw = &adapter->hw;
3838 u32 pool_mask, reg, vid;
3839 int i;
3840
3841 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3842
3843 /* Find the vlan filter for this id */
3844 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3845 reg = rd32(E1000_VLVF(i));
3846
3847 /* remove the vf from the pool */
3848 reg &= ~pool_mask;
3849
3850 /* if pool is empty then remove entry from vfta */
3851 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3852 (reg & E1000_VLVF_VLANID_ENABLE)) {
3853 reg = 0;
3854 vid = reg & E1000_VLVF_VLANID_MASK;
3855 igb_vfta_set(hw, vid, false);
3856 }
3857
3858 wr32(E1000_VLVF(i), reg);
3859 }
3860}
3861
3862static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3863{
3864 struct e1000_hw *hw = &adapter->hw;
3865 u32 reg, i;
3866
3867 /* It is an error to call this function when VFs are not enabled */
3868 if (!adapter->vfs_allocated_count)
3869 return -1;
3870
3871 /* Find the vlan filter for this id */
3872 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3873 reg = rd32(E1000_VLVF(i));
3874 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3875 vid == (reg & E1000_VLVF_VLANID_MASK))
3876 break;
3877 }
3878
3879 if (add) {
3880 if (i == E1000_VLVF_ARRAY_SIZE) {
3881 /* Did not find a matching VLAN ID entry that was
3882 * enabled. Search for a free filter entry, i.e.
3883 * one without the enable bit set
3884 */
3885 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3886 reg = rd32(E1000_VLVF(i));
3887 if (!(reg & E1000_VLVF_VLANID_ENABLE))
3888 break;
3889 }
3890 }
3891 if (i < E1000_VLVF_ARRAY_SIZE) {
3892 /* Found an enabled/available entry */
3893 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3894
3895 /* if !enabled we need to set this up in vfta */
3896 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
3897 /* add VID to filter table */
3898 igb_vfta_set(hw, vid, true);
3899 reg |= E1000_VLVF_VLANID_ENABLE;
3900 }
3901
3902 wr32(E1000_VLVF(i), reg);
3903 return 0;
3904 }
3905 } else {
3906 if (i < E1000_VLVF_ARRAY_SIZE) {
3907 /* remove vf from the pool */
3908 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
3909 /* if pool is empty then remove entry from vfta */
3910 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
3911 reg = 0;
3912 igb_vfta_set(hw, vid, false);
3913 }
3914 wr32(E1000_VLVF(i), reg);
3915 return 0;
3916 }
3917 }
3918 return -1;
3919}
3920
3921static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
3922{
3923 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3924 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
3925
3926 return igb_vlvf_set(adapter, vid, add, vf);
3927}
3928
3929static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
3930{
3931 struct e1000_hw *hw = &adapter->hw;
3932
3933 /* disable mailbox functionality for vf */
3934 adapter->vf_data[vf].clear_to_send = false;
3935
3936 /* reset offloads to defaults */
3937 igb_set_vmolr(hw, vf);
3938
3939 /* reset vlans for device */
3940 igb_clear_vf_vfta(adapter, vf);
3941
3942 /* reset multicast table array for vf */
3943 adapter->vf_data[vf].num_vf_mc_hashes = 0;
3944
3945 /* Flush and reset the mta with the new values */
3946 igb_set_multi(adapter->netdev);
3947}
3948
3949static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
3950{
3951 struct e1000_hw *hw = &adapter->hw;
3952 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
3953 u32 reg, msgbuf[3];
3954 u8 *addr = (u8 *)(&msgbuf[1]);
3955
3956 /* process all the same items cleared in a function level reset */
3957 igb_vf_reset_event(adapter, vf);
3958
3959 /* set vf mac address */
3960 igb_rar_set(hw, vf_mac, vf + 1);
3961 igb_set_rah_pool(hw, vf, vf + 1);
3962
3963 /* enable transmit and receive for vf */
3964 reg = rd32(E1000_VFTE);
3965 wr32(E1000_VFTE, reg | (1 << vf));
3966 reg = rd32(E1000_VFRE);
3967 wr32(E1000_VFRE, reg | (1 << vf));
3968
3969 /* enable mailbox functionality for vf */
3970 adapter->vf_data[vf].clear_to_send = true;
3971
3972 /* reply to reset with ack and vf mac address */
3973 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
3974 memcpy(addr, vf_mac, 6);
3975 igb_write_mbx(hw, msgbuf, 3, vf);
3976}
3977
3978static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
3979{
3980 unsigned char *addr = (char *)&msg[1];
3981 int err = -1;
3982
3983 if (is_valid_ether_addr(addr))
3984 err = igb_set_vf_mac(adapter, vf, addr);
3985
3986 return err;
3987
3988}
3989
3990static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
3991{
3992 struct e1000_hw *hw = &adapter->hw;
3993 u32 msg = E1000_VT_MSGTYPE_NACK;
3994
3995 /* if device isn't clear to send it shouldn't be reading either */
3996 if (!adapter->vf_data[vf].clear_to_send)
3997 igb_write_mbx(hw, &msg, 1, vf);
3998}
3999
4000
4001static void igb_msg_task(struct igb_adapter *adapter)
4002{
4003 struct e1000_hw *hw = &adapter->hw;
4004 u32 vf;
4005
4006 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4007 /* process any reset requests */
4008 if (!igb_check_for_rst(hw, vf)) {
4009 adapter->vf_data[vf].clear_to_send = false;
4010 igb_vf_reset_event(adapter, vf);
4011 }
4012
4013 /* process any messages pending */
4014 if (!igb_check_for_msg(hw, vf))
4015 igb_rcv_msg_from_vf(adapter, vf);
4016
4017 /* process any acks */
4018 if (!igb_check_for_ack(hw, vf))
4019 igb_rcv_ack_from_vf(adapter, vf);
4020
4021 }
4022}
4023
4024static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4025{
4026 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4027 u32 msgbuf[mbx_size];
4028 struct e1000_hw *hw = &adapter->hw;
4029 s32 retval;
4030
4031 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4032
4033 if (retval)
4034 dev_err(&adapter->pdev->dev,
4035 "Error receiving message from VF\n");
4036
4037 /* this is a message we already processed, do nothing */
4038 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4039 return retval;
4040
4041 /*
4042 * until the vf completes a reset it should not be
4043 * allowed to start any configuration.
4044 */
4045
4046 if (msgbuf[0] == E1000_VF_RESET) {
4047 igb_vf_reset_msg(adapter, vf);
4048
4049 return retval;
4050 }
4051
4052 if (!adapter->vf_data[vf].clear_to_send) {
4053 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4054 igb_write_mbx(hw, msgbuf, 1, vf);
4055 return retval;
4056 }
4057
4058 switch ((msgbuf[0] & 0xFFFF)) {
4059 case E1000_VF_SET_MAC_ADDR:
4060 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4061 break;
4062 case E1000_VF_SET_MULTICAST:
4063 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4064 break;
4065 case E1000_VF_SET_LPE:
4066 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4067 break;
4068 case E1000_VF_SET_VLAN:
4069 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4070 break;
4071 default:
4072 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4073 retval = -1;
4074 break;
4075 }
4076
4077 /* notify the VF of the results of what it sent us */
4078 if (retval)
4079 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4080 else
4081 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4082
4083 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4084
4085 igb_write_mbx(hw, msgbuf, 1, vf);
4086
4087 return retval;
4088}
4089
9d5c8243
AK		 4090/**
4091 * igb_intr_msi - Interrupt Handler
4092 * @irq: interrupt number
4093 * @data: pointer to a network interface device structure
4094 **/
4095static irqreturn_t igb_intr_msi(int irq, void *data)
4096{
4097 struct net_device *netdev = data;
4098 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4099 struct e1000_hw *hw = &adapter->hw;
4100 /* read ICR disables interrupts using IAM */
4101 u32 icr = rd32(E1000_ICR);
4102
6eb5a7f1 4103 igb_write_itr(adapter->rx_ring);
9d5c8243 4104
dda0e083
AD		 4105 if(icr & E1000_ICR_DOUTSYNC) {
4106 /* HW is reporting DMA is out of sync */
4107 adapter->stats.doosync++;
4108 }
4109
9d5c8243
AK		 4110 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4111 hw->mac.get_link_status = 1;
4112 if (!test_bit(__IGB_DOWN, &adapter->state))
4113 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4114 }
4115
288379f0 4116 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4117
4118 return IRQ_HANDLED;
4119}
4120
4121/**
4a3c6433 4122 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4123 * @irq: interrupt number
4124 * @data: pointer to a network interface device structure
4125 **/
4126static irqreturn_t igb_intr(int irq, void *data)
4127{
4128 struct net_device *netdev = data;
4129 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4130 struct e1000_hw *hw = &adapter->hw;
4131 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4132 * need for the IMC write */
4133 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4134 if (!icr)
4135 return IRQ_NONE; /* Not our interrupt */
4136
6eb5a7f1 4137 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 4138
4139 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4140 * not set, then the adapter didn't send an interrupt */
4141 if (!(icr & E1000_ICR_INT_ASSERTED))
4142 return IRQ_NONE;
4143
dda0e083
AD		 4144 if(icr & E1000_ICR_DOUTSYNC) {
4145 /* HW is reporting DMA is out of sync */
4146 adapter->stats.doosync++;
4147 }
4148
9d5c8243
AK		 4149 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4150 hw->mac.get_link_status = 1;
4151 /* guard against interrupt when we're going down */
4152 if (!test_bit(__IGB_DOWN, &adapter->state))
4153 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4154 }
4155
288379f0 4156 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4157
4158 return IRQ_HANDLED;
4159}
4160
46544258 4161static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
9d5c8243 4162{
661086df 4163 struct igb_adapter *adapter = rx_ring->adapter;
46544258 4164 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4165
46544258
AD		 4166 if (adapter->itr_setting & 3) {
4167 if (adapter->num_rx_queues == 1)
6eb5a7f1 4168 igb_set_itr(adapter);
46544258
AD		 4169 else
4170 igb_update_ring_itr(rx_ring);
9d5c8243
AK		 4171 }
4172
46544258
AD		 4173 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4174 if (adapter->msix_entries)
4175 wr32(E1000_EIMS, rx_ring->eims_value);
4176 else
4177 igb_irq_enable(adapter);
4178 }
9d5c8243
AK		 4179}
4180
46544258
AD		 4181/**
4182 * igb_poll - NAPI Rx polling callback
4183 * @napi: napi polling structure
4184 * @budget: count of how many packets we should handle
4185 **/
4186static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243
AK		 4187{
4188 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4189 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4190 struct net_device *netdev = adapter->netdev;
4191 int work_done = 0;
4192
421e02f0 4193#ifdef CONFIG_IGB_DCA
7dfc16fa 4194 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 4195 igb_update_rx_dca(rx_ring);
4196#endif
3b644cf6 4197 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243 4198
46544258
AD		 4199 if (rx_ring->buddy) {
4200#ifdef CONFIG_IGB_DCA
4201 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
4202 igb_update_tx_dca(rx_ring->buddy);
4203#endif
4204 if (!igb_clean_tx_irq(rx_ring->buddy))
4205 work_done = budget;
4206 }
4207
9d5c8243 4208 /* If not enough Rx work done, exit the polling mode */
46544258 4209 if ((work_done < budget) || !netif_running(netdev)) {
288379f0 4210 napi_complete(napi);
46544258 4211 igb_rx_irq_enable(rx_ring);
9d5c8243
AK		 4212 }
4213
46544258 4214 return work_done;
9d5c8243 4215}
6d8126f9 4216
33af6bcc
PO		 4217/**
4218 * igb_hwtstamp - utility function which checks for TX time stamp
4219 * @adapter: board private structure
4220 * @skb: packet that was just sent
4221 *
4222 * If we were asked to do hardware stamping and such a time stamp is
4223 * available, then it must have been for this skb here because we only
4224 * allow only one such packet into the queue.
4225 */
4226static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4227{
4228 union skb_shared_tx *shtx = skb_tx(skb);
4229 struct e1000_hw *hw = &adapter->hw;
4230
4231 if (unlikely(shtx->hardware)) {
4232 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4233 if (valid) {
4234 u64 regval = rd32(E1000_TXSTMPL);
4235 u64 ns;
4236 struct skb_shared_hwtstamps shhwtstamps;
4237
4238 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4239 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4240 ns = timecounter_cyc2time(&adapter->clock,
4241 regval);
4242 timecompare_update(&adapter->compare, ns);
4243 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4244 shhwtstamps.syststamp =
4245 timecompare_transform(&adapter->compare, ns);
4246 skb_tstamp_tx(skb, &shhwtstamps);
4247 }
33af6bcc
PO		 4248 }
4249}
4250
9d5c8243
AK		 4251/**
4252 * igb_clean_tx_irq - Reclaim resources after transmit completes
4253 * @adapter: board private structure
4254 * returns true if ring is completely cleaned
4255 **/
3b644cf6 4256static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 4257{
3b644cf6 4258 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 4259 struct net_device *netdev = adapter->netdev;
0e014cb1 4260 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4261 struct igb_buffer *buffer_info;
4262 struct sk_buff *skb;
0e014cb1 4263 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4264 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4265 unsigned int i, eop, count = 0;
4266 bool cleaned = false;
9d5c8243 4267
9d5c8243 4268 i = tx_ring->next_to_clean;
0e014cb1
AD		 4269 eop = tx_ring->buffer_info[i].next_to_watch;
4270 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4271
4272 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4273 (count < tx_ring->count)) {
4274 for (cleaned = false; !cleaned; count++) {
4275 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4276 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4277 cleaned = (i == eop);
9d5c8243
AK		 4278 skb = buffer_info->skb;
4279
4280 if (skb) {
4281 unsigned int segs, bytecount;
4282 /* gso_segs is currently only valid for tcp */
4283 segs = skb_shinfo(skb)->gso_segs ?: 1;
4284 /* multiply data chunks by size of headers */
4285 bytecount = ((segs - 1) * skb_headlen(skb)) +
4286 skb->len;
4287 total_packets += segs;
4288 total_bytes += bytecount;
33af6bcc
PO		 4289
4290 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 4291 }
4292
4293 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 4294 tx_desc->wb.status = 0;
9d5c8243
AK		 4295
4296 i++;
4297 if (i == tx_ring->count)
4298 i = 0;
9d5c8243 4299 }
0e014cb1
AD		 4300 eop = tx_ring->buffer_info[i].next_to_watch;
4301 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4302 }
4303
9d5c8243
AK		 4304 tx_ring->next_to_clean = i;
4305
fc7d345d 4306 if (unlikely(count &&
9d5c8243
AK		 4307 netif_carrier_ok(netdev) &&
4308 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4309 /* Make sure that anybody stopping the queue after this
4310 * sees the new next_to_clean.
4311 */
4312 smp_mb();
661086df
PWJ		 4313 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4314 !(test_bit(__IGB_DOWN, &adapter->state))) {
4315 netif_wake_subqueue(netdev, tx_ring->queue_index);
4316 ++adapter->restart_queue;
4317 }
9d5c8243
AK		 4318 }
4319
4320 if (tx_ring->detect_tx_hung) {
4321 /* Detect a transmit hang in hardware, this serializes the
4322 * check with the clearing of time_stamp and movement of i */
4323 tx_ring->detect_tx_hung = false;
4324 if (tx_ring->buffer_info[i].time_stamp &&
4325 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4326 (adapter->tx_timeout_factor * HZ))
4327 && !(rd32(E1000_STATUS) &
4328 E1000_STATUS_TXOFF)) {
4329
9d5c8243
AK		 4330 /* detected Tx unit hang */
4331 dev_err(&adapter->pdev->dev,
4332 "Detected Tx Unit Hang\n"
2d064c06 4333 " Tx Queue <%d>\n"
9d5c8243
AK		 4334 " TDH <%x>\n"
4335 " TDT <%x>\n"
4336 " next_to_use <%x>\n"
4337 " next_to_clean <%x>\n"
9d5c8243
AK		 4338 "buffer_info[next_to_clean]\n"
4339 " time_stamp <%lx>\n"
0e014cb1 4340 " next_to_watch <%x>\n"
9d5c8243
AK		 4341 " jiffies <%lx>\n"
4342 " desc.status <%x>\n",
2d064c06 4343 tx_ring->queue_index,
9d5c8243
AK		 4344 readl(adapter->hw.hw_addr + tx_ring->head),
4345 readl(adapter->hw.hw_addr + tx_ring->tail),
4346 tx_ring->next_to_use,
4347 tx_ring->next_to_clean,
9d5c8243 4348 tx_ring->buffer_info[i].time_stamp,
0e014cb1 4349 eop,
9d5c8243 4350 jiffies,
0e014cb1 4351 eop_desc->wb.status);
661086df 4352 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 4353 }
4354 }
4355 tx_ring->total_bytes += total_bytes;
4356 tx_ring->total_packets += total_packets;
e21ed353
AD		 4357 tx_ring->tx_stats.bytes += total_bytes;
4358 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 4359 adapter->net_stats.tx_bytes += total_bytes;
4360 adapter->net_stats.tx_packets += total_packets;
0e014cb1 4361 return (count < tx_ring->count);
9d5c8243
AK		 4362}
4363
9d5c8243
AK		 4364/**
4365 * igb_receive_skb - helper function to handle rx indications
eebbbdba 4366 * @ring: pointer to receive ring receving this packet
9d5c8243 4367 * @status: descriptor status field as written by hardware
73cd78f1 4368 * @rx_desc: receive descriptor containing vlan and type information.
9d5c8243
AK		 4369 * @skb: pointer to sk_buff to be indicated to stack
4370 **/
d3352520
AD		 4371static void igb_receive_skb(struct igb_ring *ring, u8 status,
4372 union e1000_adv_rx_desc * rx_desc,
4373 struct sk_buff *skb)
4374{
4375 struct igb_adapter * adapter = ring->adapter;
4376 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4377
0c8dfc83 4378 skb_record_rx_queue(skb, ring->queue_index);
5c0999b7 4379 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
d3352520 4380 if (vlan_extracted)
5c0999b7
HX		 4381 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4382 le16_to_cpu(rx_desc->wb.upper.vlan),
4383 skb);
d3352520 4384 else
5c0999b7 4385 napi_gro_receive(&ring->napi, skb);
d3352520 4386 } else {
d3352520
AD		 4387 if (vlan_extracted)
4388 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
4389 le16_to_cpu(rx_desc->wb.upper.vlan));
4390 else
d3352520 4391 netif_receive_skb(skb);
d3352520 4392 }
9d5c8243
AK		 4393}
4394
9d5c8243
AK		 4395static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4396 u32 status_err, struct sk_buff *skb)
4397{
4398 skb->ip_summed = CHECKSUM_NONE;
4399
4400 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4401 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
4402 return;
4403 /* TCP/UDP checksum error bit is set */
4404 if (status_err &
4405 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4406 /* let the stack verify checksum errors */
4407 adapter->hw_csum_err++;
4408 return;
4409 }
4410 /* It must be a TCP or UDP packet with a valid checksum */
4411 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4412 skb->ip_summed = CHECKSUM_UNNECESSARY;
4413
4414 adapter->hw_csum_good++;
4415}
4416
3b644cf6
MW		 4417static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4418 int *work_done, int budget)
9d5c8243 4419{
3b644cf6 4420 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 4421 struct net_device *netdev = adapter->netdev;
33af6bcc 4422 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4423 struct pci_dev *pdev = adapter->pdev;
4424 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4425 struct igb_buffer *buffer_info , *next_buffer;
4426 struct sk_buff *skb;
9d5c8243
AK		 4427 bool cleaned = false;
4428 int cleaned_count = 0;
4429 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1
AD		 4430 unsigned int i;
4431 u32 length, hlen, staterr;
9d5c8243
AK		 4432
4433 i = rx_ring->next_to_clean;
69d3ca53 4434 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4435 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4436 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4437
4438 while (staterr & E1000_RXD_STAT_DD) {
4439 if (*work_done >= budget)
4440 break;
4441 (*work_done)++;
9d5c8243 4442
69d3ca53
AD		 4443 skb = buffer_info->skb;
4444 prefetch(skb->data - NET_IP_ALIGN);
4445 buffer_info->skb = NULL;
4446
4447 i++;
4448 if (i == rx_ring->count)
4449 i = 0;
4450 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4451 prefetch(next_rxd);
4452 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4453
4454 length = le16_to_cpu(rx_desc->wb.upper.length);
4455 cleaned = true;
4456 cleaned_count++;
4457
bf36c1a0
AD		 4458 if (!adapter->rx_ps_hdr_size) {
4459 pci_unmap_single(pdev, buffer_info->dma,
4460 adapter->rx_buffer_len +
4461 NET_IP_ALIGN,
4462 PCI_DMA_FROMDEVICE);
4463 skb_put(skb, length);
4464 goto send_up;
9d5c8243
AK		 4465 }
4466
69d3ca53
AD		 4467 /* HW will not DMA in data larger than the given buffer, even
4468 * if it parses the (NFS, of course) header to be larger. In
4469 * that case, it fills the header buffer and spills the rest
4470 * into the page.
4471 */
4472 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4473 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4474 if (hlen > adapter->rx_ps_hdr_size)
4475 hlen = adapter->rx_ps_hdr_size;
4476
bf36c1a0
AD		 4477 if (!skb_shinfo(skb)->nr_frags) {
4478 pci_unmap_single(pdev, buffer_info->dma,
73cd78f1 4479 adapter->rx_ps_hdr_size + NET_IP_ALIGN,
bf36c1a0
AD		 4480 PCI_DMA_FROMDEVICE);
4481 skb_put(skb, hlen);
4482 }
4483
4484 if (length) {
9d5c8243 4485 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4486 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4487 buffer_info->page_dma = 0;
bf36c1a0
AD		 4488
4489 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4490 buffer_info->page,
4491 buffer_info->page_offset,
4492 length);
4493
4494 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4495 (page_count(buffer_info->page) != 1))
4496 buffer_info->page = NULL;
4497 else
4498 get_page(buffer_info->page);
9d5c8243
AK		 4499
4500 skb->len += length;
4501 skb->data_len += length;
9d5c8243 4502
bf36c1a0 4503 skb->truesize += length;
9d5c8243 4504 }
9d5c8243 4505
bf36c1a0 4506 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4507 buffer_info->skb = next_buffer->skb;
4508 buffer_info->dma = next_buffer->dma;
4509 next_buffer->skb = skb;
4510 next_buffer->dma = 0;
bf36c1a0
AD		 4511 goto next_desc;
4512 }
69d3ca53 4513send_up:
33af6bcc
PO		 4514 /*
4515 * If this bit is set, then the RX registers contain
4516 * the time stamp. No other packet will be time
4517 * stamped until we read these registers, so read the
4518 * registers to make them available again. Because
4519 * only one packet can be time stamped at a time, we
4520 * know that the register values must belong to this
4521 * one here and therefore we don't need to compare
4522 * any of the additional attributes stored for it.
4523 *
4524 * If nothing went wrong, then it should have a
4525 * skb_shared_tx that we can turn into a
4526 * skb_shared_hwtstamps.
4527 *
4528 * TODO: can time stamping be triggered (thus locking
4529 * the registers) without the packet reaching this point
4530 * here? In that case RX time stamping would get stuck.
4531 *
4532 * TODO: in "time stamp all packets" mode this bit is
4533 * not set. Need a global flag for this mode and then
4534 * always read the registers. Cannot be done without
4535 * a race condition.
4536 */
4537 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4538 u64 regval;
4539 u64 ns;
4540 struct skb_shared_hwtstamps *shhwtstamps =
4541 skb_hwtstamps(skb);
4542
4543 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4544 "igb: no RX time stamp available for time stamped packet");
4545 regval = rd32(E1000_RXSTMPL);
4546 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4547 ns = timecounter_cyc2time(&adapter->clock, regval);
4548 timecompare_update(&adapter->compare, ns);
4549 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4550 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4551 shhwtstamps->syststamp =
4552 timecompare_transform(&adapter->compare, ns);
4553 }
4554
9d5c8243
AK		 4555 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4556 dev_kfree_skb_irq(skb);
4557 goto next_desc;
4558 }
9d5c8243
AK		 4559
4560 total_bytes += skb->len;
4561 total_packets++;
4562
4563 igb_rx_checksum_adv(adapter, staterr, skb);
4564
4565 skb->protocol = eth_type_trans(skb, netdev);
4566
d3352520 4567 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 4568
9d5c8243
AK		 4569next_desc:
4570 rx_desc->wb.upper.status_error = 0;
4571
4572 /* return some buffers to hardware, one at a time is too slow */
4573 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4574 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4575 cleaned_count = 0;
4576 }
4577
4578 /* use prefetched values */
4579 rx_desc = next_rxd;
4580 buffer_info = next_buffer;
9d5c8243
AK		 4581 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4582 }
bf36c1a0 4583
9d5c8243
AK		 4584 rx_ring->next_to_clean = i;
4585 cleaned_count = IGB_DESC_UNUSED(rx_ring);
4586
4587 if (cleaned_count)
3b644cf6 4588 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4589
4590 rx_ring->total_packets += total_packets;
4591 rx_ring->total_bytes += total_bytes;
4592 rx_ring->rx_stats.packets += total_packets;
4593 rx_ring->rx_stats.bytes += total_bytes;
4594 adapter->net_stats.rx_bytes += total_bytes;
4595 adapter->net_stats.rx_packets += total_packets;
4596 return cleaned;
4597}
4598
9d5c8243
AK		 4599/**
4600 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4601 * @adapter: address of board private structure
4602 **/
3b644cf6 4603static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 4604 int cleaned_count)
4605{
3b644cf6 4606 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4607 struct net_device *netdev = adapter->netdev;
4608 struct pci_dev *pdev = adapter->pdev;
4609 union e1000_adv_rx_desc *rx_desc;
4610 struct igb_buffer *buffer_info;
4611 struct sk_buff *skb;
4612 unsigned int i;
db761762 4613 int bufsz;
9d5c8243
AK		 4614
4615 i = rx_ring->next_to_use;
4616 buffer_info = &rx_ring->buffer_info[i];
4617
db761762
AD		 4618 if (adapter->rx_ps_hdr_size)
4619 bufsz = adapter->rx_ps_hdr_size;
4620 else
4621 bufsz = adapter->rx_buffer_len;
4622 bufsz += NET_IP_ALIGN;
4623
9d5c8243
AK		 4624 while (cleaned_count--) {
4625 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4626
bf36c1a0 4627 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4628 if (!buffer_info->page) {
bf36c1a0
AD		 4629 buffer_info->page = alloc_page(GFP_ATOMIC);
4630 if (!buffer_info->page) {
4631 adapter->alloc_rx_buff_failed++;
4632 goto no_buffers;
4633 }
4634 buffer_info->page_offset = 0;
4635 } else {
4636 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4637 }
4638 buffer_info->page_dma =
db761762 4639 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 4640 buffer_info->page_offset,
4641 PAGE_SIZE / 2,
9d5c8243
AK		 4642 PCI_DMA_FROMDEVICE);
4643 }
4644
4645 if (!buffer_info->skb) {
9d5c8243 4646 skb = netdev_alloc_skb(netdev, bufsz);
9d5c8243
AK		 4647 if (!skb) {
4648 adapter->alloc_rx_buff_failed++;
4649 goto no_buffers;
4650 }
4651
4652 /* Make buffer alignment 2 beyond a 16 byte boundary
4653 * this will result in a 16 byte aligned IP header after
4654 * the 14 byte MAC header is removed
4655 */
4656 skb_reserve(skb, NET_IP_ALIGN);
4657
4658 buffer_info->skb = skb;
4659 buffer_info->dma = pci_map_single(pdev, skb->data,
4660 bufsz,
4661 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4662 }
4663 /* Refresh the desc even if buffer_addrs didn't change because
4664 * each write-back erases this info. */
4665 if (adapter->rx_ps_hdr_size) {
4666 rx_desc->read.pkt_addr =
4667 cpu_to_le64(buffer_info->page_dma);
4668 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4669 } else {
4670 rx_desc->read.pkt_addr =
4671 cpu_to_le64(buffer_info->dma);
4672 rx_desc->read.hdr_addr = 0;
4673 }
4674
4675 i++;
4676 if (i == rx_ring->count)
4677 i = 0;
4678 buffer_info = &rx_ring->buffer_info[i];
4679 }
4680
4681no_buffers:
4682 if (rx_ring->next_to_use != i) {
4683 rx_ring->next_to_use = i;
4684 if (i == 0)
4685 i = (rx_ring->count - 1);
4686 else
4687 i--;
4688
4689 /* Force memory writes to complete before letting h/w
4690 * know there are new descriptors to fetch. (Only
4691 * applicable for weak-ordered memory model archs,
4692 * such as IA-64). */
4693 wmb();
4694 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4695 }
4696}
4697
4698/**
4699 * igb_mii_ioctl -
4700 * @netdev:
4701 * @ifreq:
4702 * @cmd:
4703 **/
4704static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4705{
4706 struct igb_adapter *adapter = netdev_priv(netdev);
4707 struct mii_ioctl_data *data = if_mii(ifr);
4708
4709 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4710 return -EOPNOTSUPP;
4711
4712 switch (cmd) {
4713 case SIOCGMIIPHY:
4714 data->phy_id = adapter->hw.phy.addr;
4715 break;
4716 case SIOCGMIIREG:
4717 if (!capable(CAP_NET_ADMIN))
4718 return -EPERM;
f5f4cf08
AD		 4719 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4720 &data->val_out))
9d5c8243
AK		 4721 return -EIO;
4722 break;
4723 case SIOCSMIIREG:
4724 default:
4725 return -EOPNOTSUPP;
4726 }
4727 return 0;
4728}
4729
c6cb090b
PO		 4730/**
4731 * igb_hwtstamp_ioctl - control hardware time stamping
4732 * @netdev:
4733 * @ifreq:
4734 * @cmd:
4735 *
33af6bcc
PO		 4736 * Outgoing time stamping can be enabled and disabled. Play nice and
4737 * disable it when requested, although it shouldn't case any overhead
4738 * when no packet needs it. At most one packet in the queue may be
4739 * marked for time stamping, otherwise it would be impossible to tell
4740 * for sure to which packet the hardware time stamp belongs.
4741 *
4742 * Incoming time stamping has to be configured via the hardware
4743 * filters. Not all combinations are supported, in particular event
4744 * type has to be specified. Matching the kind of event packet is
4745 * not supported, with the exception of "all V2 events regardless of
4746 * level 2 or 4".
4747 *
c6cb090b
PO		 4748 **/
4749static int igb_hwtstamp_ioctl(struct net_device *netdev,
4750 struct ifreq *ifr, int cmd)
4751{
33af6bcc
PO		 4752 struct igb_adapter *adapter = netdev_priv(netdev);
4753 struct e1000_hw *hw = &adapter->hw;
c6cb090b 4754 struct hwtstamp_config config;
33af6bcc
PO		 4755 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4756 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4757 u32 tsync_rx_ctl_type = 0;
4758 u32 tsync_rx_cfg = 0;
4759 int is_l4 = 0;
4760 int is_l2 = 0;
4761 short port = 319; /* PTP */
4762 u32 regval;
c6cb090b
PO		 4763
4764 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4765 return -EFAULT;
4766
4767 /* reserved for future extensions */
4768 if (config.flags)
4769 return -EINVAL;
4770
33af6bcc
PO		 4771 switch (config.tx_type) {
4772 case HWTSTAMP_TX_OFF:
4773 tsync_tx_ctl_bit = 0;
4774 break;
4775 case HWTSTAMP_TX_ON:
4776 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4777 break;
4778 default:
4779 return -ERANGE;
4780 }
4781
4782 switch (config.rx_filter) {
4783 case HWTSTAMP_FILTER_NONE:
4784 tsync_rx_ctl_bit = 0;
4785 break;
4786 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4787 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4788 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4789 case HWTSTAMP_FILTER_ALL:
4790 /*
4791 * register TSYNCRXCFG must be set, therefore it is not
4792 * possible to time stamp both Sync and Delay_Req messages
4793 * => fall back to time stamping all packets
4794 */
4795 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4796 config.rx_filter = HWTSTAMP_FILTER_ALL;
4797 break;
4798 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4799 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4800 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4801 is_l4 = 1;
4802 break;
4803 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4804 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4805 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4806 is_l4 = 1;
4807 break;
4808 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4809 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4810 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4811 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4812 is_l2 = 1;
4813 is_l4 = 1;
4814 config.rx_filter = HWTSTAMP_FILTER_SOME;
4815 break;
4816 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4817 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4818 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4819 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4820 is_l2 = 1;
4821 is_l4 = 1;
4822 config.rx_filter = HWTSTAMP_FILTER_SOME;
4823 break;
4824 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4825 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4826 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4827 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4828 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4829 is_l2 = 1;
4830 break;
4831 default:
4832 return -ERANGE;
4833 }
4834
4835 /* enable/disable TX */
4836 regval = rd32(E1000_TSYNCTXCTL);
4837 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4838 wr32(E1000_TSYNCTXCTL, regval);
4839
4840 /* enable/disable RX, define which PTP packets are time stamped */
4841 regval = rd32(E1000_TSYNCRXCTL);
4842 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4843 regval = (regval & ~0xE) | tsync_rx_ctl_type;
4844 wr32(E1000_TSYNCRXCTL, regval);
4845 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4846
4847 /*
4848 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4849 * (Ethertype to filter on)
4850 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4851 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4852 */
4853 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4854
4855 /* L4 Queue Filter[0]: only filter by source and destination port */
4856 wr32(E1000_SPQF0, htons(port));
4857 wr32(E1000_IMIREXT(0), is_l4 ?
4858 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4859 wr32(E1000_IMIR(0), is_l4 ?
4860 (htons(port)
4861 | (0<<16) /* immediate interrupt disabled */
4862 | 0 /* (1<<17) bit cleared: do not bypass
4863 destination port check */)
4864 : 0);
4865 wr32(E1000_FTQF0, is_l4 ?
4866 (0x11 /* UDP */
4867 | (1<<15) /* VF not compared */
4868 | (1<<27) /* Enable Timestamping */
4869 | (7<<28) /* only source port filter enabled,
4870 source/target address and protocol
4871 masked */)
4872 : ((1<<15) | (15<<28) /* all mask bits set = filter not
4873 enabled */));
4874
4875 wrfl();
4876
4877 adapter->hwtstamp_config = config;
4878
4879 /* clear TX/RX time stamp registers, just to be sure */
4880 regval = rd32(E1000_TXSTMPH);
4881 regval = rd32(E1000_RXSTMPH);
c6cb090b 4882
33af6bcc
PO		 4883 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
4884 -EFAULT : 0;
c6cb090b
PO		 4885}
4886
9d5c8243
AK		 4887/**
4888 * igb_ioctl -
4889 * @netdev:
4890 * @ifreq:
4891 * @cmd:
4892 **/
4893static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4894{
4895 switch (cmd) {
4896 case SIOCGMIIPHY:
4897 case SIOCGMIIREG:
4898 case SIOCSMIIREG:
4899 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 4900 case SIOCSHWTSTAMP:
4901 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 4902 default:
4903 return -EOPNOTSUPP;
4904 }
4905}
4906
4907static void igb_vlan_rx_register(struct net_device *netdev,
4908 struct vlan_group *grp)
4909{
4910 struct igb_adapter *adapter = netdev_priv(netdev);
4911 struct e1000_hw *hw = &adapter->hw;
4912 u32 ctrl, rctl;
4913
4914 igb_irq_disable(adapter);
4915 adapter->vlgrp = grp;
4916
4917 if (grp) {
4918 /* enable VLAN tag insert/strip */
4919 ctrl = rd32(E1000_CTRL);
4920 ctrl |= E1000_CTRL_VME;
4921 wr32(E1000_CTRL, ctrl);
4922
4923 /* enable VLAN receive filtering */
4924 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4925 rctl &= ~E1000_RCTL_CFIEN;
4926 wr32(E1000_RCTL, rctl);
4927 igb_update_mng_vlan(adapter);
9d5c8243
AK		 4928 } else {
4929 /* disable VLAN tag insert/strip */
4930 ctrl = rd32(E1000_CTRL);
4931 ctrl &= ~E1000_CTRL_VME;
4932 wr32(E1000_CTRL, ctrl);
4933
9d5c8243
AK		 4934 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4935 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4936 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4937 }
9d5c8243
AK		 4938 }
4939
e1739522
AD		 4940 igb_rlpml_set(adapter);
4941
9d5c8243
AK		 4942 if (!test_bit(__IGB_DOWN, &adapter->state))
4943 igb_irq_enable(adapter);
4944}
4945
4946static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4947{
4948 struct igb_adapter *adapter = netdev_priv(netdev);
4949 struct e1000_hw *hw = &adapter->hw;
4ae196df 4950 int pf_id = adapter->vfs_allocated_count;
9d5c8243 4951
28b0759c 4952 if ((hw->mng_cookie.status &
9d5c8243
AK		 4953 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4954 (vid == adapter->mng_vlan_id))
4955 return;
4ae196df
AD		 4956
4957 /* add vid to vlvf if sr-iov is enabled,
4958 * if that fails add directly to filter table */
4959 if (igb_vlvf_set(adapter, vid, true, pf_id))
4960 igb_vfta_set(hw, vid, true);
4961
9d5c8243
AK		 4962}
4963
4964static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4965{
4966 struct igb_adapter *adapter = netdev_priv(netdev);
4967 struct e1000_hw *hw = &adapter->hw;
4ae196df 4968 int pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 4969
4970 igb_irq_disable(adapter);
4971 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4972
4973 if (!test_bit(__IGB_DOWN, &adapter->state))
4974 igb_irq_enable(adapter);
4975
4976 if ((adapter->hw.mng_cookie.status &
4977 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4978 (vid == adapter->mng_vlan_id)) {
4979 /* release control to f/w */
4980 igb_release_hw_control(adapter);
4981 return;
4982 }
4983
4ae196df
AD		 4984 /* remove vid from vlvf if sr-iov is enabled,
4985 * if not in vlvf remove from vfta */
4986 if (igb_vlvf_set(adapter, vid, false, pf_id))
4987 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 4988}
4989
4990static void igb_restore_vlan(struct igb_adapter *adapter)
4991{
4992 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4993
4994 if (adapter->vlgrp) {
4995 u16 vid;
4996 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4997 if (!vlan_group_get_device(adapter->vlgrp, vid))
4998 continue;
4999 igb_vlan_rx_add_vid(adapter->netdev, vid);
5000 }
5001 }
5002}
5003
5004int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5005{
5006 struct e1000_mac_info *mac = &adapter->hw.mac;
5007
5008 mac->autoneg = 0;
5009
5010 /* Fiber NICs only allow 1000 gbps Full duplex */
5011 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
5012 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5013 dev_err(&adapter->pdev->dev,
5014 "Unsupported Speed/Duplex configuration\n");
5015 return -EINVAL;
5016 }
5017
5018 switch (spddplx) {
5019 case SPEED_10 + DUPLEX_HALF:
5020 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5021 break;
5022 case SPEED_10 + DUPLEX_FULL:
5023 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5024 break;
5025 case SPEED_100 + DUPLEX_HALF:
5026 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5027 break;
5028 case SPEED_100 + DUPLEX_FULL:
5029 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5030 break;
5031 case SPEED_1000 + DUPLEX_FULL:
5032 mac->autoneg = 1;
5033 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5034 break;
5035 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5036 default:
5037 dev_err(&adapter->pdev->dev,
5038 "Unsupported Speed/Duplex configuration\n");
5039 return -EINVAL;
5040 }
5041 return 0;
5042}
5043
9d5c8243
AK		 5044static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5045{
5046 struct net_device *netdev = pci_get_drvdata(pdev);
5047 struct igb_adapter *adapter = netdev_priv(netdev);
5048 struct e1000_hw *hw = &adapter->hw;
2d064c06 5049 u32 ctrl, rctl, status;
9d5c8243
AK		 5050 u32 wufc = adapter->wol;
5051#ifdef CONFIG_PM
5052 int retval = 0;
5053#endif
5054
5055 netif_device_detach(netdev);
5056
a88f10ec
AD		 5057 if (netif_running(netdev))
5058 igb_close(netdev);
5059
5060 igb_reset_interrupt_capability(adapter);
5061
5062 igb_free_queues(adapter);
9d5c8243
AK		 5063
5064#ifdef CONFIG_PM
5065 retval = pci_save_state(pdev);
5066 if (retval)
5067 return retval;
5068#endif
5069
5070 status = rd32(E1000_STATUS);
5071 if (status & E1000_STATUS_LU)
5072 wufc &= ~E1000_WUFC_LNKC;
5073
5074 if (wufc) {
5075 igb_setup_rctl(adapter);
5076 igb_set_multi(netdev);
5077
5078 /* turn on all-multi mode if wake on multicast is enabled */
5079 if (wufc & E1000_WUFC_MC) {
5080 rctl = rd32(E1000_RCTL);
5081 rctl |= E1000_RCTL_MPE;
5082 wr32(E1000_RCTL, rctl);
5083 }
5084
5085 ctrl = rd32(E1000_CTRL);
5086 /* advertise wake from D3Cold */
5087 #define E1000_CTRL_ADVD3WUC 0x00100000
5088 /* phy power management enable */
5089 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5090 ctrl |= E1000_CTRL_ADVD3WUC;
5091 wr32(E1000_CTRL, ctrl);
5092
9d5c8243
AK		 5093 /* Allow time for pending master requests to run */
5094 igb_disable_pcie_master(&adapter->hw);
5095
5096 wr32(E1000_WUC, E1000_WUC_PME_EN);
5097 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5098 } else {
5099 wr32(E1000_WUC, 0);
5100 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5101 }
5102
2d064c06
AD		 5103 /* make sure adapter isn't asleep if manageability/wol is enabled */
5104 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 5105 pci_enable_wake(pdev, PCI_D3hot, 1);
5106 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 5107 } else {
5108 igb_shutdown_fiber_serdes_link_82575(hw);
5109 pci_enable_wake(pdev, PCI_D3hot, 0);
5110 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 5111 }
5112
5113 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5114 * would have already happened in close and is redundant. */
5115 igb_release_hw_control(adapter);
5116
5117 pci_disable_device(pdev);
5118
5119 pci_set_power_state(pdev, pci_choose_state(pdev, state));
5120
5121 return 0;
5122}
5123
5124#ifdef CONFIG_PM
5125static int igb_resume(struct pci_dev *pdev)
5126{
5127 struct net_device *netdev = pci_get_drvdata(pdev);
5128 struct igb_adapter *adapter = netdev_priv(netdev);
5129 struct e1000_hw *hw = &adapter->hw;
5130 u32 err;
5131
5132 pci_set_power_state(pdev, PCI_D0);
5133 pci_restore_state(pdev);
42bfd33a 5134
aed5dec3 5135 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5136 if (err) {
5137 dev_err(&pdev->dev,
5138 "igb: Cannot enable PCI device from suspend\n");
5139 return err;
5140 }
5141 pci_set_master(pdev);
5142
5143 pci_enable_wake(pdev, PCI_D3hot, 0);
5144 pci_enable_wake(pdev, PCI_D3cold, 0);
5145
a88f10ec
AD		 5146 igb_set_interrupt_capability(adapter);
5147
5148 if (igb_alloc_queues(adapter)) {
5149 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5150 return -ENOMEM;
9d5c8243
AK		 5151 }
5152
5153 /* e1000_power_up_phy(adapter); */
5154
5155 igb_reset(adapter);
a8564f03
AD		 5156
5157 /* let the f/w know that the h/w is now under the control of the
5158 * driver. */
5159 igb_get_hw_control(adapter);
5160
9d5c8243
AK		 5161 wr32(E1000_WUS, ~0);
5162
a88f10ec
AD		 5163 if (netif_running(netdev)) {
5164 err = igb_open(netdev);
5165 if (err)
5166 return err;
5167 }
9d5c8243
AK		 5168
5169 netif_device_attach(netdev);
5170
9d5c8243
AK		 5171 return 0;
5172}
5173#endif
5174
5175static void igb_shutdown(struct pci_dev *pdev)
5176{
5177 igb_suspend(pdev, PMSG_SUSPEND);
5178}
5179
5180#ifdef CONFIG_NET_POLL_CONTROLLER
5181/*
5182 * Polling 'interrupt' - used by things like netconsole to send skbs
5183 * without having to re-enable interrupts. It's not called while
5184 * the interrupt routine is executing.
5185 */
5186static void igb_netpoll(struct net_device *netdev)
5187{
5188 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5189 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5190 int i;
9d5c8243 5191
eebbbdba
AD		 5192 if (!adapter->msix_entries) {
5193 igb_irq_disable(adapter);
5194 napi_schedule(&adapter->rx_ring[0].napi);
5195 return;
5196 }
9d5c8243 5197
eebbbdba
AD		 5198 for (i = 0; i < adapter->num_tx_queues; i++) {
5199 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5200 wr32(E1000_EIMC, tx_ring->eims_value);
5201 igb_clean_tx_irq(tx_ring);
5202 wr32(E1000_EIMS, tx_ring->eims_value);
5203 }
9d5c8243 5204
eebbbdba
AD		 5205 for (i = 0; i < adapter->num_rx_queues; i++) {
5206 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5207 wr32(E1000_EIMC, rx_ring->eims_value);
5208 napi_schedule(&rx_ring->napi);
5209 }
9d5c8243
AK		 5210}
5211#endif /* CONFIG_NET_POLL_CONTROLLER */
5212
5213/**
5214 * igb_io_error_detected - called when PCI error is detected
5215 * @pdev: Pointer to PCI device
5216 * @state: The current pci connection state
5217 *
5218 * This function is called after a PCI bus error affecting
5219 * this device has been detected.
5220 */
5221static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5222 pci_channel_state_t state)
5223{
5224 struct net_device *netdev = pci_get_drvdata(pdev);
5225 struct igb_adapter *adapter = netdev_priv(netdev);
5226
5227 netif_device_detach(netdev);
5228
5229 if (netif_running(netdev))
5230 igb_down(adapter);
5231 pci_disable_device(pdev);
5232
5233 /* Request a slot slot reset. */
5234 return PCI_ERS_RESULT_NEED_RESET;
5235}
5236
5237/**
5238 * igb_io_slot_reset - called after the pci bus has been reset.
5239 * @pdev: Pointer to PCI device
5240 *
5241 * Restart the card from scratch, as if from a cold-boot. Implementation
5242 * resembles the first-half of the igb_resume routine.
5243 */
5244static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5245{
5246 struct net_device *netdev = pci_get_drvdata(pdev);
5247 struct igb_adapter *adapter = netdev_priv(netdev);
5248 struct e1000_hw *hw = &adapter->hw;
40a914fa 5249 pci_ers_result_t result;
42bfd33a 5250 int err;
9d5c8243 5251
aed5dec3 5252 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5253 dev_err(&pdev->dev,
5254 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5255 result = PCI_ERS_RESULT_DISCONNECT;
5256 } else {
5257 pci_set_master(pdev);
5258 pci_restore_state(pdev);
9d5c8243 5259
40a914fa
AD		 5260 pci_enable_wake(pdev, PCI_D3hot, 0);
5261 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5262
40a914fa
AD		 5263 igb_reset(adapter);
5264 wr32(E1000_WUS, ~0);
5265 result = PCI_ERS_RESULT_RECOVERED;
5266 }
9d5c8243 5267
ea943d41
JK		 5268 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5269 if (err) {
5270 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5271 "failed 0x%0x\n", err);
5272 /* non-fatal, continue */
5273 }
40a914fa
AD		 5274
5275 return result;
9d5c8243
AK		 5276}
5277
5278/**
5279 * igb_io_resume - called when traffic can start flowing again.
5280 * @pdev: Pointer to PCI device
5281 *
5282 * This callback is called when the error recovery driver tells us that
5283 * its OK to resume normal operation. Implementation resembles the
5284 * second-half of the igb_resume routine.
5285 */
5286static void igb_io_resume(struct pci_dev *pdev)
5287{
5288 struct net_device *netdev = pci_get_drvdata(pdev);
5289 struct igb_adapter *adapter = netdev_priv(netdev);
5290
9d5c8243
AK		 5291 if (netif_running(netdev)) {
5292 if (igb_up(adapter)) {
5293 dev_err(&pdev->dev, "igb_up failed after reset\n");
5294 return;
5295 }
5296 }
5297
5298 netif_device_attach(netdev);
5299
5300 /* let the f/w know that the h/w is now under the control of the
5301 * driver. */
5302 igb_get_hw_control(adapter);
9d5c8243
AK		 5303}
5304
e1739522
AD		 5305static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
5306{
5307 u32 reg_data;
5308
5309 reg_data = rd32(E1000_VMOLR(vfn));
5310 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
5311 E1000_VMOLR_ROPE | /* Accept packets matched in UTA */
5312 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
5313 E1000_VMOLR_AUPE | /* Accept untagged packets */
5314 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
5315 wr32(E1000_VMOLR(vfn), reg_data);
5316}
5317
4ae196df
AD		 5318static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
5319 int vfn)
e1739522
AD		 5320{
5321 struct e1000_hw *hw = &adapter->hw;
5322 u32 vmolr;
5323
5324 vmolr = rd32(E1000_VMOLR(vfn));
5325 vmolr &= ~E1000_VMOLR_RLPML_MASK;
5326 vmolr |= size | E1000_VMOLR_LPE;
5327 wr32(E1000_VMOLR(vfn), vmolr);
4ae196df
AD		 5328
5329 return 0;
e1739522
AD		 5330}
5331
5332static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
5333{
5334 u32 reg_data;
5335
5336 reg_data = rd32(E1000_RAH(entry));
5337 reg_data &= ~E1000_RAH_POOL_MASK;
5338 reg_data |= E1000_RAH_POOL_1 << pool;;
5339 wr32(E1000_RAH(entry), reg_data);
5340}
5341
5342static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5343 int entry_count, u16 total_rar_filters)
5344{
5345 struct e1000_hw *hw = &adapter->hw;
5346 int i = adapter->vfs_allocated_count + 1;
5347
5348 if ((i + entry_count) < total_rar_filters)
5349 total_rar_filters = i + entry_count;
5350
5351 for (; i < total_rar_filters; i++)
5352 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5353}
5354
4ae196df
AD		 5355static int igb_set_vf_mac(struct igb_adapter *adapter,
5356 int vf, unsigned char *mac_addr)
5357{
5358 struct e1000_hw *hw = &adapter->hw;
5359 int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5360
5361 igb_rar_set(hw, mac_addr, rar_entry);
5362
37680117 5363 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df
AD		 5364
5365 igb_set_rah_pool(hw, vf, rar_entry);
5366
5367 return 0;
5368}
5369
5370static void igb_vmm_control(struct igb_adapter *adapter)
5371{
5372 struct e1000_hw *hw = &adapter->hw;
5373 u32 reg_data;
5374
5375 if (!adapter->vfs_allocated_count)
5376 return;
5377
5378 /* VF's need PF reset indication before they
5379 * can send/receive mail */
5380 reg_data = rd32(E1000_CTRL_EXT);
5381 reg_data |= E1000_CTRL_EXT_PFRSTD;
5382 wr32(E1000_CTRL_EXT, reg_data);
5383
5384 igb_vmdq_set_loopback_pf(hw, true);
5385 igb_vmdq_set_replication_pf(hw, true);
5386}
5387
37680117
AD		 5388#ifdef CONFIG_PCI_IOV
5389static ssize_t igb_show_num_vfs(struct device *dev,
5390 struct device_attribute *attr, char *buf)
5391{
5392 struct igb_adapter *adapter = netdev_priv(to_net_dev(dev));
5393
5394 return sprintf(buf, "%d\n", adapter->vfs_allocated_count);
5395}
5396
5397static ssize_t igb_set_num_vfs(struct device *dev,
5398 struct device_attribute *attr,
5399 const char *buf, size_t count)
5400{
5401 struct net_device *netdev = to_net_dev(dev);
5402 struct igb_adapter *adapter = netdev_priv(netdev);
5403 struct e1000_hw *hw = &adapter->hw;
5404 struct pci_dev *pdev = adapter->pdev;
5405 unsigned int num_vfs, i;
5406 unsigned char mac_addr[ETH_ALEN];
5407 int err;
5408
5409 sscanf(buf, "%u", &num_vfs);
5410
5411 if (num_vfs > 7)
5412 num_vfs = 7;
5413
5414 /* value unchanged do nothing */
5415 if (num_vfs == adapter->vfs_allocated_count)
5416 return count;
5417
5418 if (netdev->flags & IFF_UP)
5419 igb_close(netdev);
5420
5421 igb_reset_interrupt_capability(adapter);
5422 igb_free_queues(adapter);
5423 adapter->tx_ring = NULL;
5424 adapter->rx_ring = NULL;
5425 adapter->vfs_allocated_count = 0;
5426
5427 /* reclaim resources allocated to VFs since we are changing count */
5428 if (adapter->vf_data) {
5429 /* disable iov and allow time for transactions to clear */
5430 pci_disable_sriov(pdev);
5431 msleep(500);
5432
5433 kfree(adapter->vf_data);
5434 adapter->vf_data = NULL;
5435 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
5436 msleep(100);
5437 dev_info(&pdev->dev, "IOV Disabled\n");
5438 }
5439
5440 if (num_vfs) {
5441 adapter->vf_data = kcalloc(num_vfs,
5442 sizeof(struct vf_data_storage),
5443 GFP_KERNEL);
5444 if (!adapter->vf_data) {
5445 dev_err(&pdev->dev, "Could not allocate VF private "
5446 "data - IOV enable failed\n");
5447 } else {
5448 err = pci_enable_sriov(pdev, num_vfs);
5449 if (!err) {
5450 adapter->vfs_allocated_count = num_vfs;
5451 dev_info(&pdev->dev, "%d vfs allocated\n", num_vfs);
5452 for (i = 0; i < adapter->vfs_allocated_count; i++) {
5453 random_ether_addr(mac_addr);
5454 igb_set_vf_mac(adapter, i, mac_addr);
5455 }
5456 } else {
5457 kfree(adapter->vf_data);
5458 adapter->vf_data = NULL;
5459 }
5460 }
5461 }
5462
5463 igb_set_interrupt_capability(adapter);
5464 igb_alloc_queues(adapter);
5465 igb_reset(adapter);
5466
5467 if (netdev->flags & IFF_UP)
5468 igb_open(netdev);
5469
5470 return count;
5471}
5472#endif /* CONFIG_PCI_IOV */
9d5c8243 5473/* igb_main.c */
Linux 6.x block layer and io_uring tree(s)