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igb: rename igb_update_mc_addr_list_82575 to not include the 82575
[linux-block.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
c54106bb 41#include <linux/pci-aspm.h>
9d5c8243
AK		 42#include <linux/delay.h>
43#include <linux/interrupt.h>
44#include <linux/if_ether.h>
40a914fa 45#include <linux/aer.h>
421e02f0 46#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 47#include <linux/dca.h>
48#endif
9d5c8243
AK		 49#include "igb.h"
50
0024fd00 51#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 52char igb_driver_name[] = "igb";
53char igb_driver_version[] = DRV_VERSION;
54static const char igb_driver_string[] =
55 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 56static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 57
9d5c8243
AK		 58static const struct e1000_info *igb_info_tbl[] = {
59 [board_82575] = &e1000_82575_info,
60};
61
62static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
69 /* required last entry */
70 {0, }
71};
72
73MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
74
75void igb_reset(struct igb_adapter *);
76static int igb_setup_all_tx_resources(struct igb_adapter *);
77static int igb_setup_all_rx_resources(struct igb_adapter *);
78static void igb_free_all_tx_resources(struct igb_adapter *);
79static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 80void igb_update_stats(struct igb_adapter *);
81static int igb_probe(struct pci_dev *, const struct pci_device_id *);
82static void __devexit igb_remove(struct pci_dev *pdev);
83static int igb_sw_init(struct igb_adapter *);
84static int igb_open(struct net_device *);
85static int igb_close(struct net_device *);
86static void igb_configure_tx(struct igb_adapter *);
87static void igb_configure_rx(struct igb_adapter *);
88static void igb_setup_rctl(struct igb_adapter *);
89static void igb_clean_all_tx_rings(struct igb_adapter *);
90static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 91static void igb_clean_tx_ring(struct igb_ring *);
92static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 93static void igb_set_multi(struct net_device *);
94static void igb_update_phy_info(unsigned long);
95static void igb_watchdog(unsigned long);
96static void igb_watchdog_task(struct work_struct *);
97static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
98 struct igb_ring *);
99static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
100static struct net_device_stats *igb_get_stats(struct net_device *);
101static int igb_change_mtu(struct net_device *, int);
102static int igb_set_mac(struct net_device *, void *);
103static irqreturn_t igb_intr(int irq, void *);
104static irqreturn_t igb_intr_msi(int irq, void *);
105static irqreturn_t igb_msix_other(int irq, void *);
106static irqreturn_t igb_msix_rx(int irq, void *);
107static irqreturn_t igb_msix_tx(int irq, void *);
108static int igb_clean_rx_ring_msix(struct napi_struct *, int);
421e02f0 109#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 110static void igb_update_rx_dca(struct igb_ring *);
111static void igb_update_tx_dca(struct igb_ring *);
112static void igb_setup_dca(struct igb_adapter *);
421e02f0 113#endif /* CONFIG_IGB_DCA */
3b644cf6 114static bool igb_clean_tx_irq(struct igb_ring *);
661086df 115static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 116static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
117static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 118static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
119static void igb_tx_timeout(struct net_device *);
120static void igb_reset_task(struct work_struct *);
121static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
122static void igb_vlan_rx_add_vid(struct net_device *, u16);
123static void igb_vlan_rx_kill_vid(struct net_device *, u16);
124static void igb_restore_vlan(struct igb_adapter *);
125
126static int igb_suspend(struct pci_dev *, pm_message_t);
127#ifdef CONFIG_PM
128static int igb_resume(struct pci_dev *);
129#endif
130static void igb_shutdown(struct pci_dev *);
421e02f0 131#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 132static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
133static struct notifier_block dca_notifier = {
134 .notifier_call = igb_notify_dca,
135 .next = NULL,
136 .priority = 0
137};
138#endif
9d5c8243
AK		 139
140#ifdef CONFIG_NET_POLL_CONTROLLER
141/* for netdump / net console */
142static void igb_netpoll(struct net_device *);
143#endif
144
145static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
146 pci_channel_state_t);
147static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
148static void igb_io_resume(struct pci_dev *);
149
150static struct pci_error_handlers igb_err_handler = {
151 .error_detected = igb_io_error_detected,
152 .slot_reset = igb_io_slot_reset,
153 .resume = igb_io_resume,
154};
155
156
157static struct pci_driver igb_driver = {
158 .name = igb_driver_name,
159 .id_table = igb_pci_tbl,
160 .probe = igb_probe,
161 .remove = __devexit_p(igb_remove),
162#ifdef CONFIG_PM
163 /* Power Managment Hooks */
164 .suspend = igb_suspend,
165 .resume = igb_resume,
166#endif
167 .shutdown = igb_shutdown,
168 .err_handler = &igb_err_handler
169};
170
7dfc16fa
AD		 171static int global_quad_port_a; /* global quad port a indication */
172
9d5c8243
AK		 173MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
174MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
175MODULE_LICENSE("GPL");
176MODULE_VERSION(DRV_VERSION);
177
178#ifdef DEBUG
179/**
180 * igb_get_hw_dev_name - return device name string
181 * used by hardware layer to print debugging information
182 **/
183char *igb_get_hw_dev_name(struct e1000_hw *hw)
184{
185 struct igb_adapter *adapter = hw->back;
186 return adapter->netdev->name;
187}
188#endif
189
190/**
191 * igb_init_module - Driver Registration Routine
192 *
193 * igb_init_module is the first routine called when the driver is
194 * loaded. All it does is register with the PCI subsystem.
195 **/
196static int __init igb_init_module(void)
197{
198 int ret;
199 printk(KERN_INFO "%s - version %s\n",
200 igb_driver_string, igb_driver_version);
201
202 printk(KERN_INFO "%s\n", igb_copyright);
203
7dfc16fa
AD		 204 global_quad_port_a = 0;
205
421e02f0 206#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 207 dca_register_notify(&dca_notifier);
208#endif
bbd98fe4
AD		 209
210 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 211 return ret;
212}
213
214module_init(igb_init_module);
215
216/**
217 * igb_exit_module - Driver Exit Cleanup Routine
218 *
219 * igb_exit_module is called just before the driver is removed
220 * from memory.
221 **/
222static void __exit igb_exit_module(void)
223{
421e02f0 224#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 225 dca_unregister_notify(&dca_notifier);
226#endif
9d5c8243
AK		 227 pci_unregister_driver(&igb_driver);
228}
229
230module_exit(igb_exit_module);
231
26bc19ec
AD		 232#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
233/**
234 * igb_cache_ring_register - Descriptor ring to register mapping
235 * @adapter: board private structure to initialize
236 *
237 * Once we know the feature-set enabled for the device, we'll cache
238 * the register offset the descriptor ring is assigned to.
239 **/
240static void igb_cache_ring_register(struct igb_adapter *adapter)
241{
242 int i;
243
244 switch (adapter->hw.mac.type) {
245 case e1000_82576:
246 /* The queues are allocated for virtualization such that VF 0
247 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
248 * In order to avoid collision we start at the first free queue
249 * and continue consuming queues in the same sequence
250 */
251 for (i = 0; i < adapter->num_rx_queues; i++)
252 adapter->rx_ring[i].reg_idx = Q_IDX_82576(i);
253 for (i = 0; i < adapter->num_tx_queues; i++)
254 adapter->tx_ring[i].reg_idx = Q_IDX_82576(i);
255 break;
256 case e1000_82575:
257 default:
258 for (i = 0; i < adapter->num_rx_queues; i++)
259 adapter->rx_ring[i].reg_idx = i;
260 for (i = 0; i < adapter->num_tx_queues; i++)
261 adapter->tx_ring[i].reg_idx = i;
262 break;
263 }
264}
265
9d5c8243
AK		 266/**
267 * igb_alloc_queues - Allocate memory for all rings
268 * @adapter: board private structure to initialize
269 *
270 * We allocate one ring per queue at run-time since we don't know the
271 * number of queues at compile-time.
272 **/
273static int igb_alloc_queues(struct igb_adapter *adapter)
274{
275 int i;
276
277 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
278 sizeof(struct igb_ring), GFP_KERNEL);
279 if (!adapter->tx_ring)
280 return -ENOMEM;
281
282 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
283 sizeof(struct igb_ring), GFP_KERNEL);
284 if (!adapter->rx_ring) {
285 kfree(adapter->tx_ring);
286 return -ENOMEM;
287 }
288
6eb5a7f1
AD		 289 adapter->rx_ring->buddy = adapter->tx_ring;
290
661086df
PWJ		 291 for (i = 0; i < adapter->num_tx_queues; i++) {
292 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 293 ring->count = adapter->tx_ring_count;
661086df
PWJ		 294 ring->adapter = adapter;
295 ring->queue_index = i;
296 }
9d5c8243
AK		 297 for (i = 0; i < adapter->num_rx_queues; i++) {
298 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 299 ring->count = adapter->rx_ring_count;
9d5c8243 300 ring->adapter = adapter;
844290e5 301 ring->queue_index = i;
9d5c8243
AK		 302 ring->itr_register = E1000_ITR;
303
844290e5 304 /* set a default napi handler for each rx_ring */
661086df 305 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 306 }
26bc19ec
AD		 307
308 igb_cache_ring_register(adapter);
9d5c8243
AK		 309 return 0;
310}
311
a88f10ec
AD		 312static void igb_free_queues(struct igb_adapter *adapter)
313{
314 int i;
315
316 for (i = 0; i < adapter->num_rx_queues; i++)
317 netif_napi_del(&adapter->rx_ring[i].napi);
318
319 kfree(adapter->tx_ring);
320 kfree(adapter->rx_ring);
321}
322
9d5c8243
AK		 323#define IGB_N0_QUEUE -1
324static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
325 int tx_queue, int msix_vector)
326{
327 u32 msixbm = 0;
328 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 329 u32 ivar, index;
330
331 switch (hw->mac.type) {
332 case e1000_82575:
9d5c8243
AK		 333 /* The 82575 assigns vectors using a bitmask, which matches the
334 bitmask for the EICR/EIMS/EIMC registers. To assign one
335 or more queues to a vector, we write the appropriate bits
336 into the MSIXBM register for that vector. */
337 if (rx_queue > IGB_N0_QUEUE) {
338 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
339 adapter->rx_ring[rx_queue].eims_value = msixbm;
340 }
341 if (tx_queue > IGB_N0_QUEUE) {
342 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
343 adapter->tx_ring[tx_queue].eims_value =
344 E1000_EICR_TX_QUEUE0 << tx_queue;
345 }
346 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 347 break;
348 case e1000_82576:
26bc19ec 349 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 350 Each queue has a single entry in the table to which we write
351 a vector number along with a "valid" bit. Sadly, the layout
352 of the table is somewhat counterintuitive. */
353 if (rx_queue > IGB_N0_QUEUE) {
26bc19ec 354 index = (rx_queue >> 1);
2d064c06 355 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 356 if (rx_queue & 0x1) {
2d064c06
AD		 357 /* vector goes into third byte of register */
358 ivar = ivar & 0xFF00FFFF;
359 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 360 } else {
361 /* vector goes into low byte of register */
362 ivar = ivar & 0xFFFFFF00;
363 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 364 }
365 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
366 array_wr32(E1000_IVAR0, index, ivar);
367 }
368 if (tx_queue > IGB_N0_QUEUE) {
26bc19ec 369 index = (tx_queue >> 1);
2d064c06 370 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 371 if (tx_queue & 0x1) {
2d064c06
AD		 372 /* vector goes into high byte of register */
373 ivar = ivar & 0x00FFFFFF;
374 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 375 } else {
376 /* vector goes into second byte of register */
377 ivar = ivar & 0xFFFF00FF;
378 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 379 }
380 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
381 array_wr32(E1000_IVAR0, index, ivar);
382 }
383 break;
384 default:
385 BUG();
386 break;
387 }
9d5c8243
AK		 388}
389
390/**
391 * igb_configure_msix - Configure MSI-X hardware
392 *
393 * igb_configure_msix sets up the hardware to properly
394 * generate MSI-X interrupts.
395 **/
396static void igb_configure_msix(struct igb_adapter *adapter)
397{
398 u32 tmp;
399 int i, vector = 0;
400 struct e1000_hw *hw = &adapter->hw;
401
402 adapter->eims_enable_mask = 0;
2d064c06
AD		 403 if (hw->mac.type == e1000_82576)
404 /* Turn on MSI-X capability first, or our settings
405 * won't stick. And it will take days to debug. */
406 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 407 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 408 E1000_GPIE_NSICR);
9d5c8243
AK		 409
410 for (i = 0; i < adapter->num_tx_queues; i++) {
411 struct igb_ring *tx_ring = &adapter->tx_ring[i];
412 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
413 adapter->eims_enable_mask |= tx_ring->eims_value;
414 if (tx_ring->itr_val)
6eb5a7f1 415 writel(tx_ring->itr_val,
9d5c8243
AK		 416 hw->hw_addr + tx_ring->itr_register);
417 else
418 writel(1, hw->hw_addr + tx_ring->itr_register);
419 }
420
421 for (i = 0; i < adapter->num_rx_queues; i++) {
422 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 423 rx_ring->buddy = NULL;
9d5c8243
AK		 424 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
425 adapter->eims_enable_mask |= rx_ring->eims_value;
426 if (rx_ring->itr_val)
6eb5a7f1 427 writel(rx_ring->itr_val,
9d5c8243
AK		 428 hw->hw_addr + rx_ring->itr_register);
429 else
430 writel(1, hw->hw_addr + rx_ring->itr_register);
431 }
432
433
434 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 435 switch (hw->mac.type) {
436 case e1000_82575:
9d5c8243
AK		 437 array_wr32(E1000_MSIXBM(0), vector++,
438 E1000_EIMS_OTHER);
439
9d5c8243
AK		 440 tmp = rd32(E1000_CTRL_EXT);
441 /* enable MSI-X PBA support*/
442 tmp |= E1000_CTRL_EXT_PBA_CLR;
443
444 /* Auto-Mask interrupts upon ICR read. */
445 tmp |= E1000_CTRL_EXT_EIAME;
446 tmp |= E1000_CTRL_EXT_IRCA;
447
448 wr32(E1000_CTRL_EXT, tmp);
449 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 450 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 451
2d064c06
AD		 452 break;
453
454 case e1000_82576:
455 tmp = (vector++ | E1000_IVAR_VALID) << 8;
456 wr32(E1000_IVAR_MISC, tmp);
457
458 adapter->eims_enable_mask = (1 << (vector)) - 1;
459 adapter->eims_other = 1 << (vector - 1);
460 break;
461 default:
462 /* do nothing, since nothing else supports MSI-X */
463 break;
464 } /* switch (hw->mac.type) */
9d5c8243
AK		 465 wrfl();
466}
467
468/**
469 * igb_request_msix - Initialize MSI-X interrupts
470 *
471 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
472 * kernel.
473 **/
474static int igb_request_msix(struct igb_adapter *adapter)
475{
476 struct net_device *netdev = adapter->netdev;
477 int i, err = 0, vector = 0;
478
479 vector = 0;
480
481 for (i = 0; i < adapter->num_tx_queues; i++) {
482 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 483 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 484 err = request_irq(adapter->msix_entries[vector].vector,
485 &igb_msix_tx, 0, ring->name,
486 &(adapter->tx_ring[i]));
487 if (err)
488 goto out;
489 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 490 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 491 vector++;
492 }
493 for (i = 0; i < adapter->num_rx_queues; i++) {
494 struct igb_ring *ring = &(adapter->rx_ring[i]);
495 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 496 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 497 else
498 memcpy(ring->name, netdev->name, IFNAMSIZ);
499 err = request_irq(adapter->msix_entries[vector].vector,
500 &igb_msix_rx, 0, ring->name,
501 &(adapter->rx_ring[i]));
502 if (err)
503 goto out;
504 ring->itr_register = E1000_EITR(0) + (vector << 2);
505 ring->itr_val = adapter->itr;
844290e5
PW		 506 /* overwrite the poll routine for MSIX, we've already done
507 * netif_napi_add */
508 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 509 vector++;
510 }
511
512 err = request_irq(adapter->msix_entries[vector].vector,
513 &igb_msix_other, 0, netdev->name, netdev);
514 if (err)
515 goto out;
516
9d5c8243
AK		 517 igb_configure_msix(adapter);
518 return 0;
519out:
520 return err;
521}
522
523static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
524{
525 if (adapter->msix_entries) {
526 pci_disable_msix(adapter->pdev);
527 kfree(adapter->msix_entries);
528 adapter->msix_entries = NULL;
7dfc16fa 529 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 530 pci_disable_msi(adapter->pdev);
531 return;
532}
533
534
535/**
536 * igb_set_interrupt_capability - set MSI or MSI-X if supported
537 *
538 * Attempt to configure interrupts using the best available
539 * capabilities of the hardware and kernel.
540 **/
541static void igb_set_interrupt_capability(struct igb_adapter *adapter)
542{
543 int err;
544 int numvecs, i;
545
83b7180d
AD		 546 /* Number of supported queues. */
547 /* Having more queues than CPUs doesn't make sense. */
548 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
549 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
550
9d5c8243
AK		 551 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
552 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
553 GFP_KERNEL);
554 if (!adapter->msix_entries)
555 goto msi_only;
556
557 for (i = 0; i < numvecs; i++)
558 adapter->msix_entries[i].entry = i;
559
560 err = pci_enable_msix(adapter->pdev,
561 adapter->msix_entries,
562 numvecs);
563 if (err == 0)
34a20e89 564 goto out;
9d5c8243
AK		 565
566 igb_reset_interrupt_capability(adapter);
567
568 /* If we can't do MSI-X, try MSI */
569msi_only:
570 adapter->num_rx_queues = 1;
661086df 571 adapter->num_tx_queues = 1;
9d5c8243 572 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 573 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 574out:
661086df 575 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 576 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 577 return;
578}
579
580/**
581 * igb_request_irq - initialize interrupts
582 *
583 * Attempts to configure interrupts using the best available
584 * capabilities of the hardware and kernel.
585 **/
586static int igb_request_irq(struct igb_adapter *adapter)
587{
588 struct net_device *netdev = adapter->netdev;
589 struct e1000_hw *hw = &adapter->hw;
590 int err = 0;
591
592 if (adapter->msix_entries) {
593 err = igb_request_msix(adapter);
844290e5 594 if (!err)
9d5c8243 595 goto request_done;
9d5c8243
AK		 596 /* fall back to MSI */
597 igb_reset_interrupt_capability(adapter);
598 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 599 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 600 igb_free_all_tx_resources(adapter);
601 igb_free_all_rx_resources(adapter);
602 adapter->num_rx_queues = 1;
603 igb_alloc_queues(adapter);
844290e5 604 } else {
2d064c06
AD		 605 switch (hw->mac.type) {
606 case e1000_82575:
607 wr32(E1000_MSIXBM(0),
608 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
609 break;
610 case e1000_82576:
611 wr32(E1000_IVAR0, E1000_IVAR_VALID);
612 break;
613 default:
614 break;
615 }
9d5c8243 616 }
844290e5 617
7dfc16fa 618 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 619 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
620 netdev->name, netdev);
621 if (!err)
622 goto request_done;
623 /* fall back to legacy interrupts */
624 igb_reset_interrupt_capability(adapter);
7dfc16fa 625 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 626 }
627
628 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
629 netdev->name, netdev);
630
6cb5e577 631 if (err)
9d5c8243
AK		 632 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
633 err);
9d5c8243
AK		 634
635request_done:
636 return err;
637}
638
639static void igb_free_irq(struct igb_adapter *adapter)
640{
641 struct net_device *netdev = adapter->netdev;
642
643 if (adapter->msix_entries) {
644 int vector = 0, i;
645
646 for (i = 0; i < adapter->num_tx_queues; i++)
647 free_irq(adapter->msix_entries[vector++].vector,
648 &(adapter->tx_ring[i]));
649 for (i = 0; i < adapter->num_rx_queues; i++)
650 free_irq(adapter->msix_entries[vector++].vector,
651 &(adapter->rx_ring[i]));
652
653 free_irq(adapter->msix_entries[vector++].vector, netdev);
654 return;
655 }
656
657 free_irq(adapter->pdev->irq, netdev);
658}
659
660/**
661 * igb_irq_disable - Mask off interrupt generation on the NIC
662 * @adapter: board private structure
663 **/
664static void igb_irq_disable(struct igb_adapter *adapter)
665{
666 struct e1000_hw *hw = &adapter->hw;
667
668 if (adapter->msix_entries) {
844290e5 669 wr32(E1000_EIAM, 0);
9d5c8243
AK		 670 wr32(E1000_EIMC, ~0);
671 wr32(E1000_EIAC, 0);
672 }
844290e5
PW		 673
674 wr32(E1000_IAM, 0);
9d5c8243
AK		 675 wr32(E1000_IMC, ~0);
676 wrfl();
677 synchronize_irq(adapter->pdev->irq);
678}
679
680/**
681 * igb_irq_enable - Enable default interrupt generation settings
682 * @adapter: board private structure
683 **/
684static void igb_irq_enable(struct igb_adapter *adapter)
685{
686 struct e1000_hw *hw = &adapter->hw;
687
688 if (adapter->msix_entries) {
844290e5
PW		 689 wr32(E1000_EIAC, adapter->eims_enable_mask);
690 wr32(E1000_EIAM, adapter->eims_enable_mask);
691 wr32(E1000_EIMS, adapter->eims_enable_mask);
dda0e083 692 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5
PW		 693 } else {
694 wr32(E1000_IMS, IMS_ENABLE_MASK);
695 wr32(E1000_IAM, IMS_ENABLE_MASK);
696 }
9d5c8243
AK		 697}
698
699static void igb_update_mng_vlan(struct igb_adapter *adapter)
700{
701 struct net_device *netdev = adapter->netdev;
702 u16 vid = adapter->hw.mng_cookie.vlan_id;
703 u16 old_vid = adapter->mng_vlan_id;
704 if (adapter->vlgrp) {
705 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
706 if (adapter->hw.mng_cookie.status &
707 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
708 igb_vlan_rx_add_vid(netdev, vid);
709 adapter->mng_vlan_id = vid;
710 } else
711 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
712
713 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
714 (vid != old_vid) &&
715 !vlan_group_get_device(adapter->vlgrp, old_vid))
716 igb_vlan_rx_kill_vid(netdev, old_vid);
717 } else
718 adapter->mng_vlan_id = vid;
719 }
720}
721
722/**
723 * igb_release_hw_control - release control of the h/w to f/w
724 * @adapter: address of board private structure
725 *
726 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
727 * For ASF and Pass Through versions of f/w this means that the
728 * driver is no longer loaded.
729 *
730 **/
731static void igb_release_hw_control(struct igb_adapter *adapter)
732{
733 struct e1000_hw *hw = &adapter->hw;
734 u32 ctrl_ext;
735
736 /* Let firmware take over control of h/w */
737 ctrl_ext = rd32(E1000_CTRL_EXT);
738 wr32(E1000_CTRL_EXT,
739 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
740}
741
742
743/**
744 * igb_get_hw_control - get control of the h/w from f/w
745 * @adapter: address of board private structure
746 *
747 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
748 * For ASF and Pass Through versions of f/w this means that
749 * the driver is loaded.
750 *
751 **/
752static void igb_get_hw_control(struct igb_adapter *adapter)
753{
754 struct e1000_hw *hw = &adapter->hw;
755 u32 ctrl_ext;
756
757 /* Let firmware know the driver has taken over */
758 ctrl_ext = rd32(E1000_CTRL_EXT);
759 wr32(E1000_CTRL_EXT,
760 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
761}
762
9d5c8243
AK		 763/**
764 * igb_configure - configure the hardware for RX and TX
765 * @adapter: private board structure
766 **/
767static void igb_configure(struct igb_adapter *adapter)
768{
769 struct net_device *netdev = adapter->netdev;
770 int i;
771
772 igb_get_hw_control(adapter);
773 igb_set_multi(netdev);
774
775 igb_restore_vlan(adapter);
9d5c8243
AK		 776
777 igb_configure_tx(adapter);
778 igb_setup_rctl(adapter);
779 igb_configure_rx(adapter);
662d7205
AD		 780
781 igb_rx_fifo_flush_82575(&adapter->hw);
782
9d5c8243
AK		 783 /* call IGB_DESC_UNUSED which always leaves
784 * at least 1 descriptor unused to make sure
785 * next_to_use != next_to_clean */
786 for (i = 0; i < adapter->num_rx_queues; i++) {
787 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 788 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 789 }
790
791
792 adapter->tx_queue_len = netdev->tx_queue_len;
793}
794
795
796/**
797 * igb_up - Open the interface and prepare it to handle traffic
798 * @adapter: board private structure
799 **/
800
801int igb_up(struct igb_adapter *adapter)
802{
803 struct e1000_hw *hw = &adapter->hw;
804 int i;
805
806 /* hardware has been reset, we need to reload some things */
807 igb_configure(adapter);
808
809 clear_bit(__IGB_DOWN, &adapter->state);
810
844290e5
PW		 811 for (i = 0; i < adapter->num_rx_queues; i++)
812 napi_enable(&adapter->rx_ring[i].napi);
813 if (adapter->msix_entries)
9d5c8243 814 igb_configure_msix(adapter);
9d5c8243
AK		 815
816 /* Clear any pending interrupts. */
817 rd32(E1000_ICR);
818 igb_irq_enable(adapter);
819
820 /* Fire a link change interrupt to start the watchdog. */
821 wr32(E1000_ICS, E1000_ICS_LSC);
822 return 0;
823}
824
825void igb_down(struct igb_adapter *adapter)
826{
827 struct e1000_hw *hw = &adapter->hw;
828 struct net_device *netdev = adapter->netdev;
829 u32 tctl, rctl;
830 int i;
831
832 /* signal that we're down so the interrupt handler does not
833 * reschedule our watchdog timer */
834 set_bit(__IGB_DOWN, &adapter->state);
835
836 /* disable receives in the hardware */
837 rctl = rd32(E1000_RCTL);
838 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
839 /* flush and sleep below */
840
fd2ea0a7 841 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 842
843 /* disable transmits in the hardware */
844 tctl = rd32(E1000_TCTL);
845 tctl &= ~E1000_TCTL_EN;
846 wr32(E1000_TCTL, tctl);
847 /* flush both disables and wait for them to finish */
848 wrfl();
849 msleep(10);
850
844290e5
PW		 851 for (i = 0; i < adapter->num_rx_queues; i++)
852 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 853
9d5c8243
AK		 854 igb_irq_disable(adapter);
855
856 del_timer_sync(&adapter->watchdog_timer);
857 del_timer_sync(&adapter->phy_info_timer);
858
859 netdev->tx_queue_len = adapter->tx_queue_len;
860 netif_carrier_off(netdev);
861 adapter->link_speed = 0;
862 adapter->link_duplex = 0;
863
3023682e
JK		 864 if (!pci_channel_offline(adapter->pdev))
865 igb_reset(adapter);
9d5c8243
AK		 866 igb_clean_all_tx_rings(adapter);
867 igb_clean_all_rx_rings(adapter);
868}
869
870void igb_reinit_locked(struct igb_adapter *adapter)
871{
872 WARN_ON(in_interrupt());
873 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
874 msleep(1);
875 igb_down(adapter);
876 igb_up(adapter);
877 clear_bit(__IGB_RESETTING, &adapter->state);
878}
879
880void igb_reset(struct igb_adapter *adapter)
881{
882 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 883 struct e1000_mac_info *mac = &hw->mac;
884 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 885 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
886 u16 hwm;
887
888 /* Repartition Pba for greater than 9k mtu
889 * To take effect CTRL.RST is required.
890 */
2d064c06 891 if (mac->type != e1000_82576) {
9d5c8243 892 pba = E1000_PBA_34K;
2d064c06
AD		 893 }
894 else {
895 pba = E1000_PBA_64K;
896 }
9d5c8243 897
2d064c06
AD		 898 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
899 (mac->type < e1000_82576)) {
9d5c8243
AK		 900 /* adjust PBA for jumbo frames */
901 wr32(E1000_PBA, pba);
902
903 /* To maintain wire speed transmits, the Tx FIFO should be
904 * large enough to accommodate two full transmit packets,
905 * rounded up to the next 1KB and expressed in KB. Likewise,
906 * the Rx FIFO should be large enough to accommodate at least
907 * one full receive packet and is similarly rounded up and
908 * expressed in KB. */
909 pba = rd32(E1000_PBA);
910 /* upper 16 bits has Tx packet buffer allocation size in KB */
911 tx_space = pba >> 16;
912 /* lower 16 bits has Rx packet buffer allocation size in KB */
913 pba &= 0xffff;
914 /* the tx fifo also stores 16 bytes of information about the tx
915 * but don't include ethernet FCS because hardware appends it */
916 min_tx_space = (adapter->max_frame_size +
917 sizeof(struct e1000_tx_desc) -
918 ETH_FCS_LEN) * 2;
919 min_tx_space = ALIGN(min_tx_space, 1024);
920 min_tx_space >>= 10;
921 /* software strips receive CRC, so leave room for it */
922 min_rx_space = adapter->max_frame_size;
923 min_rx_space = ALIGN(min_rx_space, 1024);
924 min_rx_space >>= 10;
925
926 /* If current Tx allocation is less than the min Tx FIFO size,
927 * and the min Tx FIFO size is less than the current Rx FIFO
928 * allocation, take space away from current Rx allocation */
929 if (tx_space < min_tx_space &&
930 ((min_tx_space - tx_space) < pba)) {
931 pba = pba - (min_tx_space - tx_space);
932
933 /* if short on rx space, rx wins and must trump tx
934 * adjustment */
935 if (pba < min_rx_space)
936 pba = min_rx_space;
937 }
2d064c06 938 wr32(E1000_PBA, pba);
9d5c8243 939 }
9d5c8243
AK		 940
941 /* flow control settings */
942 /* The high water mark must be low enough to fit one full frame
943 * (or the size used for early receive) above it in the Rx FIFO.
944 * Set it to the lower of:
945 * - 90% of the Rx FIFO size, or
946 * - the full Rx FIFO size minus one full frame */
947 hwm = min(((pba << 10) * 9 / 10),
2d064c06 948 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 949
2d064c06
AD		 950 if (mac->type < e1000_82576) {
951 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
952 fc->low_water = fc->high_water - 8;
953 } else {
954 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
955 fc->low_water = fc->high_water - 16;
956 }
9d5c8243
AK		 957 fc->pause_time = 0xFFFF;
958 fc->send_xon = 1;
959 fc->type = fc->original_type;
960
961 /* Allow time for pending master requests to run */
962 adapter->hw.mac.ops.reset_hw(&adapter->hw);
963 wr32(E1000_WUC, 0);
964
965 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
966 dev_err(&adapter->pdev->dev, "Hardware Error\n");
967
968 igb_update_mng_vlan(adapter);
969
970 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
971 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
972
973 igb_reset_adaptive(&adapter->hw);
f5f4cf08 974 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 975}
976
2e5c6922
SH		 977static const struct net_device_ops igb_netdev_ops = {
978 .ndo_open = igb_open,
979 .ndo_stop = igb_close,
00829823 980 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 981 .ndo_get_stats = igb_get_stats,
982 .ndo_set_multicast_list = igb_set_multi,
983 .ndo_set_mac_address = igb_set_mac,
984 .ndo_change_mtu = igb_change_mtu,
985 .ndo_do_ioctl = igb_ioctl,
986 .ndo_tx_timeout = igb_tx_timeout,
987 .ndo_validate_addr = eth_validate_addr,
988 .ndo_vlan_rx_register = igb_vlan_rx_register,
989 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
990 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
991#ifdef CONFIG_NET_POLL_CONTROLLER
992 .ndo_poll_controller = igb_netpoll,
993#endif
994};
995
9d5c8243
AK		 996/**
997 * igb_probe - Device Initialization Routine
998 * @pdev: PCI device information struct
999 * @ent: entry in igb_pci_tbl
1000 *
1001 * Returns 0 on success, negative on failure
1002 *
1003 * igb_probe initializes an adapter identified by a pci_dev structure.
1004 * The OS initialization, configuring of the adapter private structure,
1005 * and a hardware reset occur.
1006 **/
1007static int __devinit igb_probe(struct pci_dev *pdev,
1008 const struct pci_device_id *ent)
1009{
1010 struct net_device *netdev;
1011 struct igb_adapter *adapter;
1012 struct e1000_hw *hw;
c54106bb 1013 struct pci_dev *us_dev;
9d5c8243
AK		 1014 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1015 unsigned long mmio_start, mmio_len;
c54106bb
AD		 1016 int i, err, pci_using_dac, pos;
1017 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 1018 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1019 u32 part_num;
1020
aed5dec3 1021 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1022 if (err)
1023 return err;
1024
1025 pci_using_dac = 0;
1026 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1027 if (!err) {
1028 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1029 if (!err)
1030 pci_using_dac = 1;
1031 } else {
1032 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1033 if (err) {
1034 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1035 if (err) {
1036 dev_err(&pdev->dev, "No usable DMA "
1037 "configuration, aborting\n");
1038 goto err_dma;
1039 }
1040 }
1041 }
1042
c54106bb
AD		 1043 /* 82575 requires that the pci-e link partner disable the L0s state */
1044 switch (pdev->device) {
1045 case E1000_DEV_ID_82575EB_COPPER:
1046 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1047 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1048 us_dev = pdev->bus->self;
1049 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1050 if (pos) {
1051 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1052 &state);
1053 state &= ~PCIE_LINK_STATE_L0S;
1054 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1055 state);
ac450208
BH		 1056 dev_info(&pdev->dev,
1057 "Disabling ASPM L0s upstream switch port %s\n",
1058 pci_name(us_dev));
c54106bb
AD		 1059 }
1060 default:
1061 break;
1062 }
1063
aed5dec3
AD		 1064 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1065 IORESOURCE_MEM),
1066 igb_driver_name);
9d5c8243
AK		 1067 if (err)
1068 goto err_pci_reg;
1069
ea943d41
JK		 1070 err = pci_enable_pcie_error_reporting(pdev);
1071 if (err) {
1072 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1073 "0x%x\n", err);
1074 /* non-fatal, continue */
1075 }
40a914fa 1076
9d5c8243 1077 pci_set_master(pdev);
c682fc23 1078 pci_save_state(pdev);
9d5c8243
AK		 1079
1080 err = -ENOMEM;
661086df 1081 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1082 if (!netdev)
1083 goto err_alloc_etherdev;
1084
1085 SET_NETDEV_DEV(netdev, &pdev->dev);
1086
1087 pci_set_drvdata(pdev, netdev);
1088 adapter = netdev_priv(netdev);
1089 adapter->netdev = netdev;
1090 adapter->pdev = pdev;
1091 hw = &adapter->hw;
1092 hw->back = adapter;
1093 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1094
1095 mmio_start = pci_resource_start(pdev, 0);
1096 mmio_len = pci_resource_len(pdev, 0);
1097
1098 err = -EIO;
1099 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1100 if (!adapter->hw.hw_addr)
1101 goto err_ioremap;
1102
2e5c6922 1103 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1104 igb_set_ethtool_ops(netdev);
9d5c8243 1105 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1106
1107 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1108
1109 netdev->mem_start = mmio_start;
1110 netdev->mem_end = mmio_start + mmio_len;
1111
9d5c8243
AK		 1112 /* PCI config space info */
1113 hw->vendor_id = pdev->vendor;
1114 hw->device_id = pdev->device;
1115 hw->revision_id = pdev->revision;
1116 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1117 hw->subsystem_device_id = pdev->subsystem_device;
1118
1119 /* setup the private structure */
1120 hw->back = adapter;
1121 /* Copy the default MAC, PHY and NVM function pointers */
1122 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1123 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1124 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1125 /* Initialize skew-specific constants */
1126 err = ei->get_invariants(hw);
1127 if (err)
1128 goto err_hw_init;
1129
1130 err = igb_sw_init(adapter);
1131 if (err)
1132 goto err_sw_init;
1133
1134 igb_get_bus_info_pcie(hw);
1135
7dfc16fa
AD		 1136 /* set flags */
1137 switch (hw->mac.type) {
7dfc16fa 1138 case e1000_82575:
7dfc16fa
AD		 1139 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1140 break;
bbd98fe4 1141 case e1000_82576:
7dfc16fa
AD		 1142 default:
1143 break;
1144 }
1145
9d5c8243
AK		 1146 hw->phy.autoneg_wait_to_complete = false;
1147 hw->mac.adaptive_ifs = true;
1148
1149 /* Copper options */
1150 if (hw->phy.media_type == e1000_media_type_copper) {
1151 hw->phy.mdix = AUTO_ALL_MODES;
1152 hw->phy.disable_polarity_correction = false;
1153 hw->phy.ms_type = e1000_ms_hw_default;
1154 }
1155
1156 if (igb_check_reset_block(hw))
1157 dev_info(&pdev->dev,
1158 "PHY reset is blocked due to SOL/IDER session.\n");
1159
1160 netdev->features = NETIF_F_SG |
7d8eb29e 1161 NETIF_F_IP_CSUM |
9d5c8243
AK		 1162 NETIF_F_HW_VLAN_TX |
1163 NETIF_F_HW_VLAN_RX |
1164 NETIF_F_HW_VLAN_FILTER;
1165
7d8eb29e 1166 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1167 netdev->features |= NETIF_F_TSO;
9d5c8243 1168 netdev->features |= NETIF_F_TSO6;
48f29ffc 1169
d3352520 1170#ifdef CONFIG_IGB_LRO
5c0999b7 1171 netdev->features |= NETIF_F_GRO;
d3352520
AD		 1172#endif
1173
48f29ffc
JK		 1174 netdev->vlan_features |= NETIF_F_TSO;
1175 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1176 netdev->vlan_features |= NETIF_F_IP_CSUM;
48f29ffc
JK		 1177 netdev->vlan_features |= NETIF_F_SG;
1178
9d5c8243
AK		 1179 if (pci_using_dac)
1180 netdev->features |= NETIF_F_HIGHDMA;
1181
9d5c8243
AK		 1182 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1183
1184 /* before reading the NVM, reset the controller to put the device in a
1185 * known good starting state */
1186 hw->mac.ops.reset_hw(hw);
1187
1188 /* make sure the NVM is good */
1189 if (igb_validate_nvm_checksum(hw) < 0) {
1190 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1191 err = -EIO;
1192 goto err_eeprom;
1193 }
1194
1195 /* copy the MAC address out of the NVM */
1196 if (hw->mac.ops.read_mac_addr(hw))
1197 dev_err(&pdev->dev, "NVM Read Error\n");
1198
1199 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1200 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1201
1202 if (!is_valid_ether_addr(netdev->perm_addr)) {
1203 dev_err(&pdev->dev, "Invalid MAC Address\n");
1204 err = -EIO;
1205 goto err_eeprom;
1206 }
1207
1208 init_timer(&adapter->watchdog_timer);
1209 adapter->watchdog_timer.function = &igb_watchdog;
1210 adapter->watchdog_timer.data = (unsigned long) adapter;
1211
1212 init_timer(&adapter->phy_info_timer);
1213 adapter->phy_info_timer.function = &igb_update_phy_info;
1214 adapter->phy_info_timer.data = (unsigned long) adapter;
1215
1216 INIT_WORK(&adapter->reset_task, igb_reset_task);
1217 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1218
1219 /* Initialize link & ring properties that are user-changeable */
1220 adapter->tx_ring->count = 256;
1221 for (i = 0; i < adapter->num_tx_queues; i++)
1222 adapter->tx_ring[i].count = adapter->tx_ring->count;
1223 adapter->rx_ring->count = 256;
1224 for (i = 0; i < adapter->num_rx_queues; i++)
1225 adapter->rx_ring[i].count = adapter->rx_ring->count;
1226
1227 adapter->fc_autoneg = true;
1228 hw->mac.autoneg = true;
1229 hw->phy.autoneg_advertised = 0x2f;
1230
1231 hw->fc.original_type = e1000_fc_default;
1232 hw->fc.type = e1000_fc_default;
1233
1234 adapter->itr_setting = 3;
1235 adapter->itr = IGB_START_ITR;
1236
1237 igb_validate_mdi_setting(hw);
1238
1239 adapter->rx_csum = 1;
1240
1241 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1242 * enable the ACPI Magic Packet filter
1243 */
1244
1245 if (hw->bus.func == 0 ||
1246 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
312c75ae 1247 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
9d5c8243
AK		 1248
1249 if (eeprom_data & eeprom_apme_mask)
1250 adapter->eeprom_wol |= E1000_WUFC_MAG;
1251
1252 /* now that we have the eeprom settings, apply the special cases where
1253 * the eeprom may be wrong or the board simply won't support wake on
1254 * lan on a particular port */
1255 switch (pdev->device) {
1256 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1257 adapter->eeprom_wol = 0;
1258 break;
1259 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1260 case E1000_DEV_ID_82576_FIBER:
1261 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1262 /* Wake events only supported on port A for dual fiber
1263 * regardless of eeprom setting */
1264 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1265 adapter->eeprom_wol = 0;
1266 break;
1267 }
1268
1269 /* initialize the wol settings based on the eeprom settings */
1270 adapter->wol = adapter->eeprom_wol;
e1b86d84 1271 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1272
1273 /* reset the hardware with the new settings */
1274 igb_reset(adapter);
1275
1276 /* let the f/w know that the h/w is now under the control of the
1277 * driver. */
1278 igb_get_hw_control(adapter);
1279
1280 /* tell the stack to leave us alone until igb_open() is called */
1281 netif_carrier_off(netdev);
fd2ea0a7 1282 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1283
1284 strcpy(netdev->name, "eth%d");
1285 err = register_netdev(netdev);
1286 if (err)
1287 goto err_register;
1288
421e02f0 1289#ifdef CONFIG_IGB_DCA
bbd98fe4 1290 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1291 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1292 dev_info(&pdev->dev, "DCA enabled\n");
1293 /* Always use CB2 mode, difference is masked
1294 * in the CB driver. */
1295 wr32(E1000_DCA_CTRL, 2);
1296 igb_setup_dca(adapter);
1297 }
1298#endif
1299
9d5c8243
AK		 1300 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1301 /* print bus type/speed/width info */
7c510e4b 1302 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1303 netdev->name,
1304 ((hw->bus.speed == e1000_bus_speed_2500)
1305 ? "2.5Gb/s" : "unknown"),
1306 ((hw->bus.width == e1000_bus_width_pcie_x4)
1307 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1308 ? "Width x1" : "unknown"),
7c510e4b 1309 netdev->dev_addr);
9d5c8243
AK		 1310
1311 igb_read_part_num(hw, &part_num);
1312 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1313 (part_num >> 8), (part_num & 0xff));
1314
1315 dev_info(&pdev->dev,
1316 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1317 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1318 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1319 adapter->num_rx_queues, adapter->num_tx_queues);
1320
9d5c8243
AK		 1321 return 0;
1322
1323err_register:
1324 igb_release_hw_control(adapter);
1325err_eeprom:
1326 if (!igb_check_reset_block(hw))
f5f4cf08 1327 igb_reset_phy(hw);
9d5c8243
AK		 1328
1329 if (hw->flash_address)
1330 iounmap(hw->flash_address);
1331
a88f10ec 1332 igb_free_queues(adapter);
9d5c8243
AK		 1333err_sw_init:
1334err_hw_init:
1335 iounmap(hw->hw_addr);
1336err_ioremap:
1337 free_netdev(netdev);
1338err_alloc_etherdev:
aed5dec3
AD		 1339 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1340 IORESOURCE_MEM));
9d5c8243
AK		 1341err_pci_reg:
1342err_dma:
1343 pci_disable_device(pdev);
1344 return err;
1345}
1346
1347/**
1348 * igb_remove - Device Removal Routine
1349 * @pdev: PCI device information struct
1350 *
1351 * igb_remove is called by the PCI subsystem to alert the driver
1352 * that it should release a PCI device. The could be caused by a
1353 * Hot-Plug event, or because the driver is going to be removed from
1354 * memory.
1355 **/
1356static void __devexit igb_remove(struct pci_dev *pdev)
1357{
1358 struct net_device *netdev = pci_get_drvdata(pdev);
1359 struct igb_adapter *adapter = netdev_priv(netdev);
421e02f0 1360#ifdef CONFIG_IGB_DCA
fe4506b6 1361 struct e1000_hw *hw = &adapter->hw;
9280fa52 1362#endif
ea943d41 1363 int err;
9d5c8243
AK		 1364
1365 /* flush_scheduled work may reschedule our watchdog task, so
1366 * explicitly disable watchdog tasks from being rescheduled */
1367 set_bit(__IGB_DOWN, &adapter->state);
1368 del_timer_sync(&adapter->watchdog_timer);
1369 del_timer_sync(&adapter->phy_info_timer);
1370
1371 flush_scheduled_work();
1372
421e02f0 1373#ifdef CONFIG_IGB_DCA
7dfc16fa 1374 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1375 dev_info(&pdev->dev, "DCA disabled\n");
1376 dca_remove_requester(&pdev->dev);
7dfc16fa 1377 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1378 wr32(E1000_DCA_CTRL, 1);
1379 }
1380#endif
1381
9d5c8243
AK		 1382 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1383 * would have already happened in close and is redundant. */
1384 igb_release_hw_control(adapter);
1385
1386 unregister_netdev(netdev);
1387
f5f4cf08
AD		 1388 if (!igb_check_reset_block(&adapter->hw))
1389 igb_reset_phy(&adapter->hw);
9d5c8243 1390
9d5c8243
AK		 1391 igb_reset_interrupt_capability(adapter);
1392
a88f10ec 1393 igb_free_queues(adapter);
9d5c8243
AK		 1394
1395 iounmap(adapter->hw.hw_addr);
1396 if (adapter->hw.flash_address)
1397 iounmap(adapter->hw.flash_address);
aed5dec3
AD		 1398 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1399 IORESOURCE_MEM));
9d5c8243
AK		 1400
1401 free_netdev(netdev);
1402
ea943d41
JK		 1403 err = pci_disable_pcie_error_reporting(pdev);
1404 if (err)
1405 dev_err(&pdev->dev,
1406 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1407
9d5c8243
AK		 1408 pci_disable_device(pdev);
1409}
1410
1411/**
1412 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1413 * @adapter: board private structure to initialize
1414 *
1415 * igb_sw_init initializes the Adapter private data structure.
1416 * Fields are initialized based on PCI device information and
1417 * OS network device settings (MTU size).
1418 **/
1419static int __devinit igb_sw_init(struct igb_adapter *adapter)
1420{
1421 struct e1000_hw *hw = &adapter->hw;
1422 struct net_device *netdev = adapter->netdev;
1423 struct pci_dev *pdev = adapter->pdev;
1424
1425 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1426
68fd9910
AD		 1427 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1428 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1429 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1430 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1431 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1432 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1433
661086df
PWJ		 1434 /* This call may decrease the number of queues depending on
1435 * interrupt mode. */
9d5c8243
AK		 1436 igb_set_interrupt_capability(adapter);
1437
1438 if (igb_alloc_queues(adapter)) {
1439 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1440 return -ENOMEM;
1441 }
1442
1443 /* Explicitly disable IRQ since the NIC can be in any state. */
1444 igb_irq_disable(adapter);
1445
1446 set_bit(__IGB_DOWN, &adapter->state);
1447 return 0;
1448}
1449
1450/**
1451 * igb_open - Called when a network interface is made active
1452 * @netdev: network interface device structure
1453 *
1454 * Returns 0 on success, negative value on failure
1455 *
1456 * The open entry point is called when a network interface is made
1457 * active by the system (IFF_UP). At this point all resources needed
1458 * for transmit and receive operations are allocated, the interrupt
1459 * handler is registered with the OS, the watchdog timer is started,
1460 * and the stack is notified that the interface is ready.
1461 **/
1462static int igb_open(struct net_device *netdev)
1463{
1464 struct igb_adapter *adapter = netdev_priv(netdev);
1465 struct e1000_hw *hw = &adapter->hw;
1466 int err;
1467 int i;
1468
1469 /* disallow open during test */
1470 if (test_bit(__IGB_TESTING, &adapter->state))
1471 return -EBUSY;
1472
1473 /* allocate transmit descriptors */
1474 err = igb_setup_all_tx_resources(adapter);
1475 if (err)
1476 goto err_setup_tx;
1477
1478 /* allocate receive descriptors */
1479 err = igb_setup_all_rx_resources(adapter);
1480 if (err)
1481 goto err_setup_rx;
1482
1483 /* e1000_power_up_phy(adapter); */
1484
1485 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1486 if ((adapter->hw.mng_cookie.status &
1487 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1488 igb_update_mng_vlan(adapter);
1489
1490 /* before we allocate an interrupt, we must be ready to handle it.
1491 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1492 * as soon as we call pci_request_irq, so we have to setup our
1493 * clean_rx handler before we do so. */
1494 igb_configure(adapter);
1495
1496 err = igb_request_irq(adapter);
1497 if (err)
1498 goto err_req_irq;
1499
1500 /* From here on the code is the same as igb_up() */
1501 clear_bit(__IGB_DOWN, &adapter->state);
1502
844290e5
PW		 1503 for (i = 0; i < adapter->num_rx_queues; i++)
1504 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1505
1506 /* Clear any pending interrupts. */
1507 rd32(E1000_ICR);
844290e5
PW		 1508
1509 igb_irq_enable(adapter);
1510
d55b53ff
JK		 1511 netif_tx_start_all_queues(netdev);
1512
9d5c8243
AK		 1513 /* Fire a link status change interrupt to start the watchdog. */
1514 wr32(E1000_ICS, E1000_ICS_LSC);
1515
1516 return 0;
1517
1518err_req_irq:
1519 igb_release_hw_control(adapter);
1520 /* e1000_power_down_phy(adapter); */
1521 igb_free_all_rx_resources(adapter);
1522err_setup_rx:
1523 igb_free_all_tx_resources(adapter);
1524err_setup_tx:
1525 igb_reset(adapter);
1526
1527 return err;
1528}
1529
1530/**
1531 * igb_close - Disables a network interface
1532 * @netdev: network interface device structure
1533 *
1534 * Returns 0, this is not allowed to fail
1535 *
1536 * The close entry point is called when an interface is de-activated
1537 * by the OS. The hardware is still under the driver's control, but
1538 * needs to be disabled. A global MAC reset is issued to stop the
1539 * hardware, and all transmit and receive resources are freed.
1540 **/
1541static int igb_close(struct net_device *netdev)
1542{
1543 struct igb_adapter *adapter = netdev_priv(netdev);
1544
1545 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1546 igb_down(adapter);
1547
1548 igb_free_irq(adapter);
1549
1550 igb_free_all_tx_resources(adapter);
1551 igb_free_all_rx_resources(adapter);
1552
1553 /* kill manageability vlan ID if supported, but not if a vlan with
1554 * the same ID is registered on the host OS (let 8021q kill it) */
1555 if ((adapter->hw.mng_cookie.status &
1556 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1557 !(adapter->vlgrp &&
1558 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1559 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1560
1561 return 0;
1562}
1563
1564/**
1565 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1566 * @adapter: board private structure
1567 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1568 *
1569 * Return 0 on success, negative on failure
1570 **/
1571
1572int igb_setup_tx_resources(struct igb_adapter *adapter,
1573 struct igb_ring *tx_ring)
1574{
1575 struct pci_dev *pdev = adapter->pdev;
1576 int size;
1577
1578 size = sizeof(struct igb_buffer) * tx_ring->count;
1579 tx_ring->buffer_info = vmalloc(size);
1580 if (!tx_ring->buffer_info)
1581 goto err;
1582 memset(tx_ring->buffer_info, 0, size);
1583
1584 /* round up to nearest 4K */
0e014cb1 1585 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
9d5c8243
AK		 1586 tx_ring->size = ALIGN(tx_ring->size, 4096);
1587
1588 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1589 &tx_ring->dma);
1590
1591 if (!tx_ring->desc)
1592 goto err;
1593
1594 tx_ring->adapter = adapter;
1595 tx_ring->next_to_use = 0;
1596 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1597 return 0;
1598
1599err:
1600 vfree(tx_ring->buffer_info);
1601 dev_err(&adapter->pdev->dev,
1602 "Unable to allocate memory for the transmit descriptor ring\n");
1603 return -ENOMEM;
1604}
1605
1606/**
1607 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1608 * (Descriptors) for all queues
1609 * @adapter: board private structure
1610 *
1611 * Return 0 on success, negative on failure
1612 **/
1613static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1614{
1615 int i, err = 0;
661086df 1616 int r_idx;
9d5c8243
AK		 1617
1618 for (i = 0; i < adapter->num_tx_queues; i++) {
1619 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1620 if (err) {
1621 dev_err(&adapter->pdev->dev,
1622 "Allocation for Tx Queue %u failed\n", i);
1623 for (i--; i >= 0; i--)
3b644cf6 1624 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1625 break;
1626 }
1627 }
1628
661086df
PWJ		 1629 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1630 r_idx = i % adapter->num_tx_queues;
1631 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1632 }
9d5c8243
AK		 1633 return err;
1634}
1635
1636/**
1637 * igb_configure_tx - Configure transmit Unit after Reset
1638 * @adapter: board private structure
1639 *
1640 * Configure the Tx unit of the MAC after a reset.
1641 **/
1642static void igb_configure_tx(struct igb_adapter *adapter)
1643{
0e014cb1 1644 u64 tdba;
9d5c8243
AK		 1645 struct e1000_hw *hw = &adapter->hw;
1646 u32 tctl;
1647 u32 txdctl, txctrl;
26bc19ec 1648 int i, j;
9d5c8243
AK		 1649
1650 for (i = 0; i < adapter->num_tx_queues; i++) {
1651 struct igb_ring *ring = &(adapter->tx_ring[i]);
26bc19ec
AD		 1652 j = ring->reg_idx;
1653 wr32(E1000_TDLEN(j),
9d5c8243
AK		 1654 ring->count * sizeof(struct e1000_tx_desc));
1655 tdba = ring->dma;
26bc19ec 1656 wr32(E1000_TDBAL(j),
9d5c8243 1657 tdba & 0x00000000ffffffffULL);
26bc19ec 1658 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1659
26bc19ec
AD		 1660 ring->head = E1000_TDH(j);
1661 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1662 writel(0, hw->hw_addr + ring->tail);
1663 writel(0, hw->hw_addr + ring->head);
26bc19ec 1664 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1665 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1666 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1667
1668 /* Turn off Relaxed Ordering on head write-backs. The
1669 * writebacks MUST be delivered in order or it will
1670 * completely screw up our bookeeping.
1671 */
26bc19ec 1672 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1673 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1674 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1675 }
1676
1677
1678
1679 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1680
1681 /* Program the Transmit Control Register */
1682
1683 tctl = rd32(E1000_TCTL);
1684 tctl &= ~E1000_TCTL_CT;
1685 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1686 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1687
1688 igb_config_collision_dist(hw);
1689
1690 /* Setup Transmit Descriptor Settings for eop descriptor */
1691 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1692
1693 /* Enable transmits */
1694 tctl |= E1000_TCTL_EN;
1695
1696 wr32(E1000_TCTL, tctl);
1697}
1698
1699/**
1700 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1701 * @adapter: board private structure
1702 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1703 *
1704 * Returns 0 on success, negative on failure
1705 **/
1706
1707int igb_setup_rx_resources(struct igb_adapter *adapter,
1708 struct igb_ring *rx_ring)
1709{
1710 struct pci_dev *pdev = adapter->pdev;
1711 int size, desc_len;
1712
1713 size = sizeof(struct igb_buffer) * rx_ring->count;
1714 rx_ring->buffer_info = vmalloc(size);
1715 if (!rx_ring->buffer_info)
1716 goto err;
1717 memset(rx_ring->buffer_info, 0, size);
1718
1719 desc_len = sizeof(union e1000_adv_rx_desc);
1720
1721 /* Round up to nearest 4K */
1722 rx_ring->size = rx_ring->count * desc_len;
1723 rx_ring->size = ALIGN(rx_ring->size, 4096);
1724
1725 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1726 &rx_ring->dma);
1727
1728 if (!rx_ring->desc)
1729 goto err;
1730
1731 rx_ring->next_to_clean = 0;
1732 rx_ring->next_to_use = 0;
9d5c8243
AK		 1733
1734 rx_ring->adapter = adapter;
9d5c8243
AK		 1735
1736 return 0;
1737
1738err:
1739 vfree(rx_ring->buffer_info);
1740 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1741 "the receive descriptor ring\n");
1742 return -ENOMEM;
1743}
1744
1745/**
1746 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1747 * (Descriptors) for all queues
1748 * @adapter: board private structure
1749 *
1750 * Return 0 on success, negative on failure
1751 **/
1752static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1753{
1754 int i, err = 0;
1755
1756 for (i = 0; i < adapter->num_rx_queues; i++) {
1757 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1758 if (err) {
1759 dev_err(&adapter->pdev->dev,
1760 "Allocation for Rx Queue %u failed\n", i);
1761 for (i--; i >= 0; i--)
3b644cf6 1762 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1763 break;
1764 }
1765 }
1766
1767 return err;
1768}
1769
1770/**
1771 * igb_setup_rctl - configure the receive control registers
1772 * @adapter: Board private structure
1773 **/
1774static void igb_setup_rctl(struct igb_adapter *adapter)
1775{
1776 struct e1000_hw *hw = &adapter->hw;
1777 u32 rctl;
1778 u32 srrctl = 0;
26bc19ec 1779 int i, j;
9d5c8243
AK		 1780
1781 rctl = rd32(E1000_RCTL);
1782
1783 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1784 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1785
69d728ba 1786 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
9d5c8243
AK		 1787 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1788
87cb7e8c
AK		 1789 /*
1790 * enable stripping of CRC. It's unlikely this will break BMC
1791 * redirection as it did with e1000. Newer features require
1792 * that the HW strips the CRC.
9d5c8243 1793 */
87cb7e8c 1794 rctl |= E1000_RCTL_SECRC;
9d5c8243 1795
9b07f3d3 1796 /*
ec54d7d6 1797 * disable store bad packets and clear size bits.
9b07f3d3 1798 */
ec54d7d6 1799 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 1800
ec54d7d6 1801 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 1802 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 1803
1804 /* Setup buffer sizes */
1805 switch (adapter->rx_buffer_len) {
1806 case IGB_RXBUFFER_256:
1807 rctl |= E1000_RCTL_SZ_256;
1808 break;
1809 case IGB_RXBUFFER_512:
1810 rctl |= E1000_RCTL_SZ_512;
1811 break;
1812 default:
1813 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
1814 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1815 break;
9d5c8243
AK		 1816 }
1817
1818 /* 82575 and greater support packet-split where the protocol
1819 * header is placed in skb->data and the packet data is
1820 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1821 * In the case of a non-split, skb->data is linearly filled,
1822 * followed by the page buffers. Therefore, skb->data is
1823 * sized to hold the largest protocol header.
1824 */
1825 /* allocations using alloc_page take too long for regular MTU
1826 * so only enable packet split for jumbo frames */
ec54d7d6 1827 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 1828 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1829 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1830 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1831 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1832 } else {
1833 adapter->rx_ps_hdr_size = 0;
1834 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1835 }
1836
26bc19ec
AD		 1837 for (i = 0; i < adapter->num_rx_queues; i++) {
1838 j = adapter->rx_ring[i].reg_idx;
1839 wr32(E1000_SRRCTL(j), srrctl);
1840 }
9d5c8243
AK		 1841
1842 wr32(E1000_RCTL, rctl);
1843}
1844
1845/**
1846 * igb_configure_rx - Configure receive Unit after Reset
1847 * @adapter: board private structure
1848 *
1849 * Configure the Rx unit of the MAC after a reset.
1850 **/
1851static void igb_configure_rx(struct igb_adapter *adapter)
1852{
1853 u64 rdba;
1854 struct e1000_hw *hw = &adapter->hw;
1855 u32 rctl, rxcsum;
1856 u32 rxdctl;
26bc19ec 1857 int i, j;
9d5c8243
AK		 1858
1859 /* disable receives while setting up the descriptors */
1860 rctl = rd32(E1000_RCTL);
1861 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1862 wrfl();
1863 mdelay(10);
1864
1865 if (adapter->itr_setting > 3)
6eb5a7f1 1866 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1867
1868 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1869 * the Base and Length of the Rx Descriptor Ring */
1870 for (i = 0; i < adapter->num_rx_queues; i++) {
1871 struct igb_ring *ring = &(adapter->rx_ring[i]);
26bc19ec 1872 j = ring->reg_idx;
9d5c8243 1873 rdba = ring->dma;
26bc19ec 1874 wr32(E1000_RDBAL(j),
9d5c8243 1875 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 1876 wr32(E1000_RDBAH(j), rdba >> 32);
1877 wr32(E1000_RDLEN(j),
9d5c8243
AK		 1878 ring->count * sizeof(union e1000_adv_rx_desc));
1879
26bc19ec
AD		 1880 ring->head = E1000_RDH(j);
1881 ring->tail = E1000_RDT(j);
9d5c8243
AK		 1882 writel(0, hw->hw_addr + ring->tail);
1883 writel(0, hw->hw_addr + ring->head);
1884
26bc19ec 1885 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 1886 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1887 rxdctl &= 0xFFF00000;
1888 rxdctl |= IGB_RX_PTHRESH;
1889 rxdctl |= IGB_RX_HTHRESH << 8;
1890 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 1891 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 1892 }
1893
1894 if (adapter->num_rx_queues > 1) {
1895 u32 random[10];
1896 u32 mrqc;
1897 u32 j, shift;
1898 union e1000_reta {
1899 u32 dword;
1900 u8 bytes[4];
1901 } reta;
1902
1903 get_random_bytes(&random[0], 40);
1904
2d064c06
AD		 1905 if (hw->mac.type >= e1000_82576)
1906 shift = 0;
1907 else
1908 shift = 6;
9d5c8243
AK		 1909 for (j = 0; j < (32 * 4); j++) {
1910 reta.bytes[j & 3] =
26bc19ec 1911 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 1912 if ((j & 3) == 3)
1913 writel(reta.dword,
1914 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1915 }
1916 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1917
1918 /* Fill out hash function seeds */
1919 for (j = 0; j < 10; j++)
1920 array_wr32(E1000_RSSRK(0), j, random[j]);
1921
1922 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1923 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1924 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1925 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1926 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1927 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1928 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1929 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1930
1931
1932 wr32(E1000_MRQC, mrqc);
1933
1934 /* Multiqueue and raw packet checksumming are mutually
1935 * exclusive. Note that this not the same as TCP/IP
1936 * checksumming, which works fine. */
1937 rxcsum = rd32(E1000_RXCSUM);
1938 rxcsum |= E1000_RXCSUM_PCSD;
1939 wr32(E1000_RXCSUM, rxcsum);
1940 } else {
1941 /* Enable Receive Checksum Offload for TCP and UDP */
1942 rxcsum = rd32(E1000_RXCSUM);
1943 if (adapter->rx_csum) {
1944 rxcsum |= E1000_RXCSUM_TUOFL;
1945
1946 /* Enable IPv4 payload checksum for UDP fragments
1947 * Must be used in conjunction with packet-split. */
1948 if (adapter->rx_ps_hdr_size)
1949 rxcsum |= E1000_RXCSUM_IPPCSE;
1950 } else {
1951 rxcsum &= ~E1000_RXCSUM_TUOFL;
1952 /* don't need to clear IPPCSE as it defaults to 0 */
1953 }
1954 wr32(E1000_RXCSUM, rxcsum);
1955 }
1956
1957 if (adapter->vlgrp)
1958 wr32(E1000_RLPML,
1959 adapter->max_frame_size + VLAN_TAG_SIZE);
1960 else
1961 wr32(E1000_RLPML, adapter->max_frame_size);
1962
1963 /* Enable Receives */
1964 wr32(E1000_RCTL, rctl);
1965}
1966
1967/**
1968 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 1969 * @tx_ring: Tx descriptor ring for a specific queue
1970 *
1971 * Free all transmit software resources
1972 **/
68fd9910 1973void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1974{
3b644cf6 1975 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1976
3b644cf6 1977 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 1978
1979 vfree(tx_ring->buffer_info);
1980 tx_ring->buffer_info = NULL;
1981
1982 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1983
1984 tx_ring->desc = NULL;
1985}
1986
1987/**
1988 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1989 * @adapter: board private structure
1990 *
1991 * Free all transmit software resources
1992 **/
1993static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1994{
1995 int i;
1996
1997 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 1998 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1999}
2000
2001static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2002 struct igb_buffer *buffer_info)
2003{
2004 if (buffer_info->dma) {
2005 pci_unmap_page(adapter->pdev,
2006 buffer_info->dma,
2007 buffer_info->length,
2008 PCI_DMA_TODEVICE);
2009 buffer_info->dma = 0;
2010 }
2011 if (buffer_info->skb) {
2012 dev_kfree_skb_any(buffer_info->skb);
2013 buffer_info->skb = NULL;
2014 }
2015 buffer_info->time_stamp = 0;
2016 /* buffer_info must be completely set up in the transmit path */
2017}
2018
2019/**
2020 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2021 * @tx_ring: ring to be cleaned
2022 **/
3b644cf6 2023static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2024{
3b644cf6 2025 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2026 struct igb_buffer *buffer_info;
2027 unsigned long size;
2028 unsigned int i;
2029
2030 if (!tx_ring->buffer_info)
2031 return;
2032 /* Free all the Tx ring sk_buffs */
2033
2034 for (i = 0; i < tx_ring->count; i++) {
2035 buffer_info = &tx_ring->buffer_info[i];
2036 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2037 }
2038
2039 size = sizeof(struct igb_buffer) * tx_ring->count;
2040 memset(tx_ring->buffer_info, 0, size);
2041
2042 /* Zero out the descriptor ring */
2043
2044 memset(tx_ring->desc, 0, tx_ring->size);
2045
2046 tx_ring->next_to_use = 0;
2047 tx_ring->next_to_clean = 0;
2048
2049 writel(0, adapter->hw.hw_addr + tx_ring->head);
2050 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2051}
2052
2053/**
2054 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2055 * @adapter: board private structure
2056 **/
2057static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2058{
2059 int i;
2060
2061 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2062 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2063}
2064
2065/**
2066 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2067 * @rx_ring: ring to clean the resources from
2068 *
2069 * Free all receive software resources
2070 **/
68fd9910 2071void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2072{
3b644cf6 2073 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2074
3b644cf6 2075 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2076
2077 vfree(rx_ring->buffer_info);
2078 rx_ring->buffer_info = NULL;
2079
2080 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2081
2082 rx_ring->desc = NULL;
2083}
2084
2085/**
2086 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2087 * @adapter: board private structure
2088 *
2089 * Free all receive software resources
2090 **/
2091static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2092{
2093 int i;
2094
2095 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2096 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2097}
2098
2099/**
2100 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2101 * @rx_ring: ring to free buffers from
2102 **/
3b644cf6 2103static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2104{
3b644cf6 2105 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2106 struct igb_buffer *buffer_info;
2107 struct pci_dev *pdev = adapter->pdev;
2108 unsigned long size;
2109 unsigned int i;
2110
2111 if (!rx_ring->buffer_info)
2112 return;
2113 /* Free all the Rx ring sk_buffs */
2114 for (i = 0; i < rx_ring->count; i++) {
2115 buffer_info = &rx_ring->buffer_info[i];
2116 if (buffer_info->dma) {
2117 if (adapter->rx_ps_hdr_size)
2118 pci_unmap_single(pdev, buffer_info->dma,
2119 adapter->rx_ps_hdr_size,
2120 PCI_DMA_FROMDEVICE);
2121 else
2122 pci_unmap_single(pdev, buffer_info->dma,
2123 adapter->rx_buffer_len,
2124 PCI_DMA_FROMDEVICE);
2125 buffer_info->dma = 0;
2126 }
2127
2128 if (buffer_info->skb) {
2129 dev_kfree_skb(buffer_info->skb);
2130 buffer_info->skb = NULL;
2131 }
2132 if (buffer_info->page) {
bf36c1a0
AD		 2133 if (buffer_info->page_dma)
2134 pci_unmap_page(pdev, buffer_info->page_dma,
2135 PAGE_SIZE / 2,
2136 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2137 put_page(buffer_info->page);
2138 buffer_info->page = NULL;
2139 buffer_info->page_dma = 0;
bf36c1a0 2140 buffer_info->page_offset = 0;
9d5c8243
AK		 2141 }
2142 }
2143
9d5c8243
AK		 2144 size = sizeof(struct igb_buffer) * rx_ring->count;
2145 memset(rx_ring->buffer_info, 0, size);
2146
2147 /* Zero out the descriptor ring */
2148 memset(rx_ring->desc, 0, rx_ring->size);
2149
2150 rx_ring->next_to_clean = 0;
2151 rx_ring->next_to_use = 0;
2152
2153 writel(0, adapter->hw.hw_addr + rx_ring->head);
2154 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2155}
2156
2157/**
2158 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2159 * @adapter: board private structure
2160 **/
2161static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2162{
2163 int i;
2164
2165 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2166 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2167}
2168
2169/**
2170 * igb_set_mac - Change the Ethernet Address of the NIC
2171 * @netdev: network interface device structure
2172 * @p: pointer to an address structure
2173 *
2174 * Returns 0 on success, negative on failure
2175 **/
2176static int igb_set_mac(struct net_device *netdev, void *p)
2177{
2178 struct igb_adapter *adapter = netdev_priv(netdev);
2179 struct sockaddr *addr = p;
2180
2181 if (!is_valid_ether_addr(addr->sa_data))
2182 return -EADDRNOTAVAIL;
2183
2184 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2185 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2186
2187 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2188
2189 return 0;
2190}
2191
2192/**
2193 * igb_set_multi - Multicast and Promiscuous mode set
2194 * @netdev: network interface device structure
2195 *
2196 * The set_multi entry point is called whenever the multicast address
2197 * list or the network interface flags are updated. This routine is
2198 * responsible for configuring the hardware for proper multicast,
2199 * promiscuous mode, and all-multi behavior.
2200 **/
2201static void igb_set_multi(struct net_device *netdev)
2202{
2203 struct igb_adapter *adapter = netdev_priv(netdev);
2204 struct e1000_hw *hw = &adapter->hw;
2205 struct e1000_mac_info *mac = &hw->mac;
2206 struct dev_mc_list *mc_ptr;
2207 u8 *mta_list;
2208 u32 rctl;
2209 int i;
2210
2211 /* Check for Promiscuous and All Multicast modes */
2212
2213 rctl = rd32(E1000_RCTL);
2214
746b9f02 2215 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2216 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2217 rctl &= ~E1000_RCTL_VFE;
2218 } else {
2219 if (netdev->flags & IFF_ALLMULTI) {
2220 rctl |= E1000_RCTL_MPE;
2221 rctl &= ~E1000_RCTL_UPE;
2222 } else
2223 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2224 rctl |= E1000_RCTL_VFE;
746b9f02 2225 }
9d5c8243
AK		 2226 wr32(E1000_RCTL, rctl);
2227
2228 if (!netdev->mc_count) {
2229 /* nothing to program, so clear mc list */
8a900862
AD		 2230 igb_update_mc_addr_list(hw, NULL, 0, 1,
2231 mac->rar_entry_count);
9d5c8243
AK		 2232 return;
2233 }
2234
2235 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2236 if (!mta_list)
2237 return;
2238
2239 /* The shared function expects a packed array of only addresses. */
2240 mc_ptr = netdev->mc_list;
2241
2242 for (i = 0; i < netdev->mc_count; i++) {
2243 if (!mc_ptr)
2244 break;
2245 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2246 mc_ptr = mc_ptr->next;
2247 }
8a900862 2248 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
9d5c8243
AK		 2249 kfree(mta_list);
2250}
2251
2252/* Need to wait a few seconds after link up to get diagnostic information from
2253 * the phy */
2254static void igb_update_phy_info(unsigned long data)
2255{
2256 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2257 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2258}
2259
4d6b725e
AD		 2260/**
2261 * igb_has_link - check shared code for link and determine up/down
2262 * @adapter: pointer to driver private info
2263 **/
2264static bool igb_has_link(struct igb_adapter *adapter)
2265{
2266 struct e1000_hw *hw = &adapter->hw;
2267 bool link_active = false;
2268 s32 ret_val = 0;
2269
2270 /* get_link_status is set on LSC (link status) interrupt or
2271 * rx sequence error interrupt. get_link_status will stay
2272 * false until the e1000_check_for_link establishes link
2273 * for copper adapters ONLY
2274 */
2275 switch (hw->phy.media_type) {
2276 case e1000_media_type_copper:
2277 if (hw->mac.get_link_status) {
2278 ret_val = hw->mac.ops.check_for_link(hw);
2279 link_active = !hw->mac.get_link_status;
2280 } else {
2281 link_active = true;
2282 }
2283 break;
2284 case e1000_media_type_fiber:
2285 ret_val = hw->mac.ops.check_for_link(hw);
2286 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2287 break;
2288 case e1000_media_type_internal_serdes:
2289 ret_val = hw->mac.ops.check_for_link(hw);
2290 link_active = hw->mac.serdes_has_link;
2291 break;
2292 default:
2293 case e1000_media_type_unknown:
2294 break;
2295 }
2296
2297 return link_active;
2298}
2299
9d5c8243
AK		 2300/**
2301 * igb_watchdog - Timer Call-back
2302 * @data: pointer to adapter cast into an unsigned long
2303 **/
2304static void igb_watchdog(unsigned long data)
2305{
2306 struct igb_adapter *adapter = (struct igb_adapter *)data;
2307 /* Do the rest outside of interrupt context */
2308 schedule_work(&adapter->watchdog_task);
2309}
2310
2311static void igb_watchdog_task(struct work_struct *work)
2312{
2313 struct igb_adapter *adapter = container_of(work,
2314 struct igb_adapter, watchdog_task);
2315 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2316 struct net_device *netdev = adapter->netdev;
2317 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2318 u32 link;
7a6ea550 2319 u32 eics = 0;
7a6ea550 2320 int i;
9d5c8243 2321
4d6b725e
AD		 2322 link = igb_has_link(adapter);
2323 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2324 goto link_up;
2325
9d5c8243
AK		 2326 if (link) {
2327 if (!netif_carrier_ok(netdev)) {
2328 u32 ctrl;
2329 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2330 &adapter->link_speed,
2331 &adapter->link_duplex);
2332
2333 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2334 /* Links status message must follow this format */
2335 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2336 "Flow Control: %s\n",
527d47c1 2337 netdev->name,
9d5c8243
AK		 2338 adapter->link_speed,
2339 adapter->link_duplex == FULL_DUPLEX ?
2340 "Full Duplex" : "Half Duplex",
2341 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2342 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2343 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2344 E1000_CTRL_TFCE) ? "TX" : "None")));
2345
2346 /* tweak tx_queue_len according to speed/duplex and
2347 * adjust the timeout factor */
2348 netdev->tx_queue_len = adapter->tx_queue_len;
2349 adapter->tx_timeout_factor = 1;
2350 switch (adapter->link_speed) {
2351 case SPEED_10:
2352 netdev->tx_queue_len = 10;
2353 adapter->tx_timeout_factor = 14;
2354 break;
2355 case SPEED_100:
2356 netdev->tx_queue_len = 100;
2357 /* maybe add some timeout factor ? */
2358 break;
2359 }
2360
2361 netif_carrier_on(netdev);
fd2ea0a7 2362 netif_tx_wake_all_queues(netdev);
9d5c8243 2363
4b1a9877 2364 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2365 if (!test_bit(__IGB_DOWN, &adapter->state))
2366 mod_timer(&adapter->phy_info_timer,
2367 round_jiffies(jiffies + 2 * HZ));
2368 }
2369 } else {
2370 if (netif_carrier_ok(netdev)) {
2371 adapter->link_speed = 0;
2372 adapter->link_duplex = 0;
527d47c1
AD		 2373 /* Links status message must follow this format */
2374 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2375 netdev->name);
9d5c8243 2376 netif_carrier_off(netdev);
fd2ea0a7 2377 netif_tx_stop_all_queues(netdev);
4b1a9877
AD		 2378
2379 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2380 if (!test_bit(__IGB_DOWN, &adapter->state))
2381 mod_timer(&adapter->phy_info_timer,
2382 round_jiffies(jiffies + 2 * HZ));
2383 }
2384 }
2385
2386link_up:
2387 igb_update_stats(adapter);
2388
4b1a9877 2389 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2390 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2391 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2392 adapter->colc_old = adapter->stats.colc;
2393
2394 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2395 adapter->gorc_old = adapter->stats.gorc;
2396 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2397 adapter->gotc_old = adapter->stats.gotc;
2398
2399 igb_update_adaptive(&adapter->hw);
2400
2401 if (!netif_carrier_ok(netdev)) {
2402 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2403 /* We've lost link, so the controller stops DMA,
2404 * but we've got queued Tx work that's never going
2405 * to get done, so reset controller to flush Tx.
2406 * (Do the reset outside of interrupt context). */
2407 adapter->tx_timeout_count++;
2408 schedule_work(&adapter->reset_task);
2409 }
2410 }
2411
2412 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2413 if (adapter->msix_entries) {
2414 for (i = 0; i < adapter->num_rx_queues; i++)
2415 eics |= adapter->rx_ring[i].eims_value;
2416 wr32(E1000_EICS, eics);
2417 } else {
2418 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2419 }
9d5c8243
AK		 2420
2421 /* Force detection of hung controller every watchdog period */
2422 tx_ring->detect_tx_hung = true;
2423
2424 /* Reset the timer */
2425 if (!test_bit(__IGB_DOWN, &adapter->state))
2426 mod_timer(&adapter->watchdog_timer,
2427 round_jiffies(jiffies + 2 * HZ));
2428}
2429
2430enum latency_range {
2431 lowest_latency = 0,
2432 low_latency = 1,
2433 bulk_latency = 2,
2434 latency_invalid = 255
2435};
2436
2437
6eb5a7f1
AD		 2438/**
2439 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2440 *
2441 * Stores a new ITR value based on strictly on packet size. This
2442 * algorithm is less sophisticated than that used in igb_update_itr,
2443 * due to the difficulty of synchronizing statistics across multiple
2444 * receive rings. The divisors and thresholds used by this fuction
2445 * were determined based on theoretical maximum wire speed and testing
2446 * data, in order to minimize response time while increasing bulk
2447 * throughput.
2448 * This functionality is controlled by the InterruptThrottleRate module
2449 * parameter (see igb_param.c)
2450 * NOTE: This function is called only when operating in a multiqueue
2451 * receive environment.
2452 * @rx_ring: pointer to ring
2453 **/
2454static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2455{
6eb5a7f1
AD		 2456 int new_val = rx_ring->itr_val;
2457 int avg_wire_size = 0;
2458 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2459
6eb5a7f1
AD		 2460 if (!rx_ring->total_packets)
2461 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2462
6eb5a7f1
AD		 2463 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2464 * ints/sec - ITR timer value of 120 ticks.
2465 */
2466 if (adapter->link_speed != SPEED_1000) {
2467 new_val = 120;
2468 goto set_itr_val;
9d5c8243 2469 }
6eb5a7f1 2470 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2471
6eb5a7f1
AD		 2472 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2473 avg_wire_size += 24;
2474
2475 /* Don't starve jumbo frames */
2476 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2477
6eb5a7f1
AD		 2478 /* Give a little boost to mid-size frames */
2479 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2480 new_val = avg_wire_size / 3;
2481 else
2482 new_val = avg_wire_size / 2;
9d5c8243 2483
6eb5a7f1 2484set_itr_val:
9d5c8243
AK		 2485 if (new_val != rx_ring->itr_val) {
2486 rx_ring->itr_val = new_val;
6eb5a7f1 2487 rx_ring->set_itr = 1;
9d5c8243 2488 }
6eb5a7f1
AD		 2489clear_counts:
2490 rx_ring->total_bytes = 0;
2491 rx_ring->total_packets = 0;
9d5c8243
AK		 2492}
2493
2494/**
2495 * igb_update_itr - update the dynamic ITR value based on statistics
2496 * Stores a new ITR value based on packets and byte
2497 * counts during the last interrupt. The advantage of per interrupt
2498 * computation is faster updates and more accurate ITR for the current
2499 * traffic pattern. Constants in this function were computed
2500 * based on theoretical maximum wire speed and thresholds were set based
2501 * on testing data as well as attempting to minimize response time
2502 * while increasing bulk throughput.
2503 * this functionality is controlled by the InterruptThrottleRate module
2504 * parameter (see igb_param.c)
2505 * NOTE: These calculations are only valid when operating in a single-
2506 * queue environment.
2507 * @adapter: pointer to adapter
2508 * @itr_setting: current adapter->itr
2509 * @packets: the number of packets during this measurement interval
2510 * @bytes: the number of bytes during this measurement interval
2511 **/
2512static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2513 int packets, int bytes)
2514{
2515 unsigned int retval = itr_setting;
2516
2517 if (packets == 0)
2518 goto update_itr_done;
2519
2520 switch (itr_setting) {
2521 case lowest_latency:
2522 /* handle TSO and jumbo frames */
2523 if (bytes/packets > 8000)
2524 retval = bulk_latency;
2525 else if ((packets < 5) && (bytes > 512))
2526 retval = low_latency;
2527 break;
2528 case low_latency: /* 50 usec aka 20000 ints/s */
2529 if (bytes > 10000) {
2530 /* this if handles the TSO accounting */
2531 if (bytes/packets > 8000) {
2532 retval = bulk_latency;
2533 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2534 retval = bulk_latency;
2535 } else if ((packets > 35)) {
2536 retval = lowest_latency;
2537 }
2538 } else if (bytes/packets > 2000) {
2539 retval = bulk_latency;
2540 } else if (packets <= 2 && bytes < 512) {
2541 retval = lowest_latency;
2542 }
2543 break;
2544 case bulk_latency: /* 250 usec aka 4000 ints/s */
2545 if (bytes > 25000) {
2546 if (packets > 35)
2547 retval = low_latency;
2548 } else if (bytes < 6000) {
2549 retval = low_latency;
2550 }
2551 break;
2552 }
2553
2554update_itr_done:
2555 return retval;
2556}
2557
6eb5a7f1 2558static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2559{
2560 u16 current_itr;
2561 u32 new_itr = adapter->itr;
2562
2563 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2564 if (adapter->link_speed != SPEED_1000) {
2565 current_itr = 0;
2566 new_itr = 4000;
2567 goto set_itr_now;
2568 }
2569
2570 adapter->rx_itr = igb_update_itr(adapter,
2571 adapter->rx_itr,
2572 adapter->rx_ring->total_packets,
2573 adapter->rx_ring->total_bytes);
9d5c8243 2574
6eb5a7f1 2575 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2576 adapter->tx_itr = igb_update_itr(adapter,
2577 adapter->tx_itr,
2578 adapter->tx_ring->total_packets,
2579 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2580
2581 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2582 } else {
2583 current_itr = adapter->rx_itr;
2584 }
2585
6eb5a7f1
AD		 2586 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2587 if (adapter->itr_setting == 3 &&
2588 current_itr == lowest_latency)
2589 current_itr = low_latency;
2590
9d5c8243
AK		 2591 switch (current_itr) {
2592 /* counts and packets in update_itr are dependent on these numbers */
2593 case lowest_latency:
2594 new_itr = 70000;
2595 break;
2596 case low_latency:
2597 new_itr = 20000; /* aka hwitr = ~200 */
2598 break;
2599 case bulk_latency:
2600 new_itr = 4000;
2601 break;
2602 default:
2603 break;
2604 }
2605
2606set_itr_now:
6eb5a7f1
AD		 2607 adapter->rx_ring->total_bytes = 0;
2608 adapter->rx_ring->total_packets = 0;
2609 if (adapter->rx_ring->buddy) {
2610 adapter->rx_ring->buddy->total_bytes = 0;
2611 adapter->rx_ring->buddy->total_packets = 0;
2612 }
2613
9d5c8243
AK		 2614 if (new_itr != adapter->itr) {
2615 /* this attempts to bias the interrupt rate towards Bulk
2616 * by adding intermediate steps when interrupt rate is
2617 * increasing */
2618 new_itr = new_itr > adapter->itr ?
2619 min(adapter->itr + (new_itr >> 2), new_itr) :
2620 new_itr;
2621 /* Don't write the value here; it resets the adapter's
2622 * internal timer, and causes us to delay far longer than
2623 * we should between interrupts. Instead, we write the ITR
2624 * value at the beginning of the next interrupt so the timing
2625 * ends up being correct.
2626 */
2627 adapter->itr = new_itr;
6eb5a7f1
AD		 2628 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2629 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2630 }
2631
2632 return;
2633}
2634
2635
2636#define IGB_TX_FLAGS_CSUM 0x00000001
2637#define IGB_TX_FLAGS_VLAN 0x00000002
2638#define IGB_TX_FLAGS_TSO 0x00000004
2639#define IGB_TX_FLAGS_IPV4 0x00000008
2640#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2641#define IGB_TX_FLAGS_VLAN_SHIFT 16
2642
2643static inline int igb_tso_adv(struct igb_adapter *adapter,
2644 struct igb_ring *tx_ring,
2645 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2646{
2647 struct e1000_adv_tx_context_desc *context_desc;
2648 unsigned int i;
2649 int err;
2650 struct igb_buffer *buffer_info;
2651 u32 info = 0, tu_cmd = 0;
2652 u32 mss_l4len_idx, l4len;
2653 *hdr_len = 0;
2654
2655 if (skb_header_cloned(skb)) {
2656 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2657 if (err)
2658 return err;
2659 }
2660
2661 l4len = tcp_hdrlen(skb);
2662 *hdr_len += l4len;
2663
2664 if (skb->protocol == htons(ETH_P_IP)) {
2665 struct iphdr *iph = ip_hdr(skb);
2666 iph->tot_len = 0;
2667 iph->check = 0;
2668 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2669 iph->daddr, 0,
2670 IPPROTO_TCP,
2671 0);
2672 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2673 ipv6_hdr(skb)->payload_len = 0;
2674 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2675 &ipv6_hdr(skb)->daddr,
2676 0, IPPROTO_TCP, 0);
2677 }
2678
2679 i = tx_ring->next_to_use;
2680
2681 buffer_info = &tx_ring->buffer_info[i];
2682 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2683 /* VLAN MACLEN IPLEN */
2684 if (tx_flags & IGB_TX_FLAGS_VLAN)
2685 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2686 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2687 *hdr_len += skb_network_offset(skb);
2688 info |= skb_network_header_len(skb);
2689 *hdr_len += skb_network_header_len(skb);
2690 context_desc->vlan_macip_lens = cpu_to_le32(info);
2691
2692 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2693 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2694
2695 if (skb->protocol == htons(ETH_P_IP))
2696 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2697 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2698
2699 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2700
2701 /* MSS L4LEN IDX */
2702 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2703 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2704
7dfc16fa
AD		 2705 /* Context index must be unique per ring. */
2706 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2707 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2708
2709 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2710 context_desc->seqnum_seed = 0;
2711
2712 buffer_info->time_stamp = jiffies;
0e014cb1 2713 buffer_info->next_to_watch = i;
9d5c8243
AK		 2714 buffer_info->dma = 0;
2715 i++;
2716 if (i == tx_ring->count)
2717 i = 0;
2718
2719 tx_ring->next_to_use = i;
2720
2721 return true;
2722}
2723
2724static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2725 struct igb_ring *tx_ring,
2726 struct sk_buff *skb, u32 tx_flags)
2727{
2728 struct e1000_adv_tx_context_desc *context_desc;
2729 unsigned int i;
2730 struct igb_buffer *buffer_info;
2731 u32 info = 0, tu_cmd = 0;
2732
2733 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2734 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2735 i = tx_ring->next_to_use;
2736 buffer_info = &tx_ring->buffer_info[i];
2737 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2738
2739 if (tx_flags & IGB_TX_FLAGS_VLAN)
2740 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2741 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2742 if (skb->ip_summed == CHECKSUM_PARTIAL)
2743 info |= skb_network_header_len(skb);
2744
2745 context_desc->vlan_macip_lens = cpu_to_le32(info);
2746
2747 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2748
2749 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3 2750 switch (skb->protocol) {
09640e63 2751 case cpu_to_be16(ETH_P_IP):
9d5c8243 2752 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2753 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2754 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2755 break;
09640e63 2756 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 2757 /* XXX what about other V6 headers?? */
2758 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2759 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2760 break;
2761 default:
2762 if (unlikely(net_ratelimit()))
2763 dev_warn(&adapter->pdev->dev,
2764 "partial checksum but proto=%x!\n",
2765 skb->protocol);
2766 break;
2767 }
9d5c8243
AK		 2768 }
2769
2770 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2771 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2772 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2773 context_desc->mss_l4len_idx =
2774 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2775
2776 buffer_info->time_stamp = jiffies;
0e014cb1 2777 buffer_info->next_to_watch = i;
9d5c8243
AK		 2778 buffer_info->dma = 0;
2779
2780 i++;
2781 if (i == tx_ring->count)
2782 i = 0;
2783 tx_ring->next_to_use = i;
2784
2785 return true;
2786 }
2787
2788
2789 return false;
2790}
2791
2792#define IGB_MAX_TXD_PWR 16
2793#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2794
2795static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 2796 struct igb_ring *tx_ring, struct sk_buff *skb,
2797 unsigned int first)
9d5c8243
AK		 2798{
2799 struct igb_buffer *buffer_info;
2800 unsigned int len = skb_headlen(skb);
2801 unsigned int count = 0, i;
2802 unsigned int f;
2803
2804 i = tx_ring->next_to_use;
2805
2806 buffer_info = &tx_ring->buffer_info[i];
2807 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2808 buffer_info->length = len;
2809 /* set time_stamp *before* dma to help avoid a possible race */
2810 buffer_info->time_stamp = jiffies;
0e014cb1 2811 buffer_info->next_to_watch = i;
9d5c8243
AK		 2812 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2813 PCI_DMA_TODEVICE);
2814 count++;
2815 i++;
2816 if (i == tx_ring->count)
2817 i = 0;
2818
2819 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2820 struct skb_frag_struct *frag;
2821
2822 frag = &skb_shinfo(skb)->frags[f];
2823 len = frag->size;
2824
2825 buffer_info = &tx_ring->buffer_info[i];
2826 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2827 buffer_info->length = len;
2828 buffer_info->time_stamp = jiffies;
0e014cb1 2829 buffer_info->next_to_watch = i;
9d5c8243
AK		 2830 buffer_info->dma = pci_map_page(adapter->pdev,
2831 frag->page,
2832 frag->page_offset,
2833 len,
2834 PCI_DMA_TODEVICE);
2835
2836 count++;
2837 i++;
2838 if (i == tx_ring->count)
2839 i = 0;
2840 }
2841
0e014cb1 2842 i = ((i == 0) ? tx_ring->count - 1 : i - 1);
9d5c8243 2843 tx_ring->buffer_info[i].skb = skb;
0e014cb1 2844 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243
AK		 2845
2846 return count;
2847}
2848
2849static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2850 struct igb_ring *tx_ring,
2851 int tx_flags, int count, u32 paylen,
2852 u8 hdr_len)
2853{
2854 union e1000_adv_tx_desc *tx_desc = NULL;
2855 struct igb_buffer *buffer_info;
2856 u32 olinfo_status = 0, cmd_type_len;
2857 unsigned int i;
2858
2859 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2860 E1000_ADVTXD_DCMD_DEXT);
2861
2862 if (tx_flags & IGB_TX_FLAGS_VLAN)
2863 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2864
2865 if (tx_flags & IGB_TX_FLAGS_TSO) {
2866 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2867
2868 /* insert tcp checksum */
2869 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2870
2871 /* insert ip checksum */
2872 if (tx_flags & IGB_TX_FLAGS_IPV4)
2873 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2874
2875 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2876 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2877 }
2878
7dfc16fa
AD		 2879 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2880 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2881 IGB_TX_FLAGS_VLAN)))
661086df 2882 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2883
2884 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2885
2886 i = tx_ring->next_to_use;
2887 while (count--) {
2888 buffer_info = &tx_ring->buffer_info[i];
2889 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2890 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2891 tx_desc->read.cmd_type_len =
2892 cpu_to_le32(cmd_type_len | buffer_info->length);
2893 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2894 i++;
2895 if (i == tx_ring->count)
2896 i = 0;
2897 }
2898
2899 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2900 /* Force memory writes to complete before letting h/w
2901 * know there are new descriptors to fetch. (Only
2902 * applicable for weak-ordered memory model archs,
2903 * such as IA-64). */
2904 wmb();
2905
2906 tx_ring->next_to_use = i;
2907 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2908 /* we need this if more than one processor can write to our tail
2909 * at a time, it syncronizes IO on IA64/Altix systems */
2910 mmiowb();
2911}
2912
2913static int __igb_maybe_stop_tx(struct net_device *netdev,
2914 struct igb_ring *tx_ring, int size)
2915{
2916 struct igb_adapter *adapter = netdev_priv(netdev);
2917
661086df 2918 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 2919
9d5c8243
AK		 2920 /* Herbert's original patch had:
2921 * smp_mb__after_netif_stop_queue();
2922 * but since that doesn't exist yet, just open code it. */
2923 smp_mb();
2924
2925 /* We need to check again in a case another CPU has just
2926 * made room available. */
2927 if (IGB_DESC_UNUSED(tx_ring) < size)
2928 return -EBUSY;
2929
2930 /* A reprieve! */
661086df 2931 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 2932 ++adapter->restart_queue;
2933 return 0;
2934}
2935
2936static int igb_maybe_stop_tx(struct net_device *netdev,
2937 struct igb_ring *tx_ring, int size)
2938{
2939 if (IGB_DESC_UNUSED(tx_ring) >= size)
2940 return 0;
2941 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2942}
2943
2944#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2945
2946static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2947 struct net_device *netdev,
2948 struct igb_ring *tx_ring)
2949{
2950 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 2951 unsigned int first;
9d5c8243
AK		 2952 unsigned int tx_flags = 0;
2953 unsigned int len;
9d5c8243
AK		 2954 u8 hdr_len = 0;
2955 int tso = 0;
2956
2957 len = skb_headlen(skb);
2958
2959 if (test_bit(__IGB_DOWN, &adapter->state)) {
2960 dev_kfree_skb_any(skb);
2961 return NETDEV_TX_OK;
2962 }
2963
2964 if (skb->len <= 0) {
2965 dev_kfree_skb_any(skb);
2966 return NETDEV_TX_OK;
2967 }
2968
9d5c8243
AK		 2969 /* need: 1 descriptor per page,
2970 * + 2 desc gap to keep tail from touching head,
2971 * + 1 desc for skb->data,
2972 * + 1 desc for context descriptor,
2973 * otherwise try next time */
2974 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2975 /* this is a hard error */
9d5c8243
AK		 2976 return NETDEV_TX_BUSY;
2977 }
6eb5a7f1 2978 skb_orphan(skb);
9d5c8243
AK		 2979
2980 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2981 tx_flags |= IGB_TX_FLAGS_VLAN;
2982 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2983 }
2984
661086df
PWJ		 2985 if (skb->protocol == htons(ETH_P_IP))
2986 tx_flags |= IGB_TX_FLAGS_IPV4;
2987
0e014cb1
AD		 2988 first = tx_ring->next_to_use;
2989
9d5c8243
AK		 2990 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2991 &hdr_len) : 0;
2992
2993 if (tso < 0) {
2994 dev_kfree_skb_any(skb);
9d5c8243
AK		 2995 return NETDEV_TX_OK;
2996 }
2997
2998 if (tso)
2999 tx_flags |= IGB_TX_FLAGS_TSO;
3000 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
3001 if (skb->ip_summed == CHECKSUM_PARTIAL)
3002 tx_flags |= IGB_TX_FLAGS_CSUM;
3003
9d5c8243 3004 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
0e014cb1 3005 igb_tx_map_adv(adapter, tx_ring, skb, first),
9d5c8243
AK		 3006 skb->len, hdr_len);
3007
3008 netdev->trans_start = jiffies;
3009
3010 /* Make sure there is space in the ring for the next send. */
3011 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3012
9d5c8243
AK		 3013 return NETDEV_TX_OK;
3014}
3015
3016static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3017{
3018 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3019 struct igb_ring *tx_ring;
3020
661086df
PWJ		 3021 int r_idx = 0;
3022 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3023 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3024
3025 /* This goes back to the question of how to logically map a tx queue
3026 * to a flow. Right now, performance is impacted slightly negatively
3027 * if using multiple tx queues. If the stack breaks away from a
3028 * single qdisc implementation, we can look at this again. */
3029 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3030}
3031
3032/**
3033 * igb_tx_timeout - Respond to a Tx Hang
3034 * @netdev: network interface device structure
3035 **/
3036static void igb_tx_timeout(struct net_device *netdev)
3037{
3038 struct igb_adapter *adapter = netdev_priv(netdev);
3039 struct e1000_hw *hw = &adapter->hw;
3040
3041 /* Do the reset outside of interrupt context */
3042 adapter->tx_timeout_count++;
3043 schedule_work(&adapter->reset_task);
3044 wr32(E1000_EICS, adapter->eims_enable_mask &
3045 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3046}
3047
3048static void igb_reset_task(struct work_struct *work)
3049{
3050 struct igb_adapter *adapter;
3051 adapter = container_of(work, struct igb_adapter, reset_task);
3052
3053 igb_reinit_locked(adapter);
3054}
3055
3056/**
3057 * igb_get_stats - Get System Network Statistics
3058 * @netdev: network interface device structure
3059 *
3060 * Returns the address of the device statistics structure.
3061 * The statistics are actually updated from the timer callback.
3062 **/
3063static struct net_device_stats *
3064igb_get_stats(struct net_device *netdev)
3065{
3066 struct igb_adapter *adapter = netdev_priv(netdev);
3067
3068 /* only return the current stats */
3069 return &adapter->net_stats;
3070}
3071
3072/**
3073 * igb_change_mtu - Change the Maximum Transfer Unit
3074 * @netdev: network interface device structure
3075 * @new_mtu: new value for maximum frame size
3076 *
3077 * Returns 0 on success, negative on failure
3078 **/
3079static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3080{
3081 struct igb_adapter *adapter = netdev_priv(netdev);
3082 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3083
3084 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3085 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3086 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3087 return -EINVAL;
3088 }
3089
3090#define MAX_STD_JUMBO_FRAME_SIZE 9234
3091 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3092 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3093 return -EINVAL;
3094 }
3095
3096 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3097 msleep(1);
3098 /* igb_down has a dependency on max_frame_size */
3099 adapter->max_frame_size = max_frame;
3100 if (netif_running(netdev))
3101 igb_down(adapter);
3102
3103 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3104 * means we reserve 2 more, this pushes us to allocate from the next
3105 * larger slab size.
3106 * i.e. RXBUFFER_2048 --> size-4096 slab
3107 */
3108
3109 if (max_frame <= IGB_RXBUFFER_256)
3110 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3111 else if (max_frame <= IGB_RXBUFFER_512)
3112 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3113 else if (max_frame <= IGB_RXBUFFER_1024)
3114 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3115 else if (max_frame <= IGB_RXBUFFER_2048)
3116 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3117 else
bf36c1a0
AD		 3118#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3119 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3120#else
3121 adapter->rx_buffer_len = PAGE_SIZE / 2;
3122#endif
9d5c8243
AK		 3123 /* adjust allocation if LPE protects us, and we aren't using SBP */
3124 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3125 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3126 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3127
3128 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3129 netdev->mtu, new_mtu);
3130 netdev->mtu = new_mtu;
3131
3132 if (netif_running(netdev))
3133 igb_up(adapter);
3134 else
3135 igb_reset(adapter);
3136
3137 clear_bit(__IGB_RESETTING, &adapter->state);
3138
3139 return 0;
3140}
3141
3142/**
3143 * igb_update_stats - Update the board statistics counters
3144 * @adapter: board private structure
3145 **/
3146
3147void igb_update_stats(struct igb_adapter *adapter)
3148{
3149 struct e1000_hw *hw = &adapter->hw;
3150 struct pci_dev *pdev = adapter->pdev;
3151 u16 phy_tmp;
3152
3153#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3154
3155 /*
3156 * Prevent stats update while adapter is being reset, or if the pci
3157 * connection is down.
3158 */
3159 if (adapter->link_speed == 0)
3160 return;
3161 if (pci_channel_offline(pdev))
3162 return;
3163
3164 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3165 adapter->stats.gprc += rd32(E1000_GPRC);
3166 adapter->stats.gorc += rd32(E1000_GORCL);
3167 rd32(E1000_GORCH); /* clear GORCL */
3168 adapter->stats.bprc += rd32(E1000_BPRC);
3169 adapter->stats.mprc += rd32(E1000_MPRC);
3170 adapter->stats.roc += rd32(E1000_ROC);
3171
3172 adapter->stats.prc64 += rd32(E1000_PRC64);
3173 adapter->stats.prc127 += rd32(E1000_PRC127);
3174 adapter->stats.prc255 += rd32(E1000_PRC255);
3175 adapter->stats.prc511 += rd32(E1000_PRC511);
3176 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3177 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3178 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3179 adapter->stats.sec += rd32(E1000_SEC);
3180
3181 adapter->stats.mpc += rd32(E1000_MPC);
3182 adapter->stats.scc += rd32(E1000_SCC);
3183 adapter->stats.ecol += rd32(E1000_ECOL);
3184 adapter->stats.mcc += rd32(E1000_MCC);
3185 adapter->stats.latecol += rd32(E1000_LATECOL);
3186 adapter->stats.dc += rd32(E1000_DC);
3187 adapter->stats.rlec += rd32(E1000_RLEC);
3188 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3189 adapter->stats.xontxc += rd32(E1000_XONTXC);
3190 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3191 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3192 adapter->stats.fcruc += rd32(E1000_FCRUC);
3193 adapter->stats.gptc += rd32(E1000_GPTC);
3194 adapter->stats.gotc += rd32(E1000_GOTCL);
3195 rd32(E1000_GOTCH); /* clear GOTCL */
3196 adapter->stats.rnbc += rd32(E1000_RNBC);
3197 adapter->stats.ruc += rd32(E1000_RUC);
3198 adapter->stats.rfc += rd32(E1000_RFC);
3199 adapter->stats.rjc += rd32(E1000_RJC);
3200 adapter->stats.tor += rd32(E1000_TORH);
3201 adapter->stats.tot += rd32(E1000_TOTH);
3202 adapter->stats.tpr += rd32(E1000_TPR);
3203
3204 adapter->stats.ptc64 += rd32(E1000_PTC64);
3205 adapter->stats.ptc127 += rd32(E1000_PTC127);
3206 adapter->stats.ptc255 += rd32(E1000_PTC255);
3207 adapter->stats.ptc511 += rd32(E1000_PTC511);
3208 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3209 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3210
3211 adapter->stats.mptc += rd32(E1000_MPTC);
3212 adapter->stats.bptc += rd32(E1000_BPTC);
3213
3214 /* used for adaptive IFS */
3215
3216 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3217 adapter->stats.tpt += hw->mac.tx_packet_delta;
3218 hw->mac.collision_delta = rd32(E1000_COLC);
3219 adapter->stats.colc += hw->mac.collision_delta;
3220
3221 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3222 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3223 adapter->stats.tncrs += rd32(E1000_TNCRS);
3224 adapter->stats.tsctc += rd32(E1000_TSCTC);
3225 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3226
3227 adapter->stats.iac += rd32(E1000_IAC);
3228 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3229 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3230 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3231 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3232 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3233 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3234 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3235 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3236
3237 /* Fill out the OS statistics structure */
3238 adapter->net_stats.multicast = adapter->stats.mprc;
3239 adapter->net_stats.collisions = adapter->stats.colc;
3240
3241 /* Rx Errors */
3242
3243 /* RLEC on some newer hardware can be incorrect so build
3244 * our own version based on RUC and ROC */
3245 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3246 adapter->stats.crcerrs + adapter->stats.algnerrc +
3247 adapter->stats.ruc + adapter->stats.roc +
3248 adapter->stats.cexterr;
3249 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3250 adapter->stats.roc;
3251 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3252 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3253 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3254
3255 /* Tx Errors */
3256 adapter->net_stats.tx_errors = adapter->stats.ecol +
3257 adapter->stats.latecol;
3258 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3259 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3260 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3261
3262 /* Tx Dropped needs to be maintained elsewhere */
3263
3264 /* Phy Stats */
3265 if (hw->phy.media_type == e1000_media_type_copper) {
3266 if ((adapter->link_speed == SPEED_1000) &&
f5f4cf08 3267 (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
9d5c8243
AK		 3268 &phy_tmp))) {
3269 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3270 adapter->phy_stats.idle_errors += phy_tmp;
3271 }
3272 }
3273
3274 /* Management Stats */
3275 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3276 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3277 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3278}
3279
3280
3281static irqreturn_t igb_msix_other(int irq, void *data)
3282{
3283 struct net_device *netdev = data;
3284 struct igb_adapter *adapter = netdev_priv(netdev);
3285 struct e1000_hw *hw = &adapter->hw;
844290e5 3286 u32 icr = rd32(E1000_ICR);
9d5c8243 3287
844290e5 3288 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3289
3290 if(icr & E1000_ICR_DOUTSYNC) {
3291 /* HW is reporting DMA is out of sync */
3292 adapter->stats.doosync++;
3293 }
844290e5
PW		 3294 if (!(icr & E1000_ICR_LSC))
3295 goto no_link_interrupt;
3296 hw->mac.get_link_status = 1;
3297 /* guard against interrupt when we're going down */
3298 if (!test_bit(__IGB_DOWN, &adapter->state))
3299 mod_timer(&adapter->watchdog_timer, jiffies + 1);
eebbbdba 3300
9d5c8243 3301no_link_interrupt:
dda0e083 3302 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
844290e5 3303 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3304
3305 return IRQ_HANDLED;
3306}
3307
3308static irqreturn_t igb_msix_tx(int irq, void *data)
3309{
3310 struct igb_ring *tx_ring = data;
3311 struct igb_adapter *adapter = tx_ring->adapter;
3312 struct e1000_hw *hw = &adapter->hw;
3313
421e02f0 3314#ifdef CONFIG_IGB_DCA
7dfc16fa 3315 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3316 igb_update_tx_dca(tx_ring);
3317#endif
9d5c8243
AK		 3318 tx_ring->total_bytes = 0;
3319 tx_ring->total_packets = 0;
661086df
PWJ		 3320
3321 /* auto mask will automatically reenable the interrupt when we write
3322 * EICS */
3b644cf6 3323 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3324 /* Ring was not completely cleaned, so fire another interrupt */
3325 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3326 else
9d5c8243 3327 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3328
9d5c8243
AK		 3329 return IRQ_HANDLED;
3330}
3331
6eb5a7f1
AD		 3332static void igb_write_itr(struct igb_ring *ring)
3333{
3334 struct e1000_hw *hw = &ring->adapter->hw;
3335 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3336 switch (hw->mac.type) {
3337 case e1000_82576:
3338 wr32(ring->itr_register,
3339 ring->itr_val |
3340 0x80000000);
3341 break;
3342 default:
3343 wr32(ring->itr_register,
3344 ring->itr_val |
3345 (ring->itr_val << 16));
3346 break;
3347 }
3348 ring->set_itr = 0;
3349 }
3350}
3351
9d5c8243
AK		 3352static irqreturn_t igb_msix_rx(int irq, void *data)
3353{
3354 struct igb_ring *rx_ring = data;
9d5c8243 3355
844290e5
PW		 3356 /* Write the ITR value calculated at the end of the
3357 * previous interrupt.
3358 */
9d5c8243 3359
6eb5a7f1 3360 igb_write_itr(rx_ring);
9d5c8243 3361
288379f0
BH		 3362 if (napi_schedule_prep(&rx_ring->napi))
3363 __napi_schedule(&rx_ring->napi);
844290e5 3364
421e02f0 3365#ifdef CONFIG_IGB_DCA
8d253320 3366 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3367 igb_update_rx_dca(rx_ring);
3368#endif
3369 return IRQ_HANDLED;
3370}
3371
421e02f0 3372#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3373static void igb_update_rx_dca(struct igb_ring *rx_ring)
3374{
3375 u32 dca_rxctrl;
3376 struct igb_adapter *adapter = rx_ring->adapter;
3377 struct e1000_hw *hw = &adapter->hw;
3378 int cpu = get_cpu();
26bc19ec 3379 int q = rx_ring->reg_idx;
fe4506b6
JC		 3380
3381 if (rx_ring->cpu != cpu) {
3382 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3383 if (hw->mac.type == e1000_82576) {
3384 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3385 dca_rxctrl |= dca_get_tag(cpu) <<
3386 E1000_DCA_RXCTRL_CPUID_SHIFT;
3387 } else {
3388 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3389 dca_rxctrl |= dca_get_tag(cpu);
3390 }
fe4506b6
JC		 3391 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3392 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3393 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3394 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3395 rx_ring->cpu = cpu;
3396 }
3397 put_cpu();
3398}
3399
3400static void igb_update_tx_dca(struct igb_ring *tx_ring)
3401{
3402 u32 dca_txctrl;
3403 struct igb_adapter *adapter = tx_ring->adapter;
3404 struct e1000_hw *hw = &adapter->hw;
3405 int cpu = get_cpu();
26bc19ec 3406 int q = tx_ring->reg_idx;
fe4506b6
JC		 3407
3408 if (tx_ring->cpu != cpu) {
3409 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3410 if (hw->mac.type == e1000_82576) {
3411 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3412 dca_txctrl |= dca_get_tag(cpu) <<
3413 E1000_DCA_TXCTRL_CPUID_SHIFT;
3414 } else {
3415 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3416 dca_txctrl |= dca_get_tag(cpu);
3417 }
fe4506b6
JC		 3418 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3419 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3420 tx_ring->cpu = cpu;
3421 }
3422 put_cpu();
3423}
3424
3425static void igb_setup_dca(struct igb_adapter *adapter)
3426{
3427 int i;
3428
7dfc16fa 3429 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3430 return;
3431
3432 for (i = 0; i < adapter->num_tx_queues; i++) {
3433 adapter->tx_ring[i].cpu = -1;
3434 igb_update_tx_dca(&adapter->tx_ring[i]);
3435 }
3436 for (i = 0; i < adapter->num_rx_queues; i++) {
3437 adapter->rx_ring[i].cpu = -1;
3438 igb_update_rx_dca(&adapter->rx_ring[i]);
3439 }
3440}
3441
3442static int __igb_notify_dca(struct device *dev, void *data)
3443{
3444 struct net_device *netdev = dev_get_drvdata(dev);
3445 struct igb_adapter *adapter = netdev_priv(netdev);
3446 struct e1000_hw *hw = &adapter->hw;
3447 unsigned long event = *(unsigned long *)data;
3448
3449 switch (event) {
3450 case DCA_PROVIDER_ADD:
3451 /* if already enabled, don't do it again */
7dfc16fa 3452 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3453 break;
fe4506b6
JC		 3454 /* Always use CB2 mode, difference is masked
3455 * in the CB driver. */
3456 wr32(E1000_DCA_CTRL, 2);
3457 if (dca_add_requester(dev) == 0) {
bbd98fe4 3458 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3459 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3460 igb_setup_dca(adapter);
3461 break;
3462 }
3463 /* Fall Through since DCA is disabled. */
3464 case DCA_PROVIDER_REMOVE:
7dfc16fa 3465 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3466 /* without this a class_device is left
3467 * hanging around in the sysfs model */
3468 dca_remove_requester(dev);
3469 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3470 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3471 wr32(E1000_DCA_CTRL, 1);
3472 }
3473 break;
3474 }
bbd98fe4 3475
fe4506b6 3476 return 0;
9d5c8243
AK		 3477}
3478
fe4506b6
JC		 3479static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3480 void *p)
3481{
3482 int ret_val;
3483
3484 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3485 __igb_notify_dca);
3486
3487 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3488}
421e02f0 3489#endif /* CONFIG_IGB_DCA */
9d5c8243
AK		 3490
3491/**
3492 * igb_intr_msi - Interrupt Handler
3493 * @irq: interrupt number
3494 * @data: pointer to a network interface device structure
3495 **/
3496static irqreturn_t igb_intr_msi(int irq, void *data)
3497{
3498 struct net_device *netdev = data;
3499 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3500 struct e1000_hw *hw = &adapter->hw;
3501 /* read ICR disables interrupts using IAM */
3502 u32 icr = rd32(E1000_ICR);
3503
6eb5a7f1 3504 igb_write_itr(adapter->rx_ring);
9d5c8243 3505
dda0e083
AD		 3506 if(icr & E1000_ICR_DOUTSYNC) {
3507 /* HW is reporting DMA is out of sync */
3508 adapter->stats.doosync++;
3509 }
3510
9d5c8243
AK		 3511 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3512 hw->mac.get_link_status = 1;
3513 if (!test_bit(__IGB_DOWN, &adapter->state))
3514 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3515 }
3516
288379f0 3517 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3518
3519 return IRQ_HANDLED;
3520}
3521
3522/**
3523 * igb_intr - Interrupt Handler
3524 * @irq: interrupt number
3525 * @data: pointer to a network interface device structure
3526 **/
3527static irqreturn_t igb_intr(int irq, void *data)
3528{
3529 struct net_device *netdev = data;
3530 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3531 struct e1000_hw *hw = &adapter->hw;
3532 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3533 * need for the IMC write */
3534 u32 icr = rd32(E1000_ICR);
3535 u32 eicr = 0;
3536 if (!icr)
3537 return IRQ_NONE; /* Not our interrupt */
3538
6eb5a7f1 3539 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3540
3541 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3542 * not set, then the adapter didn't send an interrupt */
3543 if (!(icr & E1000_ICR_INT_ASSERTED))
3544 return IRQ_NONE;
3545
dda0e083
AD		 3546 if(icr & E1000_ICR_DOUTSYNC) {
3547 /* HW is reporting DMA is out of sync */
3548 adapter->stats.doosync++;
3549 }
3550
9d5c8243
AK		 3551 eicr = rd32(E1000_EICR);
3552
3553 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3554 hw->mac.get_link_status = 1;
3555 /* guard against interrupt when we're going down */
3556 if (!test_bit(__IGB_DOWN, &adapter->state))
3557 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3558 }
3559
288379f0 3560 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 3561
3562 return IRQ_HANDLED;
3563}
3564
3565/**
661086df
PWJ		 3566 * igb_poll - NAPI Rx polling callback
3567 * @napi: napi polling structure
3568 * @budget: count of how many packets we should handle
9d5c8243 3569 **/
661086df 3570static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3571{
661086df
PWJ		 3572 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3573 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3574 struct net_device *netdev = adapter->netdev;
661086df 3575 int tx_clean_complete, work_done = 0;
9d5c8243 3576
661086df 3577 /* this poll routine only supports one tx and one rx queue */
421e02f0 3578#ifdef CONFIG_IGB_DCA
7dfc16fa 3579 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3580 igb_update_tx_dca(&adapter->tx_ring[0]);
3581#endif
661086df 3582 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6 3583
421e02f0 3584#ifdef CONFIG_IGB_DCA
7dfc16fa 3585 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3586 igb_update_rx_dca(&adapter->rx_ring[0]);
3587#endif
661086df 3588 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3589
3590 /* If no Tx and not enough Rx work done, exit the polling mode */
3591 if ((tx_clean_complete && (work_done < budget)) ||
3592 !netif_running(netdev)) {
9d5c8243 3593 if (adapter->itr_setting & 3)
6eb5a7f1 3594 igb_set_itr(adapter);
288379f0 3595 napi_complete(napi);
9d5c8243
AK		 3596 if (!test_bit(__IGB_DOWN, &adapter->state))
3597 igb_irq_enable(adapter);
3598 return 0;
3599 }
3600
3601 return 1;
3602}
3603
3604static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3605{
3606 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3607 struct igb_adapter *adapter = rx_ring->adapter;
3608 struct e1000_hw *hw = &adapter->hw;
3609 struct net_device *netdev = adapter->netdev;
3610 int work_done = 0;
3611
421e02f0 3612#ifdef CONFIG_IGB_DCA
7dfc16fa 3613 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3614 igb_update_rx_dca(rx_ring);
3615#endif
3b644cf6 3616 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3617
3618
3619 /* If not enough Rx work done, exit the polling mode */
3620 if ((work_done == 0) || !netif_running(netdev)) {
288379f0 3621 napi_complete(napi);
9d5c8243 3622
6eb5a7f1
AD		 3623 if (adapter->itr_setting & 3) {
3624 if (adapter->num_rx_queues == 1)
3625 igb_set_itr(adapter);
3626 else
3627 igb_update_ring_itr(rx_ring);
9d5c8243 3628 }
844290e5
PW		 3629
3630 if (!test_bit(__IGB_DOWN, &adapter->state))
3631 wr32(E1000_EIMS, rx_ring->eims_value);
3632
9d5c8243
AK		 3633 return 0;
3634 }
3635
3636 return 1;
3637}
6d8126f9 3638
9d5c8243
AK		 3639/**
3640 * igb_clean_tx_irq - Reclaim resources after transmit completes
3641 * @adapter: board private structure
3642 * returns true if ring is completely cleaned
3643 **/
3b644cf6 3644static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3645{
3b644cf6 3646 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 3647 struct net_device *netdev = adapter->netdev;
0e014cb1 3648 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3649 struct igb_buffer *buffer_info;
3650 struct sk_buff *skb;
0e014cb1 3651 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 3652 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 3653 unsigned int i, eop, count = 0;
3654 bool cleaned = false;
9d5c8243 3655
9d5c8243 3656 i = tx_ring->next_to_clean;
0e014cb1
AD		 3657 eop = tx_ring->buffer_info[i].next_to_watch;
3658 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3659
3660 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
3661 (count < tx_ring->count)) {
3662 for (cleaned = false; !cleaned; count++) {
3663 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 3664 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 3665 cleaned = (i == eop);
9d5c8243
AK		 3666 skb = buffer_info->skb;
3667
3668 if (skb) {
3669 unsigned int segs, bytecount;
3670 /* gso_segs is currently only valid for tcp */
3671 segs = skb_shinfo(skb)->gso_segs ?: 1;
3672 /* multiply data chunks by size of headers */
3673 bytecount = ((segs - 1) * skb_headlen(skb)) +
3674 skb->len;
3675 total_packets += segs;
3676 total_bytes += bytecount;
3677 }
3678
3679 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 3680 tx_desc->wb.status = 0;
9d5c8243
AK		 3681
3682 i++;
3683 if (i == tx_ring->count)
3684 i = 0;
9d5c8243 3685 }
0e014cb1
AD		 3686
3687 eop = tx_ring->buffer_info[i].next_to_watch;
3688 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
3689 }
3690
9d5c8243
AK		 3691 tx_ring->next_to_clean = i;
3692
fc7d345d 3693 if (unlikely(count &&
9d5c8243
AK		 3694 netif_carrier_ok(netdev) &&
3695 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3696 /* Make sure that anybody stopping the queue after this
3697 * sees the new next_to_clean.
3698 */
3699 smp_mb();
661086df
PWJ		 3700 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3701 !(test_bit(__IGB_DOWN, &adapter->state))) {
3702 netif_wake_subqueue(netdev, tx_ring->queue_index);
3703 ++adapter->restart_queue;
3704 }
9d5c8243
AK		 3705 }
3706
3707 if (tx_ring->detect_tx_hung) {
3708 /* Detect a transmit hang in hardware, this serializes the
3709 * check with the clearing of time_stamp and movement of i */
3710 tx_ring->detect_tx_hung = false;
3711 if (tx_ring->buffer_info[i].time_stamp &&
3712 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3713 (adapter->tx_timeout_factor * HZ))
3714 && !(rd32(E1000_STATUS) &
3715 E1000_STATUS_TXOFF)) {
3716
9d5c8243
AK		 3717 /* detected Tx unit hang */
3718 dev_err(&adapter->pdev->dev,
3719 "Detected Tx Unit Hang\n"
2d064c06 3720 " Tx Queue <%d>\n"
9d5c8243
AK		 3721 " TDH <%x>\n"
3722 " TDT <%x>\n"
3723 " next_to_use <%x>\n"
3724 " next_to_clean <%x>\n"
9d5c8243
AK		 3725 "buffer_info[next_to_clean]\n"
3726 " time_stamp <%lx>\n"
0e014cb1 3727 " next_to_watch <%x>\n"
9d5c8243
AK		 3728 " jiffies <%lx>\n"
3729 " desc.status <%x>\n",
2d064c06 3730 tx_ring->queue_index,
9d5c8243
AK		 3731 readl(adapter->hw.hw_addr + tx_ring->head),
3732 readl(adapter->hw.hw_addr + tx_ring->tail),
3733 tx_ring->next_to_use,
3734 tx_ring->next_to_clean,
9d5c8243 3735 tx_ring->buffer_info[i].time_stamp,
0e014cb1 3736 eop,
9d5c8243 3737 jiffies,
0e014cb1 3738 eop_desc->wb.status);
661086df 3739 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3740 }
3741 }
3742 tx_ring->total_bytes += total_bytes;
3743 tx_ring->total_packets += total_packets;
e21ed353
AD		 3744 tx_ring->tx_stats.bytes += total_bytes;
3745 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3746 adapter->net_stats.tx_bytes += total_bytes;
3747 adapter->net_stats.tx_packets += total_packets;
0e014cb1 3748 return (count < tx_ring->count);
9d5c8243
AK		 3749}
3750
9d5c8243
AK		 3751/**
3752 * igb_receive_skb - helper function to handle rx indications
eebbbdba 3753 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3754 * @status: descriptor status field as written by hardware
3755 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3756 * @skb: pointer to sk_buff to be indicated to stack
3757 **/
d3352520
AD		 3758static void igb_receive_skb(struct igb_ring *ring, u8 status,
3759 union e1000_adv_rx_desc * rx_desc,
3760 struct sk_buff *skb)
3761{
3762 struct igb_adapter * adapter = ring->adapter;
3763 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3764
0c8dfc83 3765 skb_record_rx_queue(skb, ring->queue_index);
5c0999b7 3766 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
d3352520 3767 if (vlan_extracted)
5c0999b7
HX		 3768 vlan_gro_receive(&ring->napi, adapter->vlgrp,
3769 le16_to_cpu(rx_desc->wb.upper.vlan),
3770 skb);
d3352520 3771 else
5c0999b7 3772 napi_gro_receive(&ring->napi, skb);
d3352520 3773 } else {
d3352520
AD		 3774 if (vlan_extracted)
3775 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3776 le16_to_cpu(rx_desc->wb.upper.vlan));
3777 else
d3352520 3778 netif_receive_skb(skb);
d3352520 3779 }
9d5c8243
AK		 3780}
3781
3782
3783static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3784 u32 status_err, struct sk_buff *skb)
3785{
3786 skb->ip_summed = CHECKSUM_NONE;
3787
3788 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3789 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3790 return;
3791 /* TCP/UDP checksum error bit is set */
3792 if (status_err &
3793 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3794 /* let the stack verify checksum errors */
3795 adapter->hw_csum_err++;
3796 return;
3797 }
3798 /* It must be a TCP or UDP packet with a valid checksum */
3799 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3800 skb->ip_summed = CHECKSUM_UNNECESSARY;
3801
3802 adapter->hw_csum_good++;
3803}
3804
3b644cf6
MW		 3805static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3806 int *work_done, int budget)
9d5c8243 3807{
3b644cf6 3808 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3809 struct net_device *netdev = adapter->netdev;
3810 struct pci_dev *pdev = adapter->pdev;
3811 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3812 struct igb_buffer *buffer_info , *next_buffer;
3813 struct sk_buff *skb;
bf36c1a0 3814 unsigned int i;
9d5c8243
AK		 3815 u32 length, hlen, staterr;
3816 bool cleaned = false;
3817 int cleaned_count = 0;
3818 unsigned int total_bytes = 0, total_packets = 0;
3819
3820 i = rx_ring->next_to_clean;
69d3ca53 3821 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 3822 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3823 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3824
3825 while (staterr & E1000_RXD_STAT_DD) {
3826 if (*work_done >= budget)
3827 break;
3828 (*work_done)++;
9d5c8243 3829
69d3ca53
AD		 3830 skb = buffer_info->skb;
3831 prefetch(skb->data - NET_IP_ALIGN);
3832 buffer_info->skb = NULL;
3833
3834 i++;
3835 if (i == rx_ring->count)
3836 i = 0;
3837 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3838 prefetch(next_rxd);
3839 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 3840
3841 length = le16_to_cpu(rx_desc->wb.upper.length);
3842 cleaned = true;
3843 cleaned_count++;
3844
bf36c1a0
AD		 3845 if (!adapter->rx_ps_hdr_size) {
3846 pci_unmap_single(pdev, buffer_info->dma,
3847 adapter->rx_buffer_len +
3848 NET_IP_ALIGN,
3849 PCI_DMA_FROMDEVICE);
3850 skb_put(skb, length);
3851 goto send_up;
9d5c8243
AK		 3852 }
3853
69d3ca53
AD		 3854 /* HW will not DMA in data larger than the given buffer, even
3855 * if it parses the (NFS, of course) header to be larger. In
3856 * that case, it fills the header buffer and spills the rest
3857 * into the page.
3858 */
3859 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3860 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
3861 if (hlen > adapter->rx_ps_hdr_size)
3862 hlen = adapter->rx_ps_hdr_size;
3863
bf36c1a0
AD		 3864 if (!skb_shinfo(skb)->nr_frags) {
3865 pci_unmap_single(pdev, buffer_info->dma,
3866 adapter->rx_ps_hdr_size +
3867 NET_IP_ALIGN,
3868 PCI_DMA_FROMDEVICE);
3869 skb_put(skb, hlen);
3870 }
3871
3872 if (length) {
9d5c8243 3873 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3874 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3875 buffer_info->page_dma = 0;
bf36c1a0
AD		 3876
3877 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3878 buffer_info->page,
3879 buffer_info->page_offset,
3880 length);
3881
3882 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3883 (page_count(buffer_info->page) != 1))
3884 buffer_info->page = NULL;
3885 else
3886 get_page(buffer_info->page);
9d5c8243
AK		 3887
3888 skb->len += length;
3889 skb->data_len += length;
9d5c8243 3890
bf36c1a0 3891 skb->truesize += length;
9d5c8243 3892 }
9d5c8243 3893
bf36c1a0 3894 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 3895 buffer_info->skb = next_buffer->skb;
3896 buffer_info->dma = next_buffer->dma;
3897 next_buffer->skb = skb;
3898 next_buffer->dma = 0;
bf36c1a0
AD		 3899 goto next_desc;
3900 }
69d3ca53 3901send_up:
9d5c8243
AK		 3902 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3903 dev_kfree_skb_irq(skb);
3904 goto next_desc;
3905 }
9d5c8243
AK		 3906
3907 total_bytes += skb->len;
3908 total_packets++;
3909
3910 igb_rx_checksum_adv(adapter, staterr, skb);
3911
3912 skb->protocol = eth_type_trans(skb, netdev);
3913
d3352520 3914 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 3915
9d5c8243
AK		 3916next_desc:
3917 rx_desc->wb.upper.status_error = 0;
3918
3919 /* return some buffers to hardware, one at a time is too slow */
3920 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3921 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3922 cleaned_count = 0;
3923 }
3924
3925 /* use prefetched values */
3926 rx_desc = next_rxd;
3927 buffer_info = next_buffer;
9d5c8243
AK		 3928 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3929 }
bf36c1a0 3930
9d5c8243
AK		 3931 rx_ring->next_to_clean = i;
3932 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3933
3934 if (cleaned_count)
3b644cf6 3935 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3936
3937 rx_ring->total_packets += total_packets;
3938 rx_ring->total_bytes += total_bytes;
3939 rx_ring->rx_stats.packets += total_packets;
3940 rx_ring->rx_stats.bytes += total_bytes;
3941 adapter->net_stats.rx_bytes += total_bytes;
3942 adapter->net_stats.rx_packets += total_packets;
3943 return cleaned;
3944}
3945
3946
3947/**
3948 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3949 * @adapter: address of board private structure
3950 **/
3b644cf6 3951static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3952 int cleaned_count)
3953{
3b644cf6 3954 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3955 struct net_device *netdev = adapter->netdev;
3956 struct pci_dev *pdev = adapter->pdev;
3957 union e1000_adv_rx_desc *rx_desc;
3958 struct igb_buffer *buffer_info;
3959 struct sk_buff *skb;
3960 unsigned int i;
db761762 3961 int bufsz;
9d5c8243
AK		 3962
3963 i = rx_ring->next_to_use;
3964 buffer_info = &rx_ring->buffer_info[i];
3965
db761762
AD		 3966 if (adapter->rx_ps_hdr_size)
3967 bufsz = adapter->rx_ps_hdr_size;
3968 else
3969 bufsz = adapter->rx_buffer_len;
3970 bufsz += NET_IP_ALIGN;
3971
9d5c8243
AK		 3972 while (cleaned_count--) {
3973 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3974
bf36c1a0 3975 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 3976 if (!buffer_info->page) {
bf36c1a0
AD		 3977 buffer_info->page = alloc_page(GFP_ATOMIC);
3978 if (!buffer_info->page) {
3979 adapter->alloc_rx_buff_failed++;
3980 goto no_buffers;
3981 }
3982 buffer_info->page_offset = 0;
3983 } else {
3984 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 3985 }
3986 buffer_info->page_dma =
db761762 3987 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 3988 buffer_info->page_offset,
3989 PAGE_SIZE / 2,
9d5c8243
AK		 3990 PCI_DMA_FROMDEVICE);
3991 }
3992
3993 if (!buffer_info->skb) {
9d5c8243 3994 skb = netdev_alloc_skb(netdev, bufsz);
9d5c8243
AK		 3995 if (!skb) {
3996 adapter->alloc_rx_buff_failed++;
3997 goto no_buffers;
3998 }
3999
4000 /* Make buffer alignment 2 beyond a 16 byte boundary
4001 * this will result in a 16 byte aligned IP header after
4002 * the 14 byte MAC header is removed
4003 */
4004 skb_reserve(skb, NET_IP_ALIGN);
4005
4006 buffer_info->skb = skb;
4007 buffer_info->dma = pci_map_single(pdev, skb->data,
4008 bufsz,
4009 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4010 }
4011 /* Refresh the desc even if buffer_addrs didn't change because
4012 * each write-back erases this info. */
4013 if (adapter->rx_ps_hdr_size) {
4014 rx_desc->read.pkt_addr =
4015 cpu_to_le64(buffer_info->page_dma);
4016 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4017 } else {
4018 rx_desc->read.pkt_addr =
4019 cpu_to_le64(buffer_info->dma);
4020 rx_desc->read.hdr_addr = 0;
4021 }
4022
4023 i++;
4024 if (i == rx_ring->count)
4025 i = 0;
4026 buffer_info = &rx_ring->buffer_info[i];
4027 }
4028
4029no_buffers:
4030 if (rx_ring->next_to_use != i) {
4031 rx_ring->next_to_use = i;
4032 if (i == 0)
4033 i = (rx_ring->count - 1);
4034 else
4035 i--;
4036
4037 /* Force memory writes to complete before letting h/w
4038 * know there are new descriptors to fetch. (Only
4039 * applicable for weak-ordered memory model archs,
4040 * such as IA-64). */
4041 wmb();
4042 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4043 }
4044}
4045
4046/**
4047 * igb_mii_ioctl -
4048 * @netdev:
4049 * @ifreq:
4050 * @cmd:
4051 **/
4052static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4053{
4054 struct igb_adapter *adapter = netdev_priv(netdev);
4055 struct mii_ioctl_data *data = if_mii(ifr);
4056
4057 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4058 return -EOPNOTSUPP;
4059
4060 switch (cmd) {
4061 case SIOCGMIIPHY:
4062 data->phy_id = adapter->hw.phy.addr;
4063 break;
4064 case SIOCGMIIREG:
4065 if (!capable(CAP_NET_ADMIN))
4066 return -EPERM;
f5f4cf08
AD		 4067 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4068 &data->val_out))
9d5c8243
AK		 4069 return -EIO;
4070 break;
4071 case SIOCSMIIREG:
4072 default:
4073 return -EOPNOTSUPP;
4074 }
4075 return 0;
4076}
4077
4078/**
4079 * igb_ioctl -
4080 * @netdev:
4081 * @ifreq:
4082 * @cmd:
4083 **/
4084static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4085{
4086 switch (cmd) {
4087 case SIOCGMIIPHY:
4088 case SIOCGMIIREG:
4089 case SIOCSMIIREG:
4090 return igb_mii_ioctl(netdev, ifr, cmd);
4091 default:
4092 return -EOPNOTSUPP;
4093 }
4094}
4095
4096static void igb_vlan_rx_register(struct net_device *netdev,
4097 struct vlan_group *grp)
4098{
4099 struct igb_adapter *adapter = netdev_priv(netdev);
4100 struct e1000_hw *hw = &adapter->hw;
4101 u32 ctrl, rctl;
4102
4103 igb_irq_disable(adapter);
4104 adapter->vlgrp = grp;
4105
4106 if (grp) {
4107 /* enable VLAN tag insert/strip */
4108 ctrl = rd32(E1000_CTRL);
4109 ctrl |= E1000_CTRL_VME;
4110 wr32(E1000_CTRL, ctrl);
4111
4112 /* enable VLAN receive filtering */
4113 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4114 rctl &= ~E1000_RCTL_CFIEN;
4115 wr32(E1000_RCTL, rctl);
4116 igb_update_mng_vlan(adapter);
4117 wr32(E1000_RLPML,
4118 adapter->max_frame_size + VLAN_TAG_SIZE);
4119 } else {
4120 /* disable VLAN tag insert/strip */
4121 ctrl = rd32(E1000_CTRL);
4122 ctrl &= ~E1000_CTRL_VME;
4123 wr32(E1000_CTRL, ctrl);
4124
9d5c8243
AK		 4125 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4126 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4127 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4128 }
4129 wr32(E1000_RLPML,
4130 adapter->max_frame_size);
4131 }
4132
4133 if (!test_bit(__IGB_DOWN, &adapter->state))
4134 igb_irq_enable(adapter);
4135}
4136
4137static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4138{
4139 struct igb_adapter *adapter = netdev_priv(netdev);
4140 struct e1000_hw *hw = &adapter->hw;
4141 u32 vfta, index;
4142
4143 if ((adapter->hw.mng_cookie.status &
4144 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4145 (vid == adapter->mng_vlan_id))
4146 return;
4147 /* add VID to filter table */
4148 index = (vid >> 5) & 0x7F;
4149 vfta = array_rd32(E1000_VFTA, index);
4150 vfta |= (1 << (vid & 0x1F));
4151 igb_write_vfta(&adapter->hw, index, vfta);
4152}
4153
4154static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4155{
4156 struct igb_adapter *adapter = netdev_priv(netdev);
4157 struct e1000_hw *hw = &adapter->hw;
4158 u32 vfta, index;
4159
4160 igb_irq_disable(adapter);
4161 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4162
4163 if (!test_bit(__IGB_DOWN, &adapter->state))
4164 igb_irq_enable(adapter);
4165
4166 if ((adapter->hw.mng_cookie.status &
4167 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4168 (vid == adapter->mng_vlan_id)) {
4169 /* release control to f/w */
4170 igb_release_hw_control(adapter);
4171 return;
4172 }
4173
4174 /* remove VID from filter table */
4175 index = (vid >> 5) & 0x7F;
4176 vfta = array_rd32(E1000_VFTA, index);
4177 vfta &= ~(1 << (vid & 0x1F));
4178 igb_write_vfta(&adapter->hw, index, vfta);
4179}
4180
4181static void igb_restore_vlan(struct igb_adapter *adapter)
4182{
4183 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4184
4185 if (adapter->vlgrp) {
4186 u16 vid;
4187 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4188 if (!vlan_group_get_device(adapter->vlgrp, vid))
4189 continue;
4190 igb_vlan_rx_add_vid(adapter->netdev, vid);
4191 }
4192 }
4193}
4194
4195int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4196{
4197 struct e1000_mac_info *mac = &adapter->hw.mac;
4198
4199 mac->autoneg = 0;
4200
4201 /* Fiber NICs only allow 1000 gbps Full duplex */
4202 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4203 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4204 dev_err(&adapter->pdev->dev,
4205 "Unsupported Speed/Duplex configuration\n");
4206 return -EINVAL;
4207 }
4208
4209 switch (spddplx) {
4210 case SPEED_10 + DUPLEX_HALF:
4211 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4212 break;
4213 case SPEED_10 + DUPLEX_FULL:
4214 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4215 break;
4216 case SPEED_100 + DUPLEX_HALF:
4217 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4218 break;
4219 case SPEED_100 + DUPLEX_FULL:
4220 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4221 break;
4222 case SPEED_1000 + DUPLEX_FULL:
4223 mac->autoneg = 1;
4224 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4225 break;
4226 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4227 default:
4228 dev_err(&adapter->pdev->dev,
4229 "Unsupported Speed/Duplex configuration\n");
4230 return -EINVAL;
4231 }
4232 return 0;
4233}
4234
4235
4236static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4237{
4238 struct net_device *netdev = pci_get_drvdata(pdev);
4239 struct igb_adapter *adapter = netdev_priv(netdev);
4240 struct e1000_hw *hw = &adapter->hw;
2d064c06 4241 u32 ctrl, rctl, status;
9d5c8243
AK		 4242 u32 wufc = adapter->wol;
4243#ifdef CONFIG_PM
4244 int retval = 0;
4245#endif
4246
4247 netif_device_detach(netdev);
4248
a88f10ec
AD		 4249 if (netif_running(netdev))
4250 igb_close(netdev);
4251
4252 igb_reset_interrupt_capability(adapter);
4253
4254 igb_free_queues(adapter);
9d5c8243
AK		 4255
4256#ifdef CONFIG_PM
4257 retval = pci_save_state(pdev);
4258 if (retval)
4259 return retval;
4260#endif
4261
4262 status = rd32(E1000_STATUS);
4263 if (status & E1000_STATUS_LU)
4264 wufc &= ~E1000_WUFC_LNKC;
4265
4266 if (wufc) {
4267 igb_setup_rctl(adapter);
4268 igb_set_multi(netdev);
4269
4270 /* turn on all-multi mode if wake on multicast is enabled */
4271 if (wufc & E1000_WUFC_MC) {
4272 rctl = rd32(E1000_RCTL);
4273 rctl |= E1000_RCTL_MPE;
4274 wr32(E1000_RCTL, rctl);
4275 }
4276
4277 ctrl = rd32(E1000_CTRL);
4278 /* advertise wake from D3Cold */
4279 #define E1000_CTRL_ADVD3WUC 0x00100000
4280 /* phy power management enable */
4281 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4282 ctrl |= E1000_CTRL_ADVD3WUC;
4283 wr32(E1000_CTRL, ctrl);
4284
9d5c8243
AK		 4285 /* Allow time for pending master requests to run */
4286 igb_disable_pcie_master(&adapter->hw);
4287
4288 wr32(E1000_WUC, E1000_WUC_PME_EN);
4289 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4290 } else {
4291 wr32(E1000_WUC, 0);
4292 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4293 }
4294
2d064c06
AD		 4295 /* make sure adapter isn't asleep if manageability/wol is enabled */
4296 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4297 pci_enable_wake(pdev, PCI_D3hot, 1);
4298 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4299 } else {
4300 igb_shutdown_fiber_serdes_link_82575(hw);
4301 pci_enable_wake(pdev, PCI_D3hot, 0);
4302 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4303 }
4304
4305 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4306 * would have already happened in close and is redundant. */
4307 igb_release_hw_control(adapter);
4308
4309 pci_disable_device(pdev);
4310
4311 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4312
4313 return 0;
4314}
4315
4316#ifdef CONFIG_PM
4317static int igb_resume(struct pci_dev *pdev)
4318{
4319 struct net_device *netdev = pci_get_drvdata(pdev);
4320 struct igb_adapter *adapter = netdev_priv(netdev);
4321 struct e1000_hw *hw = &adapter->hw;
4322 u32 err;
4323
4324 pci_set_power_state(pdev, PCI_D0);
4325 pci_restore_state(pdev);
42bfd33a 4326
aed5dec3 4327 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4328 if (err) {
4329 dev_err(&pdev->dev,
4330 "igb: Cannot enable PCI device from suspend\n");
4331 return err;
4332 }
4333 pci_set_master(pdev);
4334
4335 pci_enable_wake(pdev, PCI_D3hot, 0);
4336 pci_enable_wake(pdev, PCI_D3cold, 0);
4337
a88f10ec
AD		 4338 igb_set_interrupt_capability(adapter);
4339
4340 if (igb_alloc_queues(adapter)) {
4341 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4342 return -ENOMEM;
9d5c8243
AK		 4343 }
4344
4345 /* e1000_power_up_phy(adapter); */
4346
4347 igb_reset(adapter);
4348 wr32(E1000_WUS, ~0);
4349
a88f10ec
AD		 4350 if (netif_running(netdev)) {
4351 err = igb_open(netdev);
4352 if (err)
4353 return err;
4354 }
9d5c8243
AK		 4355
4356 netif_device_attach(netdev);
4357
4358 /* let the f/w know that the h/w is now under the control of the
4359 * driver. */
4360 igb_get_hw_control(adapter);
4361
4362 return 0;
4363}
4364#endif
4365
4366static void igb_shutdown(struct pci_dev *pdev)
4367{
4368 igb_suspend(pdev, PMSG_SUSPEND);
4369}
4370
4371#ifdef CONFIG_NET_POLL_CONTROLLER
4372/*
4373 * Polling 'interrupt' - used by things like netconsole to send skbs
4374 * without having to re-enable interrupts. It's not called while
4375 * the interrupt routine is executing.
4376 */
4377static void igb_netpoll(struct net_device *netdev)
4378{
4379 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 4380 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4381 int i;
9d5c8243 4382
eebbbdba
AD		 4383 if (!adapter->msix_entries) {
4384 igb_irq_disable(adapter);
4385 napi_schedule(&adapter->rx_ring[0].napi);
4386 return;
4387 }
9d5c8243 4388
eebbbdba
AD		 4389 for (i = 0; i < adapter->num_tx_queues; i++) {
4390 struct igb_ring *tx_ring = &adapter->tx_ring[i];
4391 wr32(E1000_EIMC, tx_ring->eims_value);
4392 igb_clean_tx_irq(tx_ring);
4393 wr32(E1000_EIMS, tx_ring->eims_value);
4394 }
9d5c8243 4395
eebbbdba
AD		 4396 for (i = 0; i < adapter->num_rx_queues; i++) {
4397 struct igb_ring *rx_ring = &adapter->rx_ring[i];
4398 wr32(E1000_EIMC, rx_ring->eims_value);
4399 napi_schedule(&rx_ring->napi);
4400 }
9d5c8243
AK		 4401}
4402#endif /* CONFIG_NET_POLL_CONTROLLER */
4403
4404/**
4405 * igb_io_error_detected - called when PCI error is detected
4406 * @pdev: Pointer to PCI device
4407 * @state: The current pci connection state
4408 *
4409 * This function is called after a PCI bus error affecting
4410 * this device has been detected.
4411 */
4412static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4413 pci_channel_state_t state)
4414{
4415 struct net_device *netdev = pci_get_drvdata(pdev);
4416 struct igb_adapter *adapter = netdev_priv(netdev);
4417
4418 netif_device_detach(netdev);
4419
4420 if (netif_running(netdev))
4421 igb_down(adapter);
4422 pci_disable_device(pdev);
4423
4424 /* Request a slot slot reset. */
4425 return PCI_ERS_RESULT_NEED_RESET;
4426}
4427
4428/**
4429 * igb_io_slot_reset - called after the pci bus has been reset.
4430 * @pdev: Pointer to PCI device
4431 *
4432 * Restart the card from scratch, as if from a cold-boot. Implementation
4433 * resembles the first-half of the igb_resume routine.
4434 */
4435static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4436{
4437 struct net_device *netdev = pci_get_drvdata(pdev);
4438 struct igb_adapter *adapter = netdev_priv(netdev);
4439 struct e1000_hw *hw = &adapter->hw;
40a914fa 4440 pci_ers_result_t result;
42bfd33a 4441 int err;
9d5c8243 4442
aed5dec3 4443 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 4444 dev_err(&pdev->dev,
4445 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 4446 result = PCI_ERS_RESULT_DISCONNECT;
4447 } else {
4448 pci_set_master(pdev);
4449 pci_restore_state(pdev);
9d5c8243 4450
40a914fa
AD		 4451 pci_enable_wake(pdev, PCI_D3hot, 0);
4452 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 4453
40a914fa
AD		 4454 igb_reset(adapter);
4455 wr32(E1000_WUS, ~0);
4456 result = PCI_ERS_RESULT_RECOVERED;
4457 }
9d5c8243 4458
ea943d41
JK		 4459 err = pci_cleanup_aer_uncorrect_error_status(pdev);
4460 if (err) {
4461 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
4462 "failed 0x%0x\n", err);
4463 /* non-fatal, continue */
4464 }
40a914fa
AD		 4465
4466 return result;
9d5c8243
AK		 4467}
4468
4469/**
4470 * igb_io_resume - called when traffic can start flowing again.
4471 * @pdev: Pointer to PCI device
4472 *
4473 * This callback is called when the error recovery driver tells us that
4474 * its OK to resume normal operation. Implementation resembles the
4475 * second-half of the igb_resume routine.
4476 */
4477static void igb_io_resume(struct pci_dev *pdev)
4478{
4479 struct net_device *netdev = pci_get_drvdata(pdev);
4480 struct igb_adapter *adapter = netdev_priv(netdev);
4481
9d5c8243
AK		 4482 if (netif_running(netdev)) {
4483 if (igb_up(adapter)) {
4484 dev_err(&pdev->dev, "igb_up failed after reset\n");
4485 return;
4486 }
4487 }
4488
4489 netif_device_attach(netdev);
4490
4491 /* let the f/w know that the h/w is now under the control of the
4492 * driver. */
4493 igb_get_hw_control(adapter);
9d5c8243
AK		 4494}
4495
4496/* igb_main.c */
Linux 6.x block layer and io_uring tree(s)