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igb: eliminate hw from the hw_dbg macro arguments
[linux-block.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
41#include <linux/delay.h>
42#include <linux/interrupt.h>
43#include <linux/if_ether.h>
44
45#include "igb.h"
46
47#define DRV_VERSION "1.0.8-k2"
48char igb_driver_name[] = "igb";
49char igb_driver_version[] = DRV_VERSION;
50static const char igb_driver_string[] =
51 "Intel(R) Gigabit Ethernet Network Driver";
52static const char igb_copyright[] = "Copyright (c) 2007 Intel Corporation.";
53
54
55static const struct e1000_info *igb_info_tbl[] = {
56 [board_82575] = &e1000_82575_info,
57};
58
59static struct pci_device_id igb_pci_tbl[] = {
60 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
63 /* required last entry */
64 {0, }
65};
66
67MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
68
69void igb_reset(struct igb_adapter *);
70static int igb_setup_all_tx_resources(struct igb_adapter *);
71static int igb_setup_all_rx_resources(struct igb_adapter *);
72static void igb_free_all_tx_resources(struct igb_adapter *);
73static void igb_free_all_rx_resources(struct igb_adapter *);
3b644cf6
MW		 74static void igb_free_tx_resources(struct igb_ring *);
75static void igb_free_rx_resources(struct igb_ring *);
9d5c8243
AK		 76void igb_update_stats(struct igb_adapter *);
77static int igb_probe(struct pci_dev *, const struct pci_device_id *);
78static void __devexit igb_remove(struct pci_dev *pdev);
79static int igb_sw_init(struct igb_adapter *);
80static int igb_open(struct net_device *);
81static int igb_close(struct net_device *);
82static void igb_configure_tx(struct igb_adapter *);
83static void igb_configure_rx(struct igb_adapter *);
84static void igb_setup_rctl(struct igb_adapter *);
85static void igb_clean_all_tx_rings(struct igb_adapter *);
86static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 87static void igb_clean_tx_ring(struct igb_ring *);
88static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 89static void igb_set_multi(struct net_device *);
90static void igb_update_phy_info(unsigned long);
91static void igb_watchdog(unsigned long);
92static void igb_watchdog_task(struct work_struct *);
93static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
94 struct igb_ring *);
95static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
96static struct net_device_stats *igb_get_stats(struct net_device *);
97static int igb_change_mtu(struct net_device *, int);
98static int igb_set_mac(struct net_device *, void *);
99static irqreturn_t igb_intr(int irq, void *);
100static irqreturn_t igb_intr_msi(int irq, void *);
101static irqreturn_t igb_msix_other(int irq, void *);
102static irqreturn_t igb_msix_rx(int irq, void *);
103static irqreturn_t igb_msix_tx(int irq, void *);
104static int igb_clean_rx_ring_msix(struct napi_struct *, int);
3b644cf6 105static bool igb_clean_tx_irq(struct igb_ring *);
9d5c8243 106static int igb_clean(struct napi_struct *, int);
3b644cf6
MW		 107static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
108static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 109static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
110static void igb_tx_timeout(struct net_device *);
111static void igb_reset_task(struct work_struct *);
112static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
113static void igb_vlan_rx_add_vid(struct net_device *, u16);
114static void igb_vlan_rx_kill_vid(struct net_device *, u16);
115static void igb_restore_vlan(struct igb_adapter *);
116
117static int igb_suspend(struct pci_dev *, pm_message_t);
118#ifdef CONFIG_PM
119static int igb_resume(struct pci_dev *);
120#endif
121static void igb_shutdown(struct pci_dev *);
122
123#ifdef CONFIG_NET_POLL_CONTROLLER
124/* for netdump / net console */
125static void igb_netpoll(struct net_device *);
126#endif
127
128static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
129 pci_channel_state_t);
130static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
131static void igb_io_resume(struct pci_dev *);
132
133static struct pci_error_handlers igb_err_handler = {
134 .error_detected = igb_io_error_detected,
135 .slot_reset = igb_io_slot_reset,
136 .resume = igb_io_resume,
137};
138
139
140static struct pci_driver igb_driver = {
141 .name = igb_driver_name,
142 .id_table = igb_pci_tbl,
143 .probe = igb_probe,
144 .remove = __devexit_p(igb_remove),
145#ifdef CONFIG_PM
146 /* Power Managment Hooks */
147 .suspend = igb_suspend,
148 .resume = igb_resume,
149#endif
150 .shutdown = igb_shutdown,
151 .err_handler = &igb_err_handler
152};
153
154MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
155MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
156MODULE_LICENSE("GPL");
157MODULE_VERSION(DRV_VERSION);
158
159#ifdef DEBUG
160/**
161 * igb_get_hw_dev_name - return device name string
162 * used by hardware layer to print debugging information
163 **/
164char *igb_get_hw_dev_name(struct e1000_hw *hw)
165{
166 struct igb_adapter *adapter = hw->back;
167 return adapter->netdev->name;
168}
169#endif
170
171/**
172 * igb_init_module - Driver Registration Routine
173 *
174 * igb_init_module is the first routine called when the driver is
175 * loaded. All it does is register with the PCI subsystem.
176 **/
177static int __init igb_init_module(void)
178{
179 int ret;
180 printk(KERN_INFO "%s - version %s\n",
181 igb_driver_string, igb_driver_version);
182
183 printk(KERN_INFO "%s\n", igb_copyright);
184
185 ret = pci_register_driver(&igb_driver);
186 return ret;
187}
188
189module_init(igb_init_module);
190
191/**
192 * igb_exit_module - Driver Exit Cleanup Routine
193 *
194 * igb_exit_module is called just before the driver is removed
195 * from memory.
196 **/
197static void __exit igb_exit_module(void)
198{
199 pci_unregister_driver(&igb_driver);
200}
201
202module_exit(igb_exit_module);
203
204/**
205 * igb_alloc_queues - Allocate memory for all rings
206 * @adapter: board private structure to initialize
207 *
208 * We allocate one ring per queue at run-time since we don't know the
209 * number of queues at compile-time.
210 **/
211static int igb_alloc_queues(struct igb_adapter *adapter)
212{
213 int i;
214
215 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
216 sizeof(struct igb_ring), GFP_KERNEL);
217 if (!adapter->tx_ring)
218 return -ENOMEM;
219
220 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
221 sizeof(struct igb_ring), GFP_KERNEL);
222 if (!adapter->rx_ring) {
223 kfree(adapter->tx_ring);
224 return -ENOMEM;
225 }
226
227 for (i = 0; i < adapter->num_rx_queues; i++) {
228 struct igb_ring *ring = &(adapter->rx_ring[i]);
229 ring->adapter = adapter;
230 ring->itr_register = E1000_ITR;
231
232 if (!ring->napi.poll)
233 netif_napi_add(adapter->netdev, &ring->napi, igb_clean,
234 adapter->napi.weight /
235 adapter->num_rx_queues);
236 }
237 return 0;
238}
239
240#define IGB_N0_QUEUE -1
241static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
242 int tx_queue, int msix_vector)
243{
244 u32 msixbm = 0;
245 struct e1000_hw *hw = &adapter->hw;
246 /* The 82575 assigns vectors using a bitmask, which matches the
247 bitmask for the EICR/EIMS/EIMC registers. To assign one
248 or more queues to a vector, we write the appropriate bits
249 into the MSIXBM register for that vector. */
250 if (rx_queue > IGB_N0_QUEUE) {
251 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
252 adapter->rx_ring[rx_queue].eims_value = msixbm;
253 }
254 if (tx_queue > IGB_N0_QUEUE) {
255 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
256 adapter->tx_ring[tx_queue].eims_value =
257 E1000_EICR_TX_QUEUE0 << tx_queue;
258 }
259 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
260}
261
262/**
263 * igb_configure_msix - Configure MSI-X hardware
264 *
265 * igb_configure_msix sets up the hardware to properly
266 * generate MSI-X interrupts.
267 **/
268static void igb_configure_msix(struct igb_adapter *adapter)
269{
270 u32 tmp;
271 int i, vector = 0;
272 struct e1000_hw *hw = &adapter->hw;
273
274 adapter->eims_enable_mask = 0;
275
276 for (i = 0; i < adapter->num_tx_queues; i++) {
277 struct igb_ring *tx_ring = &adapter->tx_ring[i];
278 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
279 adapter->eims_enable_mask |= tx_ring->eims_value;
280 if (tx_ring->itr_val)
281 writel(1000000000 / (tx_ring->itr_val * 256),
282 hw->hw_addr + tx_ring->itr_register);
283 else
284 writel(1, hw->hw_addr + tx_ring->itr_register);
285 }
286
287 for (i = 0; i < adapter->num_rx_queues; i++) {
288 struct igb_ring *rx_ring = &adapter->rx_ring[i];
289 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
290 adapter->eims_enable_mask |= rx_ring->eims_value;
291 if (rx_ring->itr_val)
292 writel(1000000000 / (rx_ring->itr_val * 256),
293 hw->hw_addr + rx_ring->itr_register);
294 else
295 writel(1, hw->hw_addr + rx_ring->itr_register);
296 }
297
298
299 /* set vector for other causes, i.e. link changes */
300 array_wr32(E1000_MSIXBM(0), vector++,
301 E1000_EIMS_OTHER);
302
303 /* disable IAM for ICR interrupt bits */
304 wr32(E1000_IAM, 0);
305
306 tmp = rd32(E1000_CTRL_EXT);
307 /* enable MSI-X PBA support*/
308 tmp |= E1000_CTRL_EXT_PBA_CLR;
309
310 /* Auto-Mask interrupts upon ICR read. */
311 tmp |= E1000_CTRL_EXT_EIAME;
312 tmp |= E1000_CTRL_EXT_IRCA;
313
314 wr32(E1000_CTRL_EXT, tmp);
315 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
316
317 wrfl();
318}
319
320/**
321 * igb_request_msix - Initialize MSI-X interrupts
322 *
323 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
324 * kernel.
325 **/
326static int igb_request_msix(struct igb_adapter *adapter)
327{
328 struct net_device *netdev = adapter->netdev;
329 int i, err = 0, vector = 0;
330
331 vector = 0;
332
333 for (i = 0; i < adapter->num_tx_queues; i++) {
334 struct igb_ring *ring = &(adapter->tx_ring[i]);
335 sprintf(ring->name, "%s-tx%d", netdev->name, i);
336 err = request_irq(adapter->msix_entries[vector].vector,
337 &igb_msix_tx, 0, ring->name,
338 &(adapter->tx_ring[i]));
339 if (err)
340 goto out;
341 ring->itr_register = E1000_EITR(0) + (vector << 2);
342 ring->itr_val = adapter->itr;
343 vector++;
344 }
345 for (i = 0; i < adapter->num_rx_queues; i++) {
346 struct igb_ring *ring = &(adapter->rx_ring[i]);
347 if (strlen(netdev->name) < (IFNAMSIZ - 5))
348 sprintf(ring->name, "%s-rx%d", netdev->name, i);
349 else
350 memcpy(ring->name, netdev->name, IFNAMSIZ);
351 err = request_irq(adapter->msix_entries[vector].vector,
352 &igb_msix_rx, 0, ring->name,
353 &(adapter->rx_ring[i]));
354 if (err)
355 goto out;
356 ring->itr_register = E1000_EITR(0) + (vector << 2);
357 ring->itr_val = adapter->itr;
358 vector++;
359 }
360
361 err = request_irq(adapter->msix_entries[vector].vector,
362 &igb_msix_other, 0, netdev->name, netdev);
363 if (err)
364 goto out;
365
366 adapter->napi.poll = igb_clean_rx_ring_msix;
367 for (i = 0; i < adapter->num_rx_queues; i++)
368 adapter->rx_ring[i].napi.poll = adapter->napi.poll;
369 igb_configure_msix(adapter);
370 return 0;
371out:
372 return err;
373}
374
375static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
376{
377 if (adapter->msix_entries) {
378 pci_disable_msix(adapter->pdev);
379 kfree(adapter->msix_entries);
380 adapter->msix_entries = NULL;
381 } else if (adapter->msi_enabled)
382 pci_disable_msi(adapter->pdev);
383 return;
384}
385
386
387/**
388 * igb_set_interrupt_capability - set MSI or MSI-X if supported
389 *
390 * Attempt to configure interrupts using the best available
391 * capabilities of the hardware and kernel.
392 **/
393static void igb_set_interrupt_capability(struct igb_adapter *adapter)
394{
395 int err;
396 int numvecs, i;
397
398 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
399 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
400 GFP_KERNEL);
401 if (!adapter->msix_entries)
402 goto msi_only;
403
404 for (i = 0; i < numvecs; i++)
405 adapter->msix_entries[i].entry = i;
406
407 err = pci_enable_msix(adapter->pdev,
408 adapter->msix_entries,
409 numvecs);
410 if (err == 0)
411 return;
412
413 igb_reset_interrupt_capability(adapter);
414
415 /* If we can't do MSI-X, try MSI */
416msi_only:
417 adapter->num_rx_queues = 1;
418 if (!pci_enable_msi(adapter->pdev))
419 adapter->msi_enabled = 1;
420 return;
421}
422
423/**
424 * igb_request_irq - initialize interrupts
425 *
426 * Attempts to configure interrupts using the best available
427 * capabilities of the hardware and kernel.
428 **/
429static int igb_request_irq(struct igb_adapter *adapter)
430{
431 struct net_device *netdev = adapter->netdev;
432 struct e1000_hw *hw = &adapter->hw;
433 int err = 0;
434
435 if (adapter->msix_entries) {
436 err = igb_request_msix(adapter);
437 if (!err) {
9d5c8243 438 /* enable IAM, auto-mask,
6cb5e577 439 * DO NOT USE EIAM or IAM in legacy mode */
9d5c8243
AK		 440 wr32(E1000_IAM, IMS_ENABLE_MASK);
441 goto request_done;
442 }
443 /* fall back to MSI */
444 igb_reset_interrupt_capability(adapter);
445 if (!pci_enable_msi(adapter->pdev))
446 adapter->msi_enabled = 1;
447 igb_free_all_tx_resources(adapter);
448 igb_free_all_rx_resources(adapter);
449 adapter->num_rx_queues = 1;
450 igb_alloc_queues(adapter);
451 }
452 if (adapter->msi_enabled) {
453 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
454 netdev->name, netdev);
455 if (!err)
456 goto request_done;
457 /* fall back to legacy interrupts */
458 igb_reset_interrupt_capability(adapter);
459 adapter->msi_enabled = 0;
460 }
461
462 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
463 netdev->name, netdev);
464
6cb5e577 465 if (err)
9d5c8243
AK		 466 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
467 err);
9d5c8243
AK		 468
469request_done:
470 return err;
471}
472
473static void igb_free_irq(struct igb_adapter *adapter)
474{
475 struct net_device *netdev = adapter->netdev;
476
477 if (adapter->msix_entries) {
478 int vector = 0, i;
479
480 for (i = 0; i < adapter->num_tx_queues; i++)
481 free_irq(adapter->msix_entries[vector++].vector,
482 &(adapter->tx_ring[i]));
483 for (i = 0; i < adapter->num_rx_queues; i++)
484 free_irq(adapter->msix_entries[vector++].vector,
485 &(adapter->rx_ring[i]));
486
487 free_irq(adapter->msix_entries[vector++].vector, netdev);
488 return;
489 }
490
491 free_irq(adapter->pdev->irq, netdev);
492}
493
494/**
495 * igb_irq_disable - Mask off interrupt generation on the NIC
496 * @adapter: board private structure
497 **/
498static void igb_irq_disable(struct igb_adapter *adapter)
499{
500 struct e1000_hw *hw = &adapter->hw;
501
502 if (adapter->msix_entries) {
503 wr32(E1000_EIMC, ~0);
504 wr32(E1000_EIAC, 0);
505 }
506 wr32(E1000_IMC, ~0);
507 wrfl();
508 synchronize_irq(adapter->pdev->irq);
509}
510
511/**
512 * igb_irq_enable - Enable default interrupt generation settings
513 * @adapter: board private structure
514 **/
515static void igb_irq_enable(struct igb_adapter *adapter)
516{
517 struct e1000_hw *hw = &adapter->hw;
518
519 if (adapter->msix_entries) {
520 wr32(E1000_EIMS,
521 adapter->eims_enable_mask);
522 wr32(E1000_EIAC,
523 adapter->eims_enable_mask);
524 wr32(E1000_IMS, E1000_IMS_LSC);
525 } else
526 wr32(E1000_IMS, IMS_ENABLE_MASK);
527}
528
529static void igb_update_mng_vlan(struct igb_adapter *adapter)
530{
531 struct net_device *netdev = adapter->netdev;
532 u16 vid = adapter->hw.mng_cookie.vlan_id;
533 u16 old_vid = adapter->mng_vlan_id;
534 if (adapter->vlgrp) {
535 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
536 if (adapter->hw.mng_cookie.status &
537 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
538 igb_vlan_rx_add_vid(netdev, vid);
539 adapter->mng_vlan_id = vid;
540 } else
541 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
542
543 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
544 (vid != old_vid) &&
545 !vlan_group_get_device(adapter->vlgrp, old_vid))
546 igb_vlan_rx_kill_vid(netdev, old_vid);
547 } else
548 adapter->mng_vlan_id = vid;
549 }
550}
551
552/**
553 * igb_release_hw_control - release control of the h/w to f/w
554 * @adapter: address of board private structure
555 *
556 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
557 * For ASF and Pass Through versions of f/w this means that the
558 * driver is no longer loaded.
559 *
560 **/
561static void igb_release_hw_control(struct igb_adapter *adapter)
562{
563 struct e1000_hw *hw = &adapter->hw;
564 u32 ctrl_ext;
565
566 /* Let firmware take over control of h/w */
567 ctrl_ext = rd32(E1000_CTRL_EXT);
568 wr32(E1000_CTRL_EXT,
569 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
570}
571
572
573/**
574 * igb_get_hw_control - get control of the h/w from f/w
575 * @adapter: address of board private structure
576 *
577 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
578 * For ASF and Pass Through versions of f/w this means that
579 * the driver is loaded.
580 *
581 **/
582static void igb_get_hw_control(struct igb_adapter *adapter)
583{
584 struct e1000_hw *hw = &adapter->hw;
585 u32 ctrl_ext;
586
587 /* Let firmware know the driver has taken over */
588 ctrl_ext = rd32(E1000_CTRL_EXT);
589 wr32(E1000_CTRL_EXT,
590 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
591}
592
593static void igb_init_manageability(struct igb_adapter *adapter)
594{
595 struct e1000_hw *hw = &adapter->hw;
596
597 if (adapter->en_mng_pt) {
598 u32 manc2h = rd32(E1000_MANC2H);
599 u32 manc = rd32(E1000_MANC);
600
9d5c8243
AK		 601 /* enable receiving management packets to the host */
602 /* this will probably generate destination unreachable messages
603 * from the host OS, but the packets will be handled on SMBUS */
604 manc |= E1000_MANC_EN_MNG2HOST;
605#define E1000_MNG2HOST_PORT_623 (1 << 5)
606#define E1000_MNG2HOST_PORT_664 (1 << 6)
607 manc2h |= E1000_MNG2HOST_PORT_623;
608 manc2h |= E1000_MNG2HOST_PORT_664;
609 wr32(E1000_MANC2H, manc2h);
610
611 wr32(E1000_MANC, manc);
612 }
613}
614
9d5c8243
AK		 615/**
616 * igb_configure - configure the hardware for RX and TX
617 * @adapter: private board structure
618 **/
619static void igb_configure(struct igb_adapter *adapter)
620{
621 struct net_device *netdev = adapter->netdev;
622 int i;
623
624 igb_get_hw_control(adapter);
625 igb_set_multi(netdev);
626
627 igb_restore_vlan(adapter);
628 igb_init_manageability(adapter);
629
630 igb_configure_tx(adapter);
631 igb_setup_rctl(adapter);
632 igb_configure_rx(adapter);
633 /* call IGB_DESC_UNUSED which always leaves
634 * at least 1 descriptor unused to make sure
635 * next_to_use != next_to_clean */
636 for (i = 0; i < adapter->num_rx_queues; i++) {
637 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 638 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 639 }
640
641
642 adapter->tx_queue_len = netdev->tx_queue_len;
643}
644
645
646/**
647 * igb_up - Open the interface and prepare it to handle traffic
648 * @adapter: board private structure
649 **/
650
651int igb_up(struct igb_adapter *adapter)
652{
653 struct e1000_hw *hw = &adapter->hw;
654 int i;
655
656 /* hardware has been reset, we need to reload some things */
657 igb_configure(adapter);
658
659 clear_bit(__IGB_DOWN, &adapter->state);
660
661 napi_enable(&adapter->napi);
662
663 if (adapter->msix_entries) {
664 for (i = 0; i < adapter->num_rx_queues; i++)
665 napi_enable(&adapter->rx_ring[i].napi);
666 igb_configure_msix(adapter);
667 }
668
669 /* Clear any pending interrupts. */
670 rd32(E1000_ICR);
671 igb_irq_enable(adapter);
672
673 /* Fire a link change interrupt to start the watchdog. */
674 wr32(E1000_ICS, E1000_ICS_LSC);
675 return 0;
676}
677
678void igb_down(struct igb_adapter *adapter)
679{
680 struct e1000_hw *hw = &adapter->hw;
681 struct net_device *netdev = adapter->netdev;
682 u32 tctl, rctl;
683 int i;
684
685 /* signal that we're down so the interrupt handler does not
686 * reschedule our watchdog timer */
687 set_bit(__IGB_DOWN, &adapter->state);
688
689 /* disable receives in the hardware */
690 rctl = rd32(E1000_RCTL);
691 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
692 /* flush and sleep below */
693
694 netif_stop_queue(netdev);
695
696 /* disable transmits in the hardware */
697 tctl = rd32(E1000_TCTL);
698 tctl &= ~E1000_TCTL_EN;
699 wr32(E1000_TCTL, tctl);
700 /* flush both disables and wait for them to finish */
701 wrfl();
702 msleep(10);
703
704 napi_disable(&adapter->napi);
705
706 if (adapter->msix_entries)
707 for (i = 0; i < adapter->num_rx_queues; i++)
708 napi_disable(&adapter->rx_ring[i].napi);
709 igb_irq_disable(adapter);
710
711 del_timer_sync(&adapter->watchdog_timer);
712 del_timer_sync(&adapter->phy_info_timer);
713
714 netdev->tx_queue_len = adapter->tx_queue_len;
715 netif_carrier_off(netdev);
716 adapter->link_speed = 0;
717 adapter->link_duplex = 0;
718
3023682e
JK		 719 if (!pci_channel_offline(adapter->pdev))
720 igb_reset(adapter);
9d5c8243
AK		 721 igb_clean_all_tx_rings(adapter);
722 igb_clean_all_rx_rings(adapter);
723}
724
725void igb_reinit_locked(struct igb_adapter *adapter)
726{
727 WARN_ON(in_interrupt());
728 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
729 msleep(1);
730 igb_down(adapter);
731 igb_up(adapter);
732 clear_bit(__IGB_RESETTING, &adapter->state);
733}
734
735void igb_reset(struct igb_adapter *adapter)
736{
737 struct e1000_hw *hw = &adapter->hw;
738 struct e1000_fc_info *fc = &adapter->hw.fc;
739 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
740 u16 hwm;
741
742 /* Repartition Pba for greater than 9k mtu
743 * To take effect CTRL.RST is required.
744 */
745 pba = E1000_PBA_34K;
746
747 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
748 /* adjust PBA for jumbo frames */
749 wr32(E1000_PBA, pba);
750
751 /* To maintain wire speed transmits, the Tx FIFO should be
752 * large enough to accommodate two full transmit packets,
753 * rounded up to the next 1KB and expressed in KB. Likewise,
754 * the Rx FIFO should be large enough to accommodate at least
755 * one full receive packet and is similarly rounded up and
756 * expressed in KB. */
757 pba = rd32(E1000_PBA);
758 /* upper 16 bits has Tx packet buffer allocation size in KB */
759 tx_space = pba >> 16;
760 /* lower 16 bits has Rx packet buffer allocation size in KB */
761 pba &= 0xffff;
762 /* the tx fifo also stores 16 bytes of information about the tx
763 * but don't include ethernet FCS because hardware appends it */
764 min_tx_space = (adapter->max_frame_size +
765 sizeof(struct e1000_tx_desc) -
766 ETH_FCS_LEN) * 2;
767 min_tx_space = ALIGN(min_tx_space, 1024);
768 min_tx_space >>= 10;
769 /* software strips receive CRC, so leave room for it */
770 min_rx_space = adapter->max_frame_size;
771 min_rx_space = ALIGN(min_rx_space, 1024);
772 min_rx_space >>= 10;
773
774 /* If current Tx allocation is less than the min Tx FIFO size,
775 * and the min Tx FIFO size is less than the current Rx FIFO
776 * allocation, take space away from current Rx allocation */
777 if (tx_space < min_tx_space &&
778 ((min_tx_space - tx_space) < pba)) {
779 pba = pba - (min_tx_space - tx_space);
780
781 /* if short on rx space, rx wins and must trump tx
782 * adjustment */
783 if (pba < min_rx_space)
784 pba = min_rx_space;
785 }
786 }
787 wr32(E1000_PBA, pba);
788
789 /* flow control settings */
790 /* The high water mark must be low enough to fit one full frame
791 * (or the size used for early receive) above it in the Rx FIFO.
792 * Set it to the lower of:
793 * - 90% of the Rx FIFO size, or
794 * - the full Rx FIFO size minus one full frame */
795 hwm = min(((pba << 10) * 9 / 10),
796 ((pba << 10) - adapter->max_frame_size));
797
798 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
799 fc->low_water = fc->high_water - 8;
800 fc->pause_time = 0xFFFF;
801 fc->send_xon = 1;
802 fc->type = fc->original_type;
803
804 /* Allow time for pending master requests to run */
805 adapter->hw.mac.ops.reset_hw(&adapter->hw);
806 wr32(E1000_WUC, 0);
807
808 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
809 dev_err(&adapter->pdev->dev, "Hardware Error\n");
810
811 igb_update_mng_vlan(adapter);
812
813 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
814 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
815
816 igb_reset_adaptive(&adapter->hw);
68707acb
BH		 817 if (adapter->hw.phy.ops.get_phy_info)
818 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 819}
820
42bfd33a
TI		 821/**
822 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
823 * @pdev: PCI device information struct
824 *
825 * Returns true if an adapter needs ioport resources
826 **/
827static int igb_is_need_ioport(struct pci_dev *pdev)
828{
829 switch (pdev->device) {
830 /* Currently there are no adapters that need ioport resources */
831 default:
832 return false;
833 }
834}
835
9d5c8243
AK		 836/**
837 * igb_probe - Device Initialization Routine
838 * @pdev: PCI device information struct
839 * @ent: entry in igb_pci_tbl
840 *
841 * Returns 0 on success, negative on failure
842 *
843 * igb_probe initializes an adapter identified by a pci_dev structure.
844 * The OS initialization, configuring of the adapter private structure,
845 * and a hardware reset occur.
846 **/
847static int __devinit igb_probe(struct pci_dev *pdev,
848 const struct pci_device_id *ent)
849{
850 struct net_device *netdev;
851 struct igb_adapter *adapter;
852 struct e1000_hw *hw;
853 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
854 unsigned long mmio_start, mmio_len;
9d5c8243
AK		 855 int i, err, pci_using_dac;
856 u16 eeprom_data = 0;
857 u16 eeprom_apme_mask = IGB_EEPROM_APME;
858 u32 part_num;
42bfd33a 859 int bars, need_ioport;
9d5c8243 860
42bfd33a
TI		 861 /* do not allocate ioport bars when not needed */
862 need_ioport = igb_is_need_ioport(pdev);
863 if (need_ioport) {
864 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
865 err = pci_enable_device(pdev);
866 } else {
867 bars = pci_select_bars(pdev, IORESOURCE_MEM);
868 err = pci_enable_device_mem(pdev);
869 }
9d5c8243
AK		 870 if (err)
871 return err;
872
873 pci_using_dac = 0;
874 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
875 if (!err) {
876 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
877 if (!err)
878 pci_using_dac = 1;
879 } else {
880 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
881 if (err) {
882 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
883 if (err) {
884 dev_err(&pdev->dev, "No usable DMA "
885 "configuration, aborting\n");
886 goto err_dma;
887 }
888 }
889 }
890
42bfd33a 891 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
9d5c8243
AK		 892 if (err)
893 goto err_pci_reg;
894
895 pci_set_master(pdev);
c682fc23 896 pci_save_state(pdev);
9d5c8243
AK		 897
898 err = -ENOMEM;
899 netdev = alloc_etherdev(sizeof(struct igb_adapter));
900 if (!netdev)
901 goto err_alloc_etherdev;
902
903 SET_NETDEV_DEV(netdev, &pdev->dev);
904
905 pci_set_drvdata(pdev, netdev);
906 adapter = netdev_priv(netdev);
907 adapter->netdev = netdev;
908 adapter->pdev = pdev;
909 hw = &adapter->hw;
910 hw->back = adapter;
911 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
42bfd33a
TI		 912 adapter->bars = bars;
913 adapter->need_ioport = need_ioport;
9d5c8243
AK		 914
915 mmio_start = pci_resource_start(pdev, 0);
916 mmio_len = pci_resource_len(pdev, 0);
917
918 err = -EIO;
919 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
920 if (!adapter->hw.hw_addr)
921 goto err_ioremap;
922
923 netdev->open = &igb_open;
924 netdev->stop = &igb_close;
925 netdev->get_stats = &igb_get_stats;
926 netdev->set_multicast_list = &igb_set_multi;
927 netdev->set_mac_address = &igb_set_mac;
928 netdev->change_mtu = &igb_change_mtu;
929 netdev->do_ioctl = &igb_ioctl;
930 igb_set_ethtool_ops(netdev);
931 netdev->tx_timeout = &igb_tx_timeout;
932 netdev->watchdog_timeo = 5 * HZ;
933 netif_napi_add(netdev, &adapter->napi, igb_clean, 64);
934 netdev->vlan_rx_register = igb_vlan_rx_register;
935 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
936 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
937#ifdef CONFIG_NET_POLL_CONTROLLER
938 netdev->poll_controller = igb_netpoll;
939#endif
940 netdev->hard_start_xmit = &igb_xmit_frame_adv;
941
942 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
943
944 netdev->mem_start = mmio_start;
945 netdev->mem_end = mmio_start + mmio_len;
946
9d5c8243
AK		 947 /* PCI config space info */
948 hw->vendor_id = pdev->vendor;
949 hw->device_id = pdev->device;
950 hw->revision_id = pdev->revision;
951 hw->subsystem_vendor_id = pdev->subsystem_vendor;
952 hw->subsystem_device_id = pdev->subsystem_device;
953
954 /* setup the private structure */
955 hw->back = adapter;
956 /* Copy the default MAC, PHY and NVM function pointers */
957 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
958 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
959 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
960 /* Initialize skew-specific constants */
961 err = ei->get_invariants(hw);
962 if (err)
963 goto err_hw_init;
964
965 err = igb_sw_init(adapter);
966 if (err)
967 goto err_sw_init;
968
969 igb_get_bus_info_pcie(hw);
970
971 hw->phy.autoneg_wait_to_complete = false;
972 hw->mac.adaptive_ifs = true;
973
974 /* Copper options */
975 if (hw->phy.media_type == e1000_media_type_copper) {
976 hw->phy.mdix = AUTO_ALL_MODES;
977 hw->phy.disable_polarity_correction = false;
978 hw->phy.ms_type = e1000_ms_hw_default;
979 }
980
981 if (igb_check_reset_block(hw))
982 dev_info(&pdev->dev,
983 "PHY reset is blocked due to SOL/IDER session.\n");
984
985 netdev->features = NETIF_F_SG |
986 NETIF_F_HW_CSUM |
987 NETIF_F_HW_VLAN_TX |
988 NETIF_F_HW_VLAN_RX |
989 NETIF_F_HW_VLAN_FILTER;
990
991 netdev->features |= NETIF_F_TSO;
9d5c8243 992 netdev->features |= NETIF_F_TSO6;
48f29ffc
JK		 993
994 netdev->vlan_features |= NETIF_F_TSO;
995 netdev->vlan_features |= NETIF_F_TSO6;
996 netdev->vlan_features |= NETIF_F_HW_CSUM;
997 netdev->vlan_features |= NETIF_F_SG;
998
9d5c8243
AK		 999 if (pci_using_dac)
1000 netdev->features |= NETIF_F_HIGHDMA;
1001
1002 netdev->features |= NETIF_F_LLTX;
1003 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1004
1005 /* before reading the NVM, reset the controller to put the device in a
1006 * known good starting state */
1007 hw->mac.ops.reset_hw(hw);
1008
1009 /* make sure the NVM is good */
1010 if (igb_validate_nvm_checksum(hw) < 0) {
1011 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1012 err = -EIO;
1013 goto err_eeprom;
1014 }
1015
1016 /* copy the MAC address out of the NVM */
1017 if (hw->mac.ops.read_mac_addr(hw))
1018 dev_err(&pdev->dev, "NVM Read Error\n");
1019
1020 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1021 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1022
1023 if (!is_valid_ether_addr(netdev->perm_addr)) {
1024 dev_err(&pdev->dev, "Invalid MAC Address\n");
1025 err = -EIO;
1026 goto err_eeprom;
1027 }
1028
1029 init_timer(&adapter->watchdog_timer);
1030 adapter->watchdog_timer.function = &igb_watchdog;
1031 adapter->watchdog_timer.data = (unsigned long) adapter;
1032
1033 init_timer(&adapter->phy_info_timer);
1034 adapter->phy_info_timer.function = &igb_update_phy_info;
1035 adapter->phy_info_timer.data = (unsigned long) adapter;
1036
1037 INIT_WORK(&adapter->reset_task, igb_reset_task);
1038 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1039
1040 /* Initialize link & ring properties that are user-changeable */
1041 adapter->tx_ring->count = 256;
1042 for (i = 0; i < adapter->num_tx_queues; i++)
1043 adapter->tx_ring[i].count = adapter->tx_ring->count;
1044 adapter->rx_ring->count = 256;
1045 for (i = 0; i < adapter->num_rx_queues; i++)
1046 adapter->rx_ring[i].count = adapter->rx_ring->count;
1047
1048 adapter->fc_autoneg = true;
1049 hw->mac.autoneg = true;
1050 hw->phy.autoneg_advertised = 0x2f;
1051
1052 hw->fc.original_type = e1000_fc_default;
1053 hw->fc.type = e1000_fc_default;
1054
1055 adapter->itr_setting = 3;
1056 adapter->itr = IGB_START_ITR;
1057
1058 igb_validate_mdi_setting(hw);
1059
1060 adapter->rx_csum = 1;
1061
1062 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1063 * enable the ACPI Magic Packet filter
1064 */
1065
1066 if (hw->bus.func == 0 ||
1067 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1068 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1069 &eeprom_data);
1070
1071 if (eeprom_data & eeprom_apme_mask)
1072 adapter->eeprom_wol |= E1000_WUFC_MAG;
1073
1074 /* now that we have the eeprom settings, apply the special cases where
1075 * the eeprom may be wrong or the board simply won't support wake on
1076 * lan on a particular port */
1077 switch (pdev->device) {
1078 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1079 adapter->eeprom_wol = 0;
1080 break;
1081 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1082 /* Wake events only supported on port A for dual fiber
1083 * regardless of eeprom setting */
1084 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1085 adapter->eeprom_wol = 0;
1086 break;
1087 }
1088
1089 /* initialize the wol settings based on the eeprom settings */
1090 adapter->wol = adapter->eeprom_wol;
1091
1092 /* reset the hardware with the new settings */
1093 igb_reset(adapter);
1094
1095 /* let the f/w know that the h/w is now under the control of the
1096 * driver. */
1097 igb_get_hw_control(adapter);
1098
1099 /* tell the stack to leave us alone until igb_open() is called */
1100 netif_carrier_off(netdev);
1101 netif_stop_queue(netdev);
1102
1103 strcpy(netdev->name, "eth%d");
1104 err = register_netdev(netdev);
1105 if (err)
1106 goto err_register;
1107
1108 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1109 /* print bus type/speed/width info */
1110 dev_info(&pdev->dev,
1111 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1112 netdev->name,
1113 ((hw->bus.speed == e1000_bus_speed_2500)
1114 ? "2.5Gb/s" : "unknown"),
1115 ((hw->bus.width == e1000_bus_width_pcie_x4)
1116 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1117 ? "Width x1" : "unknown"),
1118 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1119 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1120
1121 igb_read_part_num(hw, &part_num);
1122 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1123 (part_num >> 8), (part_num & 0xff));
1124
1125 dev_info(&pdev->dev,
1126 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1127 adapter->msix_entries ? "MSI-X" :
1128 adapter->msi_enabled ? "MSI" : "legacy",
1129 adapter->num_rx_queues, adapter->num_tx_queues);
1130
9d5c8243
AK		 1131 return 0;
1132
1133err_register:
1134 igb_release_hw_control(adapter);
1135err_eeprom:
1136 if (!igb_check_reset_block(hw))
1137 hw->phy.ops.reset_phy(hw);
1138
1139 if (hw->flash_address)
1140 iounmap(hw->flash_address);
1141
1142 igb_remove_device(hw);
1143 kfree(adapter->tx_ring);
1144 kfree(adapter->rx_ring);
1145err_sw_init:
1146err_hw_init:
1147 iounmap(hw->hw_addr);
1148err_ioremap:
1149 free_netdev(netdev);
1150err_alloc_etherdev:
42bfd33a 1151 pci_release_selected_regions(pdev, bars);
9d5c8243
AK		 1152err_pci_reg:
1153err_dma:
1154 pci_disable_device(pdev);
1155 return err;
1156}
1157
1158/**
1159 * igb_remove - Device Removal Routine
1160 * @pdev: PCI device information struct
1161 *
1162 * igb_remove is called by the PCI subsystem to alert the driver
1163 * that it should release a PCI device. The could be caused by a
1164 * Hot-Plug event, or because the driver is going to be removed from
1165 * memory.
1166 **/
1167static void __devexit igb_remove(struct pci_dev *pdev)
1168{
1169 struct net_device *netdev = pci_get_drvdata(pdev);
1170 struct igb_adapter *adapter = netdev_priv(netdev);
1171
1172 /* flush_scheduled work may reschedule our watchdog task, so
1173 * explicitly disable watchdog tasks from being rescheduled */
1174 set_bit(__IGB_DOWN, &adapter->state);
1175 del_timer_sync(&adapter->watchdog_timer);
1176 del_timer_sync(&adapter->phy_info_timer);
1177
1178 flush_scheduled_work();
1179
9d5c8243
AK		 1180 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1181 * would have already happened in close and is redundant. */
1182 igb_release_hw_control(adapter);
1183
1184 unregister_netdev(netdev);
1185
1186 if (!igb_check_reset_block(&adapter->hw))
1187 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1188
1189 igb_remove_device(&adapter->hw);
1190 igb_reset_interrupt_capability(adapter);
1191
1192 kfree(adapter->tx_ring);
1193 kfree(adapter->rx_ring);
1194
1195 iounmap(adapter->hw.hw_addr);
1196 if (adapter->hw.flash_address)
1197 iounmap(adapter->hw.flash_address);
42bfd33a 1198 pci_release_selected_regions(pdev, adapter->bars);
9d5c8243
AK		 1199
1200 free_netdev(netdev);
1201
1202 pci_disable_device(pdev);
1203}
1204
1205/**
1206 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1207 * @adapter: board private structure to initialize
1208 *
1209 * igb_sw_init initializes the Adapter private data structure.
1210 * Fields are initialized based on PCI device information and
1211 * OS network device settings (MTU size).
1212 **/
1213static int __devinit igb_sw_init(struct igb_adapter *adapter)
1214{
1215 struct e1000_hw *hw = &adapter->hw;
1216 struct net_device *netdev = adapter->netdev;
1217 struct pci_dev *pdev = adapter->pdev;
1218
1219 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1220
1221 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1222 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1223 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1224 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1225
1226 /* Number of supported queues. */
1227 /* Having more queues than CPUs doesn't make sense. */
1228 adapter->num_tx_queues = 1;
1229 adapter->num_rx_queues = min(IGB_MAX_RX_QUEUES, num_online_cpus());
1230
1231 igb_set_interrupt_capability(adapter);
1232
1233 if (igb_alloc_queues(adapter)) {
1234 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1235 return -ENOMEM;
1236 }
1237
1238 /* Explicitly disable IRQ since the NIC can be in any state. */
1239 igb_irq_disable(adapter);
1240
1241 set_bit(__IGB_DOWN, &adapter->state);
1242 return 0;
1243}
1244
1245/**
1246 * igb_open - Called when a network interface is made active
1247 * @netdev: network interface device structure
1248 *
1249 * Returns 0 on success, negative value on failure
1250 *
1251 * The open entry point is called when a network interface is made
1252 * active by the system (IFF_UP). At this point all resources needed
1253 * for transmit and receive operations are allocated, the interrupt
1254 * handler is registered with the OS, the watchdog timer is started,
1255 * and the stack is notified that the interface is ready.
1256 **/
1257static int igb_open(struct net_device *netdev)
1258{
1259 struct igb_adapter *adapter = netdev_priv(netdev);
1260 struct e1000_hw *hw = &adapter->hw;
1261 int err;
1262 int i;
1263
1264 /* disallow open during test */
1265 if (test_bit(__IGB_TESTING, &adapter->state))
1266 return -EBUSY;
1267
1268 /* allocate transmit descriptors */
1269 err = igb_setup_all_tx_resources(adapter);
1270 if (err)
1271 goto err_setup_tx;
1272
1273 /* allocate receive descriptors */
1274 err = igb_setup_all_rx_resources(adapter);
1275 if (err)
1276 goto err_setup_rx;
1277
1278 /* e1000_power_up_phy(adapter); */
1279
1280 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1281 if ((adapter->hw.mng_cookie.status &
1282 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1283 igb_update_mng_vlan(adapter);
1284
1285 /* before we allocate an interrupt, we must be ready to handle it.
1286 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1287 * as soon as we call pci_request_irq, so we have to setup our
1288 * clean_rx handler before we do so. */
1289 igb_configure(adapter);
1290
1291 err = igb_request_irq(adapter);
1292 if (err)
1293 goto err_req_irq;
1294
1295 /* From here on the code is the same as igb_up() */
1296 clear_bit(__IGB_DOWN, &adapter->state);
1297
1298 napi_enable(&adapter->napi);
1299 if (adapter->msix_entries)
1300 for (i = 0; i < adapter->num_rx_queues; i++)
1301 napi_enable(&adapter->rx_ring[i].napi);
1302
1303 igb_irq_enable(adapter);
1304
1305 /* Clear any pending interrupts. */
1306 rd32(E1000_ICR);
1307 /* Fire a link status change interrupt to start the watchdog. */
1308 wr32(E1000_ICS, E1000_ICS_LSC);
1309
1310 return 0;
1311
1312err_req_irq:
1313 igb_release_hw_control(adapter);
1314 /* e1000_power_down_phy(adapter); */
1315 igb_free_all_rx_resources(adapter);
1316err_setup_rx:
1317 igb_free_all_tx_resources(adapter);
1318err_setup_tx:
1319 igb_reset(adapter);
1320
1321 return err;
1322}
1323
1324/**
1325 * igb_close - Disables a network interface
1326 * @netdev: network interface device structure
1327 *
1328 * Returns 0, this is not allowed to fail
1329 *
1330 * The close entry point is called when an interface is de-activated
1331 * by the OS. The hardware is still under the driver's control, but
1332 * needs to be disabled. A global MAC reset is issued to stop the
1333 * hardware, and all transmit and receive resources are freed.
1334 **/
1335static int igb_close(struct net_device *netdev)
1336{
1337 struct igb_adapter *adapter = netdev_priv(netdev);
1338
1339 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1340 igb_down(adapter);
1341
1342 igb_free_irq(adapter);
1343
1344 igb_free_all_tx_resources(adapter);
1345 igb_free_all_rx_resources(adapter);
1346
1347 /* kill manageability vlan ID if supported, but not if a vlan with
1348 * the same ID is registered on the host OS (let 8021q kill it) */
1349 if ((adapter->hw.mng_cookie.status &
1350 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1351 !(adapter->vlgrp &&
1352 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1353 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1354
1355 return 0;
1356}
1357
1358/**
1359 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1360 * @adapter: board private structure
1361 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1362 *
1363 * Return 0 on success, negative on failure
1364 **/
1365
1366int igb_setup_tx_resources(struct igb_adapter *adapter,
1367 struct igb_ring *tx_ring)
1368{
1369 struct pci_dev *pdev = adapter->pdev;
1370 int size;
1371
1372 size = sizeof(struct igb_buffer) * tx_ring->count;
1373 tx_ring->buffer_info = vmalloc(size);
1374 if (!tx_ring->buffer_info)
1375 goto err;
1376 memset(tx_ring->buffer_info, 0, size);
1377
1378 /* round up to nearest 4K */
1379 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1380 + sizeof(u32);
1381 tx_ring->size = ALIGN(tx_ring->size, 4096);
1382
1383 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1384 &tx_ring->dma);
1385
1386 if (!tx_ring->desc)
1387 goto err;
1388
1389 tx_ring->adapter = adapter;
1390 tx_ring->next_to_use = 0;
1391 tx_ring->next_to_clean = 0;
1392 spin_lock_init(&tx_ring->tx_clean_lock);
1393 spin_lock_init(&tx_ring->tx_lock);
1394 return 0;
1395
1396err:
1397 vfree(tx_ring->buffer_info);
1398 dev_err(&adapter->pdev->dev,
1399 "Unable to allocate memory for the transmit descriptor ring\n");
1400 return -ENOMEM;
1401}
1402
1403/**
1404 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1405 * (Descriptors) for all queues
1406 * @adapter: board private structure
1407 *
1408 * Return 0 on success, negative on failure
1409 **/
1410static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1411{
1412 int i, err = 0;
1413
1414 for (i = 0; i < adapter->num_tx_queues; i++) {
1415 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1416 if (err) {
1417 dev_err(&adapter->pdev->dev,
1418 "Allocation for Tx Queue %u failed\n", i);
1419 for (i--; i >= 0; i--)
3b644cf6 1420 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1421 break;
1422 }
1423 }
1424
1425 return err;
1426}
1427
1428/**
1429 * igb_configure_tx - Configure transmit Unit after Reset
1430 * @adapter: board private structure
1431 *
1432 * Configure the Tx unit of the MAC after a reset.
1433 **/
1434static void igb_configure_tx(struct igb_adapter *adapter)
1435{
1436 u64 tdba, tdwba;
1437 struct e1000_hw *hw = &adapter->hw;
1438 u32 tctl;
1439 u32 txdctl, txctrl;
1440 int i;
1441
1442 for (i = 0; i < adapter->num_tx_queues; i++) {
1443 struct igb_ring *ring = &(adapter->tx_ring[i]);
1444
1445 wr32(E1000_TDLEN(i),
1446 ring->count * sizeof(struct e1000_tx_desc));
1447 tdba = ring->dma;
1448 wr32(E1000_TDBAL(i),
1449 tdba & 0x00000000ffffffffULL);
1450 wr32(E1000_TDBAH(i), tdba >> 32);
1451
1452 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1453 tdwba |= 1; /* enable head wb */
1454 wr32(E1000_TDWBAL(i),
1455 tdwba & 0x00000000ffffffffULL);
1456 wr32(E1000_TDWBAH(i), tdwba >> 32);
1457
1458 ring->head = E1000_TDH(i);
1459 ring->tail = E1000_TDT(i);
1460 writel(0, hw->hw_addr + ring->tail);
1461 writel(0, hw->hw_addr + ring->head);
1462 txdctl = rd32(E1000_TXDCTL(i));
1463 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1464 wr32(E1000_TXDCTL(i), txdctl);
1465
1466 /* Turn off Relaxed Ordering on head write-backs. The
1467 * writebacks MUST be delivered in order or it will
1468 * completely screw up our bookeeping.
1469 */
1470 txctrl = rd32(E1000_DCA_TXCTRL(i));
1471 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1472 wr32(E1000_DCA_TXCTRL(i), txctrl);
1473 }
1474
1475
1476
1477 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1478
1479 /* Program the Transmit Control Register */
1480
1481 tctl = rd32(E1000_TCTL);
1482 tctl &= ~E1000_TCTL_CT;
1483 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1484 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1485
1486 igb_config_collision_dist(hw);
1487
1488 /* Setup Transmit Descriptor Settings for eop descriptor */
1489 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1490
1491 /* Enable transmits */
1492 tctl |= E1000_TCTL_EN;
1493
1494 wr32(E1000_TCTL, tctl);
1495}
1496
1497/**
1498 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1499 * @adapter: board private structure
1500 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1501 *
1502 * Returns 0 on success, negative on failure
1503 **/
1504
1505int igb_setup_rx_resources(struct igb_adapter *adapter,
1506 struct igb_ring *rx_ring)
1507{
1508 struct pci_dev *pdev = adapter->pdev;
1509 int size, desc_len;
1510
1511 size = sizeof(struct igb_buffer) * rx_ring->count;
1512 rx_ring->buffer_info = vmalloc(size);
1513 if (!rx_ring->buffer_info)
1514 goto err;
1515 memset(rx_ring->buffer_info, 0, size);
1516
1517 desc_len = sizeof(union e1000_adv_rx_desc);
1518
1519 /* Round up to nearest 4K */
1520 rx_ring->size = rx_ring->count * desc_len;
1521 rx_ring->size = ALIGN(rx_ring->size, 4096);
1522
1523 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1524 &rx_ring->dma);
1525
1526 if (!rx_ring->desc)
1527 goto err;
1528
1529 rx_ring->next_to_clean = 0;
1530 rx_ring->next_to_use = 0;
1531 rx_ring->pending_skb = NULL;
1532
1533 rx_ring->adapter = adapter;
1534 /* FIXME: do we want to setup ring->napi->poll here? */
1535 rx_ring->napi.poll = adapter->napi.poll;
1536
1537 return 0;
1538
1539err:
1540 vfree(rx_ring->buffer_info);
1541 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1542 "the receive descriptor ring\n");
1543 return -ENOMEM;
1544}
1545
1546/**
1547 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1548 * (Descriptors) for all queues
1549 * @adapter: board private structure
1550 *
1551 * Return 0 on success, negative on failure
1552 **/
1553static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1554{
1555 int i, err = 0;
1556
1557 for (i = 0; i < adapter->num_rx_queues; i++) {
1558 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1559 if (err) {
1560 dev_err(&adapter->pdev->dev,
1561 "Allocation for Rx Queue %u failed\n", i);
1562 for (i--; i >= 0; i--)
3b644cf6 1563 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1564 break;
1565 }
1566 }
1567
1568 return err;
1569}
1570
1571/**
1572 * igb_setup_rctl - configure the receive control registers
1573 * @adapter: Board private structure
1574 **/
1575static void igb_setup_rctl(struct igb_adapter *adapter)
1576{
1577 struct e1000_hw *hw = &adapter->hw;
1578 u32 rctl;
1579 u32 srrctl = 0;
1580 int i;
1581
1582 rctl = rd32(E1000_RCTL);
1583
1584 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1585
1586 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1587 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1588 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1589
1590 /* disable the stripping of CRC because it breaks
1591 * BMC firmware connected over SMBUS
1592 rctl |= E1000_RCTL_SECRC;
1593 */
1594
1595 rctl &= ~E1000_RCTL_SBP;
1596
1597 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1598 rctl &= ~E1000_RCTL_LPE;
1599 else
1600 rctl |= E1000_RCTL_LPE;
1601 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1602 /* Setup buffer sizes */
1603 rctl &= ~E1000_RCTL_SZ_4096;
1604 rctl |= E1000_RCTL_BSEX;
1605 switch (adapter->rx_buffer_len) {
1606 case IGB_RXBUFFER_256:
1607 rctl |= E1000_RCTL_SZ_256;
1608 rctl &= ~E1000_RCTL_BSEX;
1609 break;
1610 case IGB_RXBUFFER_512:
1611 rctl |= E1000_RCTL_SZ_512;
1612 rctl &= ~E1000_RCTL_BSEX;
1613 break;
1614 case IGB_RXBUFFER_1024:
1615 rctl |= E1000_RCTL_SZ_1024;
1616 rctl &= ~E1000_RCTL_BSEX;
1617 break;
1618 case IGB_RXBUFFER_2048:
1619 default:
1620 rctl |= E1000_RCTL_SZ_2048;
1621 rctl &= ~E1000_RCTL_BSEX;
1622 break;
1623 case IGB_RXBUFFER_4096:
1624 rctl |= E1000_RCTL_SZ_4096;
1625 break;
1626 case IGB_RXBUFFER_8192:
1627 rctl |= E1000_RCTL_SZ_8192;
1628 break;
1629 case IGB_RXBUFFER_16384:
1630 rctl |= E1000_RCTL_SZ_16384;
1631 break;
1632 }
1633 } else {
1634 rctl &= ~E1000_RCTL_BSEX;
1635 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1636 }
1637
1638 /* 82575 and greater support packet-split where the protocol
1639 * header is placed in skb->data and the packet data is
1640 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1641 * In the case of a non-split, skb->data is linearly filled,
1642 * followed by the page buffers. Therefore, skb->data is
1643 * sized to hold the largest protocol header.
1644 */
1645 /* allocations using alloc_page take too long for regular MTU
1646 * so only enable packet split for jumbo frames */
1647 if (rctl & E1000_RCTL_LPE) {
1648 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1649 srrctl = adapter->rx_ps_hdr_size <<
1650 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1651 /* buffer size is ALWAYS one page */
1652 srrctl |= PAGE_SIZE >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1653 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1654 } else {
1655 adapter->rx_ps_hdr_size = 0;
1656 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1657 }
1658
1659 for (i = 0; i < adapter->num_rx_queues; i++)
1660 wr32(E1000_SRRCTL(i), srrctl);
1661
1662 wr32(E1000_RCTL, rctl);
1663}
1664
1665/**
1666 * igb_configure_rx - Configure receive Unit after Reset
1667 * @adapter: board private structure
1668 *
1669 * Configure the Rx unit of the MAC after a reset.
1670 **/
1671static void igb_configure_rx(struct igb_adapter *adapter)
1672{
1673 u64 rdba;
1674 struct e1000_hw *hw = &adapter->hw;
1675 u32 rctl, rxcsum;
1676 u32 rxdctl;
1677 int i;
1678
1679 /* disable receives while setting up the descriptors */
1680 rctl = rd32(E1000_RCTL);
1681 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1682 wrfl();
1683 mdelay(10);
1684
1685 if (adapter->itr_setting > 3)
1686 wr32(E1000_ITR,
1687 1000000000 / (adapter->itr * 256));
1688
1689 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1690 * the Base and Length of the Rx Descriptor Ring */
1691 for (i = 0; i < adapter->num_rx_queues; i++) {
1692 struct igb_ring *ring = &(adapter->rx_ring[i]);
1693 rdba = ring->dma;
1694 wr32(E1000_RDBAL(i),
1695 rdba & 0x00000000ffffffffULL);
1696 wr32(E1000_RDBAH(i), rdba >> 32);
1697 wr32(E1000_RDLEN(i),
1698 ring->count * sizeof(union e1000_adv_rx_desc));
1699
1700 ring->head = E1000_RDH(i);
1701 ring->tail = E1000_RDT(i);
1702 writel(0, hw->hw_addr + ring->tail);
1703 writel(0, hw->hw_addr + ring->head);
1704
1705 rxdctl = rd32(E1000_RXDCTL(i));
1706 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1707 rxdctl &= 0xFFF00000;
1708 rxdctl |= IGB_RX_PTHRESH;
1709 rxdctl |= IGB_RX_HTHRESH << 8;
1710 rxdctl |= IGB_RX_WTHRESH << 16;
1711 wr32(E1000_RXDCTL(i), rxdctl);
1712 }
1713
1714 if (adapter->num_rx_queues > 1) {
1715 u32 random[10];
1716 u32 mrqc;
1717 u32 j, shift;
1718 union e1000_reta {
1719 u32 dword;
1720 u8 bytes[4];
1721 } reta;
1722
1723 get_random_bytes(&random[0], 40);
1724
1725 shift = 6;
1726 for (j = 0; j < (32 * 4); j++) {
1727 reta.bytes[j & 3] =
1728 (j % adapter->num_rx_queues) << shift;
1729 if ((j & 3) == 3)
1730 writel(reta.dword,
1731 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1732 }
1733 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1734
1735 /* Fill out hash function seeds */
1736 for (j = 0; j < 10; j++)
1737 array_wr32(E1000_RSSRK(0), j, random[j]);
1738
1739 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1740 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1741 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1742 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1743 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1744 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1745 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1746 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1747
1748
1749 wr32(E1000_MRQC, mrqc);
1750
1751 /* Multiqueue and raw packet checksumming are mutually
1752 * exclusive. Note that this not the same as TCP/IP
1753 * checksumming, which works fine. */
1754 rxcsum = rd32(E1000_RXCSUM);
1755 rxcsum |= E1000_RXCSUM_PCSD;
1756 wr32(E1000_RXCSUM, rxcsum);
1757 } else {
1758 /* Enable Receive Checksum Offload for TCP and UDP */
1759 rxcsum = rd32(E1000_RXCSUM);
1760 if (adapter->rx_csum) {
1761 rxcsum |= E1000_RXCSUM_TUOFL;
1762
1763 /* Enable IPv4 payload checksum for UDP fragments
1764 * Must be used in conjunction with packet-split. */
1765 if (adapter->rx_ps_hdr_size)
1766 rxcsum |= E1000_RXCSUM_IPPCSE;
1767 } else {
1768 rxcsum &= ~E1000_RXCSUM_TUOFL;
1769 /* don't need to clear IPPCSE as it defaults to 0 */
1770 }
1771 wr32(E1000_RXCSUM, rxcsum);
1772 }
1773
1774 if (adapter->vlgrp)
1775 wr32(E1000_RLPML,
1776 adapter->max_frame_size + VLAN_TAG_SIZE);
1777 else
1778 wr32(E1000_RLPML, adapter->max_frame_size);
1779
1780 /* Enable Receives */
1781 wr32(E1000_RCTL, rctl);
1782}
1783
1784/**
1785 * igb_free_tx_resources - Free Tx Resources per Queue
1786 * @adapter: board private structure
1787 * @tx_ring: Tx descriptor ring for a specific queue
1788 *
1789 * Free all transmit software resources
1790 **/
3b644cf6 1791static void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1792{
3b644cf6 1793 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1794
3b644cf6 1795 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 1796
1797 vfree(tx_ring->buffer_info);
1798 tx_ring->buffer_info = NULL;
1799
1800 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1801
1802 tx_ring->desc = NULL;
1803}
1804
1805/**
1806 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1807 * @adapter: board private structure
1808 *
1809 * Free all transmit software resources
1810 **/
1811static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1812{
1813 int i;
1814
1815 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 1816 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1817}
1818
1819static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
1820 struct igb_buffer *buffer_info)
1821{
1822 if (buffer_info->dma) {
1823 pci_unmap_page(adapter->pdev,
1824 buffer_info->dma,
1825 buffer_info->length,
1826 PCI_DMA_TODEVICE);
1827 buffer_info->dma = 0;
1828 }
1829 if (buffer_info->skb) {
1830 dev_kfree_skb_any(buffer_info->skb);
1831 buffer_info->skb = NULL;
1832 }
1833 buffer_info->time_stamp = 0;
1834 /* buffer_info must be completely set up in the transmit path */
1835}
1836
1837/**
1838 * igb_clean_tx_ring - Free Tx Buffers
1839 * @adapter: board private structure
1840 * @tx_ring: ring to be cleaned
1841 **/
3b644cf6 1842static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 1843{
3b644cf6 1844 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 1845 struct igb_buffer *buffer_info;
1846 unsigned long size;
1847 unsigned int i;
1848
1849 if (!tx_ring->buffer_info)
1850 return;
1851 /* Free all the Tx ring sk_buffs */
1852
1853 for (i = 0; i < tx_ring->count; i++) {
1854 buffer_info = &tx_ring->buffer_info[i];
1855 igb_unmap_and_free_tx_resource(adapter, buffer_info);
1856 }
1857
1858 size = sizeof(struct igb_buffer) * tx_ring->count;
1859 memset(tx_ring->buffer_info, 0, size);
1860
1861 /* Zero out the descriptor ring */
1862
1863 memset(tx_ring->desc, 0, tx_ring->size);
1864
1865 tx_ring->next_to_use = 0;
1866 tx_ring->next_to_clean = 0;
1867
1868 writel(0, adapter->hw.hw_addr + tx_ring->head);
1869 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1870}
1871
1872/**
1873 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
1874 * @adapter: board private structure
1875 **/
1876static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
1877{
1878 int i;
1879
1880 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 1881 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 1882}
1883
1884/**
1885 * igb_free_rx_resources - Free Rx Resources
1886 * @adapter: board private structure
1887 * @rx_ring: ring to clean the resources from
1888 *
1889 * Free all receive software resources
1890 **/
3b644cf6 1891static void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 1892{
3b644cf6 1893 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 1894
3b644cf6 1895 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 1896
1897 vfree(rx_ring->buffer_info);
1898 rx_ring->buffer_info = NULL;
1899
1900 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1901
1902 rx_ring->desc = NULL;
1903}
1904
1905/**
1906 * igb_free_all_rx_resources - Free Rx Resources for All Queues
1907 * @adapter: board private structure
1908 *
1909 * Free all receive software resources
1910 **/
1911static void igb_free_all_rx_resources(struct igb_adapter *adapter)
1912{
1913 int i;
1914
1915 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 1916 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1917}
1918
1919/**
1920 * igb_clean_rx_ring - Free Rx Buffers per Queue
1921 * @adapter: board private structure
1922 * @rx_ring: ring to free buffers from
1923 **/
3b644cf6 1924static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 1925{
3b644cf6 1926 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 1927 struct igb_buffer *buffer_info;
1928 struct pci_dev *pdev = adapter->pdev;
1929 unsigned long size;
1930 unsigned int i;
1931
1932 if (!rx_ring->buffer_info)
1933 return;
1934 /* Free all the Rx ring sk_buffs */
1935 for (i = 0; i < rx_ring->count; i++) {
1936 buffer_info = &rx_ring->buffer_info[i];
1937 if (buffer_info->dma) {
1938 if (adapter->rx_ps_hdr_size)
1939 pci_unmap_single(pdev, buffer_info->dma,
1940 adapter->rx_ps_hdr_size,
1941 PCI_DMA_FROMDEVICE);
1942 else
1943 pci_unmap_single(pdev, buffer_info->dma,
1944 adapter->rx_buffer_len,
1945 PCI_DMA_FROMDEVICE);
1946 buffer_info->dma = 0;
1947 }
1948
1949 if (buffer_info->skb) {
1950 dev_kfree_skb(buffer_info->skb);
1951 buffer_info->skb = NULL;
1952 }
1953 if (buffer_info->page) {
1954 pci_unmap_page(pdev, buffer_info->page_dma,
1955 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1956 put_page(buffer_info->page);
1957 buffer_info->page = NULL;
1958 buffer_info->page_dma = 0;
1959 }
1960 }
1961
1962 /* there also may be some cached data from a chained receive */
1963 if (rx_ring->pending_skb) {
1964 dev_kfree_skb(rx_ring->pending_skb);
1965 rx_ring->pending_skb = NULL;
1966 }
1967
1968 size = sizeof(struct igb_buffer) * rx_ring->count;
1969 memset(rx_ring->buffer_info, 0, size);
1970
1971 /* Zero out the descriptor ring */
1972 memset(rx_ring->desc, 0, rx_ring->size);
1973
1974 rx_ring->next_to_clean = 0;
1975 rx_ring->next_to_use = 0;
1976
1977 writel(0, adapter->hw.hw_addr + rx_ring->head);
1978 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1979}
1980
1981/**
1982 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
1983 * @adapter: board private structure
1984 **/
1985static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
1986{
1987 int i;
1988
1989 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 1990 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 1991}
1992
1993/**
1994 * igb_set_mac - Change the Ethernet Address of the NIC
1995 * @netdev: network interface device structure
1996 * @p: pointer to an address structure
1997 *
1998 * Returns 0 on success, negative on failure
1999 **/
2000static int igb_set_mac(struct net_device *netdev, void *p)
2001{
2002 struct igb_adapter *adapter = netdev_priv(netdev);
2003 struct sockaddr *addr = p;
2004
2005 if (!is_valid_ether_addr(addr->sa_data))
2006 return -EADDRNOTAVAIL;
2007
2008 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2009 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2010
2011 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2012
2013 return 0;
2014}
2015
2016/**
2017 * igb_set_multi - Multicast and Promiscuous mode set
2018 * @netdev: network interface device structure
2019 *
2020 * The set_multi entry point is called whenever the multicast address
2021 * list or the network interface flags are updated. This routine is
2022 * responsible for configuring the hardware for proper multicast,
2023 * promiscuous mode, and all-multi behavior.
2024 **/
2025static void igb_set_multi(struct net_device *netdev)
2026{
2027 struct igb_adapter *adapter = netdev_priv(netdev);
2028 struct e1000_hw *hw = &adapter->hw;
2029 struct e1000_mac_info *mac = &hw->mac;
2030 struct dev_mc_list *mc_ptr;
2031 u8 *mta_list;
2032 u32 rctl;
2033 int i;
2034
2035 /* Check for Promiscuous and All Multicast modes */
2036
2037 rctl = rd32(E1000_RCTL);
2038
2039 if (netdev->flags & IFF_PROMISC)
2040 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2041 else if (netdev->flags & IFF_ALLMULTI) {
2042 rctl |= E1000_RCTL_MPE;
2043 rctl &= ~E1000_RCTL_UPE;
2044 } else
2045 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2046
2047 wr32(E1000_RCTL, rctl);
2048
2049 if (!netdev->mc_count) {
2050 /* nothing to program, so clear mc list */
2051 igb_update_mc_addr_list(hw, NULL, 0, 1,
2052 mac->rar_entry_count);
2053 return;
2054 }
2055
2056 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2057 if (!mta_list)
2058 return;
2059
2060 /* The shared function expects a packed array of only addresses. */
2061 mc_ptr = netdev->mc_list;
2062
2063 for (i = 0; i < netdev->mc_count; i++) {
2064 if (!mc_ptr)
2065 break;
2066 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2067 mc_ptr = mc_ptr->next;
2068 }
2069 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
2070 kfree(mta_list);
2071}
2072
2073/* Need to wait a few seconds after link up to get diagnostic information from
2074 * the phy */
2075static void igb_update_phy_info(unsigned long data)
2076{
2077 struct igb_adapter *adapter = (struct igb_adapter *) data;
68707acb
BH		 2078 if (adapter->hw.phy.ops.get_phy_info)
2079 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
9d5c8243
AK		 2080}
2081
2082/**
2083 * igb_watchdog - Timer Call-back
2084 * @data: pointer to adapter cast into an unsigned long
2085 **/
2086static void igb_watchdog(unsigned long data)
2087{
2088 struct igb_adapter *adapter = (struct igb_adapter *)data;
2089 /* Do the rest outside of interrupt context */
2090 schedule_work(&adapter->watchdog_task);
2091}
2092
2093static void igb_watchdog_task(struct work_struct *work)
2094{
2095 struct igb_adapter *adapter = container_of(work,
2096 struct igb_adapter, watchdog_task);
2097 struct e1000_hw *hw = &adapter->hw;
2098
2099 struct net_device *netdev = adapter->netdev;
2100 struct igb_ring *tx_ring = adapter->tx_ring;
2101 struct e1000_mac_info *mac = &adapter->hw.mac;
2102 u32 link;
2103 s32 ret_val;
2104
2105 if ((netif_carrier_ok(netdev)) &&
2106 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2107 goto link_up;
2108
2109 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2110 if ((ret_val == E1000_ERR_PHY) &&
2111 (hw->phy.type == e1000_phy_igp_3) &&
2112 (rd32(E1000_CTRL) &
2113 E1000_PHY_CTRL_GBE_DISABLE))
2114 dev_info(&adapter->pdev->dev,
2115 "Gigabit has been disabled, downgrading speed\n");
2116
2117 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2118 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2119 link = mac->serdes_has_link;
2120 else
2121 link = rd32(E1000_STATUS) &
2122 E1000_STATUS_LU;
2123
2124 if (link) {
2125 if (!netif_carrier_ok(netdev)) {
2126 u32 ctrl;
2127 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2128 &adapter->link_speed,
2129 &adapter->link_duplex);
2130
2131 ctrl = rd32(E1000_CTRL);
2132 dev_info(&adapter->pdev->dev,
2133 "NIC Link is Up %d Mbps %s, "
2134 "Flow Control: %s\n",
2135 adapter->link_speed,
2136 adapter->link_duplex == FULL_DUPLEX ?
2137 "Full Duplex" : "Half Duplex",
2138 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2139 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2140 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2141 E1000_CTRL_TFCE) ? "TX" : "None")));
2142
2143 /* tweak tx_queue_len according to speed/duplex and
2144 * adjust the timeout factor */
2145 netdev->tx_queue_len = adapter->tx_queue_len;
2146 adapter->tx_timeout_factor = 1;
2147 switch (adapter->link_speed) {
2148 case SPEED_10:
2149 netdev->tx_queue_len = 10;
2150 adapter->tx_timeout_factor = 14;
2151 break;
2152 case SPEED_100:
2153 netdev->tx_queue_len = 100;
2154 /* maybe add some timeout factor ? */
2155 break;
2156 }
2157
2158 netif_carrier_on(netdev);
2159 netif_wake_queue(netdev);
2160
2161 if (!test_bit(__IGB_DOWN, &adapter->state))
2162 mod_timer(&adapter->phy_info_timer,
2163 round_jiffies(jiffies + 2 * HZ));
2164 }
2165 } else {
2166 if (netif_carrier_ok(netdev)) {
2167 adapter->link_speed = 0;
2168 adapter->link_duplex = 0;
2169 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2170 netif_carrier_off(netdev);
2171 netif_stop_queue(netdev);
2172 if (!test_bit(__IGB_DOWN, &adapter->state))
2173 mod_timer(&adapter->phy_info_timer,
2174 round_jiffies(jiffies + 2 * HZ));
2175 }
2176 }
2177
2178link_up:
2179 igb_update_stats(adapter);
2180
2181 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2182 adapter->tpt_old = adapter->stats.tpt;
2183 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2184 adapter->colc_old = adapter->stats.colc;
2185
2186 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2187 adapter->gorc_old = adapter->stats.gorc;
2188 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2189 adapter->gotc_old = adapter->stats.gotc;
2190
2191 igb_update_adaptive(&adapter->hw);
2192
2193 if (!netif_carrier_ok(netdev)) {
2194 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2195 /* We've lost link, so the controller stops DMA,
2196 * but we've got queued Tx work that's never going
2197 * to get done, so reset controller to flush Tx.
2198 * (Do the reset outside of interrupt context). */
2199 adapter->tx_timeout_count++;
2200 schedule_work(&adapter->reset_task);
2201 }
2202 }
2203
2204 /* Cause software interrupt to ensure rx ring is cleaned */
2205 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2206
2207 /* Force detection of hung controller every watchdog period */
2208 tx_ring->detect_tx_hung = true;
2209
2210 /* Reset the timer */
2211 if (!test_bit(__IGB_DOWN, &adapter->state))
2212 mod_timer(&adapter->watchdog_timer,
2213 round_jiffies(jiffies + 2 * HZ));
2214}
2215
2216enum latency_range {
2217 lowest_latency = 0,
2218 low_latency = 1,
2219 bulk_latency = 2,
2220 latency_invalid = 255
2221};
2222
2223
2224static void igb_lower_rx_eitr(struct igb_adapter *adapter,
2225 struct igb_ring *rx_ring)
2226{
2227 struct e1000_hw *hw = &adapter->hw;
2228 int new_val;
2229
2230 new_val = rx_ring->itr_val / 2;
2231 if (new_val < IGB_MIN_DYN_ITR)
2232 new_val = IGB_MIN_DYN_ITR;
2233
2234 if (new_val != rx_ring->itr_val) {
2235 rx_ring->itr_val = new_val;
2236 wr32(rx_ring->itr_register,
2237 1000000000 / (new_val * 256));
2238 }
2239}
2240
2241static void igb_raise_rx_eitr(struct igb_adapter *adapter,
2242 struct igb_ring *rx_ring)
2243{
2244 struct e1000_hw *hw = &adapter->hw;
2245 int new_val;
2246
2247 new_val = rx_ring->itr_val * 2;
2248 if (new_val > IGB_MAX_DYN_ITR)
2249 new_val = IGB_MAX_DYN_ITR;
2250
2251 if (new_val != rx_ring->itr_val) {
2252 rx_ring->itr_val = new_val;
2253 wr32(rx_ring->itr_register,
2254 1000000000 / (new_val * 256));
2255 }
2256}
2257
2258/**
2259 * igb_update_itr - update the dynamic ITR value based on statistics
2260 * Stores a new ITR value based on packets and byte
2261 * counts during the last interrupt. The advantage of per interrupt
2262 * computation is faster updates and more accurate ITR for the current
2263 * traffic pattern. Constants in this function were computed
2264 * based on theoretical maximum wire speed and thresholds were set based
2265 * on testing data as well as attempting to minimize response time
2266 * while increasing bulk throughput.
2267 * this functionality is controlled by the InterruptThrottleRate module
2268 * parameter (see igb_param.c)
2269 * NOTE: These calculations are only valid when operating in a single-
2270 * queue environment.
2271 * @adapter: pointer to adapter
2272 * @itr_setting: current adapter->itr
2273 * @packets: the number of packets during this measurement interval
2274 * @bytes: the number of bytes during this measurement interval
2275 **/
2276static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2277 int packets, int bytes)
2278{
2279 unsigned int retval = itr_setting;
2280
2281 if (packets == 0)
2282 goto update_itr_done;
2283
2284 switch (itr_setting) {
2285 case lowest_latency:
2286 /* handle TSO and jumbo frames */
2287 if (bytes/packets > 8000)
2288 retval = bulk_latency;
2289 else if ((packets < 5) && (bytes > 512))
2290 retval = low_latency;
2291 break;
2292 case low_latency: /* 50 usec aka 20000 ints/s */
2293 if (bytes > 10000) {
2294 /* this if handles the TSO accounting */
2295 if (bytes/packets > 8000) {
2296 retval = bulk_latency;
2297 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2298 retval = bulk_latency;
2299 } else if ((packets > 35)) {
2300 retval = lowest_latency;
2301 }
2302 } else if (bytes/packets > 2000) {
2303 retval = bulk_latency;
2304 } else if (packets <= 2 && bytes < 512) {
2305 retval = lowest_latency;
2306 }
2307 break;
2308 case bulk_latency: /* 250 usec aka 4000 ints/s */
2309 if (bytes > 25000) {
2310 if (packets > 35)
2311 retval = low_latency;
2312 } else if (bytes < 6000) {
2313 retval = low_latency;
2314 }
2315 break;
2316 }
2317
2318update_itr_done:
2319 return retval;
2320}
2321
2322static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2323 int rx_only)
2324{
2325 u16 current_itr;
2326 u32 new_itr = adapter->itr;
2327
2328 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2329 if (adapter->link_speed != SPEED_1000) {
2330 current_itr = 0;
2331 new_itr = 4000;
2332 goto set_itr_now;
2333 }
2334
2335 adapter->rx_itr = igb_update_itr(adapter,
2336 adapter->rx_itr,
2337 adapter->rx_ring->total_packets,
2338 adapter->rx_ring->total_bytes);
2339 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2340 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2341 adapter->rx_itr = low_latency;
2342
2343 if (!rx_only) {
2344 adapter->tx_itr = igb_update_itr(adapter,
2345 adapter->tx_itr,
2346 adapter->tx_ring->total_packets,
2347 adapter->tx_ring->total_bytes);
2348 /* conservative mode (itr 3) eliminates the
2349 * lowest_latency setting */
2350 if (adapter->itr_setting == 3 &&
2351 adapter->tx_itr == lowest_latency)
2352 adapter->tx_itr = low_latency;
2353
2354 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2355 } else {
2356 current_itr = adapter->rx_itr;
2357 }
2358
2359 switch (current_itr) {
2360 /* counts and packets in update_itr are dependent on these numbers */
2361 case lowest_latency:
2362 new_itr = 70000;
2363 break;
2364 case low_latency:
2365 new_itr = 20000; /* aka hwitr = ~200 */
2366 break;
2367 case bulk_latency:
2368 new_itr = 4000;
2369 break;
2370 default:
2371 break;
2372 }
2373
2374set_itr_now:
2375 if (new_itr != adapter->itr) {
2376 /* this attempts to bias the interrupt rate towards Bulk
2377 * by adding intermediate steps when interrupt rate is
2378 * increasing */
2379 new_itr = new_itr > adapter->itr ?
2380 min(adapter->itr + (new_itr >> 2), new_itr) :
2381 new_itr;
2382 /* Don't write the value here; it resets the adapter's
2383 * internal timer, and causes us to delay far longer than
2384 * we should between interrupts. Instead, we write the ITR
2385 * value at the beginning of the next interrupt so the timing
2386 * ends up being correct.
2387 */
2388 adapter->itr = new_itr;
2389 adapter->set_itr = 1;
2390 }
2391
2392 return;
2393}
2394
2395
2396#define IGB_TX_FLAGS_CSUM 0x00000001
2397#define IGB_TX_FLAGS_VLAN 0x00000002
2398#define IGB_TX_FLAGS_TSO 0x00000004
2399#define IGB_TX_FLAGS_IPV4 0x00000008
2400#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2401#define IGB_TX_FLAGS_VLAN_SHIFT 16
2402
2403static inline int igb_tso_adv(struct igb_adapter *adapter,
2404 struct igb_ring *tx_ring,
2405 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2406{
2407 struct e1000_adv_tx_context_desc *context_desc;
2408 unsigned int i;
2409 int err;
2410 struct igb_buffer *buffer_info;
2411 u32 info = 0, tu_cmd = 0;
2412 u32 mss_l4len_idx, l4len;
2413 *hdr_len = 0;
2414
2415 if (skb_header_cloned(skb)) {
2416 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2417 if (err)
2418 return err;
2419 }
2420
2421 l4len = tcp_hdrlen(skb);
2422 *hdr_len += l4len;
2423
2424 if (skb->protocol == htons(ETH_P_IP)) {
2425 struct iphdr *iph = ip_hdr(skb);
2426 iph->tot_len = 0;
2427 iph->check = 0;
2428 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2429 iph->daddr, 0,
2430 IPPROTO_TCP,
2431 0);
2432 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2433 ipv6_hdr(skb)->payload_len = 0;
2434 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2435 &ipv6_hdr(skb)->daddr,
2436 0, IPPROTO_TCP, 0);
2437 }
2438
2439 i = tx_ring->next_to_use;
2440
2441 buffer_info = &tx_ring->buffer_info[i];
2442 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2443 /* VLAN MACLEN IPLEN */
2444 if (tx_flags & IGB_TX_FLAGS_VLAN)
2445 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2446 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2447 *hdr_len += skb_network_offset(skb);
2448 info |= skb_network_header_len(skb);
2449 *hdr_len += skb_network_header_len(skb);
2450 context_desc->vlan_macip_lens = cpu_to_le32(info);
2451
2452 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2453 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2454
2455 if (skb->protocol == htons(ETH_P_IP))
2456 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2457 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2458
2459 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2460
2461 /* MSS L4LEN IDX */
2462 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2463 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2464
2465 /* Context index must be unique per ring. Luckily, so is the interrupt
2466 * mask value. */
2467 mss_l4len_idx |= tx_ring->eims_value >> 4;
2468
2469 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2470 context_desc->seqnum_seed = 0;
2471
2472 buffer_info->time_stamp = jiffies;
2473 buffer_info->dma = 0;
2474 i++;
2475 if (i == tx_ring->count)
2476 i = 0;
2477
2478 tx_ring->next_to_use = i;
2479
2480 return true;
2481}
2482
2483static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2484 struct igb_ring *tx_ring,
2485 struct sk_buff *skb, u32 tx_flags)
2486{
2487 struct e1000_adv_tx_context_desc *context_desc;
2488 unsigned int i;
2489 struct igb_buffer *buffer_info;
2490 u32 info = 0, tu_cmd = 0;
2491
2492 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2493 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2494 i = tx_ring->next_to_use;
2495 buffer_info = &tx_ring->buffer_info[i];
2496 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2497
2498 if (tx_flags & IGB_TX_FLAGS_VLAN)
2499 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2500 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2501 if (skb->ip_summed == CHECKSUM_PARTIAL)
2502 info |= skb_network_header_len(skb);
2503
2504 context_desc->vlan_macip_lens = cpu_to_le32(info);
2505
2506 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2507
2508 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3
MW		 2509 switch (skb->protocol) {
2510 case __constant_htons(ETH_P_IP):
9d5c8243 2511 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2512 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2513 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2514 break;
2515 case __constant_htons(ETH_P_IPV6):
2516 /* XXX what about other V6 headers?? */
2517 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2518 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2519 break;
2520 default:
2521 if (unlikely(net_ratelimit()))
2522 dev_warn(&adapter->pdev->dev,
2523 "partial checksum but proto=%x!\n",
2524 skb->protocol);
2525 break;
2526 }
9d5c8243
AK		 2527 }
2528
2529 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2530 context_desc->seqnum_seed = 0;
2531 context_desc->mss_l4len_idx =
2532 cpu_to_le32(tx_ring->eims_value >> 4);
2533
2534 buffer_info->time_stamp = jiffies;
2535 buffer_info->dma = 0;
2536
2537 i++;
2538 if (i == tx_ring->count)
2539 i = 0;
2540 tx_ring->next_to_use = i;
2541
2542 return true;
2543 }
2544
2545
2546 return false;
2547}
2548
2549#define IGB_MAX_TXD_PWR 16
2550#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2551
2552static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2553 struct igb_ring *tx_ring,
2554 struct sk_buff *skb)
2555{
2556 struct igb_buffer *buffer_info;
2557 unsigned int len = skb_headlen(skb);
2558 unsigned int count = 0, i;
2559 unsigned int f;
2560
2561 i = tx_ring->next_to_use;
2562
2563 buffer_info = &tx_ring->buffer_info[i];
2564 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2565 buffer_info->length = len;
2566 /* set time_stamp *before* dma to help avoid a possible race */
2567 buffer_info->time_stamp = jiffies;
2568 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2569 PCI_DMA_TODEVICE);
2570 count++;
2571 i++;
2572 if (i == tx_ring->count)
2573 i = 0;
2574
2575 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2576 struct skb_frag_struct *frag;
2577
2578 frag = &skb_shinfo(skb)->frags[f];
2579 len = frag->size;
2580
2581 buffer_info = &tx_ring->buffer_info[i];
2582 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2583 buffer_info->length = len;
2584 buffer_info->time_stamp = jiffies;
2585 buffer_info->dma = pci_map_page(adapter->pdev,
2586 frag->page,
2587 frag->page_offset,
2588 len,
2589 PCI_DMA_TODEVICE);
2590
2591 count++;
2592 i++;
2593 if (i == tx_ring->count)
2594 i = 0;
2595 }
2596
2597 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2598 tx_ring->buffer_info[i].skb = skb;
2599
2600 return count;
2601}
2602
2603static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2604 struct igb_ring *tx_ring,
2605 int tx_flags, int count, u32 paylen,
2606 u8 hdr_len)
2607{
2608 union e1000_adv_tx_desc *tx_desc = NULL;
2609 struct igb_buffer *buffer_info;
2610 u32 olinfo_status = 0, cmd_type_len;
2611 unsigned int i;
2612
2613 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2614 E1000_ADVTXD_DCMD_DEXT);
2615
2616 if (tx_flags & IGB_TX_FLAGS_VLAN)
2617 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2618
2619 if (tx_flags & IGB_TX_FLAGS_TSO) {
2620 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2621
2622 /* insert tcp checksum */
2623 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2624
2625 /* insert ip checksum */
2626 if (tx_flags & IGB_TX_FLAGS_IPV4)
2627 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2628
2629 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2630 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2631 }
2632
2633 if (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2634 IGB_TX_FLAGS_VLAN))
2635 olinfo_status |= tx_ring->eims_value >> 4;
2636
2637 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2638
2639 i = tx_ring->next_to_use;
2640 while (count--) {
2641 buffer_info = &tx_ring->buffer_info[i];
2642 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2643 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2644 tx_desc->read.cmd_type_len =
2645 cpu_to_le32(cmd_type_len | buffer_info->length);
2646 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2647 i++;
2648 if (i == tx_ring->count)
2649 i = 0;
2650 }
2651
2652 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2653 /* Force memory writes to complete before letting h/w
2654 * know there are new descriptors to fetch. (Only
2655 * applicable for weak-ordered memory model archs,
2656 * such as IA-64). */
2657 wmb();
2658
2659 tx_ring->next_to_use = i;
2660 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2661 /* we need this if more than one processor can write to our tail
2662 * at a time, it syncronizes IO on IA64/Altix systems */
2663 mmiowb();
2664}
2665
2666static int __igb_maybe_stop_tx(struct net_device *netdev,
2667 struct igb_ring *tx_ring, int size)
2668{
2669 struct igb_adapter *adapter = netdev_priv(netdev);
2670
2671 netif_stop_queue(netdev);
2672 /* Herbert's original patch had:
2673 * smp_mb__after_netif_stop_queue();
2674 * but since that doesn't exist yet, just open code it. */
2675 smp_mb();
2676
2677 /* We need to check again in a case another CPU has just
2678 * made room available. */
2679 if (IGB_DESC_UNUSED(tx_ring) < size)
2680 return -EBUSY;
2681
2682 /* A reprieve! */
2683 netif_start_queue(netdev);
2684 ++adapter->restart_queue;
2685 return 0;
2686}
2687
2688static int igb_maybe_stop_tx(struct net_device *netdev,
2689 struct igb_ring *tx_ring, int size)
2690{
2691 if (IGB_DESC_UNUSED(tx_ring) >= size)
2692 return 0;
2693 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2694}
2695
2696#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2697
2698static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2699 struct net_device *netdev,
2700 struct igb_ring *tx_ring)
2701{
2702 struct igb_adapter *adapter = netdev_priv(netdev);
2703 unsigned int tx_flags = 0;
2704 unsigned int len;
2705 unsigned long irq_flags;
2706 u8 hdr_len = 0;
2707 int tso = 0;
2708
2709 len = skb_headlen(skb);
2710
2711 if (test_bit(__IGB_DOWN, &adapter->state)) {
2712 dev_kfree_skb_any(skb);
2713 return NETDEV_TX_OK;
2714 }
2715
2716 if (skb->len <= 0) {
2717 dev_kfree_skb_any(skb);
2718 return NETDEV_TX_OK;
2719 }
2720
2721 if (!spin_trylock_irqsave(&tx_ring->tx_lock, irq_flags))
2722 /* Collision - tell upper layer to requeue */
2723 return NETDEV_TX_LOCKED;
2724
2725 /* need: 1 descriptor per page,
2726 * + 2 desc gap to keep tail from touching head,
2727 * + 1 desc for skb->data,
2728 * + 1 desc for context descriptor,
2729 * otherwise try next time */
2730 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2731 /* this is a hard error */
2732 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2733 return NETDEV_TX_BUSY;
2734 }
2735
2736 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2737 tx_flags |= IGB_TX_FLAGS_VLAN;
2738 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2739 }
2740
2741 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2742 &hdr_len) : 0;
2743
2744 if (tso < 0) {
2745 dev_kfree_skb_any(skb);
2746 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2747 return NETDEV_TX_OK;
2748 }
2749
2750 if (tso)
2751 tx_flags |= IGB_TX_FLAGS_TSO;
2752 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2753 if (skb->ip_summed == CHECKSUM_PARTIAL)
2754 tx_flags |= IGB_TX_FLAGS_CSUM;
2755
2756 if (skb->protocol == htons(ETH_P_IP))
2757 tx_flags |= IGB_TX_FLAGS_IPV4;
2758
2759 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2760 igb_tx_map_adv(adapter, tx_ring, skb),
2761 skb->len, hdr_len);
2762
2763 netdev->trans_start = jiffies;
2764
2765 /* Make sure there is space in the ring for the next send. */
2766 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2767
2768 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2769 return NETDEV_TX_OK;
2770}
2771
2772static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2773{
2774 struct igb_adapter *adapter = netdev_priv(netdev);
2775 struct igb_ring *tx_ring = &adapter->tx_ring[0];
2776
2777 /* This goes back to the question of how to logically map a tx queue
2778 * to a flow. Right now, performance is impacted slightly negatively
2779 * if using multiple tx queues. If the stack breaks away from a
2780 * single qdisc implementation, we can look at this again. */
2781 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
2782}
2783
2784/**
2785 * igb_tx_timeout - Respond to a Tx Hang
2786 * @netdev: network interface device structure
2787 **/
2788static void igb_tx_timeout(struct net_device *netdev)
2789{
2790 struct igb_adapter *adapter = netdev_priv(netdev);
2791 struct e1000_hw *hw = &adapter->hw;
2792
2793 /* Do the reset outside of interrupt context */
2794 adapter->tx_timeout_count++;
2795 schedule_work(&adapter->reset_task);
2796 wr32(E1000_EICS, adapter->eims_enable_mask &
2797 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
2798}
2799
2800static void igb_reset_task(struct work_struct *work)
2801{
2802 struct igb_adapter *adapter;
2803 adapter = container_of(work, struct igb_adapter, reset_task);
2804
2805 igb_reinit_locked(adapter);
2806}
2807
2808/**
2809 * igb_get_stats - Get System Network Statistics
2810 * @netdev: network interface device structure
2811 *
2812 * Returns the address of the device statistics structure.
2813 * The statistics are actually updated from the timer callback.
2814 **/
2815static struct net_device_stats *
2816igb_get_stats(struct net_device *netdev)
2817{
2818 struct igb_adapter *adapter = netdev_priv(netdev);
2819
2820 /* only return the current stats */
2821 return &adapter->net_stats;
2822}
2823
2824/**
2825 * igb_change_mtu - Change the Maximum Transfer Unit
2826 * @netdev: network interface device structure
2827 * @new_mtu: new value for maximum frame size
2828 *
2829 * Returns 0 on success, negative on failure
2830 **/
2831static int igb_change_mtu(struct net_device *netdev, int new_mtu)
2832{
2833 struct igb_adapter *adapter = netdev_priv(netdev);
2834 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2835
2836 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2837 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2838 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
2839 return -EINVAL;
2840 }
2841
2842#define MAX_STD_JUMBO_FRAME_SIZE 9234
2843 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
2844 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
2845 return -EINVAL;
2846 }
2847
2848 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2849 msleep(1);
2850 /* igb_down has a dependency on max_frame_size */
2851 adapter->max_frame_size = max_frame;
2852 if (netif_running(netdev))
2853 igb_down(adapter);
2854
2855 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
2856 * means we reserve 2 more, this pushes us to allocate from the next
2857 * larger slab size.
2858 * i.e. RXBUFFER_2048 --> size-4096 slab
2859 */
2860
2861 if (max_frame <= IGB_RXBUFFER_256)
2862 adapter->rx_buffer_len = IGB_RXBUFFER_256;
2863 else if (max_frame <= IGB_RXBUFFER_512)
2864 adapter->rx_buffer_len = IGB_RXBUFFER_512;
2865 else if (max_frame <= IGB_RXBUFFER_1024)
2866 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
2867 else if (max_frame <= IGB_RXBUFFER_2048)
2868 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
2869 else
2870 adapter->rx_buffer_len = IGB_RXBUFFER_4096;
2871 /* adjust allocation if LPE protects us, and we aren't using SBP */
2872 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
2873 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
2874 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2875
2876 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
2877 netdev->mtu, new_mtu);
2878 netdev->mtu = new_mtu;
2879
2880 if (netif_running(netdev))
2881 igb_up(adapter);
2882 else
2883 igb_reset(adapter);
2884
2885 clear_bit(__IGB_RESETTING, &adapter->state);
2886
2887 return 0;
2888}
2889
2890/**
2891 * igb_update_stats - Update the board statistics counters
2892 * @adapter: board private structure
2893 **/
2894
2895void igb_update_stats(struct igb_adapter *adapter)
2896{
2897 struct e1000_hw *hw = &adapter->hw;
2898 struct pci_dev *pdev = adapter->pdev;
2899 u16 phy_tmp;
2900
2901#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
2902
2903 /*
2904 * Prevent stats update while adapter is being reset, or if the pci
2905 * connection is down.
2906 */
2907 if (adapter->link_speed == 0)
2908 return;
2909 if (pci_channel_offline(pdev))
2910 return;
2911
2912 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
2913 adapter->stats.gprc += rd32(E1000_GPRC);
2914 adapter->stats.gorc += rd32(E1000_GORCL);
2915 rd32(E1000_GORCH); /* clear GORCL */
2916 adapter->stats.bprc += rd32(E1000_BPRC);
2917 adapter->stats.mprc += rd32(E1000_MPRC);
2918 adapter->stats.roc += rd32(E1000_ROC);
2919
2920 adapter->stats.prc64 += rd32(E1000_PRC64);
2921 adapter->stats.prc127 += rd32(E1000_PRC127);
2922 adapter->stats.prc255 += rd32(E1000_PRC255);
2923 adapter->stats.prc511 += rd32(E1000_PRC511);
2924 adapter->stats.prc1023 += rd32(E1000_PRC1023);
2925 adapter->stats.prc1522 += rd32(E1000_PRC1522);
2926 adapter->stats.symerrs += rd32(E1000_SYMERRS);
2927 adapter->stats.sec += rd32(E1000_SEC);
2928
2929 adapter->stats.mpc += rd32(E1000_MPC);
2930 adapter->stats.scc += rd32(E1000_SCC);
2931 adapter->stats.ecol += rd32(E1000_ECOL);
2932 adapter->stats.mcc += rd32(E1000_MCC);
2933 adapter->stats.latecol += rd32(E1000_LATECOL);
2934 adapter->stats.dc += rd32(E1000_DC);
2935 adapter->stats.rlec += rd32(E1000_RLEC);
2936 adapter->stats.xonrxc += rd32(E1000_XONRXC);
2937 adapter->stats.xontxc += rd32(E1000_XONTXC);
2938 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
2939 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
2940 adapter->stats.fcruc += rd32(E1000_FCRUC);
2941 adapter->stats.gptc += rd32(E1000_GPTC);
2942 adapter->stats.gotc += rd32(E1000_GOTCL);
2943 rd32(E1000_GOTCH); /* clear GOTCL */
2944 adapter->stats.rnbc += rd32(E1000_RNBC);
2945 adapter->stats.ruc += rd32(E1000_RUC);
2946 adapter->stats.rfc += rd32(E1000_RFC);
2947 adapter->stats.rjc += rd32(E1000_RJC);
2948 adapter->stats.tor += rd32(E1000_TORH);
2949 adapter->stats.tot += rd32(E1000_TOTH);
2950 adapter->stats.tpr += rd32(E1000_TPR);
2951
2952 adapter->stats.ptc64 += rd32(E1000_PTC64);
2953 adapter->stats.ptc127 += rd32(E1000_PTC127);
2954 adapter->stats.ptc255 += rd32(E1000_PTC255);
2955 adapter->stats.ptc511 += rd32(E1000_PTC511);
2956 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
2957 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
2958
2959 adapter->stats.mptc += rd32(E1000_MPTC);
2960 adapter->stats.bptc += rd32(E1000_BPTC);
2961
2962 /* used for adaptive IFS */
2963
2964 hw->mac.tx_packet_delta = rd32(E1000_TPT);
2965 adapter->stats.tpt += hw->mac.tx_packet_delta;
2966 hw->mac.collision_delta = rd32(E1000_COLC);
2967 adapter->stats.colc += hw->mac.collision_delta;
2968
2969 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
2970 adapter->stats.rxerrc += rd32(E1000_RXERRC);
2971 adapter->stats.tncrs += rd32(E1000_TNCRS);
2972 adapter->stats.tsctc += rd32(E1000_TSCTC);
2973 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
2974
2975 adapter->stats.iac += rd32(E1000_IAC);
2976 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
2977 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
2978 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
2979 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
2980 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
2981 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
2982 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
2983 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
2984
2985 /* Fill out the OS statistics structure */
2986 adapter->net_stats.multicast = adapter->stats.mprc;
2987 adapter->net_stats.collisions = adapter->stats.colc;
2988
2989 /* Rx Errors */
2990
2991 /* RLEC on some newer hardware can be incorrect so build
2992 * our own version based on RUC and ROC */
2993 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
2994 adapter->stats.crcerrs + adapter->stats.algnerrc +
2995 adapter->stats.ruc + adapter->stats.roc +
2996 adapter->stats.cexterr;
2997 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
2998 adapter->stats.roc;
2999 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3000 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3001 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3002
3003 /* Tx Errors */
3004 adapter->net_stats.tx_errors = adapter->stats.ecol +
3005 adapter->stats.latecol;
3006 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3007 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3008 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3009
3010 /* Tx Dropped needs to be maintained elsewhere */
3011
3012 /* Phy Stats */
3013 if (hw->phy.media_type == e1000_media_type_copper) {
3014 if ((adapter->link_speed == SPEED_1000) &&
3015 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
3016 &phy_tmp))) {
3017 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3018 adapter->phy_stats.idle_errors += phy_tmp;
3019 }
3020 }
3021
3022 /* Management Stats */
3023 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3024 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3025 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3026}
3027
3028
3029static irqreturn_t igb_msix_other(int irq, void *data)
3030{
3031 struct net_device *netdev = data;
3032 struct igb_adapter *adapter = netdev_priv(netdev);
3033 struct e1000_hw *hw = &adapter->hw;
3034 u32 eicr;
3035 /* disable interrupts from the "other" bit, avoid re-entry */
3036 wr32(E1000_EIMC, E1000_EIMS_OTHER);
3037
3038 eicr = rd32(E1000_EICR);
3039
3040 if (eicr & E1000_EIMS_OTHER) {
3041 u32 icr = rd32(E1000_ICR);
3042 /* reading ICR causes bit 31 of EICR to be cleared */
3043 if (!(icr & E1000_ICR_LSC))
3044 goto no_link_interrupt;
3045 hw->mac.get_link_status = 1;
3046 /* guard against interrupt when we're going down */
3047 if (!test_bit(__IGB_DOWN, &adapter->state))
3048 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3049 }
3050
3051no_link_interrupt:
3052 wr32(E1000_IMS, E1000_IMS_LSC);
3053 wr32(E1000_EIMS, E1000_EIMS_OTHER);
3054
3055 return IRQ_HANDLED;
3056}
3057
3058static irqreturn_t igb_msix_tx(int irq, void *data)
3059{
3060 struct igb_ring *tx_ring = data;
3061 struct igb_adapter *adapter = tx_ring->adapter;
3062 struct e1000_hw *hw = &adapter->hw;
3063
3064 if (!tx_ring->itr_val)
3065 wr32(E1000_EIMC, tx_ring->eims_value);
3066
3067 tx_ring->total_bytes = 0;
3068 tx_ring->total_packets = 0;
3b644cf6 3069 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3070 /* Ring was not completely cleaned, so fire another interrupt */
3071 wr32(E1000_EICS, tx_ring->eims_value);
3072
3073 if (!tx_ring->itr_val)
3074 wr32(E1000_EIMS, tx_ring->eims_value);
3075 return IRQ_HANDLED;
3076}
3077
3078static irqreturn_t igb_msix_rx(int irq, void *data)
3079{
3080 struct igb_ring *rx_ring = data;
3081 struct igb_adapter *adapter = rx_ring->adapter;
3082 struct e1000_hw *hw = &adapter->hw;
3083
3084 if (!rx_ring->itr_val)
3085 wr32(E1000_EIMC, rx_ring->eims_value);
3086
3087 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi)) {
3088 rx_ring->total_bytes = 0;
3089 rx_ring->total_packets = 0;
3090 rx_ring->no_itr_adjust = 0;
3091 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3092 } else {
3093 if (!rx_ring->no_itr_adjust) {
3094 igb_lower_rx_eitr(adapter, rx_ring);
3095 rx_ring->no_itr_adjust = 1;
3096 }
3097 }
3098
3099 return IRQ_HANDLED;
3100}
3101
3102
3103/**
3104 * igb_intr_msi - Interrupt Handler
3105 * @irq: interrupt number
3106 * @data: pointer to a network interface device structure
3107 **/
3108static irqreturn_t igb_intr_msi(int irq, void *data)
3109{
3110 struct net_device *netdev = data;
3111 struct igb_adapter *adapter = netdev_priv(netdev);
3112 struct napi_struct *napi = &adapter->napi;
3113 struct e1000_hw *hw = &adapter->hw;
3114 /* read ICR disables interrupts using IAM */
3115 u32 icr = rd32(E1000_ICR);
3116
3117 /* Write the ITR value calculated at the end of the
3118 * previous interrupt.
3119 */
3120 if (adapter->set_itr) {
3121 wr32(E1000_ITR,
3122 1000000000 / (adapter->itr * 256));
3123 adapter->set_itr = 0;
3124 }
3125
3126 /* read ICR disables interrupts using IAM */
3127 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3128 hw->mac.get_link_status = 1;
3129 if (!test_bit(__IGB_DOWN, &adapter->state))
3130 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3131 }
3132
3133 if (netif_rx_schedule_prep(netdev, napi)) {
3134 adapter->tx_ring->total_bytes = 0;
3135 adapter->tx_ring->total_packets = 0;
3136 adapter->rx_ring->total_bytes = 0;
3137 adapter->rx_ring->total_packets = 0;
3138 __netif_rx_schedule(netdev, napi);
3139 }
3140
3141 return IRQ_HANDLED;
3142}
3143
3144/**
3145 * igb_intr - Interrupt Handler
3146 * @irq: interrupt number
3147 * @data: pointer to a network interface device structure
3148 **/
3149static irqreturn_t igb_intr(int irq, void *data)
3150{
3151 struct net_device *netdev = data;
3152 struct igb_adapter *adapter = netdev_priv(netdev);
3153 struct napi_struct *napi = &adapter->napi;
3154 struct e1000_hw *hw = &adapter->hw;
3155 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3156 * need for the IMC write */
3157 u32 icr = rd32(E1000_ICR);
3158 u32 eicr = 0;
3159 if (!icr)
3160 return IRQ_NONE; /* Not our interrupt */
3161
3162 /* Write the ITR value calculated at the end of the
3163 * previous interrupt.
3164 */
3165 if (adapter->set_itr) {
3166 wr32(E1000_ITR,
3167 1000000000 / (adapter->itr * 256));
3168 adapter->set_itr = 0;
3169 }
3170
3171 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3172 * not set, then the adapter didn't send an interrupt */
3173 if (!(icr & E1000_ICR_INT_ASSERTED))
3174 return IRQ_NONE;
3175
3176 eicr = rd32(E1000_EICR);
3177
3178 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3179 hw->mac.get_link_status = 1;
3180 /* guard against interrupt when we're going down */
3181 if (!test_bit(__IGB_DOWN, &adapter->state))
3182 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3183 }
3184
3185 if (netif_rx_schedule_prep(netdev, napi)) {
3186 adapter->tx_ring->total_bytes = 0;
3187 adapter->rx_ring->total_bytes = 0;
3188 adapter->tx_ring->total_packets = 0;
3189 adapter->rx_ring->total_packets = 0;
3190 __netif_rx_schedule(netdev, napi);
3191 }
3192
3193 return IRQ_HANDLED;
3194}
3195
3196/**
3197 * igb_clean - NAPI Rx polling callback
3198 * @adapter: board private structure
3199 **/
3200static int igb_clean(struct napi_struct *napi, int budget)
3201{
3202 struct igb_adapter *adapter = container_of(napi, struct igb_adapter,
3203 napi);
3204 struct net_device *netdev = adapter->netdev;
3205 int tx_clean_complete = 1, work_done = 0;
3206 int i;
3207
3208 /* Must NOT use netdev_priv macro here. */
3209 adapter = netdev->priv;
3210
3211 /* Keep link state information with original netdev */
3212 if (!netif_carrier_ok(netdev))
3213 goto quit_polling;
3214
3215 /* igb_clean is called per-cpu. This lock protects tx_ring[i] from
3216 * being cleaned by multiple cpus simultaneously. A failure obtaining
3217 * the lock means tx_ring[i] is currently being cleaned anyway. */
3218 for (i = 0; i < adapter->num_tx_queues; i++) {
3219 if (spin_trylock(&adapter->tx_ring[i].tx_clean_lock)) {
3b644cf6 3220 tx_clean_complete &= igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 3221 spin_unlock(&adapter->tx_ring[i].tx_clean_lock);
3222 }
3223 }
3224
3225 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 3226 igb_clean_rx_irq_adv(&adapter->rx_ring[i], &work_done,
9d5c8243
AK		 3227 adapter->rx_ring[i].napi.weight);
3228
3229 /* If no Tx and not enough Rx work done, exit the polling mode */
3230 if ((tx_clean_complete && (work_done < budget)) ||
3231 !netif_running(netdev)) {
3232quit_polling:
3233 if (adapter->itr_setting & 3)
3234 igb_set_itr(adapter, E1000_ITR, false);
3235 netif_rx_complete(netdev, napi);
3236 if (!test_bit(__IGB_DOWN, &adapter->state))
3237 igb_irq_enable(adapter);
3238 return 0;
3239 }
3240
3241 return 1;
3242}
3243
3244static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3245{
3246 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3247 struct igb_adapter *adapter = rx_ring->adapter;
3248 struct e1000_hw *hw = &adapter->hw;
3249 struct net_device *netdev = adapter->netdev;
3250 int work_done = 0;
3251
3252 /* Keep link state information with original netdev */
3253 if (!netif_carrier_ok(netdev))
3254 goto quit_polling;
3255
3b644cf6 3256 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3257
3258
3259 /* If not enough Rx work done, exit the polling mode */
3260 if ((work_done == 0) || !netif_running(netdev)) {
3261quit_polling:
3262 netif_rx_complete(netdev, napi);
3263
3264 wr32(E1000_EIMS, rx_ring->eims_value);
3265 if ((adapter->itr_setting & 3) && !rx_ring->no_itr_adjust &&
3266 (rx_ring->total_packets > IGB_DYN_ITR_PACKET_THRESHOLD)) {
3267 int mean_size = rx_ring->total_bytes /
3268 rx_ring->total_packets;
3269 if (mean_size < IGB_DYN_ITR_LENGTH_LOW)
3270 igb_raise_rx_eitr(adapter, rx_ring);
3271 else if (mean_size > IGB_DYN_ITR_LENGTH_HIGH)
3272 igb_lower_rx_eitr(adapter, rx_ring);
3273 }
3274 return 0;
3275 }
3276
3277 return 1;
3278}
6d8126f9
AV		 3279
3280static inline u32 get_head(struct igb_ring *tx_ring)
3281{
3282 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3283 return le32_to_cpu(*(volatile __le32 *)end);
3284}
3285
9d5c8243
AK		 3286/**
3287 * igb_clean_tx_irq - Reclaim resources after transmit completes
3288 * @adapter: board private structure
3289 * returns true if ring is completely cleaned
3290 **/
3b644cf6 3291static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3292{
3b644cf6 3293 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243 3294 struct e1000_hw *hw = &adapter->hw;
3b644cf6 3295 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3296 struct e1000_tx_desc *tx_desc;
3297 struct igb_buffer *buffer_info;
3298 struct sk_buff *skb;
3299 unsigned int i;
3300 u32 head, oldhead;
3301 unsigned int count = 0;
3302 bool cleaned = false;
3303 bool retval = true;
3304 unsigned int total_bytes = 0, total_packets = 0;
3305
3306 rmb();
6d8126f9 3307 head = get_head(tx_ring);
9d5c8243
AK		 3308 i = tx_ring->next_to_clean;
3309 while (1) {
3310 while (i != head) {
3311 cleaned = true;
3312 tx_desc = E1000_TX_DESC(*tx_ring, i);
3313 buffer_info = &tx_ring->buffer_info[i];
3314 skb = buffer_info->skb;
3315
3316 if (skb) {
3317 unsigned int segs, bytecount;
3318 /* gso_segs is currently only valid for tcp */
3319 segs = skb_shinfo(skb)->gso_segs ?: 1;
3320 /* multiply data chunks by size of headers */
3321 bytecount = ((segs - 1) * skb_headlen(skb)) +
3322 skb->len;
3323 total_packets += segs;
3324 total_bytes += bytecount;
3325 }
3326
3327 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3328 tx_desc->upper.data = 0;
3329
3330 i++;
3331 if (i == tx_ring->count)
3332 i = 0;
3333
3334 count++;
3335 if (count == IGB_MAX_TX_CLEAN) {
3336 retval = false;
3337 goto done_cleaning;
3338 }
3339 }
3340 oldhead = head;
3341 rmb();
6d8126f9 3342 head = get_head(tx_ring);
9d5c8243
AK		 3343 if (head == oldhead)
3344 goto done_cleaning;
3345 } /* while (1) */
3346
3347done_cleaning:
3348 tx_ring->next_to_clean = i;
3349
3350 if (unlikely(cleaned &&
3351 netif_carrier_ok(netdev) &&
3352 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3353 /* Make sure that anybody stopping the queue after this
3354 * sees the new next_to_clean.
3355 */
3356 smp_mb();
3357 if (netif_queue_stopped(netdev) &&
3358 !(test_bit(__IGB_DOWN, &adapter->state))) {
3359 netif_wake_queue(netdev);
3360 ++adapter->restart_queue;
3361 }
3362 }
3363
3364 if (tx_ring->detect_tx_hung) {
3365 /* Detect a transmit hang in hardware, this serializes the
3366 * check with the clearing of time_stamp and movement of i */
3367 tx_ring->detect_tx_hung = false;
3368 if (tx_ring->buffer_info[i].time_stamp &&
3369 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3370 (adapter->tx_timeout_factor * HZ))
3371 && !(rd32(E1000_STATUS) &
3372 E1000_STATUS_TXOFF)) {
3373
3374 tx_desc = E1000_TX_DESC(*tx_ring, i);
3375 /* detected Tx unit hang */
3376 dev_err(&adapter->pdev->dev,
3377 "Detected Tx Unit Hang\n"
3378 " Tx Queue <%lu>\n"
3379 " TDH <%x>\n"
3380 " TDT <%x>\n"
3381 " next_to_use <%x>\n"
3382 " next_to_clean <%x>\n"
3383 " head (WB) <%x>\n"
3384 "buffer_info[next_to_clean]\n"
3385 " time_stamp <%lx>\n"
3386 " jiffies <%lx>\n"
3387 " desc.status <%x>\n",
3388 (unsigned long)((tx_ring - adapter->tx_ring) /
3389 sizeof(struct igb_ring)),
3390 readl(adapter->hw.hw_addr + tx_ring->head),
3391 readl(adapter->hw.hw_addr + tx_ring->tail),
3392 tx_ring->next_to_use,
3393 tx_ring->next_to_clean,
3394 head,
3395 tx_ring->buffer_info[i].time_stamp,
3396 jiffies,
3397 tx_desc->upper.fields.status);
3398 netif_stop_queue(netdev);
3399 }
3400 }
3401 tx_ring->total_bytes += total_bytes;
3402 tx_ring->total_packets += total_packets;
3403 adapter->net_stats.tx_bytes += total_bytes;
3404 adapter->net_stats.tx_packets += total_packets;
3405 return retval;
3406}
3407
3408
3409/**
3410 * igb_receive_skb - helper function to handle rx indications
3411 * @adapter: board private structure
3412 * @status: descriptor status field as written by hardware
3413 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3414 * @skb: pointer to sk_buff to be indicated to stack
3415 **/
6d8126f9 3416static void igb_receive_skb(struct igb_adapter *adapter, u8 status, __le16 vlan,
9d5c8243
AK		 3417 struct sk_buff *skb)
3418{
3419 if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
3420 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3421 le16_to_cpu(vlan) &
3422 E1000_RXD_SPC_VLAN_MASK);
3423 else
3424 netif_receive_skb(skb);
3425}
3426
3427
3428static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3429 u32 status_err, struct sk_buff *skb)
3430{
3431 skb->ip_summed = CHECKSUM_NONE;
3432
3433 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3434 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3435 return;
3436 /* TCP/UDP checksum error bit is set */
3437 if (status_err &
3438 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3439 /* let the stack verify checksum errors */
3440 adapter->hw_csum_err++;
3441 return;
3442 }
3443 /* It must be a TCP or UDP packet with a valid checksum */
3444 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3445 skb->ip_summed = CHECKSUM_UNNECESSARY;
3446
3447 adapter->hw_csum_good++;
3448}
3449
3b644cf6
MW		 3450static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3451 int *work_done, int budget)
9d5c8243 3452{
3b644cf6 3453 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3454 struct net_device *netdev = adapter->netdev;
3455 struct pci_dev *pdev = adapter->pdev;
3456 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3457 struct igb_buffer *buffer_info , *next_buffer;
3458 struct sk_buff *skb;
3459 unsigned int i, j;
3460 u32 length, hlen, staterr;
3461 bool cleaned = false;
3462 int cleaned_count = 0;
3463 unsigned int total_bytes = 0, total_packets = 0;
3464
3465 i = rx_ring->next_to_clean;
3466 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3467 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3468
3469 while (staterr & E1000_RXD_STAT_DD) {
3470 if (*work_done >= budget)
3471 break;
3472 (*work_done)++;
3473 buffer_info = &rx_ring->buffer_info[i];
3474
3475 /* HW will not DMA in data larger than the given buffer, even
3476 * if it parses the (NFS, of course) header to be larger. In
3477 * that case, it fills the header buffer and spills the rest
3478 * into the page.
3479 */
7deb07b1
AV		 3480 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3481 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
9d5c8243
AK		 3482 if (hlen > adapter->rx_ps_hdr_size)
3483 hlen = adapter->rx_ps_hdr_size;
3484
3485 length = le16_to_cpu(rx_desc->wb.upper.length);
3486 cleaned = true;
3487 cleaned_count++;
3488
3489 if (rx_ring->pending_skb != NULL) {
3490 skb = rx_ring->pending_skb;
3491 rx_ring->pending_skb = NULL;
3492 j = rx_ring->pending_skb_page;
3493 } else {
3494 skb = buffer_info->skb;
3495 prefetch(skb->data - NET_IP_ALIGN);
3496 buffer_info->skb = NULL;
3497 if (hlen) {
3498 pci_unmap_single(pdev, buffer_info->dma,
3499 adapter->rx_ps_hdr_size +
3500 NET_IP_ALIGN,
3501 PCI_DMA_FROMDEVICE);
3502 skb_put(skb, hlen);
3503 } else {
3504 pci_unmap_single(pdev, buffer_info->dma,
3505 adapter->rx_buffer_len +
3506 NET_IP_ALIGN,
3507 PCI_DMA_FROMDEVICE);
3508 skb_put(skb, length);
3509 goto send_up;
3510 }
3511 j = 0;
3512 }
3513
3514 while (length) {
3515 pci_unmap_page(pdev, buffer_info->page_dma,
3516 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3517 buffer_info->page_dma = 0;
3518 skb_fill_page_desc(skb, j, buffer_info->page,
3519 0, length);
3520 buffer_info->page = NULL;
3521
3522 skb->len += length;
3523 skb->data_len += length;
3524 skb->truesize += length;
3525 rx_desc->wb.upper.status_error = 0;
3526 if (staterr & E1000_RXD_STAT_EOP)
3527 break;
3528
3529 j++;
3530 cleaned_count++;
3531 i++;
3532 if (i == rx_ring->count)
3533 i = 0;
3534
3535 buffer_info = &rx_ring->buffer_info[i];
3536 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3537 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3538 length = le16_to_cpu(rx_desc->wb.upper.length);
3539 if (!(staterr & E1000_RXD_STAT_DD)) {
3540 rx_ring->pending_skb = skb;
3541 rx_ring->pending_skb_page = j;
3542 goto out;
3543 }
3544 }
3545send_up:
3546 pskb_trim(skb, skb->len - 4);
3547 i++;
3548 if (i == rx_ring->count)
3549 i = 0;
3550 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3551 prefetch(next_rxd);
3552 next_buffer = &rx_ring->buffer_info[i];
3553
3554 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3555 dev_kfree_skb_irq(skb);
3556 goto next_desc;
3557 }
3558 rx_ring->no_itr_adjust |= (staterr & E1000_RXD_STAT_DYNINT);
3559
3560 total_bytes += skb->len;
3561 total_packets++;
3562
3563 igb_rx_checksum_adv(adapter, staterr, skb);
3564
3565 skb->protocol = eth_type_trans(skb, netdev);
3566
3567 igb_receive_skb(adapter, staterr, rx_desc->wb.upper.vlan, skb);
3568
3569 netdev->last_rx = jiffies;
3570
3571next_desc:
3572 rx_desc->wb.upper.status_error = 0;
3573
3574 /* return some buffers to hardware, one at a time is too slow */
3575 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3576 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3577 cleaned_count = 0;
3578 }
3579
3580 /* use prefetched values */
3581 rx_desc = next_rxd;
3582 buffer_info = next_buffer;
3583
3584 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3585 }
3586out:
3587 rx_ring->next_to_clean = i;
3588 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3589
3590 if (cleaned_count)
3b644cf6 3591 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3592
3593 rx_ring->total_packets += total_packets;
3594 rx_ring->total_bytes += total_bytes;
3595 rx_ring->rx_stats.packets += total_packets;
3596 rx_ring->rx_stats.bytes += total_bytes;
3597 adapter->net_stats.rx_bytes += total_bytes;
3598 adapter->net_stats.rx_packets += total_packets;
3599 return cleaned;
3600}
3601
3602
3603/**
3604 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3605 * @adapter: address of board private structure
3606 **/
3b644cf6 3607static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3608 int cleaned_count)
3609{
3b644cf6 3610 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3611 struct net_device *netdev = adapter->netdev;
3612 struct pci_dev *pdev = adapter->pdev;
3613 union e1000_adv_rx_desc *rx_desc;
3614 struct igb_buffer *buffer_info;
3615 struct sk_buff *skb;
3616 unsigned int i;
3617
3618 i = rx_ring->next_to_use;
3619 buffer_info = &rx_ring->buffer_info[i];
3620
3621 while (cleaned_count--) {
3622 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3623
3624 if (adapter->rx_ps_hdr_size && !buffer_info->page) {
3625 buffer_info->page = alloc_page(GFP_ATOMIC);
3626 if (!buffer_info->page) {
3627 adapter->alloc_rx_buff_failed++;
3628 goto no_buffers;
3629 }
3630 buffer_info->page_dma =
3631 pci_map_page(pdev,
3632 buffer_info->page,
3633 0, PAGE_SIZE,
3634 PCI_DMA_FROMDEVICE);
3635 }
3636
3637 if (!buffer_info->skb) {
3638 int bufsz;
3639
3640 if (adapter->rx_ps_hdr_size)
3641 bufsz = adapter->rx_ps_hdr_size;
3642 else
3643 bufsz = adapter->rx_buffer_len;
3644 bufsz += NET_IP_ALIGN;
3645 skb = netdev_alloc_skb(netdev, bufsz);
3646
3647 if (!skb) {
3648 adapter->alloc_rx_buff_failed++;
3649 goto no_buffers;
3650 }
3651
3652 /* Make buffer alignment 2 beyond a 16 byte boundary
3653 * this will result in a 16 byte aligned IP header after
3654 * the 14 byte MAC header is removed
3655 */
3656 skb_reserve(skb, NET_IP_ALIGN);
3657
3658 buffer_info->skb = skb;
3659 buffer_info->dma = pci_map_single(pdev, skb->data,
3660 bufsz,
3661 PCI_DMA_FROMDEVICE);
3662
3663 }
3664 /* Refresh the desc even if buffer_addrs didn't change because
3665 * each write-back erases this info. */
3666 if (adapter->rx_ps_hdr_size) {
3667 rx_desc->read.pkt_addr =
3668 cpu_to_le64(buffer_info->page_dma);
3669 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
3670 } else {
3671 rx_desc->read.pkt_addr =
3672 cpu_to_le64(buffer_info->dma);
3673 rx_desc->read.hdr_addr = 0;
3674 }
3675
3676 i++;
3677 if (i == rx_ring->count)
3678 i = 0;
3679 buffer_info = &rx_ring->buffer_info[i];
3680 }
3681
3682no_buffers:
3683 if (rx_ring->next_to_use != i) {
3684 rx_ring->next_to_use = i;
3685 if (i == 0)
3686 i = (rx_ring->count - 1);
3687 else
3688 i--;
3689
3690 /* Force memory writes to complete before letting h/w
3691 * know there are new descriptors to fetch. (Only
3692 * applicable for weak-ordered memory model archs,
3693 * such as IA-64). */
3694 wmb();
3695 writel(i, adapter->hw.hw_addr + rx_ring->tail);
3696 }
3697}
3698
3699/**
3700 * igb_mii_ioctl -
3701 * @netdev:
3702 * @ifreq:
3703 * @cmd:
3704 **/
3705static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3706{
3707 struct igb_adapter *adapter = netdev_priv(netdev);
3708 struct mii_ioctl_data *data = if_mii(ifr);
3709
3710 if (adapter->hw.phy.media_type != e1000_media_type_copper)
3711 return -EOPNOTSUPP;
3712
3713 switch (cmd) {
3714 case SIOCGMIIPHY:
3715 data->phy_id = adapter->hw.phy.addr;
3716 break;
3717 case SIOCGMIIREG:
3718 if (!capable(CAP_NET_ADMIN))
3719 return -EPERM;
3720 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
3721 data->reg_num
3722 & 0x1F, &data->val_out))
3723 return -EIO;
3724 break;
3725 case SIOCSMIIREG:
3726 default:
3727 return -EOPNOTSUPP;
3728 }
3729 return 0;
3730}
3731
3732/**
3733 * igb_ioctl -
3734 * @netdev:
3735 * @ifreq:
3736 * @cmd:
3737 **/
3738static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3739{
3740 switch (cmd) {
3741 case SIOCGMIIPHY:
3742 case SIOCGMIIREG:
3743 case SIOCSMIIREG:
3744 return igb_mii_ioctl(netdev, ifr, cmd);
3745 default:
3746 return -EOPNOTSUPP;
3747 }
3748}
3749
3750static void igb_vlan_rx_register(struct net_device *netdev,
3751 struct vlan_group *grp)
3752{
3753 struct igb_adapter *adapter = netdev_priv(netdev);
3754 struct e1000_hw *hw = &adapter->hw;
3755 u32 ctrl, rctl;
3756
3757 igb_irq_disable(adapter);
3758 adapter->vlgrp = grp;
3759
3760 if (grp) {
3761 /* enable VLAN tag insert/strip */
3762 ctrl = rd32(E1000_CTRL);
3763 ctrl |= E1000_CTRL_VME;
3764 wr32(E1000_CTRL, ctrl);
3765
3766 /* enable VLAN receive filtering */
3767 rctl = rd32(E1000_RCTL);
3768 rctl |= E1000_RCTL_VFE;
3769 rctl &= ~E1000_RCTL_CFIEN;
3770 wr32(E1000_RCTL, rctl);
3771 igb_update_mng_vlan(adapter);
3772 wr32(E1000_RLPML,
3773 adapter->max_frame_size + VLAN_TAG_SIZE);
3774 } else {
3775 /* disable VLAN tag insert/strip */
3776 ctrl = rd32(E1000_CTRL);
3777 ctrl &= ~E1000_CTRL_VME;
3778 wr32(E1000_CTRL, ctrl);
3779
3780 /* disable VLAN filtering */
3781 rctl = rd32(E1000_RCTL);
3782 rctl &= ~E1000_RCTL_VFE;
3783 wr32(E1000_RCTL, rctl);
3784 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
3785 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3786 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
3787 }
3788 wr32(E1000_RLPML,
3789 adapter->max_frame_size);
3790 }
3791
3792 if (!test_bit(__IGB_DOWN, &adapter->state))
3793 igb_irq_enable(adapter);
3794}
3795
3796static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3797{
3798 struct igb_adapter *adapter = netdev_priv(netdev);
3799 struct e1000_hw *hw = &adapter->hw;
3800 u32 vfta, index;
3801
3802 if ((adapter->hw.mng_cookie.status &
3803 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3804 (vid == adapter->mng_vlan_id))
3805 return;
3806 /* add VID to filter table */
3807 index = (vid >> 5) & 0x7F;
3808 vfta = array_rd32(E1000_VFTA, index);
3809 vfta |= (1 << (vid & 0x1F));
3810 igb_write_vfta(&adapter->hw, index, vfta);
3811}
3812
3813static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3814{
3815 struct igb_adapter *adapter = netdev_priv(netdev);
3816 struct e1000_hw *hw = &adapter->hw;
3817 u32 vfta, index;
3818
3819 igb_irq_disable(adapter);
3820 vlan_group_set_device(adapter->vlgrp, vid, NULL);
3821
3822 if (!test_bit(__IGB_DOWN, &adapter->state))
3823 igb_irq_enable(adapter);
3824
3825 if ((adapter->hw.mng_cookie.status &
3826 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3827 (vid == adapter->mng_vlan_id)) {
3828 /* release control to f/w */
3829 igb_release_hw_control(adapter);
3830 return;
3831 }
3832
3833 /* remove VID from filter table */
3834 index = (vid >> 5) & 0x7F;
3835 vfta = array_rd32(E1000_VFTA, index);
3836 vfta &= ~(1 << (vid & 0x1F));
3837 igb_write_vfta(&adapter->hw, index, vfta);
3838}
3839
3840static void igb_restore_vlan(struct igb_adapter *adapter)
3841{
3842 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3843
3844 if (adapter->vlgrp) {
3845 u16 vid;
3846 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3847 if (!vlan_group_get_device(adapter->vlgrp, vid))
3848 continue;
3849 igb_vlan_rx_add_vid(adapter->netdev, vid);
3850 }
3851 }
3852}
3853
3854int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
3855{
3856 struct e1000_mac_info *mac = &adapter->hw.mac;
3857
3858 mac->autoneg = 0;
3859
3860 /* Fiber NICs only allow 1000 gbps Full duplex */
3861 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
3862 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
3863 dev_err(&adapter->pdev->dev,
3864 "Unsupported Speed/Duplex configuration\n");
3865 return -EINVAL;
3866 }
3867
3868 switch (spddplx) {
3869 case SPEED_10 + DUPLEX_HALF:
3870 mac->forced_speed_duplex = ADVERTISE_10_HALF;
3871 break;
3872 case SPEED_10 + DUPLEX_FULL:
3873 mac->forced_speed_duplex = ADVERTISE_10_FULL;
3874 break;
3875 case SPEED_100 + DUPLEX_HALF:
3876 mac->forced_speed_duplex = ADVERTISE_100_HALF;
3877 break;
3878 case SPEED_100 + DUPLEX_FULL:
3879 mac->forced_speed_duplex = ADVERTISE_100_FULL;
3880 break;
3881 case SPEED_1000 + DUPLEX_FULL:
3882 mac->autoneg = 1;
3883 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
3884 break;
3885 case SPEED_1000 + DUPLEX_HALF: /* not supported */
3886 default:
3887 dev_err(&adapter->pdev->dev,
3888 "Unsupported Speed/Duplex configuration\n");
3889 return -EINVAL;
3890 }
3891 return 0;
3892}
3893
3894
3895static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
3896{
3897 struct net_device *netdev = pci_get_drvdata(pdev);
3898 struct igb_adapter *adapter = netdev_priv(netdev);
3899 struct e1000_hw *hw = &adapter->hw;
3900 u32 ctrl, ctrl_ext, rctl, status;
3901 u32 wufc = adapter->wol;
3902#ifdef CONFIG_PM
3903 int retval = 0;
3904#endif
3905
3906 netif_device_detach(netdev);
3907
3908 if (netif_running(netdev)) {
3909 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3910 igb_down(adapter);
3911 igb_free_irq(adapter);
3912 }
3913
3914#ifdef CONFIG_PM
3915 retval = pci_save_state(pdev);
3916 if (retval)
3917 return retval;
3918#endif
3919
3920 status = rd32(E1000_STATUS);
3921 if (status & E1000_STATUS_LU)
3922 wufc &= ~E1000_WUFC_LNKC;
3923
3924 if (wufc) {
3925 igb_setup_rctl(adapter);
3926 igb_set_multi(netdev);
3927
3928 /* turn on all-multi mode if wake on multicast is enabled */
3929 if (wufc & E1000_WUFC_MC) {
3930 rctl = rd32(E1000_RCTL);
3931 rctl |= E1000_RCTL_MPE;
3932 wr32(E1000_RCTL, rctl);
3933 }
3934
3935 ctrl = rd32(E1000_CTRL);
3936 /* advertise wake from D3Cold */
3937 #define E1000_CTRL_ADVD3WUC 0x00100000
3938 /* phy power management enable */
3939 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
3940 ctrl |= E1000_CTRL_ADVD3WUC;
3941 wr32(E1000_CTRL, ctrl);
3942
3943 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3944 adapter->hw.phy.media_type ==
3945 e1000_media_type_internal_serdes) {
3946 /* keep the laser running in D3 */
3947 ctrl_ext = rd32(E1000_CTRL_EXT);
3948 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
3949 wr32(E1000_CTRL_EXT, ctrl_ext);
3950 }
3951
3952 /* Allow time for pending master requests to run */
3953 igb_disable_pcie_master(&adapter->hw);
3954
3955 wr32(E1000_WUC, E1000_WUC_PME_EN);
3956 wr32(E1000_WUFC, wufc);
3957 pci_enable_wake(pdev, PCI_D3hot, 1);
3958 pci_enable_wake(pdev, PCI_D3cold, 1);
3959 } else {
3960 wr32(E1000_WUC, 0);
3961 wr32(E1000_WUFC, 0);
3962 pci_enable_wake(pdev, PCI_D3hot, 0);
3963 pci_enable_wake(pdev, PCI_D3cold, 0);
3964 }
3965
9d5c8243
AK		 3966 /* make sure adapter isn't asleep if manageability is enabled */
3967 if (adapter->en_mng_pt) {
3968 pci_enable_wake(pdev, PCI_D3hot, 1);
3969 pci_enable_wake(pdev, PCI_D3cold, 1);
3970 }
3971
3972 /* Release control of h/w to f/w. If f/w is AMT enabled, this
3973 * would have already happened in close and is redundant. */
3974 igb_release_hw_control(adapter);
3975
3976 pci_disable_device(pdev);
3977
3978 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3979
3980 return 0;
3981}
3982
3983#ifdef CONFIG_PM
3984static int igb_resume(struct pci_dev *pdev)
3985{
3986 struct net_device *netdev = pci_get_drvdata(pdev);
3987 struct igb_adapter *adapter = netdev_priv(netdev);
3988 struct e1000_hw *hw = &adapter->hw;
3989 u32 err;
3990
3991 pci_set_power_state(pdev, PCI_D0);
3992 pci_restore_state(pdev);
42bfd33a
TI		 3993
3994 if (adapter->need_ioport)
3995 err = pci_enable_device(pdev);
3996 else
3997 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 3998 if (err) {
3999 dev_err(&pdev->dev,
4000 "igb: Cannot enable PCI device from suspend\n");
4001 return err;
4002 }
4003 pci_set_master(pdev);
4004
4005 pci_enable_wake(pdev, PCI_D3hot, 0);
4006 pci_enable_wake(pdev, PCI_D3cold, 0);
4007
4008 if (netif_running(netdev)) {
4009 err = igb_request_irq(adapter);
4010 if (err)
4011 return err;
4012 }
4013
4014 /* e1000_power_up_phy(adapter); */
4015
4016 igb_reset(adapter);
4017 wr32(E1000_WUS, ~0);
4018
4019 igb_init_manageability(adapter);
4020
4021 if (netif_running(netdev))
4022 igb_up(adapter);
4023
4024 netif_device_attach(netdev);
4025
4026 /* let the f/w know that the h/w is now under the control of the
4027 * driver. */
4028 igb_get_hw_control(adapter);
4029
4030 return 0;
4031}
4032#endif
4033
4034static void igb_shutdown(struct pci_dev *pdev)
4035{
4036 igb_suspend(pdev, PMSG_SUSPEND);
4037}
4038
4039#ifdef CONFIG_NET_POLL_CONTROLLER
4040/*
4041 * Polling 'interrupt' - used by things like netconsole to send skbs
4042 * without having to re-enable interrupts. It's not called while
4043 * the interrupt routine is executing.
4044 */
4045static void igb_netpoll(struct net_device *netdev)
4046{
4047 struct igb_adapter *adapter = netdev_priv(netdev);
4048 int i;
4049 int work_done = 0;
4050
4051 igb_irq_disable(adapter);
4052 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4053 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4054
4055 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4056 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4057 &work_done,
4058 adapter->rx_ring[i].napi.weight);
4059
4060 igb_irq_enable(adapter);
4061}
4062#endif /* CONFIG_NET_POLL_CONTROLLER */
4063
4064/**
4065 * igb_io_error_detected - called when PCI error is detected
4066 * @pdev: Pointer to PCI device
4067 * @state: The current pci connection state
4068 *
4069 * This function is called after a PCI bus error affecting
4070 * this device has been detected.
4071 */
4072static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4073 pci_channel_state_t state)
4074{
4075 struct net_device *netdev = pci_get_drvdata(pdev);
4076 struct igb_adapter *adapter = netdev_priv(netdev);
4077
4078 netif_device_detach(netdev);
4079
4080 if (netif_running(netdev))
4081 igb_down(adapter);
4082 pci_disable_device(pdev);
4083
4084 /* Request a slot slot reset. */
4085 return PCI_ERS_RESULT_NEED_RESET;
4086}
4087
4088/**
4089 * igb_io_slot_reset - called after the pci bus has been reset.
4090 * @pdev: Pointer to PCI device
4091 *
4092 * Restart the card from scratch, as if from a cold-boot. Implementation
4093 * resembles the first-half of the igb_resume routine.
4094 */
4095static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4096{
4097 struct net_device *netdev = pci_get_drvdata(pdev);
4098 struct igb_adapter *adapter = netdev_priv(netdev);
4099 struct e1000_hw *hw = &adapter->hw;
42bfd33a 4100 int err;
9d5c8243 4101
42bfd33a
TI		 4102 if (adapter->need_ioport)
4103 err = pci_enable_device(pdev);
4104 else
4105 err = pci_enable_device_mem(pdev);
4106 if (err) {
9d5c8243
AK		 4107 dev_err(&pdev->dev,
4108 "Cannot re-enable PCI device after reset.\n");
4109 return PCI_ERS_RESULT_DISCONNECT;
4110 }
4111 pci_set_master(pdev);
c682fc23 4112 pci_restore_state(pdev);
9d5c8243
AK		 4113
4114 pci_enable_wake(pdev, PCI_D3hot, 0);
4115 pci_enable_wake(pdev, PCI_D3cold, 0);
4116
4117 igb_reset(adapter);
4118 wr32(E1000_WUS, ~0);
4119
4120 return PCI_ERS_RESULT_RECOVERED;
4121}
4122
4123/**
4124 * igb_io_resume - called when traffic can start flowing again.
4125 * @pdev: Pointer to PCI device
4126 *
4127 * This callback is called when the error recovery driver tells us that
4128 * its OK to resume normal operation. Implementation resembles the
4129 * second-half of the igb_resume routine.
4130 */
4131static void igb_io_resume(struct pci_dev *pdev)
4132{
4133 struct net_device *netdev = pci_get_drvdata(pdev);
4134 struct igb_adapter *adapter = netdev_priv(netdev);
4135
4136 igb_init_manageability(adapter);
4137
4138 if (netif_running(netdev)) {
4139 if (igb_up(adapter)) {
4140 dev_err(&pdev->dev, "igb_up failed after reset\n");
4141 return;
4142 }
4143 }
4144
4145 netif_device_attach(netdev);
4146
4147 /* let the f/w know that the h/w is now under the control of the
4148 * driver. */
4149 igb_get_hw_control(adapter);
4150
4151}
4152
4153/* igb_main.c */
Linux 6.x block layer and io_uring tree(s)