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igb: add completion timeout workaround for 82575/82576
[linux-block.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
86d5d38f 4 Copyright(c) 2007-2009 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
40#include <linux/if_vlan.h>
41#include <linux/pci.h>
c54106bb 42#include <linux/pci-aspm.h>
9d5c8243
AK		 43#include <linux/delay.h>
44#include <linux/interrupt.h>
45#include <linux/if_ether.h>
40a914fa 46#include <linux/aer.h>
421e02f0 47#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 48#include <linux/dca.h>
49#endif
9d5c8243
AK		 50#include "igb.h"
51
86d5d38f 52#define DRV_VERSION "1.3.16-k2"
9d5c8243
AK		 53char igb_driver_name[] = "igb";
54char igb_driver_version[] = DRV_VERSION;
55static const char igb_driver_string[] =
56 "Intel(R) Gigabit Ethernet Network Driver";
86d5d38f 57static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
9d5c8243 58
9d5c8243
AK		 59static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61};
62
63static struct pci_device_id igb_pci_tbl[] = {
2d064c06 64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
2d064c06
AD		 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
c8ea5ea9 68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
72 /* required last entry */
73 {0, }
74};
75
76MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
77
78void igb_reset(struct igb_adapter *);
79static int igb_setup_all_tx_resources(struct igb_adapter *);
80static int igb_setup_all_rx_resources(struct igb_adapter *);
81static void igb_free_all_tx_resources(struct igb_adapter *);
82static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 83void igb_update_stats(struct igb_adapter *);
84static int igb_probe(struct pci_dev *, const struct pci_device_id *);
85static void __devexit igb_remove(struct pci_dev *pdev);
86static int igb_sw_init(struct igb_adapter *);
87static int igb_open(struct net_device *);
88static int igb_close(struct net_device *);
89static void igb_configure_tx(struct igb_adapter *);
90static void igb_configure_rx(struct igb_adapter *);
91static void igb_setup_rctl(struct igb_adapter *);
92static void igb_clean_all_tx_rings(struct igb_adapter *);
93static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 94static void igb_clean_tx_ring(struct igb_ring *);
95static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 96static void igb_set_multi(struct net_device *);
97static void igb_update_phy_info(unsigned long);
98static void igb_watchdog(unsigned long);
99static void igb_watchdog_task(struct work_struct *);
100static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
101 struct igb_ring *);
102static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
103static struct net_device_stats *igb_get_stats(struct net_device *);
104static int igb_change_mtu(struct net_device *, int);
105static int igb_set_mac(struct net_device *, void *);
106static irqreturn_t igb_intr(int irq, void *);
107static irqreturn_t igb_intr_msi(int irq, void *);
108static irqreturn_t igb_msix_other(int irq, void *);
109static irqreturn_t igb_msix_rx(int irq, void *);
110static irqreturn_t igb_msix_tx(int irq, void *);
421e02f0 111#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 112static void igb_update_rx_dca(struct igb_ring *);
113static void igb_update_tx_dca(struct igb_ring *);
114static void igb_setup_dca(struct igb_adapter *);
421e02f0 115#endif /* CONFIG_IGB_DCA */
3b644cf6 116static bool igb_clean_tx_irq(struct igb_ring *);
661086df 117static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 118static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
119static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
9d5c8243
AK		 120static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
121static void igb_tx_timeout(struct net_device *);
122static void igb_reset_task(struct work_struct *);
123static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
124static void igb_vlan_rx_add_vid(struct net_device *, u16);
125static void igb_vlan_rx_kill_vid(struct net_device *, u16);
126static void igb_restore_vlan(struct igb_adapter *);
4ae196df
AD		 127static void igb_ping_all_vfs(struct igb_adapter *);
128static void igb_msg_task(struct igb_adapter *);
129static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
e1739522 130static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
4ae196df 131static void igb_vmm_control(struct igb_adapter *);
4ae196df
AD		 132static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
133static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
9d5c8243 134
c8159b2d
ED		 135static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
136{
137 u32 reg_data;
138
139 reg_data = rd32(E1000_VMOLR(vfn));
140 reg_data |= E1000_VMOLR_BAM | /* Accept broadcast */
141 E1000_VMOLR_ROPE | /* Accept packets matched in UTA */
142 E1000_VMOLR_ROMPE | /* Accept packets matched in MTA */
143 E1000_VMOLR_AUPE | /* Accept untagged packets */
144 E1000_VMOLR_STRVLAN; /* Strip vlan tags */
145 wr32(E1000_VMOLR(vfn), reg_data);
146}
147
148static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
149 int vfn)
150{
151 struct e1000_hw *hw = &adapter->hw;
152 u32 vmolr;
153
154 vmolr = rd32(E1000_VMOLR(vfn));
155 vmolr &= ~E1000_VMOLR_RLPML_MASK;
156 vmolr |= size | E1000_VMOLR_LPE;
157 wr32(E1000_VMOLR(vfn), vmolr);
158
159 return 0;
160}
161
162static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
163{
164 u32 reg_data;
165
166 reg_data = rd32(E1000_RAH(entry));
167 reg_data &= ~E1000_RAH_POOL_MASK;
168 reg_data |= E1000_RAH_POOL_1 << pool;;
169 wr32(E1000_RAH(entry), reg_data);
170}
171
9d5c8243 172#ifdef CONFIG_PM
3fe7c4c9 173static int igb_suspend(struct pci_dev *, pm_message_t);
9d5c8243
AK		 174static int igb_resume(struct pci_dev *);
175#endif
176static void igb_shutdown(struct pci_dev *);
421e02f0 177#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 178static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
179static struct notifier_block dca_notifier = {
180 .notifier_call = igb_notify_dca,
181 .next = NULL,
182 .priority = 0
183};
184#endif
9d5c8243
AK		 185#ifdef CONFIG_NET_POLL_CONTROLLER
186/* for netdump / net console */
187static void igb_netpoll(struct net_device *);
188#endif
37680117 189#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 190static unsigned int max_vfs = 0;
191module_param(max_vfs, uint, 0);
192MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
193 "per physical function");
194#endif /* CONFIG_PCI_IOV */
195
9d5c8243
AK		 196static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
197 pci_channel_state_t);
198static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
199static void igb_io_resume(struct pci_dev *);
200
201static struct pci_error_handlers igb_err_handler = {
202 .error_detected = igb_io_error_detected,
203 .slot_reset = igb_io_slot_reset,
204 .resume = igb_io_resume,
205};
206
207
208static struct pci_driver igb_driver = {
209 .name = igb_driver_name,
210 .id_table = igb_pci_tbl,
211 .probe = igb_probe,
212 .remove = __devexit_p(igb_remove),
213#ifdef CONFIG_PM
214 /* Power Managment Hooks */
215 .suspend = igb_suspend,
216 .resume = igb_resume,
217#endif
218 .shutdown = igb_shutdown,
219 .err_handler = &igb_err_handler
220};
221
7dfc16fa
AD		 222static int global_quad_port_a; /* global quad port a indication */
223
9d5c8243
AK		 224MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
225MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
226MODULE_LICENSE("GPL");
227MODULE_VERSION(DRV_VERSION);
228
38c845c7
PO		 229/**
230 * Scale the NIC clock cycle by a large factor so that
231 * relatively small clock corrections can be added or
232 * substracted at each clock tick. The drawbacks of a
233 * large factor are a) that the clock register overflows
234 * more quickly (not such a big deal) and b) that the
235 * increment per tick has to fit into 24 bits.
236 *
237 * Note that
238 * TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
239 * IGB_TSYNC_SCALE
240 * TIMINCA += TIMINCA * adjustment [ppm] / 1e9
241 *
242 * The base scale factor is intentionally a power of two
243 * so that the division in %struct timecounter can be done with
244 * a shift.
245 */
246#define IGB_TSYNC_SHIFT (19)
247#define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
248
249/**
250 * The duration of one clock cycle of the NIC.
251 *
252 * @todo This hard-coded value is part of the specification and might change
253 * in future hardware revisions. Add revision check.
254 */
255#define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
256
257#if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
258# error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
259#endif
260
261/**
262 * igb_read_clock - read raw cycle counter (to be used by time counter)
263 */
264static cycle_t igb_read_clock(const struct cyclecounter *tc)
265{
266 struct igb_adapter *adapter =
267 container_of(tc, struct igb_adapter, cycles);
268 struct e1000_hw *hw = &adapter->hw;
269 u64 stamp;
270
271 stamp = rd32(E1000_SYSTIML);
272 stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
273
274 return stamp;
275}
276
9d5c8243
AK		 277#ifdef DEBUG
278/**
279 * igb_get_hw_dev_name - return device name string
280 * used by hardware layer to print debugging information
281 **/
282char *igb_get_hw_dev_name(struct e1000_hw *hw)
283{
284 struct igb_adapter *adapter = hw->back;
285 return adapter->netdev->name;
286}
38c845c7
PO		 287
288/**
289 * igb_get_time_str - format current NIC and system time as string
290 */
291static char *igb_get_time_str(struct igb_adapter *adapter,
292 char buffer[160])
293{
294 cycle_t hw = adapter->cycles.read(&adapter->cycles);
295 struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
296 struct timespec sys;
297 struct timespec delta;
298 getnstimeofday(&sys);
299
300 delta = timespec_sub(nic, sys);
301
302 sprintf(buffer,
33af6bcc
PO		 303 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
304 hw,
38c845c7
PO		 305 (long)nic.tv_sec, nic.tv_nsec,
306 (long)sys.tv_sec, sys.tv_nsec,
307 (long)delta.tv_sec, delta.tv_nsec);
308
309 return buffer;
310}
9d5c8243
AK		 311#endif
312
c493ea45
AD		 313/**
314 * igb_desc_unused - calculate if we have unused descriptors
315 **/
316static int igb_desc_unused(struct igb_ring *ring)
317{
318 if (ring->next_to_clean > ring->next_to_use)
319 return ring->next_to_clean - ring->next_to_use - 1;
320
321 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
322}
323
9d5c8243
AK		 324/**
325 * igb_init_module - Driver Registration Routine
326 *
327 * igb_init_module is the first routine called when the driver is
328 * loaded. All it does is register with the PCI subsystem.
329 **/
330static int __init igb_init_module(void)
331{
332 int ret;
333 printk(KERN_INFO "%s - version %s\n",
334 igb_driver_string, igb_driver_version);
335
336 printk(KERN_INFO "%s\n", igb_copyright);
337
7dfc16fa
AD		 338 global_quad_port_a = 0;
339
421e02f0 340#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 341 dca_register_notify(&dca_notifier);
342#endif
bbd98fe4
AD		 343
344 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 345 return ret;
346}
347
348module_init(igb_init_module);
349
350/**
351 * igb_exit_module - Driver Exit Cleanup Routine
352 *
353 * igb_exit_module is called just before the driver is removed
354 * from memory.
355 **/
356static void __exit igb_exit_module(void)
357{
421e02f0 358#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 359 dca_unregister_notify(&dca_notifier);
360#endif
9d5c8243
AK		 361 pci_unregister_driver(&igb_driver);
362}
363
364module_exit(igb_exit_module);
365
26bc19ec
AD		 366#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
367/**
368 * igb_cache_ring_register - Descriptor ring to register mapping
369 * @adapter: board private structure to initialize
370 *
371 * Once we know the feature-set enabled for the device, we'll cache
372 * the register offset the descriptor ring is assigned to.
373 **/
374static void igb_cache_ring_register(struct igb_adapter *adapter)
375{
376 int i;
1bfaf07b 377 unsigned int rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 378
379 switch (adapter->hw.mac.type) {
380 case e1000_82576:
381 /* The queues are allocated for virtualization such that VF 0
382 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
383 * In order to avoid collision we start at the first free queue
384 * and continue consuming queues in the same sequence
385 */
386 for (i = 0; i < adapter->num_rx_queues; i++)
1bfaf07b
AD		 387 adapter->rx_ring[i].reg_idx = rbase_offset +
388 Q_IDX_82576(i);
26bc19ec 389 for (i = 0; i < adapter->num_tx_queues; i++)
1bfaf07b
AD		 390 adapter->tx_ring[i].reg_idx = rbase_offset +
391 Q_IDX_82576(i);
26bc19ec
AD		 392 break;
393 case e1000_82575:
394 default:
395 for (i = 0; i < adapter->num_rx_queues; i++)
396 adapter->rx_ring[i].reg_idx = i;
397 for (i = 0; i < adapter->num_tx_queues; i++)
398 adapter->tx_ring[i].reg_idx = i;
399 break;
400 }
401}
402
9d5c8243
AK		 403/**
404 * igb_alloc_queues - Allocate memory for all rings
405 * @adapter: board private structure to initialize
406 *
407 * We allocate one ring per queue at run-time since we don't know the
408 * number of queues at compile-time.
409 **/
410static int igb_alloc_queues(struct igb_adapter *adapter)
411{
412 int i;
413
414 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
415 sizeof(struct igb_ring), GFP_KERNEL);
416 if (!adapter->tx_ring)
417 return -ENOMEM;
418
419 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
420 sizeof(struct igb_ring), GFP_KERNEL);
421 if (!adapter->rx_ring) {
422 kfree(adapter->tx_ring);
423 return -ENOMEM;
424 }
425
6eb5a7f1
AD		 426 adapter->rx_ring->buddy = adapter->tx_ring;
427
661086df
PWJ		 428 for (i = 0; i < adapter->num_tx_queues; i++) {
429 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 430 ring->count = adapter->tx_ring_count;
661086df
PWJ		 431 ring->adapter = adapter;
432 ring->queue_index = i;
433 }
9d5c8243
AK		 434 for (i = 0; i < adapter->num_rx_queues; i++) {
435 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 436 ring->count = adapter->rx_ring_count;
9d5c8243 437 ring->adapter = adapter;
844290e5 438 ring->queue_index = i;
9d5c8243
AK		 439 ring->itr_register = E1000_ITR;
440
844290e5 441 /* set a default napi handler for each rx_ring */
661086df 442 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243 443 }
26bc19ec
AD		 444
445 igb_cache_ring_register(adapter);
9d5c8243
AK		 446 return 0;
447}
448
a88f10ec
AD		 449static void igb_free_queues(struct igb_adapter *adapter)
450{
451 int i;
452
453 for (i = 0; i < adapter->num_rx_queues; i++)
454 netif_napi_del(&adapter->rx_ring[i].napi);
455
d1a8c9e1
AD		 456 adapter->num_rx_queues = 0;
457 adapter->num_tx_queues = 0;
458
a88f10ec
AD		 459 kfree(adapter->tx_ring);
460 kfree(adapter->rx_ring);
461}
462
9d5c8243
AK		 463#define IGB_N0_QUEUE -1
464static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
465 int tx_queue, int msix_vector)
466{
467 u32 msixbm = 0;
468 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 469 u32 ivar, index;
470
471 switch (hw->mac.type) {
472 case e1000_82575:
9d5c8243
AK		 473 /* The 82575 assigns vectors using a bitmask, which matches the
474 bitmask for the EICR/EIMS/EIMC registers. To assign one
475 or more queues to a vector, we write the appropriate bits
476 into the MSIXBM register for that vector. */
477 if (rx_queue > IGB_N0_QUEUE) {
478 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
479 adapter->rx_ring[rx_queue].eims_value = msixbm;
480 }
481 if (tx_queue > IGB_N0_QUEUE) {
482 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
483 adapter->tx_ring[tx_queue].eims_value =
484 E1000_EICR_TX_QUEUE0 << tx_queue;
485 }
486 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 487 break;
488 case e1000_82576:
26bc19ec 489 /* 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 490 Each queue has a single entry in the table to which we write
491 a vector number along with a "valid" bit. Sadly, the layout
492 of the table is somewhat counterintuitive. */
493 if (rx_queue > IGB_N0_QUEUE) {
1bfaf07b 494 index = (rx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 495 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 496 if (rx_queue & 0x1) {
2d064c06
AD		 497 /* vector goes into third byte of register */
498 ivar = ivar & 0xFF00FFFF;
499 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
26bc19ec
AD		 500 } else {
501 /* vector goes into low byte of register */
502 ivar = ivar & 0xFFFFFF00;
503 ivar |= msix_vector | E1000_IVAR_VALID;
2d064c06
AD		 504 }
505 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
506 array_wr32(E1000_IVAR0, index, ivar);
507 }
508 if (tx_queue > IGB_N0_QUEUE) {
1bfaf07b 509 index = (tx_queue >> 1) + adapter->vfs_allocated_count;
2d064c06 510 ivar = array_rd32(E1000_IVAR0, index);
26bc19ec 511 if (tx_queue & 0x1) {
2d064c06
AD		 512 /* vector goes into high byte of register */
513 ivar = ivar & 0x00FFFFFF;
514 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
26bc19ec
AD		 515 } else {
516 /* vector goes into second byte of register */
517 ivar = ivar & 0xFFFF00FF;
518 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
2d064c06
AD		 519 }
520 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
521 array_wr32(E1000_IVAR0, index, ivar);
522 }
523 break;
524 default:
525 BUG();
526 break;
527 }
9d5c8243
AK		 528}
529
530/**
531 * igb_configure_msix - Configure MSI-X hardware
532 *
533 * igb_configure_msix sets up the hardware to properly
534 * generate MSI-X interrupts.
535 **/
536static void igb_configure_msix(struct igb_adapter *adapter)
537{
538 u32 tmp;
539 int i, vector = 0;
540 struct e1000_hw *hw = &adapter->hw;
541
542 adapter->eims_enable_mask = 0;
2d064c06
AD		 543 if (hw->mac.type == e1000_82576)
544 /* Turn on MSI-X capability first, or our settings
545 * won't stick. And it will take days to debug. */
546 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
eebbbdba 547 E1000_GPIE_PBA | E1000_GPIE_EIAME |
2d064c06 548 E1000_GPIE_NSICR);
9d5c8243
AK		 549
550 for (i = 0; i < adapter->num_tx_queues; i++) {
551 struct igb_ring *tx_ring = &adapter->tx_ring[i];
552 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
553 adapter->eims_enable_mask |= tx_ring->eims_value;
554 if (tx_ring->itr_val)
6eb5a7f1 555 writel(tx_ring->itr_val,
9d5c8243
AK		 556 hw->hw_addr + tx_ring->itr_register);
557 else
558 writel(1, hw->hw_addr + tx_ring->itr_register);
559 }
560
561 for (i = 0; i < adapter->num_rx_queues; i++) {
562 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 563 rx_ring->buddy = NULL;
9d5c8243
AK		 564 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
565 adapter->eims_enable_mask |= rx_ring->eims_value;
566 if (rx_ring->itr_val)
6eb5a7f1 567 writel(rx_ring->itr_val,
9d5c8243
AK		 568 hw->hw_addr + rx_ring->itr_register);
569 else
570 writel(1, hw->hw_addr + rx_ring->itr_register);
571 }
572
573
574 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 575 switch (hw->mac.type) {
576 case e1000_82575:
9d5c8243
AK		 577 array_wr32(E1000_MSIXBM(0), vector++,
578 E1000_EIMS_OTHER);
579
9d5c8243
AK		 580 tmp = rd32(E1000_CTRL_EXT);
581 /* enable MSI-X PBA support*/
582 tmp |= E1000_CTRL_EXT_PBA_CLR;
583
584 /* Auto-Mask interrupts upon ICR read. */
585 tmp |= E1000_CTRL_EXT_EIAME;
586 tmp |= E1000_CTRL_EXT_IRCA;
587
588 wr32(E1000_CTRL_EXT, tmp);
589 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 590 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 591
2d064c06
AD		 592 break;
593
594 case e1000_82576:
595 tmp = (vector++ | E1000_IVAR_VALID) << 8;
596 wr32(E1000_IVAR_MISC, tmp);
597
598 adapter->eims_enable_mask = (1 << (vector)) - 1;
599 adapter->eims_other = 1 << (vector - 1);
600 break;
601 default:
602 /* do nothing, since nothing else supports MSI-X */
603 break;
604 } /* switch (hw->mac.type) */
9d5c8243
AK		 605 wrfl();
606}
607
608/**
609 * igb_request_msix - Initialize MSI-X interrupts
610 *
611 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
612 * kernel.
613 **/
614static int igb_request_msix(struct igb_adapter *adapter)
615{
616 struct net_device *netdev = adapter->netdev;
617 int i, err = 0, vector = 0;
618
619 vector = 0;
620
621 for (i = 0; i < adapter->num_tx_queues; i++) {
622 struct igb_ring *ring = &(adapter->tx_ring[i]);
cb7b48f6 623 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
9d5c8243
AK		 624 err = request_irq(adapter->msix_entries[vector].vector,
625 &igb_msix_tx, 0, ring->name,
626 &(adapter->tx_ring[i]));
627 if (err)
628 goto out;
629 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 630 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 631 vector++;
632 }
633 for (i = 0; i < adapter->num_rx_queues; i++) {
634 struct igb_ring *ring = &(adapter->rx_ring[i]);
635 if (strlen(netdev->name) < (IFNAMSIZ - 5))
cb7b48f6 636 sprintf(ring->name, "%s-rx-%d", netdev->name, i);
9d5c8243
AK		 637 else
638 memcpy(ring->name, netdev->name, IFNAMSIZ);
639 err = request_irq(adapter->msix_entries[vector].vector,
640 &igb_msix_rx, 0, ring->name,
641 &(adapter->rx_ring[i]));
642 if (err)
643 goto out;
644 ring->itr_register = E1000_EITR(0) + (vector << 2);
645 ring->itr_val = adapter->itr;
646 vector++;
647 }
648
649 err = request_irq(adapter->msix_entries[vector].vector,
650 &igb_msix_other, 0, netdev->name, netdev);
651 if (err)
652 goto out;
653
9d5c8243
AK		 654 igb_configure_msix(adapter);
655 return 0;
656out:
657 return err;
658}
659
660static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
661{
662 if (adapter->msix_entries) {
663 pci_disable_msix(adapter->pdev);
664 kfree(adapter->msix_entries);
665 adapter->msix_entries = NULL;
7dfc16fa 666 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 667 pci_disable_msi(adapter->pdev);
668 return;
669}
670
671
672/**
673 * igb_set_interrupt_capability - set MSI or MSI-X if supported
674 *
675 * Attempt to configure interrupts using the best available
676 * capabilities of the hardware and kernel.
677 **/
678static void igb_set_interrupt_capability(struct igb_adapter *adapter)
679{
680 int err;
681 int numvecs, i;
682
83b7180d
AD		 683 /* Number of supported queues. */
684 /* Having more queues than CPUs doesn't make sense. */
685 adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
686 adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
687
9d5c8243
AK		 688 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
689 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
690 GFP_KERNEL);
691 if (!adapter->msix_entries)
692 goto msi_only;
693
694 for (i = 0; i < numvecs; i++)
695 adapter->msix_entries[i].entry = i;
696
697 err = pci_enable_msix(adapter->pdev,
698 adapter->msix_entries,
699 numvecs);
700 if (err == 0)
34a20e89 701 goto out;
9d5c8243
AK		 702
703 igb_reset_interrupt_capability(adapter);
704
705 /* If we can't do MSI-X, try MSI */
706msi_only:
2a3abf6d
AD		 707#ifdef CONFIG_PCI_IOV
708 /* disable SR-IOV for non MSI-X configurations */
709 if (adapter->vf_data) {
710 struct e1000_hw *hw = &adapter->hw;
711 /* disable iov and allow time for transactions to clear */
712 pci_disable_sriov(adapter->pdev);
713 msleep(500);
714
715 kfree(adapter->vf_data);
716 adapter->vf_data = NULL;
717 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
718 msleep(100);
719 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
720 }
721#endif
9d5c8243 722 adapter->num_rx_queues = 1;
661086df 723 adapter->num_tx_queues = 1;
9d5c8243 724 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 725 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 726out:
661086df 727 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 728 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 729 return;
730}
731
732/**
733 * igb_request_irq - initialize interrupts
734 *
735 * Attempts to configure interrupts using the best available
736 * capabilities of the hardware and kernel.
737 **/
738static int igb_request_irq(struct igb_adapter *adapter)
739{
740 struct net_device *netdev = adapter->netdev;
741 struct e1000_hw *hw = &adapter->hw;
742 int err = 0;
743
744 if (adapter->msix_entries) {
745 err = igb_request_msix(adapter);
844290e5 746 if (!err)
9d5c8243 747 goto request_done;
9d5c8243
AK		 748 /* fall back to MSI */
749 igb_reset_interrupt_capability(adapter);
750 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 751 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 752 igb_free_all_tx_resources(adapter);
753 igb_free_all_rx_resources(adapter);
754 adapter->num_rx_queues = 1;
755 igb_alloc_queues(adapter);
844290e5 756 } else {
2d064c06
AD		 757 switch (hw->mac.type) {
758 case e1000_82575:
759 wr32(E1000_MSIXBM(0),
760 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
761 break;
762 case e1000_82576:
763 wr32(E1000_IVAR0, E1000_IVAR_VALID);
764 break;
765 default:
766 break;
767 }
9d5c8243 768 }
844290e5 769
7dfc16fa 770 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 771 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
772 netdev->name, netdev);
773 if (!err)
774 goto request_done;
775 /* fall back to legacy interrupts */
776 igb_reset_interrupt_capability(adapter);
7dfc16fa 777 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 778 }
779
780 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
781 netdev->name, netdev);
782
6cb5e577 783 if (err)
9d5c8243
AK		 784 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
785 err);
9d5c8243
AK		 786
787request_done:
788 return err;
789}
790
791static void igb_free_irq(struct igb_adapter *adapter)
792{
793 struct net_device *netdev = adapter->netdev;
794
795 if (adapter->msix_entries) {
796 int vector = 0, i;
797
798 for (i = 0; i < adapter->num_tx_queues; i++)
799 free_irq(adapter->msix_entries[vector++].vector,
800 &(adapter->tx_ring[i]));
801 for (i = 0; i < adapter->num_rx_queues; i++)
802 free_irq(adapter->msix_entries[vector++].vector,
803 &(adapter->rx_ring[i]));
804
805 free_irq(adapter->msix_entries[vector++].vector, netdev);
806 return;
807 }
808
809 free_irq(adapter->pdev->irq, netdev);
810}
811
812/**
813 * igb_irq_disable - Mask off interrupt generation on the NIC
814 * @adapter: board private structure
815 **/
816static void igb_irq_disable(struct igb_adapter *adapter)
817{
818 struct e1000_hw *hw = &adapter->hw;
819
820 if (adapter->msix_entries) {
844290e5 821 wr32(E1000_EIAM, 0);
9d5c8243
AK		 822 wr32(E1000_EIMC, ~0);
823 wr32(E1000_EIAC, 0);
824 }
844290e5
PW		 825
826 wr32(E1000_IAM, 0);
9d5c8243
AK		 827 wr32(E1000_IMC, ~0);
828 wrfl();
829 synchronize_irq(adapter->pdev->irq);
830}
831
832/**
833 * igb_irq_enable - Enable default interrupt generation settings
834 * @adapter: board private structure
835 **/
836static void igb_irq_enable(struct igb_adapter *adapter)
837{
838 struct e1000_hw *hw = &adapter->hw;
839
840 if (adapter->msix_entries) {
844290e5
PW		 841 wr32(E1000_EIAC, adapter->eims_enable_mask);
842 wr32(E1000_EIAM, adapter->eims_enable_mask);
843 wr32(E1000_EIMS, adapter->eims_enable_mask);
4ae196df
AD		 844 if (adapter->vfs_allocated_count)
845 wr32(E1000_MBVFIMR, 0xFF);
846 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
847 E1000_IMS_DOUTSYNC));
844290e5
PW		 848 } else {
849 wr32(E1000_IMS, IMS_ENABLE_MASK);
850 wr32(E1000_IAM, IMS_ENABLE_MASK);
851 }
9d5c8243
AK		 852}
853
854static void igb_update_mng_vlan(struct igb_adapter *adapter)
855{
856 struct net_device *netdev = adapter->netdev;
857 u16 vid = adapter->hw.mng_cookie.vlan_id;
858 u16 old_vid = adapter->mng_vlan_id;
859 if (adapter->vlgrp) {
860 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
861 if (adapter->hw.mng_cookie.status &
862 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
863 igb_vlan_rx_add_vid(netdev, vid);
864 adapter->mng_vlan_id = vid;
865 } else
866 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
867
868 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
869 (vid != old_vid) &&
870 !vlan_group_get_device(adapter->vlgrp, old_vid))
871 igb_vlan_rx_kill_vid(netdev, old_vid);
872 } else
873 adapter->mng_vlan_id = vid;
874 }
875}
876
877/**
878 * igb_release_hw_control - release control of the h/w to f/w
879 * @adapter: address of board private structure
880 *
881 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
882 * For ASF and Pass Through versions of f/w this means that the
883 * driver is no longer loaded.
884 *
885 **/
886static void igb_release_hw_control(struct igb_adapter *adapter)
887{
888 struct e1000_hw *hw = &adapter->hw;
889 u32 ctrl_ext;
890
891 /* Let firmware take over control of h/w */
892 ctrl_ext = rd32(E1000_CTRL_EXT);
893 wr32(E1000_CTRL_EXT,
894 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
895}
896
897
898/**
899 * igb_get_hw_control - get control of the h/w from f/w
900 * @adapter: address of board private structure
901 *
902 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
903 * For ASF and Pass Through versions of f/w this means that
904 * the driver is loaded.
905 *
906 **/
907static void igb_get_hw_control(struct igb_adapter *adapter)
908{
909 struct e1000_hw *hw = &adapter->hw;
910 u32 ctrl_ext;
911
912 /* Let firmware know the driver has taken over */
913 ctrl_ext = rd32(E1000_CTRL_EXT);
914 wr32(E1000_CTRL_EXT,
915 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
916}
917
9d5c8243
AK		 918/**
919 * igb_configure - configure the hardware for RX and TX
920 * @adapter: private board structure
921 **/
922static void igb_configure(struct igb_adapter *adapter)
923{
924 struct net_device *netdev = adapter->netdev;
925 int i;
926
927 igb_get_hw_control(adapter);
928 igb_set_multi(netdev);
929
930 igb_restore_vlan(adapter);
9d5c8243
AK		 931
932 igb_configure_tx(adapter);
933 igb_setup_rctl(adapter);
934 igb_configure_rx(adapter);
662d7205
AD		 935
936 igb_rx_fifo_flush_82575(&adapter->hw);
937
c493ea45 938 /* call igb_desc_unused which always leaves
9d5c8243
AK		 939 * at least 1 descriptor unused to make sure
940 * next_to_use != next_to_clean */
941 for (i = 0; i < adapter->num_rx_queues; i++) {
942 struct igb_ring *ring = &adapter->rx_ring[i];
c493ea45 943 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
9d5c8243
AK		 944 }
945
946
947 adapter->tx_queue_len = netdev->tx_queue_len;
948}
949
950
951/**
952 * igb_up - Open the interface and prepare it to handle traffic
953 * @adapter: board private structure
954 **/
955
956int igb_up(struct igb_adapter *adapter)
957{
958 struct e1000_hw *hw = &adapter->hw;
959 int i;
960
961 /* hardware has been reset, we need to reload some things */
962 igb_configure(adapter);
963
964 clear_bit(__IGB_DOWN, &adapter->state);
965
844290e5
PW		 966 for (i = 0; i < adapter->num_rx_queues; i++)
967 napi_enable(&adapter->rx_ring[i].napi);
968 if (adapter->msix_entries)
9d5c8243 969 igb_configure_msix(adapter);
9d5c8243 970
4ae196df 971 igb_vmm_control(adapter);
e1739522
AD		 972 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
973 igb_set_vmolr(hw, adapter->vfs_allocated_count);
974
9d5c8243
AK		 975 /* Clear any pending interrupts. */
976 rd32(E1000_ICR);
977 igb_irq_enable(adapter);
978
4cb9be7a
JB		 979 netif_tx_start_all_queues(adapter->netdev);
980
9d5c8243
AK		 981 /* Fire a link change interrupt to start the watchdog. */
982 wr32(E1000_ICS, E1000_ICS_LSC);
983 return 0;
984}
985
986void igb_down(struct igb_adapter *adapter)
987{
988 struct e1000_hw *hw = &adapter->hw;
989 struct net_device *netdev = adapter->netdev;
990 u32 tctl, rctl;
991 int i;
992
993 /* signal that we're down so the interrupt handler does not
994 * reschedule our watchdog timer */
995 set_bit(__IGB_DOWN, &adapter->state);
996
997 /* disable receives in the hardware */
998 rctl = rd32(E1000_RCTL);
999 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1000 /* flush and sleep below */
1001
fd2ea0a7 1002 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1003
1004 /* disable transmits in the hardware */
1005 tctl = rd32(E1000_TCTL);
1006 tctl &= ~E1000_TCTL_EN;
1007 wr32(E1000_TCTL, tctl);
1008 /* flush both disables and wait for them to finish */
1009 wrfl();
1010 msleep(10);
1011
844290e5
PW		 1012 for (i = 0; i < adapter->num_rx_queues; i++)
1013 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 1014
9d5c8243
AK		 1015 igb_irq_disable(adapter);
1016
1017 del_timer_sync(&adapter->watchdog_timer);
1018 del_timer_sync(&adapter->phy_info_timer);
1019
1020 netdev->tx_queue_len = adapter->tx_queue_len;
1021 netif_carrier_off(netdev);
04fe6358
AD		 1022
1023 /* record the stats before reset*/
1024 igb_update_stats(adapter);
1025
9d5c8243
AK		 1026 adapter->link_speed = 0;
1027 adapter->link_duplex = 0;
1028
3023682e
JK		 1029 if (!pci_channel_offline(adapter->pdev))
1030 igb_reset(adapter);
9d5c8243
AK		 1031 igb_clean_all_tx_rings(adapter);
1032 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1033#ifdef CONFIG_IGB_DCA
1034
1035 /* since we reset the hardware DCA settings were cleared */
1036 igb_setup_dca(adapter);
1037#endif
9d5c8243
AK		 1038}
1039
1040void igb_reinit_locked(struct igb_adapter *adapter)
1041{
1042 WARN_ON(in_interrupt());
1043 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1044 msleep(1);
1045 igb_down(adapter);
1046 igb_up(adapter);
1047 clear_bit(__IGB_RESETTING, &adapter->state);
1048}
1049
1050void igb_reset(struct igb_adapter *adapter)
1051{
1052 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1053 struct e1000_mac_info *mac = &hw->mac;
1054 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1055 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1056 u16 hwm;
1057
1058 /* Repartition Pba for greater than 9k mtu
1059 * To take effect CTRL.RST is required.
1060 */
fa4dfae0
AD		 1061 switch (mac->type) {
1062 case e1000_82576:
2d064c06 1063 pba = E1000_PBA_64K;
fa4dfae0
AD		 1064 break;
1065 case e1000_82575:
1066 default:
1067 pba = E1000_PBA_34K;
1068 break;
2d064c06 1069 }
9d5c8243 1070
2d064c06
AD		 1071 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1072 (mac->type < e1000_82576)) {
9d5c8243
AK		 1073 /* adjust PBA for jumbo frames */
1074 wr32(E1000_PBA, pba);
1075
1076 /* To maintain wire speed transmits, the Tx FIFO should be
1077 * large enough to accommodate two full transmit packets,
1078 * rounded up to the next 1KB and expressed in KB. Likewise,
1079 * the Rx FIFO should be large enough to accommodate at least
1080 * one full receive packet and is similarly rounded up and
1081 * expressed in KB. */
1082 pba = rd32(E1000_PBA);
1083 /* upper 16 bits has Tx packet buffer allocation size in KB */
1084 tx_space = pba >> 16;
1085 /* lower 16 bits has Rx packet buffer allocation size in KB */
1086 pba &= 0xffff;
1087 /* the tx fifo also stores 16 bytes of information about the tx
1088 * but don't include ethernet FCS because hardware appends it */
1089 min_tx_space = (adapter->max_frame_size +
85e8d004 1090 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1091 ETH_FCS_LEN) * 2;
1092 min_tx_space = ALIGN(min_tx_space, 1024);
1093 min_tx_space >>= 10;
1094 /* software strips receive CRC, so leave room for it */
1095 min_rx_space = adapter->max_frame_size;
1096 min_rx_space = ALIGN(min_rx_space, 1024);
1097 min_rx_space >>= 10;
1098
1099 /* If current Tx allocation is less than the min Tx FIFO size,
1100 * and the min Tx FIFO size is less than the current Rx FIFO
1101 * allocation, take space away from current Rx allocation */
1102 if (tx_space < min_tx_space &&
1103 ((min_tx_space - tx_space) < pba)) {
1104 pba = pba - (min_tx_space - tx_space);
1105
1106 /* if short on rx space, rx wins and must trump tx
1107 * adjustment */
1108 if (pba < min_rx_space)
1109 pba = min_rx_space;
1110 }
2d064c06 1111 wr32(E1000_PBA, pba);
9d5c8243 1112 }
9d5c8243
AK		 1113
1114 /* flow control settings */
1115 /* The high water mark must be low enough to fit one full frame
1116 * (or the size used for early receive) above it in the Rx FIFO.
1117 * Set it to the lower of:
1118 * - 90% of the Rx FIFO size, or
1119 * - the full Rx FIFO size minus one full frame */
1120 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1121 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1122
2d064c06
AD		 1123 if (mac->type < e1000_82576) {
1124 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1125 fc->low_water = fc->high_water - 8;
1126 } else {
1127 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1128 fc->low_water = fc->high_water - 16;
1129 }
9d5c8243
AK		 1130 fc->pause_time = 0xFFFF;
1131 fc->send_xon = 1;
1132 fc->type = fc->original_type;
1133
4ae196df
AD		 1134 /* disable receive for all VFs and wait one second */
1135 if (adapter->vfs_allocated_count) {
1136 int i;
1137 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1138 adapter->vf_data[i].clear_to_send = false;
1139
1140 /* ping all the active vfs to let them know we are going down */
1141 igb_ping_all_vfs(adapter);
1142
1143 /* disable transmits and receives */
1144 wr32(E1000_VFRE, 0);
1145 wr32(E1000_VFTE, 0);
1146 }
1147
9d5c8243
AK		 1148 /* Allow time for pending master requests to run */
1149 adapter->hw.mac.ops.reset_hw(&adapter->hw);
1150 wr32(E1000_WUC, 0);
1151
1152 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1153 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1154
1155 igb_update_mng_vlan(adapter);
1156
1157 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1158 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1159
1160 igb_reset_adaptive(&adapter->hw);
f5f4cf08 1161 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 1162}
1163
2e5c6922
SH		 1164static const struct net_device_ops igb_netdev_ops = {
1165 .ndo_open = igb_open,
1166 .ndo_stop = igb_close,
00829823 1167 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 1168 .ndo_get_stats = igb_get_stats,
1169 .ndo_set_multicast_list = igb_set_multi,
1170 .ndo_set_mac_address = igb_set_mac,
1171 .ndo_change_mtu = igb_change_mtu,
1172 .ndo_do_ioctl = igb_ioctl,
1173 .ndo_tx_timeout = igb_tx_timeout,
1174 .ndo_validate_addr = eth_validate_addr,
1175 .ndo_vlan_rx_register = igb_vlan_rx_register,
1176 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1177 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
1178#ifdef CONFIG_NET_POLL_CONTROLLER
1179 .ndo_poll_controller = igb_netpoll,
1180#endif
1181};
1182
9d5c8243
AK		 1183/**
1184 * igb_probe - Device Initialization Routine
1185 * @pdev: PCI device information struct
1186 * @ent: entry in igb_pci_tbl
1187 *
1188 * Returns 0 on success, negative on failure
1189 *
1190 * igb_probe initializes an adapter identified by a pci_dev structure.
1191 * The OS initialization, configuring of the adapter private structure,
1192 * and a hardware reset occur.
1193 **/
1194static int __devinit igb_probe(struct pci_dev *pdev,
1195 const struct pci_device_id *ent)
1196{
1197 struct net_device *netdev;
1198 struct igb_adapter *adapter;
1199 struct e1000_hw *hw;
1200 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1201 unsigned long mmio_start, mmio_len;
2d6a5e95 1202 int err, pci_using_dac;
682337fe 1203 u16 eeprom_data = 0;
9d5c8243
AK		 1204 u16 eeprom_apme_mask = IGB_EEPROM_APME;
1205 u32 part_num;
1206
aed5dec3 1207 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1208 if (err)
1209 return err;
1210
1211 pci_using_dac = 0;
6a35528a 1212 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243 1213 if (!err) {
6a35528a 1214 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
9d5c8243
AK		 1215 if (!err)
1216 pci_using_dac = 1;
1217 } else {
284901a9 1218 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243 1219 if (err) {
284901a9 1220 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
9d5c8243
AK		 1221 if (err) {
1222 dev_err(&pdev->dev, "No usable DMA "
1223 "configuration, aborting\n");
1224 goto err_dma;
1225 }
1226 }
1227 }
1228
aed5dec3
AD		 1229 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1230 IORESOURCE_MEM),
1231 igb_driver_name);
9d5c8243
AK		 1232 if (err)
1233 goto err_pci_reg;
1234
ea943d41
JK		 1235 err = pci_enable_pcie_error_reporting(pdev);
1236 if (err) {
1237 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1238 "0x%x\n", err);
1239 /* non-fatal, continue */
1240 }
40a914fa 1241
9d5c8243 1242 pci_set_master(pdev);
c682fc23 1243 pci_save_state(pdev);
9d5c8243
AK		 1244
1245 err = -ENOMEM;
1bfaf07b
AD		 1246 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1247 IGB_ABS_MAX_TX_QUEUES);
9d5c8243
AK		 1248 if (!netdev)
1249 goto err_alloc_etherdev;
1250
1251 SET_NETDEV_DEV(netdev, &pdev->dev);
1252
1253 pci_set_drvdata(pdev, netdev);
1254 adapter = netdev_priv(netdev);
1255 adapter->netdev = netdev;
1256 adapter->pdev = pdev;
1257 hw = &adapter->hw;
1258 hw->back = adapter;
1259 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1260
1261 mmio_start = pci_resource_start(pdev, 0);
1262 mmio_len = pci_resource_len(pdev, 0);
1263
1264 err = -EIO;
28b0759c
AD		 1265 hw->hw_addr = ioremap(mmio_start, mmio_len);
1266 if (!hw->hw_addr)
9d5c8243
AK		 1267 goto err_ioremap;
1268
2e5c6922 1269 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1270 igb_set_ethtool_ops(netdev);
9d5c8243 1271 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1272
1273 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1274
1275 netdev->mem_start = mmio_start;
1276 netdev->mem_end = mmio_start + mmio_len;
1277
9d5c8243
AK		 1278 /* PCI config space info */
1279 hw->vendor_id = pdev->vendor;
1280 hw->device_id = pdev->device;
1281 hw->revision_id = pdev->revision;
1282 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1283 hw->subsystem_device_id = pdev->subsystem_device;
1284
1285 /* setup the private structure */
1286 hw->back = adapter;
1287 /* Copy the default MAC, PHY and NVM function pointers */
1288 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1289 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1290 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1291 /* Initialize skew-specific constants */
1292 err = ei->get_invariants(hw);
1293 if (err)
450c87c8 1294 goto err_sw_init;
9d5c8243 1295
2a3abf6d
AD		 1296#ifdef CONFIG_PCI_IOV
1297 /* since iov functionality isn't critical to base device function we
1298 * can accept failure. If it fails we don't allow iov to be enabled */
1299 if (hw->mac.type == e1000_82576) {
1300 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1301 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1302 int i;
1303 unsigned char mac_addr[ETH_ALEN];
1304
9ca046d5 1305 if (num_vfs) {
2a3abf6d
AD		 1306 adapter->vf_data = kcalloc(num_vfs,
1307 sizeof(struct vf_data_storage),
1308 GFP_KERNEL);
9ca046d5
AD		 1309 if (!adapter->vf_data) {
1310 dev_err(&pdev->dev,
1311 "Could not allocate VF private data - "
1312 "IOV enable failed\n");
2a3abf6d 1313 } else {
9ca046d5
AD		 1314 err = pci_enable_sriov(pdev, num_vfs);
1315 if (!err) {
1316 adapter->vfs_allocated_count = num_vfs;
1317 dev_info(&pdev->dev,
1318 "%d vfs allocated\n",
1319 num_vfs);
1320 for (i = 0;
1321 i < adapter->vfs_allocated_count;
1322 i++) {
1323 random_ether_addr(mac_addr);
1324 igb_set_vf_mac(adapter, i,
1325 mac_addr);
1326 }
1327 } else {
1328 kfree(adapter->vf_data);
1329 adapter->vf_data = NULL;
1330 }
2a3abf6d
AD		 1331 }
1332 }
1333 }
1334
1335#endif
450c87c8 1336 /* setup the private structure */
9d5c8243
AK		 1337 err = igb_sw_init(adapter);
1338 if (err)
1339 goto err_sw_init;
1340
1341 igb_get_bus_info_pcie(hw);
1342
7dfc16fa
AD		 1343 /* set flags */
1344 switch (hw->mac.type) {
7dfc16fa 1345 case e1000_82575:
7dfc16fa
AD		 1346 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1347 break;
bbd98fe4 1348 case e1000_82576:
7dfc16fa
AD		 1349 default:
1350 break;
1351 }
1352
9d5c8243
AK		 1353 hw->phy.autoneg_wait_to_complete = false;
1354 hw->mac.adaptive_ifs = true;
1355
1356 /* Copper options */
1357 if (hw->phy.media_type == e1000_media_type_copper) {
1358 hw->phy.mdix = AUTO_ALL_MODES;
1359 hw->phy.disable_polarity_correction = false;
1360 hw->phy.ms_type = e1000_ms_hw_default;
1361 }
1362
1363 if (igb_check_reset_block(hw))
1364 dev_info(&pdev->dev,
1365 "PHY reset is blocked due to SOL/IDER session.\n");
1366
1367 netdev->features = NETIF_F_SG |
7d8eb29e 1368 NETIF_F_IP_CSUM |
9d5c8243
AK		 1369 NETIF_F_HW_VLAN_TX |
1370 NETIF_F_HW_VLAN_RX |
1371 NETIF_F_HW_VLAN_FILTER;
1372
7d8eb29e 1373 netdev->features |= NETIF_F_IPV6_CSUM;
9d5c8243 1374 netdev->features |= NETIF_F_TSO;
9d5c8243 1375 netdev->features |= NETIF_F_TSO6;
48f29ffc 1376
5c0999b7 1377 netdev->features |= NETIF_F_GRO;
d3352520 1378
48f29ffc
JK		 1379 netdev->vlan_features |= NETIF_F_TSO;
1380 netdev->vlan_features |= NETIF_F_TSO6;
7d8eb29e 1381 netdev->vlan_features |= NETIF_F_IP_CSUM;
48f29ffc
JK		 1382 netdev->vlan_features |= NETIF_F_SG;
1383
9d5c8243
AK		 1384 if (pci_using_dac)
1385 netdev->features |= NETIF_F_HIGHDMA;
1386
b9473560
JB		 1387 if (adapter->hw.mac.type == e1000_82576)
1388 netdev->features |= NETIF_F_SCTP_CSUM;
1389
9d5c8243
AK		 1390 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1391
1392 /* before reading the NVM, reset the controller to put the device in a
1393 * known good starting state */
1394 hw->mac.ops.reset_hw(hw);
1395
1396 /* make sure the NVM is good */
1397 if (igb_validate_nvm_checksum(hw) < 0) {
1398 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1399 err = -EIO;
1400 goto err_eeprom;
1401 }
1402
1403 /* copy the MAC address out of the NVM */
1404 if (hw->mac.ops.read_mac_addr(hw))
1405 dev_err(&pdev->dev, "NVM Read Error\n");
1406
1407 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1408 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1409
1410 if (!is_valid_ether_addr(netdev->perm_addr)) {
1411 dev_err(&pdev->dev, "Invalid MAC Address\n");
1412 err = -EIO;
1413 goto err_eeprom;
1414 }
1415
0e340485
AD		 1416 setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1417 (unsigned long) adapter);
1418 setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1419 (unsigned long) adapter);
9d5c8243
AK		 1420
1421 INIT_WORK(&adapter->reset_task, igb_reset_task);
1422 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1423
450c87c8 1424 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 1425 adapter->fc_autoneg = true;
1426 hw->mac.autoneg = true;
1427 hw->phy.autoneg_advertised = 0x2f;
1428
1429 hw->fc.original_type = e1000_fc_default;
1430 hw->fc.type = e1000_fc_default;
1431
cbd347ad 1432 adapter->itr_setting = IGB_DEFAULT_ITR;
9d5c8243
AK		 1433 adapter->itr = IGB_START_ITR;
1434
1435 igb_validate_mdi_setting(hw);
1436
9d5c8243
AK		 1437 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1438 * enable the ACPI Magic Packet filter
1439 */
1440
a2cf8b6c 1441 if (hw->bus.func == 0)
312c75ae 1442 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
a2cf8b6c
AD		 1443 else if (hw->bus.func == 1)
1444 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 1445
1446 if (eeprom_data & eeprom_apme_mask)
1447 adapter->eeprom_wol |= E1000_WUFC_MAG;
1448
1449 /* now that we have the eeprom settings, apply the special cases where
1450 * the eeprom may be wrong or the board simply won't support wake on
1451 * lan on a particular port */
1452 switch (pdev->device) {
1453 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1454 adapter->eeprom_wol = 0;
1455 break;
1456 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1457 case E1000_DEV_ID_82576_FIBER:
1458 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1459 /* Wake events only supported on port A for dual fiber
1460 * regardless of eeprom setting */
1461 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1462 adapter->eeprom_wol = 0;
1463 break;
c8ea5ea9
AD		 1464 case E1000_DEV_ID_82576_QUAD_COPPER:
1465 /* if quad port adapter, disable WoL on all but port A */
1466 if (global_quad_port_a != 0)
1467 adapter->eeprom_wol = 0;
1468 else
1469 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1470 /* Reset for multiple quad port adapters */
1471 if (++global_quad_port_a == 4)
1472 global_quad_port_a = 0;
1473 break;
9d5c8243
AK		 1474 }
1475
1476 /* initialize the wol settings based on the eeprom settings */
1477 adapter->wol = adapter->eeprom_wol;
e1b86d84 1478 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1479
1480 /* reset the hardware with the new settings */
1481 igb_reset(adapter);
1482
1483 /* let the f/w know that the h/w is now under the control of the
1484 * driver. */
1485 igb_get_hw_control(adapter);
1486
9d5c8243
AK		 1487 strcpy(netdev->name, "eth%d");
1488 err = register_netdev(netdev);
1489 if (err)
1490 goto err_register;
1491
b168dfc5
JB		 1492 /* carrier off reporting is important to ethtool even BEFORE open */
1493 netif_carrier_off(netdev);
1494
421e02f0 1495#ifdef CONFIG_IGB_DCA
bbd98fe4 1496 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 1497 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 1498 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 1499 igb_setup_dca(adapter);
1500 }
1501#endif
1502
38c845c7
PO		 1503 /*
1504 * Initialize hardware timer: we keep it running just in case
1505 * that some program needs it later on.
1506 */
1507 memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1508 adapter->cycles.read = igb_read_clock;
1509 adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1510 adapter->cycles.mult = 1;
1511 adapter->cycles.shift = IGB_TSYNC_SHIFT;
1512 wr32(E1000_TIMINCA,
1513 (1<<24) |
1514 IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1515#if 0
1516 /*
1517 * Avoid rollover while we initialize by resetting the time counter.
1518 */
1519 wr32(E1000_SYSTIML, 0x00000000);
1520 wr32(E1000_SYSTIMH, 0x00000000);
1521#else
1522 /*
1523 * Set registers so that rollover occurs soon to test this.
1524 */
1525 wr32(E1000_SYSTIML, 0x00000000);
1526 wr32(E1000_SYSTIMH, 0xFF800000);
1527#endif
1528 wrfl();
1529 timecounter_init(&adapter->clock,
1530 &adapter->cycles,
1531 ktime_to_ns(ktime_get_real()));
1532
33af6bcc
PO		 1533 /*
1534 * Synchronize our NIC clock against system wall clock. NIC
1535 * time stamp reading requires ~3us per sample, each sample
1536 * was pretty stable even under load => only require 10
1537 * samples for each offset comparison.
1538 */
1539 memset(&adapter->compare, 0, sizeof(adapter->compare));
1540 adapter->compare.source = &adapter->clock;
1541 adapter->compare.target = ktime_get_real;
1542 adapter->compare.num_samples = 10;
1543 timecompare_update(&adapter->compare, 0);
1544
38c845c7
PO		 1545#ifdef DEBUG
1546 {
1547 char buffer[160];
1548 printk(KERN_DEBUG
1549 "igb: %s: hw %p initialized timer\n",
1550 igb_get_time_str(adapter, buffer),
1551 &adapter->hw);
1552 }
1553#endif
1554
9d5c8243
AK		 1555 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1556 /* print bus type/speed/width info */
7c510e4b 1557 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1558 netdev->name,
1559 ((hw->bus.speed == e1000_bus_speed_2500)
1560 ? "2.5Gb/s" : "unknown"),
59c3de89
AD		 1561 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1562 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1563 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1564 "unknown"),
7c510e4b 1565 netdev->dev_addr);
9d5c8243
AK		 1566
1567 igb_read_part_num(hw, &part_num);
1568 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1569 (part_num >> 8), (part_num & 0xff));
1570
1571 dev_info(&pdev->dev,
1572 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1573 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1574 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1575 adapter->num_rx_queues, adapter->num_tx_queues);
1576
9d5c8243
AK		 1577 return 0;
1578
1579err_register:
1580 igb_release_hw_control(adapter);
1581err_eeprom:
1582 if (!igb_check_reset_block(hw))
f5f4cf08 1583 igb_reset_phy(hw);
9d5c8243
AK		 1584
1585 if (hw->flash_address)
1586 iounmap(hw->flash_address);
1587
a88f10ec 1588 igb_free_queues(adapter);
9d5c8243 1589err_sw_init:
9d5c8243
AK		 1590 iounmap(hw->hw_addr);
1591err_ioremap:
1592 free_netdev(netdev);
1593err_alloc_etherdev:
aed5dec3
AD		 1594 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1595 IORESOURCE_MEM));
9d5c8243
AK		 1596err_pci_reg:
1597err_dma:
1598 pci_disable_device(pdev);
1599 return err;
1600}
1601
1602/**
1603 * igb_remove - Device Removal Routine
1604 * @pdev: PCI device information struct
1605 *
1606 * igb_remove is called by the PCI subsystem to alert the driver
1607 * that it should release a PCI device. The could be caused by a
1608 * Hot-Plug event, or because the driver is going to be removed from
1609 * memory.
1610 **/
1611static void __devexit igb_remove(struct pci_dev *pdev)
1612{
1613 struct net_device *netdev = pci_get_drvdata(pdev);
1614 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 1615 struct e1000_hw *hw = &adapter->hw;
ea943d41 1616 int err;
9d5c8243
AK		 1617
1618 /* flush_scheduled work may reschedule our watchdog task, so
1619 * explicitly disable watchdog tasks from being rescheduled */
1620 set_bit(__IGB_DOWN, &adapter->state);
1621 del_timer_sync(&adapter->watchdog_timer);
1622 del_timer_sync(&adapter->phy_info_timer);
1623
1624 flush_scheduled_work();
1625
421e02f0 1626#ifdef CONFIG_IGB_DCA
7dfc16fa 1627 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1628 dev_info(&pdev->dev, "DCA disabled\n");
1629 dca_remove_requester(&pdev->dev);
7dfc16fa 1630 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 1631 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 1632 }
1633#endif
1634
9d5c8243
AK		 1635 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1636 * would have already happened in close and is redundant. */
1637 igb_release_hw_control(adapter);
1638
1639 unregister_netdev(netdev);
1640
f5f4cf08
AD		 1641 if (!igb_check_reset_block(&adapter->hw))
1642 igb_reset_phy(&adapter->hw);
9d5c8243 1643
9d5c8243
AK		 1644 igb_reset_interrupt_capability(adapter);
1645
a88f10ec 1646 igb_free_queues(adapter);
9d5c8243 1647
37680117
AD		 1648#ifdef CONFIG_PCI_IOV
1649 /* reclaim resources allocated to VFs */
1650 if (adapter->vf_data) {
1651 /* disable iov and allow time for transactions to clear */
1652 pci_disable_sriov(pdev);
1653 msleep(500);
1654
1655 kfree(adapter->vf_data);
1656 adapter->vf_data = NULL;
1657 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1658 msleep(100);
1659 dev_info(&pdev->dev, "IOV Disabled\n");
1660 }
1661#endif
28b0759c
AD		 1662 iounmap(hw->hw_addr);
1663 if (hw->flash_address)
1664 iounmap(hw->flash_address);
aed5dec3
AD		 1665 pci_release_selected_regions(pdev, pci_select_bars(pdev,
1666 IORESOURCE_MEM));
9d5c8243
AK		 1667
1668 free_netdev(netdev);
1669
ea943d41
JK		 1670 err = pci_disable_pcie_error_reporting(pdev);
1671 if (err)
1672 dev_err(&pdev->dev,
1673 "pci_disable_pcie_error_reporting failed 0x%x\n", err);
40a914fa 1674
9d5c8243
AK		 1675 pci_disable_device(pdev);
1676}
1677
1678/**
1679 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1680 * @adapter: board private structure to initialize
1681 *
1682 * igb_sw_init initializes the Adapter private data structure.
1683 * Fields are initialized based on PCI device information and
1684 * OS network device settings (MTU size).
1685 **/
1686static int __devinit igb_sw_init(struct igb_adapter *adapter)
1687{
1688 struct e1000_hw *hw = &adapter->hw;
1689 struct net_device *netdev = adapter->netdev;
1690 struct pci_dev *pdev = adapter->pdev;
1691
1692 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1693
68fd9910
AD		 1694 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1695 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1696 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1697 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1698 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1699 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1700
661086df
PWJ		 1701 /* This call may decrease the number of queues depending on
1702 * interrupt mode. */
9d5c8243
AK		 1703 igb_set_interrupt_capability(adapter);
1704
1705 if (igb_alloc_queues(adapter)) {
1706 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1707 return -ENOMEM;
1708 }
1709
1710 /* Explicitly disable IRQ since the NIC can be in any state. */
1711 igb_irq_disable(adapter);
1712
1713 set_bit(__IGB_DOWN, &adapter->state);
1714 return 0;
1715}
1716
1717/**
1718 * igb_open - Called when a network interface is made active
1719 * @netdev: network interface device structure
1720 *
1721 * Returns 0 on success, negative value on failure
1722 *
1723 * The open entry point is called when a network interface is made
1724 * active by the system (IFF_UP). At this point all resources needed
1725 * for transmit and receive operations are allocated, the interrupt
1726 * handler is registered with the OS, the watchdog timer is started,
1727 * and the stack is notified that the interface is ready.
1728 **/
1729static int igb_open(struct net_device *netdev)
1730{
1731 struct igb_adapter *adapter = netdev_priv(netdev);
1732 struct e1000_hw *hw = &adapter->hw;
1733 int err;
1734 int i;
1735
1736 /* disallow open during test */
1737 if (test_bit(__IGB_TESTING, &adapter->state))
1738 return -EBUSY;
1739
b168dfc5
JB		 1740 netif_carrier_off(netdev);
1741
9d5c8243
AK		 1742 /* allocate transmit descriptors */
1743 err = igb_setup_all_tx_resources(adapter);
1744 if (err)
1745 goto err_setup_tx;
1746
1747 /* allocate receive descriptors */
1748 err = igb_setup_all_rx_resources(adapter);
1749 if (err)
1750 goto err_setup_rx;
1751
1752 /* e1000_power_up_phy(adapter); */
1753
1754 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1755 if ((adapter->hw.mng_cookie.status &
1756 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1757 igb_update_mng_vlan(adapter);
1758
1759 /* before we allocate an interrupt, we must be ready to handle it.
1760 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1761 * as soon as we call pci_request_irq, so we have to setup our
1762 * clean_rx handler before we do so. */
1763 igb_configure(adapter);
1764
4ae196df 1765 igb_vmm_control(adapter);
e1739522
AD		 1766 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1767 igb_set_vmolr(hw, adapter->vfs_allocated_count);
1768
9d5c8243
AK		 1769 err = igb_request_irq(adapter);
1770 if (err)
1771 goto err_req_irq;
1772
1773 /* From here on the code is the same as igb_up() */
1774 clear_bit(__IGB_DOWN, &adapter->state);
1775
844290e5
PW		 1776 for (i = 0; i < adapter->num_rx_queues; i++)
1777 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1778
1779 /* Clear any pending interrupts. */
1780 rd32(E1000_ICR);
844290e5
PW		 1781
1782 igb_irq_enable(adapter);
1783
d55b53ff
JK		 1784 netif_tx_start_all_queues(netdev);
1785
9d5c8243
AK		 1786 /* Fire a link status change interrupt to start the watchdog. */
1787 wr32(E1000_ICS, E1000_ICS_LSC);
1788
1789 return 0;
1790
1791err_req_irq:
1792 igb_release_hw_control(adapter);
1793 /* e1000_power_down_phy(adapter); */
1794 igb_free_all_rx_resources(adapter);
1795err_setup_rx:
1796 igb_free_all_tx_resources(adapter);
1797err_setup_tx:
1798 igb_reset(adapter);
1799
1800 return err;
1801}
1802
1803/**
1804 * igb_close - Disables a network interface
1805 * @netdev: network interface device structure
1806 *
1807 * Returns 0, this is not allowed to fail
1808 *
1809 * The close entry point is called when an interface is de-activated
1810 * by the OS. The hardware is still under the driver's control, but
1811 * needs to be disabled. A global MAC reset is issued to stop the
1812 * hardware, and all transmit and receive resources are freed.
1813 **/
1814static int igb_close(struct net_device *netdev)
1815{
1816 struct igb_adapter *adapter = netdev_priv(netdev);
1817
1818 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1819 igb_down(adapter);
1820
1821 igb_free_irq(adapter);
1822
1823 igb_free_all_tx_resources(adapter);
1824 igb_free_all_rx_resources(adapter);
1825
1826 /* kill manageability vlan ID if supported, but not if a vlan with
1827 * the same ID is registered on the host OS (let 8021q kill it) */
1828 if ((adapter->hw.mng_cookie.status &
1829 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1830 !(adapter->vlgrp &&
1831 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1832 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1833
1834 return 0;
1835}
1836
1837/**
1838 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1839 * @adapter: board private structure
1840 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1841 *
1842 * Return 0 on success, negative on failure
1843 **/
9d5c8243
AK		 1844int igb_setup_tx_resources(struct igb_adapter *adapter,
1845 struct igb_ring *tx_ring)
1846{
1847 struct pci_dev *pdev = adapter->pdev;
1848 int size;
1849
1850 size = sizeof(struct igb_buffer) * tx_ring->count;
1851 tx_ring->buffer_info = vmalloc(size);
1852 if (!tx_ring->buffer_info)
1853 goto err;
1854 memset(tx_ring->buffer_info, 0, size);
1855
1856 /* round up to nearest 4K */
85e8d004 1857 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 1858 tx_ring->size = ALIGN(tx_ring->size, 4096);
1859
1860 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1861 &tx_ring->dma);
1862
1863 if (!tx_ring->desc)
1864 goto err;
1865
1866 tx_ring->adapter = adapter;
1867 tx_ring->next_to_use = 0;
1868 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1869 return 0;
1870
1871err:
1872 vfree(tx_ring->buffer_info);
1873 dev_err(&adapter->pdev->dev,
1874 "Unable to allocate memory for the transmit descriptor ring\n");
1875 return -ENOMEM;
1876}
1877
1878/**
1879 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1880 * (Descriptors) for all queues
1881 * @adapter: board private structure
1882 *
1883 * Return 0 on success, negative on failure
1884 **/
1885static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1886{
1887 int i, err = 0;
661086df 1888 int r_idx;
9d5c8243
AK		 1889
1890 for (i = 0; i < adapter->num_tx_queues; i++) {
1891 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1892 if (err) {
1893 dev_err(&adapter->pdev->dev,
1894 "Allocation for Tx Queue %u failed\n", i);
1895 for (i--; i >= 0; i--)
3b644cf6 1896 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1897 break;
1898 }
1899 }
1900
661086df
PWJ		 1901 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1902 r_idx = i % adapter->num_tx_queues;
1903 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
eebbbdba 1904 }
9d5c8243
AK		 1905 return err;
1906}
1907
1908/**
1909 * igb_configure_tx - Configure transmit Unit after Reset
1910 * @adapter: board private structure
1911 *
1912 * Configure the Tx unit of the MAC after a reset.
1913 **/
1914static void igb_configure_tx(struct igb_adapter *adapter)
1915{
0e014cb1 1916 u64 tdba;
9d5c8243
AK		 1917 struct e1000_hw *hw = &adapter->hw;
1918 u32 tctl;
1919 u32 txdctl, txctrl;
26bc19ec 1920 int i, j;
9d5c8243
AK		 1921
1922 for (i = 0; i < adapter->num_tx_queues; i++) {
73cd78f1 1923 struct igb_ring *ring = &adapter->tx_ring[i];
26bc19ec
AD		 1924 j = ring->reg_idx;
1925 wr32(E1000_TDLEN(j),
85e8d004 1926 ring->count * sizeof(union e1000_adv_tx_desc));
9d5c8243 1927 tdba = ring->dma;
26bc19ec 1928 wr32(E1000_TDBAL(j),
73cd78f1 1929 tdba & 0x00000000ffffffffULL);
26bc19ec 1930 wr32(E1000_TDBAH(j), tdba >> 32);
9d5c8243 1931
26bc19ec
AD		 1932 ring->head = E1000_TDH(j);
1933 ring->tail = E1000_TDT(j);
9d5c8243
AK		 1934 writel(0, hw->hw_addr + ring->tail);
1935 writel(0, hw->hw_addr + ring->head);
26bc19ec 1936 txdctl = rd32(E1000_TXDCTL(j));
9d5c8243 1937 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
26bc19ec 1938 wr32(E1000_TXDCTL(j), txdctl);
9d5c8243
AK		 1939
1940 /* Turn off Relaxed Ordering on head write-backs. The
1941 * writebacks MUST be delivered in order or it will
1942 * completely screw up our bookeeping.
1943 */
26bc19ec 1944 txctrl = rd32(E1000_DCA_TXCTRL(j));
9d5c8243 1945 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
26bc19ec 1946 wr32(E1000_DCA_TXCTRL(j), txctrl);
9d5c8243
AK		 1947 }
1948
e1739522
AD		 1949 /* disable queue 0 to prevent tail bump w/o re-configuration */
1950 if (adapter->vfs_allocated_count)
1951 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 1952
1953 /* Program the Transmit Control Register */
9d5c8243
AK		 1954 tctl = rd32(E1000_TCTL);
1955 tctl &= ~E1000_TCTL_CT;
1956 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1957 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1958
1959 igb_config_collision_dist(hw);
1960
1961 /* Setup Transmit Descriptor Settings for eop descriptor */
1962 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1963
1964 /* Enable transmits */
1965 tctl |= E1000_TCTL_EN;
1966
1967 wr32(E1000_TCTL, tctl);
1968}
1969
1970/**
1971 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1972 * @adapter: board private structure
1973 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1974 *
1975 * Returns 0 on success, negative on failure
1976 **/
9d5c8243
AK		 1977int igb_setup_rx_resources(struct igb_adapter *adapter,
1978 struct igb_ring *rx_ring)
1979{
1980 struct pci_dev *pdev = adapter->pdev;
1981 int size, desc_len;
1982
1983 size = sizeof(struct igb_buffer) * rx_ring->count;
1984 rx_ring->buffer_info = vmalloc(size);
1985 if (!rx_ring->buffer_info)
1986 goto err;
1987 memset(rx_ring->buffer_info, 0, size);
1988
1989 desc_len = sizeof(union e1000_adv_rx_desc);
1990
1991 /* Round up to nearest 4K */
1992 rx_ring->size = rx_ring->count * desc_len;
1993 rx_ring->size = ALIGN(rx_ring->size, 4096);
1994
1995 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1996 &rx_ring->dma);
1997
1998 if (!rx_ring->desc)
1999 goto err;
2000
2001 rx_ring->next_to_clean = 0;
2002 rx_ring->next_to_use = 0;
9d5c8243
AK		 2003
2004 rx_ring->adapter = adapter;
9d5c8243
AK		 2005
2006 return 0;
2007
2008err:
2009 vfree(rx_ring->buffer_info);
2010 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
2011 "the receive descriptor ring\n");
2012 return -ENOMEM;
2013}
2014
2015/**
2016 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2017 * (Descriptors) for all queues
2018 * @adapter: board private structure
2019 *
2020 * Return 0 on success, negative on failure
2021 **/
2022static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2023{
2024 int i, err = 0;
2025
2026 for (i = 0; i < adapter->num_rx_queues; i++) {
2027 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2028 if (err) {
2029 dev_err(&adapter->pdev->dev,
2030 "Allocation for Rx Queue %u failed\n", i);
2031 for (i--; i >= 0; i--)
3b644cf6 2032 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2033 break;
2034 }
2035 }
2036
2037 return err;
2038}
2039
2040/**
2041 * igb_setup_rctl - configure the receive control registers
2042 * @adapter: Board private structure
2043 **/
2044static void igb_setup_rctl(struct igb_adapter *adapter)
2045{
2046 struct e1000_hw *hw = &adapter->hw;
2047 u32 rctl;
2048 u32 srrctl = 0;
77a22941 2049 int i;
9d5c8243
AK		 2050
2051 rctl = rd32(E1000_RCTL);
2052
2053 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2054 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2055
69d728ba 2056 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2057 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2058
87cb7e8c
AK		 2059 /*
2060 * enable stripping of CRC. It's unlikely this will break BMC
2061 * redirection as it did with e1000. Newer features require
2062 * that the HW strips the CRC.
73cd78f1 2063 */
87cb7e8c 2064 rctl |= E1000_RCTL_SECRC;
9d5c8243 2065
9b07f3d3 2066 /*
ec54d7d6 2067 * disable store bad packets and clear size bits.
9b07f3d3 2068 */
ec54d7d6 2069 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2070
ec54d7d6 2071 /* enable LPE when to prevent packets larger than max_frame_size */
9b07f3d3 2072 rctl |= E1000_RCTL_LPE;
b4557be2
AD		 2073
2074 /* Setup buffer sizes */
2075 switch (adapter->rx_buffer_len) {
2076 case IGB_RXBUFFER_256:
2077 rctl |= E1000_RCTL_SZ_256;
2078 break;
2079 case IGB_RXBUFFER_512:
2080 rctl |= E1000_RCTL_SZ_512;
2081 break;
2082 default:
2083 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2084 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2085 break;
9d5c8243
AK		 2086 }
2087
2088 /* 82575 and greater support packet-split where the protocol
2089 * header is placed in skb->data and the packet data is
2090 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2091 * In the case of a non-split, skb->data is linearly filled,
2092 * followed by the page buffers. Therefore, skb->data is
2093 * sized to hold the largest protocol header.
2094 */
2095 /* allocations using alloc_page take too long for regular MTU
2096 * so only enable packet split for jumbo frames */
ec54d7d6 2097 if (adapter->netdev->mtu > ETH_DATA_LEN) {
9d5c8243 2098 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 2099 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 2100 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 2101 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2102 } else {
2103 adapter->rx_ps_hdr_size = 0;
2104 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2105 }
2106
e1739522
AD		 2107 /* Attention!!! For SR-IOV PF driver operations you must enable
2108 * queue drop for all VF and PF queues to prevent head of line blocking
2109 * if an un-trusted VF does not provide descriptors to hardware.
2110 */
2111 if (adapter->vfs_allocated_count) {
2112 u32 vmolr;
2113
e1739522
AD		 2114 /* set all queue drop enable bits */
2115 wr32(E1000_QDE, ALL_QUEUES);
2116 srrctl |= E1000_SRRCTL_DROP_EN;
2117
2118 /* disable queue 0 to prevent tail write w/o re-config */
2119 wr32(E1000_RXDCTL(0), 0);
2120
77a22941 2121 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
e1739522
AD		 2122 if (rctl & E1000_RCTL_LPE)
2123 vmolr |= E1000_VMOLR_LPE;
77a22941 2124 if (adapter->num_rx_queues > 1)
e1739522 2125 vmolr |= E1000_VMOLR_RSSE;
77a22941 2126 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
e1739522
AD		 2127 }
2128
26bc19ec 2129 for (i = 0; i < adapter->num_rx_queues; i++) {
77a22941 2130 int j = adapter->rx_ring[i].reg_idx;
26bc19ec
AD		 2131 wr32(E1000_SRRCTL(j), srrctl);
2132 }
9d5c8243
AK		 2133
2134 wr32(E1000_RCTL, rctl);
2135}
2136
e1739522
AD		 2137/**
2138 * igb_rlpml_set - set maximum receive packet size
2139 * @adapter: board private structure
2140 *
2141 * Configure maximum receivable packet size.
2142 **/
2143static void igb_rlpml_set(struct igb_adapter *adapter)
2144{
2145 u32 max_frame_size = adapter->max_frame_size;
2146 struct e1000_hw *hw = &adapter->hw;
2147 u16 pf_id = adapter->vfs_allocated_count;
2148
2149 if (adapter->vlgrp)
2150 max_frame_size += VLAN_TAG_SIZE;
2151
2152 /* if vfs are enabled we set RLPML to the largest possible request
2153 * size and set the VMOLR RLPML to the size we need */
2154 if (pf_id) {
2155 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2156 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2157 }
2158
2159 wr32(E1000_RLPML, max_frame_size);
2160}
2161
2162/**
2163 * igb_configure_vt_default_pool - Configure VT default pool
2164 * @adapter: board private structure
2165 *
2166 * Configure the default pool
2167 **/
2168static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2169{
2170 struct e1000_hw *hw = &adapter->hw;
2171 u16 pf_id = adapter->vfs_allocated_count;
2172 u32 vtctl;
2173
2174 /* not in sr-iov mode - do nothing */
2175 if (!pf_id)
2176 return;
2177
2178 vtctl = rd32(E1000_VT_CTL);
2179 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2180 E1000_VT_CTL_DISABLE_DEF_POOL);
2181 vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2182 wr32(E1000_VT_CTL, vtctl);
2183}
2184
9d5c8243
AK		 2185/**
2186 * igb_configure_rx - Configure receive Unit after Reset
2187 * @adapter: board private structure
2188 *
2189 * Configure the Rx unit of the MAC after a reset.
2190 **/
2191static void igb_configure_rx(struct igb_adapter *adapter)
2192{
2193 u64 rdba;
2194 struct e1000_hw *hw = &adapter->hw;
2195 u32 rctl, rxcsum;
2196 u32 rxdctl;
9107584e 2197 int i;
9d5c8243
AK		 2198
2199 /* disable receives while setting up the descriptors */
2200 rctl = rd32(E1000_RCTL);
2201 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2202 wrfl();
2203 mdelay(10);
2204
2205 if (adapter->itr_setting > 3)
6eb5a7f1 2206 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 2207
2208 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2209 * the Base and Length of the Rx Descriptor Ring */
2210 for (i = 0; i < adapter->num_rx_queues; i++) {
73cd78f1 2211 struct igb_ring *ring = &adapter->rx_ring[i];
9107584e 2212 int j = ring->reg_idx;
9d5c8243 2213 rdba = ring->dma;
26bc19ec 2214 wr32(E1000_RDBAL(j),
73cd78f1 2215 rdba & 0x00000000ffffffffULL);
26bc19ec
AD		 2216 wr32(E1000_RDBAH(j), rdba >> 32);
2217 wr32(E1000_RDLEN(j),
73cd78f1 2218 ring->count * sizeof(union e1000_adv_rx_desc));
9d5c8243 2219
26bc19ec
AD		 2220 ring->head = E1000_RDH(j);
2221 ring->tail = E1000_RDT(j);
9d5c8243
AK		 2222 writel(0, hw->hw_addr + ring->tail);
2223 writel(0, hw->hw_addr + ring->head);
2224
26bc19ec 2225 rxdctl = rd32(E1000_RXDCTL(j));
9d5c8243
AK		 2226 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2227 rxdctl &= 0xFFF00000;
2228 rxdctl |= IGB_RX_PTHRESH;
2229 rxdctl |= IGB_RX_HTHRESH << 8;
2230 rxdctl |= IGB_RX_WTHRESH << 16;
26bc19ec 2231 wr32(E1000_RXDCTL(j), rxdctl);
9d5c8243
AK		 2232 }
2233
2234 if (adapter->num_rx_queues > 1) {
2235 u32 random[10];
2236 u32 mrqc;
2237 u32 j, shift;
2238 union e1000_reta {
2239 u32 dword;
2240 u8 bytes[4];
2241 } reta;
2242
2243 get_random_bytes(&random[0], 40);
2244
2d064c06
AD		 2245 if (hw->mac.type >= e1000_82576)
2246 shift = 0;
2247 else
2248 shift = 6;
9d5c8243
AK		 2249 for (j = 0; j < (32 * 4); j++) {
2250 reta.bytes[j & 3] =
26bc19ec 2251 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
9d5c8243
AK		 2252 if ((j & 3) == 3)
2253 writel(reta.dword,
2254 hw->hw_addr + E1000_RETA(0) + (j & ~3));
2255 }
e1739522
AD		 2256 if (adapter->vfs_allocated_count)
2257 mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2258 else
2259 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
9d5c8243
AK		 2260
2261 /* Fill out hash function seeds */
2262 for (j = 0; j < 10; j++)
2263 array_wr32(E1000_RSSRK(0), j, random[j]);
2264
2265 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2266 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2267 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2268 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2269 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2270 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2271 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2272 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2273
9d5c8243 2274 wr32(E1000_MRQC, mrqc);
2844f797 2275 } else if (adapter->vfs_allocated_count) {
e1739522 2276 /* Enable multi-queue for sr-iov */
2844f797 2277 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
9d5c8243
AK		 2278 }
2279
2844f797
AD		 2280 /* Enable Receive Checksum Offload for TCP and UDP */
2281 rxcsum = rd32(E1000_RXCSUM);
2282 /* Disable raw packet checksumming */
2283 rxcsum |= E1000_RXCSUM_PCSD;
7beb0146
AD		 2284
2285 if (adapter->hw.mac.type == e1000_82576)
b9473560
JB		 2286 /* Enable Receive Checksum Offload for SCTP */
2287 rxcsum |= E1000_RXCSUM_CRCOFL;
2288
7beb0146 2289 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2844f797
AD		 2290 wr32(E1000_RXCSUM, rxcsum);
2291
e1739522
AD		 2292 /* Set the default pool for the PF's first queue */
2293 igb_configure_vt_default_pool(adapter);
2294
2295 igb_rlpml_set(adapter);
9d5c8243
AK		 2296
2297 /* Enable Receives */
2298 wr32(E1000_RCTL, rctl);
2299}
2300
2301/**
2302 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 2303 * @tx_ring: Tx descriptor ring for a specific queue
2304 *
2305 * Free all transmit software resources
2306 **/
68fd9910 2307void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2308{
3b644cf6 2309 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 2310
3b644cf6 2311 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 2312
2313 vfree(tx_ring->buffer_info);
2314 tx_ring->buffer_info = NULL;
2315
2316 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2317
2318 tx_ring->desc = NULL;
2319}
2320
2321/**
2322 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2323 * @adapter: board private structure
2324 *
2325 * Free all transmit software resources
2326 **/
2327static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2328{
2329 int i;
2330
2331 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2332 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2333}
2334
2335static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2336 struct igb_buffer *buffer_info)
2337{
65689fef 2338 buffer_info->dma = 0;
9d5c8243 2339 if (buffer_info->skb) {
65689fef
AD		 2340 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2341 DMA_TO_DEVICE);
9d5c8243
AK		 2342 dev_kfree_skb_any(buffer_info->skb);
2343 buffer_info->skb = NULL;
2344 }
2345 buffer_info->time_stamp = 0;
2346 /* buffer_info must be completely set up in the transmit path */
2347}
2348
2349/**
2350 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2351 * @tx_ring: ring to be cleaned
2352 **/
3b644cf6 2353static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2354{
3b644cf6 2355 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2356 struct igb_buffer *buffer_info;
2357 unsigned long size;
2358 unsigned int i;
2359
2360 if (!tx_ring->buffer_info)
2361 return;
2362 /* Free all the Tx ring sk_buffs */
2363
2364 for (i = 0; i < tx_ring->count; i++) {
2365 buffer_info = &tx_ring->buffer_info[i];
2366 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2367 }
2368
2369 size = sizeof(struct igb_buffer) * tx_ring->count;
2370 memset(tx_ring->buffer_info, 0, size);
2371
2372 /* Zero out the descriptor ring */
2373
2374 memset(tx_ring->desc, 0, tx_ring->size);
2375
2376 tx_ring->next_to_use = 0;
2377 tx_ring->next_to_clean = 0;
2378
2379 writel(0, adapter->hw.hw_addr + tx_ring->head);
2380 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2381}
2382
2383/**
2384 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2385 * @adapter: board private structure
2386 **/
2387static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2388{
2389 int i;
2390
2391 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2392 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2393}
2394
2395/**
2396 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2397 * @rx_ring: ring to clean the resources from
2398 *
2399 * Free all receive software resources
2400 **/
68fd9910 2401void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2402{
3b644cf6 2403 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2404
3b644cf6 2405 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2406
2407 vfree(rx_ring->buffer_info);
2408 rx_ring->buffer_info = NULL;
2409
2410 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2411
2412 rx_ring->desc = NULL;
2413}
2414
2415/**
2416 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2417 * @adapter: board private structure
2418 *
2419 * Free all receive software resources
2420 **/
2421static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2422{
2423 int i;
2424
2425 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2426 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2427}
2428
2429/**
2430 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2431 * @rx_ring: ring to free buffers from
2432 **/
3b644cf6 2433static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2434{
3b644cf6 2435 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2436 struct igb_buffer *buffer_info;
2437 struct pci_dev *pdev = adapter->pdev;
2438 unsigned long size;
2439 unsigned int i;
2440
2441 if (!rx_ring->buffer_info)
2442 return;
2443 /* Free all the Rx ring sk_buffs */
2444 for (i = 0; i < rx_ring->count; i++) {
2445 buffer_info = &rx_ring->buffer_info[i];
2446 if (buffer_info->dma) {
2447 if (adapter->rx_ps_hdr_size)
2448 pci_unmap_single(pdev, buffer_info->dma,
2449 adapter->rx_ps_hdr_size,
2450 PCI_DMA_FROMDEVICE);
2451 else
2452 pci_unmap_single(pdev, buffer_info->dma,
2453 adapter->rx_buffer_len,
2454 PCI_DMA_FROMDEVICE);
2455 buffer_info->dma = 0;
2456 }
2457
2458 if (buffer_info->skb) {
2459 dev_kfree_skb(buffer_info->skb);
2460 buffer_info->skb = NULL;
2461 }
2462 if (buffer_info->page) {
bf36c1a0
AD		 2463 if (buffer_info->page_dma)
2464 pci_unmap_page(pdev, buffer_info->page_dma,
2465 PAGE_SIZE / 2,
2466 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2467 put_page(buffer_info->page);
2468 buffer_info->page = NULL;
2469 buffer_info->page_dma = 0;
bf36c1a0 2470 buffer_info->page_offset = 0;
9d5c8243
AK		 2471 }
2472 }
2473
9d5c8243
AK		 2474 size = sizeof(struct igb_buffer) * rx_ring->count;
2475 memset(rx_ring->buffer_info, 0, size);
2476
2477 /* Zero out the descriptor ring */
2478 memset(rx_ring->desc, 0, rx_ring->size);
2479
2480 rx_ring->next_to_clean = 0;
2481 rx_ring->next_to_use = 0;
2482
2483 writel(0, adapter->hw.hw_addr + rx_ring->head);
2484 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2485}
2486
2487/**
2488 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2489 * @adapter: board private structure
2490 **/
2491static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2492{
2493 int i;
2494
2495 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2496 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2497}
2498
2499/**
2500 * igb_set_mac - Change the Ethernet Address of the NIC
2501 * @netdev: network interface device structure
2502 * @p: pointer to an address structure
2503 *
2504 * Returns 0 on success, negative on failure
2505 **/
2506static int igb_set_mac(struct net_device *netdev, void *p)
2507{
2508 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 2509 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2510 struct sockaddr *addr = p;
2511
2512 if (!is_valid_ether_addr(addr->sa_data))
2513 return -EADDRNOTAVAIL;
2514
2515 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 2516 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 2517
28b0759c 2518 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
9d5c8243 2519
e1739522
AD		 2520 igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2521
9d5c8243
AK		 2522 return 0;
2523}
2524
2525/**
2526 * igb_set_multi - Multicast and Promiscuous mode set
2527 * @netdev: network interface device structure
2528 *
2529 * The set_multi entry point is called whenever the multicast address
2530 * list or the network interface flags are updated. This routine is
2531 * responsible for configuring the hardware for proper multicast,
2532 * promiscuous mode, and all-multi behavior.
2533 **/
2534static void igb_set_multi(struct net_device *netdev)
2535{
2536 struct igb_adapter *adapter = netdev_priv(netdev);
2537 struct e1000_hw *hw = &adapter->hw;
2538 struct e1000_mac_info *mac = &hw->mac;
2539 struct dev_mc_list *mc_ptr;
c5cd11e3 2540 u8 *mta_list = NULL;
9d5c8243
AK		 2541 u32 rctl;
2542 int i;
2543
2544 /* Check for Promiscuous and All Multicast modes */
2545
2546 rctl = rd32(E1000_RCTL);
2547
746b9f02 2548 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2549 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2550 rctl &= ~E1000_RCTL_VFE;
2551 } else {
2552 if (netdev->flags & IFF_ALLMULTI) {
2553 rctl |= E1000_RCTL_MPE;
2554 rctl &= ~E1000_RCTL_UPE;
2555 } else
2556 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2557 rctl |= E1000_RCTL_VFE;
746b9f02 2558 }
9d5c8243
AK		 2559 wr32(E1000_RCTL, rctl);
2560
c5cd11e3
AD		 2561 if (netdev->mc_count) {
2562 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2563 if (!mta_list) {
2564 dev_err(&adapter->pdev->dev,
2565 "failed to allocate multicast filter list\n");
2566 return;
2567 }
9d5c8243
AK		 2568 }
2569
9d5c8243
AK		 2570 /* The shared function expects a packed array of only addresses. */
2571 mc_ptr = netdev->mc_list;
2572
2573 for (i = 0; i < netdev->mc_count; i++) {
2574 if (!mc_ptr)
2575 break;
2576 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2577 mc_ptr = mc_ptr->next;
2578 }
e1739522
AD		 2579 igb_update_mc_addr_list(hw, mta_list, i,
2580 adapter->vfs_allocated_count + 1,
2581 mac->rar_entry_count);
2582
2583 igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
4ae196df
AD		 2584 igb_restore_vf_multicasts(adapter);
2585
9d5c8243
AK		 2586 kfree(mta_list);
2587}
2588
2589/* Need to wait a few seconds after link up to get diagnostic information from
2590 * the phy */
2591static void igb_update_phy_info(unsigned long data)
2592{
2593 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2594 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2595}
2596
4d6b725e
AD		 2597/**
2598 * igb_has_link - check shared code for link and determine up/down
2599 * @adapter: pointer to driver private info
2600 **/
2601static bool igb_has_link(struct igb_adapter *adapter)
2602{
2603 struct e1000_hw *hw = &adapter->hw;
2604 bool link_active = false;
2605 s32 ret_val = 0;
2606
2607 /* get_link_status is set on LSC (link status) interrupt or
2608 * rx sequence error interrupt. get_link_status will stay
2609 * false until the e1000_check_for_link establishes link
2610 * for copper adapters ONLY
2611 */
2612 switch (hw->phy.media_type) {
2613 case e1000_media_type_copper:
2614 if (hw->mac.get_link_status) {
2615 ret_val = hw->mac.ops.check_for_link(hw);
2616 link_active = !hw->mac.get_link_status;
2617 } else {
2618 link_active = true;
2619 }
2620 break;
4d6b725e
AD		 2621 case e1000_media_type_internal_serdes:
2622 ret_val = hw->mac.ops.check_for_link(hw);
2623 link_active = hw->mac.serdes_has_link;
2624 break;
2625 default:
2626 case e1000_media_type_unknown:
2627 break;
2628 }
2629
2630 return link_active;
2631}
2632
9d5c8243
AK		 2633/**
2634 * igb_watchdog - Timer Call-back
2635 * @data: pointer to adapter cast into an unsigned long
2636 **/
2637static void igb_watchdog(unsigned long data)
2638{
2639 struct igb_adapter *adapter = (struct igb_adapter *)data;
2640 /* Do the rest outside of interrupt context */
2641 schedule_work(&adapter->watchdog_task);
2642}
2643
2644static void igb_watchdog_task(struct work_struct *work)
2645{
2646 struct igb_adapter *adapter = container_of(work,
2647 struct igb_adapter, watchdog_task);
2648 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 2649 struct net_device *netdev = adapter->netdev;
2650 struct igb_ring *tx_ring = adapter->tx_ring;
9d5c8243 2651 u32 link;
7a6ea550 2652 u32 eics = 0;
7a6ea550 2653 int i;
9d5c8243 2654
4d6b725e
AD		 2655 link = igb_has_link(adapter);
2656 if ((netif_carrier_ok(netdev)) && link)
9d5c8243
AK		 2657 goto link_up;
2658
9d5c8243
AK		 2659 if (link) {
2660 if (!netif_carrier_ok(netdev)) {
2661 u32 ctrl;
2662 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2663 &adapter->link_speed,
2664 &adapter->link_duplex);
2665
2666 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2667 /* Links status message must follow this format */
2668 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2669 "Flow Control: %s\n",
527d47c1 2670 netdev->name,
9d5c8243
AK		 2671 adapter->link_speed,
2672 adapter->link_duplex == FULL_DUPLEX ?
2673 "Full Duplex" : "Half Duplex",
2674 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2675 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2676 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2677 E1000_CTRL_TFCE) ? "TX" : "None")));
2678
2679 /* tweak tx_queue_len according to speed/duplex and
2680 * adjust the timeout factor */
2681 netdev->tx_queue_len = adapter->tx_queue_len;
2682 adapter->tx_timeout_factor = 1;
2683 switch (adapter->link_speed) {
2684 case SPEED_10:
2685 netdev->tx_queue_len = 10;
2686 adapter->tx_timeout_factor = 14;
2687 break;
2688 case SPEED_100:
2689 netdev->tx_queue_len = 100;
2690 /* maybe add some timeout factor ? */
2691 break;
2692 }
2693
2694 netif_carrier_on(netdev);
9d5c8243 2695
4ae196df
AD		 2696 igb_ping_all_vfs(adapter);
2697
4b1a9877 2698 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2699 if (!test_bit(__IGB_DOWN, &adapter->state))
2700 mod_timer(&adapter->phy_info_timer,
2701 round_jiffies(jiffies + 2 * HZ));
2702 }
2703 } else {
2704 if (netif_carrier_ok(netdev)) {
2705 adapter->link_speed = 0;
2706 adapter->link_duplex = 0;
527d47c1
AD		 2707 /* Links status message must follow this format */
2708 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2709 netdev->name);
9d5c8243 2710 netif_carrier_off(netdev);
4b1a9877 2711
4ae196df
AD		 2712 igb_ping_all_vfs(adapter);
2713
4b1a9877 2714 /* link state has changed, schedule phy info update */
9d5c8243
AK		 2715 if (!test_bit(__IGB_DOWN, &adapter->state))
2716 mod_timer(&adapter->phy_info_timer,
2717 round_jiffies(jiffies + 2 * HZ));
2718 }
2719 }
2720
2721link_up:
2722 igb_update_stats(adapter);
2723
4b1a9877 2724 hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
9d5c8243 2725 adapter->tpt_old = adapter->stats.tpt;
4b1a9877 2726 hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
9d5c8243
AK		 2727 adapter->colc_old = adapter->stats.colc;
2728
2729 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2730 adapter->gorc_old = adapter->stats.gorc;
2731 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2732 adapter->gotc_old = adapter->stats.gotc;
2733
2734 igb_update_adaptive(&adapter->hw);
2735
2736 if (!netif_carrier_ok(netdev)) {
c493ea45 2737 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
9d5c8243
AK		 2738 /* We've lost link, so the controller stops DMA,
2739 * but we've got queued Tx work that's never going
2740 * to get done, so reset controller to flush Tx.
2741 * (Do the reset outside of interrupt context). */
2742 adapter->tx_timeout_count++;
2743 schedule_work(&adapter->reset_task);
c2d5ab49
JB		 2744 /* return immediately since reset is imminent */
2745 return;
9d5c8243
AK		 2746 }
2747 }
2748
2749 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2750 if (adapter->msix_entries) {
2751 for (i = 0; i < adapter->num_rx_queues; i++)
2752 eics |= adapter->rx_ring[i].eims_value;
2753 wr32(E1000_EICS, eics);
2754 } else {
2755 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2756 }
9d5c8243
AK		 2757
2758 /* Force detection of hung controller every watchdog period */
2759 tx_ring->detect_tx_hung = true;
2760
2761 /* Reset the timer */
2762 if (!test_bit(__IGB_DOWN, &adapter->state))
2763 mod_timer(&adapter->watchdog_timer,
2764 round_jiffies(jiffies + 2 * HZ));
2765}
2766
2767enum latency_range {
2768 lowest_latency = 0,
2769 low_latency = 1,
2770 bulk_latency = 2,
2771 latency_invalid = 255
2772};
2773
2774
6eb5a7f1
AD		 2775/**
2776 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2777 *
2778 * Stores a new ITR value based on strictly on packet size. This
2779 * algorithm is less sophisticated than that used in igb_update_itr,
2780 * due to the difficulty of synchronizing statistics across multiple
2781 * receive rings. The divisors and thresholds used by this fuction
2782 * were determined based on theoretical maximum wire speed and testing
2783 * data, in order to minimize response time while increasing bulk
2784 * throughput.
2785 * This functionality is controlled by the InterruptThrottleRate module
2786 * parameter (see igb_param.c)
2787 * NOTE: This function is called only when operating in a multiqueue
2788 * receive environment.
2789 * @rx_ring: pointer to ring
2790 **/
2791static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2792{
6eb5a7f1
AD		 2793 int new_val = rx_ring->itr_val;
2794 int avg_wire_size = 0;
2795 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2796
6eb5a7f1
AD		 2797 if (!rx_ring->total_packets)
2798 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2799
6eb5a7f1
AD		 2800 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2801 * ints/sec - ITR timer value of 120 ticks.
2802 */
2803 if (adapter->link_speed != SPEED_1000) {
2804 new_val = 120;
2805 goto set_itr_val;
9d5c8243 2806 }
6eb5a7f1 2807 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2808
6eb5a7f1
AD		 2809 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2810 avg_wire_size += 24;
2811
2812 /* Don't starve jumbo frames */
2813 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2814
6eb5a7f1
AD		 2815 /* Give a little boost to mid-size frames */
2816 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2817 new_val = avg_wire_size / 3;
2818 else
2819 new_val = avg_wire_size / 2;
9d5c8243 2820
6eb5a7f1 2821set_itr_val:
9d5c8243
AK		 2822 if (new_val != rx_ring->itr_val) {
2823 rx_ring->itr_val = new_val;
6eb5a7f1 2824 rx_ring->set_itr = 1;
9d5c8243 2825 }
6eb5a7f1
AD		 2826clear_counts:
2827 rx_ring->total_bytes = 0;
2828 rx_ring->total_packets = 0;
9d5c8243
AK		 2829}
2830
2831/**
2832 * igb_update_itr - update the dynamic ITR value based on statistics
2833 * Stores a new ITR value based on packets and byte
2834 * counts during the last interrupt. The advantage of per interrupt
2835 * computation is faster updates and more accurate ITR for the current
2836 * traffic pattern. Constants in this function were computed
2837 * based on theoretical maximum wire speed and thresholds were set based
2838 * on testing data as well as attempting to minimize response time
2839 * while increasing bulk throughput.
2840 * this functionality is controlled by the InterruptThrottleRate module
2841 * parameter (see igb_param.c)
2842 * NOTE: These calculations are only valid when operating in a single-
2843 * queue environment.
2844 * @adapter: pointer to adapter
2845 * @itr_setting: current adapter->itr
2846 * @packets: the number of packets during this measurement interval
2847 * @bytes: the number of bytes during this measurement interval
2848 **/
2849static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2850 int packets, int bytes)
2851{
2852 unsigned int retval = itr_setting;
2853
2854 if (packets == 0)
2855 goto update_itr_done;
2856
2857 switch (itr_setting) {
2858 case lowest_latency:
2859 /* handle TSO and jumbo frames */
2860 if (bytes/packets > 8000)
2861 retval = bulk_latency;
2862 else if ((packets < 5) && (bytes > 512))
2863 retval = low_latency;
2864 break;
2865 case low_latency: /* 50 usec aka 20000 ints/s */
2866 if (bytes > 10000) {
2867 /* this if handles the TSO accounting */
2868 if (bytes/packets > 8000) {
2869 retval = bulk_latency;
2870 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2871 retval = bulk_latency;
2872 } else if ((packets > 35)) {
2873 retval = lowest_latency;
2874 }
2875 } else if (bytes/packets > 2000) {
2876 retval = bulk_latency;
2877 } else if (packets <= 2 && bytes < 512) {
2878 retval = lowest_latency;
2879 }
2880 break;
2881 case bulk_latency: /* 250 usec aka 4000 ints/s */
2882 if (bytes > 25000) {
2883 if (packets > 35)
2884 retval = low_latency;
1e5c3d21 2885 } else if (bytes < 1500) {
9d5c8243
AK		 2886 retval = low_latency;
2887 }
2888 break;
2889 }
2890
2891update_itr_done:
2892 return retval;
2893}
2894
6eb5a7f1 2895static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2896{
2897 u16 current_itr;
2898 u32 new_itr = adapter->itr;
2899
2900 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2901 if (adapter->link_speed != SPEED_1000) {
2902 current_itr = 0;
2903 new_itr = 4000;
2904 goto set_itr_now;
2905 }
2906
2907 adapter->rx_itr = igb_update_itr(adapter,
2908 adapter->rx_itr,
2909 adapter->rx_ring->total_packets,
2910 adapter->rx_ring->total_bytes);
9d5c8243 2911
6eb5a7f1 2912 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2913 adapter->tx_itr = igb_update_itr(adapter,
2914 adapter->tx_itr,
2915 adapter->tx_ring->total_packets,
2916 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2917 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2918 } else {
2919 current_itr = adapter->rx_itr;
2920 }
2921
6eb5a7f1 2922 /* conservative mode (itr 3) eliminates the lowest_latency setting */
73cd78f1 2923 if (adapter->itr_setting == 3 && current_itr == lowest_latency)
6eb5a7f1
AD		 2924 current_itr = low_latency;
2925
9d5c8243
AK		 2926 switch (current_itr) {
2927 /* counts and packets in update_itr are dependent on these numbers */
2928 case lowest_latency:
78b1f607 2929 new_itr = 56; /* aka 70,000 ints/sec */
9d5c8243
AK		 2930 break;
2931 case low_latency:
78b1f607 2932 new_itr = 196; /* aka 20,000 ints/sec */
9d5c8243
AK		 2933 break;
2934 case bulk_latency:
78b1f607 2935 new_itr = 980; /* aka 4,000 ints/sec */
9d5c8243
AK		 2936 break;
2937 default:
2938 break;
2939 }
2940
2941set_itr_now:
6eb5a7f1
AD		 2942 adapter->rx_ring->total_bytes = 0;
2943 adapter->rx_ring->total_packets = 0;
2944 if (adapter->rx_ring->buddy) {
2945 adapter->rx_ring->buddy->total_bytes = 0;
2946 adapter->rx_ring->buddy->total_packets = 0;
2947 }
2948
9d5c8243
AK		 2949 if (new_itr != adapter->itr) {
2950 /* this attempts to bias the interrupt rate towards Bulk
2951 * by adding intermediate steps when interrupt rate is
2952 * increasing */
2953 new_itr = new_itr > adapter->itr ?
78b1f607
AD		 2954 max((new_itr * adapter->itr) /
2955 (new_itr + (adapter->itr >> 2)), new_itr) :
9d5c8243
AK		 2956 new_itr;
2957 /* Don't write the value here; it resets the adapter's
2958 * internal timer, and causes us to delay far longer than
2959 * we should between interrupts. Instead, we write the ITR
2960 * value at the beginning of the next interrupt so the timing
2961 * ends up being correct.
2962 */
2963 adapter->itr = new_itr;
78b1f607 2964 adapter->rx_ring->itr_val = new_itr;
6eb5a7f1 2965 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2966 }
2967
2968 return;
2969}
2970
2971
2972#define IGB_TX_FLAGS_CSUM 0x00000001
2973#define IGB_TX_FLAGS_VLAN 0x00000002
2974#define IGB_TX_FLAGS_TSO 0x00000004
2975#define IGB_TX_FLAGS_IPV4 0x00000008
33af6bcc 2976#define IGB_TX_FLAGS_TSTAMP 0x00000010
9d5c8243
AK		 2977#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2978#define IGB_TX_FLAGS_VLAN_SHIFT 16
2979
2980static inline int igb_tso_adv(struct igb_adapter *adapter,
2981 struct igb_ring *tx_ring,
2982 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2983{
2984 struct e1000_adv_tx_context_desc *context_desc;
2985 unsigned int i;
2986 int err;
2987 struct igb_buffer *buffer_info;
2988 u32 info = 0, tu_cmd = 0;
2989 u32 mss_l4len_idx, l4len;
2990 *hdr_len = 0;
2991
2992 if (skb_header_cloned(skb)) {
2993 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2994 if (err)
2995 return err;
2996 }
2997
2998 l4len = tcp_hdrlen(skb);
2999 *hdr_len += l4len;
3000
3001 if (skb->protocol == htons(ETH_P_IP)) {
3002 struct iphdr *iph = ip_hdr(skb);
3003 iph->tot_len = 0;
3004 iph->check = 0;
3005 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3006 iph->daddr, 0,
3007 IPPROTO_TCP,
3008 0);
3009 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3010 ipv6_hdr(skb)->payload_len = 0;
3011 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3012 &ipv6_hdr(skb)->daddr,
3013 0, IPPROTO_TCP, 0);
3014 }
3015
3016 i = tx_ring->next_to_use;
3017
3018 buffer_info = &tx_ring->buffer_info[i];
3019 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3020 /* VLAN MACLEN IPLEN */
3021 if (tx_flags & IGB_TX_FLAGS_VLAN)
3022 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3023 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3024 *hdr_len += skb_network_offset(skb);
3025 info |= skb_network_header_len(skb);
3026 *hdr_len += skb_network_header_len(skb);
3027 context_desc->vlan_macip_lens = cpu_to_le32(info);
3028
3029 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3030 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3031
3032 if (skb->protocol == htons(ETH_P_IP))
3033 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3034 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3035
3036 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3037
3038 /* MSS L4LEN IDX */
3039 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3040 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3041
73cd78f1 3042 /* For 82575, context index must be unique per ring. */
7dfc16fa
AD		 3043 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3044 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 3045
3046 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3047 context_desc->seqnum_seed = 0;
3048
3049 buffer_info->time_stamp = jiffies;
0e014cb1 3050 buffer_info->next_to_watch = i;
9d5c8243
AK		 3051 buffer_info->dma = 0;
3052 i++;
3053 if (i == tx_ring->count)
3054 i = 0;
3055
3056 tx_ring->next_to_use = i;
3057
3058 return true;
3059}
3060
3061static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3062 struct igb_ring *tx_ring,
3063 struct sk_buff *skb, u32 tx_flags)
3064{
3065 struct e1000_adv_tx_context_desc *context_desc;
3066 unsigned int i;
3067 struct igb_buffer *buffer_info;
3068 u32 info = 0, tu_cmd = 0;
3069
3070 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3071 (tx_flags & IGB_TX_FLAGS_VLAN)) {
3072 i = tx_ring->next_to_use;
3073 buffer_info = &tx_ring->buffer_info[i];
3074 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3075
3076 if (tx_flags & IGB_TX_FLAGS_VLAN)
3077 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3078 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3079 if (skb->ip_summed == CHECKSUM_PARTIAL)
3080 info |= skb_network_header_len(skb);
3081
3082 context_desc->vlan_macip_lens = cpu_to_le32(info);
3083
3084 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3085
3086 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fa4a7ef3
AJ		 3087 __be16 protocol;
3088
3089 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3090 const struct vlan_ethhdr *vhdr =
3091 (const struct vlan_ethhdr*)skb->data;
3092
3093 protocol = vhdr->h_vlan_encapsulated_proto;
3094 } else {
3095 protocol = skb->protocol;
3096 }
3097
3098 switch (protocol) {
09640e63 3099 case cpu_to_be16(ETH_P_IP):
9d5c8243 3100 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 3101 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3102 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3103 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3104 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3 3105 break;
09640e63 3106 case cpu_to_be16(ETH_P_IPV6):
44b0cda3
MW		 3107 /* XXX what about other V6 headers?? */
3108 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3109 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
b9473560
JB		 3110 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3111 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
44b0cda3
MW		 3112 break;
3113 default:
3114 if (unlikely(net_ratelimit()))
3115 dev_warn(&adapter->pdev->dev,
3116 "partial checksum but proto=%x!\n",
3117 skb->protocol);
3118 break;
3119 }
9d5c8243
AK		 3120 }
3121
3122 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3123 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 3124 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3125 context_desc->mss_l4len_idx =
3126 cpu_to_le32(tx_ring->queue_index << 4);
265de409
AD		 3127 else
3128 context_desc->mss_l4len_idx = 0;
9d5c8243
AK		 3129
3130 buffer_info->time_stamp = jiffies;
0e014cb1 3131 buffer_info->next_to_watch = i;
9d5c8243
AK		 3132 buffer_info->dma = 0;
3133
3134 i++;
3135 if (i == tx_ring->count)
3136 i = 0;
3137 tx_ring->next_to_use = i;
3138
3139 return true;
3140 }
9d5c8243
AK		 3141 return false;
3142}
3143
3144#define IGB_MAX_TXD_PWR 16
3145#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
3146
3147static inline int igb_tx_map_adv(struct igb_adapter *adapter,
0e014cb1
AD		 3148 struct igb_ring *tx_ring, struct sk_buff *skb,
3149 unsigned int first)
9d5c8243
AK		 3150{
3151 struct igb_buffer *buffer_info;
3152 unsigned int len = skb_headlen(skb);
3153 unsigned int count = 0, i;
3154 unsigned int f;
65689fef 3155 dma_addr_t *map;
9d5c8243
AK		 3156
3157 i = tx_ring->next_to_use;
3158
65689fef
AD		 3159 if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3160 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3161 return 0;
3162 }
3163
3164 map = skb_shinfo(skb)->dma_maps;
3165
9d5c8243
AK		 3166 buffer_info = &tx_ring->buffer_info[i];
3167 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3168 buffer_info->length = len;
3169 /* set time_stamp *before* dma to help avoid a possible race */
3170 buffer_info->time_stamp = jiffies;
0e014cb1 3171 buffer_info->next_to_watch = i;
042a53a9 3172 buffer_info->dma = skb_shinfo(skb)->dma_head;
9d5c8243
AK		 3173
3174 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3175 struct skb_frag_struct *frag;
3176
65689fef
AD		 3177 i++;
3178 if (i == tx_ring->count)
3179 i = 0;
3180
9d5c8243
AK		 3181 frag = &skb_shinfo(skb)->frags[f];
3182 len = frag->size;
3183
3184 buffer_info = &tx_ring->buffer_info[i];
3185 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3186 buffer_info->length = len;
3187 buffer_info->time_stamp = jiffies;
0e014cb1 3188 buffer_info->next_to_watch = i;
65689fef 3189 buffer_info->dma = map[count];
9d5c8243 3190 count++;
9d5c8243
AK		 3191 }
3192
9d5c8243 3193 tx_ring->buffer_info[i].skb = skb;
0e014cb1 3194 tx_ring->buffer_info[first].next_to_watch = i;
9d5c8243 3195
042a53a9 3196 return count + 1;
9d5c8243
AK		 3197}
3198
3199static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3200 struct igb_ring *tx_ring,
3201 int tx_flags, int count, u32 paylen,
3202 u8 hdr_len)
3203{
3204 union e1000_adv_tx_desc *tx_desc = NULL;
3205 struct igb_buffer *buffer_info;
3206 u32 olinfo_status = 0, cmd_type_len;
3207 unsigned int i;
3208
3209 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3210 E1000_ADVTXD_DCMD_DEXT);
3211
3212 if (tx_flags & IGB_TX_FLAGS_VLAN)
3213 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3214
33af6bcc
PO		 3215 if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3216 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3217
9d5c8243
AK		 3218 if (tx_flags & IGB_TX_FLAGS_TSO) {
3219 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3220
3221 /* insert tcp checksum */
3222 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3223
3224 /* insert ip checksum */
3225 if (tx_flags & IGB_TX_FLAGS_IPV4)
3226 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3227
3228 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3229 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3230 }
3231
7dfc16fa
AD		 3232 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3233 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3234 IGB_TX_FLAGS_VLAN)))
661086df 3235 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 3236
3237 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3238
3239 i = tx_ring->next_to_use;
3240 while (count--) {
3241 buffer_info = &tx_ring->buffer_info[i];
3242 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3243 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3244 tx_desc->read.cmd_type_len =
3245 cpu_to_le32(cmd_type_len | buffer_info->length);
3246 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3247 i++;
3248 if (i == tx_ring->count)
3249 i = 0;
3250 }
3251
3252 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3253 /* Force memory writes to complete before letting h/w
3254 * know there are new descriptors to fetch. (Only
3255 * applicable for weak-ordered memory model archs,
3256 * such as IA-64). */
3257 wmb();
3258
3259 tx_ring->next_to_use = i;
3260 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3261 /* we need this if more than one processor can write to our tail
3262 * at a time, it syncronizes IO on IA64/Altix systems */
3263 mmiowb();
3264}
3265
3266static int __igb_maybe_stop_tx(struct net_device *netdev,
3267 struct igb_ring *tx_ring, int size)
3268{
3269 struct igb_adapter *adapter = netdev_priv(netdev);
3270
661086df 3271 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 3272
9d5c8243
AK		 3273 /* Herbert's original patch had:
3274 * smp_mb__after_netif_stop_queue();
3275 * but since that doesn't exist yet, just open code it. */
3276 smp_mb();
3277
3278 /* We need to check again in a case another CPU has just
3279 * made room available. */
c493ea45 3280 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 3281 return -EBUSY;
3282
3283 /* A reprieve! */
661086df 3284 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3285 ++adapter->restart_queue;
3286 return 0;
3287}
3288
3289static int igb_maybe_stop_tx(struct net_device *netdev,
3290 struct igb_ring *tx_ring, int size)
3291{
c493ea45 3292 if (igb_desc_unused(tx_ring) >= size)
9d5c8243
AK		 3293 return 0;
3294 return __igb_maybe_stop_tx(netdev, tx_ring, size);
3295}
3296
9d5c8243
AK		 3297static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3298 struct net_device *netdev,
3299 struct igb_ring *tx_ring)
3300{
3301 struct igb_adapter *adapter = netdev_priv(netdev);
0e014cb1 3302 unsigned int first;
9d5c8243 3303 unsigned int tx_flags = 0;
9d5c8243 3304 u8 hdr_len = 0;
65689fef 3305 int count = 0;
9d5c8243 3306 int tso = 0;
33af6bcc 3307 union skb_shared_tx *shtx;
9d5c8243 3308
9d5c8243
AK		 3309 if (test_bit(__IGB_DOWN, &adapter->state)) {
3310 dev_kfree_skb_any(skb);
3311 return NETDEV_TX_OK;
3312 }
3313
3314 if (skb->len <= 0) {
3315 dev_kfree_skb_any(skb);
3316 return NETDEV_TX_OK;
3317 }
3318
9d5c8243
AK		 3319 /* need: 1 descriptor per page,
3320 * + 2 desc gap to keep tail from touching head,
3321 * + 1 desc for skb->data,
3322 * + 1 desc for context descriptor,
3323 * otherwise try next time */
3324 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3325 /* this is a hard error */
9d5c8243
AK		 3326 return NETDEV_TX_BUSY;
3327 }
33af6bcc
PO		 3328
3329 /*
3330 * TODO: check that there currently is no other packet with
3331 * time stamping in the queue
3332 *
3333 * When doing time stamping, keep the connection to the socket
3334 * a while longer: it is still needed by skb_hwtstamp_tx(),
3335 * called either in igb_tx_hwtstamp() or by our caller when
3336 * doing software time stamping.
3337 */
3338 shtx = skb_tx(skb);
3339 if (unlikely(shtx->hardware)) {
3340 shtx->in_progress = 1;
3341 tx_flags |= IGB_TX_FLAGS_TSTAMP;
33af6bcc 3342 }
9d5c8243
AK		 3343
3344 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3345 tx_flags |= IGB_TX_FLAGS_VLAN;
3346 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3347 }
3348
661086df
PWJ		 3349 if (skb->protocol == htons(ETH_P_IP))
3350 tx_flags |= IGB_TX_FLAGS_IPV4;
3351
0e014cb1 3352 first = tx_ring->next_to_use;
9d5c8243
AK		 3353 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3354 &hdr_len) : 0;
3355
3356 if (tso < 0) {
3357 dev_kfree_skb_any(skb);
9d5c8243
AK		 3358 return NETDEV_TX_OK;
3359 }
3360
3361 if (tso)
3362 tx_flags |= IGB_TX_FLAGS_TSO;
bc1cbd34
AD		 3363 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3364 (skb->ip_summed == CHECKSUM_PARTIAL))
3365 tx_flags |= IGB_TX_FLAGS_CSUM;
9d5c8243 3366
65689fef
AD		 3367 /*
3368 * count reflects descriptors mapped, if 0 then mapping error
3369 * has occured and we need to rewind the descriptor queue
3370 */
3371 count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3372
3373 if (count) {
3374 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3375 skb->len, hdr_len);
65689fef
AD		 3376 /* Make sure there is space in the ring for the next send. */
3377 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3378 } else {
3379 dev_kfree_skb_any(skb);
3380 tx_ring->buffer_info[first].time_stamp = 0;
3381 tx_ring->next_to_use = first;
3382 }
9d5c8243 3383
9d5c8243
AK		 3384 return NETDEV_TX_OK;
3385}
3386
3387static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3388{
3389 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3390 struct igb_ring *tx_ring;
3391
661086df 3392 int r_idx = 0;
1bfaf07b 3393 r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
661086df 3394 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3395
3396 /* This goes back to the question of how to logically map a tx queue
3397 * to a flow. Right now, performance is impacted slightly negatively
3398 * if using multiple tx queues. If the stack breaks away from a
3399 * single qdisc implementation, we can look at this again. */
3400 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3401}
3402
3403/**
3404 * igb_tx_timeout - Respond to a Tx Hang
3405 * @netdev: network interface device structure
3406 **/
3407static void igb_tx_timeout(struct net_device *netdev)
3408{
3409 struct igb_adapter *adapter = netdev_priv(netdev);
3410 struct e1000_hw *hw = &adapter->hw;
3411
3412 /* Do the reset outside of interrupt context */
3413 adapter->tx_timeout_count++;
3414 schedule_work(&adapter->reset_task);
265de409
AD		 3415 wr32(E1000_EICS,
3416 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 3417}
3418
3419static void igb_reset_task(struct work_struct *work)
3420{
3421 struct igb_adapter *adapter;
3422 adapter = container_of(work, struct igb_adapter, reset_task);
3423
3424 igb_reinit_locked(adapter);
3425}
3426
3427/**
3428 * igb_get_stats - Get System Network Statistics
3429 * @netdev: network interface device structure
3430 *
3431 * Returns the address of the device statistics structure.
3432 * The statistics are actually updated from the timer callback.
3433 **/
73cd78f1 3434static struct net_device_stats *igb_get_stats(struct net_device *netdev)
9d5c8243
AK		 3435{
3436 struct igb_adapter *adapter = netdev_priv(netdev);
3437
3438 /* only return the current stats */
3439 return &adapter->net_stats;
3440}
3441
3442/**
3443 * igb_change_mtu - Change the Maximum Transfer Unit
3444 * @netdev: network interface device structure
3445 * @new_mtu: new value for maximum frame size
3446 *
3447 * Returns 0 on success, negative on failure
3448 **/
3449static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3450{
3451 struct igb_adapter *adapter = netdev_priv(netdev);
3452 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3453
3454 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3455 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3456 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3457 return -EINVAL;
3458 }
3459
9d5c8243
AK		 3460 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3461 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3462 return -EINVAL;
3463 }
3464
3465 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3466 msleep(1);
73cd78f1 3467
9d5c8243
AK		 3468 /* igb_down has a dependency on max_frame_size */
3469 adapter->max_frame_size = max_frame;
3470 if (netif_running(netdev))
3471 igb_down(adapter);
3472
3473 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3474 * means we reserve 2 more, this pushes us to allocate from the next
3475 * larger slab size.
3476 * i.e. RXBUFFER_2048 --> size-4096 slab
3477 */
3478
3479 if (max_frame <= IGB_RXBUFFER_256)
3480 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3481 else if (max_frame <= IGB_RXBUFFER_512)
3482 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3483 else if (max_frame <= IGB_RXBUFFER_1024)
3484 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3485 else if (max_frame <= IGB_RXBUFFER_2048)
3486 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3487 else
bf36c1a0
AD		 3488#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3489 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3490#else
3491 adapter->rx_buffer_len = PAGE_SIZE / 2;
3492#endif
e1739522
AD		 3493
3494 /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3495 if (adapter->vfs_allocated_count &&
3496 (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3497 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3498
9d5c8243
AK		 3499 /* adjust allocation if LPE protects us, and we aren't using SBP */
3500 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3501 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3502 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3503
3504 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3505 netdev->mtu, new_mtu);
3506 netdev->mtu = new_mtu;
3507
3508 if (netif_running(netdev))
3509 igb_up(adapter);
3510 else
3511 igb_reset(adapter);
3512
3513 clear_bit(__IGB_RESETTING, &adapter->state);
3514
3515 return 0;
3516}
3517
3518/**
3519 * igb_update_stats - Update the board statistics counters
3520 * @adapter: board private structure
3521 **/
3522
3523void igb_update_stats(struct igb_adapter *adapter)
3524{
3525 struct e1000_hw *hw = &adapter->hw;
3526 struct pci_dev *pdev = adapter->pdev;
3527 u16 phy_tmp;
3528
3529#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3530
3531 /*
3532 * Prevent stats update while adapter is being reset, or if the pci
3533 * connection is down.
3534 */
3535 if (adapter->link_speed == 0)
3536 return;
3537 if (pci_channel_offline(pdev))
3538 return;
3539
3540 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3541 adapter->stats.gprc += rd32(E1000_GPRC);
3542 adapter->stats.gorc += rd32(E1000_GORCL);
3543 rd32(E1000_GORCH); /* clear GORCL */
3544 adapter->stats.bprc += rd32(E1000_BPRC);
3545 adapter->stats.mprc += rd32(E1000_MPRC);
3546 adapter->stats.roc += rd32(E1000_ROC);
3547
3548 adapter->stats.prc64 += rd32(E1000_PRC64);
3549 adapter->stats.prc127 += rd32(E1000_PRC127);
3550 adapter->stats.prc255 += rd32(E1000_PRC255);
3551 adapter->stats.prc511 += rd32(E1000_PRC511);
3552 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3553 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3554 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3555 adapter->stats.sec += rd32(E1000_SEC);
3556
3557 adapter->stats.mpc += rd32(E1000_MPC);
3558 adapter->stats.scc += rd32(E1000_SCC);
3559 adapter->stats.ecol += rd32(E1000_ECOL);
3560 adapter->stats.mcc += rd32(E1000_MCC);
3561 adapter->stats.latecol += rd32(E1000_LATECOL);
3562 adapter->stats.dc += rd32(E1000_DC);
3563 adapter->stats.rlec += rd32(E1000_RLEC);
3564 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3565 adapter->stats.xontxc += rd32(E1000_XONTXC);
3566 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3567 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3568 adapter->stats.fcruc += rd32(E1000_FCRUC);
3569 adapter->stats.gptc += rd32(E1000_GPTC);
3570 adapter->stats.gotc += rd32(E1000_GOTCL);
3571 rd32(E1000_GOTCH); /* clear GOTCL */
3572 adapter->stats.rnbc += rd32(E1000_RNBC);
3573 adapter->stats.ruc += rd32(E1000_RUC);
3574 adapter->stats.rfc += rd32(E1000_RFC);
3575 adapter->stats.rjc += rd32(E1000_RJC);
3576 adapter->stats.tor += rd32(E1000_TORH);
3577 adapter->stats.tot += rd32(E1000_TOTH);
3578 adapter->stats.tpr += rd32(E1000_TPR);
3579
3580 adapter->stats.ptc64 += rd32(E1000_PTC64);
3581 adapter->stats.ptc127 += rd32(E1000_PTC127);
3582 adapter->stats.ptc255 += rd32(E1000_PTC255);
3583 adapter->stats.ptc511 += rd32(E1000_PTC511);
3584 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3585 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3586
3587 adapter->stats.mptc += rd32(E1000_MPTC);
3588 adapter->stats.bptc += rd32(E1000_BPTC);
3589
3590 /* used for adaptive IFS */
3591
3592 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3593 adapter->stats.tpt += hw->mac.tx_packet_delta;
3594 hw->mac.collision_delta = rd32(E1000_COLC);
3595 adapter->stats.colc += hw->mac.collision_delta;
3596
3597 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3598 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3599 adapter->stats.tncrs += rd32(E1000_TNCRS);
3600 adapter->stats.tsctc += rd32(E1000_TSCTC);
3601 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3602
3603 adapter->stats.iac += rd32(E1000_IAC);
3604 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3605 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3606 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3607 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3608 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3609 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3610 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3611 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3612
3613 /* Fill out the OS statistics structure */
3614 adapter->net_stats.multicast = adapter->stats.mprc;
3615 adapter->net_stats.collisions = adapter->stats.colc;
3616
3617 /* Rx Errors */
3618
8c0ab70a
JDB		 3619 if (hw->mac.type != e1000_82575) {
3620 u32 rqdpc_tmp;
3ea73afa 3621 u64 rqdpc_total = 0;
8c0ab70a
JDB		 3622 int i;
3623 /* Read out drops stats per RX queue. Notice RQDPC (Receive
3624 * Queue Drop Packet Count) stats only gets incremented, if
3625 * the DROP_EN but it set (in the SRRCTL register for that
3626 * queue). If DROP_EN bit is NOT set, then the some what
3627 * equivalent count is stored in RNBC (not per queue basis).
3628 * Also note the drop count is due to lack of available
3629 * descriptors.
3630 */
3631 for (i = 0; i < adapter->num_rx_queues; i++) {
3632 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3633 adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3ea73afa 3634 rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
8c0ab70a 3635 }
3ea73afa 3636 adapter->net_stats.rx_fifo_errors = rqdpc_total;
8c0ab70a
JDB		 3637 }
3638
3ea73afa
JDB		 3639 /* Note RNBC (Receive No Buffers Count) is an not an exact
3640 * drop count as the hardware FIFO might save the day. Thats
3641 * one of the reason for saving it in rx_fifo_errors, as its
3642 * potentially not a true drop.
3643 */
3644 adapter->net_stats.rx_fifo_errors += adapter->stats.rnbc;
3645
9d5c8243 3646 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 3647 * our own version based on RUC and ROC */
9d5c8243
AK		 3648 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3649 adapter->stats.crcerrs + adapter->stats.algnerrc +
3650 adapter->stats.ruc + adapter->stats.roc +
3651 adapter->stats.cexterr;
3652 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3653 adapter->stats.roc;
3654 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3655 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3656 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3657
3658 /* Tx Errors */
3659 adapter->net_stats.tx_errors = adapter->stats.ecol +
3660 adapter->stats.latecol;
3661 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3662 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3663 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3664
3665 /* Tx Dropped needs to be maintained elsewhere */
3666
3667 /* Phy Stats */
3668 if (hw->phy.media_type == e1000_media_type_copper) {
3669 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 3670 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 3671 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3672 adapter->phy_stats.idle_errors += phy_tmp;
3673 }
3674 }
3675
3676 /* Management Stats */
3677 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3678 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3679 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3680}
3681
9d5c8243
AK		 3682static irqreturn_t igb_msix_other(int irq, void *data)
3683{
3684 struct net_device *netdev = data;
3685 struct igb_adapter *adapter = netdev_priv(netdev);
3686 struct e1000_hw *hw = &adapter->hw;
844290e5 3687 u32 icr = rd32(E1000_ICR);
9d5c8243 3688
844290e5 3689 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083
AD		 3690
3691 if(icr & E1000_ICR_DOUTSYNC) {
3692 /* HW is reporting DMA is out of sync */
3693 adapter->stats.doosync++;
3694 }
eebbbdba 3695
4ae196df
AD		 3696 /* Check for a mailbox event */
3697 if (icr & E1000_ICR_VMMB)
3698 igb_msg_task(adapter);
3699
3700 if (icr & E1000_ICR_LSC) {
3701 hw->mac.get_link_status = 1;
3702 /* guard against interrupt when we're going down */
3703 if (!test_bit(__IGB_DOWN, &adapter->state))
3704 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3705 }
3706
3707 wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
844290e5 3708 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3709
3710 return IRQ_HANDLED;
3711}
3712
3713static irqreturn_t igb_msix_tx(int irq, void *data)
3714{
3715 struct igb_ring *tx_ring = data;
3716 struct igb_adapter *adapter = tx_ring->adapter;
3717 struct e1000_hw *hw = &adapter->hw;
3718
421e02f0 3719#ifdef CONFIG_IGB_DCA
7dfc16fa 3720 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3721 igb_update_tx_dca(tx_ring);
3722#endif
73cd78f1 3723
9d5c8243
AK		 3724 tx_ring->total_bytes = 0;
3725 tx_ring->total_packets = 0;
661086df
PWJ		 3726
3727 /* auto mask will automatically reenable the interrupt when we write
3728 * EICS */
3b644cf6 3729 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3730 /* Ring was not completely cleaned, so fire another interrupt */
3731 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3732 else
9d5c8243 3733 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3734
9d5c8243
AK		 3735 return IRQ_HANDLED;
3736}
3737
6eb5a7f1
AD		 3738static void igb_write_itr(struct igb_ring *ring)
3739{
3740 struct e1000_hw *hw = &ring->adapter->hw;
3741 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3742 switch (hw->mac.type) {
3743 case e1000_82576:
73cd78f1 3744 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3745 0x80000000);
3746 break;
3747 default:
73cd78f1 3748 wr32(ring->itr_register, ring->itr_val |
6eb5a7f1
AD		 3749 (ring->itr_val << 16));
3750 break;
3751 }
3752 ring->set_itr = 0;
3753 }
3754}
3755
9d5c8243
AK		 3756static irqreturn_t igb_msix_rx(int irq, void *data)
3757{
3758 struct igb_ring *rx_ring = data;
9d5c8243 3759
844290e5
PW		 3760 /* Write the ITR value calculated at the end of the
3761 * previous interrupt.
3762 */
9d5c8243 3763
6eb5a7f1 3764 igb_write_itr(rx_ring);
9d5c8243 3765
288379f0
BH		 3766 if (napi_schedule_prep(&rx_ring->napi))
3767 __napi_schedule(&rx_ring->napi);
844290e5 3768
421e02f0 3769#ifdef CONFIG_IGB_DCA
8d253320 3770 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3771 igb_update_rx_dca(rx_ring);
3772#endif
3773 return IRQ_HANDLED;
3774}
3775
421e02f0 3776#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3777static void igb_update_rx_dca(struct igb_ring *rx_ring)
3778{
3779 u32 dca_rxctrl;
3780 struct igb_adapter *adapter = rx_ring->adapter;
3781 struct e1000_hw *hw = &adapter->hw;
3782 int cpu = get_cpu();
26bc19ec 3783 int q = rx_ring->reg_idx;
fe4506b6
JC		 3784
3785 if (rx_ring->cpu != cpu) {
3786 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3787 if (hw->mac.type == e1000_82576) {
3788 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
92be7917 3789 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3790 E1000_DCA_RXCTRL_CPUID_SHIFT;
3791 } else {
3792 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 3793 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3794 }
fe4506b6
JC		 3795 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3796 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3797 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3798 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3799 rx_ring->cpu = cpu;
3800 }
3801 put_cpu();
3802}
3803
3804static void igb_update_tx_dca(struct igb_ring *tx_ring)
3805{
3806 u32 dca_txctrl;
3807 struct igb_adapter *adapter = tx_ring->adapter;
3808 struct e1000_hw *hw = &adapter->hw;
3809 int cpu = get_cpu();
26bc19ec 3810 int q = tx_ring->reg_idx;
fe4506b6
JC		 3811
3812 if (tx_ring->cpu != cpu) {
3813 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3814 if (hw->mac.type == e1000_82576) {
3815 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
92be7917 3816 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
2d064c06
AD		 3817 E1000_DCA_TXCTRL_CPUID_SHIFT;
3818 } else {
3819 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
92be7917 3820 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 3821 }
fe4506b6
JC		 3822 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3823 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3824 tx_ring->cpu = cpu;
3825 }
3826 put_cpu();
3827}
3828
3829static void igb_setup_dca(struct igb_adapter *adapter)
3830{
7e0e99ef 3831 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 3832 int i;
3833
7dfc16fa 3834 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3835 return;
3836
7e0e99ef
AD		 3837 /* Always use CB2 mode, difference is masked in the CB driver. */
3838 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3839
fe4506b6
JC		 3840 for (i = 0; i < adapter->num_tx_queues; i++) {
3841 adapter->tx_ring[i].cpu = -1;
3842 igb_update_tx_dca(&adapter->tx_ring[i]);
3843 }
3844 for (i = 0; i < adapter->num_rx_queues; i++) {
3845 adapter->rx_ring[i].cpu = -1;
3846 igb_update_rx_dca(&adapter->rx_ring[i]);
3847 }
3848}
3849
3850static int __igb_notify_dca(struct device *dev, void *data)
3851{
3852 struct net_device *netdev = dev_get_drvdata(dev);
3853 struct igb_adapter *adapter = netdev_priv(netdev);
3854 struct e1000_hw *hw = &adapter->hw;
3855 unsigned long event = *(unsigned long *)data;
3856
3857 switch (event) {
3858 case DCA_PROVIDER_ADD:
3859 /* if already enabled, don't do it again */
7dfc16fa 3860 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3861 break;
fe4506b6
JC		 3862 /* Always use CB2 mode, difference is masked
3863 * in the CB driver. */
cbd347ad 3864 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
fe4506b6 3865 if (dca_add_requester(dev) == 0) {
bbd98fe4 3866 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3867 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3868 igb_setup_dca(adapter);
3869 break;
3870 }
3871 /* Fall Through since DCA is disabled. */
3872 case DCA_PROVIDER_REMOVE:
7dfc16fa 3873 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3874 /* without this a class_device is left
3875 * hanging around in the sysfs model */
3876 dca_remove_requester(dev);
3877 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3878 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 3879 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 3880 }
3881 break;
3882 }
bbd98fe4 3883
fe4506b6 3884 return 0;
9d5c8243
AK		 3885}
3886
fe4506b6
JC		 3887static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3888 void *p)
3889{
3890 int ret_val;
3891
3892 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3893 __igb_notify_dca);
3894
3895 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3896}
421e02f0 3897#endif /* CONFIG_IGB_DCA */
9d5c8243 3898
4ae196df
AD		 3899static void igb_ping_all_vfs(struct igb_adapter *adapter)
3900{
3901 struct e1000_hw *hw = &adapter->hw;
3902 u32 ping;
3903 int i;
3904
3905 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3906 ping = E1000_PF_CONTROL_MSG;
3907 if (adapter->vf_data[i].clear_to_send)
3908 ping |= E1000_VT_MSGTYPE_CTS;
3909 igb_write_mbx(hw, &ping, 1, i);
3910 }
3911}
3912
3913static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3914 u32 *msgbuf, u32 vf)
3915{
3916 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3917 u16 *hash_list = (u16 *)&msgbuf[1];
3918 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3919 int i;
3920
3921 /* only up to 30 hash values supported */
3922 if (n > 30)
3923 n = 30;
3924
3925 /* salt away the number of multi cast addresses assigned
3926 * to this VF for later use to restore when the PF multi cast
3927 * list changes
3928 */
3929 vf_data->num_vf_mc_hashes = n;
3930
3931 /* VFs are limited to using the MTA hash table for their multicast
3932 * addresses */
3933 for (i = 0; i < n; i++)
3934 vf_data->vf_mc_hashes[i] = hash_list[i];;
3935
3936 /* Flush and reset the mta with the new values */
3937 igb_set_multi(adapter->netdev);
3938
3939 return 0;
3940}
3941
3942static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3943{
3944 struct e1000_hw *hw = &adapter->hw;
3945 struct vf_data_storage *vf_data;
3946 int i, j;
3947
3948 for (i = 0; i < adapter->vfs_allocated_count; i++) {
3949 vf_data = &adapter->vf_data[i];
75f4f382 3950 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
4ae196df
AD		 3951 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3952 }
3953}
3954
3955static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3956{
3957 struct e1000_hw *hw = &adapter->hw;
3958 u32 pool_mask, reg, vid;
3959 int i;
3960
3961 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3962
3963 /* Find the vlan filter for this id */
3964 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3965 reg = rd32(E1000_VLVF(i));
3966
3967 /* remove the vf from the pool */
3968 reg &= ~pool_mask;
3969
3970 /* if pool is empty then remove entry from vfta */
3971 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3972 (reg & E1000_VLVF_VLANID_ENABLE)) {
3973 reg = 0;
3974 vid = reg & E1000_VLVF_VLANID_MASK;
3975 igb_vfta_set(hw, vid, false);
3976 }
3977
3978 wr32(E1000_VLVF(i), reg);
3979 }
3980}
3981
3982static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3983{
3984 struct e1000_hw *hw = &adapter->hw;
3985 u32 reg, i;
3986
3987 /* It is an error to call this function when VFs are not enabled */
3988 if (!adapter->vfs_allocated_count)
3989 return -1;
3990
3991 /* Find the vlan filter for this id */
3992 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3993 reg = rd32(E1000_VLVF(i));
3994 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3995 vid == (reg & E1000_VLVF_VLANID_MASK))
3996 break;
3997 }
3998
3999 if (add) {
4000 if (i == E1000_VLVF_ARRAY_SIZE) {
4001 /* Did not find a matching VLAN ID entry that was
4002 * enabled. Search for a free filter entry, i.e.
4003 * one without the enable bit set
4004 */
4005 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4006 reg = rd32(E1000_VLVF(i));
4007 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4008 break;
4009 }
4010 }
4011 if (i < E1000_VLVF_ARRAY_SIZE) {
4012 /* Found an enabled/available entry */
4013 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4014
4015 /* if !enabled we need to set this up in vfta */
4016 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
cad6d05f
AD		 4017 /* add VID to filter table, if bit already set
4018 * PF must have added it outside of table */
4019 if (igb_vfta_set(hw, vid, true))
4020 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4021 adapter->vfs_allocated_count);
4ae196df
AD		 4022 reg |= E1000_VLVF_VLANID_ENABLE;
4023 }
cad6d05f
AD		 4024 reg &= ~E1000_VLVF_VLANID_MASK;
4025 reg |= vid;
4ae196df
AD		 4026
4027 wr32(E1000_VLVF(i), reg);
4028 return 0;
4029 }
4030 } else {
4031 if (i < E1000_VLVF_ARRAY_SIZE) {
4032 /* remove vf from the pool */
4033 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4034 /* if pool is empty then remove entry from vfta */
4035 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4036 reg = 0;
4037 igb_vfta_set(hw, vid, false);
4038 }
4039 wr32(E1000_VLVF(i), reg);
4040 return 0;
4041 }
4042 }
4043 return -1;
4044}
4045
4046static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4047{
4048 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4049 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4050
4051 return igb_vlvf_set(adapter, vid, add, vf);
4052}
4053
4054static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4055{
4056 struct e1000_hw *hw = &adapter->hw;
4057
4058 /* disable mailbox functionality for vf */
4059 adapter->vf_data[vf].clear_to_send = false;
4060
4061 /* reset offloads to defaults */
4062 igb_set_vmolr(hw, vf);
4063
4064 /* reset vlans for device */
4065 igb_clear_vf_vfta(adapter, vf);
4066
4067 /* reset multicast table array for vf */
4068 adapter->vf_data[vf].num_vf_mc_hashes = 0;
4069
4070 /* Flush and reset the mta with the new values */
4071 igb_set_multi(adapter->netdev);
4072}
4073
4074static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4075{
4076 struct e1000_hw *hw = &adapter->hw;
4077 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4078 u32 reg, msgbuf[3];
4079 u8 *addr = (u8 *)(&msgbuf[1]);
4080
4081 /* process all the same items cleared in a function level reset */
4082 igb_vf_reset_event(adapter, vf);
4083
4084 /* set vf mac address */
4085 igb_rar_set(hw, vf_mac, vf + 1);
4086 igb_set_rah_pool(hw, vf, vf + 1);
4087
4088 /* enable transmit and receive for vf */
4089 reg = rd32(E1000_VFTE);
4090 wr32(E1000_VFTE, reg | (1 << vf));
4091 reg = rd32(E1000_VFRE);
4092 wr32(E1000_VFRE, reg | (1 << vf));
4093
4094 /* enable mailbox functionality for vf */
4095 adapter->vf_data[vf].clear_to_send = true;
4096
4097 /* reply to reset with ack and vf mac address */
4098 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4099 memcpy(addr, vf_mac, 6);
4100 igb_write_mbx(hw, msgbuf, 3, vf);
4101}
4102
4103static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4104{
4105 unsigned char *addr = (char *)&msg[1];
4106 int err = -1;
4107
4108 if (is_valid_ether_addr(addr))
4109 err = igb_set_vf_mac(adapter, vf, addr);
4110
4111 return err;
4112
4113}
4114
4115static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4116{
4117 struct e1000_hw *hw = &adapter->hw;
4118 u32 msg = E1000_VT_MSGTYPE_NACK;
4119
4120 /* if device isn't clear to send it shouldn't be reading either */
4121 if (!adapter->vf_data[vf].clear_to_send)
4122 igb_write_mbx(hw, &msg, 1, vf);
4123}
4124
4125
4126static void igb_msg_task(struct igb_adapter *adapter)
4127{
4128 struct e1000_hw *hw = &adapter->hw;
4129 u32 vf;
4130
4131 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4132 /* process any reset requests */
4133 if (!igb_check_for_rst(hw, vf)) {
4134 adapter->vf_data[vf].clear_to_send = false;
4135 igb_vf_reset_event(adapter, vf);
4136 }
4137
4138 /* process any messages pending */
4139 if (!igb_check_for_msg(hw, vf))
4140 igb_rcv_msg_from_vf(adapter, vf);
4141
4142 /* process any acks */
4143 if (!igb_check_for_ack(hw, vf))
4144 igb_rcv_ack_from_vf(adapter, vf);
4145
4146 }
4147}
4148
4149static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4150{
4151 u32 mbx_size = E1000_VFMAILBOX_SIZE;
4152 u32 msgbuf[mbx_size];
4153 struct e1000_hw *hw = &adapter->hw;
4154 s32 retval;
4155
4156 retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4157
4158 if (retval)
4159 dev_err(&adapter->pdev->dev,
4160 "Error receiving message from VF\n");
4161
4162 /* this is a message we already processed, do nothing */
4163 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4164 return retval;
4165
4166 /*
4167 * until the vf completes a reset it should not be
4168 * allowed to start any configuration.
4169 */
4170
4171 if (msgbuf[0] == E1000_VF_RESET) {
4172 igb_vf_reset_msg(adapter, vf);
4173
4174 return retval;
4175 }
4176
4177 if (!adapter->vf_data[vf].clear_to_send) {
4178 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4179 igb_write_mbx(hw, msgbuf, 1, vf);
4180 return retval;
4181 }
4182
4183 switch ((msgbuf[0] & 0xFFFF)) {
4184 case E1000_VF_SET_MAC_ADDR:
4185 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4186 break;
4187 case E1000_VF_SET_MULTICAST:
4188 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4189 break;
4190 case E1000_VF_SET_LPE:
4191 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4192 break;
4193 case E1000_VF_SET_VLAN:
4194 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4195 break;
4196 default:
4197 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4198 retval = -1;
4199 break;
4200 }
4201
4202 /* notify the VF of the results of what it sent us */
4203 if (retval)
4204 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4205 else
4206 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4207
4208 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4209
4210 igb_write_mbx(hw, msgbuf, 1, vf);
4211
4212 return retval;
4213}
4214
9d5c8243
AK		 4215/**
4216 * igb_intr_msi - Interrupt Handler
4217 * @irq: interrupt number
4218 * @data: pointer to a network interface device structure
4219 **/
4220static irqreturn_t igb_intr_msi(int irq, void *data)
4221{
4222 struct net_device *netdev = data;
4223 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4224 struct e1000_hw *hw = &adapter->hw;
4225 /* read ICR disables interrupts using IAM */
4226 u32 icr = rd32(E1000_ICR);
4227
6eb5a7f1 4228 igb_write_itr(adapter->rx_ring);
9d5c8243 4229
dda0e083
AD		 4230 if(icr & E1000_ICR_DOUTSYNC) {
4231 /* HW is reporting DMA is out of sync */
4232 adapter->stats.doosync++;
4233 }
4234
9d5c8243
AK		 4235 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4236 hw->mac.get_link_status = 1;
4237 if (!test_bit(__IGB_DOWN, &adapter->state))
4238 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4239 }
4240
288379f0 4241 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4242
4243 return IRQ_HANDLED;
4244}
4245
4246/**
4a3c6433 4247 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 4248 * @irq: interrupt number
4249 * @data: pointer to a network interface device structure
4250 **/
4251static irqreturn_t igb_intr(int irq, void *data)
4252{
4253 struct net_device *netdev = data;
4254 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 4255 struct e1000_hw *hw = &adapter->hw;
4256 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
4257 * need for the IMC write */
4258 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 4259 if (!icr)
4260 return IRQ_NONE; /* Not our interrupt */
4261
6eb5a7f1 4262 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 4263
4264 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4265 * not set, then the adapter didn't send an interrupt */
4266 if (!(icr & E1000_ICR_INT_ASSERTED))
4267 return IRQ_NONE;
4268
dda0e083
AD		 4269 if(icr & E1000_ICR_DOUTSYNC) {
4270 /* HW is reporting DMA is out of sync */
4271 adapter->stats.doosync++;
4272 }
4273
9d5c8243
AK		 4274 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4275 hw->mac.get_link_status = 1;
4276 /* guard against interrupt when we're going down */
4277 if (!test_bit(__IGB_DOWN, &adapter->state))
4278 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4279 }
4280
288379f0 4281 napi_schedule(&adapter->rx_ring[0].napi);
9d5c8243
AK		 4282
4283 return IRQ_HANDLED;
4284}
4285
46544258 4286static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
9d5c8243 4287{
661086df 4288 struct igb_adapter *adapter = rx_ring->adapter;
46544258 4289 struct e1000_hw *hw = &adapter->hw;
9d5c8243 4290
46544258
AD		 4291 if (adapter->itr_setting & 3) {
4292 if (adapter->num_rx_queues == 1)
6eb5a7f1 4293 igb_set_itr(adapter);
46544258
AD		 4294 else
4295 igb_update_ring_itr(rx_ring);
9d5c8243
AK		 4296 }
4297
46544258
AD		 4298 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4299 if (adapter->msix_entries)
4300 wr32(E1000_EIMS, rx_ring->eims_value);
4301 else
4302 igb_irq_enable(adapter);
4303 }
9d5c8243
AK		 4304}
4305
46544258
AD		 4306/**
4307 * igb_poll - NAPI Rx polling callback
4308 * @napi: napi polling structure
4309 * @budget: count of how many packets we should handle
4310 **/
4311static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243
AK		 4312{
4313 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
9d5c8243
AK		 4314 int work_done = 0;
4315
421e02f0 4316#ifdef CONFIG_IGB_DCA
bd38e5d1 4317 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 4318 igb_update_rx_dca(rx_ring);
4319#endif
3b644cf6 4320 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243 4321
46544258
AD		 4322 if (rx_ring->buddy) {
4323#ifdef CONFIG_IGB_DCA
bd38e5d1 4324 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
46544258
AD		 4325 igb_update_tx_dca(rx_ring->buddy);
4326#endif
4327 if (!igb_clean_tx_irq(rx_ring->buddy))
4328 work_done = budget;
4329 }
4330
9d5c8243 4331 /* If not enough Rx work done, exit the polling mode */
5e6d5b17 4332 if (work_done < budget) {
288379f0 4333 napi_complete(napi);
46544258 4334 igb_rx_irq_enable(rx_ring);
9d5c8243
AK		 4335 }
4336
46544258 4337 return work_done;
9d5c8243 4338}
6d8126f9 4339
33af6bcc
PO		 4340/**
4341 * igb_hwtstamp - utility function which checks for TX time stamp
4342 * @adapter: board private structure
4343 * @skb: packet that was just sent
4344 *
4345 * If we were asked to do hardware stamping and such a time stamp is
4346 * available, then it must have been for this skb here because we only
4347 * allow only one such packet into the queue.
4348 */
4349static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4350{
4351 union skb_shared_tx *shtx = skb_tx(skb);
4352 struct e1000_hw *hw = &adapter->hw;
4353
4354 if (unlikely(shtx->hardware)) {
4355 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4356 if (valid) {
4357 u64 regval = rd32(E1000_TXSTMPL);
4358 u64 ns;
4359 struct skb_shared_hwtstamps shhwtstamps;
4360
4361 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4362 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4363 ns = timecounter_cyc2time(&adapter->clock,
4364 regval);
4365 timecompare_update(&adapter->compare, ns);
4366 shhwtstamps.hwtstamp = ns_to_ktime(ns);
4367 shhwtstamps.syststamp =
4368 timecompare_transform(&adapter->compare, ns);
4369 skb_tstamp_tx(skb, &shhwtstamps);
4370 }
33af6bcc
PO		 4371 }
4372}
4373
9d5c8243
AK		 4374/**
4375 * igb_clean_tx_irq - Reclaim resources after transmit completes
4376 * @adapter: board private structure
4377 * returns true if ring is completely cleaned
4378 **/
3b644cf6 4379static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 4380{
3b644cf6 4381 struct igb_adapter *adapter = tx_ring->adapter;
3b644cf6 4382 struct net_device *netdev = adapter->netdev;
0e014cb1 4383 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4384 struct igb_buffer *buffer_info;
4385 struct sk_buff *skb;
0e014cb1 4386 union e1000_adv_tx_desc *tx_desc, *eop_desc;
9d5c8243 4387 unsigned int total_bytes = 0, total_packets = 0;
0e014cb1
AD		 4388 unsigned int i, eop, count = 0;
4389 bool cleaned = false;
9d5c8243 4390
9d5c8243 4391 i = tx_ring->next_to_clean;
0e014cb1
AD		 4392 eop = tx_ring->buffer_info[i].next_to_watch;
4393 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4394
4395 while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4396 (count < tx_ring->count)) {
4397 for (cleaned = false; !cleaned; count++) {
4398 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
9d5c8243 4399 buffer_info = &tx_ring->buffer_info[i];
0e014cb1 4400 cleaned = (i == eop);
9d5c8243
AK		 4401 skb = buffer_info->skb;
4402
4403 if (skb) {
4404 unsigned int segs, bytecount;
4405 /* gso_segs is currently only valid for tcp */
4406 segs = skb_shinfo(skb)->gso_segs ?: 1;
4407 /* multiply data chunks by size of headers */
4408 bytecount = ((segs - 1) * skb_headlen(skb)) +
4409 skb->len;
4410 total_packets += segs;
4411 total_bytes += bytecount;
33af6bcc
PO		 4412
4413 igb_tx_hwtstamp(adapter, skb);
9d5c8243
AK		 4414 }
4415
4416 igb_unmap_and_free_tx_resource(adapter, buffer_info);
0e014cb1 4417 tx_desc->wb.status = 0;
9d5c8243
AK		 4418
4419 i++;
4420 if (i == tx_ring->count)
4421 i = 0;
9d5c8243 4422 }
0e014cb1
AD		 4423 eop = tx_ring->buffer_info[i].next_to_watch;
4424 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4425 }
4426
9d5c8243
AK		 4427 tx_ring->next_to_clean = i;
4428
fc7d345d 4429 if (unlikely(count &&
9d5c8243 4430 netif_carrier_ok(netdev) &&
c493ea45 4431 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
9d5c8243
AK		 4432 /* Make sure that anybody stopping the queue after this
4433 * sees the new next_to_clean.
4434 */
4435 smp_mb();
661086df
PWJ		 4436 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4437 !(test_bit(__IGB_DOWN, &adapter->state))) {
4438 netif_wake_subqueue(netdev, tx_ring->queue_index);
4439 ++adapter->restart_queue;
4440 }
9d5c8243
AK		 4441 }
4442
4443 if (tx_ring->detect_tx_hung) {
4444 /* Detect a transmit hang in hardware, this serializes the
4445 * check with the clearing of time_stamp and movement of i */
4446 tx_ring->detect_tx_hung = false;
4447 if (tx_ring->buffer_info[i].time_stamp &&
4448 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4449 (adapter->tx_timeout_factor * HZ))
4450 && !(rd32(E1000_STATUS) &
4451 E1000_STATUS_TXOFF)) {
4452
9d5c8243
AK		 4453 /* detected Tx unit hang */
4454 dev_err(&adapter->pdev->dev,
4455 "Detected Tx Unit Hang\n"
2d064c06 4456 " Tx Queue <%d>\n"
9d5c8243
AK		 4457 " TDH <%x>\n"
4458 " TDT <%x>\n"
4459 " next_to_use <%x>\n"
4460 " next_to_clean <%x>\n"
9d5c8243
AK		 4461 "buffer_info[next_to_clean]\n"
4462 " time_stamp <%lx>\n"
0e014cb1 4463 " next_to_watch <%x>\n"
9d5c8243
AK		 4464 " jiffies <%lx>\n"
4465 " desc.status <%x>\n",
2d064c06 4466 tx_ring->queue_index,
9d5c8243
AK		 4467 readl(adapter->hw.hw_addr + tx_ring->head),
4468 readl(adapter->hw.hw_addr + tx_ring->tail),
4469 tx_ring->next_to_use,
4470 tx_ring->next_to_clean,
9d5c8243 4471 tx_ring->buffer_info[i].time_stamp,
0e014cb1 4472 eop,
9d5c8243 4473 jiffies,
0e014cb1 4474 eop_desc->wb.status);
661086df 4475 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 4476 }
4477 }
4478 tx_ring->total_bytes += total_bytes;
4479 tx_ring->total_packets += total_packets;
e21ed353
AD		 4480 tx_ring->tx_stats.bytes += total_bytes;
4481 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 4482 adapter->net_stats.tx_bytes += total_bytes;
4483 adapter->net_stats.tx_packets += total_packets;
0e014cb1 4484 return (count < tx_ring->count);
9d5c8243
AK		 4485}
4486
9d5c8243
AK		 4487/**
4488 * igb_receive_skb - helper function to handle rx indications
eebbbdba 4489 * @ring: pointer to receive ring receving this packet
9d5c8243 4490 * @status: descriptor status field as written by hardware
73cd78f1 4491 * @rx_desc: receive descriptor containing vlan and type information.
9d5c8243
AK		 4492 * @skb: pointer to sk_buff to be indicated to stack
4493 **/
d3352520
AD		 4494static void igb_receive_skb(struct igb_ring *ring, u8 status,
4495 union e1000_adv_rx_desc * rx_desc,
4496 struct sk_buff *skb)
4497{
4498 struct igb_adapter * adapter = ring->adapter;
4499 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4500
0c8dfc83 4501 skb_record_rx_queue(skb, ring->queue_index);
182ff8df
AD		 4502 if (vlan_extracted)
4503 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4504 le16_to_cpu(rx_desc->wb.upper.vlan),
4505 skb);
4506 else
4507 napi_gro_receive(&ring->napi, skb);
9d5c8243
AK		 4508}
4509
9d5c8243
AK		 4510static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4511 u32 status_err, struct sk_buff *skb)
4512{
4513 skb->ip_summed = CHECKSUM_NONE;
4514
4515 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
7beb0146
AD		 4516 if ((status_err & E1000_RXD_STAT_IXSM) ||
4517 (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
9d5c8243
AK		 4518 return;
4519 /* TCP/UDP checksum error bit is set */
4520 if (status_err &
4521 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 4522 /*
4523 * work around errata with sctp packets where the TCPE aka
4524 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4525 * packets, (aka let the stack check the crc32c)
4526 */
4527 if (!((adapter->hw.mac.type == e1000_82576) &&
4528 (skb->len == 60)))
4529 adapter->hw_csum_err++;
9d5c8243 4530 /* let the stack verify checksum errors */
9d5c8243
AK		 4531 return;
4532 }
4533 /* It must be a TCP or UDP packet with a valid checksum */
4534 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4535 skb->ip_summed = CHECKSUM_UNNECESSARY;
4536
b9473560 4537 dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
9d5c8243
AK		 4538 adapter->hw_csum_good++;
4539}
4540
3b644cf6
MW		 4541static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4542 int *work_done, int budget)
9d5c8243 4543{
3b644cf6 4544 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 4545 struct net_device *netdev = adapter->netdev;
33af6bcc 4546 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 4547 struct pci_dev *pdev = adapter->pdev;
4548 union e1000_adv_rx_desc *rx_desc , *next_rxd;
4549 struct igb_buffer *buffer_info , *next_buffer;
4550 struct sk_buff *skb;
9d5c8243
AK		 4551 bool cleaned = false;
4552 int cleaned_count = 0;
4553 unsigned int total_bytes = 0, total_packets = 0;
73cd78f1
AD		 4554 unsigned int i;
4555 u32 length, hlen, staterr;
9d5c8243
AK		 4556
4557 i = rx_ring->next_to_clean;
69d3ca53 4558 buffer_info = &rx_ring->buffer_info[i];
9d5c8243
AK		 4559 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4560 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4561
4562 while (staterr & E1000_RXD_STAT_DD) {
4563 if (*work_done >= budget)
4564 break;
4565 (*work_done)++;
9d5c8243 4566
69d3ca53
AD		 4567 skb = buffer_info->skb;
4568 prefetch(skb->data - NET_IP_ALIGN);
4569 buffer_info->skb = NULL;
4570
4571 i++;
4572 if (i == rx_ring->count)
4573 i = 0;
4574 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4575 prefetch(next_rxd);
4576 next_buffer = &rx_ring->buffer_info[i];
9d5c8243
AK		 4577
4578 length = le16_to_cpu(rx_desc->wb.upper.length);
4579 cleaned = true;
4580 cleaned_count++;
4581
91615f76 4582 /* this is the fast path for the non-packet split case */
bf36c1a0
AD		 4583 if (!adapter->rx_ps_hdr_size) {
4584 pci_unmap_single(pdev, buffer_info->dma,
91615f76 4585 adapter->rx_buffer_len,
bf36c1a0 4586 PCI_DMA_FROMDEVICE);
91615f76 4587 buffer_info->dma = 0;
bf36c1a0
AD		 4588 skb_put(skb, length);
4589 goto send_up;
9d5c8243
AK		 4590 }
4591
69d3ca53
AD		 4592 /* HW will not DMA in data larger than the given buffer, even
4593 * if it parses the (NFS, of course) header to be larger. In
4594 * that case, it fills the header buffer and spills the rest
4595 * into the page.
4596 */
4597 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4598 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4599 if (hlen > adapter->rx_ps_hdr_size)
4600 hlen = adapter->rx_ps_hdr_size;
4601
bf36c1a0
AD		 4602 if (!skb_shinfo(skb)->nr_frags) {
4603 pci_unmap_single(pdev, buffer_info->dma,
91615f76 4604 adapter->rx_ps_hdr_size,
bf36c1a0 4605 PCI_DMA_FROMDEVICE);
91615f76 4606 buffer_info->dma = 0;
bf36c1a0
AD		 4607 skb_put(skb, hlen);
4608 }
4609
4610 if (length) {
9d5c8243 4611 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 4612 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 4613 buffer_info->page_dma = 0;
bf36c1a0
AD		 4614
4615 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4616 buffer_info->page,
4617 buffer_info->page_offset,
4618 length);
4619
4620 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4621 (page_count(buffer_info->page) != 1))
4622 buffer_info->page = NULL;
4623 else
4624 get_page(buffer_info->page);
9d5c8243
AK		 4625
4626 skb->len += length;
4627 skb->data_len += length;
9d5c8243 4628
bf36c1a0 4629 skb->truesize += length;
9d5c8243 4630 }
9d5c8243 4631
bf36c1a0 4632 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 4633 buffer_info->skb = next_buffer->skb;
4634 buffer_info->dma = next_buffer->dma;
4635 next_buffer->skb = skb;
4636 next_buffer->dma = 0;
bf36c1a0
AD		 4637 goto next_desc;
4638 }
69d3ca53 4639send_up:
33af6bcc
PO		 4640 /*
4641 * If this bit is set, then the RX registers contain
4642 * the time stamp. No other packet will be time
4643 * stamped until we read these registers, so read the
4644 * registers to make them available again. Because
4645 * only one packet can be time stamped at a time, we
4646 * know that the register values must belong to this
4647 * one here and therefore we don't need to compare
4648 * any of the additional attributes stored for it.
4649 *
4650 * If nothing went wrong, then it should have a
4651 * skb_shared_tx that we can turn into a
4652 * skb_shared_hwtstamps.
4653 *
4654 * TODO: can time stamping be triggered (thus locking
4655 * the registers) without the packet reaching this point
4656 * here? In that case RX time stamping would get stuck.
4657 *
4658 * TODO: in "time stamp all packets" mode this bit is
4659 * not set. Need a global flag for this mode and then
4660 * always read the registers. Cannot be done without
4661 * a race condition.
4662 */
4663 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4664 u64 regval;
4665 u64 ns;
4666 struct skb_shared_hwtstamps *shhwtstamps =
4667 skb_hwtstamps(skb);
4668
4669 WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4670 "igb: no RX time stamp available for time stamped packet");
4671 regval = rd32(E1000_RXSTMPL);
4672 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4673 ns = timecounter_cyc2time(&adapter->clock, regval);
4674 timecompare_update(&adapter->compare, ns);
4675 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4676 shhwtstamps->hwtstamp = ns_to_ktime(ns);
4677 shhwtstamps->syststamp =
4678 timecompare_transform(&adapter->compare, ns);
4679 }
4680
9d5c8243
AK		 4681 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4682 dev_kfree_skb_irq(skb);
4683 goto next_desc;
4684 }
9d5c8243
AK		 4685
4686 total_bytes += skb->len;
4687 total_packets++;
4688
4689 igb_rx_checksum_adv(adapter, staterr, skb);
4690
4691 skb->protocol = eth_type_trans(skb, netdev);
4692
d3352520 4693 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 4694
9d5c8243
AK		 4695next_desc:
4696 rx_desc->wb.upper.status_error = 0;
4697
4698 /* return some buffers to hardware, one at a time is too slow */
4699 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 4700 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4701 cleaned_count = 0;
4702 }
4703
4704 /* use prefetched values */
4705 rx_desc = next_rxd;
4706 buffer_info = next_buffer;
9d5c8243
AK		 4707 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4708 }
bf36c1a0 4709
9d5c8243 4710 rx_ring->next_to_clean = i;
c493ea45 4711 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243
AK		 4712
4713 if (cleaned_count)
3b644cf6 4714 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 4715
4716 rx_ring->total_packets += total_packets;
4717 rx_ring->total_bytes += total_bytes;
4718 rx_ring->rx_stats.packets += total_packets;
4719 rx_ring->rx_stats.bytes += total_bytes;
4720 adapter->net_stats.rx_bytes += total_bytes;
4721 adapter->net_stats.rx_packets += total_packets;
4722 return cleaned;
4723}
4724
9d5c8243
AK		 4725/**
4726 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4727 * @adapter: address of board private structure
4728 **/
3b644cf6 4729static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 4730 int cleaned_count)
4731{
3b644cf6 4732 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 4733 struct net_device *netdev = adapter->netdev;
4734 struct pci_dev *pdev = adapter->pdev;
4735 union e1000_adv_rx_desc *rx_desc;
4736 struct igb_buffer *buffer_info;
4737 struct sk_buff *skb;
4738 unsigned int i;
db761762 4739 int bufsz;
9d5c8243
AK		 4740
4741 i = rx_ring->next_to_use;
4742 buffer_info = &rx_ring->buffer_info[i];
4743
db761762
AD		 4744 if (adapter->rx_ps_hdr_size)
4745 bufsz = adapter->rx_ps_hdr_size;
4746 else
4747 bufsz = adapter->rx_buffer_len;
db761762 4748
9d5c8243
AK		 4749 while (cleaned_count--) {
4750 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4751
bf36c1a0 4752 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4753 if (!buffer_info->page) {
bf36c1a0
AD		 4754 buffer_info->page = alloc_page(GFP_ATOMIC);
4755 if (!buffer_info->page) {
4756 adapter->alloc_rx_buff_failed++;
4757 goto no_buffers;
4758 }
4759 buffer_info->page_offset = 0;
4760 } else {
4761 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4762 }
4763 buffer_info->page_dma =
db761762 4764 pci_map_page(pdev, buffer_info->page,
bf36c1a0
AD		 4765 buffer_info->page_offset,
4766 PAGE_SIZE / 2,
9d5c8243
AK		 4767 PCI_DMA_FROMDEVICE);
4768 }
4769
4770 if (!buffer_info->skb) {
91615f76 4771 skb = netdev_alloc_skb(netdev, bufsz + NET_IP_ALIGN);
9d5c8243
AK		 4772 if (!skb) {
4773 adapter->alloc_rx_buff_failed++;
4774 goto no_buffers;
4775 }
4776
4777 /* Make buffer alignment 2 beyond a 16 byte boundary
4778 * this will result in a 16 byte aligned IP header after
4779 * the 14 byte MAC header is removed
4780 */
4781 skb_reserve(skb, NET_IP_ALIGN);
4782
4783 buffer_info->skb = skb;
4784 buffer_info->dma = pci_map_single(pdev, skb->data,
4785 bufsz,
4786 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 4787 }
4788 /* Refresh the desc even if buffer_addrs didn't change because
4789 * each write-back erases this info. */
4790 if (adapter->rx_ps_hdr_size) {
4791 rx_desc->read.pkt_addr =
4792 cpu_to_le64(buffer_info->page_dma);
4793 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4794 } else {
4795 rx_desc->read.pkt_addr =
4796 cpu_to_le64(buffer_info->dma);
4797 rx_desc->read.hdr_addr = 0;
4798 }
4799
4800 i++;
4801 if (i == rx_ring->count)
4802 i = 0;
4803 buffer_info = &rx_ring->buffer_info[i];
4804 }
4805
4806no_buffers:
4807 if (rx_ring->next_to_use != i) {
4808 rx_ring->next_to_use = i;
4809 if (i == 0)
4810 i = (rx_ring->count - 1);
4811 else
4812 i--;
4813
4814 /* Force memory writes to complete before letting h/w
4815 * know there are new descriptors to fetch. (Only
4816 * applicable for weak-ordered memory model archs,
4817 * such as IA-64). */
4818 wmb();
4819 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4820 }
4821}
4822
4823/**
4824 * igb_mii_ioctl -
4825 * @netdev:
4826 * @ifreq:
4827 * @cmd:
4828 **/
4829static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4830{
4831 struct igb_adapter *adapter = netdev_priv(netdev);
4832 struct mii_ioctl_data *data = if_mii(ifr);
4833
4834 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4835 return -EOPNOTSUPP;
4836
4837 switch (cmd) {
4838 case SIOCGMIIPHY:
4839 data->phy_id = adapter->hw.phy.addr;
4840 break;
4841 case SIOCGMIIREG:
4842 if (!capable(CAP_NET_ADMIN))
4843 return -EPERM;
f5f4cf08
AD		 4844 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4845 &data->val_out))
9d5c8243
AK		 4846 return -EIO;
4847 break;
4848 case SIOCSMIIREG:
4849 default:
4850 return -EOPNOTSUPP;
4851 }
4852 return 0;
4853}
4854
c6cb090b
PO		 4855/**
4856 * igb_hwtstamp_ioctl - control hardware time stamping
4857 * @netdev:
4858 * @ifreq:
4859 * @cmd:
4860 *
33af6bcc
PO		 4861 * Outgoing time stamping can be enabled and disabled. Play nice and
4862 * disable it when requested, although it shouldn't case any overhead
4863 * when no packet needs it. At most one packet in the queue may be
4864 * marked for time stamping, otherwise it would be impossible to tell
4865 * for sure to which packet the hardware time stamp belongs.
4866 *
4867 * Incoming time stamping has to be configured via the hardware
4868 * filters. Not all combinations are supported, in particular event
4869 * type has to be specified. Matching the kind of event packet is
4870 * not supported, with the exception of "all V2 events regardless of
4871 * level 2 or 4".
4872 *
c6cb090b
PO		 4873 **/
4874static int igb_hwtstamp_ioctl(struct net_device *netdev,
4875 struct ifreq *ifr, int cmd)
4876{
33af6bcc
PO		 4877 struct igb_adapter *adapter = netdev_priv(netdev);
4878 struct e1000_hw *hw = &adapter->hw;
c6cb090b 4879 struct hwtstamp_config config;
33af6bcc
PO		 4880 u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4881 u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4882 u32 tsync_rx_ctl_type = 0;
4883 u32 tsync_rx_cfg = 0;
4884 int is_l4 = 0;
4885 int is_l2 = 0;
4886 short port = 319; /* PTP */
4887 u32 regval;
c6cb090b
PO		 4888
4889 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4890 return -EFAULT;
4891
4892 /* reserved for future extensions */
4893 if (config.flags)
4894 return -EINVAL;
4895
33af6bcc
PO		 4896 switch (config.tx_type) {
4897 case HWTSTAMP_TX_OFF:
4898 tsync_tx_ctl_bit = 0;
4899 break;
4900 case HWTSTAMP_TX_ON:
4901 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4902 break;
4903 default:
4904 return -ERANGE;
4905 }
4906
4907 switch (config.rx_filter) {
4908 case HWTSTAMP_FILTER_NONE:
4909 tsync_rx_ctl_bit = 0;
4910 break;
4911 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4912 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4913 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4914 case HWTSTAMP_FILTER_ALL:
4915 /*
4916 * register TSYNCRXCFG must be set, therefore it is not
4917 * possible to time stamp both Sync and Delay_Req messages
4918 * => fall back to time stamping all packets
4919 */
4920 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4921 config.rx_filter = HWTSTAMP_FILTER_ALL;
4922 break;
4923 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4924 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4925 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4926 is_l4 = 1;
4927 break;
4928 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4929 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4930 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4931 is_l4 = 1;
4932 break;
4933 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4934 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4935 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4936 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4937 is_l2 = 1;
4938 is_l4 = 1;
4939 config.rx_filter = HWTSTAMP_FILTER_SOME;
4940 break;
4941 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4942 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4943 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4944 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4945 is_l2 = 1;
4946 is_l4 = 1;
4947 config.rx_filter = HWTSTAMP_FILTER_SOME;
4948 break;
4949 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4950 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4951 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4952 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4953 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4954 is_l2 = 1;
4955 break;
4956 default:
4957 return -ERANGE;
4958 }
4959
4960 /* enable/disable TX */
4961 regval = rd32(E1000_TSYNCTXCTL);
4962 regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4963 wr32(E1000_TSYNCTXCTL, regval);
4964
4965 /* enable/disable RX, define which PTP packets are time stamped */
4966 regval = rd32(E1000_TSYNCRXCTL);
4967 regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4968 regval = (regval & ~0xE) | tsync_rx_ctl_type;
4969 wr32(E1000_TSYNCRXCTL, regval);
4970 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4971
4972 /*
4973 * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4974 * (Ethertype to filter on)
4975 * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4976 * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4977 */
4978 wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4979
4980 /* L4 Queue Filter[0]: only filter by source and destination port */
4981 wr32(E1000_SPQF0, htons(port));
4982 wr32(E1000_IMIREXT(0), is_l4 ?
4983 ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4984 wr32(E1000_IMIR(0), is_l4 ?
4985 (htons(port)
4986 | (0<<16) /* immediate interrupt disabled */
4987 | 0 /* (1<<17) bit cleared: do not bypass
4988 destination port check */)
4989 : 0);
4990 wr32(E1000_FTQF0, is_l4 ?
4991 (0x11 /* UDP */
4992 | (1<<15) /* VF not compared */
4993 | (1<<27) /* Enable Timestamping */
4994 | (7<<28) /* only source port filter enabled,
4995 source/target address and protocol
4996 masked */)
4997 : ((1<<15) | (15<<28) /* all mask bits set = filter not
4998 enabled */));
4999
5000 wrfl();
5001
5002 adapter->hwtstamp_config = config;
5003
5004 /* clear TX/RX time stamp registers, just to be sure */
5005 regval = rd32(E1000_TXSTMPH);
5006 regval = rd32(E1000_RXSTMPH);
c6cb090b 5007
33af6bcc
PO		 5008 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5009 -EFAULT : 0;
c6cb090b
PO		 5010}
5011
9d5c8243
AK		 5012/**
5013 * igb_ioctl -
5014 * @netdev:
5015 * @ifreq:
5016 * @cmd:
5017 **/
5018static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5019{
5020 switch (cmd) {
5021 case SIOCGMIIPHY:
5022 case SIOCGMIIREG:
5023 case SIOCSMIIREG:
5024 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b
PO		 5025 case SIOCSHWTSTAMP:
5026 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 5027 default:
5028 return -EOPNOTSUPP;
5029 }
5030}
5031
009bc06e
AD		 5032s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5033{
5034 struct igb_adapter *adapter = hw->back;
5035 u16 cap_offset;
5036
5037 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5038 if (!cap_offset)
5039 return -E1000_ERR_CONFIG;
5040
5041 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5042
5043 return 0;
5044}
5045
5046s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5047{
5048 struct igb_adapter *adapter = hw->back;
5049 u16 cap_offset;
5050
5051 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5052 if (!cap_offset)
5053 return -E1000_ERR_CONFIG;
5054
5055 pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5056
5057 return 0;
5058}
5059
9d5c8243
AK		 5060static void igb_vlan_rx_register(struct net_device *netdev,
5061 struct vlan_group *grp)
5062{
5063 struct igb_adapter *adapter = netdev_priv(netdev);
5064 struct e1000_hw *hw = &adapter->hw;
5065 u32 ctrl, rctl;
5066
5067 igb_irq_disable(adapter);
5068 adapter->vlgrp = grp;
5069
5070 if (grp) {
5071 /* enable VLAN tag insert/strip */
5072 ctrl = rd32(E1000_CTRL);
5073 ctrl |= E1000_CTRL_VME;
5074 wr32(E1000_CTRL, ctrl);
5075
5076 /* enable VLAN receive filtering */
5077 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 5078 rctl &= ~E1000_RCTL_CFIEN;
5079 wr32(E1000_RCTL, rctl);
5080 igb_update_mng_vlan(adapter);
9d5c8243
AK		 5081 } else {
5082 /* disable VLAN tag insert/strip */
5083 ctrl = rd32(E1000_CTRL);
5084 ctrl &= ~E1000_CTRL_VME;
5085 wr32(E1000_CTRL, ctrl);
5086
9d5c8243
AK		 5087 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5088 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5089 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5090 }
9d5c8243
AK		 5091 }
5092
e1739522
AD		 5093 igb_rlpml_set(adapter);
5094
9d5c8243
AK		 5095 if (!test_bit(__IGB_DOWN, &adapter->state))
5096 igb_irq_enable(adapter);
5097}
5098
5099static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5100{
5101 struct igb_adapter *adapter = netdev_priv(netdev);
5102 struct e1000_hw *hw = &adapter->hw;
4ae196df 5103 int pf_id = adapter->vfs_allocated_count;
9d5c8243 5104
28b0759c 5105 if ((hw->mng_cookie.status &
9d5c8243
AK		 5106 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5107 (vid == adapter->mng_vlan_id))
5108 return;
4ae196df
AD		 5109
5110 /* add vid to vlvf if sr-iov is enabled,
5111 * if that fails add directly to filter table */
5112 if (igb_vlvf_set(adapter, vid, true, pf_id))
5113 igb_vfta_set(hw, vid, true);
5114
9d5c8243
AK		 5115}
5116
5117static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5118{
5119 struct igb_adapter *adapter = netdev_priv(netdev);
5120 struct e1000_hw *hw = &adapter->hw;
4ae196df 5121 int pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 5122
5123 igb_irq_disable(adapter);
5124 vlan_group_set_device(adapter->vlgrp, vid, NULL);
5125
5126 if (!test_bit(__IGB_DOWN, &adapter->state))
5127 igb_irq_enable(adapter);
5128
5129 if ((adapter->hw.mng_cookie.status &
5130 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5131 (vid == adapter->mng_vlan_id)) {
5132 /* release control to f/w */
5133 igb_release_hw_control(adapter);
5134 return;
5135 }
5136
4ae196df
AD		 5137 /* remove vid from vlvf if sr-iov is enabled,
5138 * if not in vlvf remove from vfta */
5139 if (igb_vlvf_set(adapter, vid, false, pf_id))
5140 igb_vfta_set(hw, vid, false);
9d5c8243
AK		 5141}
5142
5143static void igb_restore_vlan(struct igb_adapter *adapter)
5144{
5145 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5146
5147 if (adapter->vlgrp) {
5148 u16 vid;
5149 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5150 if (!vlan_group_get_device(adapter->vlgrp, vid))
5151 continue;
5152 igb_vlan_rx_add_vid(adapter->netdev, vid);
5153 }
5154 }
5155}
5156
5157int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5158{
5159 struct e1000_mac_info *mac = &adapter->hw.mac;
5160
5161 mac->autoneg = 0;
5162
9d5c8243
AK		 5163 switch (spddplx) {
5164 case SPEED_10 + DUPLEX_HALF:
5165 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5166 break;
5167 case SPEED_10 + DUPLEX_FULL:
5168 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5169 break;
5170 case SPEED_100 + DUPLEX_HALF:
5171 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5172 break;
5173 case SPEED_100 + DUPLEX_FULL:
5174 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5175 break;
5176 case SPEED_1000 + DUPLEX_FULL:
5177 mac->autoneg = 1;
5178 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5179 break;
5180 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5181 default:
5182 dev_err(&adapter->pdev->dev,
5183 "Unsupported Speed/Duplex configuration\n");
5184 return -EINVAL;
5185 }
5186 return 0;
5187}
5188
3fe7c4c9 5189static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
9d5c8243
AK		 5190{
5191 struct net_device *netdev = pci_get_drvdata(pdev);
5192 struct igb_adapter *adapter = netdev_priv(netdev);
5193 struct e1000_hw *hw = &adapter->hw;
2d064c06 5194 u32 ctrl, rctl, status;
9d5c8243
AK		 5195 u32 wufc = adapter->wol;
5196#ifdef CONFIG_PM
5197 int retval = 0;
5198#endif
5199
5200 netif_device_detach(netdev);
5201
a88f10ec
AD		 5202 if (netif_running(netdev))
5203 igb_close(netdev);
5204
5205 igb_reset_interrupt_capability(adapter);
5206
5207 igb_free_queues(adapter);
9d5c8243
AK		 5208
5209#ifdef CONFIG_PM
5210 retval = pci_save_state(pdev);
5211 if (retval)
5212 return retval;
5213#endif
5214
5215 status = rd32(E1000_STATUS);
5216 if (status & E1000_STATUS_LU)
5217 wufc &= ~E1000_WUFC_LNKC;
5218
5219 if (wufc) {
5220 igb_setup_rctl(adapter);
5221 igb_set_multi(netdev);
5222
5223 /* turn on all-multi mode if wake on multicast is enabled */
5224 if (wufc & E1000_WUFC_MC) {
5225 rctl = rd32(E1000_RCTL);
5226 rctl |= E1000_RCTL_MPE;
5227 wr32(E1000_RCTL, rctl);
5228 }
5229
5230 ctrl = rd32(E1000_CTRL);
5231 /* advertise wake from D3Cold */
5232 #define E1000_CTRL_ADVD3WUC 0x00100000
5233 /* phy power management enable */
5234 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5235 ctrl |= E1000_CTRL_ADVD3WUC;
5236 wr32(E1000_CTRL, ctrl);
5237
9d5c8243
AK		 5238 /* Allow time for pending master requests to run */
5239 igb_disable_pcie_master(&adapter->hw);
5240
5241 wr32(E1000_WUC, E1000_WUC_PME_EN);
5242 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 5243 } else {
5244 wr32(E1000_WUC, 0);
5245 wr32(E1000_WUFC, 0);
9d5c8243
AK		 5246 }
5247
3fe7c4c9
RW		 5248 *enable_wake = wufc || adapter->en_mng_pt;
5249 if (!*enable_wake)
2d064c06 5250 igb_shutdown_fiber_serdes_link_82575(hw);
9d5c8243
AK		 5251
5252 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5253 * would have already happened in close and is redundant. */
5254 igb_release_hw_control(adapter);
5255
5256 pci_disable_device(pdev);
5257
9d5c8243
AK		 5258 return 0;
5259}
5260
5261#ifdef CONFIG_PM
3fe7c4c9
RW		 5262static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5263{
5264 int retval;
5265 bool wake;
5266
5267 retval = __igb_shutdown(pdev, &wake);
5268 if (retval)
5269 return retval;
5270
5271 if (wake) {
5272 pci_prepare_to_sleep(pdev);
5273 } else {
5274 pci_wake_from_d3(pdev, false);
5275 pci_set_power_state(pdev, PCI_D3hot);
5276 }
5277
5278 return 0;
5279}
5280
9d5c8243
AK		 5281static int igb_resume(struct pci_dev *pdev)
5282{
5283 struct net_device *netdev = pci_get_drvdata(pdev);
5284 struct igb_adapter *adapter = netdev_priv(netdev);
5285 struct e1000_hw *hw = &adapter->hw;
5286 u32 err;
5287
5288 pci_set_power_state(pdev, PCI_D0);
5289 pci_restore_state(pdev);
42bfd33a 5290
aed5dec3 5291 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 5292 if (err) {
5293 dev_err(&pdev->dev,
5294 "igb: Cannot enable PCI device from suspend\n");
5295 return err;
5296 }
5297 pci_set_master(pdev);
5298
5299 pci_enable_wake(pdev, PCI_D3hot, 0);
5300 pci_enable_wake(pdev, PCI_D3cold, 0);
5301
a88f10ec
AD		 5302 igb_set_interrupt_capability(adapter);
5303
5304 if (igb_alloc_queues(adapter)) {
5305 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5306 return -ENOMEM;
9d5c8243
AK		 5307 }
5308
5309 /* e1000_power_up_phy(adapter); */
5310
5311 igb_reset(adapter);
a8564f03
AD		 5312
5313 /* let the f/w know that the h/w is now under the control of the
5314 * driver. */
5315 igb_get_hw_control(adapter);
5316
9d5c8243
AK		 5317 wr32(E1000_WUS, ~0);
5318
a88f10ec
AD		 5319 if (netif_running(netdev)) {
5320 err = igb_open(netdev);
5321 if (err)
5322 return err;
5323 }
9d5c8243
AK		 5324
5325 netif_device_attach(netdev);
5326
9d5c8243
AK		 5327 return 0;
5328}
5329#endif
5330
5331static void igb_shutdown(struct pci_dev *pdev)
5332{
3fe7c4c9
RW		 5333 bool wake;
5334
5335 __igb_shutdown(pdev, &wake);
5336
5337 if (system_state == SYSTEM_POWER_OFF) {
5338 pci_wake_from_d3(pdev, wake);
5339 pci_set_power_state(pdev, PCI_D3hot);
5340 }
9d5c8243
AK		 5341}
5342
5343#ifdef CONFIG_NET_POLL_CONTROLLER
5344/*
5345 * Polling 'interrupt' - used by things like netconsole to send skbs
5346 * without having to re-enable interrupts. It's not called while
5347 * the interrupt routine is executing.
5348 */
5349static void igb_netpoll(struct net_device *netdev)
5350{
5351 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 5352 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5353 int i;
9d5c8243 5354
eebbbdba
AD		 5355 if (!adapter->msix_entries) {
5356 igb_irq_disable(adapter);
5357 napi_schedule(&adapter->rx_ring[0].napi);
5358 return;
5359 }
9d5c8243 5360
eebbbdba
AD		 5361 for (i = 0; i < adapter->num_tx_queues; i++) {
5362 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5363 wr32(E1000_EIMC, tx_ring->eims_value);
5364 igb_clean_tx_irq(tx_ring);
5365 wr32(E1000_EIMS, tx_ring->eims_value);
5366 }
9d5c8243 5367
eebbbdba
AD		 5368 for (i = 0; i < adapter->num_rx_queues; i++) {
5369 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5370 wr32(E1000_EIMC, rx_ring->eims_value);
5371 napi_schedule(&rx_ring->napi);
5372 }
9d5c8243
AK		 5373}
5374#endif /* CONFIG_NET_POLL_CONTROLLER */
5375
5376/**
5377 * igb_io_error_detected - called when PCI error is detected
5378 * @pdev: Pointer to PCI device
5379 * @state: The current pci connection state
5380 *
5381 * This function is called after a PCI bus error affecting
5382 * this device has been detected.
5383 */
5384static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5385 pci_channel_state_t state)
5386{
5387 struct net_device *netdev = pci_get_drvdata(pdev);
5388 struct igb_adapter *adapter = netdev_priv(netdev);
5389
5390 netif_device_detach(netdev);
5391
59ed6eec
AD		 5392 if (state == pci_channel_io_perm_failure)
5393 return PCI_ERS_RESULT_DISCONNECT;
5394
9d5c8243
AK		 5395 if (netif_running(netdev))
5396 igb_down(adapter);
5397 pci_disable_device(pdev);
5398
5399 /* Request a slot slot reset. */
5400 return PCI_ERS_RESULT_NEED_RESET;
5401}
5402
5403/**
5404 * igb_io_slot_reset - called after the pci bus has been reset.
5405 * @pdev: Pointer to PCI device
5406 *
5407 * Restart the card from scratch, as if from a cold-boot. Implementation
5408 * resembles the first-half of the igb_resume routine.
5409 */
5410static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5411{
5412 struct net_device *netdev = pci_get_drvdata(pdev);
5413 struct igb_adapter *adapter = netdev_priv(netdev);
5414 struct e1000_hw *hw = &adapter->hw;
40a914fa 5415 pci_ers_result_t result;
42bfd33a 5416 int err;
9d5c8243 5417
aed5dec3 5418 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 5419 dev_err(&pdev->dev,
5420 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 5421 result = PCI_ERS_RESULT_DISCONNECT;
5422 } else {
5423 pci_set_master(pdev);
5424 pci_restore_state(pdev);
9d5c8243 5425
40a914fa
AD		 5426 pci_enable_wake(pdev, PCI_D3hot, 0);
5427 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 5428
40a914fa
AD		 5429 igb_reset(adapter);
5430 wr32(E1000_WUS, ~0);
5431 result = PCI_ERS_RESULT_RECOVERED;
5432 }
9d5c8243 5433
ea943d41
JK		 5434 err = pci_cleanup_aer_uncorrect_error_status(pdev);
5435 if (err) {
5436 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5437 "failed 0x%0x\n", err);
5438 /* non-fatal, continue */
5439 }
40a914fa
AD		 5440
5441 return result;
9d5c8243
AK		 5442}
5443
5444/**
5445 * igb_io_resume - called when traffic can start flowing again.
5446 * @pdev: Pointer to PCI device
5447 *
5448 * This callback is called when the error recovery driver tells us that
5449 * its OK to resume normal operation. Implementation resembles the
5450 * second-half of the igb_resume routine.
5451 */
5452static void igb_io_resume(struct pci_dev *pdev)
5453{
5454 struct net_device *netdev = pci_get_drvdata(pdev);
5455 struct igb_adapter *adapter = netdev_priv(netdev);
5456
9d5c8243
AK		 5457 if (netif_running(netdev)) {
5458 if (igb_up(adapter)) {
5459 dev_err(&pdev->dev, "igb_up failed after reset\n");
5460 return;
5461 }
5462 }
5463
5464 netif_device_attach(netdev);
5465
5466 /* let the f/w know that the h/w is now under the control of the
5467 * driver. */
5468 igb_get_hw_control(adapter);
9d5c8243
AK		 5469}
5470
e1739522
AD		 5471static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5472 int entry_count, u16 total_rar_filters)
5473{
5474 struct e1000_hw *hw = &adapter->hw;
5475 int i = adapter->vfs_allocated_count + 1;
5476
5477 if ((i + entry_count) < total_rar_filters)
5478 total_rar_filters = i + entry_count;
5479
5480 for (; i < total_rar_filters; i++)
5481 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5482}
5483
4ae196df
AD		 5484static int igb_set_vf_mac(struct igb_adapter *adapter,
5485 int vf, unsigned char *mac_addr)
5486{
5487 struct e1000_hw *hw = &adapter->hw;
5488 int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5489
5490 igb_rar_set(hw, mac_addr, rar_entry);
5491
37680117 5492 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df
AD		 5493
5494 igb_set_rah_pool(hw, vf, rar_entry);
5495
5496 return 0;
5497}
5498
5499static void igb_vmm_control(struct igb_adapter *adapter)
5500{
5501 struct e1000_hw *hw = &adapter->hw;
5502 u32 reg_data;
5503
5504 if (!adapter->vfs_allocated_count)
5505 return;
5506
5507 /* VF's need PF reset indication before they
5508 * can send/receive mail */
5509 reg_data = rd32(E1000_CTRL_EXT);
5510 reg_data |= E1000_CTRL_EXT_PFRSTD;
5511 wr32(E1000_CTRL_EXT, reg_data);
5512
5513 igb_vmdq_set_loopback_pf(hw, true);
5514 igb_vmdq_set_replication_pf(hw, true);
5515}
5516
9d5c8243 5517/* igb_main.c */
Linux 6.x block layer and io_uring tree(s)