Commit | Line | Data |
---|---|---|
9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | /* ethtool support for igb */ | |
29 | ||
30 | #include <linux/vmalloc.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/if_ether.h> | |
36 | #include <linux/ethtool.h> | |
d43c36dc | 37 | #include <linux/sched.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
9d5c8243 AK |
39 | |
40 | #include "igb.h" | |
41 | ||
42 | struct igb_stats { | |
43 | char stat_string[ETH_GSTRING_LEN]; | |
44 | int sizeof_stat; | |
45 | int stat_offset; | |
46 | }; | |
47 | ||
128e45eb AD |
48 | #define IGB_STAT(_name, _stat) { \ |
49 | .stat_string = _name, \ | |
50 | .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \ | |
51 | .stat_offset = offsetof(struct igb_adapter, _stat) \ | |
52 | } | |
9d5c8243 | 53 | static const struct igb_stats igb_gstrings_stats[] = { |
128e45eb AD |
54 | IGB_STAT("rx_packets", stats.gprc), |
55 | IGB_STAT("tx_packets", stats.gptc), | |
56 | IGB_STAT("rx_bytes", stats.gorc), | |
57 | IGB_STAT("tx_bytes", stats.gotc), | |
58 | IGB_STAT("rx_broadcast", stats.bprc), | |
59 | IGB_STAT("tx_broadcast", stats.bptc), | |
60 | IGB_STAT("rx_multicast", stats.mprc), | |
61 | IGB_STAT("tx_multicast", stats.mptc), | |
62 | IGB_STAT("multicast", stats.mprc), | |
63 | IGB_STAT("collisions", stats.colc), | |
64 | IGB_STAT("rx_crc_errors", stats.crcerrs), | |
65 | IGB_STAT("rx_no_buffer_count", stats.rnbc), | |
66 | IGB_STAT("rx_missed_errors", stats.mpc), | |
67 | IGB_STAT("tx_aborted_errors", stats.ecol), | |
68 | IGB_STAT("tx_carrier_errors", stats.tncrs), | |
69 | IGB_STAT("tx_window_errors", stats.latecol), | |
70 | IGB_STAT("tx_abort_late_coll", stats.latecol), | |
71 | IGB_STAT("tx_deferred_ok", stats.dc), | |
72 | IGB_STAT("tx_single_coll_ok", stats.scc), | |
73 | IGB_STAT("tx_multi_coll_ok", stats.mcc), | |
74 | IGB_STAT("tx_timeout_count", tx_timeout_count), | |
75 | IGB_STAT("rx_long_length_errors", stats.roc), | |
76 | IGB_STAT("rx_short_length_errors", stats.ruc), | |
77 | IGB_STAT("rx_align_errors", stats.algnerrc), | |
78 | IGB_STAT("tx_tcp_seg_good", stats.tsctc), | |
79 | IGB_STAT("tx_tcp_seg_failed", stats.tsctfc), | |
80 | IGB_STAT("rx_flow_control_xon", stats.xonrxc), | |
81 | IGB_STAT("rx_flow_control_xoff", stats.xoffrxc), | |
82 | IGB_STAT("tx_flow_control_xon", stats.xontxc), | |
83 | IGB_STAT("tx_flow_control_xoff", stats.xofftxc), | |
84 | IGB_STAT("rx_long_byte_count", stats.gorc), | |
85 | IGB_STAT("tx_dma_out_of_sync", stats.doosync), | |
86 | IGB_STAT("tx_smbus", stats.mgptc), | |
87 | IGB_STAT("rx_smbus", stats.mgprc), | |
88 | IGB_STAT("dropped_smbus", stats.mgpdc), | |
0a915b95 CW |
89 | IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc), |
90 | IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc), | |
91 | IGB_STAT("os2bmc_tx_by_host", stats.o2bspc), | |
92 | IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc), | |
128e45eb AD |
93 | }; |
94 | ||
95 | #define IGB_NETDEV_STAT(_net_stat) { \ | |
96 | .stat_string = __stringify(_net_stat), \ | |
12dcd86b ED |
97 | .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \ |
98 | .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \ | |
128e45eb AD |
99 | } |
100 | static const struct igb_stats igb_gstrings_net_stats[] = { | |
101 | IGB_NETDEV_STAT(rx_errors), | |
102 | IGB_NETDEV_STAT(tx_errors), | |
103 | IGB_NETDEV_STAT(tx_dropped), | |
104 | IGB_NETDEV_STAT(rx_length_errors), | |
105 | IGB_NETDEV_STAT(rx_over_errors), | |
106 | IGB_NETDEV_STAT(rx_frame_errors), | |
107 | IGB_NETDEV_STAT(rx_fifo_errors), | |
108 | IGB_NETDEV_STAT(tx_fifo_errors), | |
109 | IGB_NETDEV_STAT(tx_heartbeat_errors) | |
9d5c8243 AK |
110 | }; |
111 | ||
128e45eb AD |
112 | #define IGB_GLOBAL_STATS_LEN \ |
113 | (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)) | |
114 | #define IGB_NETDEV_STATS_LEN \ | |
115 | (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats)) | |
116 | #define IGB_RX_QUEUE_STATS_LEN \ | |
117 | (sizeof(struct igb_rx_queue_stats) / sizeof(u64)) | |
12dcd86b ED |
118 | |
119 | #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */ | |
120 | ||
9d5c8243 | 121 | #define IGB_QUEUE_STATS_LEN \ |
317f66bd | 122 | ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \ |
128e45eb | 123 | IGB_RX_QUEUE_STATS_LEN) + \ |
317f66bd | 124 | (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \ |
128e45eb AD |
125 | IGB_TX_QUEUE_STATS_LEN)) |
126 | #define IGB_STATS_LEN \ | |
127 | (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN) | |
128 | ||
9d5c8243 AK |
129 | static const char igb_gstrings_test[][ETH_GSTRING_LEN] = { |
130 | "Register test (offline)", "Eeprom test (offline)", | |
131 | "Interrupt test (offline)", "Loopback test (offline)", | |
132 | "Link test (on/offline)" | |
133 | }; | |
317f66bd | 134 | #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN) |
9d5c8243 AK |
135 | |
136 | static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) | |
137 | { | |
138 | struct igb_adapter *adapter = netdev_priv(netdev); | |
139 | struct e1000_hw *hw = &adapter->hw; | |
317f66bd | 140 | u32 status; |
9d5c8243 AK |
141 | |
142 | if (hw->phy.media_type == e1000_media_type_copper) { | |
143 | ||
144 | ecmd->supported = (SUPPORTED_10baseT_Half | | |
145 | SUPPORTED_10baseT_Full | | |
146 | SUPPORTED_100baseT_Half | | |
147 | SUPPORTED_100baseT_Full | | |
148 | SUPPORTED_1000baseT_Full| | |
149 | SUPPORTED_Autoneg | | |
150 | SUPPORTED_TP); | |
151 | ecmd->advertising = ADVERTISED_TP; | |
152 | ||
153 | if (hw->mac.autoneg == 1) { | |
154 | ecmd->advertising |= ADVERTISED_Autoneg; | |
155 | /* the e1000 autoneg seems to match ethtool nicely */ | |
156 | ecmd->advertising |= hw->phy.autoneg_advertised; | |
157 | } | |
158 | ||
159 | ecmd->port = PORT_TP; | |
160 | ecmd->phy_address = hw->phy.addr; | |
161 | } else { | |
162 | ecmd->supported = (SUPPORTED_1000baseT_Full | | |
163 | SUPPORTED_FIBRE | | |
164 | SUPPORTED_Autoneg); | |
165 | ||
166 | ecmd->advertising = (ADVERTISED_1000baseT_Full | | |
167 | ADVERTISED_FIBRE | | |
168 | ADVERTISED_Autoneg); | |
169 | ||
170 | ecmd->port = PORT_FIBRE; | |
171 | } | |
172 | ||
173 | ecmd->transceiver = XCVR_INTERNAL; | |
174 | ||
317f66bd | 175 | status = rd32(E1000_STATUS); |
9d5c8243 | 176 | |
317f66bd | 177 | if (status & E1000_STATUS_LU) { |
9d5c8243 | 178 | |
317f66bd AD |
179 | if ((status & E1000_STATUS_SPEED_1000) || |
180 | hw->phy.media_type != e1000_media_type_copper) | |
70739497 | 181 | ethtool_cmd_speed_set(ecmd, SPEED_1000); |
317f66bd | 182 | else if (status & E1000_STATUS_SPEED_100) |
70739497 | 183 | ethtool_cmd_speed_set(ecmd, SPEED_100); |
317f66bd | 184 | else |
70739497 | 185 | ethtool_cmd_speed_set(ecmd, SPEED_10); |
9d5c8243 | 186 | |
317f66bd AD |
187 | if ((status & E1000_STATUS_FD) || |
188 | hw->phy.media_type != e1000_media_type_copper) | |
9d5c8243 AK |
189 | ecmd->duplex = DUPLEX_FULL; |
190 | else | |
191 | ecmd->duplex = DUPLEX_HALF; | |
192 | } else { | |
70739497 | 193 | ethtool_cmd_speed_set(ecmd, -1); |
9d5c8243 AK |
194 | ecmd->duplex = -1; |
195 | } | |
196 | ||
dcc3ae9a | 197 | ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; |
9d5c8243 AK |
198 | return 0; |
199 | } | |
200 | ||
201 | static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) | |
202 | { | |
203 | struct igb_adapter *adapter = netdev_priv(netdev); | |
204 | struct e1000_hw *hw = &adapter->hw; | |
205 | ||
206 | /* When SoL/IDER sessions are active, autoneg/speed/duplex | |
207 | * cannot be changed */ | |
208 | if (igb_check_reset_block(hw)) { | |
209 | dev_err(&adapter->pdev->dev, "Cannot change link " | |
210 | "characteristics when SoL/IDER is active.\n"); | |
211 | return -EINVAL; | |
212 | } | |
213 | ||
214 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
215 | msleep(1); | |
216 | ||
217 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
218 | hw->mac.autoneg = 1; | |
dcc3ae9a AD |
219 | hw->phy.autoneg_advertised = ecmd->advertising | |
220 | ADVERTISED_TP | | |
221 | ADVERTISED_Autoneg; | |
9d5c8243 | 222 | ecmd->advertising = hw->phy.autoneg_advertised; |
0cce119a AD |
223 | if (adapter->fc_autoneg) |
224 | hw->fc.requested_mode = e1000_fc_default; | |
dcc3ae9a | 225 | } else { |
25db0338 DD |
226 | u32 speed = ethtool_cmd_speed(ecmd); |
227 | if (igb_set_spd_dplx(adapter, speed + ecmd->duplex)) { | |
9d5c8243 AK |
228 | clear_bit(__IGB_RESETTING, &adapter->state); |
229 | return -EINVAL; | |
230 | } | |
dcc3ae9a | 231 | } |
9d5c8243 AK |
232 | |
233 | /* reset the link */ | |
9d5c8243 AK |
234 | if (netif_running(adapter->netdev)) { |
235 | igb_down(adapter); | |
236 | igb_up(adapter); | |
237 | } else | |
238 | igb_reset(adapter); | |
239 | ||
240 | clear_bit(__IGB_RESETTING, &adapter->state); | |
241 | return 0; | |
242 | } | |
243 | ||
3145535a NN |
244 | static u32 igb_get_link(struct net_device *netdev) |
245 | { | |
246 | struct igb_adapter *adapter = netdev_priv(netdev); | |
247 | struct e1000_mac_info *mac = &adapter->hw.mac; | |
248 | ||
249 | /* | |
250 | * If the link is not reported up to netdev, interrupts are disabled, | |
251 | * and so the physical link state may have changed since we last | |
252 | * looked. Set get_link_status to make sure that the true link | |
253 | * state is interrogated, rather than pulling a cached and possibly | |
254 | * stale link state from the driver. | |
255 | */ | |
256 | if (!netif_carrier_ok(netdev)) | |
257 | mac->get_link_status = 1; | |
258 | ||
259 | return igb_has_link(adapter); | |
260 | } | |
261 | ||
9d5c8243 AK |
262 | static void igb_get_pauseparam(struct net_device *netdev, |
263 | struct ethtool_pauseparam *pause) | |
264 | { | |
265 | struct igb_adapter *adapter = netdev_priv(netdev); | |
266 | struct e1000_hw *hw = &adapter->hw; | |
267 | ||
268 | pause->autoneg = | |
269 | (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); | |
270 | ||
0cce119a | 271 | if (hw->fc.current_mode == e1000_fc_rx_pause) |
9d5c8243 | 272 | pause->rx_pause = 1; |
0cce119a | 273 | else if (hw->fc.current_mode == e1000_fc_tx_pause) |
9d5c8243 | 274 | pause->tx_pause = 1; |
0cce119a | 275 | else if (hw->fc.current_mode == e1000_fc_full) { |
9d5c8243 AK |
276 | pause->rx_pause = 1; |
277 | pause->tx_pause = 1; | |
278 | } | |
279 | } | |
280 | ||
281 | static int igb_set_pauseparam(struct net_device *netdev, | |
282 | struct ethtool_pauseparam *pause) | |
283 | { | |
284 | struct igb_adapter *adapter = netdev_priv(netdev); | |
285 | struct e1000_hw *hw = &adapter->hw; | |
286 | int retval = 0; | |
287 | ||
288 | adapter->fc_autoneg = pause->autoneg; | |
289 | ||
290 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
291 | msleep(1); | |
292 | ||
9d5c8243 | 293 | if (adapter->fc_autoneg == AUTONEG_ENABLE) { |
0cce119a | 294 | hw->fc.requested_mode = e1000_fc_default; |
9d5c8243 AK |
295 | if (netif_running(adapter->netdev)) { |
296 | igb_down(adapter); | |
297 | igb_up(adapter); | |
317f66bd | 298 | } else { |
9d5c8243 | 299 | igb_reset(adapter); |
317f66bd | 300 | } |
0cce119a AD |
301 | } else { |
302 | if (pause->rx_pause && pause->tx_pause) | |
303 | hw->fc.requested_mode = e1000_fc_full; | |
304 | else if (pause->rx_pause && !pause->tx_pause) | |
305 | hw->fc.requested_mode = e1000_fc_rx_pause; | |
306 | else if (!pause->rx_pause && pause->tx_pause) | |
307 | hw->fc.requested_mode = e1000_fc_tx_pause; | |
308 | else if (!pause->rx_pause && !pause->tx_pause) | |
309 | hw->fc.requested_mode = e1000_fc_none; | |
310 | ||
311 | hw->fc.current_mode = hw->fc.requested_mode; | |
312 | ||
dcc3ae9a AD |
313 | retval = ((hw->phy.media_type == e1000_media_type_copper) ? |
314 | igb_force_mac_fc(hw) : igb_setup_link(hw)); | |
0cce119a | 315 | } |
9d5c8243 AK |
316 | |
317 | clear_bit(__IGB_RESETTING, &adapter->state); | |
318 | return retval; | |
319 | } | |
320 | ||
321 | static u32 igb_get_rx_csum(struct net_device *netdev) | |
322 | { | |
323 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3025a446 | 324 | return !!(adapter->rx_ring[0]->flags & IGB_RING_FLAG_RX_CSUM); |
9d5c8243 AK |
325 | } |
326 | ||
327 | static int igb_set_rx_csum(struct net_device *netdev, u32 data) | |
328 | { | |
329 | struct igb_adapter *adapter = netdev_priv(netdev); | |
85ad76b2 | 330 | int i; |
7beb0146 | 331 | |
85ad76b2 AD |
332 | for (i = 0; i < adapter->num_rx_queues; i++) { |
333 | if (data) | |
3025a446 | 334 | adapter->rx_ring[i]->flags |= IGB_RING_FLAG_RX_CSUM; |
85ad76b2 | 335 | else |
3025a446 | 336 | adapter->rx_ring[i]->flags &= ~IGB_RING_FLAG_RX_CSUM; |
85ad76b2 | 337 | } |
9d5c8243 AK |
338 | |
339 | return 0; | |
340 | } | |
341 | ||
342 | static u32 igb_get_tx_csum(struct net_device *netdev) | |
343 | { | |
7d8eb29e | 344 | return (netdev->features & NETIF_F_IP_CSUM) != 0; |
9d5c8243 AK |
345 | } |
346 | ||
347 | static int igb_set_tx_csum(struct net_device *netdev, u32 data) | |
348 | { | |
b9473560 JB |
349 | struct igb_adapter *adapter = netdev_priv(netdev); |
350 | ||
351 | if (data) { | |
7d8eb29e | 352 | netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); |
317f66bd | 353 | if (adapter->hw.mac.type >= e1000_82576) |
b9473560 JB |
354 | netdev->features |= NETIF_F_SCTP_CSUM; |
355 | } else { | |
356 | netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | |
357 | NETIF_F_SCTP_CSUM); | |
358 | } | |
9d5c8243 AK |
359 | |
360 | return 0; | |
361 | } | |
362 | ||
363 | static int igb_set_tso(struct net_device *netdev, u32 data) | |
364 | { | |
365 | struct igb_adapter *adapter = netdev_priv(netdev); | |
366 | ||
7d8eb29e | 367 | if (data) { |
9d5c8243 | 368 | netdev->features |= NETIF_F_TSO; |
9d5c8243 | 369 | netdev->features |= NETIF_F_TSO6; |
7d8eb29e AD |
370 | } else { |
371 | netdev->features &= ~NETIF_F_TSO; | |
9d5c8243 | 372 | netdev->features &= ~NETIF_F_TSO6; |
7d8eb29e | 373 | } |
9d5c8243 AK |
374 | |
375 | dev_info(&adapter->pdev->dev, "TSO is %s\n", | |
376 | data ? "Enabled" : "Disabled"); | |
377 | return 0; | |
378 | } | |
379 | ||
380 | static u32 igb_get_msglevel(struct net_device *netdev) | |
381 | { | |
382 | struct igb_adapter *adapter = netdev_priv(netdev); | |
383 | return adapter->msg_enable; | |
384 | } | |
385 | ||
386 | static void igb_set_msglevel(struct net_device *netdev, u32 data) | |
387 | { | |
388 | struct igb_adapter *adapter = netdev_priv(netdev); | |
389 | adapter->msg_enable = data; | |
390 | } | |
391 | ||
392 | static int igb_get_regs_len(struct net_device *netdev) | |
393 | { | |
394 | #define IGB_REGS_LEN 551 | |
395 | return IGB_REGS_LEN * sizeof(u32); | |
396 | } | |
397 | ||
398 | static void igb_get_regs(struct net_device *netdev, | |
399 | struct ethtool_regs *regs, void *p) | |
400 | { | |
401 | struct igb_adapter *adapter = netdev_priv(netdev); | |
402 | struct e1000_hw *hw = &adapter->hw; | |
403 | u32 *regs_buff = p; | |
404 | u8 i; | |
405 | ||
406 | memset(p, 0, IGB_REGS_LEN * sizeof(u32)); | |
407 | ||
408 | regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; | |
409 | ||
410 | /* General Registers */ | |
411 | regs_buff[0] = rd32(E1000_CTRL); | |
412 | regs_buff[1] = rd32(E1000_STATUS); | |
413 | regs_buff[2] = rd32(E1000_CTRL_EXT); | |
414 | regs_buff[3] = rd32(E1000_MDIC); | |
415 | regs_buff[4] = rd32(E1000_SCTL); | |
416 | regs_buff[5] = rd32(E1000_CONNSW); | |
417 | regs_buff[6] = rd32(E1000_VET); | |
418 | regs_buff[7] = rd32(E1000_LEDCTL); | |
419 | regs_buff[8] = rd32(E1000_PBA); | |
420 | regs_buff[9] = rd32(E1000_PBS); | |
421 | regs_buff[10] = rd32(E1000_FRTIMER); | |
422 | regs_buff[11] = rd32(E1000_TCPTIMER); | |
423 | ||
424 | /* NVM Register */ | |
425 | regs_buff[12] = rd32(E1000_EECD); | |
426 | ||
427 | /* Interrupt */ | |
fe59de38 AD |
428 | /* Reading EICS for EICR because they read the |
429 | * same but EICS does not clear on read */ | |
430 | regs_buff[13] = rd32(E1000_EICS); | |
9d5c8243 AK |
431 | regs_buff[14] = rd32(E1000_EICS); |
432 | regs_buff[15] = rd32(E1000_EIMS); | |
433 | regs_buff[16] = rd32(E1000_EIMC); | |
434 | regs_buff[17] = rd32(E1000_EIAC); | |
435 | regs_buff[18] = rd32(E1000_EIAM); | |
fe59de38 AD |
436 | /* Reading ICS for ICR because they read the |
437 | * same but ICS does not clear on read */ | |
438 | regs_buff[19] = rd32(E1000_ICS); | |
9d5c8243 AK |
439 | regs_buff[20] = rd32(E1000_ICS); |
440 | regs_buff[21] = rd32(E1000_IMS); | |
441 | regs_buff[22] = rd32(E1000_IMC); | |
442 | regs_buff[23] = rd32(E1000_IAC); | |
443 | regs_buff[24] = rd32(E1000_IAM); | |
444 | regs_buff[25] = rd32(E1000_IMIRVP); | |
445 | ||
446 | /* Flow Control */ | |
447 | regs_buff[26] = rd32(E1000_FCAL); | |
448 | regs_buff[27] = rd32(E1000_FCAH); | |
449 | regs_buff[28] = rd32(E1000_FCTTV); | |
450 | regs_buff[29] = rd32(E1000_FCRTL); | |
451 | regs_buff[30] = rd32(E1000_FCRTH); | |
452 | regs_buff[31] = rd32(E1000_FCRTV); | |
453 | ||
454 | /* Receive */ | |
455 | regs_buff[32] = rd32(E1000_RCTL); | |
456 | regs_buff[33] = rd32(E1000_RXCSUM); | |
457 | regs_buff[34] = rd32(E1000_RLPML); | |
458 | regs_buff[35] = rd32(E1000_RFCTL); | |
459 | regs_buff[36] = rd32(E1000_MRQC); | |
e1739522 | 460 | regs_buff[37] = rd32(E1000_VT_CTL); |
9d5c8243 AK |
461 | |
462 | /* Transmit */ | |
463 | regs_buff[38] = rd32(E1000_TCTL); | |
464 | regs_buff[39] = rd32(E1000_TCTL_EXT); | |
465 | regs_buff[40] = rd32(E1000_TIPG); | |
466 | regs_buff[41] = rd32(E1000_DTXCTL); | |
467 | ||
468 | /* Wake Up */ | |
469 | regs_buff[42] = rd32(E1000_WUC); | |
470 | regs_buff[43] = rd32(E1000_WUFC); | |
471 | regs_buff[44] = rd32(E1000_WUS); | |
472 | regs_buff[45] = rd32(E1000_IPAV); | |
473 | regs_buff[46] = rd32(E1000_WUPL); | |
474 | ||
475 | /* MAC */ | |
476 | regs_buff[47] = rd32(E1000_PCS_CFG0); | |
477 | regs_buff[48] = rd32(E1000_PCS_LCTL); | |
478 | regs_buff[49] = rd32(E1000_PCS_LSTAT); | |
479 | regs_buff[50] = rd32(E1000_PCS_ANADV); | |
480 | regs_buff[51] = rd32(E1000_PCS_LPAB); | |
481 | regs_buff[52] = rd32(E1000_PCS_NPTX); | |
482 | regs_buff[53] = rd32(E1000_PCS_LPABNP); | |
483 | ||
484 | /* Statistics */ | |
485 | regs_buff[54] = adapter->stats.crcerrs; | |
486 | regs_buff[55] = adapter->stats.algnerrc; | |
487 | regs_buff[56] = adapter->stats.symerrs; | |
488 | regs_buff[57] = adapter->stats.rxerrc; | |
489 | regs_buff[58] = adapter->stats.mpc; | |
490 | regs_buff[59] = adapter->stats.scc; | |
491 | regs_buff[60] = adapter->stats.ecol; | |
492 | regs_buff[61] = adapter->stats.mcc; | |
493 | regs_buff[62] = adapter->stats.latecol; | |
494 | regs_buff[63] = adapter->stats.colc; | |
495 | regs_buff[64] = adapter->stats.dc; | |
496 | regs_buff[65] = adapter->stats.tncrs; | |
497 | regs_buff[66] = adapter->stats.sec; | |
498 | regs_buff[67] = adapter->stats.htdpmc; | |
499 | regs_buff[68] = adapter->stats.rlec; | |
500 | regs_buff[69] = adapter->stats.xonrxc; | |
501 | regs_buff[70] = adapter->stats.xontxc; | |
502 | regs_buff[71] = adapter->stats.xoffrxc; | |
503 | regs_buff[72] = adapter->stats.xofftxc; | |
504 | regs_buff[73] = adapter->stats.fcruc; | |
505 | regs_buff[74] = adapter->stats.prc64; | |
506 | regs_buff[75] = adapter->stats.prc127; | |
507 | regs_buff[76] = adapter->stats.prc255; | |
508 | regs_buff[77] = adapter->stats.prc511; | |
509 | regs_buff[78] = adapter->stats.prc1023; | |
510 | regs_buff[79] = adapter->stats.prc1522; | |
511 | regs_buff[80] = adapter->stats.gprc; | |
512 | regs_buff[81] = adapter->stats.bprc; | |
513 | regs_buff[82] = adapter->stats.mprc; | |
514 | regs_buff[83] = adapter->stats.gptc; | |
515 | regs_buff[84] = adapter->stats.gorc; | |
516 | regs_buff[86] = adapter->stats.gotc; | |
517 | regs_buff[88] = adapter->stats.rnbc; | |
518 | regs_buff[89] = adapter->stats.ruc; | |
519 | regs_buff[90] = adapter->stats.rfc; | |
520 | regs_buff[91] = adapter->stats.roc; | |
521 | regs_buff[92] = adapter->stats.rjc; | |
522 | regs_buff[93] = adapter->stats.mgprc; | |
523 | regs_buff[94] = adapter->stats.mgpdc; | |
524 | regs_buff[95] = adapter->stats.mgptc; | |
525 | regs_buff[96] = adapter->stats.tor; | |
526 | regs_buff[98] = adapter->stats.tot; | |
527 | regs_buff[100] = adapter->stats.tpr; | |
528 | regs_buff[101] = adapter->stats.tpt; | |
529 | regs_buff[102] = adapter->stats.ptc64; | |
530 | regs_buff[103] = adapter->stats.ptc127; | |
531 | regs_buff[104] = adapter->stats.ptc255; | |
532 | regs_buff[105] = adapter->stats.ptc511; | |
533 | regs_buff[106] = adapter->stats.ptc1023; | |
534 | regs_buff[107] = adapter->stats.ptc1522; | |
535 | regs_buff[108] = adapter->stats.mptc; | |
536 | regs_buff[109] = adapter->stats.bptc; | |
537 | regs_buff[110] = adapter->stats.tsctc; | |
538 | regs_buff[111] = adapter->stats.iac; | |
539 | regs_buff[112] = adapter->stats.rpthc; | |
540 | regs_buff[113] = adapter->stats.hgptc; | |
541 | regs_buff[114] = adapter->stats.hgorc; | |
542 | regs_buff[116] = adapter->stats.hgotc; | |
543 | regs_buff[118] = adapter->stats.lenerrs; | |
544 | regs_buff[119] = adapter->stats.scvpc; | |
545 | regs_buff[120] = adapter->stats.hrmpc; | |
546 | ||
9d5c8243 AK |
547 | for (i = 0; i < 4; i++) |
548 | regs_buff[121 + i] = rd32(E1000_SRRCTL(i)); | |
549 | for (i = 0; i < 4; i++) | |
83ab50a5 | 550 | regs_buff[125 + i] = rd32(E1000_PSRTYPE(i)); |
9d5c8243 AK |
551 | for (i = 0; i < 4; i++) |
552 | regs_buff[129 + i] = rd32(E1000_RDBAL(i)); | |
553 | for (i = 0; i < 4; i++) | |
554 | regs_buff[133 + i] = rd32(E1000_RDBAH(i)); | |
555 | for (i = 0; i < 4; i++) | |
556 | regs_buff[137 + i] = rd32(E1000_RDLEN(i)); | |
557 | for (i = 0; i < 4; i++) | |
558 | regs_buff[141 + i] = rd32(E1000_RDH(i)); | |
559 | for (i = 0; i < 4; i++) | |
560 | regs_buff[145 + i] = rd32(E1000_RDT(i)); | |
561 | for (i = 0; i < 4; i++) | |
562 | regs_buff[149 + i] = rd32(E1000_RXDCTL(i)); | |
563 | ||
564 | for (i = 0; i < 10; i++) | |
565 | regs_buff[153 + i] = rd32(E1000_EITR(i)); | |
566 | for (i = 0; i < 8; i++) | |
567 | regs_buff[163 + i] = rd32(E1000_IMIR(i)); | |
568 | for (i = 0; i < 8; i++) | |
569 | regs_buff[171 + i] = rd32(E1000_IMIREXT(i)); | |
570 | for (i = 0; i < 16; i++) | |
571 | regs_buff[179 + i] = rd32(E1000_RAL(i)); | |
572 | for (i = 0; i < 16; i++) | |
573 | regs_buff[195 + i] = rd32(E1000_RAH(i)); | |
574 | ||
575 | for (i = 0; i < 4; i++) | |
576 | regs_buff[211 + i] = rd32(E1000_TDBAL(i)); | |
577 | for (i = 0; i < 4; i++) | |
578 | regs_buff[215 + i] = rd32(E1000_TDBAH(i)); | |
579 | for (i = 0; i < 4; i++) | |
580 | regs_buff[219 + i] = rd32(E1000_TDLEN(i)); | |
581 | for (i = 0; i < 4; i++) | |
582 | regs_buff[223 + i] = rd32(E1000_TDH(i)); | |
583 | for (i = 0; i < 4; i++) | |
584 | regs_buff[227 + i] = rd32(E1000_TDT(i)); | |
585 | for (i = 0; i < 4; i++) | |
586 | regs_buff[231 + i] = rd32(E1000_TXDCTL(i)); | |
587 | for (i = 0; i < 4; i++) | |
588 | regs_buff[235 + i] = rd32(E1000_TDWBAL(i)); | |
589 | for (i = 0; i < 4; i++) | |
590 | regs_buff[239 + i] = rd32(E1000_TDWBAH(i)); | |
591 | for (i = 0; i < 4; i++) | |
592 | regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i)); | |
593 | ||
594 | for (i = 0; i < 4; i++) | |
595 | regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i)); | |
596 | for (i = 0; i < 4; i++) | |
597 | regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i)); | |
598 | for (i = 0; i < 32; i++) | |
599 | regs_buff[255 + i] = rd32(E1000_WUPM_REG(i)); | |
600 | for (i = 0; i < 128; i++) | |
601 | regs_buff[287 + i] = rd32(E1000_FFMT_REG(i)); | |
602 | for (i = 0; i < 128; i++) | |
603 | regs_buff[415 + i] = rd32(E1000_FFVT_REG(i)); | |
604 | for (i = 0; i < 4; i++) | |
605 | regs_buff[543 + i] = rd32(E1000_FFLT_REG(i)); | |
606 | ||
607 | regs_buff[547] = rd32(E1000_TDFH); | |
608 | regs_buff[548] = rd32(E1000_TDFT); | |
609 | regs_buff[549] = rd32(E1000_TDFHS); | |
610 | regs_buff[550] = rd32(E1000_TDFPC); | |
0a915b95 CW |
611 | regs_buff[551] = adapter->stats.o2bgptc; |
612 | regs_buff[552] = adapter->stats.b2ospc; | |
613 | regs_buff[553] = adapter->stats.o2bspc; | |
614 | regs_buff[554] = adapter->stats.b2ogprc; | |
9d5c8243 AK |
615 | } |
616 | ||
617 | static int igb_get_eeprom_len(struct net_device *netdev) | |
618 | { | |
619 | struct igb_adapter *adapter = netdev_priv(netdev); | |
620 | return adapter->hw.nvm.word_size * 2; | |
621 | } | |
622 | ||
623 | static int igb_get_eeprom(struct net_device *netdev, | |
624 | struct ethtool_eeprom *eeprom, u8 *bytes) | |
625 | { | |
626 | struct igb_adapter *adapter = netdev_priv(netdev); | |
627 | struct e1000_hw *hw = &adapter->hw; | |
628 | u16 *eeprom_buff; | |
629 | int first_word, last_word; | |
630 | int ret_val = 0; | |
631 | u16 i; | |
632 | ||
633 | if (eeprom->len == 0) | |
634 | return -EINVAL; | |
635 | ||
636 | eeprom->magic = hw->vendor_id | (hw->device_id << 16); | |
637 | ||
638 | first_word = eeprom->offset >> 1; | |
639 | last_word = (eeprom->offset + eeprom->len - 1) >> 1; | |
640 | ||
641 | eeprom_buff = kmalloc(sizeof(u16) * | |
642 | (last_word - first_word + 1), GFP_KERNEL); | |
643 | if (!eeprom_buff) | |
644 | return -ENOMEM; | |
645 | ||
646 | if (hw->nvm.type == e1000_nvm_eeprom_spi) | |
312c75ae | 647 | ret_val = hw->nvm.ops.read(hw, first_word, |
9d5c8243 AK |
648 | last_word - first_word + 1, |
649 | eeprom_buff); | |
650 | else { | |
651 | for (i = 0; i < last_word - first_word + 1; i++) { | |
312c75ae | 652 | ret_val = hw->nvm.ops.read(hw, first_word + i, 1, |
9d5c8243 AK |
653 | &eeprom_buff[i]); |
654 | if (ret_val) | |
655 | break; | |
656 | } | |
657 | } | |
658 | ||
659 | /* Device's eeprom is always little-endian, word addressable */ | |
660 | for (i = 0; i < last_word - first_word + 1; i++) | |
661 | le16_to_cpus(&eeprom_buff[i]); | |
662 | ||
663 | memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), | |
664 | eeprom->len); | |
665 | kfree(eeprom_buff); | |
666 | ||
667 | return ret_val; | |
668 | } | |
669 | ||
670 | static int igb_set_eeprom(struct net_device *netdev, | |
671 | struct ethtool_eeprom *eeprom, u8 *bytes) | |
672 | { | |
673 | struct igb_adapter *adapter = netdev_priv(netdev); | |
674 | struct e1000_hw *hw = &adapter->hw; | |
675 | u16 *eeprom_buff; | |
676 | void *ptr; | |
677 | int max_len, first_word, last_word, ret_val = 0; | |
678 | u16 i; | |
679 | ||
680 | if (eeprom->len == 0) | |
681 | return -EOPNOTSUPP; | |
682 | ||
683 | if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) | |
684 | return -EFAULT; | |
685 | ||
686 | max_len = hw->nvm.word_size * 2; | |
687 | ||
688 | first_word = eeprom->offset >> 1; | |
689 | last_word = (eeprom->offset + eeprom->len - 1) >> 1; | |
690 | eeprom_buff = kmalloc(max_len, GFP_KERNEL); | |
691 | if (!eeprom_buff) | |
692 | return -ENOMEM; | |
693 | ||
694 | ptr = (void *)eeprom_buff; | |
695 | ||
696 | if (eeprom->offset & 1) { | |
697 | /* need read/modify/write of first changed EEPROM word */ | |
698 | /* only the second byte of the word is being modified */ | |
312c75ae | 699 | ret_val = hw->nvm.ops.read(hw, first_word, 1, |
9d5c8243 AK |
700 | &eeprom_buff[0]); |
701 | ptr++; | |
702 | } | |
703 | if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { | |
704 | /* need read/modify/write of last changed EEPROM word */ | |
705 | /* only the first byte of the word is being modified */ | |
312c75ae | 706 | ret_val = hw->nvm.ops.read(hw, last_word, 1, |
9d5c8243 AK |
707 | &eeprom_buff[last_word - first_word]); |
708 | } | |
709 | ||
710 | /* Device's eeprom is always little-endian, word addressable */ | |
711 | for (i = 0; i < last_word - first_word + 1; i++) | |
712 | le16_to_cpus(&eeprom_buff[i]); | |
713 | ||
714 | memcpy(ptr, bytes, eeprom->len); | |
715 | ||
716 | for (i = 0; i < last_word - first_word + 1; i++) | |
717 | eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]); | |
718 | ||
312c75ae | 719 | ret_val = hw->nvm.ops.write(hw, first_word, |
9d5c8243 AK |
720 | last_word - first_word + 1, eeprom_buff); |
721 | ||
722 | /* Update the checksum over the first part of the EEPROM if needed | |
723 | * and flush shadow RAM for 82573 controllers */ | |
724 | if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG))) | |
4322e561 | 725 | hw->nvm.ops.update(hw); |
9d5c8243 AK |
726 | |
727 | kfree(eeprom_buff); | |
728 | return ret_val; | |
729 | } | |
730 | ||
731 | static void igb_get_drvinfo(struct net_device *netdev, | |
732 | struct ethtool_drvinfo *drvinfo) | |
733 | { | |
734 | struct igb_adapter *adapter = netdev_priv(netdev); | |
735 | char firmware_version[32]; | |
736 | u16 eeprom_data; | |
737 | ||
3b668a77 CW |
738 | strncpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver) - 1); |
739 | strncpy(drvinfo->version, igb_driver_version, | |
740 | sizeof(drvinfo->version) - 1); | |
9d5c8243 AK |
741 | |
742 | /* EEPROM image version # is reported as firmware version # for | |
743 | * 82575 controllers */ | |
312c75ae | 744 | adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data); |
9d5c8243 AK |
745 | sprintf(firmware_version, "%d.%d-%d", |
746 | (eeprom_data & 0xF000) >> 12, | |
747 | (eeprom_data & 0x0FF0) >> 4, | |
748 | eeprom_data & 0x000F); | |
749 | ||
3b668a77 CW |
750 | strncpy(drvinfo->fw_version, firmware_version, |
751 | sizeof(drvinfo->fw_version) - 1); | |
752 | strncpy(drvinfo->bus_info, pci_name(adapter->pdev), | |
753 | sizeof(drvinfo->bus_info) - 1); | |
9d5c8243 AK |
754 | drvinfo->n_stats = IGB_STATS_LEN; |
755 | drvinfo->testinfo_len = IGB_TEST_LEN; | |
756 | drvinfo->regdump_len = igb_get_regs_len(netdev); | |
757 | drvinfo->eedump_len = igb_get_eeprom_len(netdev); | |
758 | } | |
759 | ||
760 | static void igb_get_ringparam(struct net_device *netdev, | |
761 | struct ethtool_ringparam *ring) | |
762 | { | |
763 | struct igb_adapter *adapter = netdev_priv(netdev); | |
9d5c8243 AK |
764 | |
765 | ring->rx_max_pending = IGB_MAX_RXD; | |
766 | ring->tx_max_pending = IGB_MAX_TXD; | |
767 | ring->rx_mini_max_pending = 0; | |
768 | ring->rx_jumbo_max_pending = 0; | |
68fd9910 AD |
769 | ring->rx_pending = adapter->rx_ring_count; |
770 | ring->tx_pending = adapter->tx_ring_count; | |
9d5c8243 AK |
771 | ring->rx_mini_pending = 0; |
772 | ring->rx_jumbo_pending = 0; | |
773 | } | |
774 | ||
775 | static int igb_set_ringparam(struct net_device *netdev, | |
776 | struct ethtool_ringparam *ring) | |
777 | { | |
778 | struct igb_adapter *adapter = netdev_priv(netdev); | |
68fd9910 | 779 | struct igb_ring *temp_ring; |
6d9f4fc4 | 780 | int i, err = 0; |
0e15439a | 781 | u16 new_rx_count, new_tx_count; |
9d5c8243 AK |
782 | |
783 | if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) | |
784 | return -EINVAL; | |
785 | ||
0e15439a AD |
786 | new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD); |
787 | new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD); | |
9d5c8243 AK |
788 | new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE); |
789 | ||
0e15439a AD |
790 | new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD); |
791 | new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD); | |
9d5c8243 AK |
792 | new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE); |
793 | ||
68fd9910 AD |
794 | if ((new_tx_count == adapter->tx_ring_count) && |
795 | (new_rx_count == adapter->rx_ring_count)) { | |
9d5c8243 AK |
796 | /* nothing to do */ |
797 | return 0; | |
798 | } | |
799 | ||
6d9f4fc4 AD |
800 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) |
801 | msleep(1); | |
802 | ||
803 | if (!netif_running(adapter->netdev)) { | |
804 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 805 | adapter->tx_ring[i]->count = new_tx_count; |
6d9f4fc4 | 806 | for (i = 0; i < adapter->num_rx_queues; i++) |
3025a446 | 807 | adapter->rx_ring[i]->count = new_rx_count; |
6d9f4fc4 AD |
808 | adapter->tx_ring_count = new_tx_count; |
809 | adapter->rx_ring_count = new_rx_count; | |
810 | goto clear_reset; | |
811 | } | |
812 | ||
68fd9910 AD |
813 | if (adapter->num_tx_queues > adapter->num_rx_queues) |
814 | temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring)); | |
815 | else | |
816 | temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring)); | |
68fd9910 | 817 | |
6d9f4fc4 AD |
818 | if (!temp_ring) { |
819 | err = -ENOMEM; | |
820 | goto clear_reset; | |
821 | } | |
9d5c8243 | 822 | |
6d9f4fc4 | 823 | igb_down(adapter); |
9d5c8243 AK |
824 | |
825 | /* | |
826 | * We can't just free everything and then setup again, | |
827 | * because the ISRs in MSI-X mode get passed pointers | |
828 | * to the tx and rx ring structs. | |
829 | */ | |
68fd9910 | 830 | if (new_tx_count != adapter->tx_ring_count) { |
9d5c8243 | 831 | for (i = 0; i < adapter->num_tx_queues; i++) { |
3025a446 AD |
832 | memcpy(&temp_ring[i], adapter->tx_ring[i], |
833 | sizeof(struct igb_ring)); | |
834 | ||
68fd9910 | 835 | temp_ring[i].count = new_tx_count; |
80785298 | 836 | err = igb_setup_tx_resources(&temp_ring[i]); |
9d5c8243 | 837 | if (err) { |
68fd9910 AD |
838 | while (i) { |
839 | i--; | |
840 | igb_free_tx_resources(&temp_ring[i]); | |
841 | } | |
9d5c8243 AK |
842 | goto err_setup; |
843 | } | |
9d5c8243 | 844 | } |
68fd9910 | 845 | |
3025a446 AD |
846 | for (i = 0; i < adapter->num_tx_queues; i++) { |
847 | igb_free_tx_resources(adapter->tx_ring[i]); | |
68fd9910 | 848 | |
3025a446 AD |
849 | memcpy(adapter->tx_ring[i], &temp_ring[i], |
850 | sizeof(struct igb_ring)); | |
851 | } | |
68fd9910 AD |
852 | |
853 | adapter->tx_ring_count = new_tx_count; | |
9d5c8243 AK |
854 | } |
855 | ||
3025a446 | 856 | if (new_rx_count != adapter->rx_ring_count) { |
68fd9910 | 857 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3025a446 AD |
858 | memcpy(&temp_ring[i], adapter->rx_ring[i], |
859 | sizeof(struct igb_ring)); | |
860 | ||
68fd9910 | 861 | temp_ring[i].count = new_rx_count; |
80785298 | 862 | err = igb_setup_rx_resources(&temp_ring[i]); |
9d5c8243 | 863 | if (err) { |
68fd9910 AD |
864 | while (i) { |
865 | i--; | |
866 | igb_free_rx_resources(&temp_ring[i]); | |
867 | } | |
9d5c8243 AK |
868 | goto err_setup; |
869 | } | |
870 | ||
9d5c8243 | 871 | } |
68fd9910 | 872 | |
3025a446 AD |
873 | for (i = 0; i < adapter->num_rx_queues; i++) { |
874 | igb_free_rx_resources(adapter->rx_ring[i]); | |
68fd9910 | 875 | |
3025a446 AD |
876 | memcpy(adapter->rx_ring[i], &temp_ring[i], |
877 | sizeof(struct igb_ring)); | |
878 | } | |
68fd9910 AD |
879 | |
880 | adapter->rx_ring_count = new_rx_count; | |
9d5c8243 | 881 | } |
9d5c8243 | 882 | err_setup: |
6d9f4fc4 | 883 | igb_up(adapter); |
68fd9910 | 884 | vfree(temp_ring); |
6d9f4fc4 AD |
885 | clear_reset: |
886 | clear_bit(__IGB_RESETTING, &adapter->state); | |
9d5c8243 AK |
887 | return err; |
888 | } | |
889 | ||
890 | /* ethtool register test data */ | |
891 | struct igb_reg_test { | |
892 | u16 reg; | |
2d064c06 AD |
893 | u16 reg_offset; |
894 | u16 array_len; | |
895 | u16 test_type; | |
9d5c8243 AK |
896 | u32 mask; |
897 | u32 write; | |
898 | }; | |
899 | ||
900 | /* In the hardware, registers are laid out either singly, in arrays | |
901 | * spaced 0x100 bytes apart, or in contiguous tables. We assume | |
902 | * most tests take place on arrays or single registers (handled | |
903 | * as a single-element array) and special-case the tables. | |
904 | * Table tests are always pattern tests. | |
905 | * | |
906 | * We also make provision for some required setup steps by specifying | |
907 | * registers to be written without any read-back testing. | |
908 | */ | |
909 | ||
910 | #define PATTERN_TEST 1 | |
911 | #define SET_READ_TEST 2 | |
912 | #define WRITE_NO_TEST 3 | |
913 | #define TABLE32_TEST 4 | |
914 | #define TABLE64_TEST_LO 5 | |
915 | #define TABLE64_TEST_HI 6 | |
916 | ||
d2ba2ed8 AD |
917 | /* i350 reg test */ |
918 | static struct igb_reg_test reg_test_i350[] = { | |
919 | { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
920 | { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
921 | { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
922 | { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 }, | |
923 | { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
924 | { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1b6e6618 | 925 | { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, |
d2ba2ed8 AD |
926 | { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, |
927 | { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1b6e6618 | 928 | { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, |
d2ba2ed8 AD |
929 | /* RDH is read-only for i350, only test RDT. */ |
930 | { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
931 | { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
932 | { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, | |
933 | { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
934 | { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, | |
935 | { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
936 | { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1b6e6618 | 937 | { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, |
d2ba2ed8 AD |
938 | { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, |
939 | { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1b6e6618 | 940 | { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, |
d2ba2ed8 AD |
941 | { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, |
942 | { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
943 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
944 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, | |
945 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, | |
946 | { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
947 | { E1000_RA, 0, 16, TABLE64_TEST_LO, | |
948 | 0xFFFFFFFF, 0xFFFFFFFF }, | |
949 | { E1000_RA, 0, 16, TABLE64_TEST_HI, | |
950 | 0xC3FFFFFF, 0xFFFFFFFF }, | |
951 | { E1000_RA2, 0, 16, TABLE64_TEST_LO, | |
952 | 0xFFFFFFFF, 0xFFFFFFFF }, | |
953 | { E1000_RA2, 0, 16, TABLE64_TEST_HI, | |
954 | 0xC3FFFFFF, 0xFFFFFFFF }, | |
955 | { E1000_MTA, 0, 128, TABLE32_TEST, | |
956 | 0xFFFFFFFF, 0xFFFFFFFF }, | |
957 | { 0, 0, 0, 0 } | |
958 | }; | |
959 | ||
55cac248 AD |
960 | /* 82580 reg test */ |
961 | static struct igb_reg_test reg_test_82580[] = { | |
962 | { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
963 | { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
964 | { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
965 | { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
966 | { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
967 | { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
968 | { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
969 | { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
970 | { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
971 | { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
972 | /* RDH is read-only for 82580, only test RDT. */ | |
973 | { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
974 | { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
975 | { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, | |
976 | { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
977 | { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, | |
978 | { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
979 | { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
980 | { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
981 | { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
982 | { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
983 | { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
984 | { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
985 | { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
986 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
987 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, | |
988 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, | |
989 | { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
990 | { E1000_RA, 0, 16, TABLE64_TEST_LO, | |
991 | 0xFFFFFFFF, 0xFFFFFFFF }, | |
992 | { E1000_RA, 0, 16, TABLE64_TEST_HI, | |
993 | 0x83FFFFFF, 0xFFFFFFFF }, | |
994 | { E1000_RA2, 0, 8, TABLE64_TEST_LO, | |
995 | 0xFFFFFFFF, 0xFFFFFFFF }, | |
996 | { E1000_RA2, 0, 8, TABLE64_TEST_HI, | |
997 | 0x83FFFFFF, 0xFFFFFFFF }, | |
998 | { E1000_MTA, 0, 128, TABLE32_TEST, | |
999 | 0xFFFFFFFF, 0xFFFFFFFF }, | |
1000 | { 0, 0, 0, 0 } | |
1001 | }; | |
1002 | ||
2d064c06 AD |
1003 | /* 82576 reg test */ |
1004 | static struct igb_reg_test reg_test_82576[] = { | |
1005 | { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1006 | { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
1007 | { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
1008 | { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1009 | { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1010 | { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1011 | { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
2753f4ce AD |
1012 | { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, |
1013 | { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1014 | { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
1015 | /* Enable all RX queues before testing. */ | |
1016 | { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, | |
1017 | { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, | |
2d064c06 AD |
1018 | /* RDH is read-only for 82576, only test RDT. */ |
1019 | { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
2753f4ce | 1020 | { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, |
2d064c06 | 1021 | { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, |
2753f4ce | 1022 | { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 }, |
2d064c06 AD |
1023 | { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, |
1024 | { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
1025 | { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, | |
1026 | { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1027 | { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1028 | { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
2753f4ce AD |
1029 | { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, |
1030 | { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1031 | { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, | |
2d064c06 AD |
1032 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, |
1033 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, | |
1034 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, | |
1035 | { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
1036 | { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1037 | { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, | |
1038 | { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1039 | { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, | |
1040 | { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1041 | { 0, 0, 0, 0 } | |
1042 | }; | |
1043 | ||
1044 | /* 82575 register test */ | |
9d5c8243 | 1045 | static struct igb_reg_test reg_test_82575[] = { |
2d064c06 AD |
1046 | { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, |
1047 | { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
1048 | { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, | |
1049 | { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1050 | { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1051 | { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1052 | { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, | |
9d5c8243 | 1053 | /* Enable all four RX queues before testing. */ |
2d064c06 | 1054 | { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, |
9d5c8243 | 1055 | /* RDH is read-only for 82575, only test RDT. */ |
2d064c06 AD |
1056 | { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, |
1057 | { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, | |
1058 | { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, | |
1059 | { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, | |
1060 | { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, | |
1061 | { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, | |
1062 | { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1063 | { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, | |
1064 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
1065 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, | |
1066 | { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, | |
1067 | { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, | |
1068 | { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, | |
1069 | { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, | |
1070 | { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, | |
1071 | { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, | |
9d5c8243 AK |
1072 | { 0, 0, 0, 0 } |
1073 | }; | |
1074 | ||
1075 | static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data, | |
1076 | int reg, u32 mask, u32 write) | |
1077 | { | |
2753f4ce | 1078 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 1079 | u32 pat, val; |
317f66bd | 1080 | static const u32 _test[] = |
9d5c8243 AK |
1081 | {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; |
1082 | for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { | |
2753f4ce | 1083 | wr32(reg, (_test[pat] & write)); |
93ed8359 | 1084 | val = rd32(reg) & mask; |
9d5c8243 AK |
1085 | if (val != (_test[pat] & write & mask)) { |
1086 | dev_err(&adapter->pdev->dev, "pattern test reg %04X " | |
1087 | "failed: got 0x%08X expected 0x%08X\n", | |
1088 | reg, val, (_test[pat] & write & mask)); | |
1089 | *data = reg; | |
1090 | return 1; | |
1091 | } | |
1092 | } | |
317f66bd | 1093 | |
9d5c8243 AK |
1094 | return 0; |
1095 | } | |
1096 | ||
1097 | static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data, | |
1098 | int reg, u32 mask, u32 write) | |
1099 | { | |
2753f4ce | 1100 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 1101 | u32 val; |
2753f4ce AD |
1102 | wr32(reg, write & mask); |
1103 | val = rd32(reg); | |
9d5c8243 AK |
1104 | if ((write & mask) != (val & mask)) { |
1105 | dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:" | |
1106 | " got 0x%08X expected 0x%08X\n", reg, | |
1107 | (val & mask), (write & mask)); | |
1108 | *data = reg; | |
1109 | return 1; | |
1110 | } | |
317f66bd | 1111 | |
9d5c8243 AK |
1112 | return 0; |
1113 | } | |
1114 | ||
1115 | #define REG_PATTERN_TEST(reg, mask, write) \ | |
1116 | do { \ | |
1117 | if (reg_pattern_test(adapter, data, reg, mask, write)) \ | |
1118 | return 1; \ | |
1119 | } while (0) | |
1120 | ||
1121 | #define REG_SET_AND_CHECK(reg, mask, write) \ | |
1122 | do { \ | |
1123 | if (reg_set_and_check(adapter, data, reg, mask, write)) \ | |
1124 | return 1; \ | |
1125 | } while (0) | |
1126 | ||
1127 | static int igb_reg_test(struct igb_adapter *adapter, u64 *data) | |
1128 | { | |
1129 | struct e1000_hw *hw = &adapter->hw; | |
1130 | struct igb_reg_test *test; | |
1131 | u32 value, before, after; | |
1132 | u32 i, toggle; | |
1133 | ||
2d064c06 | 1134 | switch (adapter->hw.mac.type) { |
d2ba2ed8 AD |
1135 | case e1000_i350: |
1136 | test = reg_test_i350; | |
1137 | toggle = 0x7FEFF3FF; | |
1138 | break; | |
55cac248 AD |
1139 | case e1000_82580: |
1140 | test = reg_test_82580; | |
1141 | toggle = 0x7FEFF3FF; | |
1142 | break; | |
2d064c06 AD |
1143 | case e1000_82576: |
1144 | test = reg_test_82576; | |
317f66bd | 1145 | toggle = 0x7FFFF3FF; |
2d064c06 AD |
1146 | break; |
1147 | default: | |
1148 | test = reg_test_82575; | |
317f66bd | 1149 | toggle = 0x7FFFF3FF; |
2d064c06 AD |
1150 | break; |
1151 | } | |
9d5c8243 AK |
1152 | |
1153 | /* Because the status register is such a special case, | |
1154 | * we handle it separately from the rest of the register | |
1155 | * tests. Some bits are read-only, some toggle, and some | |
1156 | * are writable on newer MACs. | |
1157 | */ | |
1158 | before = rd32(E1000_STATUS); | |
1159 | value = (rd32(E1000_STATUS) & toggle); | |
1160 | wr32(E1000_STATUS, toggle); | |
1161 | after = rd32(E1000_STATUS) & toggle; | |
1162 | if (value != after) { | |
1163 | dev_err(&adapter->pdev->dev, "failed STATUS register test " | |
1164 | "got: 0x%08X expected: 0x%08X\n", after, value); | |
1165 | *data = 1; | |
1166 | return 1; | |
1167 | } | |
1168 | /* restore previous status */ | |
1169 | wr32(E1000_STATUS, before); | |
1170 | ||
1171 | /* Perform the remainder of the register test, looping through | |
1172 | * the test table until we either fail or reach the null entry. | |
1173 | */ | |
1174 | while (test->reg) { | |
1175 | for (i = 0; i < test->array_len; i++) { | |
1176 | switch (test->test_type) { | |
1177 | case PATTERN_TEST: | |
2753f4ce AD |
1178 | REG_PATTERN_TEST(test->reg + |
1179 | (i * test->reg_offset), | |
9d5c8243 AK |
1180 | test->mask, |
1181 | test->write); | |
1182 | break; | |
1183 | case SET_READ_TEST: | |
2753f4ce AD |
1184 | REG_SET_AND_CHECK(test->reg + |
1185 | (i * test->reg_offset), | |
9d5c8243 AK |
1186 | test->mask, |
1187 | test->write); | |
1188 | break; | |
1189 | case WRITE_NO_TEST: | |
1190 | writel(test->write, | |
1191 | (adapter->hw.hw_addr + test->reg) | |
2d064c06 | 1192 | + (i * test->reg_offset)); |
9d5c8243 AK |
1193 | break; |
1194 | case TABLE32_TEST: | |
1195 | REG_PATTERN_TEST(test->reg + (i * 4), | |
1196 | test->mask, | |
1197 | test->write); | |
1198 | break; | |
1199 | case TABLE64_TEST_LO: | |
1200 | REG_PATTERN_TEST(test->reg + (i * 8), | |
1201 | test->mask, | |
1202 | test->write); | |
1203 | break; | |
1204 | case TABLE64_TEST_HI: | |
1205 | REG_PATTERN_TEST((test->reg + 4) + (i * 8), | |
1206 | test->mask, | |
1207 | test->write); | |
1208 | break; | |
1209 | } | |
1210 | } | |
1211 | test++; | |
1212 | } | |
1213 | ||
1214 | *data = 0; | |
1215 | return 0; | |
1216 | } | |
1217 | ||
1218 | static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data) | |
1219 | { | |
1220 | u16 temp; | |
1221 | u16 checksum = 0; | |
1222 | u16 i; | |
1223 | ||
1224 | *data = 0; | |
1225 | /* Read and add up the contents of the EEPROM */ | |
1226 | for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { | |
317f66bd | 1227 | if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp)) < 0) { |
9d5c8243 AK |
1228 | *data = 1; |
1229 | break; | |
1230 | } | |
1231 | checksum += temp; | |
1232 | } | |
1233 | ||
1234 | /* If Checksum is not Correct return error else test passed */ | |
1235 | if ((checksum != (u16) NVM_SUM) && !(*data)) | |
1236 | *data = 2; | |
1237 | ||
1238 | return *data; | |
1239 | } | |
1240 | ||
1241 | static irqreturn_t igb_test_intr(int irq, void *data) | |
1242 | { | |
317f66bd | 1243 | struct igb_adapter *adapter = (struct igb_adapter *) data; |
9d5c8243 AK |
1244 | struct e1000_hw *hw = &adapter->hw; |
1245 | ||
1246 | adapter->test_icr |= rd32(E1000_ICR); | |
1247 | ||
1248 | return IRQ_HANDLED; | |
1249 | } | |
1250 | ||
1251 | static int igb_intr_test(struct igb_adapter *adapter, u64 *data) | |
1252 | { | |
1253 | struct e1000_hw *hw = &adapter->hw; | |
1254 | struct net_device *netdev = adapter->netdev; | |
2753f4ce | 1255 | u32 mask, ics_mask, i = 0, shared_int = true; |
9d5c8243 AK |
1256 | u32 irq = adapter->pdev->irq; |
1257 | ||
1258 | *data = 0; | |
1259 | ||
1260 | /* Hook up test interrupt handler just for this test */ | |
4eefa8f0 AD |
1261 | if (adapter->msix_entries) { |
1262 | if (request_irq(adapter->msix_entries[0].vector, | |
a0607fd3 | 1263 | igb_test_intr, 0, netdev->name, adapter)) { |
4eefa8f0 AD |
1264 | *data = 1; |
1265 | return -1; | |
1266 | } | |
4eefa8f0 | 1267 | } else if (adapter->flags & IGB_FLAG_HAS_MSI) { |
9d5c8243 | 1268 | shared_int = false; |
4eefa8f0 | 1269 | if (request_irq(irq, |
a0607fd3 | 1270 | igb_test_intr, 0, netdev->name, adapter)) { |
9d5c8243 AK |
1271 | *data = 1; |
1272 | return -1; | |
1273 | } | |
a0607fd3 | 1274 | } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED, |
4eefa8f0 | 1275 | netdev->name, adapter)) { |
9d5c8243 | 1276 | shared_int = false; |
a0607fd3 | 1277 | } else if (request_irq(irq, igb_test_intr, IRQF_SHARED, |
4eefa8f0 | 1278 | netdev->name, adapter)) { |
9d5c8243 AK |
1279 | *data = 1; |
1280 | return -1; | |
1281 | } | |
1282 | dev_info(&adapter->pdev->dev, "testing %s interrupt\n", | |
1283 | (shared_int ? "shared" : "unshared")); | |
317f66bd | 1284 | |
9d5c8243 | 1285 | /* Disable all the interrupts */ |
4eefa8f0 | 1286 | wr32(E1000_IMC, ~0); |
9d5c8243 AK |
1287 | msleep(10); |
1288 | ||
2753f4ce | 1289 | /* Define all writable bits for ICS */ |
4eefa8f0 | 1290 | switch (hw->mac.type) { |
2753f4ce AD |
1291 | case e1000_82575: |
1292 | ics_mask = 0x37F47EDD; | |
1293 | break; | |
1294 | case e1000_82576: | |
1295 | ics_mask = 0x77D4FBFD; | |
1296 | break; | |
55cac248 AD |
1297 | case e1000_82580: |
1298 | ics_mask = 0x77DCFED5; | |
1299 | break; | |
d2ba2ed8 AD |
1300 | case e1000_i350: |
1301 | ics_mask = 0x77DCFED5; | |
1302 | break; | |
2753f4ce AD |
1303 | default: |
1304 | ics_mask = 0x7FFFFFFF; | |
1305 | break; | |
1306 | } | |
1307 | ||
9d5c8243 | 1308 | /* Test each interrupt */ |
2753f4ce | 1309 | for (; i < 31; i++) { |
9d5c8243 AK |
1310 | /* Interrupt to test */ |
1311 | mask = 1 << i; | |
1312 | ||
2753f4ce AD |
1313 | if (!(mask & ics_mask)) |
1314 | continue; | |
1315 | ||
9d5c8243 AK |
1316 | if (!shared_int) { |
1317 | /* Disable the interrupt to be reported in | |
1318 | * the cause register and then force the same | |
1319 | * interrupt and see if one gets posted. If | |
1320 | * an interrupt was posted to the bus, the | |
1321 | * test failed. | |
1322 | */ | |
1323 | adapter->test_icr = 0; | |
2753f4ce AD |
1324 | |
1325 | /* Flush any pending interrupts */ | |
1326 | wr32(E1000_ICR, ~0); | |
1327 | ||
1328 | wr32(E1000_IMC, mask); | |
1329 | wr32(E1000_ICS, mask); | |
9d5c8243 AK |
1330 | msleep(10); |
1331 | ||
1332 | if (adapter->test_icr & mask) { | |
1333 | *data = 3; | |
1334 | break; | |
1335 | } | |
1336 | } | |
1337 | ||
1338 | /* Enable the interrupt to be reported in | |
1339 | * the cause register and then force the same | |
1340 | * interrupt and see if one gets posted. If | |
1341 | * an interrupt was not posted to the bus, the | |
1342 | * test failed. | |
1343 | */ | |
1344 | adapter->test_icr = 0; | |
2753f4ce AD |
1345 | |
1346 | /* Flush any pending interrupts */ | |
1347 | wr32(E1000_ICR, ~0); | |
1348 | ||
9d5c8243 AK |
1349 | wr32(E1000_IMS, mask); |
1350 | wr32(E1000_ICS, mask); | |
1351 | msleep(10); | |
1352 | ||
1353 | if (!(adapter->test_icr & mask)) { | |
1354 | *data = 4; | |
1355 | break; | |
1356 | } | |
1357 | ||
1358 | if (!shared_int) { | |
1359 | /* Disable the other interrupts to be reported in | |
1360 | * the cause register and then force the other | |
1361 | * interrupts and see if any get posted. If | |
1362 | * an interrupt was posted to the bus, the | |
1363 | * test failed. | |
1364 | */ | |
1365 | adapter->test_icr = 0; | |
2753f4ce AD |
1366 | |
1367 | /* Flush any pending interrupts */ | |
1368 | wr32(E1000_ICR, ~0); | |
1369 | ||
1370 | wr32(E1000_IMC, ~mask); | |
1371 | wr32(E1000_ICS, ~mask); | |
9d5c8243 AK |
1372 | msleep(10); |
1373 | ||
2753f4ce | 1374 | if (adapter->test_icr & mask) { |
9d5c8243 AK |
1375 | *data = 5; |
1376 | break; | |
1377 | } | |
1378 | } | |
1379 | } | |
1380 | ||
1381 | /* Disable all the interrupts */ | |
2753f4ce | 1382 | wr32(E1000_IMC, ~0); |
9d5c8243 AK |
1383 | msleep(10); |
1384 | ||
1385 | /* Unhook test interrupt handler */ | |
4eefa8f0 AD |
1386 | if (adapter->msix_entries) |
1387 | free_irq(adapter->msix_entries[0].vector, adapter); | |
1388 | else | |
1389 | free_irq(irq, adapter); | |
9d5c8243 AK |
1390 | |
1391 | return *data; | |
1392 | } | |
1393 | ||
1394 | static void igb_free_desc_rings(struct igb_adapter *adapter) | |
1395 | { | |
d7ee5b3a AD |
1396 | igb_free_tx_resources(&adapter->test_tx_ring); |
1397 | igb_free_rx_resources(&adapter->test_rx_ring); | |
9d5c8243 AK |
1398 | } |
1399 | ||
1400 | static int igb_setup_desc_rings(struct igb_adapter *adapter) | |
1401 | { | |
9d5c8243 AK |
1402 | struct igb_ring *tx_ring = &adapter->test_tx_ring; |
1403 | struct igb_ring *rx_ring = &adapter->test_rx_ring; | |
d7ee5b3a | 1404 | struct e1000_hw *hw = &adapter->hw; |
ad93d17e | 1405 | int ret_val; |
9d5c8243 AK |
1406 | |
1407 | /* Setup Tx descriptor ring and Tx buffers */ | |
d7ee5b3a | 1408 | tx_ring->count = IGB_DEFAULT_TXD; |
59d71989 | 1409 | tx_ring->dev = &adapter->pdev->dev; |
d7ee5b3a AD |
1410 | tx_ring->netdev = adapter->netdev; |
1411 | tx_ring->reg_idx = adapter->vfs_allocated_count; | |
9d5c8243 | 1412 | |
d7ee5b3a | 1413 | if (igb_setup_tx_resources(tx_ring)) { |
9d5c8243 AK |
1414 | ret_val = 1; |
1415 | goto err_nomem; | |
1416 | } | |
1417 | ||
d7ee5b3a AD |
1418 | igb_setup_tctl(adapter); |
1419 | igb_configure_tx_ring(adapter, tx_ring); | |
9d5c8243 | 1420 | |
9d5c8243 | 1421 | /* Setup Rx descriptor ring and Rx buffers */ |
d7ee5b3a | 1422 | rx_ring->count = IGB_DEFAULT_RXD; |
59d71989 | 1423 | rx_ring->dev = &adapter->pdev->dev; |
d7ee5b3a AD |
1424 | rx_ring->netdev = adapter->netdev; |
1425 | rx_ring->rx_buffer_len = IGB_RXBUFFER_2048; | |
1426 | rx_ring->reg_idx = adapter->vfs_allocated_count; | |
1427 | ||
1428 | if (igb_setup_rx_resources(rx_ring)) { | |
1429 | ret_val = 3; | |
9d5c8243 AK |
1430 | goto err_nomem; |
1431 | } | |
9d5c8243 | 1432 | |
d7ee5b3a AD |
1433 | /* set the default queue to queue 0 of PF */ |
1434 | wr32(E1000_MRQC, adapter->vfs_allocated_count << 3); | |
9d5c8243 | 1435 | |
d7ee5b3a AD |
1436 | /* enable receive ring */ |
1437 | igb_setup_rctl(adapter); | |
1438 | igb_configure_rx_ring(adapter, rx_ring); | |
9d5c8243 | 1439 | |
d7ee5b3a | 1440 | igb_alloc_rx_buffers_adv(rx_ring, igb_desc_unused(rx_ring)); |
9d5c8243 AK |
1441 | |
1442 | return 0; | |
1443 | ||
1444 | err_nomem: | |
1445 | igb_free_desc_rings(adapter); | |
1446 | return ret_val; | |
1447 | } | |
1448 | ||
1449 | static void igb_phy_disable_receiver(struct igb_adapter *adapter) | |
1450 | { | |
1451 | struct e1000_hw *hw = &adapter->hw; | |
1452 | ||
1453 | /* Write out to PHY registers 29 and 30 to disable the Receiver. */ | |
f5f4cf08 AD |
1454 | igb_write_phy_reg(hw, 29, 0x001F); |
1455 | igb_write_phy_reg(hw, 30, 0x8FFC); | |
1456 | igb_write_phy_reg(hw, 29, 0x001A); | |
1457 | igb_write_phy_reg(hw, 30, 0x8FF0); | |
9d5c8243 AK |
1458 | } |
1459 | ||
1460 | static int igb_integrated_phy_loopback(struct igb_adapter *adapter) | |
1461 | { | |
1462 | struct e1000_hw *hw = &adapter->hw; | |
1463 | u32 ctrl_reg = 0; | |
9d5c8243 AK |
1464 | |
1465 | hw->mac.autoneg = false; | |
1466 | ||
1467 | if (hw->phy.type == e1000_phy_m88) { | |
1468 | /* Auto-MDI/MDIX Off */ | |
f5f4cf08 | 1469 | igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); |
9d5c8243 | 1470 | /* reset to update Auto-MDI/MDIX */ |
f5f4cf08 | 1471 | igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); |
9d5c8243 | 1472 | /* autoneg off */ |
f5f4cf08 | 1473 | igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); |
55cac248 AD |
1474 | } else if (hw->phy.type == e1000_phy_82580) { |
1475 | /* enable MII loopback */ | |
1476 | igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041); | |
9d5c8243 AK |
1477 | } |
1478 | ||
1479 | ctrl_reg = rd32(E1000_CTRL); | |
1480 | ||
1481 | /* force 1000, set loopback */ | |
f5f4cf08 | 1482 | igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); |
9d5c8243 AK |
1483 | |
1484 | /* Now set up the MAC to the same speed/duplex as the PHY. */ | |
1485 | ctrl_reg = rd32(E1000_CTRL); | |
1486 | ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ | |
1487 | ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ | |
1488 | E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ | |
1489 | E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ | |
cdfa9f64 AD |
1490 | E1000_CTRL_FD | /* Force Duplex to FULL */ |
1491 | E1000_CTRL_SLU); /* Set link up enable bit */ | |
9d5c8243 | 1492 | |
cdfa9f64 | 1493 | if (hw->phy.type == e1000_phy_m88) |
9d5c8243 | 1494 | ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ |
9d5c8243 AK |
1495 | |
1496 | wr32(E1000_CTRL, ctrl_reg); | |
1497 | ||
1498 | /* Disable the receiver on the PHY so when a cable is plugged in, the | |
1499 | * PHY does not begin to autoneg when a cable is reconnected to the NIC. | |
1500 | */ | |
1501 | if (hw->phy.type == e1000_phy_m88) | |
1502 | igb_phy_disable_receiver(adapter); | |
1503 | ||
1504 | udelay(500); | |
1505 | ||
1506 | return 0; | |
1507 | } | |
1508 | ||
1509 | static int igb_set_phy_loopback(struct igb_adapter *adapter) | |
1510 | { | |
1511 | return igb_integrated_phy_loopback(adapter); | |
1512 | } | |
1513 | ||
1514 | static int igb_setup_loopback_test(struct igb_adapter *adapter) | |
1515 | { | |
1516 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 | 1517 | u32 reg; |
9d5c8243 | 1518 | |
317f66bd AD |
1519 | reg = rd32(E1000_CTRL_EXT); |
1520 | ||
1521 | /* use CTRL_EXT to identify link type as SGMII can appear as copper */ | |
1522 | if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) { | |
2d064c06 AD |
1523 | reg = rd32(E1000_RCTL); |
1524 | reg |= E1000_RCTL_LBM_TCVR; | |
1525 | wr32(E1000_RCTL, reg); | |
1526 | ||
1527 | wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); | |
1528 | ||
1529 | reg = rd32(E1000_CTRL); | |
1530 | reg &= ~(E1000_CTRL_RFCE | | |
1531 | E1000_CTRL_TFCE | | |
1532 | E1000_CTRL_LRST); | |
1533 | reg |= E1000_CTRL_SLU | | |
2753f4ce | 1534 | E1000_CTRL_FD; |
2d064c06 AD |
1535 | wr32(E1000_CTRL, reg); |
1536 | ||
1537 | /* Unset switch control to serdes energy detect */ | |
1538 | reg = rd32(E1000_CONNSW); | |
1539 | reg &= ~E1000_CONNSW_ENRGSRC; | |
1540 | wr32(E1000_CONNSW, reg); | |
1541 | ||
1542 | /* Set PCS register for forced speed */ | |
1543 | reg = rd32(E1000_PCS_LCTL); | |
1544 | reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ | |
1545 | reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ | |
1546 | E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ | |
1547 | E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ | |
1548 | E1000_PCS_LCTL_FSD | /* Force Speed */ | |
1549 | E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ | |
1550 | wr32(E1000_PCS_LCTL, reg); | |
1551 | ||
9d5c8243 | 1552 | return 0; |
9d5c8243 AK |
1553 | } |
1554 | ||
317f66bd | 1555 | return igb_set_phy_loopback(adapter); |
9d5c8243 AK |
1556 | } |
1557 | ||
1558 | static void igb_loopback_cleanup(struct igb_adapter *adapter) | |
1559 | { | |
1560 | struct e1000_hw *hw = &adapter->hw; | |
1561 | u32 rctl; | |
1562 | u16 phy_reg; | |
1563 | ||
1564 | rctl = rd32(E1000_RCTL); | |
1565 | rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); | |
1566 | wr32(E1000_RCTL, rctl); | |
1567 | ||
1568 | hw->mac.autoneg = true; | |
f5f4cf08 | 1569 | igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); |
9d5c8243 AK |
1570 | if (phy_reg & MII_CR_LOOPBACK) { |
1571 | phy_reg &= ~MII_CR_LOOPBACK; | |
f5f4cf08 | 1572 | igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); |
9d5c8243 AK |
1573 | igb_phy_sw_reset(hw); |
1574 | } | |
1575 | } | |
1576 | ||
1577 | static void igb_create_lbtest_frame(struct sk_buff *skb, | |
1578 | unsigned int frame_size) | |
1579 | { | |
1580 | memset(skb->data, 0xFF, frame_size); | |
317f66bd AD |
1581 | frame_size /= 2; |
1582 | memset(&skb->data[frame_size], 0xAA, frame_size - 1); | |
1583 | memset(&skb->data[frame_size + 10], 0xBE, 1); | |
1584 | memset(&skb->data[frame_size + 12], 0xAF, 1); | |
9d5c8243 AK |
1585 | } |
1586 | ||
1587 | static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size) | |
1588 | { | |
317f66bd AD |
1589 | frame_size /= 2; |
1590 | if (*(skb->data + 3) == 0xFF) { | |
1591 | if ((*(skb->data + frame_size + 10) == 0xBE) && | |
1592 | (*(skb->data + frame_size + 12) == 0xAF)) { | |
9d5c8243 | 1593 | return 0; |
317f66bd AD |
1594 | } |
1595 | } | |
9d5c8243 AK |
1596 | return 13; |
1597 | } | |
1598 | ||
ad93d17e AD |
1599 | static int igb_clean_test_rings(struct igb_ring *rx_ring, |
1600 | struct igb_ring *tx_ring, | |
1601 | unsigned int size) | |
1602 | { | |
1603 | union e1000_adv_rx_desc *rx_desc; | |
1604 | struct igb_buffer *buffer_info; | |
1605 | int rx_ntc, tx_ntc, count = 0; | |
1606 | u32 staterr; | |
1607 | ||
1608 | /* initialize next to clean and descriptor values */ | |
1609 | rx_ntc = rx_ring->next_to_clean; | |
1610 | tx_ntc = tx_ring->next_to_clean; | |
1611 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc); | |
1612 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1613 | ||
1614 | while (staterr & E1000_RXD_STAT_DD) { | |
1615 | /* check rx buffer */ | |
1616 | buffer_info = &rx_ring->buffer_info[rx_ntc]; | |
1617 | ||
1618 | /* unmap rx buffer, will be remapped by alloc_rx_buffers */ | |
59d71989 | 1619 | dma_unmap_single(rx_ring->dev, |
ad93d17e AD |
1620 | buffer_info->dma, |
1621 | rx_ring->rx_buffer_len, | |
59d71989 | 1622 | DMA_FROM_DEVICE); |
ad93d17e AD |
1623 | buffer_info->dma = 0; |
1624 | ||
1625 | /* verify contents of skb */ | |
1626 | if (!igb_check_lbtest_frame(buffer_info->skb, size)) | |
1627 | count++; | |
1628 | ||
1629 | /* unmap buffer on tx side */ | |
1630 | buffer_info = &tx_ring->buffer_info[tx_ntc]; | |
1631 | igb_unmap_and_free_tx_resource(tx_ring, buffer_info); | |
1632 | ||
1633 | /* increment rx/tx next to clean counters */ | |
1634 | rx_ntc++; | |
1635 | if (rx_ntc == rx_ring->count) | |
1636 | rx_ntc = 0; | |
1637 | tx_ntc++; | |
1638 | if (tx_ntc == tx_ring->count) | |
1639 | tx_ntc = 0; | |
1640 | ||
1641 | /* fetch next descriptor */ | |
1642 | rx_desc = E1000_RX_DESC_ADV(*rx_ring, rx_ntc); | |
1643 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1644 | } | |
1645 | ||
1646 | /* re-map buffers to ring, store next to clean values */ | |
1647 | igb_alloc_rx_buffers_adv(rx_ring, count); | |
1648 | rx_ring->next_to_clean = rx_ntc; | |
1649 | tx_ring->next_to_clean = tx_ntc; | |
1650 | ||
1651 | return count; | |
1652 | } | |
1653 | ||
9d5c8243 AK |
1654 | static int igb_run_loopback_test(struct igb_adapter *adapter) |
1655 | { | |
9d5c8243 AK |
1656 | struct igb_ring *tx_ring = &adapter->test_tx_ring; |
1657 | struct igb_ring *rx_ring = &adapter->test_rx_ring; | |
ad93d17e AD |
1658 | int i, j, lc, good_cnt, ret_val = 0; |
1659 | unsigned int size = 1024; | |
1660 | netdev_tx_t tx_ret_val; | |
1661 | struct sk_buff *skb; | |
1662 | ||
1663 | /* allocate test skb */ | |
1664 | skb = alloc_skb(size, GFP_KERNEL); | |
1665 | if (!skb) | |
1666 | return 11; | |
9d5c8243 | 1667 | |
ad93d17e AD |
1668 | /* place data into test skb */ |
1669 | igb_create_lbtest_frame(skb, size); | |
1670 | skb_put(skb, size); | |
9d5c8243 | 1671 | |
317f66bd AD |
1672 | /* |
1673 | * Calculate the loop count based on the largest descriptor ring | |
9d5c8243 AK |
1674 | * The idea is to wrap the largest ring a number of times using 64 |
1675 | * send/receive pairs during each loop | |
1676 | */ | |
1677 | ||
1678 | if (rx_ring->count <= tx_ring->count) | |
1679 | lc = ((tx_ring->count / 64) * 2) + 1; | |
1680 | else | |
1681 | lc = ((rx_ring->count / 64) * 2) + 1; | |
1682 | ||
9d5c8243 | 1683 | for (j = 0; j <= lc; j++) { /* loop count loop */ |
ad93d17e | 1684 | /* reset count of good packets */ |
9d5c8243 | 1685 | good_cnt = 0; |
ad93d17e AD |
1686 | |
1687 | /* place 64 packets on the transmit queue*/ | |
1688 | for (i = 0; i < 64; i++) { | |
1689 | skb_get(skb); | |
1690 | tx_ret_val = igb_xmit_frame_ring_adv(skb, tx_ring); | |
1691 | if (tx_ret_val == NETDEV_TX_OK) | |
9d5c8243 | 1692 | good_cnt++; |
ad93d17e AD |
1693 | } |
1694 | ||
9d5c8243 | 1695 | if (good_cnt != 64) { |
ad93d17e | 1696 | ret_val = 12; |
9d5c8243 AK |
1697 | break; |
1698 | } | |
ad93d17e AD |
1699 | |
1700 | /* allow 200 milliseconds for packets to go from tx to rx */ | |
1701 | msleep(200); | |
1702 | ||
1703 | good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size); | |
1704 | if (good_cnt != 64) { | |
1705 | ret_val = 13; | |
9d5c8243 AK |
1706 | break; |
1707 | } | |
1708 | } /* end loop count loop */ | |
ad93d17e AD |
1709 | |
1710 | /* free the original skb */ | |
1711 | kfree_skb(skb); | |
1712 | ||
9d5c8243 AK |
1713 | return ret_val; |
1714 | } | |
1715 | ||
1716 | static int igb_loopback_test(struct igb_adapter *adapter, u64 *data) | |
1717 | { | |
1718 | /* PHY loopback cannot be performed if SoL/IDER | |
1719 | * sessions are active */ | |
1720 | if (igb_check_reset_block(&adapter->hw)) { | |
1721 | dev_err(&adapter->pdev->dev, | |
1722 | "Cannot do PHY loopback test " | |
1723 | "when SoL/IDER is active.\n"); | |
1724 | *data = 0; | |
1725 | goto out; | |
1726 | } | |
1727 | *data = igb_setup_desc_rings(adapter); | |
1728 | if (*data) | |
1729 | goto out; | |
1730 | *data = igb_setup_loopback_test(adapter); | |
1731 | if (*data) | |
1732 | goto err_loopback; | |
1733 | *data = igb_run_loopback_test(adapter); | |
1734 | igb_loopback_cleanup(adapter); | |
1735 | ||
1736 | err_loopback: | |
1737 | igb_free_desc_rings(adapter); | |
1738 | out: | |
1739 | return *data; | |
1740 | } | |
1741 | ||
1742 | static int igb_link_test(struct igb_adapter *adapter, u64 *data) | |
1743 | { | |
1744 | struct e1000_hw *hw = &adapter->hw; | |
1745 | *data = 0; | |
1746 | if (hw->phy.media_type == e1000_media_type_internal_serdes) { | |
1747 | int i = 0; | |
1748 | hw->mac.serdes_has_link = false; | |
1749 | ||
1750 | /* On some blade server designs, link establishment | |
1751 | * could take as long as 2-3 minutes */ | |
1752 | do { | |
1753 | hw->mac.ops.check_for_link(&adapter->hw); | |
1754 | if (hw->mac.serdes_has_link) | |
1755 | return *data; | |
1756 | msleep(20); | |
1757 | } while (i++ < 3750); | |
1758 | ||
1759 | *data = 1; | |
1760 | } else { | |
1761 | hw->mac.ops.check_for_link(&adapter->hw); | |
1762 | if (hw->mac.autoneg) | |
1763 | msleep(4000); | |
1764 | ||
317f66bd | 1765 | if (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) |
9d5c8243 AK |
1766 | *data = 1; |
1767 | } | |
1768 | return *data; | |
1769 | } | |
1770 | ||
1771 | static void igb_diag_test(struct net_device *netdev, | |
1772 | struct ethtool_test *eth_test, u64 *data) | |
1773 | { | |
1774 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1775 | u16 autoneg_advertised; | |
1776 | u8 forced_speed_duplex, autoneg; | |
1777 | bool if_running = netif_running(netdev); | |
1778 | ||
1779 | set_bit(__IGB_TESTING, &adapter->state); | |
1780 | if (eth_test->flags == ETH_TEST_FL_OFFLINE) { | |
1781 | /* Offline tests */ | |
1782 | ||
1783 | /* save speed, duplex, autoneg settings */ | |
1784 | autoneg_advertised = adapter->hw.phy.autoneg_advertised; | |
1785 | forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; | |
1786 | autoneg = adapter->hw.mac.autoneg; | |
1787 | ||
1788 | dev_info(&adapter->pdev->dev, "offline testing starting\n"); | |
1789 | ||
88a268c1 NN |
1790 | /* power up link for link test */ |
1791 | igb_power_up_link(adapter); | |
1792 | ||
9d5c8243 AK |
1793 | /* Link test performed before hardware reset so autoneg doesn't |
1794 | * interfere with test result */ | |
1795 | if (igb_link_test(adapter, &data[4])) | |
1796 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1797 | ||
1798 | if (if_running) | |
1799 | /* indicate we're in test mode */ | |
1800 | dev_close(netdev); | |
1801 | else | |
1802 | igb_reset(adapter); | |
1803 | ||
1804 | if (igb_reg_test(adapter, &data[0])) | |
1805 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1806 | ||
1807 | igb_reset(adapter); | |
1808 | if (igb_eeprom_test(adapter, &data[1])) | |
1809 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1810 | ||
1811 | igb_reset(adapter); | |
1812 | if (igb_intr_test(adapter, &data[2])) | |
1813 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1814 | ||
1815 | igb_reset(adapter); | |
88a268c1 NN |
1816 | /* power up link for loopback test */ |
1817 | igb_power_up_link(adapter); | |
9d5c8243 AK |
1818 | if (igb_loopback_test(adapter, &data[3])) |
1819 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1820 | ||
1821 | /* restore speed, duplex, autoneg settings */ | |
1822 | adapter->hw.phy.autoneg_advertised = autoneg_advertised; | |
1823 | adapter->hw.mac.forced_speed_duplex = forced_speed_duplex; | |
1824 | adapter->hw.mac.autoneg = autoneg; | |
1825 | ||
1826 | /* force this routine to wait until autoneg complete/timeout */ | |
1827 | adapter->hw.phy.autoneg_wait_to_complete = true; | |
1828 | igb_reset(adapter); | |
1829 | adapter->hw.phy.autoneg_wait_to_complete = false; | |
1830 | ||
1831 | clear_bit(__IGB_TESTING, &adapter->state); | |
1832 | if (if_running) | |
1833 | dev_open(netdev); | |
1834 | } else { | |
1835 | dev_info(&adapter->pdev->dev, "online testing starting\n"); | |
88a268c1 NN |
1836 | |
1837 | /* PHY is powered down when interface is down */ | |
8d420a1b AD |
1838 | if (if_running && igb_link_test(adapter, &data[4])) |
1839 | eth_test->flags |= ETH_TEST_FL_FAILED; | |
1840 | else | |
88a268c1 | 1841 | data[4] = 0; |
9d5c8243 AK |
1842 | |
1843 | /* Online tests aren't run; pass by default */ | |
1844 | data[0] = 0; | |
1845 | data[1] = 0; | |
1846 | data[2] = 0; | |
1847 | data[3] = 0; | |
1848 | ||
1849 | clear_bit(__IGB_TESTING, &adapter->state); | |
1850 | } | |
1851 | msleep_interruptible(4 * 1000); | |
1852 | } | |
1853 | ||
1854 | static int igb_wol_exclusion(struct igb_adapter *adapter, | |
1855 | struct ethtool_wolinfo *wol) | |
1856 | { | |
1857 | struct e1000_hw *hw = &adapter->hw; | |
1858 | int retval = 1; /* fail by default */ | |
1859 | ||
1860 | switch (hw->device_id) { | |
1861 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
1862 | /* WoL not supported */ | |
1863 | wol->supported = 0; | |
1864 | break; | |
1865 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
2d064c06 AD |
1866 | case E1000_DEV_ID_82576_FIBER: |
1867 | case E1000_DEV_ID_82576_SERDES: | |
9d5c8243 AK |
1868 | /* Wake events not supported on port B */ |
1869 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) { | |
1870 | wol->supported = 0; | |
1871 | break; | |
1872 | } | |
7dfc16fa AD |
1873 | /* return success for non excluded adapter ports */ |
1874 | retval = 0; | |
1875 | break; | |
c8ea5ea9 | 1876 | case E1000_DEV_ID_82576_QUAD_COPPER: |
d5aa2252 | 1877 | case E1000_DEV_ID_82576_QUAD_COPPER_ET2: |
c8ea5ea9 AD |
1878 | /* quad port adapters only support WoL on port A */ |
1879 | if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) { | |
1880 | wol->supported = 0; | |
1881 | break; | |
1882 | } | |
1883 | /* return success for non excluded adapter ports */ | |
1884 | retval = 0; | |
1885 | break; | |
9d5c8243 AK |
1886 | default: |
1887 | /* dual port cards only support WoL on port A from now on | |
1888 | * unless it was enabled in the eeprom for port B | |
1889 | * so exclude FUNC_1 ports from having WoL enabled */ | |
58b8b042 | 1890 | if ((rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) && |
9d5c8243 AK |
1891 | !adapter->eeprom_wol) { |
1892 | wol->supported = 0; | |
1893 | break; | |
1894 | } | |
1895 | ||
1896 | retval = 0; | |
1897 | } | |
1898 | ||
1899 | return retval; | |
1900 | } | |
1901 | ||
1902 | static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | |
1903 | { | |
1904 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1905 | ||
1906 | wol->supported = WAKE_UCAST | WAKE_MCAST | | |
22939f06 NN |
1907 | WAKE_BCAST | WAKE_MAGIC | |
1908 | WAKE_PHY; | |
9d5c8243 AK |
1909 | wol->wolopts = 0; |
1910 | ||
1911 | /* this function will set ->supported = 0 and return 1 if wol is not | |
1912 | * supported by this hardware */ | |
e1b86d84 RW |
1913 | if (igb_wol_exclusion(adapter, wol) || |
1914 | !device_can_wakeup(&adapter->pdev->dev)) | |
9d5c8243 AK |
1915 | return; |
1916 | ||
1917 | /* apply any specific unsupported masks here */ | |
1918 | switch (adapter->hw.device_id) { | |
1919 | default: | |
1920 | break; | |
1921 | } | |
1922 | ||
1923 | if (adapter->wol & E1000_WUFC_EX) | |
1924 | wol->wolopts |= WAKE_UCAST; | |
1925 | if (adapter->wol & E1000_WUFC_MC) | |
1926 | wol->wolopts |= WAKE_MCAST; | |
1927 | if (adapter->wol & E1000_WUFC_BC) | |
1928 | wol->wolopts |= WAKE_BCAST; | |
1929 | if (adapter->wol & E1000_WUFC_MAG) | |
1930 | wol->wolopts |= WAKE_MAGIC; | |
22939f06 NN |
1931 | if (adapter->wol & E1000_WUFC_LNKC) |
1932 | wol->wolopts |= WAKE_PHY; | |
9d5c8243 AK |
1933 | } |
1934 | ||
1935 | static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | |
1936 | { | |
1937 | struct igb_adapter *adapter = netdev_priv(netdev); | |
9d5c8243 | 1938 | |
22939f06 | 1939 | if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) |
9d5c8243 AK |
1940 | return -EOPNOTSUPP; |
1941 | ||
e1b86d84 RW |
1942 | if (igb_wol_exclusion(adapter, wol) || |
1943 | !device_can_wakeup(&adapter->pdev->dev)) | |
9d5c8243 AK |
1944 | return wol->wolopts ? -EOPNOTSUPP : 0; |
1945 | ||
9d5c8243 AK |
1946 | /* these settings will always override what we currently have */ |
1947 | adapter->wol = 0; | |
1948 | ||
1949 | if (wol->wolopts & WAKE_UCAST) | |
1950 | adapter->wol |= E1000_WUFC_EX; | |
1951 | if (wol->wolopts & WAKE_MCAST) | |
1952 | adapter->wol |= E1000_WUFC_MC; | |
1953 | if (wol->wolopts & WAKE_BCAST) | |
1954 | adapter->wol |= E1000_WUFC_BC; | |
1955 | if (wol->wolopts & WAKE_MAGIC) | |
1956 | adapter->wol |= E1000_WUFC_MAG; | |
22939f06 NN |
1957 | if (wol->wolopts & WAKE_PHY) |
1958 | adapter->wol |= E1000_WUFC_LNKC; | |
e1b86d84 RW |
1959 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
1960 | ||
9d5c8243 AK |
1961 | return 0; |
1962 | } | |
1963 | ||
9d5c8243 AK |
1964 | /* bit defines for adapter->led_status */ |
1965 | #define IGB_LED_ON 0 | |
1966 | ||
1967 | static int igb_phys_id(struct net_device *netdev, u32 data) | |
1968 | { | |
1969 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1970 | struct e1000_hw *hw = &adapter->hw; | |
317f66bd | 1971 | unsigned long timeout; |
9d5c8243 | 1972 | |
317f66bd AD |
1973 | timeout = data * 1000; |
1974 | ||
1975 | /* | |
1976 | * msleep_interruptable only accepts unsigned int so we are limited | |
1977 | * in how long a duration we can wait | |
1978 | */ | |
1979 | if (!timeout || timeout > UINT_MAX) | |
1980 | timeout = UINT_MAX; | |
9d5c8243 AK |
1981 | |
1982 | igb_blink_led(hw); | |
317f66bd | 1983 | msleep_interruptible(timeout); |
9d5c8243 AK |
1984 | |
1985 | igb_led_off(hw); | |
1986 | clear_bit(IGB_LED_ON, &adapter->led_status); | |
1987 | igb_cleanup_led(hw); | |
1988 | ||
1989 | return 0; | |
1990 | } | |
1991 | ||
1992 | static int igb_set_coalesce(struct net_device *netdev, | |
1993 | struct ethtool_coalesce *ec) | |
1994 | { | |
1995 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6eb5a7f1 | 1996 | int i; |
9d5c8243 AK |
1997 | |
1998 | if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) || | |
1999 | ((ec->rx_coalesce_usecs > 3) && | |
2000 | (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) || | |
2001 | (ec->rx_coalesce_usecs == 2)) | |
2002 | return -EINVAL; | |
2003 | ||
4fc82adf AD |
2004 | if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) || |
2005 | ((ec->tx_coalesce_usecs > 3) && | |
2006 | (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) || | |
2007 | (ec->tx_coalesce_usecs == 2)) | |
2008 | return -EINVAL; | |
2009 | ||
2010 | if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs) | |
2011 | return -EINVAL; | |
2012 | ||
831ec0b4 CW |
2013 | /* If ITR is disabled, disable DMAC */ |
2014 | if (ec->rx_coalesce_usecs == 0) { | |
2015 | if (adapter->flags & IGB_FLAG_DMAC) | |
2016 | adapter->flags &= ~IGB_FLAG_DMAC; | |
2017 | } | |
2018 | ||
9d5c8243 | 2019 | /* convert to rate of irq's per second */ |
4fc82adf AD |
2020 | if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) |
2021 | adapter->rx_itr_setting = ec->rx_coalesce_usecs; | |
2022 | else | |
2023 | adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; | |
2024 | ||
2025 | /* convert to rate of irq's per second */ | |
2026 | if (adapter->flags & IGB_FLAG_QUEUE_PAIRS) | |
2027 | adapter->tx_itr_setting = adapter->rx_itr_setting; | |
2028 | else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3) | |
2029 | adapter->tx_itr_setting = ec->tx_coalesce_usecs; | |
2030 | else | |
2031 | adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; | |
9d5c8243 | 2032 | |
047e0030 AD |
2033 | for (i = 0; i < adapter->num_q_vectors; i++) { |
2034 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
4fc82adf AD |
2035 | if (q_vector->rx_ring) |
2036 | q_vector->itr_val = adapter->rx_itr_setting; | |
2037 | else | |
2038 | q_vector->itr_val = adapter->tx_itr_setting; | |
2039 | if (q_vector->itr_val && q_vector->itr_val <= 3) | |
2040 | q_vector->itr_val = IGB_START_ITR; | |
047e0030 AD |
2041 | q_vector->set_itr = 1; |
2042 | } | |
9d5c8243 AK |
2043 | |
2044 | return 0; | |
2045 | } | |
2046 | ||
2047 | static int igb_get_coalesce(struct net_device *netdev, | |
2048 | struct ethtool_coalesce *ec) | |
2049 | { | |
2050 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2051 | ||
4fc82adf AD |
2052 | if (adapter->rx_itr_setting <= 3) |
2053 | ec->rx_coalesce_usecs = adapter->rx_itr_setting; | |
9d5c8243 | 2054 | else |
4fc82adf AD |
2055 | ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; |
2056 | ||
2057 | if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) { | |
2058 | if (adapter->tx_itr_setting <= 3) | |
2059 | ec->tx_coalesce_usecs = adapter->tx_itr_setting; | |
2060 | else | |
2061 | ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; | |
2062 | } | |
9d5c8243 AK |
2063 | |
2064 | return 0; | |
2065 | } | |
2066 | ||
9d5c8243 AK |
2067 | static int igb_nway_reset(struct net_device *netdev) |
2068 | { | |
2069 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2070 | if (netif_running(netdev)) | |
2071 | igb_reinit_locked(adapter); | |
2072 | return 0; | |
2073 | } | |
2074 | ||
2075 | static int igb_get_sset_count(struct net_device *netdev, int sset) | |
2076 | { | |
2077 | switch (sset) { | |
2078 | case ETH_SS_STATS: | |
2079 | return IGB_STATS_LEN; | |
2080 | case ETH_SS_TEST: | |
2081 | return IGB_TEST_LEN; | |
2082 | default: | |
2083 | return -ENOTSUPP; | |
2084 | } | |
2085 | } | |
2086 | ||
2087 | static void igb_get_ethtool_stats(struct net_device *netdev, | |
2088 | struct ethtool_stats *stats, u64 *data) | |
2089 | { | |
2090 | struct igb_adapter *adapter = netdev_priv(netdev); | |
12dcd86b ED |
2091 | struct rtnl_link_stats64 *net_stats = &adapter->stats64; |
2092 | unsigned int start; | |
2093 | struct igb_ring *ring; | |
2094 | int i, j; | |
128e45eb | 2095 | char *p; |
9d5c8243 | 2096 | |
12dcd86b ED |
2097 | spin_lock(&adapter->stats64_lock); |
2098 | igb_update_stats(adapter, net_stats); | |
317f66bd | 2099 | |
9d5c8243 | 2100 | for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { |
128e45eb | 2101 | p = (char *)adapter + igb_gstrings_stats[i].stat_offset; |
9d5c8243 AK |
2102 | data[i] = (igb_gstrings_stats[i].sizeof_stat == |
2103 | sizeof(u64)) ? *(u64 *)p : *(u32 *)p; | |
2104 | } | |
128e45eb AD |
2105 | for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) { |
2106 | p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset; | |
2107 | data[i] = (igb_gstrings_net_stats[j].sizeof_stat == | |
2108 | sizeof(u64)) ? *(u64 *)p : *(u32 *)p; | |
2109 | } | |
e21ed353 | 2110 | for (j = 0; j < adapter->num_tx_queues; j++) { |
12dcd86b ED |
2111 | u64 restart2; |
2112 | ||
2113 | ring = adapter->tx_ring[j]; | |
2114 | do { | |
2115 | start = u64_stats_fetch_begin_bh(&ring->tx_syncp); | |
2116 | data[i] = ring->tx_stats.packets; | |
2117 | data[i+1] = ring->tx_stats.bytes; | |
2118 | data[i+2] = ring->tx_stats.restart_queue; | |
2119 | } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); | |
2120 | do { | |
2121 | start = u64_stats_fetch_begin_bh(&ring->tx_syncp2); | |
2122 | restart2 = ring->tx_stats.restart_queue2; | |
2123 | } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start)); | |
2124 | data[i+2] += restart2; | |
2125 | ||
2126 | i += IGB_TX_QUEUE_STATS_LEN; | |
e21ed353 | 2127 | } |
9d5c8243 | 2128 | for (j = 0; j < adapter->num_rx_queues; j++) { |
12dcd86b ED |
2129 | ring = adapter->rx_ring[j]; |
2130 | do { | |
2131 | start = u64_stats_fetch_begin_bh(&ring->rx_syncp); | |
2132 | data[i] = ring->rx_stats.packets; | |
2133 | data[i+1] = ring->rx_stats.bytes; | |
2134 | data[i+2] = ring->rx_stats.drops; | |
2135 | data[i+3] = ring->rx_stats.csum_err; | |
2136 | data[i+4] = ring->rx_stats.alloc_failed; | |
2137 | } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); | |
2138 | i += IGB_RX_QUEUE_STATS_LEN; | |
9d5c8243 | 2139 | } |
12dcd86b | 2140 | spin_unlock(&adapter->stats64_lock); |
9d5c8243 AK |
2141 | } |
2142 | ||
2143 | static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data) | |
2144 | { | |
2145 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2146 | u8 *p = data; | |
2147 | int i; | |
2148 | ||
2149 | switch (stringset) { | |
2150 | case ETH_SS_TEST: | |
2151 | memcpy(data, *igb_gstrings_test, | |
2152 | IGB_TEST_LEN*ETH_GSTRING_LEN); | |
2153 | break; | |
2154 | case ETH_SS_STATS: | |
2155 | for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { | |
2156 | memcpy(p, igb_gstrings_stats[i].stat_string, | |
2157 | ETH_GSTRING_LEN); | |
2158 | p += ETH_GSTRING_LEN; | |
2159 | } | |
128e45eb AD |
2160 | for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) { |
2161 | memcpy(p, igb_gstrings_net_stats[i].stat_string, | |
2162 | ETH_GSTRING_LEN); | |
2163 | p += ETH_GSTRING_LEN; | |
2164 | } | |
9d5c8243 AK |
2165 | for (i = 0; i < adapter->num_tx_queues; i++) { |
2166 | sprintf(p, "tx_queue_%u_packets", i); | |
2167 | p += ETH_GSTRING_LEN; | |
2168 | sprintf(p, "tx_queue_%u_bytes", i); | |
2169 | p += ETH_GSTRING_LEN; | |
04a5fcaa AD |
2170 | sprintf(p, "tx_queue_%u_restart", i); |
2171 | p += ETH_GSTRING_LEN; | |
9d5c8243 AK |
2172 | } |
2173 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2174 | sprintf(p, "rx_queue_%u_packets", i); | |
2175 | p += ETH_GSTRING_LEN; | |
2176 | sprintf(p, "rx_queue_%u_bytes", i); | |
2177 | p += ETH_GSTRING_LEN; | |
8c0ab70a JDB |
2178 | sprintf(p, "rx_queue_%u_drops", i); |
2179 | p += ETH_GSTRING_LEN; | |
04a5fcaa AD |
2180 | sprintf(p, "rx_queue_%u_csum_err", i); |
2181 | p += ETH_GSTRING_LEN; | |
2182 | sprintf(p, "rx_queue_%u_alloc_failed", i); | |
2183 | p += ETH_GSTRING_LEN; | |
9d5c8243 AK |
2184 | } |
2185 | /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */ | |
2186 | break; | |
2187 | } | |
2188 | } | |
2189 | ||
0fc0b732 | 2190 | static const struct ethtool_ops igb_ethtool_ops = { |
9d5c8243 AK |
2191 | .get_settings = igb_get_settings, |
2192 | .set_settings = igb_set_settings, | |
2193 | .get_drvinfo = igb_get_drvinfo, | |
2194 | .get_regs_len = igb_get_regs_len, | |
2195 | .get_regs = igb_get_regs, | |
2196 | .get_wol = igb_get_wol, | |
2197 | .set_wol = igb_set_wol, | |
2198 | .get_msglevel = igb_get_msglevel, | |
2199 | .set_msglevel = igb_set_msglevel, | |
2200 | .nway_reset = igb_nway_reset, | |
3145535a | 2201 | .get_link = igb_get_link, |
9d5c8243 AK |
2202 | .get_eeprom_len = igb_get_eeprom_len, |
2203 | .get_eeprom = igb_get_eeprom, | |
2204 | .set_eeprom = igb_set_eeprom, | |
2205 | .get_ringparam = igb_get_ringparam, | |
2206 | .set_ringparam = igb_set_ringparam, | |
2207 | .get_pauseparam = igb_get_pauseparam, | |
2208 | .set_pauseparam = igb_set_pauseparam, | |
2209 | .get_rx_csum = igb_get_rx_csum, | |
2210 | .set_rx_csum = igb_set_rx_csum, | |
2211 | .get_tx_csum = igb_get_tx_csum, | |
2212 | .set_tx_csum = igb_set_tx_csum, | |
2213 | .get_sg = ethtool_op_get_sg, | |
2214 | .set_sg = ethtool_op_set_sg, | |
2215 | .get_tso = ethtool_op_get_tso, | |
2216 | .set_tso = igb_set_tso, | |
2217 | .self_test = igb_diag_test, | |
2218 | .get_strings = igb_get_strings, | |
2219 | .phys_id = igb_phys_id, | |
2220 | .get_sset_count = igb_get_sset_count, | |
2221 | .get_ethtool_stats = igb_get_ethtool_stats, | |
2222 | .get_coalesce = igb_get_coalesce, | |
2223 | .set_coalesce = igb_set_coalesce, | |
2224 | }; | |
2225 | ||
2226 | void igb_set_ethtool_ops(struct net_device *netdev) | |
2227 | { | |
2228 | SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops); | |
2229 | } |