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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | ||
29 | /* Linux PRO/1000 Ethernet Driver main header file */ | |
30 | ||
31 | #ifndef _IGB_H_ | |
32 | #define _IGB_H_ | |
33 | ||
34 | #include "e1000_mac.h" | |
35 | #include "e1000_82575.h" | |
36 | ||
38c845c7 | 37 | #include <linux/clocksource.h> |
33af6bcc PO |
38 | #include <linux/timecompare.h> |
39 | #include <linux/net_tstamp.h> | |
38c845c7 | 40 | |
9d5c8243 AK |
41 | struct igb_adapter; |
42 | ||
6eb5a7f1 AD |
43 | /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */ |
44 | #define IGB_START_ITR 648 | |
9d5c8243 | 45 | |
9d5c8243 AK |
46 | /* TX/RX descriptor defines */ |
47 | #define IGB_DEFAULT_TXD 256 | |
48 | #define IGB_MIN_TXD 80 | |
49 | #define IGB_MAX_TXD 4096 | |
50 | ||
51 | #define IGB_DEFAULT_RXD 256 | |
52 | #define IGB_MIN_RXD 80 | |
53 | #define IGB_MAX_RXD 4096 | |
54 | ||
55 | #define IGB_DEFAULT_ITR 3 /* dynamic */ | |
56 | #define IGB_MAX_ITR_USECS 10000 | |
57 | #define IGB_MIN_ITR_USECS 10 | |
047e0030 AD |
58 | #define NON_Q_VECTORS 1 |
59 | #define MAX_Q_VECTORS 8 | |
9d5c8243 AK |
60 | |
61 | /* Transmit and receive queues */ | |
a99955fc AD |
62 | #define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \ |
63 | (hw->mac.type > e1000_82575 ? 8 : 4)) | |
64 | #define IGB_ABS_MAX_TX_QUEUES 8 | |
65 | #define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES | |
9d5c8243 | 66 | |
4ae196df AD |
67 | #define IGB_MAX_VF_MC_ENTRIES 30 |
68 | #define IGB_MAX_VF_FUNCTIONS 8 | |
69 | #define IGB_MAX_VFTA_ENTRIES 128 | |
70 | ||
71 | struct vf_data_storage { | |
72 | unsigned char vf_mac_addresses[ETH_ALEN]; | |
73 | u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; | |
74 | u16 num_vf_mc_hashes; | |
ae641bdc | 75 | u16 vlans_enabled; |
f2ca0dbe AD |
76 | u32 flags; |
77 | unsigned long last_nack; | |
8151d294 WM |
78 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
79 | u16 pf_qos; | |
4ae196df AD |
80 | }; |
81 | ||
f2ca0dbe | 82 | #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ |
7d5753f0 AD |
83 | #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ |
84 | #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ | |
8151d294 | 85 | #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ |
f2ca0dbe | 86 | |
9d5c8243 AK |
87 | /* RX descriptor control thresholds. |
88 | * PTHRESH - MAC will consider prefetch if it has fewer than this number of | |
89 | * descriptors available in its onboard memory. | |
90 | * Setting this to 0 disables RX descriptor prefetch. | |
91 | * HTHRESH - MAC will only prefetch if there are at least this many descriptors | |
92 | * available in host memory. | |
93 | * If PTHRESH is 0, this should also be 0. | |
94 | * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back | |
95 | * descriptors until either it has this many to write back, or the | |
96 | * ITR timer expires. | |
97 | */ | |
85b430b4 | 98 | #define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8) |
9d5c8243 AK |
99 | #define IGB_RX_HTHRESH 8 |
100 | #define IGB_RX_WTHRESH 1 | |
85b430b4 AD |
101 | #define IGB_TX_PTHRESH 8 |
102 | #define IGB_TX_HTHRESH 1 | |
103 | #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ | |
104 | adapter->msix_entries) ? 0 : 16) | |
9d5c8243 AK |
105 | |
106 | /* this is the size past which hardware will drop packets when setting LPE=0 */ | |
107 | #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 | |
108 | ||
109 | /* Supported Rx Buffer Sizes */ | |
110 | #define IGB_RXBUFFER_128 128 /* Used for packet split */ | |
9d5c8243 AK |
111 | #define IGB_RXBUFFER_1024 1024 |
112 | #define IGB_RXBUFFER_2048 2048 | |
9d5c8243 AK |
113 | #define IGB_RXBUFFER_16384 16384 |
114 | ||
e1739522 | 115 | #define MAX_STD_JUMBO_FRAME_SIZE 9234 |
9d5c8243 AK |
116 | |
117 | /* How many Tx Descriptors do we need to call netif_wake_queue ? */ | |
118 | #define IGB_TX_QUEUE_WAKE 16 | |
119 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ | |
120 | #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
121 | ||
122 | #define AUTO_ALL_MODES 0 | |
123 | #define IGB_EEPROM_APME 0x0400 | |
124 | ||
125 | #ifndef IGB_MASTER_SLAVE | |
126 | /* Switch to override PHY master/slave setting */ | |
127 | #define IGB_MASTER_SLAVE e1000_ms_hw_default | |
128 | #endif | |
129 | ||
130 | #define IGB_MNG_VLAN_NONE -1 | |
131 | ||
132 | /* wrapper around a pointer to a socket buffer, | |
133 | * so a DMA handle can be stored along with the buffer */ | |
134 | struct igb_buffer { | |
135 | struct sk_buff *skb; | |
136 | dma_addr_t dma; | |
137 | union { | |
138 | /* TX */ | |
139 | struct { | |
140 | unsigned long time_stamp; | |
0e014cb1 AD |
141 | u16 length; |
142 | u16 next_to_watch; | |
6366ad33 | 143 | u16 mapped_as_page; |
40e90c26 | 144 | u16 gso_segs; |
9d5c8243 AK |
145 | }; |
146 | /* RX */ | |
147 | struct { | |
148 | struct page *page; | |
6366ad33 AD |
149 | dma_addr_t page_dma; |
150 | u16 page_offset; | |
9d5c8243 AK |
151 | }; |
152 | }; | |
153 | }; | |
154 | ||
8c0ab70a | 155 | struct igb_tx_queue_stats { |
9d5c8243 AK |
156 | u64 packets; |
157 | u64 bytes; | |
04a5fcaa | 158 | u64 restart_queue; |
9d5c8243 AK |
159 | }; |
160 | ||
8c0ab70a JDB |
161 | struct igb_rx_queue_stats { |
162 | u64 packets; | |
163 | u64 bytes; | |
164 | u64 drops; | |
04a5fcaa AD |
165 | u64 csum_err; |
166 | u64 alloc_failed; | |
8c0ab70a JDB |
167 | }; |
168 | ||
047e0030 | 169 | struct igb_q_vector { |
9d5c8243 | 170 | struct igb_adapter *adapter; /* backlink */ |
047e0030 AD |
171 | struct igb_ring *rx_ring; |
172 | struct igb_ring *tx_ring; | |
173 | struct napi_struct napi; | |
174 | ||
175 | u32 eims_value; | |
176 | u16 cpu; | |
177 | ||
178 | u16 itr_val; | |
179 | u8 set_itr; | |
047e0030 AD |
180 | void __iomem *itr_register; |
181 | ||
182 | char name[IFNAMSIZ + 9]; | |
183 | }; | |
184 | ||
185 | struct igb_ring { | |
186 | struct igb_q_vector *q_vector; /* backlink to q_vector */ | |
e694e964 | 187 | struct net_device *netdev; /* back pointer to net_device */ |
80785298 | 188 | struct pci_dev *pdev; /* pci device for dma mapping */ |
047e0030 | 189 | dma_addr_t dma; /* phys address of the ring */ |
e694e964 | 190 | void *desc; /* descriptor ring memory */ |
047e0030 | 191 | unsigned int size; /* length of desc. ring in bytes */ |
2e5655e7 | 192 | u16 count; /* number of desc. in the ring */ |
9d5c8243 AK |
193 | u16 next_to_use; |
194 | u16 next_to_clean; | |
2e5655e7 AD |
195 | u8 queue_index; |
196 | u8 reg_idx; | |
fce99e34 AD |
197 | void __iomem *head; |
198 | void __iomem *tail; | |
9d5c8243 AK |
199 | struct igb_buffer *buffer_info; /* array of buffer info structs */ |
200 | ||
9d5c8243 AK |
201 | unsigned int total_bytes; |
202 | unsigned int total_packets; | |
203 | ||
85ad76b2 AD |
204 | u32 flags; |
205 | ||
9d5c8243 AK |
206 | union { |
207 | /* TX */ | |
208 | struct { | |
8c0ab70a | 209 | struct igb_tx_queue_stats tx_stats; |
9d5c8243 AK |
210 | bool detect_tx_hung; |
211 | }; | |
212 | /* RX */ | |
213 | struct { | |
8c0ab70a | 214 | struct igb_rx_queue_stats rx_stats; |
4c844851 | 215 | u32 rx_buffer_len; |
9d5c8243 AK |
216 | }; |
217 | }; | |
9d5c8243 AK |
218 | }; |
219 | ||
85ad76b2 AD |
220 | #define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */ |
221 | #define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */ | |
222 | ||
223 | #define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */ | |
224 | ||
225 | #define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS) | |
226 | ||
9d5c8243 AK |
227 | #define E1000_RX_DESC_ADV(R, i) \ |
228 | (&(((union e1000_adv_rx_desc *)((R).desc))[i])) | |
229 | #define E1000_TX_DESC_ADV(R, i) \ | |
230 | (&(((union e1000_adv_tx_desc *)((R).desc))[i])) | |
231 | #define E1000_TX_CTXTDESC_ADV(R, i) \ | |
232 | (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i])) | |
9d5c8243 | 233 | |
d7ee5b3a AD |
234 | /* igb_desc_unused - calculate if we have unused descriptors */ |
235 | static inline int igb_desc_unused(struct igb_ring *ring) | |
236 | { | |
237 | if (ring->next_to_clean > ring->next_to_use) | |
238 | return ring->next_to_clean - ring->next_to_use - 1; | |
239 | ||
240 | return ring->count + ring->next_to_clean - ring->next_to_use - 1; | |
241 | } | |
242 | ||
9d5c8243 | 243 | /* board specific private data structure */ |
9d5c8243 AK |
244 | struct igb_adapter { |
245 | struct timer_list watchdog_timer; | |
246 | struct timer_list phy_info_timer; | |
247 | struct vlan_group *vlgrp; | |
248 | u16 mng_vlan_id; | |
249 | u32 bd_number; | |
9d5c8243 AK |
250 | u32 wol; |
251 | u32 en_mng_pt; | |
252 | u16 link_speed; | |
253 | u16 link_duplex; | |
2e5655e7 | 254 | |
9d5c8243 | 255 | /* Interrupt Throttle Rate */ |
4fc82adf AD |
256 | u32 rx_itr_setting; |
257 | u32 tx_itr_setting; | |
9d5c8243 AK |
258 | u16 tx_itr; |
259 | u16 rx_itr; | |
9d5c8243 AK |
260 | |
261 | struct work_struct reset_task; | |
262 | struct work_struct watchdog_task; | |
263 | bool fc_autoneg; | |
264 | u8 tx_timeout_factor; | |
265 | struct timer_list blink_timer; | |
266 | unsigned long led_status; | |
267 | ||
268 | /* TX */ | |
3025a446 | 269 | struct igb_ring *tx_ring[16]; |
9d5c8243 | 270 | unsigned long tx_queue_len; |
9d5c8243 AK |
271 | u32 tx_timeout_count; |
272 | ||
273 | /* RX */ | |
3025a446 | 274 | struct igb_ring *rx_ring[16]; |
9d5c8243 AK |
275 | int num_tx_queues; |
276 | int num_rx_queues; | |
277 | ||
9d5c8243 AK |
278 | u32 max_frame_size; |
279 | u32 min_frame_size; | |
280 | ||
281 | /* OS defined structs */ | |
282 | struct net_device *netdev; | |
9d5c8243 | 283 | struct pci_dev *pdev; |
38c845c7 PO |
284 | struct cyclecounter cycles; |
285 | struct timecounter clock; | |
33af6bcc PO |
286 | struct timecompare compare; |
287 | struct hwtstamp_config hwtstamp_config; | |
9d5c8243 AK |
288 | |
289 | /* structs defined in e1000_hw.h */ | |
290 | struct e1000_hw hw; | |
291 | struct e1000_hw_stats stats; | |
292 | struct e1000_phy_info phy_info; | |
293 | struct e1000_phy_stats phy_stats; | |
294 | ||
295 | u32 test_icr; | |
296 | struct igb_ring test_tx_ring; | |
297 | struct igb_ring test_rx_ring; | |
298 | ||
299 | int msg_enable; | |
047e0030 AD |
300 | |
301 | unsigned int num_q_vectors; | |
302 | struct igb_q_vector *q_vector[MAX_Q_VECTORS]; | |
9d5c8243 AK |
303 | struct msix_entry *msix_entries; |
304 | u32 eims_enable_mask; | |
844290e5 | 305 | u32 eims_other; |
9d5c8243 AK |
306 | |
307 | /* to not mess up cache alignment, always add to the bottom */ | |
308 | unsigned long state; | |
7dfc16fa | 309 | unsigned int flags; |
9d5c8243 | 310 | u32 eeprom_wol; |
42bfd33a | 311 | |
1bfaf07b | 312 | struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES]; |
2e5655e7 AD |
313 | u16 tx_ring_count; |
314 | u16 rx_ring_count; | |
1bfaf07b | 315 | unsigned int vfs_allocated_count; |
4ae196df | 316 | struct vf_data_storage *vf_data; |
a99955fc | 317 | u32 rss_queues; |
9d5c8243 AK |
318 | }; |
319 | ||
7dfc16fa | 320 | #define IGB_FLAG_HAS_MSI (1 << 0) |
cbd347ad AD |
321 | #define IGB_FLAG_DCA_ENABLED (1 << 1) |
322 | #define IGB_FLAG_QUAD_PORT_A (1 << 2) | |
4fc82adf | 323 | #define IGB_FLAG_QUEUE_PAIRS (1 << 3) |
7dfc16fa | 324 | |
c5b9bd5e | 325 | #define IGB_82576_TSYNC_SHIFT 19 |
55cac248 | 326 | #define IGB_82580_TSYNC_SHIFT 24 |
9d5c8243 AK |
327 | enum e1000_state_t { |
328 | __IGB_TESTING, | |
329 | __IGB_RESETTING, | |
330 | __IGB_DOWN | |
331 | }; | |
332 | ||
333 | enum igb_boards { | |
334 | board_82575, | |
335 | }; | |
336 | ||
337 | extern char igb_driver_name[]; | |
338 | extern char igb_driver_version[]; | |
339 | ||
340 | extern char *igb_get_hw_dev_name(struct e1000_hw *hw); | |
341 | extern int igb_up(struct igb_adapter *); | |
342 | extern void igb_down(struct igb_adapter *); | |
343 | extern void igb_reinit_locked(struct igb_adapter *); | |
344 | extern void igb_reset(struct igb_adapter *); | |
345 | extern int igb_set_spd_dplx(struct igb_adapter *, u16); | |
80785298 AD |
346 | extern int igb_setup_tx_resources(struct igb_ring *); |
347 | extern int igb_setup_rx_resources(struct igb_ring *); | |
68fd9910 AD |
348 | extern void igb_free_tx_resources(struct igb_ring *); |
349 | extern void igb_free_rx_resources(struct igb_ring *); | |
d7ee5b3a AD |
350 | extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); |
351 | extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); | |
352 | extern void igb_setup_tctl(struct igb_adapter *); | |
353 | extern void igb_setup_rctl(struct igb_adapter *); | |
b1a436c3 AD |
354 | extern netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *, struct igb_ring *); |
355 | extern void igb_unmap_and_free_tx_resource(struct igb_ring *, | |
356 | struct igb_buffer *); | |
d7ee5b3a | 357 | extern void igb_alloc_rx_buffers_adv(struct igb_ring *, int); |
9d5c8243 | 358 | extern void igb_update_stats(struct igb_adapter *); |
3145535a | 359 | extern bool igb_has_link(struct igb_adapter *adapter); |
9d5c8243 | 360 | extern void igb_set_ethtool_ops(struct net_device *); |
88a268c1 | 361 | extern void igb_power_up_link(struct igb_adapter *); |
9d5c8243 | 362 | |
f5f4cf08 AD |
363 | static inline s32 igb_reset_phy(struct e1000_hw *hw) |
364 | { | |
a8d2a0c2 AD |
365 | if (hw->phy.ops.reset) |
366 | return hw->phy.ops.reset(hw); | |
f5f4cf08 AD |
367 | |
368 | return 0; | |
369 | } | |
370 | ||
371 | static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) | |
372 | { | |
a8d2a0c2 AD |
373 | if (hw->phy.ops.read_reg) |
374 | return hw->phy.ops.read_reg(hw, offset, data); | |
f5f4cf08 AD |
375 | |
376 | return 0; | |
377 | } | |
378 | ||
379 | static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) | |
380 | { | |
a8d2a0c2 AD |
381 | if (hw->phy.ops.write_reg) |
382 | return hw->phy.ops.write_reg(hw, offset, data); | |
f5f4cf08 AD |
383 | |
384 | return 0; | |
385 | } | |
386 | ||
387 | static inline s32 igb_get_phy_info(struct e1000_hw *hw) | |
388 | { | |
389 | if (hw->phy.ops.get_phy_info) | |
390 | return hw->phy.ops.get_phy_info(hw); | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
9d5c8243 | 395 | #endif /* _IGB_H_ */ |