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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | ||
29 | /* Linux PRO/1000 Ethernet Driver main header file */ | |
30 | ||
31 | #ifndef _IGB_H_ | |
32 | #define _IGB_H_ | |
33 | ||
34 | #include "e1000_mac.h" | |
35 | #include "e1000_82575.h" | |
36 | ||
38c845c7 | 37 | #include <linux/clocksource.h> |
33af6bcc PO |
38 | #include <linux/timecompare.h> |
39 | #include <linux/net_tstamp.h> | |
38c845c7 | 40 | |
9d5c8243 AK |
41 | struct igb_adapter; |
42 | ||
6eb5a7f1 AD |
43 | /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */ |
44 | #define IGB_START_ITR 648 | |
9d5c8243 | 45 | |
9d5c8243 AK |
46 | /* TX/RX descriptor defines */ |
47 | #define IGB_DEFAULT_TXD 256 | |
48 | #define IGB_MIN_TXD 80 | |
49 | #define IGB_MAX_TXD 4096 | |
50 | ||
51 | #define IGB_DEFAULT_RXD 256 | |
52 | #define IGB_MIN_RXD 80 | |
53 | #define IGB_MAX_RXD 4096 | |
54 | ||
55 | #define IGB_DEFAULT_ITR 3 /* dynamic */ | |
56 | #define IGB_MAX_ITR_USECS 10000 | |
57 | #define IGB_MIN_ITR_USECS 10 | |
047e0030 AD |
58 | #define NON_Q_VECTORS 1 |
59 | #define MAX_Q_VECTORS 8 | |
9d5c8243 AK |
60 | |
61 | /* Transmit and receive queues */ | |
a99955fc AD |
62 | #define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \ |
63 | (hw->mac.type > e1000_82575 ? 8 : 4)) | |
64 | #define IGB_ABS_MAX_TX_QUEUES 8 | |
65 | #define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES | |
9d5c8243 | 66 | |
4ae196df AD |
67 | #define IGB_MAX_VF_MC_ENTRIES 30 |
68 | #define IGB_MAX_VF_FUNCTIONS 8 | |
69 | #define IGB_MAX_VFTA_ENTRIES 128 | |
70 | ||
71 | struct vf_data_storage { | |
72 | unsigned char vf_mac_addresses[ETH_ALEN]; | |
73 | u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; | |
74 | u16 num_vf_mc_hashes; | |
ae641bdc | 75 | u16 vlans_enabled; |
f2ca0dbe AD |
76 | u32 flags; |
77 | unsigned long last_nack; | |
4ae196df AD |
78 | }; |
79 | ||
f2ca0dbe | 80 | #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ |
7d5753f0 AD |
81 | #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ |
82 | #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ | |
f2ca0dbe | 83 | |
9d5c8243 AK |
84 | /* RX descriptor control thresholds. |
85 | * PTHRESH - MAC will consider prefetch if it has fewer than this number of | |
86 | * descriptors available in its onboard memory. | |
87 | * Setting this to 0 disables RX descriptor prefetch. | |
88 | * HTHRESH - MAC will only prefetch if there are at least this many descriptors | |
89 | * available in host memory. | |
90 | * If PTHRESH is 0, this should also be 0. | |
91 | * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back | |
92 | * descriptors until either it has this many to write back, or the | |
93 | * ITR timer expires. | |
94 | */ | |
85b430b4 | 95 | #define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8) |
9d5c8243 AK |
96 | #define IGB_RX_HTHRESH 8 |
97 | #define IGB_RX_WTHRESH 1 | |
85b430b4 AD |
98 | #define IGB_TX_PTHRESH 8 |
99 | #define IGB_TX_HTHRESH 1 | |
100 | #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ | |
101 | adapter->msix_entries) ? 0 : 16) | |
9d5c8243 AK |
102 | |
103 | /* this is the size past which hardware will drop packets when setting LPE=0 */ | |
104 | #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 | |
105 | ||
106 | /* Supported Rx Buffer Sizes */ | |
107 | #define IGB_RXBUFFER_128 128 /* Used for packet split */ | |
9d5c8243 AK |
108 | #define IGB_RXBUFFER_1024 1024 |
109 | #define IGB_RXBUFFER_2048 2048 | |
9d5c8243 AK |
110 | #define IGB_RXBUFFER_16384 16384 |
111 | ||
e1739522 | 112 | #define MAX_STD_JUMBO_FRAME_SIZE 9234 |
9d5c8243 AK |
113 | |
114 | /* How many Tx Descriptors do we need to call netif_wake_queue ? */ | |
115 | #define IGB_TX_QUEUE_WAKE 16 | |
116 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ | |
117 | #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
118 | ||
119 | #define AUTO_ALL_MODES 0 | |
120 | #define IGB_EEPROM_APME 0x0400 | |
121 | ||
122 | #ifndef IGB_MASTER_SLAVE | |
123 | /* Switch to override PHY master/slave setting */ | |
124 | #define IGB_MASTER_SLAVE e1000_ms_hw_default | |
125 | #endif | |
126 | ||
127 | #define IGB_MNG_VLAN_NONE -1 | |
128 | ||
129 | /* wrapper around a pointer to a socket buffer, | |
130 | * so a DMA handle can be stored along with the buffer */ | |
131 | struct igb_buffer { | |
132 | struct sk_buff *skb; | |
133 | dma_addr_t dma; | |
134 | union { | |
135 | /* TX */ | |
136 | struct { | |
137 | unsigned long time_stamp; | |
0e014cb1 AD |
138 | u16 length; |
139 | u16 next_to_watch; | |
9d5c8243 AK |
140 | }; |
141 | /* RX */ | |
142 | struct { | |
143 | struct page *page; | |
144 | u64 page_dma; | |
bf36c1a0 | 145 | unsigned int page_offset; |
9d5c8243 AK |
146 | }; |
147 | }; | |
148 | }; | |
149 | ||
8c0ab70a | 150 | struct igb_tx_queue_stats { |
9d5c8243 AK |
151 | u64 packets; |
152 | u64 bytes; | |
04a5fcaa | 153 | u64 restart_queue; |
9d5c8243 AK |
154 | }; |
155 | ||
8c0ab70a JDB |
156 | struct igb_rx_queue_stats { |
157 | u64 packets; | |
158 | u64 bytes; | |
159 | u64 drops; | |
04a5fcaa AD |
160 | u64 csum_err; |
161 | u64 alloc_failed; | |
8c0ab70a JDB |
162 | }; |
163 | ||
047e0030 | 164 | struct igb_q_vector { |
9d5c8243 | 165 | struct igb_adapter *adapter; /* backlink */ |
047e0030 AD |
166 | struct igb_ring *rx_ring; |
167 | struct igb_ring *tx_ring; | |
168 | struct napi_struct napi; | |
169 | ||
170 | u32 eims_value; | |
171 | u16 cpu; | |
172 | ||
173 | u16 itr_val; | |
174 | u8 set_itr; | |
175 | u8 itr_shift; | |
176 | void __iomem *itr_register; | |
177 | ||
178 | char name[IFNAMSIZ + 9]; | |
179 | }; | |
180 | ||
181 | struct igb_ring { | |
182 | struct igb_q_vector *q_vector; /* backlink to q_vector */ | |
e694e964 | 183 | struct net_device *netdev; /* back pointer to net_device */ |
80785298 | 184 | struct pci_dev *pdev; /* pci device for dma mapping */ |
047e0030 | 185 | dma_addr_t dma; /* phys address of the ring */ |
e694e964 | 186 | void *desc; /* descriptor ring memory */ |
047e0030 | 187 | unsigned int size; /* length of desc. ring in bytes */ |
2e5655e7 | 188 | u16 count; /* number of desc. in the ring */ |
9d5c8243 AK |
189 | u16 next_to_use; |
190 | u16 next_to_clean; | |
2e5655e7 AD |
191 | u8 queue_index; |
192 | u8 reg_idx; | |
fce99e34 AD |
193 | void __iomem *head; |
194 | void __iomem *tail; | |
9d5c8243 AK |
195 | struct igb_buffer *buffer_info; /* array of buffer info structs */ |
196 | ||
9d5c8243 AK |
197 | unsigned int total_bytes; |
198 | unsigned int total_packets; | |
199 | ||
85ad76b2 AD |
200 | u32 flags; |
201 | ||
9d5c8243 AK |
202 | union { |
203 | /* TX */ | |
204 | struct { | |
8c0ab70a | 205 | struct igb_tx_queue_stats tx_stats; |
9d5c8243 AK |
206 | bool detect_tx_hung; |
207 | }; | |
208 | /* RX */ | |
209 | struct { | |
8c0ab70a | 210 | struct igb_rx_queue_stats rx_stats; |
4c844851 | 211 | u32 rx_buffer_len; |
9d5c8243 AK |
212 | }; |
213 | }; | |
9d5c8243 AK |
214 | }; |
215 | ||
85ad76b2 AD |
216 | #define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */ |
217 | #define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */ | |
218 | ||
219 | #define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */ | |
220 | ||
221 | #define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS) | |
222 | ||
9d5c8243 AK |
223 | #define E1000_RX_DESC_ADV(R, i) \ |
224 | (&(((union e1000_adv_rx_desc *)((R).desc))[i])) | |
225 | #define E1000_TX_DESC_ADV(R, i) \ | |
226 | (&(((union e1000_adv_tx_desc *)((R).desc))[i])) | |
227 | #define E1000_TX_CTXTDESC_ADV(R, i) \ | |
228 | (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i])) | |
9d5c8243 | 229 | |
d7ee5b3a AD |
230 | /* igb_desc_unused - calculate if we have unused descriptors */ |
231 | static inline int igb_desc_unused(struct igb_ring *ring) | |
232 | { | |
233 | if (ring->next_to_clean > ring->next_to_use) | |
234 | return ring->next_to_clean - ring->next_to_use - 1; | |
235 | ||
236 | return ring->count + ring->next_to_clean - ring->next_to_use - 1; | |
237 | } | |
238 | ||
9d5c8243 AK |
239 | /* board specific private data structure */ |
240 | ||
241 | struct igb_adapter { | |
242 | struct timer_list watchdog_timer; | |
243 | struct timer_list phy_info_timer; | |
244 | struct vlan_group *vlgrp; | |
245 | u16 mng_vlan_id; | |
246 | u32 bd_number; | |
9d5c8243 AK |
247 | u32 wol; |
248 | u32 en_mng_pt; | |
249 | u16 link_speed; | |
250 | u16 link_duplex; | |
2e5655e7 | 251 | |
9d5c8243 | 252 | /* Interrupt Throttle Rate */ |
4fc82adf AD |
253 | u32 rx_itr_setting; |
254 | u32 tx_itr_setting; | |
9d5c8243 AK |
255 | u16 tx_itr; |
256 | u16 rx_itr; | |
9d5c8243 AK |
257 | |
258 | struct work_struct reset_task; | |
259 | struct work_struct watchdog_task; | |
260 | bool fc_autoneg; | |
261 | u8 tx_timeout_factor; | |
262 | struct timer_list blink_timer; | |
263 | unsigned long led_status; | |
264 | ||
265 | /* TX */ | |
266 | struct igb_ring *tx_ring; /* One per active queue */ | |
9d5c8243 | 267 | unsigned long tx_queue_len; |
9d5c8243 AK |
268 | u32 tx_timeout_count; |
269 | ||
270 | /* RX */ | |
271 | struct igb_ring *rx_ring; /* One per active queue */ | |
272 | int num_tx_queues; | |
273 | int num_rx_queues; | |
274 | ||
9d5c8243 AK |
275 | u32 max_frame_size; |
276 | u32 min_frame_size; | |
277 | ||
278 | /* OS defined structs */ | |
279 | struct net_device *netdev; | |
9d5c8243 | 280 | struct pci_dev *pdev; |
38c845c7 PO |
281 | struct cyclecounter cycles; |
282 | struct timecounter clock; | |
33af6bcc PO |
283 | struct timecompare compare; |
284 | struct hwtstamp_config hwtstamp_config; | |
9d5c8243 AK |
285 | |
286 | /* structs defined in e1000_hw.h */ | |
287 | struct e1000_hw hw; | |
288 | struct e1000_hw_stats stats; | |
289 | struct e1000_phy_info phy_info; | |
290 | struct e1000_phy_stats phy_stats; | |
291 | ||
292 | u32 test_icr; | |
293 | struct igb_ring test_tx_ring; | |
294 | struct igb_ring test_rx_ring; | |
295 | ||
296 | int msg_enable; | |
047e0030 AD |
297 | |
298 | unsigned int num_q_vectors; | |
299 | struct igb_q_vector *q_vector[MAX_Q_VECTORS]; | |
9d5c8243 AK |
300 | struct msix_entry *msix_entries; |
301 | u32 eims_enable_mask; | |
844290e5 | 302 | u32 eims_other; |
9d5c8243 AK |
303 | |
304 | /* to not mess up cache alignment, always add to the bottom */ | |
305 | unsigned long state; | |
7dfc16fa | 306 | unsigned int flags; |
9d5c8243 | 307 | u32 eeprom_wol; |
42bfd33a | 308 | |
1bfaf07b | 309 | struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES]; |
2e5655e7 AD |
310 | u16 tx_ring_count; |
311 | u16 rx_ring_count; | |
1bfaf07b | 312 | unsigned int vfs_allocated_count; |
4ae196df | 313 | struct vf_data_storage *vf_data; |
a99955fc | 314 | u32 rss_queues; |
9d5c8243 AK |
315 | }; |
316 | ||
7dfc16fa | 317 | #define IGB_FLAG_HAS_MSI (1 << 0) |
cbd347ad AD |
318 | #define IGB_FLAG_DCA_ENABLED (1 << 1) |
319 | #define IGB_FLAG_QUAD_PORT_A (1 << 2) | |
4fc82adf | 320 | #define IGB_FLAG_QUEUE_PAIRS (1 << 3) |
7dfc16fa | 321 | |
c5b9bd5e | 322 | #define IGB_82576_TSYNC_SHIFT 19 |
9d5c8243 AK |
323 | enum e1000_state_t { |
324 | __IGB_TESTING, | |
325 | __IGB_RESETTING, | |
326 | __IGB_DOWN | |
327 | }; | |
328 | ||
329 | enum igb_boards { | |
330 | board_82575, | |
331 | }; | |
332 | ||
333 | extern char igb_driver_name[]; | |
334 | extern char igb_driver_version[]; | |
335 | ||
336 | extern char *igb_get_hw_dev_name(struct e1000_hw *hw); | |
337 | extern int igb_up(struct igb_adapter *); | |
338 | extern void igb_down(struct igb_adapter *); | |
339 | extern void igb_reinit_locked(struct igb_adapter *); | |
340 | extern void igb_reset(struct igb_adapter *); | |
341 | extern int igb_set_spd_dplx(struct igb_adapter *, u16); | |
80785298 AD |
342 | extern int igb_setup_tx_resources(struct igb_ring *); |
343 | extern int igb_setup_rx_resources(struct igb_ring *); | |
68fd9910 AD |
344 | extern void igb_free_tx_resources(struct igb_ring *); |
345 | extern void igb_free_rx_resources(struct igb_ring *); | |
d7ee5b3a AD |
346 | extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); |
347 | extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); | |
348 | extern void igb_setup_tctl(struct igb_adapter *); | |
349 | extern void igb_setup_rctl(struct igb_adapter *); | |
b1a436c3 AD |
350 | extern netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *, struct igb_ring *); |
351 | extern void igb_unmap_and_free_tx_resource(struct igb_ring *, | |
352 | struct igb_buffer *); | |
d7ee5b3a | 353 | extern void igb_alloc_rx_buffers_adv(struct igb_ring *, int); |
9d5c8243 AK |
354 | extern void igb_update_stats(struct igb_adapter *); |
355 | extern void igb_set_ethtool_ops(struct net_device *); | |
356 | ||
f5f4cf08 AD |
357 | static inline s32 igb_reset_phy(struct e1000_hw *hw) |
358 | { | |
a8d2a0c2 AD |
359 | if (hw->phy.ops.reset) |
360 | return hw->phy.ops.reset(hw); | |
f5f4cf08 AD |
361 | |
362 | return 0; | |
363 | } | |
364 | ||
365 | static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) | |
366 | { | |
a8d2a0c2 AD |
367 | if (hw->phy.ops.read_reg) |
368 | return hw->phy.ops.read_reg(hw, offset, data); | |
f5f4cf08 AD |
369 | |
370 | return 0; | |
371 | } | |
372 | ||
373 | static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) | |
374 | { | |
a8d2a0c2 AD |
375 | if (hw->phy.ops.write_reg) |
376 | return hw->phy.ops.write_reg(hw, offset, data); | |
f5f4cf08 AD |
377 | |
378 | return 0; | |
379 | } | |
380 | ||
381 | static inline s32 igb_get_phy_info(struct e1000_hw *hw) | |
382 | { | |
383 | if (hw->phy.ops.get_phy_info) | |
384 | return hw->phy.ops.get_phy_info(hw); | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
9d5c8243 | 389 | #endif /* _IGB_H_ */ |