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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/if_ether.h> | |
29 | #include <linux/delay.h> | |
30 | ||
31 | #include "e1000_mac.h" | |
32 | #include "e1000_phy.h" | |
33 | ||
9d5c8243 AK |
34 | static s32 igb_phy_setup_autoneg(struct e1000_hw *hw); |
35 | static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, | |
36 | u16 *phy_ctrl); | |
37 | static s32 igb_wait_autoneg(struct e1000_hw *hw); | |
38 | ||
39 | /* Cable length tables */ | |
40 | static const u16 e1000_m88_cable_length_table[] = | |
41 | { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; | |
2553bb26 AD |
42 | #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ |
43 | (sizeof(e1000_m88_cable_length_table) / \ | |
44 | sizeof(e1000_m88_cable_length_table[0])) | |
9d5c8243 AK |
45 | |
46 | static const u16 e1000_igp_2_cable_length_table[] = | |
47 | { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, | |
48 | 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, | |
49 | 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, | |
50 | 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, | |
51 | 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, | |
52 | 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, | |
53 | 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, | |
54 | 104, 109, 114, 118, 121, 124}; | |
55 | #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ | |
56 | (sizeof(e1000_igp_2_cable_length_table) / \ | |
57 | sizeof(e1000_igp_2_cable_length_table[0])) | |
58 | ||
59 | /** | |
733596be | 60 | * igb_check_reset_block - Check if PHY reset is blocked |
9d5c8243 AK |
61 | * @hw: pointer to the HW structure |
62 | * | |
63 | * Read the PHY management control register and check whether a PHY reset | |
64 | * is blocked. If a reset is not blocked return 0, otherwise | |
65 | * return E1000_BLK_PHY_RESET (12). | |
66 | **/ | |
67 | s32 igb_check_reset_block(struct e1000_hw *hw) | |
68 | { | |
69 | u32 manc; | |
70 | ||
71 | manc = rd32(E1000_MANC); | |
72 | ||
73 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | |
74 | E1000_BLK_PHY_RESET : 0; | |
75 | } | |
76 | ||
77 | /** | |
733596be | 78 | * igb_get_phy_id - Retrieve the PHY ID and revision |
9d5c8243 AK |
79 | * @hw: pointer to the HW structure |
80 | * | |
81 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
82 | * revision in the hardware structure. | |
83 | **/ | |
84 | s32 igb_get_phy_id(struct e1000_hw *hw) | |
85 | { | |
86 | struct e1000_phy_info *phy = &hw->phy; | |
87 | s32 ret_val = 0; | |
88 | u16 phy_id; | |
89 | ||
a8d2a0c2 | 90 | ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); |
9d5c8243 AK |
91 | if (ret_val) |
92 | goto out; | |
93 | ||
94 | phy->id = (u32)(phy_id << 16); | |
95 | udelay(20); | |
a8d2a0c2 | 96 | ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); |
9d5c8243 AK |
97 | if (ret_val) |
98 | goto out; | |
99 | ||
100 | phy->id |= (u32)(phy_id & PHY_REVISION_MASK); | |
101 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
102 | ||
103 | out: | |
104 | return ret_val; | |
105 | } | |
106 | ||
107 | /** | |
733596be | 108 | * igb_phy_reset_dsp - Reset PHY DSP |
9d5c8243 AK |
109 | * @hw: pointer to the HW structure |
110 | * | |
111 | * Reset the digital signal processor. | |
112 | **/ | |
113 | static s32 igb_phy_reset_dsp(struct e1000_hw *hw) | |
114 | { | |
2553bb26 AD |
115 | s32 ret_val = 0; |
116 | ||
117 | if (!(hw->phy.ops.write_reg)) | |
118 | goto out; | |
9d5c8243 | 119 | |
a8d2a0c2 | 120 | ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); |
9d5c8243 AK |
121 | if (ret_val) |
122 | goto out; | |
123 | ||
a8d2a0c2 | 124 | ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); |
9d5c8243 AK |
125 | |
126 | out: | |
127 | return ret_val; | |
128 | } | |
129 | ||
130 | /** | |
733596be | 131 | * igb_read_phy_reg_mdic - Read MDI control register |
9d5c8243 AK |
132 | * @hw: pointer to the HW structure |
133 | * @offset: register offset to be read | |
134 | * @data: pointer to the read data | |
135 | * | |
136 | * Reads the MDI control regsiter in the PHY at offset and stores the | |
137 | * information read to data. | |
138 | **/ | |
bb2ac47b | 139 | s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
9d5c8243 AK |
140 | { |
141 | struct e1000_phy_info *phy = &hw->phy; | |
142 | u32 i, mdic = 0; | |
143 | s32 ret_val = 0; | |
144 | ||
145 | if (offset > MAX_PHY_REG_ADDRESS) { | |
652fff32 | 146 | hw_dbg("PHY Address %d is out of range\n", offset); |
9d5c8243 AK |
147 | ret_val = -E1000_ERR_PARAM; |
148 | goto out; | |
149 | } | |
150 | ||
151 | /* | |
152 | * Set up Op-code, Phy Address, and register offset in the MDI | |
153 | * Control register. The MAC will take care of interfacing with the | |
154 | * PHY to retrieve the desired data. | |
155 | */ | |
156 | mdic = ((offset << E1000_MDIC_REG_SHIFT) | | |
157 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
158 | (E1000_MDIC_OP_READ)); | |
159 | ||
160 | wr32(E1000_MDIC, mdic); | |
161 | ||
162 | /* | |
163 | * Poll the ready bit to see if the MDI read completed | |
164 | * Increasing the time out as testing showed failures with | |
165 | * the lower time out | |
166 | */ | |
167 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { | |
168 | udelay(50); | |
169 | mdic = rd32(E1000_MDIC); | |
170 | if (mdic & E1000_MDIC_READY) | |
171 | break; | |
172 | } | |
173 | if (!(mdic & E1000_MDIC_READY)) { | |
652fff32 | 174 | hw_dbg("MDI Read did not complete\n"); |
9d5c8243 AK |
175 | ret_val = -E1000_ERR_PHY; |
176 | goto out; | |
177 | } | |
178 | if (mdic & E1000_MDIC_ERROR) { | |
652fff32 | 179 | hw_dbg("MDI Error\n"); |
9d5c8243 AK |
180 | ret_val = -E1000_ERR_PHY; |
181 | goto out; | |
182 | } | |
183 | *data = (u16) mdic; | |
184 | ||
185 | out: | |
186 | return ret_val; | |
187 | } | |
188 | ||
189 | /** | |
733596be | 190 | * igb_write_phy_reg_mdic - Write MDI control register |
9d5c8243 AK |
191 | * @hw: pointer to the HW structure |
192 | * @offset: register offset to write to | |
193 | * @data: data to write to register at offset | |
194 | * | |
195 | * Writes data to MDI control register in the PHY at offset. | |
196 | **/ | |
bb2ac47b | 197 | s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) |
9d5c8243 AK |
198 | { |
199 | struct e1000_phy_info *phy = &hw->phy; | |
200 | u32 i, mdic = 0; | |
201 | s32 ret_val = 0; | |
202 | ||
203 | if (offset > MAX_PHY_REG_ADDRESS) { | |
652fff32 | 204 | hw_dbg("PHY Address %d is out of range\n", offset); |
9d5c8243 AK |
205 | ret_val = -E1000_ERR_PARAM; |
206 | goto out; | |
207 | } | |
208 | ||
209 | /* | |
210 | * Set up Op-code, Phy Address, and register offset in the MDI | |
211 | * Control register. The MAC will take care of interfacing with the | |
212 | * PHY to retrieve the desired data. | |
213 | */ | |
214 | mdic = (((u32)data) | | |
215 | (offset << E1000_MDIC_REG_SHIFT) | | |
216 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
217 | (E1000_MDIC_OP_WRITE)); | |
218 | ||
219 | wr32(E1000_MDIC, mdic); | |
220 | ||
221 | /* | |
222 | * Poll the ready bit to see if the MDI read completed | |
223 | * Increasing the time out as testing showed failures with | |
224 | * the lower time out | |
225 | */ | |
226 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { | |
227 | udelay(50); | |
228 | mdic = rd32(E1000_MDIC); | |
229 | if (mdic & E1000_MDIC_READY) | |
230 | break; | |
231 | } | |
232 | if (!(mdic & E1000_MDIC_READY)) { | |
652fff32 | 233 | hw_dbg("MDI Write did not complete\n"); |
9d5c8243 AK |
234 | ret_val = -E1000_ERR_PHY; |
235 | goto out; | |
236 | } | |
237 | if (mdic & E1000_MDIC_ERROR) { | |
652fff32 | 238 | hw_dbg("MDI Error\n"); |
9d5c8243 AK |
239 | ret_val = -E1000_ERR_PHY; |
240 | goto out; | |
241 | } | |
242 | ||
243 | out: | |
244 | return ret_val; | |
245 | } | |
246 | ||
bf6f7a92 AD |
247 | /** |
248 | * igb_read_phy_reg_i2c - Read PHY register using i2c | |
249 | * @hw: pointer to the HW structure | |
250 | * @offset: register offset to be read | |
251 | * @data: pointer to the read data | |
252 | * | |
253 | * Reads the PHY register at offset using the i2c interface and stores the | |
254 | * retrieved information in data. | |
255 | **/ | |
256 | s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) | |
257 | { | |
258 | struct e1000_phy_info *phy = &hw->phy; | |
259 | u32 i, i2ccmd = 0; | |
260 | ||
261 | ||
262 | /* | |
263 | * Set up Op-code, Phy Address, and register address in the I2CCMD | |
264 | * register. The MAC will take care of interfacing with the | |
265 | * PHY to retrieve the desired data. | |
266 | */ | |
267 | i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | | |
268 | (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | | |
269 | (E1000_I2CCMD_OPCODE_READ)); | |
270 | ||
271 | wr32(E1000_I2CCMD, i2ccmd); | |
272 | ||
273 | /* Poll the ready bit to see if the I2C read completed */ | |
274 | for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { | |
275 | udelay(50); | |
276 | i2ccmd = rd32(E1000_I2CCMD); | |
277 | if (i2ccmd & E1000_I2CCMD_READY) | |
278 | break; | |
279 | } | |
280 | if (!(i2ccmd & E1000_I2CCMD_READY)) { | |
281 | hw_dbg("I2CCMD Read did not complete\n"); | |
282 | return -E1000_ERR_PHY; | |
283 | } | |
284 | if (i2ccmd & E1000_I2CCMD_ERROR) { | |
285 | hw_dbg("I2CCMD Error bit set\n"); | |
286 | return -E1000_ERR_PHY; | |
287 | } | |
288 | ||
289 | /* Need to byte-swap the 16-bit value. */ | |
290 | *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
295 | /** | |
296 | * igb_write_phy_reg_i2c - Write PHY register using i2c | |
297 | * @hw: pointer to the HW structure | |
298 | * @offset: register offset to write to | |
299 | * @data: data to write at register offset | |
300 | * | |
301 | * Writes the data to PHY register at the offset using the i2c interface. | |
302 | **/ | |
303 | s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) | |
304 | { | |
305 | struct e1000_phy_info *phy = &hw->phy; | |
306 | u32 i, i2ccmd = 0; | |
307 | u16 phy_data_swapped; | |
308 | ||
309 | ||
310 | /* Swap the data bytes for the I2C interface */ | |
311 | phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); | |
312 | ||
313 | /* | |
314 | * Set up Op-code, Phy Address, and register address in the I2CCMD | |
315 | * register. The MAC will take care of interfacing with the | |
316 | * PHY to retrieve the desired data. | |
317 | */ | |
318 | i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | | |
319 | (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | | |
320 | E1000_I2CCMD_OPCODE_WRITE | | |
321 | phy_data_swapped); | |
322 | ||
323 | wr32(E1000_I2CCMD, i2ccmd); | |
324 | ||
325 | /* Poll the ready bit to see if the I2C read completed */ | |
326 | for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { | |
327 | udelay(50); | |
328 | i2ccmd = rd32(E1000_I2CCMD); | |
329 | if (i2ccmd & E1000_I2CCMD_READY) | |
330 | break; | |
331 | } | |
332 | if (!(i2ccmd & E1000_I2CCMD_READY)) { | |
333 | hw_dbg("I2CCMD Write did not complete\n"); | |
334 | return -E1000_ERR_PHY; | |
335 | } | |
336 | if (i2ccmd & E1000_I2CCMD_ERROR) { | |
337 | hw_dbg("I2CCMD Error bit set\n"); | |
338 | return -E1000_ERR_PHY; | |
339 | } | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
9d5c8243 | 344 | /** |
733596be | 345 | * igb_read_phy_reg_igp - Read igp PHY register |
9d5c8243 AK |
346 | * @hw: pointer to the HW structure |
347 | * @offset: register offset to be read | |
348 | * @data: pointer to the read data | |
349 | * | |
350 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
351 | * and storing the retrieved information in data. Release any acquired | |
352 | * semaphores before exiting. | |
353 | **/ | |
354 | s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) | |
355 | { | |
a8d2a0c2 AD |
356 | s32 ret_val = 0; |
357 | ||
358 | if (!(hw->phy.ops.acquire)) | |
359 | goto out; | |
9d5c8243 | 360 | |
a8d2a0c2 | 361 | ret_val = hw->phy.ops.acquire(hw); |
9d5c8243 AK |
362 | if (ret_val) |
363 | goto out; | |
364 | ||
365 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
366 | ret_val = igb_write_phy_reg_mdic(hw, | |
367 | IGP01E1000_PHY_PAGE_SELECT, | |
368 | (u16)offset); | |
369 | if (ret_val) { | |
a8d2a0c2 | 370 | hw->phy.ops.release(hw); |
9d5c8243 AK |
371 | goto out; |
372 | } | |
373 | } | |
374 | ||
a8d2a0c2 AD |
375 | ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
376 | data); | |
9d5c8243 | 377 | |
a8d2a0c2 | 378 | hw->phy.ops.release(hw); |
9d5c8243 AK |
379 | |
380 | out: | |
381 | return ret_val; | |
382 | } | |
383 | ||
384 | /** | |
733596be | 385 | * igb_write_phy_reg_igp - Write igp PHY register |
9d5c8243 AK |
386 | * @hw: pointer to the HW structure |
387 | * @offset: register offset to write to | |
388 | * @data: data to write at register offset | |
389 | * | |
390 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
391 | * at the offset. Release any acquired semaphores before exiting. | |
392 | **/ | |
393 | s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) | |
394 | { | |
a8d2a0c2 | 395 | s32 ret_val = 0; |
9d5c8243 | 396 | |
a8d2a0c2 AD |
397 | if (!(hw->phy.ops.acquire)) |
398 | goto out; | |
399 | ||
400 | ret_val = hw->phy.ops.acquire(hw); | |
9d5c8243 AK |
401 | if (ret_val) |
402 | goto out; | |
403 | ||
404 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
405 | ret_val = igb_write_phy_reg_mdic(hw, | |
406 | IGP01E1000_PHY_PAGE_SELECT, | |
407 | (u16)offset); | |
408 | if (ret_val) { | |
a8d2a0c2 | 409 | hw->phy.ops.release(hw); |
9d5c8243 AK |
410 | goto out; |
411 | } | |
412 | } | |
413 | ||
a8d2a0c2 | 414 | ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
9d5c8243 AK |
415 | data); |
416 | ||
a8d2a0c2 | 417 | hw->phy.ops.release(hw); |
9d5c8243 AK |
418 | |
419 | out: | |
420 | return ret_val; | |
421 | } | |
422 | ||
2909c3f7 AD |
423 | /** |
424 | * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link | |
425 | * @hw: pointer to the HW structure | |
426 | * | |
427 | * Sets up Carrier-sense on Transmit and downshift values. | |
428 | **/ | |
429 | s32 igb_copper_link_setup_82580(struct e1000_hw *hw) | |
430 | { | |
431 | struct e1000_phy_info *phy = &hw->phy; | |
432 | s32 ret_val; | |
433 | u16 phy_data; | |
434 | ||
435 | ||
436 | if (phy->reset_disable) { | |
437 | ret_val = 0; | |
438 | goto out; | |
439 | } | |
440 | ||
441 | if (phy->type == e1000_phy_82580) { | |
442 | ret_val = hw->phy.ops.reset(hw); | |
443 | if (ret_val) { | |
444 | hw_dbg("Error resetting the PHY.\n"); | |
445 | goto out; | |
446 | } | |
447 | } | |
448 | ||
449 | /* Enable CRS on TX. This must be set for half-duplex operation. */ | |
450 | ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data); | |
451 | if (ret_val) | |
452 | goto out; | |
453 | ||
454 | phy_data |= I82580_CFG_ASSERT_CRS_ON_TX; | |
455 | ||
456 | /* Enable downshift */ | |
457 | phy_data |= I82580_CFG_ENABLE_DOWNSHIFT; | |
458 | ||
459 | ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); | |
2909c3f7 AD |
460 | |
461 | out: | |
462 | return ret_val; | |
463 | } | |
464 | ||
9d5c8243 | 465 | /** |
733596be | 466 | * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link |
9d5c8243 AK |
467 | * @hw: pointer to the HW structure |
468 | * | |
469 | * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock | |
470 | * and downshift values are set also. | |
471 | **/ | |
472 | s32 igb_copper_link_setup_m88(struct e1000_hw *hw) | |
473 | { | |
474 | struct e1000_phy_info *phy = &hw->phy; | |
475 | s32 ret_val; | |
476 | u16 phy_data; | |
477 | ||
478 | if (phy->reset_disable) { | |
479 | ret_val = 0; | |
480 | goto out; | |
481 | } | |
482 | ||
483 | /* Enable CRS on TX. This must be set for half-duplex operation. */ | |
a8d2a0c2 | 484 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
485 | if (ret_val) |
486 | goto out; | |
487 | ||
488 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
489 | ||
490 | /* | |
491 | * Options: | |
492 | * MDI/MDI-X = 0 (default) | |
493 | * 0 - Auto for all speeds | |
494 | * 1 - MDI mode | |
495 | * 2 - MDI-X mode | |
496 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
497 | */ | |
498 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
499 | ||
500 | switch (phy->mdix) { | |
501 | case 1: | |
502 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
503 | break; | |
504 | case 2: | |
505 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
506 | break; | |
507 | case 3: | |
508 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
509 | break; | |
510 | case 0: | |
511 | default: | |
512 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
513 | break; | |
514 | } | |
515 | ||
516 | /* | |
517 | * Options: | |
518 | * disable_polarity_correction = 0 (default) | |
519 | * Automatic Correction for Reversed Cable Polarity | |
520 | * 0 - Disabled | |
521 | * 1 - Enabled | |
522 | */ | |
523 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | |
524 | if (phy->disable_polarity_correction == 1) | |
525 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; | |
526 | ||
a8d2a0c2 | 527 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
9d5c8243 AK |
528 | if (ret_val) |
529 | goto out; | |
530 | ||
531 | if (phy->revision < E1000_REVISION_4) { | |
532 | /* | |
533 | * Force TX_CLK in the Extended PHY Specific Control Register | |
534 | * to 25MHz clock. | |
535 | */ | |
a8d2a0c2 | 536 | ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
9d5c8243 AK |
537 | &phy_data); |
538 | if (ret_val) | |
539 | goto out; | |
540 | ||
541 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
542 | ||
543 | if ((phy->revision == E1000_REVISION_2) && | |
544 | (phy->id == M88E1111_I_PHY_ID)) { | |
545 | /* 82573L PHY - set the downshift counter to 5x. */ | |
546 | phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; | |
547 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; | |
548 | } else { | |
549 | /* Configure Master and Slave downshift values */ | |
550 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | |
551 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); | |
552 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | | |
553 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); | |
554 | } | |
a8d2a0c2 | 555 | ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
9d5c8243 AK |
556 | phy_data); |
557 | if (ret_val) | |
558 | goto out; | |
559 | } | |
560 | ||
561 | /* Commit the changes. */ | |
562 | ret_val = igb_phy_sw_reset(hw); | |
563 | if (ret_val) { | |
652fff32 | 564 | hw_dbg("Error committing the PHY changes\n"); |
9d5c8243 AK |
565 | goto out; |
566 | } | |
567 | ||
568 | out: | |
569 | return ret_val; | |
570 | } | |
571 | ||
308fb39a JG |
572 | /** |
573 | * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link | |
574 | * @hw: pointer to the HW structure | |
575 | * | |
576 | * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. | |
577 | * Also enables and sets the downshift parameters. | |
578 | **/ | |
579 | s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw) | |
580 | { | |
581 | struct e1000_phy_info *phy = &hw->phy; | |
582 | s32 ret_val; | |
583 | u16 phy_data; | |
584 | ||
585 | if (phy->reset_disable) { | |
586 | ret_val = 0; | |
587 | goto out; | |
588 | } | |
589 | ||
590 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ | |
591 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
592 | if (ret_val) | |
593 | goto out; | |
594 | ||
595 | /* | |
596 | * Options: | |
597 | * MDI/MDI-X = 0 (default) | |
598 | * 0 - Auto for all speeds | |
599 | * 1 - MDI mode | |
600 | * 2 - MDI-X mode | |
601 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
602 | */ | |
603 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
604 | ||
605 | switch (phy->mdix) { | |
606 | case 1: | |
607 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
608 | break; | |
609 | case 2: | |
610 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
611 | break; | |
612 | case 3: | |
613 | /* M88E1112 does not support this mode) */ | |
614 | if (phy->id != M88E1112_E_PHY_ID) { | |
615 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
616 | break; | |
617 | } | |
618 | case 0: | |
619 | default: | |
620 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
621 | break; | |
622 | } | |
623 | ||
624 | /* | |
625 | * Options: | |
626 | * disable_polarity_correction = 0 (default) | |
627 | * Automatic Correction for Reversed Cable Polarity | |
628 | * 0 - Disabled | |
629 | * 1 - Enabled | |
630 | */ | |
631 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | |
632 | if (phy->disable_polarity_correction == 1) | |
633 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; | |
634 | ||
635 | /* Enable downshift and setting it to X6 */ | |
636 | phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; | |
637 | phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; | |
638 | phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; | |
639 | ||
640 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
641 | if (ret_val) | |
642 | goto out; | |
643 | ||
644 | /* Commit the changes. */ | |
645 | ret_val = igb_phy_sw_reset(hw); | |
646 | if (ret_val) { | |
647 | hw_dbg("Error committing the PHY changes\n"); | |
648 | goto out; | |
649 | } | |
650 | ||
651 | out: | |
652 | return ret_val; | |
653 | } | |
654 | ||
9d5c8243 | 655 | /** |
733596be | 656 | * igb_copper_link_setup_igp - Setup igp PHY's for copper link |
9d5c8243 AK |
657 | * @hw: pointer to the HW structure |
658 | * | |
659 | * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for | |
660 | * igp PHY's. | |
661 | **/ | |
662 | s32 igb_copper_link_setup_igp(struct e1000_hw *hw) | |
663 | { | |
664 | struct e1000_phy_info *phy = &hw->phy; | |
665 | s32 ret_val; | |
666 | u16 data; | |
667 | ||
668 | if (phy->reset_disable) { | |
669 | ret_val = 0; | |
670 | goto out; | |
671 | } | |
672 | ||
a8d2a0c2 | 673 | ret_val = phy->ops.reset(hw); |
9d5c8243 | 674 | if (ret_val) { |
652fff32 | 675 | hw_dbg("Error resetting the PHY.\n"); |
9d5c8243 AK |
676 | goto out; |
677 | } | |
678 | ||
a6a60569 AD |
679 | /* |
680 | * Wait 100ms for MAC to configure PHY from NVM settings, to avoid | |
681 | * timeout issues when LFS is enabled. | |
682 | */ | |
683 | msleep(100); | |
9d5c8243 AK |
684 | |
685 | /* | |
686 | * The NVM settings will configure LPLU in D3 for | |
687 | * non-IGP1 PHYs. | |
688 | */ | |
689 | if (phy->type == e1000_phy_igp) { | |
690 | /* disable lplu d3 during driver init */ | |
a8d2a0c2 AD |
691 | if (phy->ops.set_d3_lplu_state) |
692 | ret_val = phy->ops.set_d3_lplu_state(hw, false); | |
9d5c8243 | 693 | if (ret_val) { |
652fff32 | 694 | hw_dbg("Error Disabling LPLU D3\n"); |
9d5c8243 AK |
695 | goto out; |
696 | } | |
697 | } | |
698 | ||
699 | /* disable lplu d0 during driver init */ | |
a8d2a0c2 | 700 | ret_val = phy->ops.set_d0_lplu_state(hw, false); |
9d5c8243 | 701 | if (ret_val) { |
652fff32 | 702 | hw_dbg("Error Disabling LPLU D0\n"); |
9d5c8243 AK |
703 | goto out; |
704 | } | |
705 | /* Configure mdi-mdix settings */ | |
a8d2a0c2 | 706 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); |
9d5c8243 AK |
707 | if (ret_val) |
708 | goto out; | |
709 | ||
710 | data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
711 | ||
712 | switch (phy->mdix) { | |
713 | case 1: | |
714 | data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
715 | break; | |
716 | case 2: | |
717 | data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
718 | break; | |
719 | case 0: | |
720 | default: | |
721 | data |= IGP01E1000_PSCR_AUTO_MDIX; | |
722 | break; | |
723 | } | |
a8d2a0c2 | 724 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); |
9d5c8243 AK |
725 | if (ret_val) |
726 | goto out; | |
727 | ||
728 | /* set auto-master slave resolution settings */ | |
729 | if (hw->mac.autoneg) { | |
730 | /* | |
731 | * when autonegotiation advertisement is only 1000Mbps then we | |
732 | * should disable SmartSpeed and enable Auto MasterSlave | |
733 | * resolution as hardware default. | |
734 | */ | |
735 | if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { | |
736 | /* Disable SmartSpeed */ | |
a8d2a0c2 AD |
737 | ret_val = phy->ops.read_reg(hw, |
738 | IGP01E1000_PHY_PORT_CONFIG, | |
739 | &data); | |
9d5c8243 AK |
740 | if (ret_val) |
741 | goto out; | |
742 | ||
743 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 744 | ret_val = phy->ops.write_reg(hw, |
9d5c8243 AK |
745 | IGP01E1000_PHY_PORT_CONFIG, |
746 | data); | |
747 | if (ret_val) | |
748 | goto out; | |
749 | ||
750 | /* Set auto Master/Slave resolution process */ | |
a8d2a0c2 | 751 | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); |
9d5c8243 AK |
752 | if (ret_val) |
753 | goto out; | |
754 | ||
755 | data &= ~CR_1000T_MS_ENABLE; | |
a8d2a0c2 | 756 | ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); |
9d5c8243 AK |
757 | if (ret_val) |
758 | goto out; | |
759 | } | |
760 | ||
a8d2a0c2 | 761 | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); |
9d5c8243 AK |
762 | if (ret_val) |
763 | goto out; | |
764 | ||
765 | /* load defaults for future use */ | |
766 | phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? | |
767 | ((data & CR_1000T_MS_VALUE) ? | |
768 | e1000_ms_force_master : | |
769 | e1000_ms_force_slave) : | |
770 | e1000_ms_auto; | |
771 | ||
772 | switch (phy->ms_type) { | |
773 | case e1000_ms_force_master: | |
774 | data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | |
775 | break; | |
776 | case e1000_ms_force_slave: | |
777 | data |= CR_1000T_MS_ENABLE; | |
778 | data &= ~(CR_1000T_MS_VALUE); | |
779 | break; | |
780 | case e1000_ms_auto: | |
781 | data &= ~CR_1000T_MS_ENABLE; | |
782 | default: | |
783 | break; | |
784 | } | |
a8d2a0c2 | 785 | ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); |
9d5c8243 AK |
786 | if (ret_val) |
787 | goto out; | |
788 | } | |
789 | ||
790 | out: | |
791 | return ret_val; | |
792 | } | |
793 | ||
794 | /** | |
733596be | 795 | * igb_copper_link_autoneg - Setup/Enable autoneg for copper link |
9d5c8243 AK |
796 | * @hw: pointer to the HW structure |
797 | * | |
798 | * Performs initial bounds checking on autoneg advertisement parameter, then | |
799 | * configure to advertise the full capability. Setup the PHY to autoneg | |
800 | * and restart the negotiation process between the link partner. If | |
801 | * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. | |
802 | **/ | |
81fadd81 | 803 | static s32 igb_copper_link_autoneg(struct e1000_hw *hw) |
9d5c8243 AK |
804 | { |
805 | struct e1000_phy_info *phy = &hw->phy; | |
806 | s32 ret_val; | |
807 | u16 phy_ctrl; | |
808 | ||
809 | /* | |
810 | * Perform some bounds checking on the autoneg advertisement | |
811 | * parameter. | |
812 | */ | |
813 | phy->autoneg_advertised &= phy->autoneg_mask; | |
814 | ||
815 | /* | |
816 | * If autoneg_advertised is zero, we assume it was not defaulted | |
817 | * by the calling code so we set to advertise full capability. | |
818 | */ | |
819 | if (phy->autoneg_advertised == 0) | |
820 | phy->autoneg_advertised = phy->autoneg_mask; | |
821 | ||
652fff32 | 822 | hw_dbg("Reconfiguring auto-neg advertisement params\n"); |
9d5c8243 AK |
823 | ret_val = igb_phy_setup_autoneg(hw); |
824 | if (ret_val) { | |
652fff32 | 825 | hw_dbg("Error Setting up Auto-Negotiation\n"); |
9d5c8243 AK |
826 | goto out; |
827 | } | |
652fff32 | 828 | hw_dbg("Restarting Auto-Neg\n"); |
9d5c8243 AK |
829 | |
830 | /* | |
831 | * Restart auto-negotiation by setting the Auto Neg Enable bit and | |
832 | * the Auto Neg Restart bit in the PHY control register. | |
833 | */ | |
a8d2a0c2 | 834 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); |
9d5c8243 AK |
835 | if (ret_val) |
836 | goto out; | |
837 | ||
838 | phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); | |
a8d2a0c2 | 839 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); |
9d5c8243 AK |
840 | if (ret_val) |
841 | goto out; | |
842 | ||
843 | /* | |
844 | * Does the user want to wait for Auto-Neg to complete here, or | |
845 | * check at a later time (for example, callback routine). | |
846 | */ | |
847 | if (phy->autoneg_wait_to_complete) { | |
848 | ret_val = igb_wait_autoneg(hw); | |
849 | if (ret_val) { | |
652fff32 AK |
850 | hw_dbg("Error while waiting for " |
851 | "autoneg to complete\n"); | |
9d5c8243 AK |
852 | goto out; |
853 | } | |
854 | } | |
855 | ||
856 | hw->mac.get_link_status = true; | |
857 | ||
858 | out: | |
859 | return ret_val; | |
860 | } | |
861 | ||
862 | /** | |
733596be | 863 | * igb_phy_setup_autoneg - Configure PHY for auto-negotiation |
9d5c8243 AK |
864 | * @hw: pointer to the HW structure |
865 | * | |
866 | * Reads the MII auto-neg advertisement register and/or the 1000T control | |
867 | * register and if the PHY is already setup for auto-negotiation, then | |
868 | * return successful. Otherwise, setup advertisement and flow control to | |
869 | * the appropriate values for the wanted auto-negotiation. | |
870 | **/ | |
871 | static s32 igb_phy_setup_autoneg(struct e1000_hw *hw) | |
872 | { | |
873 | struct e1000_phy_info *phy = &hw->phy; | |
874 | s32 ret_val; | |
875 | u16 mii_autoneg_adv_reg; | |
876 | u16 mii_1000t_ctrl_reg = 0; | |
877 | ||
878 | phy->autoneg_advertised &= phy->autoneg_mask; | |
879 | ||
880 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
a8d2a0c2 | 881 | ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
9d5c8243 AK |
882 | if (ret_val) |
883 | goto out; | |
884 | ||
885 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
886 | /* Read the MII 1000Base-T Control Register (Address 9). */ | |
a8d2a0c2 | 887 | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, |
9d5c8243 AK |
888 | &mii_1000t_ctrl_reg); |
889 | if (ret_val) | |
890 | goto out; | |
891 | } | |
892 | ||
893 | /* | |
894 | * Need to parse both autoneg_advertised and fc and set up | |
895 | * the appropriate PHY registers. First we will parse for | |
896 | * autoneg_advertised software override. Since we can advertise | |
897 | * a plethora of combinations, we need to check each bit | |
898 | * individually. | |
899 | */ | |
900 | ||
901 | /* | |
902 | * First we clear all the 10/100 mb speed bits in the Auto-Neg | |
903 | * Advertisement Register (Address 4) and the 1000 mb speed bits in | |
904 | * the 1000Base-T Control Register (Address 9). | |
905 | */ | |
906 | mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | | |
907 | NWAY_AR_100TX_HD_CAPS | | |
908 | NWAY_AR_10T_FD_CAPS | | |
909 | NWAY_AR_10T_HD_CAPS); | |
910 | mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); | |
911 | ||
652fff32 | 912 | hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); |
9d5c8243 AK |
913 | |
914 | /* Do we want to advertise 10 Mb Half Duplex? */ | |
915 | if (phy->autoneg_advertised & ADVERTISE_10_HALF) { | |
652fff32 | 916 | hw_dbg("Advertise 10mb Half duplex\n"); |
9d5c8243 AK |
917 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
918 | } | |
919 | ||
920 | /* Do we want to advertise 10 Mb Full Duplex? */ | |
921 | if (phy->autoneg_advertised & ADVERTISE_10_FULL) { | |
652fff32 | 922 | hw_dbg("Advertise 10mb Full duplex\n"); |
9d5c8243 AK |
923 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
924 | } | |
925 | ||
926 | /* Do we want to advertise 100 Mb Half Duplex? */ | |
927 | if (phy->autoneg_advertised & ADVERTISE_100_HALF) { | |
652fff32 | 928 | hw_dbg("Advertise 100mb Half duplex\n"); |
9d5c8243 AK |
929 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
930 | } | |
931 | ||
932 | /* Do we want to advertise 100 Mb Full Duplex? */ | |
933 | if (phy->autoneg_advertised & ADVERTISE_100_FULL) { | |
652fff32 | 934 | hw_dbg("Advertise 100mb Full duplex\n"); |
9d5c8243 AK |
935 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
936 | } | |
937 | ||
938 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | |
939 | if (phy->autoneg_advertised & ADVERTISE_1000_HALF) | |
652fff32 | 940 | hw_dbg("Advertise 1000mb Half duplex request denied!\n"); |
9d5c8243 AK |
941 | |
942 | /* Do we want to advertise 1000 Mb Full Duplex? */ | |
943 | if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { | |
652fff32 | 944 | hw_dbg("Advertise 1000mb Full duplex\n"); |
9d5c8243 AK |
945 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
946 | } | |
947 | ||
948 | /* | |
949 | * Check for a software override of the flow control settings, and | |
950 | * setup the PHY advertisement registers accordingly. If | |
951 | * auto-negotiation is enabled, then software will have to set the | |
952 | * "PAUSE" bits to the correct value in the Auto-Negotiation | |
953 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- | |
954 | * negotiation. | |
955 | * | |
956 | * The possible values of the "fc" parameter are: | |
957 | * 0: Flow control is completely disabled | |
958 | * 1: Rx flow control is enabled (we can receive pause frames | |
959 | * but not send pause frames). | |
960 | * 2: Tx flow control is enabled (we can send pause frames | |
961 | * but we do not support receiving pause frames). | |
962 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
963 | * other: No software override. The flow control configuration | |
964 | * in the EEPROM is used. | |
965 | */ | |
0cce119a | 966 | switch (hw->fc.current_mode) { |
9d5c8243 AK |
967 | case e1000_fc_none: |
968 | /* | |
969 | * Flow control (RX & TX) is completely disabled by a | |
970 | * software over-ride. | |
971 | */ | |
972 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
973 | break; | |
974 | case e1000_fc_rx_pause: | |
975 | /* | |
976 | * RX Flow control is enabled, and TX Flow control is | |
977 | * disabled, by a software over-ride. | |
978 | * | |
979 | * Since there really isn't a way to advertise that we are | |
980 | * capable of RX Pause ONLY, we will advertise that we | |
981 | * support both symmetric and asymmetric RX PAUSE. Later | |
982 | * (in e1000_config_fc_after_link_up) we will disable the | |
983 | * hw's ability to send PAUSE frames. | |
984 | */ | |
985 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
986 | break; | |
987 | case e1000_fc_tx_pause: | |
988 | /* | |
989 | * TX Flow control is enabled, and RX Flow control is | |
990 | * disabled, by a software over-ride. | |
991 | */ | |
992 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | |
993 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | |
994 | break; | |
995 | case e1000_fc_full: | |
996 | /* | |
997 | * Flow control (both RX and TX) is enabled by a software | |
998 | * over-ride. | |
999 | */ | |
1000 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1001 | break; | |
1002 | default: | |
652fff32 | 1003 | hw_dbg("Flow control param set incorrectly\n"); |
9d5c8243 AK |
1004 | ret_val = -E1000_ERR_CONFIG; |
1005 | goto out; | |
1006 | } | |
1007 | ||
a8d2a0c2 | 1008 | ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
9d5c8243 AK |
1009 | if (ret_val) |
1010 | goto out; | |
1011 | ||
652fff32 | 1012 | hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
9d5c8243 AK |
1013 | |
1014 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
a8d2a0c2 AD |
1015 | ret_val = phy->ops.write_reg(hw, |
1016 | PHY_1000T_CTRL, | |
1017 | mii_1000t_ctrl_reg); | |
9d5c8243 AK |
1018 | if (ret_val) |
1019 | goto out; | |
1020 | } | |
1021 | ||
1022 | out: | |
1023 | return ret_val; | |
1024 | } | |
1025 | ||
81fadd81 AD |
1026 | /** |
1027 | * igb_setup_copper_link - Configure copper link settings | |
1028 | * @hw: pointer to the HW structure | |
1029 | * | |
1030 | * Calls the appropriate function to configure the link for auto-neg or forced | |
1031 | * speed and duplex. Then we check for link, once link is established calls | |
1032 | * to configure collision distance and flow control are called. If link is | |
1033 | * not established, we return -E1000_ERR_PHY (-2). | |
1034 | **/ | |
1035 | s32 igb_setup_copper_link(struct e1000_hw *hw) | |
1036 | { | |
1037 | s32 ret_val; | |
1038 | bool link; | |
1039 | ||
1040 | ||
1041 | if (hw->mac.autoneg) { | |
1042 | /* | |
1043 | * Setup autoneg and flow control advertisement and perform | |
1044 | * autonegotiation. | |
1045 | */ | |
1046 | ret_val = igb_copper_link_autoneg(hw); | |
1047 | if (ret_val) | |
1048 | goto out; | |
1049 | } else { | |
1050 | /* | |
1051 | * PHY will be set to 10H, 10F, 100H or 100F | |
1052 | * depending on user settings. | |
1053 | */ | |
1054 | hw_dbg("Forcing Speed and Duplex\n"); | |
1055 | ret_val = hw->phy.ops.force_speed_duplex(hw); | |
1056 | if (ret_val) { | |
1057 | hw_dbg("Error Forcing Speed and Duplex\n"); | |
1058 | goto out; | |
1059 | } | |
1060 | } | |
1061 | ||
1062 | /* | |
1063 | * Check link status. Wait up to 100 microseconds for link to become | |
1064 | * valid. | |
1065 | */ | |
1066 | ret_val = igb_phy_has_link(hw, | |
1067 | COPPER_LINK_UP_LIMIT, | |
1068 | 10, | |
1069 | &link); | |
1070 | if (ret_val) | |
1071 | goto out; | |
1072 | ||
1073 | if (link) { | |
1074 | hw_dbg("Valid link established!!!\n"); | |
1075 | igb_config_collision_dist(hw); | |
1076 | ret_val = igb_config_fc_after_link_up(hw); | |
1077 | } else { | |
1078 | hw_dbg("Unable to establish link!!!\n"); | |
1079 | } | |
1080 | ||
1081 | out: | |
1082 | return ret_val; | |
1083 | } | |
1084 | ||
9d5c8243 | 1085 | /** |
733596be | 1086 | * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY |
9d5c8243 AK |
1087 | * @hw: pointer to the HW structure |
1088 | * | |
1089 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1090 | * auto-crossover to force MDI manually. Waits for link and returns | |
1091 | * successful if link up is successful, else -E1000_ERR_PHY (-2). | |
1092 | **/ | |
1093 | s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw) | |
1094 | { | |
1095 | struct e1000_phy_info *phy = &hw->phy; | |
1096 | s32 ret_val; | |
1097 | u16 phy_data; | |
1098 | bool link; | |
1099 | ||
a8d2a0c2 | 1100 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
9d5c8243 AK |
1101 | if (ret_val) |
1102 | goto out; | |
1103 | ||
1104 | igb_phy_force_speed_duplex_setup(hw, &phy_data); | |
1105 | ||
a8d2a0c2 | 1106 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); |
9d5c8243 AK |
1107 | if (ret_val) |
1108 | goto out; | |
1109 | ||
1110 | /* | |
1111 | * Clear Auto-Crossover to force MDI manually. IGP requires MDI | |
1112 | * forced whenever speed and duplex are forced. | |
1113 | */ | |
a8d2a0c2 | 1114 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
9d5c8243 AK |
1115 | if (ret_val) |
1116 | goto out; | |
1117 | ||
1118 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
1119 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1120 | ||
a8d2a0c2 | 1121 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
9d5c8243 AK |
1122 | if (ret_val) |
1123 | goto out; | |
1124 | ||
652fff32 | 1125 | hw_dbg("IGP PSCR: %X\n", phy_data); |
9d5c8243 AK |
1126 | |
1127 | udelay(1); | |
1128 | ||
1129 | if (phy->autoneg_wait_to_complete) { | |
652fff32 | 1130 | hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); |
9d5c8243 AK |
1131 | |
1132 | ret_val = igb_phy_has_link(hw, | |
1133 | PHY_FORCE_LIMIT, | |
1134 | 100000, | |
1135 | &link); | |
1136 | if (ret_val) | |
1137 | goto out; | |
1138 | ||
1139 | if (!link) | |
652fff32 | 1140 | hw_dbg("Link taking longer than expected.\n"); |
9d5c8243 AK |
1141 | |
1142 | /* Try once more */ | |
1143 | ret_val = igb_phy_has_link(hw, | |
1144 | PHY_FORCE_LIMIT, | |
1145 | 100000, | |
1146 | &link); | |
1147 | if (ret_val) | |
1148 | goto out; | |
1149 | } | |
1150 | ||
1151 | out: | |
1152 | return ret_val; | |
1153 | } | |
1154 | ||
1155 | /** | |
733596be | 1156 | * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY |
9d5c8243 AK |
1157 | * @hw: pointer to the HW structure |
1158 | * | |
1159 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1160 | * auto-crossover to force MDI manually. Resets the PHY to commit the | |
1161 | * changes. If time expires while waiting for link up, we reset the DSP. | |
1162 | * After reset, TX_CLK and CRS on TX must be set. Return successful upon | |
1163 | * successful completion, else return corresponding error code. | |
1164 | **/ | |
1165 | s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw) | |
1166 | { | |
1167 | struct e1000_phy_info *phy = &hw->phy; | |
1168 | s32 ret_val; | |
1169 | u16 phy_data; | |
1170 | bool link; | |
1171 | ||
1172 | /* | |
1173 | * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
1174 | * forced whenever speed and duplex are forced. | |
1175 | */ | |
a8d2a0c2 | 1176 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
1177 | if (ret_val) |
1178 | goto out; | |
1179 | ||
1180 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
a8d2a0c2 | 1181 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
9d5c8243 AK |
1182 | if (ret_val) |
1183 | goto out; | |
1184 | ||
652fff32 | 1185 | hw_dbg("M88E1000 PSCR: %X\n", phy_data); |
9d5c8243 | 1186 | |
a8d2a0c2 | 1187 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
9d5c8243 AK |
1188 | if (ret_val) |
1189 | goto out; | |
1190 | ||
1191 | igb_phy_force_speed_duplex_setup(hw, &phy_data); | |
1192 | ||
a8d2a0c2 | 1193 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); |
9d5c8243 AK |
1194 | if (ret_val) |
1195 | goto out; | |
1196 | ||
2553bb26 AD |
1197 | /* Reset the phy to commit changes. */ |
1198 | ret_val = igb_phy_sw_reset(hw); | |
1199 | if (ret_val) | |
1200 | goto out; | |
9d5c8243 AK |
1201 | |
1202 | if (phy->autoneg_wait_to_complete) { | |
652fff32 | 1203 | hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); |
9d5c8243 | 1204 | |
2553bb26 | 1205 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); |
9d5c8243 AK |
1206 | if (ret_val) |
1207 | goto out; | |
1208 | ||
1209 | if (!link) { | |
308fb39a JG |
1210 | if (hw->phy.type != e1000_phy_m88 || |
1211 | hw->phy.id == I347AT4_E_PHY_ID || | |
1212 | hw->phy.id == M88E1112_E_PHY_ID) { | |
1213 | hw_dbg("Link taking longer than expected.\n"); | |
1214 | } else { | |
1215 | ||
1216 | /* | |
1217 | * We didn't get link. | |
1218 | * Reset the DSP and cross our fingers. | |
1219 | */ | |
1220 | ret_val = phy->ops.write_reg(hw, | |
1221 | M88E1000_PHY_PAGE_SELECT, | |
1222 | 0x001d); | |
1223 | if (ret_val) | |
1224 | goto out; | |
1225 | ret_val = igb_phy_reset_dsp(hw); | |
1226 | if (ret_val) | |
1227 | goto out; | |
1228 | } | |
9d5c8243 AK |
1229 | } |
1230 | ||
1231 | /* Try once more */ | |
1232 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, | |
2553bb26 | 1233 | 100000, &link); |
9d5c8243 AK |
1234 | if (ret_val) |
1235 | goto out; | |
1236 | } | |
1237 | ||
308fb39a JG |
1238 | if (hw->phy.type != e1000_phy_m88 || |
1239 | hw->phy.id == I347AT4_E_PHY_ID || | |
1240 | hw->phy.id == M88E1112_E_PHY_ID) | |
1241 | goto out; | |
1242 | ||
a8d2a0c2 | 1243 | ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
1244 | if (ret_val) |
1245 | goto out; | |
1246 | ||
1247 | /* | |
1248 | * Resetting the phy means we need to re-force TX_CLK in the | |
1249 | * Extended PHY Specific Control Register to 25MHz clock from | |
1250 | * the reset value of 2.5MHz. | |
1251 | */ | |
1252 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
a8d2a0c2 | 1253 | ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
9d5c8243 AK |
1254 | if (ret_val) |
1255 | goto out; | |
1256 | ||
1257 | /* | |
1258 | * In addition, we must re-enable CRS on Tx for both half and full | |
1259 | * duplex. | |
1260 | */ | |
a8d2a0c2 | 1261 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
1262 | if (ret_val) |
1263 | goto out; | |
1264 | ||
1265 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
a8d2a0c2 | 1266 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
9d5c8243 AK |
1267 | |
1268 | out: | |
1269 | return ret_val; | |
1270 | } | |
1271 | ||
1272 | /** | |
733596be | 1273 | * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex |
9d5c8243 AK |
1274 | * @hw: pointer to the HW structure |
1275 | * @phy_ctrl: pointer to current value of PHY_CONTROL | |
1276 | * | |
1277 | * Forces speed and duplex on the PHY by doing the following: disable flow | |
1278 | * control, force speed/duplex on the MAC, disable auto speed detection, | |
1279 | * disable auto-negotiation, configure duplex, configure speed, configure | |
1280 | * the collision distance, write configuration to CTRL register. The | |
1281 | * caller must write to the PHY_CONTROL register for these settings to | |
1282 | * take affect. | |
1283 | **/ | |
1284 | static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, | |
1285 | u16 *phy_ctrl) | |
1286 | { | |
1287 | struct e1000_mac_info *mac = &hw->mac; | |
1288 | u32 ctrl; | |
1289 | ||
1290 | /* Turn off flow control when forcing speed/duplex */ | |
0cce119a | 1291 | hw->fc.current_mode = e1000_fc_none; |
9d5c8243 AK |
1292 | |
1293 | /* Force speed/duplex on the mac */ | |
1294 | ctrl = rd32(E1000_CTRL); | |
1295 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1296 | ctrl &= ~E1000_CTRL_SPD_SEL; | |
1297 | ||
1298 | /* Disable Auto Speed Detection */ | |
1299 | ctrl &= ~E1000_CTRL_ASDE; | |
1300 | ||
1301 | /* Disable autoneg on the phy */ | |
1302 | *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; | |
1303 | ||
1304 | /* Forcing Full or Half Duplex? */ | |
1305 | if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { | |
1306 | ctrl &= ~E1000_CTRL_FD; | |
1307 | *phy_ctrl &= ~MII_CR_FULL_DUPLEX; | |
652fff32 | 1308 | hw_dbg("Half Duplex\n"); |
9d5c8243 AK |
1309 | } else { |
1310 | ctrl |= E1000_CTRL_FD; | |
1311 | *phy_ctrl |= MII_CR_FULL_DUPLEX; | |
652fff32 | 1312 | hw_dbg("Full Duplex\n"); |
9d5c8243 AK |
1313 | } |
1314 | ||
1315 | /* Forcing 10mb or 100mb? */ | |
1316 | if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { | |
1317 | ctrl |= E1000_CTRL_SPD_100; | |
1318 | *phy_ctrl |= MII_CR_SPEED_100; | |
1319 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); | |
652fff32 | 1320 | hw_dbg("Forcing 100mb\n"); |
9d5c8243 AK |
1321 | } else { |
1322 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | |
1323 | *phy_ctrl |= MII_CR_SPEED_10; | |
1324 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); | |
652fff32 | 1325 | hw_dbg("Forcing 10mb\n"); |
9d5c8243 AK |
1326 | } |
1327 | ||
1328 | igb_config_collision_dist(hw); | |
1329 | ||
1330 | wr32(E1000_CTRL, ctrl); | |
1331 | } | |
1332 | ||
1333 | /** | |
733596be | 1334 | * igb_set_d3_lplu_state - Sets low power link up state for D3 |
9d5c8243 AK |
1335 | * @hw: pointer to the HW structure |
1336 | * @active: boolean used to enable/disable lplu | |
1337 | * | |
1338 | * Success returns 0, Failure returns 1 | |
1339 | * | |
1340 | * The low power link up (lplu) state is set to the power management level D3 | |
1341 | * and SmartSpeed is disabled when active is true, else clear lplu for D3 | |
1342 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU | |
1343 | * is used during Dx states where the power conservation is most important. | |
1344 | * During driver activity, SmartSpeed should be enabled so performance is | |
1345 | * maintained. | |
1346 | **/ | |
1347 | s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active) | |
1348 | { | |
1349 | struct e1000_phy_info *phy = &hw->phy; | |
2553bb26 | 1350 | s32 ret_val = 0; |
9d5c8243 AK |
1351 | u16 data; |
1352 | ||
2553bb26 AD |
1353 | if (!(hw->phy.ops.read_reg)) |
1354 | goto out; | |
1355 | ||
a8d2a0c2 | 1356 | ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
9d5c8243 AK |
1357 | if (ret_val) |
1358 | goto out; | |
1359 | ||
1360 | if (!active) { | |
1361 | data &= ~IGP02E1000_PM_D3_LPLU; | |
a8d2a0c2 | 1362 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
9d5c8243 AK |
1363 | data); |
1364 | if (ret_val) | |
1365 | goto out; | |
1366 | /* | |
1367 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
1368 | * during Dx states where the power conservation is most | |
1369 | * important. During driver activity we should enable | |
1370 | * SmartSpeed, so performance is maintained. | |
1371 | */ | |
1372 | if (phy->smart_speed == e1000_smart_speed_on) { | |
a8d2a0c2 | 1373 | ret_val = phy->ops.read_reg(hw, |
9d5c8243 AK |
1374 | IGP01E1000_PHY_PORT_CONFIG, |
1375 | &data); | |
1376 | if (ret_val) | |
1377 | goto out; | |
1378 | ||
1379 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 1380 | ret_val = phy->ops.write_reg(hw, |
9d5c8243 AK |
1381 | IGP01E1000_PHY_PORT_CONFIG, |
1382 | data); | |
1383 | if (ret_val) | |
1384 | goto out; | |
1385 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
a8d2a0c2 | 1386 | ret_val = phy->ops.read_reg(hw, |
9d5c8243 AK |
1387 | IGP01E1000_PHY_PORT_CONFIG, |
1388 | &data); | |
1389 | if (ret_val) | |
1390 | goto out; | |
1391 | ||
1392 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 1393 | ret_val = phy->ops.write_reg(hw, |
9d5c8243 AK |
1394 | IGP01E1000_PHY_PORT_CONFIG, |
1395 | data); | |
1396 | if (ret_val) | |
1397 | goto out; | |
1398 | } | |
1399 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
1400 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
1401 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
1402 | data |= IGP02E1000_PM_D3_LPLU; | |
a8d2a0c2 | 1403 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
9d5c8243 AK |
1404 | data); |
1405 | if (ret_val) | |
1406 | goto out; | |
1407 | ||
1408 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
a8d2a0c2 | 1409 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
9d5c8243 AK |
1410 | &data); |
1411 | if (ret_val) | |
1412 | goto out; | |
1413 | ||
1414 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 1415 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
9d5c8243 AK |
1416 | data); |
1417 | } | |
1418 | ||
1419 | out: | |
1420 | return ret_val; | |
1421 | } | |
1422 | ||
1423 | /** | |
733596be | 1424 | * igb_check_downshift - Checks whether a downshift in speed occured |
9d5c8243 AK |
1425 | * @hw: pointer to the HW structure |
1426 | * | |
1427 | * Success returns 0, Failure returns 1 | |
1428 | * | |
1429 | * A downshift is detected by querying the PHY link health. | |
1430 | **/ | |
1431 | s32 igb_check_downshift(struct e1000_hw *hw) | |
1432 | { | |
1433 | struct e1000_phy_info *phy = &hw->phy; | |
1434 | s32 ret_val; | |
1435 | u16 phy_data, offset, mask; | |
1436 | ||
1437 | switch (phy->type) { | |
1438 | case e1000_phy_m88: | |
1439 | case e1000_phy_gg82563: | |
1440 | offset = M88E1000_PHY_SPEC_STATUS; | |
1441 | mask = M88E1000_PSSR_DOWNSHIFT; | |
1442 | break; | |
1443 | case e1000_phy_igp_2: | |
1444 | case e1000_phy_igp: | |
1445 | case e1000_phy_igp_3: | |
1446 | offset = IGP01E1000_PHY_LINK_HEALTH; | |
1447 | mask = IGP01E1000_PLHR_SS_DOWNGRADE; | |
1448 | break; | |
1449 | default: | |
1450 | /* speed downshift not supported */ | |
1451 | phy->speed_downgraded = false; | |
1452 | ret_val = 0; | |
1453 | goto out; | |
1454 | } | |
1455 | ||
a8d2a0c2 | 1456 | ret_val = phy->ops.read_reg(hw, offset, &phy_data); |
9d5c8243 AK |
1457 | |
1458 | if (!ret_val) | |
1459 | phy->speed_downgraded = (phy_data & mask) ? true : false; | |
1460 | ||
1461 | out: | |
1462 | return ret_val; | |
1463 | } | |
1464 | ||
1465 | /** | |
733596be | 1466 | * igb_check_polarity_m88 - Checks the polarity. |
9d5c8243 AK |
1467 | * @hw: pointer to the HW structure |
1468 | * | |
1469 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1470 | * | |
1471 | * Polarity is determined based on the PHY specific status register. | |
1472 | **/ | |
1473 | static s32 igb_check_polarity_m88(struct e1000_hw *hw) | |
1474 | { | |
1475 | struct e1000_phy_info *phy = &hw->phy; | |
1476 | s32 ret_val; | |
1477 | u16 data; | |
1478 | ||
a8d2a0c2 | 1479 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); |
9d5c8243 AK |
1480 | |
1481 | if (!ret_val) | |
1482 | phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) | |
1483 | ? e1000_rev_polarity_reversed | |
1484 | : e1000_rev_polarity_normal; | |
1485 | ||
1486 | return ret_val; | |
1487 | } | |
1488 | ||
1489 | /** | |
733596be | 1490 | * igb_check_polarity_igp - Checks the polarity. |
9d5c8243 AK |
1491 | * @hw: pointer to the HW structure |
1492 | * | |
1493 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1494 | * | |
1495 | * Polarity is determined based on the PHY port status register, and the | |
1496 | * current speed (since there is no polarity at 100Mbps). | |
1497 | **/ | |
1498 | static s32 igb_check_polarity_igp(struct e1000_hw *hw) | |
1499 | { | |
1500 | struct e1000_phy_info *phy = &hw->phy; | |
1501 | s32 ret_val; | |
1502 | u16 data, offset, mask; | |
1503 | ||
1504 | /* | |
1505 | * Polarity is determined based on the speed of | |
1506 | * our connection. | |
1507 | */ | |
a8d2a0c2 | 1508 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
9d5c8243 AK |
1509 | if (ret_val) |
1510 | goto out; | |
1511 | ||
1512 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
1513 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
1514 | offset = IGP01E1000_PHY_PCS_INIT_REG; | |
1515 | mask = IGP01E1000_PHY_POLARITY_MASK; | |
1516 | } else { | |
1517 | /* | |
1518 | * This really only applies to 10Mbps since | |
1519 | * there is no polarity for 100Mbps (always 0). | |
1520 | */ | |
1521 | offset = IGP01E1000_PHY_PORT_STATUS; | |
1522 | mask = IGP01E1000_PSSR_POLARITY_REVERSED; | |
1523 | } | |
1524 | ||
a8d2a0c2 | 1525 | ret_val = phy->ops.read_reg(hw, offset, &data); |
9d5c8243 AK |
1526 | |
1527 | if (!ret_val) | |
1528 | phy->cable_polarity = (data & mask) | |
1529 | ? e1000_rev_polarity_reversed | |
1530 | : e1000_rev_polarity_normal; | |
1531 | ||
1532 | out: | |
1533 | return ret_val; | |
1534 | } | |
1535 | ||
1536 | /** | |
733596be | 1537 | * igb_wait_autoneg - Wait for auto-neg compeletion |
9d5c8243 AK |
1538 | * @hw: pointer to the HW structure |
1539 | * | |
1540 | * Waits for auto-negotiation to complete or for the auto-negotiation time | |
1541 | * limit to expire, which ever happens first. | |
1542 | **/ | |
1543 | static s32 igb_wait_autoneg(struct e1000_hw *hw) | |
1544 | { | |
1545 | s32 ret_val = 0; | |
1546 | u16 i, phy_status; | |
1547 | ||
1548 | /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ | |
1549 | for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { | |
a8d2a0c2 | 1550 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
9d5c8243 AK |
1551 | if (ret_val) |
1552 | break; | |
a8d2a0c2 | 1553 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
9d5c8243 AK |
1554 | if (ret_val) |
1555 | break; | |
1556 | if (phy_status & MII_SR_AUTONEG_COMPLETE) | |
1557 | break; | |
1558 | msleep(100); | |
1559 | } | |
1560 | ||
1561 | /* | |
1562 | * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation | |
1563 | * has completed. | |
1564 | */ | |
1565 | return ret_val; | |
1566 | } | |
1567 | ||
1568 | /** | |
733596be | 1569 | * igb_phy_has_link - Polls PHY for link |
9d5c8243 AK |
1570 | * @hw: pointer to the HW structure |
1571 | * @iterations: number of times to poll for link | |
1572 | * @usec_interval: delay between polling attempts | |
1573 | * @success: pointer to whether polling was successful or not | |
1574 | * | |
1575 | * Polls the PHY status register for link, 'iterations' number of times. | |
1576 | **/ | |
1577 | s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, | |
1578 | u32 usec_interval, bool *success) | |
1579 | { | |
1580 | s32 ret_val = 0; | |
1581 | u16 i, phy_status; | |
1582 | ||
1583 | for (i = 0; i < iterations; i++) { | |
1584 | /* | |
1585 | * Some PHYs require the PHY_STATUS register to be read | |
1586 | * twice due to the link bit being sticky. No harm doing | |
1587 | * it across the board. | |
1588 | */ | |
a8d2a0c2 | 1589 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
ab576389 AD |
1590 | if (ret_val) { |
1591 | /* | |
1592 | * If the first read fails, another entity may have | |
1593 | * ownership of the resources, wait and try again to | |
1594 | * see if they have relinquished the resources yet. | |
1595 | */ | |
1596 | udelay(usec_interval); | |
1597 | } | |
a8d2a0c2 | 1598 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
9d5c8243 AK |
1599 | if (ret_val) |
1600 | break; | |
1601 | if (phy_status & MII_SR_LINK_STATUS) | |
1602 | break; | |
1603 | if (usec_interval >= 1000) | |
1604 | mdelay(usec_interval/1000); | |
1605 | else | |
1606 | udelay(usec_interval); | |
1607 | } | |
1608 | ||
1609 | *success = (i < iterations) ? true : false; | |
1610 | ||
1611 | return ret_val; | |
1612 | } | |
1613 | ||
1614 | /** | |
733596be | 1615 | * igb_get_cable_length_m88 - Determine cable length for m88 PHY |
9d5c8243 AK |
1616 | * @hw: pointer to the HW structure |
1617 | * | |
1618 | * Reads the PHY specific status register to retrieve the cable length | |
1619 | * information. The cable length is determined by averaging the minimum and | |
1620 | * maximum values to get the "average" cable length. The m88 PHY has four | |
1621 | * possible cable length values, which are: | |
1622 | * Register Value Cable Length | |
1623 | * 0 < 50 meters | |
1624 | * 1 50 - 80 meters | |
1625 | * 2 80 - 110 meters | |
1626 | * 3 110 - 140 meters | |
1627 | * 4 > 140 meters | |
1628 | **/ | |
1629 | s32 igb_get_cable_length_m88(struct e1000_hw *hw) | |
1630 | { | |
1631 | struct e1000_phy_info *phy = &hw->phy; | |
1632 | s32 ret_val; | |
1633 | u16 phy_data, index; | |
1634 | ||
a8d2a0c2 | 1635 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
9d5c8243 AK |
1636 | if (ret_val) |
1637 | goto out; | |
1638 | ||
1639 | index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
1640 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; | |
2553bb26 AD |
1641 | if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { |
1642 | ret_val = -E1000_ERR_PHY; | |
1643 | goto out; | |
1644 | } | |
1645 | ||
9d5c8243 | 1646 | phy->min_cable_length = e1000_m88_cable_length_table[index]; |
2553bb26 | 1647 | phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; |
9d5c8243 AK |
1648 | |
1649 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1650 | ||
1651 | out: | |
1652 | return ret_val; | |
1653 | } | |
1654 | ||
308fb39a JG |
1655 | s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw) |
1656 | { | |
1657 | struct e1000_phy_info *phy = &hw->phy; | |
1658 | s32 ret_val; | |
1659 | u16 phy_data, phy_data2, index, default_page, is_cm; | |
1660 | ||
1661 | switch (hw->phy.id) { | |
1662 | case I347AT4_E_PHY_ID: | |
1663 | /* Remember the original page select and set it to 7 */ | |
1664 | ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, | |
1665 | &default_page); | |
1666 | if (ret_val) | |
1667 | goto out; | |
1668 | ||
1669 | ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); | |
1670 | if (ret_val) | |
1671 | goto out; | |
1672 | ||
1673 | /* Get cable length from PHY Cable Diagnostics Control Reg */ | |
1674 | ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), | |
1675 | &phy_data); | |
1676 | if (ret_val) | |
1677 | goto out; | |
1678 | ||
1679 | /* Check if the unit of cable length is meters or cm */ | |
1680 | ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); | |
1681 | if (ret_val) | |
1682 | goto out; | |
1683 | ||
1684 | is_cm = !(phy_data & I347AT4_PCDC_CABLE_LENGTH_UNIT); | |
1685 | ||
1686 | /* Populate the phy structure with cable length in meters */ | |
1687 | phy->min_cable_length = phy_data / (is_cm ? 100 : 1); | |
1688 | phy->max_cable_length = phy_data / (is_cm ? 100 : 1); | |
1689 | phy->cable_length = phy_data / (is_cm ? 100 : 1); | |
1690 | ||
1691 | /* Reset the page selec to its original value */ | |
1692 | ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, | |
1693 | default_page); | |
1694 | if (ret_val) | |
1695 | goto out; | |
1696 | break; | |
1697 | case M88E1112_E_PHY_ID: | |
1698 | /* Remember the original page select and set it to 5 */ | |
1699 | ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, | |
1700 | &default_page); | |
1701 | if (ret_val) | |
1702 | goto out; | |
1703 | ||
1704 | ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); | |
1705 | if (ret_val) | |
1706 | goto out; | |
1707 | ||
1708 | ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, | |
1709 | &phy_data); | |
1710 | if (ret_val) | |
1711 | goto out; | |
1712 | ||
1713 | index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
1714 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; | |
1715 | if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { | |
1716 | ret_val = -E1000_ERR_PHY; | |
1717 | goto out; | |
1718 | } | |
1719 | ||
1720 | phy->min_cable_length = e1000_m88_cable_length_table[index]; | |
1721 | phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; | |
1722 | ||
1723 | phy->cable_length = (phy->min_cable_length + | |
1724 | phy->max_cable_length) / 2; | |
1725 | ||
1726 | /* Reset the page select to its original value */ | |
1727 | ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, | |
1728 | default_page); | |
1729 | if (ret_val) | |
1730 | goto out; | |
1731 | ||
1732 | break; | |
1733 | default: | |
1734 | ret_val = -E1000_ERR_PHY; | |
1735 | goto out; | |
1736 | } | |
1737 | ||
1738 | out: | |
1739 | return ret_val; | |
1740 | } | |
1741 | ||
9d5c8243 | 1742 | /** |
733596be | 1743 | * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY |
9d5c8243 AK |
1744 | * @hw: pointer to the HW structure |
1745 | * | |
1746 | * The automatic gain control (agc) normalizes the amplitude of the | |
1747 | * received signal, adjusting for the attenuation produced by the | |
a8d2a0c2 AD |
1748 | * cable. By reading the AGC registers, which represent the |
1749 | * combination of coarse and fine gain value, the value can be put | |
9d5c8243 AK |
1750 | * into a lookup table to obtain the approximate cable length |
1751 | * for each channel. | |
1752 | **/ | |
1753 | s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) | |
1754 | { | |
1755 | struct e1000_phy_info *phy = &hw->phy; | |
1756 | s32 ret_val = 0; | |
1757 | u16 phy_data, i, agc_value = 0; | |
1758 | u16 cur_agc_index, max_agc_index = 0; | |
1759 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; | |
66744500 JK |
1760 | static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { |
1761 | IGP02E1000_PHY_AGC_A, | |
1762 | IGP02E1000_PHY_AGC_B, | |
1763 | IGP02E1000_PHY_AGC_C, | |
1764 | IGP02E1000_PHY_AGC_D | |
1765 | }; | |
9d5c8243 AK |
1766 | |
1767 | /* Read the AGC registers for all channels */ | |
1768 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | |
a8d2a0c2 | 1769 | ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); |
9d5c8243 AK |
1770 | if (ret_val) |
1771 | goto out; | |
1772 | ||
1773 | /* | |
1774 | * Getting bits 15:9, which represent the combination of | |
a8d2a0c2 | 1775 | * coarse and fine gain values. The result is a number |
9d5c8243 AK |
1776 | * that can be put into the lookup table to obtain the |
1777 | * approximate cable length. | |
1778 | */ | |
1779 | cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & | |
1780 | IGP02E1000_AGC_LENGTH_MASK; | |
1781 | ||
1782 | /* Array index bound check. */ | |
1783 | if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || | |
1784 | (cur_agc_index == 0)) { | |
1785 | ret_val = -E1000_ERR_PHY; | |
1786 | goto out; | |
1787 | } | |
1788 | ||
1789 | /* Remove min & max AGC values from calculation. */ | |
1790 | if (e1000_igp_2_cable_length_table[min_agc_index] > | |
1791 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1792 | min_agc_index = cur_agc_index; | |
1793 | if (e1000_igp_2_cable_length_table[max_agc_index] < | |
1794 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1795 | max_agc_index = cur_agc_index; | |
1796 | ||
1797 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; | |
1798 | } | |
1799 | ||
1800 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + | |
1801 | e1000_igp_2_cable_length_table[max_agc_index]); | |
1802 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); | |
1803 | ||
1804 | /* Calculate cable length with the error range of +/- 10 meters. */ | |
1805 | phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? | |
1806 | (agc_value - IGP02E1000_AGC_RANGE) : 0; | |
1807 | phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; | |
1808 | ||
1809 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1810 | ||
1811 | out: | |
1812 | return ret_val; | |
1813 | } | |
1814 | ||
1815 | /** | |
733596be | 1816 | * igb_get_phy_info_m88 - Retrieve PHY information |
9d5c8243 AK |
1817 | * @hw: pointer to the HW structure |
1818 | * | |
1819 | * Valid for only copper links. Read the PHY status register (sticky read) | |
1820 | * to verify that link is up. Read the PHY special control register to | |
1821 | * determine the polarity and 10base-T extended distance. Read the PHY | |
1822 | * special status register to determine MDI/MDIx and current speed. If | |
1823 | * speed is 1000, then determine cable length, local and remote receiver. | |
1824 | **/ | |
1825 | s32 igb_get_phy_info_m88(struct e1000_hw *hw) | |
1826 | { | |
1827 | struct e1000_phy_info *phy = &hw->phy; | |
1828 | s32 ret_val; | |
1829 | u16 phy_data; | |
1830 | bool link; | |
1831 | ||
a8d2a0c2 | 1832 | if (phy->media_type != e1000_media_type_copper) { |
652fff32 | 1833 | hw_dbg("Phy info is only valid for copper media\n"); |
9d5c8243 AK |
1834 | ret_val = -E1000_ERR_CONFIG; |
1835 | goto out; | |
1836 | } | |
1837 | ||
1838 | ret_val = igb_phy_has_link(hw, 1, 0, &link); | |
1839 | if (ret_val) | |
1840 | goto out; | |
1841 | ||
1842 | if (!link) { | |
652fff32 | 1843 | hw_dbg("Phy info is only valid if link is up\n"); |
9d5c8243 AK |
1844 | ret_val = -E1000_ERR_CONFIG; |
1845 | goto out; | |
1846 | } | |
1847 | ||
a8d2a0c2 | 1848 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
1849 | if (ret_val) |
1850 | goto out; | |
1851 | ||
1852 | phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) | |
a8d2a0c2 | 1853 | ? true : false; |
9d5c8243 AK |
1854 | |
1855 | ret_val = igb_check_polarity_m88(hw); | |
1856 | if (ret_val) | |
1857 | goto out; | |
1858 | ||
a8d2a0c2 | 1859 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
9d5c8243 AK |
1860 | if (ret_val) |
1861 | goto out; | |
1862 | ||
1863 | phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; | |
1864 | ||
1865 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { | |
a8d2a0c2 | 1866 | ret_val = phy->ops.get_cable_length(hw); |
9d5c8243 AK |
1867 | if (ret_val) |
1868 | goto out; | |
1869 | ||
a8d2a0c2 | 1870 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); |
9d5c8243 AK |
1871 | if (ret_val) |
1872 | goto out; | |
1873 | ||
1874 | phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) | |
1875 | ? e1000_1000t_rx_status_ok | |
1876 | : e1000_1000t_rx_status_not_ok; | |
1877 | ||
1878 | phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) | |
1879 | ? e1000_1000t_rx_status_ok | |
1880 | : e1000_1000t_rx_status_not_ok; | |
1881 | } else { | |
1882 | /* Set values to "undefined" */ | |
1883 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
1884 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
1885 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
1886 | } | |
1887 | ||
1888 | out: | |
1889 | return ret_val; | |
1890 | } | |
1891 | ||
1892 | /** | |
733596be | 1893 | * igb_get_phy_info_igp - Retrieve igp PHY information |
9d5c8243 AK |
1894 | * @hw: pointer to the HW structure |
1895 | * | |
1896 | * Read PHY status to determine if link is up. If link is up, then | |
1897 | * set/determine 10base-T extended distance and polarity correction. Read | |
1898 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
1899 | * determine on the cable length, local and remote receiver. | |
1900 | **/ | |
1901 | s32 igb_get_phy_info_igp(struct e1000_hw *hw) | |
1902 | { | |
1903 | struct e1000_phy_info *phy = &hw->phy; | |
1904 | s32 ret_val; | |
1905 | u16 data; | |
1906 | bool link; | |
1907 | ||
1908 | ret_val = igb_phy_has_link(hw, 1, 0, &link); | |
1909 | if (ret_val) | |
1910 | goto out; | |
1911 | ||
1912 | if (!link) { | |
652fff32 | 1913 | hw_dbg("Phy info is only valid if link is up\n"); |
9d5c8243 AK |
1914 | ret_val = -E1000_ERR_CONFIG; |
1915 | goto out; | |
1916 | } | |
1917 | ||
1918 | phy->polarity_correction = true; | |
1919 | ||
1920 | ret_val = igb_check_polarity_igp(hw); | |
1921 | if (ret_val) | |
1922 | goto out; | |
1923 | ||
a8d2a0c2 | 1924 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
9d5c8243 AK |
1925 | if (ret_val) |
1926 | goto out; | |
1927 | ||
1928 | phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; | |
1929 | ||
1930 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
1931 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
a8d2a0c2 | 1932 | ret_val = phy->ops.get_cable_length(hw); |
9d5c8243 AK |
1933 | if (ret_val) |
1934 | goto out; | |
1935 | ||
a8d2a0c2 | 1936 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); |
9d5c8243 AK |
1937 | if (ret_val) |
1938 | goto out; | |
1939 | ||
1940 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | |
1941 | ? e1000_1000t_rx_status_ok | |
1942 | : e1000_1000t_rx_status_not_ok; | |
1943 | ||
1944 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) | |
1945 | ? e1000_1000t_rx_status_ok | |
1946 | : e1000_1000t_rx_status_not_ok; | |
1947 | } else { | |
1948 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
1949 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
1950 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
1951 | } | |
1952 | ||
1953 | out: | |
1954 | return ret_val; | |
1955 | } | |
1956 | ||
1957 | /** | |
733596be | 1958 | * igb_phy_sw_reset - PHY software reset |
9d5c8243 AK |
1959 | * @hw: pointer to the HW structure |
1960 | * | |
1961 | * Does a software reset of the PHY by reading the PHY control register and | |
1962 | * setting/write the control register reset bit to the PHY. | |
1963 | **/ | |
1964 | s32 igb_phy_sw_reset(struct e1000_hw *hw) | |
1965 | { | |
d314737a | 1966 | s32 ret_val = 0; |
9d5c8243 AK |
1967 | u16 phy_ctrl; |
1968 | ||
d314737a AD |
1969 | if (!(hw->phy.ops.read_reg)) |
1970 | goto out; | |
1971 | ||
a8d2a0c2 | 1972 | ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); |
9d5c8243 AK |
1973 | if (ret_val) |
1974 | goto out; | |
1975 | ||
1976 | phy_ctrl |= MII_CR_RESET; | |
a8d2a0c2 | 1977 | ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); |
9d5c8243 AK |
1978 | if (ret_val) |
1979 | goto out; | |
1980 | ||
1981 | udelay(1); | |
1982 | ||
1983 | out: | |
1984 | return ret_val; | |
1985 | } | |
1986 | ||
1987 | /** | |
733596be | 1988 | * igb_phy_hw_reset - PHY hardware reset |
9d5c8243 AK |
1989 | * @hw: pointer to the HW structure |
1990 | * | |
1991 | * Verify the reset block is not blocking us from resetting. Acquire | |
1992 | * semaphore (if necessary) and read/set/write the device control reset | |
1993 | * bit in the PHY. Wait the appropriate delay time for the device to | |
1994 | * reset and relase the semaphore (if necessary). | |
1995 | **/ | |
1996 | s32 igb_phy_hw_reset(struct e1000_hw *hw) | |
1997 | { | |
1998 | struct e1000_phy_info *phy = &hw->phy; | |
1999 | s32 ret_val; | |
2000 | u32 ctrl; | |
2001 | ||
2002 | ret_val = igb_check_reset_block(hw); | |
2003 | if (ret_val) { | |
2004 | ret_val = 0; | |
2005 | goto out; | |
2006 | } | |
2007 | ||
a8d2a0c2 | 2008 | ret_val = phy->ops.acquire(hw); |
9d5c8243 AK |
2009 | if (ret_val) |
2010 | goto out; | |
2011 | ||
2012 | ctrl = rd32(E1000_CTRL); | |
2013 | wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); | |
2014 | wrfl(); | |
2015 | ||
2016 | udelay(phy->reset_delay_us); | |
2017 | ||
2018 | wr32(E1000_CTRL, ctrl); | |
2019 | wrfl(); | |
2020 | ||
2021 | udelay(150); | |
2022 | ||
a8d2a0c2 | 2023 | phy->ops.release(hw); |
9d5c8243 | 2024 | |
a8d2a0c2 | 2025 | ret_val = phy->ops.get_cfg_done(hw); |
9d5c8243 AK |
2026 | |
2027 | out: | |
2028 | return ret_val; | |
2029 | } | |
2030 | ||
9d5c8243 | 2031 | /** |
733596be | 2032 | * igb_phy_init_script_igp3 - Inits the IGP3 PHY |
9d5c8243 AK |
2033 | * @hw: pointer to the HW structure |
2034 | * | |
2035 | * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. | |
2036 | **/ | |
2037 | s32 igb_phy_init_script_igp3(struct e1000_hw *hw) | |
2038 | { | |
652fff32 | 2039 | hw_dbg("Running IGP 3 PHY init script\n"); |
9d5c8243 AK |
2040 | |
2041 | /* PHY init IGP 3 */ | |
2042 | /* Enable rise/fall, 10-mode work in class-A */ | |
a8d2a0c2 | 2043 | hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); |
9d5c8243 | 2044 | /* Remove all caps from Replica path filter */ |
a8d2a0c2 | 2045 | hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); |
9d5c8243 | 2046 | /* Bias trimming for ADC, AFE and Driver (Default) */ |
a8d2a0c2 | 2047 | hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); |
9d5c8243 | 2048 | /* Increase Hybrid poly bias */ |
a8d2a0c2 | 2049 | hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); |
9d5c8243 | 2050 | /* Add 4% to TX amplitude in Giga mode */ |
a8d2a0c2 | 2051 | hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); |
9d5c8243 | 2052 | /* Disable trimming (TTT) */ |
a8d2a0c2 | 2053 | hw->phy.ops.write_reg(hw, 0x2011, 0x0000); |
9d5c8243 | 2054 | /* Poly DC correction to 94.6% + 2% for all channels */ |
a8d2a0c2 | 2055 | hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); |
9d5c8243 | 2056 | /* ABS DC correction to 95.9% */ |
a8d2a0c2 | 2057 | hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); |
9d5c8243 | 2058 | /* BG temp curve trim */ |
a8d2a0c2 | 2059 | hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); |
9d5c8243 | 2060 | /* Increasing ADC OPAMP stage 1 currents to max */ |
a8d2a0c2 | 2061 | hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); |
9d5c8243 | 2062 | /* Force 1000 ( required for enabling PHY regs configuration) */ |
a8d2a0c2 | 2063 | hw->phy.ops.write_reg(hw, 0x0000, 0x0140); |
9d5c8243 | 2064 | /* Set upd_freq to 6 */ |
a8d2a0c2 | 2065 | hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); |
9d5c8243 | 2066 | /* Disable NPDFE */ |
a8d2a0c2 | 2067 | hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); |
9d5c8243 | 2068 | /* Disable adaptive fixed FFE (Default) */ |
a8d2a0c2 | 2069 | hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); |
9d5c8243 | 2070 | /* Enable FFE hysteresis */ |
a8d2a0c2 | 2071 | hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); |
9d5c8243 | 2072 | /* Fixed FFE for short cable lengths */ |
a8d2a0c2 | 2073 | hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); |
9d5c8243 | 2074 | /* Fixed FFE for medium cable lengths */ |
a8d2a0c2 | 2075 | hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); |
9d5c8243 | 2076 | /* Fixed FFE for long cable lengths */ |
a8d2a0c2 | 2077 | hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); |
9d5c8243 | 2078 | /* Enable Adaptive Clip Threshold */ |
a8d2a0c2 | 2079 | hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); |
9d5c8243 | 2080 | /* AHT reset limit to 1 */ |
a8d2a0c2 | 2081 | hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); |
9d5c8243 | 2082 | /* Set AHT master delay to 127 msec */ |
a8d2a0c2 | 2083 | hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); |
9d5c8243 | 2084 | /* Set scan bits for AHT */ |
a8d2a0c2 | 2085 | hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); |
9d5c8243 | 2086 | /* Set AHT Preset bits */ |
a8d2a0c2 | 2087 | hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); |
9d5c8243 | 2088 | /* Change integ_factor of channel A to 3 */ |
a8d2a0c2 | 2089 | hw->phy.ops.write_reg(hw, 0x1895, 0x0003); |
9d5c8243 | 2090 | /* Change prop_factor of channels BCD to 8 */ |
a8d2a0c2 | 2091 | hw->phy.ops.write_reg(hw, 0x1796, 0x0008); |
9d5c8243 | 2092 | /* Change cg_icount + enable integbp for channels BCD */ |
a8d2a0c2 | 2093 | hw->phy.ops.write_reg(hw, 0x1798, 0xD008); |
9d5c8243 AK |
2094 | /* |
2095 | * Change cg_icount + enable integbp + change prop_factor_master | |
2096 | * to 8 for channel A | |
2097 | */ | |
a8d2a0c2 | 2098 | hw->phy.ops.write_reg(hw, 0x1898, 0xD918); |
9d5c8243 | 2099 | /* Disable AHT in Slave mode on channel A */ |
a8d2a0c2 | 2100 | hw->phy.ops.write_reg(hw, 0x187A, 0x0800); |
9d5c8243 AK |
2101 | /* |
2102 | * Enable LPLU and disable AN to 1000 in non-D0a states, | |
2103 | * Enable SPD+B2B | |
2104 | */ | |
a8d2a0c2 | 2105 | hw->phy.ops.write_reg(hw, 0x0019, 0x008D); |
9d5c8243 | 2106 | /* Enable restart AN on an1000_dis change */ |
a8d2a0c2 | 2107 | hw->phy.ops.write_reg(hw, 0x001B, 0x2080); |
9d5c8243 | 2108 | /* Enable wh_fifo read clock in 10/100 modes */ |
a8d2a0c2 | 2109 | hw->phy.ops.write_reg(hw, 0x0014, 0x0045); |
9d5c8243 | 2110 | /* Restart AN, Speed selection is 1000 */ |
a8d2a0c2 | 2111 | hw->phy.ops.write_reg(hw, 0x0000, 0x1340); |
9d5c8243 AK |
2112 | |
2113 | return 0; | |
2114 | } | |
2115 | ||
88a268c1 NN |
2116 | /** |
2117 | * igb_power_up_phy_copper - Restore copper link in case of PHY power down | |
2118 | * @hw: pointer to the HW structure | |
2119 | * | |
2120 | * In the case of a PHY power down to save power, or to turn off link during a | |
2121 | * driver unload, restore the link to previous settings. | |
2122 | **/ | |
2123 | void igb_power_up_phy_copper(struct e1000_hw *hw) | |
2124 | { | |
2125 | u16 mii_reg = 0; | |
2126 | ||
2127 | /* The PHY will retain its settings across a power down/up cycle */ | |
2128 | hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); | |
2129 | mii_reg &= ~MII_CR_POWER_DOWN; | |
2130 | hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); | |
2131 | } | |
2132 | ||
2133 | /** | |
2134 | * igb_power_down_phy_copper - Power down copper PHY | |
2135 | * @hw: pointer to the HW structure | |
2136 | * | |
2137 | * Power down PHY to save power when interface is down and wake on lan | |
2138 | * is not enabled. | |
2139 | **/ | |
2140 | void igb_power_down_phy_copper(struct e1000_hw *hw) | |
2141 | { | |
2142 | u16 mii_reg = 0; | |
2143 | ||
2144 | /* The PHY will retain its settings across a power down/up cycle */ | |
2145 | hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); | |
2146 | mii_reg |= MII_CR_POWER_DOWN; | |
2147 | hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); | |
2148 | msleep(1); | |
2149 | } | |
2150 | ||
2909c3f7 AD |
2151 | /** |
2152 | * igb_check_polarity_82580 - Checks the polarity. | |
2153 | * @hw: pointer to the HW structure | |
2154 | * | |
2155 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
2156 | * | |
2157 | * Polarity is determined based on the PHY specific status register. | |
2158 | **/ | |
bb2ac47b | 2159 | static s32 igb_check_polarity_82580(struct e1000_hw *hw) |
2909c3f7 AD |
2160 | { |
2161 | struct e1000_phy_info *phy = &hw->phy; | |
2162 | s32 ret_val; | |
2163 | u16 data; | |
2164 | ||
2165 | ||
2166 | ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); | |
2167 | ||
2168 | if (!ret_val) | |
2169 | phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY) | |
2170 | ? e1000_rev_polarity_reversed | |
2171 | : e1000_rev_polarity_normal; | |
2172 | ||
2173 | return ret_val; | |
2174 | } | |
2175 | ||
2176 | /** | |
2177 | * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY | |
2178 | * @hw: pointer to the HW structure | |
2179 | * | |
2180 | * Calls the PHY setup function to force speed and duplex. Clears the | |
2181 | * auto-crossover to force MDI manually. Waits for link and returns | |
2182 | * successful if link up is successful, else -E1000_ERR_PHY (-2). | |
2183 | **/ | |
2184 | s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw) | |
2185 | { | |
2186 | struct e1000_phy_info *phy = &hw->phy; | |
2187 | s32 ret_val; | |
2188 | u16 phy_data; | |
2189 | bool link; | |
2190 | ||
2191 | ||
2192 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); | |
2193 | if (ret_val) | |
2194 | goto out; | |
2195 | ||
2196 | igb_phy_force_speed_duplex_setup(hw, &phy_data); | |
2197 | ||
2198 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); | |
2199 | if (ret_val) | |
2200 | goto out; | |
2201 | ||
2202 | /* | |
2203 | * Clear Auto-Crossover to force MDI manually. 82580 requires MDI | |
2204 | * forced whenever speed and duplex are forced. | |
2205 | */ | |
2206 | ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); | |
2207 | if (ret_val) | |
2208 | goto out; | |
2209 | ||
2210 | phy_data &= ~I82580_PHY_CTRL2_AUTO_MDIX; | |
2211 | phy_data &= ~I82580_PHY_CTRL2_FORCE_MDI_MDIX; | |
2212 | ||
2213 | ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); | |
2214 | if (ret_val) | |
2215 | goto out; | |
2216 | ||
2217 | hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data); | |
2218 | ||
2219 | udelay(1); | |
2220 | ||
2221 | if (phy->autoneg_wait_to_complete) { | |
2222 | hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n"); | |
2223 | ||
2224 | ret_val = igb_phy_has_link(hw, | |
2225 | PHY_FORCE_LIMIT, | |
2226 | 100000, | |
2227 | &link); | |
2228 | if (ret_val) | |
2229 | goto out; | |
2230 | ||
2231 | if (!link) | |
2232 | hw_dbg("Link taking longer than expected.\n"); | |
2233 | ||
2234 | /* Try once more */ | |
2235 | ret_val = igb_phy_has_link(hw, | |
2236 | PHY_FORCE_LIMIT, | |
2237 | 100000, | |
2238 | &link); | |
2239 | if (ret_val) | |
2240 | goto out; | |
2241 | } | |
2242 | ||
2243 | out: | |
2244 | return ret_val; | |
2245 | } | |
2246 | ||
2247 | /** | |
2248 | * igb_get_phy_info_82580 - Retrieve I82580 PHY information | |
2249 | * @hw: pointer to the HW structure | |
2250 | * | |
2251 | * Read PHY status to determine if link is up. If link is up, then | |
2252 | * set/determine 10base-T extended distance and polarity correction. Read | |
2253 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
2254 | * determine on the cable length, local and remote receiver. | |
2255 | **/ | |
2256 | s32 igb_get_phy_info_82580(struct e1000_hw *hw) | |
2257 | { | |
2258 | struct e1000_phy_info *phy = &hw->phy; | |
2259 | s32 ret_val; | |
2260 | u16 data; | |
2261 | bool link; | |
2262 | ||
2263 | ||
2264 | ret_val = igb_phy_has_link(hw, 1, 0, &link); | |
2265 | if (ret_val) | |
2266 | goto out; | |
2267 | ||
2268 | if (!link) { | |
2269 | hw_dbg("Phy info is only valid if link is up\n"); | |
2270 | ret_val = -E1000_ERR_CONFIG; | |
2271 | goto out; | |
2272 | } | |
2273 | ||
2274 | phy->polarity_correction = true; | |
2275 | ||
2276 | ret_val = igb_check_polarity_82580(hw); | |
2277 | if (ret_val) | |
2278 | goto out; | |
2279 | ||
2280 | ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); | |
2281 | if (ret_val) | |
2282 | goto out; | |
2283 | ||
2284 | phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false; | |
2285 | ||
2286 | if ((data & I82580_PHY_STATUS2_SPEED_MASK) == | |
2287 | I82580_PHY_STATUS2_SPEED_1000MBPS) { | |
2288 | ret_val = hw->phy.ops.get_cable_length(hw); | |
2289 | if (ret_val) | |
2290 | goto out; | |
2291 | ||
2292 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); | |
2293 | if (ret_val) | |
2294 | goto out; | |
2295 | ||
2296 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | |
2297 | ? e1000_1000t_rx_status_ok | |
2298 | : e1000_1000t_rx_status_not_ok; | |
2299 | ||
2300 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) | |
2301 | ? e1000_1000t_rx_status_ok | |
2302 | : e1000_1000t_rx_status_not_ok; | |
2303 | } else { | |
2304 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
2305 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
2306 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
2307 | } | |
2308 | ||
2309 | out: | |
2310 | return ret_val; | |
2311 | } | |
2312 | ||
2313 | /** | |
2314 | * igb_get_cable_length_82580 - Determine cable length for 82580 PHY | |
2315 | * @hw: pointer to the HW structure | |
2316 | * | |
2317 | * Reads the diagnostic status register and verifies result is valid before | |
2318 | * placing it in the phy_cable_length field. | |
2319 | **/ | |
2320 | s32 igb_get_cable_length_82580(struct e1000_hw *hw) | |
2321 | { | |
2322 | struct e1000_phy_info *phy = &hw->phy; | |
2323 | s32 ret_val; | |
2324 | u16 phy_data, length; | |
2325 | ||
2326 | ||
2327 | ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data); | |
2328 | if (ret_val) | |
2329 | goto out; | |
2330 | ||
2331 | length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >> | |
2332 | I82580_DSTATUS_CABLE_LENGTH_SHIFT; | |
2333 | ||
2334 | if (length == E1000_CABLE_LENGTH_UNDEFINED) | |
2335 | ret_val = -E1000_ERR_PHY; | |
2336 | ||
2337 | phy->cable_length = length; | |
2338 | ||
2339 | out: | |
2340 | return ret_val; | |
2341 | } |