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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
86d5d38f | 4 | Copyright(c) 2007-2009 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #ifndef _E1000_HW_H_ | |
29 | #define _E1000_HW_H_ | |
30 | ||
31 | #include <linux/types.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/io.h> | |
c041076a | 34 | #include <linux/netdevice.h> |
9d5c8243 | 35 | |
9d5c8243 AK |
36 | #include "e1000_regs.h" |
37 | #include "e1000_defines.h" | |
38 | ||
39 | struct e1000_hw; | |
40 | ||
2d064c06 AD |
41 | #define E1000_DEV_ID_82576 0x10C9 |
42 | #define E1000_DEV_ID_82576_FIBER 0x10E6 | |
43 | #define E1000_DEV_ID_82576_SERDES 0x10E7 | |
c8ea5ea9 | 44 | #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 |
b894fa26 | 45 | #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 |
9eb2341d | 46 | #define E1000_DEV_ID_82576_NS 0x150A |
747d49ba | 47 | #define E1000_DEV_ID_82576_NS_SERDES 0x1518 |
4703bf73 | 48 | #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D |
9d5c8243 AK |
49 | #define E1000_DEV_ID_82575EB_COPPER 0x10A7 |
50 | #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 | |
51 | #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 | |
bb2ac47b AD |
52 | #define E1000_DEV_ID_82580_COPPER 0x150E |
53 | #define E1000_DEV_ID_82580_FIBER 0x150F | |
54 | #define E1000_DEV_ID_82580_SERDES 0x1510 | |
55 | #define E1000_DEV_ID_82580_SGMII 0x1511 | |
56 | #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 | |
1b5dda33 GJ |
57 | #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 |
58 | #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A | |
59 | #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C | |
60 | #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 | |
d2ba2ed8 AD |
61 | #define E1000_DEV_ID_I350_COPPER 0x1521 |
62 | #define E1000_DEV_ID_I350_FIBER 0x1522 | |
63 | #define E1000_DEV_ID_I350_SERDES 0x1523 | |
64 | #define E1000_DEV_ID_I350_SGMII 0x1524 | |
9d5c8243 AK |
65 | |
66 | #define E1000_REVISION_2 2 | |
67 | #define E1000_REVISION_4 4 | |
68 | ||
70d92f86 | 69 | #define E1000_FUNC_0 0 |
9d5c8243 | 70 | #define E1000_FUNC_1 1 |
bb2ac47b AD |
71 | #define E1000_FUNC_2 2 |
72 | #define E1000_FUNC_3 3 | |
9d5c8243 | 73 | |
bb2ac47b | 74 | #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 |
22896639 | 75 | #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 |
bb2ac47b AD |
76 | #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 |
77 | #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 | |
22896639 | 78 | |
9d5c8243 AK |
79 | enum e1000_mac_type { |
80 | e1000_undefined = 0, | |
81 | e1000_82575, | |
2d064c06 | 82 | e1000_82576, |
bb2ac47b | 83 | e1000_82580, |
d2ba2ed8 | 84 | e1000_i350, |
9d5c8243 AK |
85 | e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ |
86 | }; | |
87 | ||
88 | enum e1000_media_type { | |
89 | e1000_media_type_unknown = 0, | |
90 | e1000_media_type_copper = 1, | |
dcc3ae9a | 91 | e1000_media_type_internal_serdes = 2, |
9d5c8243 AK |
92 | e1000_num_media_types |
93 | }; | |
94 | ||
95 | enum e1000_nvm_type { | |
96 | e1000_nvm_unknown = 0, | |
97 | e1000_nvm_none, | |
98 | e1000_nvm_eeprom_spi, | |
9d5c8243 AK |
99 | e1000_nvm_flash_hw, |
100 | e1000_nvm_flash_sw | |
101 | }; | |
102 | ||
103 | enum e1000_nvm_override { | |
104 | e1000_nvm_override_none = 0, | |
105 | e1000_nvm_override_spi_small, | |
106 | e1000_nvm_override_spi_large, | |
9d5c8243 AK |
107 | }; |
108 | ||
109 | enum e1000_phy_type { | |
110 | e1000_phy_unknown = 0, | |
111 | e1000_phy_none, | |
112 | e1000_phy_m88, | |
113 | e1000_phy_igp, | |
114 | e1000_phy_igp_2, | |
115 | e1000_phy_gg82563, | |
116 | e1000_phy_igp_3, | |
117 | e1000_phy_ife, | |
2909c3f7 | 118 | e1000_phy_82580, |
9d5c8243 AK |
119 | }; |
120 | ||
121 | enum e1000_bus_type { | |
122 | e1000_bus_type_unknown = 0, | |
123 | e1000_bus_type_pci, | |
124 | e1000_bus_type_pcix, | |
125 | e1000_bus_type_pci_express, | |
126 | e1000_bus_type_reserved | |
127 | }; | |
128 | ||
129 | enum e1000_bus_speed { | |
130 | e1000_bus_speed_unknown = 0, | |
131 | e1000_bus_speed_33, | |
132 | e1000_bus_speed_66, | |
133 | e1000_bus_speed_100, | |
134 | e1000_bus_speed_120, | |
135 | e1000_bus_speed_133, | |
136 | e1000_bus_speed_2500, | |
137 | e1000_bus_speed_5000, | |
138 | e1000_bus_speed_reserved | |
139 | }; | |
140 | ||
141 | enum e1000_bus_width { | |
142 | e1000_bus_width_unknown = 0, | |
143 | e1000_bus_width_pcie_x1, | |
144 | e1000_bus_width_pcie_x2, | |
145 | e1000_bus_width_pcie_x4 = 4, | |
146 | e1000_bus_width_pcie_x8 = 8, | |
147 | e1000_bus_width_32, | |
148 | e1000_bus_width_64, | |
149 | e1000_bus_width_reserved | |
150 | }; | |
151 | ||
152 | enum e1000_1000t_rx_status { | |
153 | e1000_1000t_rx_status_not_ok = 0, | |
154 | e1000_1000t_rx_status_ok, | |
155 | e1000_1000t_rx_status_undefined = 0xFF | |
156 | }; | |
157 | ||
158 | enum e1000_rev_polarity { | |
159 | e1000_rev_polarity_normal = 0, | |
160 | e1000_rev_polarity_reversed, | |
161 | e1000_rev_polarity_undefined = 0xFF | |
162 | }; | |
163 | ||
0cce119a | 164 | enum e1000_fc_mode { |
9d5c8243 AK |
165 | e1000_fc_none = 0, |
166 | e1000_fc_rx_pause, | |
167 | e1000_fc_tx_pause, | |
168 | e1000_fc_full, | |
169 | e1000_fc_default = 0xFF | |
170 | }; | |
171 | ||
9d5c8243 AK |
172 | /* Statistics counters collected by the MAC */ |
173 | struct e1000_hw_stats { | |
174 | u64 crcerrs; | |
175 | u64 algnerrc; | |
176 | u64 symerrs; | |
177 | u64 rxerrc; | |
178 | u64 mpc; | |
179 | u64 scc; | |
180 | u64 ecol; | |
181 | u64 mcc; | |
182 | u64 latecol; | |
183 | u64 colc; | |
184 | u64 dc; | |
185 | u64 tncrs; | |
186 | u64 sec; | |
187 | u64 cexterr; | |
188 | u64 rlec; | |
189 | u64 xonrxc; | |
190 | u64 xontxc; | |
191 | u64 xoffrxc; | |
192 | u64 xofftxc; | |
193 | u64 fcruc; | |
194 | u64 prc64; | |
195 | u64 prc127; | |
196 | u64 prc255; | |
197 | u64 prc511; | |
198 | u64 prc1023; | |
199 | u64 prc1522; | |
200 | u64 gprc; | |
201 | u64 bprc; | |
202 | u64 mprc; | |
203 | u64 gptc; | |
204 | u64 gorc; | |
205 | u64 gotc; | |
206 | u64 rnbc; | |
207 | u64 ruc; | |
208 | u64 rfc; | |
209 | u64 roc; | |
210 | u64 rjc; | |
211 | u64 mgprc; | |
212 | u64 mgpdc; | |
213 | u64 mgptc; | |
214 | u64 tor; | |
215 | u64 tot; | |
216 | u64 tpr; | |
217 | u64 tpt; | |
218 | u64 ptc64; | |
219 | u64 ptc127; | |
220 | u64 ptc255; | |
221 | u64 ptc511; | |
222 | u64 ptc1023; | |
223 | u64 ptc1522; | |
224 | u64 mptc; | |
225 | u64 bptc; | |
226 | u64 tsctc; | |
227 | u64 tsctfc; | |
228 | u64 iac; | |
229 | u64 icrxptc; | |
230 | u64 icrxatc; | |
231 | u64 ictxptc; | |
232 | u64 ictxatc; | |
233 | u64 ictxqec; | |
234 | u64 ictxqmtc; | |
235 | u64 icrxdmtc; | |
236 | u64 icrxoc; | |
237 | u64 cbtmpc; | |
238 | u64 htdpmc; | |
239 | u64 cbrdpc; | |
240 | u64 cbrmpc; | |
241 | u64 rpthc; | |
242 | u64 hgptc; | |
243 | u64 htcbdpc; | |
244 | u64 hgorc; | |
245 | u64 hgotc; | |
246 | u64 lenerrs; | |
247 | u64 scvpc; | |
248 | u64 hrmpc; | |
dda0e083 | 249 | u64 doosync; |
9d5c8243 AK |
250 | }; |
251 | ||
252 | struct e1000_phy_stats { | |
253 | u32 idle_errors; | |
254 | u32 receive_errors; | |
255 | }; | |
256 | ||
257 | struct e1000_host_mng_dhcp_cookie { | |
258 | u32 signature; | |
259 | u8 status; | |
260 | u8 reserved0; | |
261 | u16 vlan_id; | |
262 | u32 reserved1; | |
263 | u16 reserved2; | |
264 | u8 reserved3; | |
265 | u8 checksum; | |
266 | }; | |
267 | ||
268 | /* Host Interface "Rev 1" */ | |
269 | struct e1000_host_command_header { | |
270 | u8 command_id; | |
271 | u8 command_length; | |
272 | u8 command_options; | |
273 | u8 checksum; | |
274 | }; | |
275 | ||
276 | #define E1000_HI_MAX_DATA_LENGTH 252 | |
277 | struct e1000_host_command_info { | |
278 | struct e1000_host_command_header command_header; | |
279 | u8 command_data[E1000_HI_MAX_DATA_LENGTH]; | |
280 | }; | |
281 | ||
282 | /* Host Interface "Rev 2" */ | |
283 | struct e1000_host_mng_command_header { | |
284 | u8 command_id; | |
285 | u8 checksum; | |
286 | u16 reserved1; | |
287 | u16 reserved2; | |
288 | u16 command_length; | |
289 | }; | |
290 | ||
291 | #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 | |
292 | struct e1000_host_mng_command_info { | |
293 | struct e1000_host_mng_command_header command_header; | |
294 | u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; | |
295 | }; | |
296 | ||
297 | #include "e1000_mac.h" | |
298 | #include "e1000_phy.h" | |
299 | #include "e1000_nvm.h" | |
4ae196df | 300 | #include "e1000_mbx.h" |
9d5c8243 AK |
301 | |
302 | struct e1000_mac_operations { | |
303 | s32 (*check_for_link)(struct e1000_hw *); | |
304 | s32 (*reset_hw)(struct e1000_hw *); | |
305 | s32 (*init_hw)(struct e1000_hw *); | |
2d064c06 | 306 | bool (*check_mng_mode)(struct e1000_hw *); |
9d5c8243 AK |
307 | s32 (*setup_physical_interface)(struct e1000_hw *); |
308 | void (*rar_set)(struct e1000_hw *, u8 *, u32); | |
309 | s32 (*read_mac_addr)(struct e1000_hw *); | |
310 | s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *); | |
311 | }; | |
312 | ||
313 | struct e1000_phy_operations { | |
a8d2a0c2 | 314 | s32 (*acquire)(struct e1000_hw *); |
bb2ac47b | 315 | s32 (*check_polarity)(struct e1000_hw *); |
2d064c06 | 316 | s32 (*check_reset_block)(struct e1000_hw *); |
9d5c8243 AK |
317 | s32 (*force_speed_duplex)(struct e1000_hw *); |
318 | s32 (*get_cfg_done)(struct e1000_hw *hw); | |
319 | s32 (*get_cable_length)(struct e1000_hw *); | |
320 | s32 (*get_phy_info)(struct e1000_hw *); | |
a8d2a0c2 AD |
321 | s32 (*read_reg)(struct e1000_hw *, u32, u16 *); |
322 | void (*release)(struct e1000_hw *); | |
323 | s32 (*reset)(struct e1000_hw *); | |
9d5c8243 AK |
324 | s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); |
325 | s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); | |
a8d2a0c2 | 326 | s32 (*write_reg)(struct e1000_hw *, u32, u16); |
9d5c8243 AK |
327 | }; |
328 | ||
329 | struct e1000_nvm_operations { | |
312c75ae AD |
330 | s32 (*acquire)(struct e1000_hw *); |
331 | s32 (*read)(struct e1000_hw *, u16, u16, u16 *); | |
332 | void (*release)(struct e1000_hw *); | |
333 | s32 (*write)(struct e1000_hw *, u16, u16, u16 *); | |
9d5c8243 AK |
334 | }; |
335 | ||
336 | struct e1000_info { | |
337 | s32 (*get_invariants)(struct e1000_hw *); | |
338 | struct e1000_mac_operations *mac_ops; | |
339 | struct e1000_phy_operations *phy_ops; | |
340 | struct e1000_nvm_operations *nvm_ops; | |
341 | }; | |
342 | ||
343 | extern const struct e1000_info e1000_82575_info; | |
344 | ||
345 | struct e1000_mac_info { | |
346 | struct e1000_mac_operations ops; | |
347 | ||
348 | u8 addr[6]; | |
349 | u8 perm_addr[6]; | |
350 | ||
351 | enum e1000_mac_type type; | |
352 | ||
9d5c8243 AK |
353 | u32 ledctl_default; |
354 | u32 ledctl_mode1; | |
355 | u32 ledctl_mode2; | |
356 | u32 mc_filter_type; | |
9d5c8243 AK |
357 | u32 txcw; |
358 | ||
9d5c8243 | 359 | u16 mta_reg_count; |
68d480c4 | 360 | u16 uta_reg_count; |
28fc06f5 AD |
361 | |
362 | /* Maximum size of the MTA register table in all supported adapters */ | |
363 | #define MAX_MTA_REG 128 | |
364 | u32 mta_shadow[MAX_MTA_REG]; | |
9d5c8243 AK |
365 | u16 rar_entry_count; |
366 | ||
367 | u8 forced_speed_duplex; | |
368 | ||
369 | bool adaptive_ifs; | |
370 | bool arc_subsystem_valid; | |
371 | bool asf_firmware_present; | |
372 | bool autoneg; | |
373 | bool autoneg_failed; | |
9d5c8243 AK |
374 | bool disable_hw_init_bits; |
375 | bool get_link_status; | |
376 | bool ifs_params_forced; | |
377 | bool in_ifs_mode; | |
378 | bool report_tx_early; | |
379 | bool serdes_has_link; | |
380 | bool tx_pkt_filtering; | |
381 | }; | |
382 | ||
383 | struct e1000_phy_info { | |
384 | struct e1000_phy_operations ops; | |
385 | ||
386 | enum e1000_phy_type type; | |
387 | ||
388 | enum e1000_1000t_rx_status local_rx; | |
389 | enum e1000_1000t_rx_status remote_rx; | |
390 | enum e1000_ms_type ms_type; | |
391 | enum e1000_ms_type original_ms_type; | |
392 | enum e1000_rev_polarity cable_polarity; | |
393 | enum e1000_smart_speed smart_speed; | |
394 | ||
395 | u32 addr; | |
396 | u32 id; | |
397 | u32 reset_delay_us; /* in usec */ | |
398 | u32 revision; | |
399 | ||
400 | enum e1000_media_type media_type; | |
401 | ||
402 | u16 autoneg_advertised; | |
403 | u16 autoneg_mask; | |
404 | u16 cable_length; | |
405 | u16 max_cable_length; | |
406 | u16 min_cable_length; | |
407 | ||
408 | u8 mdix; | |
409 | ||
410 | bool disable_polarity_correction; | |
411 | bool is_mdix; | |
412 | bool polarity_correction; | |
413 | bool reset_disable; | |
414 | bool speed_downgraded; | |
415 | bool autoneg_wait_to_complete; | |
416 | }; | |
417 | ||
418 | struct e1000_nvm_info { | |
419 | struct e1000_nvm_operations ops; | |
420 | ||
421 | enum e1000_nvm_type type; | |
422 | enum e1000_nvm_override override; | |
423 | ||
424 | u32 flash_bank_size; | |
425 | u32 flash_base_addr; | |
426 | ||
427 | u16 word_size; | |
428 | u16 delay_usec; | |
429 | u16 address_bits; | |
430 | u16 opcode_bits; | |
431 | u16 page_size; | |
432 | }; | |
433 | ||
434 | struct e1000_bus_info { | |
435 | enum e1000_bus_type type; | |
436 | enum e1000_bus_speed speed; | |
437 | enum e1000_bus_width width; | |
438 | ||
439 | u32 snoop; | |
440 | ||
441 | u16 func; | |
442 | u16 pci_cmd_word; | |
443 | }; | |
444 | ||
445 | struct e1000_fc_info { | |
446 | u32 high_water; /* Flow control high-water mark */ | |
447 | u32 low_water; /* Flow control low-water mark */ | |
448 | u16 pause_time; /* Flow control pause timer */ | |
449 | bool send_xon; /* Flow control send XON */ | |
450 | bool strict_ieee; /* Strict IEEE mode */ | |
0cce119a AD |
451 | enum e1000_fc_mode current_mode; /* Type of flow control */ |
452 | enum e1000_fc_mode requested_mode; | |
9d5c8243 AK |
453 | }; |
454 | ||
4ae196df AD |
455 | struct e1000_mbx_operations { |
456 | s32 (*init_params)(struct e1000_hw *hw); | |
457 | s32 (*read)(struct e1000_hw *, u32 *, u16, u16); | |
458 | s32 (*write)(struct e1000_hw *, u32 *, u16, u16); | |
459 | s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); | |
460 | s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); | |
461 | s32 (*check_for_msg)(struct e1000_hw *, u16); | |
462 | s32 (*check_for_ack)(struct e1000_hw *, u16); | |
463 | s32 (*check_for_rst)(struct e1000_hw *, u16); | |
464 | }; | |
465 | ||
466 | struct e1000_mbx_stats { | |
467 | u32 msgs_tx; | |
468 | u32 msgs_rx; | |
469 | ||
470 | u32 acks; | |
471 | u32 reqs; | |
472 | u32 rsts; | |
473 | }; | |
474 | ||
475 | struct e1000_mbx_info { | |
476 | struct e1000_mbx_operations ops; | |
477 | struct e1000_mbx_stats stats; | |
478 | u32 timeout; | |
479 | u32 usec_delay; | |
480 | u16 size; | |
481 | }; | |
482 | ||
c1889bfe AD |
483 | struct e1000_dev_spec_82575 { |
484 | bool sgmii_active; | |
bb2ac47b | 485 | bool global_device_reset; |
c1889bfe AD |
486 | }; |
487 | ||
9d5c8243 AK |
488 | struct e1000_hw { |
489 | void *back; | |
9d5c8243 AK |
490 | |
491 | u8 __iomem *hw_addr; | |
492 | u8 __iomem *flash_address; | |
493 | unsigned long io_base; | |
494 | ||
495 | struct e1000_mac_info mac; | |
496 | struct e1000_fc_info fc; | |
497 | struct e1000_phy_info phy; | |
498 | struct e1000_nvm_info nvm; | |
499 | struct e1000_bus_info bus; | |
4ae196df | 500 | struct e1000_mbx_info mbx; |
9d5c8243 AK |
501 | struct e1000_host_mng_dhcp_cookie mng_cookie; |
502 | ||
c1889bfe AD |
503 | union { |
504 | struct e1000_dev_spec_82575 _82575; | |
505 | } dev_spec; | |
9d5c8243 AK |
506 | |
507 | u16 device_id; | |
508 | u16 subsystem_vendor_id; | |
509 | u16 subsystem_device_id; | |
510 | u16 vendor_id; | |
511 | ||
512 | u8 revision_id; | |
513 | }; | |
514 | ||
c041076a | 515 | extern struct net_device *igb_get_hw_dev(struct e1000_hw *hw); |
652fff32 | 516 | #define hw_dbg(format, arg...) \ |
c041076a AD |
517 | netdev_dbg(igb_get_hw_dev(hw), format, ##arg) |
518 | ||
009bc06e AD |
519 | /* These functions must be implemented by drivers */ |
520 | s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); | |
521 | s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); | |
c041076a | 522 | #endif /* _E1000_HW_H_ */ |