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mrf24j40: add cca ed level support
[linux-2.6-block.git] / drivers / net / ieee802154 / mrf24j40.c
CommitLineData
3731a334
AO		 1/*
2 * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
3 *
4 * Copyright (C) 2012 Alan Ott <alan@signal11.us>
5 * Signal 11 Software
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
3731a334
AO		 16 */
17
18#include <linux/spi/spi.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
b0156792 21#include <linux/regmap.h>
4ca24aca 22#include <linux/ieee802154.h>
5ad60d36 23#include <net/cfg802154.h>
3731a334
AO		 24#include <net/mac802154.h>
25
26/* MRF24J40 Short Address Registers */
c9f883f6
AA		 27#define REG_RXMCR 0x00 /* Receive MAC control */
28#define REG_PANIDL 0x01 /* PAN ID (low) */
29#define REG_PANIDH 0x02 /* PAN ID (high) */
30#define REG_SADRL 0x03 /* Short address (low) */
31#define REG_SADRH 0x04 /* Short address (high) */
32#define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */
554b4949
AA		 33#define REG_EADR1 0x06
34#define REG_EADR2 0x07
35#define REG_EADR3 0x08
36#define REG_EADR4 0x09
37#define REG_EADR5 0x0A
38#define REG_EADR6 0x0B
39#define REG_EADR7 0x0C
40#define REG_RXFLUSH 0x0D
41#define REG_ORDER 0x10
c9f883f6 42#define REG_TXMCR 0x11 /* Transmit MAC control */
554b4949
AA		 43#define REG_ACKTMOUT 0x12
44#define REG_ESLOTG1 0x13
45#define REG_SYMTICKL 0x14
46#define REG_SYMTICKH 0x15
c9f883f6
AA		 47#define REG_PACON0 0x16 /* Power Amplifier Control */
48#define REG_PACON1 0x17 /* Power Amplifier Control */
49#define REG_PACON2 0x18 /* Power Amplifier Control */
554b4949 50#define REG_TXBCON0 0x1A
c9f883f6 51#define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
554b4949
AA		 52#define REG_TXG1CON 0x1C
53#define REG_TXG2CON 0x1D
54#define REG_ESLOTG23 0x1E
55#define REG_ESLOTG45 0x1F
56#define REG_ESLOTG67 0x20
57#define REG_TXPEND 0x21
58#define REG_WAKECON 0x22
59#define REG_FROMOFFSET 0x23
c9f883f6 60#define REG_TXSTAT 0x24 /* TX MAC Status Register */
554b4949
AA		 61#define REG_TXBCON1 0x25
62#define REG_GATECLK 0x26
63#define REG_TXTIME 0x27
64#define REG_HSYMTMRL 0x28
65#define REG_HSYMTMRH 0x29
c9f883f6 66#define REG_SOFTRST 0x2A /* Soft Reset */
554b4949
AA		 67#define REG_SECCON0 0x2C
68#define REG_SECCON1 0x2D
c9f883f6 69#define REG_TXSTBL 0x2E /* TX Stabilization */
554b4949 70#define REG_RXSR 0x30
c9f883f6
AA		 71#define REG_INTSTAT 0x31 /* Interrupt Status */
72#define REG_INTCON 0x32 /* Interrupt Control */
73#define REG_GPIO 0x33 /* GPIO */
74#define REG_TRISGPIO 0x34 /* GPIO direction */
554b4949 75#define REG_SLPACK 0x35
c9f883f6 76#define REG_RFCTL 0x36 /* RF Control Mode Register */
554b4949
AA		 77#define REG_SECCR2 0x37
78#define REG_BBREG0 0x38
c9f883f6
AA		 79#define REG_BBREG1 0x39 /* Baseband Registers */
80#define REG_BBREG2 0x3A /* */
554b4949
AA		 81#define REG_BBREG3 0x3B
82#define REG_BBREG4 0x3C
c9f883f6
AA		 83#define REG_BBREG6 0x3E /* */
84#define REG_CCAEDTH 0x3F /* Energy Detection Threshold */
3731a334
AO		 85
86/* MRF24J40 Long Address Registers */
c9f883f6
AA		 87#define REG_RFCON0 0x200 /* RF Control Registers */
88#define REG_RFCON1 0x201
89#define REG_RFCON2 0x202
90#define REG_RFCON3 0x203
91#define REG_RFCON5 0x205
92#define REG_RFCON6 0x206
93#define REG_RFCON7 0x207
94#define REG_RFCON8 0x208
554b4949
AA		 95#define REG_SLPCAL0 0x209
96#define REG_SLPCAL1 0x20A
97#define REG_SLPCAL2 0x20B
98#define REG_RFSTATE 0x20F
c9f883f6
AA		 99#define REG_RSSI 0x210
100#define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */
101#define REG_SLPCON1 0x220
102#define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
103#define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
554b4949
AA		 104#define REG_REMCNTL 0x224
105#define REG_REMCNTH 0x225
106#define REG_MAINCNT0 0x226
107#define REG_MAINCNT1 0x227
108#define REG_MAINCNT2 0x228
109#define REG_MAINCNT3 0x229
c9f883f6 110#define REG_TESTMODE 0x22F /* Test mode */
554b4949
AA		 111#define REG_ASSOEAR0 0x230
112#define REG_ASSOEAR1 0x231
113#define REG_ASSOEAR2 0x232
114#define REG_ASSOEAR3 0x233
115#define REG_ASSOEAR4 0x234
116#define REG_ASSOEAR5 0x235
117#define REG_ASSOEAR6 0x236
118#define REG_ASSOEAR7 0x237
119#define REG_ASSOSAR0 0x238
120#define REG_ASSOSAR1 0x239
121#define REG_UNONCE0 0x240
122#define REG_UNONCE1 0x241
123#define REG_UNONCE2 0x242
124#define REG_UNONCE3 0x243
125#define REG_UNONCE4 0x244
126#define REG_UNONCE5 0x245
127#define REG_UNONCE6 0x246
128#define REG_UNONCE7 0x247
129#define REG_UNONCE8 0x248
130#define REG_UNONCE9 0x249
131#define REG_UNONCE10 0x24A
132#define REG_UNONCE11 0x24B
133#define REG_UNONCE12 0x24C
c9f883f6 134#define REG_RX_FIFO 0x300 /* Receive FIFO */
3731a334
AO		 135
136/* Device configuration: Only channels 11-26 on page 0 are supported. */
137#define MRF24J40_CHAN_MIN 11
138#define MRF24J40_CHAN_MAX 26
139#define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
140 - ((u32)1 << MRF24J40_CHAN_MIN))
141
142#define TX_FIFO_SIZE 128 /* From datasheet */
143#define RX_FIFO_SIZE 144 /* From datasheet */
144#define SET_CHANNEL_DELAY_US 192 /* From datasheet */
145
db9e0ee8
SV		 146enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC };
147
3731a334
AO		 148/* Device Private Data */
149struct mrf24j40 {
150 struct spi_device *spi;
5a504397 151 struct ieee802154_hw *hw;
3731a334 152
b0156792
AA		 153 struct regmap *regmap_short;
154 struct regmap *regmap_long;
6844a0e4
AA		 155
156 /* for writing txfifo */
157 struct spi_message tx_msg;
158 u8 tx_hdr_buf[2];
159 struct spi_transfer tx_hdr_trx;
160 u8 tx_len_buf[2];
161 struct spi_transfer tx_len_trx;
162 struct spi_transfer tx_buf_trx;
163 struct sk_buff *tx_skb;
164
165 /* post transmit message to send frame out */
166 struct spi_message tx_post_msg;
167 u8 tx_post_buf[2];
168 struct spi_transfer tx_post_trx;
169
c91a3011
AA		 170 /* for protect/unprotect/read length rxfifo */
171 struct spi_message rx_msg;
172 u8 rx_buf[3];
173 struct spi_transfer rx_trx;
174
175 /* receive handling */
176 struct spi_message rx_buf_msg;
177 u8 rx_addr_buf[2];
178 struct spi_transfer rx_addr_trx;
179 u8 rx_lqi_buf[2];
180 struct spi_transfer rx_lqi_trx;
181 u8 rx_fifo_buf[RX_FIFO_SIZE];
182 struct spi_transfer rx_fifo_buf_trx;
183
37441611
AA		 184 /* isr handling for reading intstat */
185 struct spi_message irq_msg;
186 u8 irq_buf[2];
187 struct spi_transfer irq_trx;
3731a334
AO		 188};
189
b0156792
AA		 190/* regmap information for short address register access */
191#define MRF24J40_SHORT_WRITE 0x01
192#define MRF24J40_SHORT_READ 0x00
193#define MRF24J40_SHORT_NUMREGS 0x3F
194
195/* regmap information for long address register access */
196#define MRF24J40_LONG_ACCESS 0x80
197#define MRF24J40_LONG_NUMREGS 0x38F
198
3731a334
AO		 199/* Read/Write SPI Commands for Short and Long Address registers. */
200#define MRF24J40_READSHORT(reg) ((reg) << 1)
201#define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
202#define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
203#define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
204
cf82dabd
AO		 205/* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
206#define MAX_SPI_SPEED_HZ 10000000
3731a334
AO		 207
208#define printdev(X) (&X->spi->dev)
209
b0156792
AA		 210static bool
211mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg)
212{
213 switch (reg) {
214 case REG_RXMCR:
215 case REG_PANIDL:
216 case REG_PANIDH:
217 case REG_SADRL:
218 case REG_SADRH:
219 case REG_EADR0:
220 case REG_EADR1:
221 case REG_EADR2:
222 case REG_EADR3:
223 case REG_EADR4:
224 case REG_EADR5:
225 case REG_EADR6:
226 case REG_EADR7:
227 case REG_RXFLUSH:
228 case REG_ORDER:
229 case REG_TXMCR:
230 case REG_ACKTMOUT:
231 case REG_ESLOTG1:
232 case REG_SYMTICKL:
233 case REG_SYMTICKH:
234 case REG_PACON0:
235 case REG_PACON1:
236 case REG_PACON2:
237 case REG_TXBCON0:
238 case REG_TXNCON:
239 case REG_TXG1CON:
240 case REG_TXG2CON:
241 case REG_ESLOTG23:
242 case REG_ESLOTG45:
243 case REG_ESLOTG67:
244 case REG_TXPEND:
245 case REG_WAKECON:
246 case REG_FROMOFFSET:
247 case REG_TXBCON1:
248 case REG_GATECLK:
249 case REG_TXTIME:
250 case REG_HSYMTMRL:
251 case REG_HSYMTMRH:
252 case REG_SOFTRST:
253 case REG_SECCON0:
254 case REG_SECCON1:
255 case REG_TXSTBL:
256 case REG_RXSR:
257 case REG_INTCON:
258 case REG_TRISGPIO:
259 case REG_GPIO:
260 case REG_RFCTL:
261 case REG_SLPACK:
262 case REG_BBREG0:
263 case REG_BBREG1:
264 case REG_BBREG2:
265 case REG_BBREG3:
266 case REG_BBREG4:
267 case REG_BBREG6:
268 case REG_CCAEDTH:
269 return true;
270 default:
271 return false;
272 }
273}
274
275static bool
276mrf24j40_short_reg_readable(struct device *dev, unsigned int reg)
277{
278 bool rc;
279
280 /* all writeable are also readable */
281 rc = mrf24j40_short_reg_writeable(dev, reg);
282 if (rc)
283 return rc;
284
285 /* readonly regs */
286 switch (reg) {
287 case REG_TXSTAT:
288 case REG_INTSTAT:
289 return true;
290 default:
291 return false;
292 }
293}
294
295static bool
296mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg)
297{
298 /* can be changed during runtime */
299 switch (reg) {
300 case REG_TXSTAT:
301 case REG_INTSTAT:
302 case REG_RXFLUSH:
303 case REG_TXNCON:
304 case REG_SOFTRST:
305 case REG_RFCTL:
306 case REG_TXBCON0:
307 case REG_TXG1CON:
308 case REG_TXG2CON:
309 case REG_TXBCON1:
310 case REG_SECCON0:
311 case REG_RXSR:
312 case REG_SLPACK:
313 case REG_SECCR2:
314 case REG_BBREG6:
315 /* use them in spi_async and regmap so it's volatile */
316 case REG_BBREG1:
317 return true;
318 default:
319 return false;
320 }
321}
322
323static bool
324mrf24j40_short_reg_precious(struct device *dev, unsigned int reg)
325{
326 /* don't clear irq line on read */
327 switch (reg) {
328 case REG_INTSTAT:
329 return true;
330 default:
331 return false;
332 }
333}
334
335static const struct regmap_config mrf24j40_short_regmap = {
336 .name = "mrf24j40_short",
337 .reg_bits = 7,
338 .val_bits = 8,
339 .pad_bits = 1,
340 .write_flag_mask = MRF24J40_SHORT_WRITE,
341 .read_flag_mask = MRF24J40_SHORT_READ,
342 .cache_type = REGCACHE_RBTREE,
343 .max_register = MRF24J40_SHORT_NUMREGS,
344 .writeable_reg = mrf24j40_short_reg_writeable,
345 .readable_reg = mrf24j40_short_reg_readable,
346 .volatile_reg = mrf24j40_short_reg_volatile,
347 .precious_reg = mrf24j40_short_reg_precious,
348};
349
350static bool
351mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg)
352{
353 switch (reg) {
354 case REG_RFCON0:
355 case REG_RFCON1:
356 case REG_RFCON2:
357 case REG_RFCON3:
358 case REG_RFCON5:
359 case REG_RFCON6:
360 case REG_RFCON7:
361 case REG_RFCON8:
362 case REG_SLPCAL2:
363 case REG_SLPCON0:
364 case REG_SLPCON1:
365 case REG_WAKETIMEL:
366 case REG_WAKETIMEH:
367 case REG_REMCNTL:
368 case REG_REMCNTH:
369 case REG_MAINCNT0:
370 case REG_MAINCNT1:
371 case REG_MAINCNT2:
372 case REG_MAINCNT3:
373 case REG_TESTMODE:
374 case REG_ASSOEAR0:
375 case REG_ASSOEAR1:
376 case REG_ASSOEAR2:
377 case REG_ASSOEAR3:
378 case REG_ASSOEAR4:
379 case REG_ASSOEAR5:
380 case REG_ASSOEAR6:
381 case REG_ASSOEAR7:
382 case REG_ASSOSAR0:
383 case REG_ASSOSAR1:
384 case REG_UNONCE0:
385 case REG_UNONCE1:
386 case REG_UNONCE2:
387 case REG_UNONCE3:
388 case REG_UNONCE4:
389 case REG_UNONCE5:
390 case REG_UNONCE6:
391 case REG_UNONCE7:
392 case REG_UNONCE8:
393 case REG_UNONCE9:
394 case REG_UNONCE10:
395 case REG_UNONCE11:
396 case REG_UNONCE12:
397 return true;
398 default:
399 return false;
400 }
401}
402
403static bool
404mrf24j40_long_reg_readable(struct device *dev, unsigned int reg)
405{
406 bool rc;
407
408 /* all writeable are also readable */
409 rc = mrf24j40_long_reg_writeable(dev, reg);
410 if (rc)
411 return rc;
412
413 /* readonly regs */
414 switch (reg) {
415 case REG_SLPCAL0:
416 case REG_SLPCAL1:
417 case REG_RFSTATE:
418 case REG_RSSI:
419 return true;
420 default:
421 return false;
422 }
423}
424
425static bool
426mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg)
427{
428 /* can be changed during runtime */
429 switch (reg) {
430 case REG_SLPCAL0:
431 case REG_SLPCAL1:
432 case REG_SLPCAL2:
433 case REG_RFSTATE:
434 case REG_RSSI:
435 case REG_MAINCNT3:
436 return true;
437 default:
438 return false;
439 }
440}
441
442static const struct regmap_config mrf24j40_long_regmap = {
443 .name = "mrf24j40_long",
444 .reg_bits = 11,
445 .val_bits = 8,
446 .pad_bits = 5,
447 .write_flag_mask = MRF24J40_LONG_ACCESS,
448 .read_flag_mask = MRF24J40_LONG_ACCESS,
449 .cache_type = REGCACHE_RBTREE,
450 .max_register = MRF24J40_LONG_NUMREGS,
451 .writeable_reg = mrf24j40_long_reg_writeable,
452 .readable_reg = mrf24j40_long_reg_readable,
453 .volatile_reg = mrf24j40_long_reg_volatile,
454};
455
456static int mrf24j40_long_regmap_write(void *context, const void *data,
457 size_t count)
458{
459 struct spi_device *spi = context;
460 u8 buf[3];
461
462 if (count > 3)
463 return -EINVAL;
464
465 /* regmap supports read/write mask only in frist byte
466 * long write access need to set the 12th bit, so we
467 * make special handling for write.
468 */
469 memcpy(buf, data, count);
470 buf[1] |= (1 << 4);
471
472 return spi_write(spi, buf, count);
473}
474
475static int
476mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size,
477 void *val, size_t val_size)
478{
479 struct spi_device *spi = context;
480
481 return spi_write_then_read(spi, reg, reg_size, val, val_size);
482}
483
484static const struct regmap_bus mrf24j40_long_regmap_bus = {
485 .write = mrf24j40_long_regmap_write,
486 .read = mrf24j40_long_regmap_read,
487 .reg_format_endian_default = REGMAP_ENDIAN_BIG,
488 .val_format_endian_default = REGMAP_ENDIAN_BIG,
489};
490
6844a0e4
AA		 491static void write_tx_buf_complete(void *context)
492{
493 struct mrf24j40 *devrec = context;
494 __le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb);
495 u8 val = 0x01;
496 int ret;
497
498 if (ieee802154_is_ackreq(fc))
499 val |= 0x04;
500
501 devrec->tx_post_msg.complete = NULL;
502 devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON);
503 devrec->tx_post_buf[1] = val;
504
505 ret = spi_async(devrec->spi, &devrec->tx_post_msg);
506 if (ret)
507 dev_err(printdev(devrec), "SPI write Failed for transmit buf\n");
508}
509
3731a334
AO		 510/* This function relies on an undocumented write method. Once a write command
511 and address is set, as many bytes of data as desired can be clocked into
512 the device. The datasheet only shows setting one byte at a time. */
513static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
514 const u8 *data, size_t length)
515{
3731a334 516 u16 cmd;
6844a0e4 517 int ret;
3731a334
AO		 518
519 /* Range check the length. 2 bytes are used for the length fields.*/
520 if (length > TX_FIFO_SIZE-2) {
521 dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
522 length = TX_FIFO_SIZE-2;
523 }
524
3731a334 525 cmd = MRF24J40_WRITELONG(reg);
6844a0e4
AA		 526 devrec->tx_hdr_buf[0] = cmd >> 8 & 0xff;
527 devrec->tx_hdr_buf[1] = cmd & 0xff;
528 devrec->tx_len_buf[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
529 devrec->tx_len_buf[1] = length; /* Total length */
530 devrec->tx_buf_trx.tx_buf = data;
531 devrec->tx_buf_trx.len = length;
532
533 ret = spi_async(devrec->spi, &devrec->tx_msg);
3731a334
AO		 534 if (ret)
535 dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
536
3731a334
AO		 537 return ret;
538}
539
6844a0e4
AA		 540static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb)
541{
542 struct mrf24j40 *devrec = hw->priv;
543
544 dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
545 devrec->tx_skb = skb;
546
547 return write_tx_buf(devrec, 0x000, skb->data, skb->len);
548}
549
5a504397 550static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level)
3731a334
AO		 551{
552 /* TODO: */
ca079ad6 553 pr_warn("mrf24j40: ed not implemented\n");
3731a334
AO		 554 *level = 0;
555 return 0;
556}
557
5a504397 558static int mrf24j40_start(struct ieee802154_hw *hw)
3731a334 559{
5a504397 560 struct mrf24j40 *devrec = hw->priv;
3731a334
AO		 561
562 dev_dbg(printdev(devrec), "start\n");
563
42c7148e
AA		 564 /* Clear TXNIE and RXIE. Enable interrupts */
565 return regmap_update_bits(devrec->regmap_short, REG_INTCON,
566 0x01 | 0x08, 0x00);
3731a334
AO		 567}
568
5a504397 569static void mrf24j40_stop(struct ieee802154_hw *hw)
3731a334 570{
5a504397 571 struct mrf24j40 *devrec = hw->priv;
529160dc 572
3731a334
AO		 573 dev_dbg(printdev(devrec), "stop\n");
574
42c7148e
AA		 575 /* Set TXNIE and RXIE. Disable Interrupts */
576 regmap_update_bits(devrec->regmap_short, REG_INTCON, 0x01 | 0x08,
577 0x01 | 0x08);
3731a334
AO		 578}
579
e37d2ec8 580static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
3731a334 581{
5a504397 582 struct mrf24j40 *devrec = hw->priv;
3731a334
AO		 583 u8 val;
584 int ret;
585
586 dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
587
588 WARN_ON(page != 0);
589 WARN_ON(channel < MRF24J40_CHAN_MIN);
590 WARN_ON(channel > MRF24J40_CHAN_MAX);
591
592 /* Set Channel TODO */
593 val = (channel-11) << 4 | 0x03;
42c7148e
AA		 594 ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0, 0xf0, val);
595 if (ret)
596 return ret;
3731a334
AO		 597
598 /* RF Reset */
42c7148e 599 ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, 0x04, 0x04);
3731a334
AO		 600 if (ret)
601 return ret;
3731a334 602
42c7148e
AA		 603 ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, 0x04, 0x00);
604 if (!ret)
605 udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
3731a334 606
42c7148e 607 return ret;
3731a334
AO		 608}
609
5a504397 610static int mrf24j40_filter(struct ieee802154_hw *hw,
3731a334
AO		 611 struct ieee802154_hw_addr_filt *filt,
612 unsigned long changed)
613{
5a504397 614 struct mrf24j40 *devrec = hw->priv;
3731a334
AO		 615
616 dev_dbg(printdev(devrec), "filter\n");
617
57205c14 618 if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
3731a334
AO		 619 /* Short Addr */
620 u8 addrh, addrl;
529160dc 621
b70ab2e8
PB		 622 addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff;
623 addrl = le16_to_cpu(filt->short_addr) & 0xff;
3731a334 624
42c7148e
AA		 625 regmap_write(devrec->regmap_short, REG_SADRH, addrh);
626 regmap_write(devrec->regmap_short, REG_SADRL, addrl);
3731a334
AO		 627 dev_dbg(printdev(devrec),
628 "Set short addr to %04hx\n", filt->short_addr);
629 }
630
57205c14 631 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
3731a334 632 /* Device Address */
b70ab2e8
PB		 633 u8 i, addr[8];
634
635 memcpy(addr, &filt->ieee_addr, 8);
3731a334 636 for (i = 0; i < 8; i++)
42c7148e
AA		 637 regmap_write(devrec->regmap_short, REG_EADR0 + i,
638 addr[i]);
3731a334
AO		 639
640#ifdef DEBUG
ca079ad6 641 pr_debug("Set long addr to: ");
3731a334 642 for (i = 0; i < 8; i++)
ca079ad6
VB		 643 pr_debug("%02hhx ", addr[7 - i]);
644 pr_debug("\n");
3731a334
AO		 645#endif
646 }
647
57205c14 648 if (changed & IEEE802154_AFILT_PANID_CHANGED) {
3731a334
AO		 649 /* PAN ID */
650 u8 panidl, panidh;
529160dc 651
b70ab2e8
PB		 652 panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff;
653 panidl = le16_to_cpu(filt->pan_id) & 0xff;
42c7148e
AA		 654 regmap_write(devrec->regmap_short, REG_PANIDH, panidh);
655 regmap_write(devrec->regmap_short, REG_PANIDL, panidl);
3731a334
AO		 656
657 dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
658 }
659
57205c14 660 if (changed & IEEE802154_AFILT_PANC_CHANGED) {
3731a334
AO		 661 /* Pan Coordinator */
662 u8 val;
663 int ret;
664
3731a334 665 if (filt->pan_coord)
42c7148e 666 val = 0x8;
3731a334 667 else
42c7148e
AA		 668 val = 0x0;
669 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x8,
670 val);
671 if (ret)
672 return ret;
3731a334
AO		 673
674 /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
675 * REG_ORDER is maintained as default (no beacon/superframe).
676 */
677
678 dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
ce261bc3 679 filt->pan_coord ? "on" : "off");
3731a334
AO		 680 }
681
682 return 0;
683}
684
c91a3011 685static void mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 *devrec)
3731a334 686{
c91a3011 687 int ret;
3731a334 688
c91a3011
AA		 689 /* Turn back on reception of packets off the air. */
690 devrec->rx_msg.complete = NULL;
691 devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
692 devrec->rx_buf[1] = 0x00; /* CLR RXDECINV */
693 ret = spi_async(devrec->spi, &devrec->rx_msg);
3731a334 694 if (ret)
c91a3011
AA		 695 dev_err(printdev(devrec), "failed to unlock rx buffer\n");
696}
3731a334 697
c91a3011
AA		 698static void mrf24j40_handle_rx_read_buf_complete(void *context)
699{
700 struct mrf24j40 *devrec = context;
701 u8 len = devrec->rx_buf[2];
702 u8 rx_local_buf[RX_FIFO_SIZE];
703 struct sk_buff *skb;
704
705 memcpy(rx_local_buf, devrec->rx_fifo_buf, len);
706 mrf24j40_handle_rx_read_buf_unlock(devrec);
707
708 skb = dev_alloc_skb(IEEE802154_MTU);
3731a334 709 if (!skb) {
c91a3011
AA		 710 dev_err(printdev(devrec), "failed to allocate skb\n");
711 return;
3731a334
AO		 712 }
713
c91a3011
AA		 714 memcpy(skb_put(skb, len), rx_local_buf, len);
715 ieee802154_rx_irqsafe(devrec->hw, skb, 0);
716
717#ifdef DEBUG
718 print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ", DUMP_PREFIX_OFFSET, 16, 1,
719 rx_local_buf, len, 0);
720 pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
721 devrec->rx_lqi_buf[0], devrec->rx_lqi_buf[1]);
722#endif
723}
724
725static void mrf24j40_handle_rx_read_buf(void *context)
726{
727 struct mrf24j40 *devrec = context;
728 u16 cmd;
729 int ret;
730
731 /* if length is invalid read the full MTU */
732 if (!ieee802154_is_valid_psdu_len(devrec->rx_buf[2]))
733 devrec->rx_buf[2] = IEEE802154_MTU;
734
735 cmd = MRF24J40_READLONG(REG_RX_FIFO + 1);
736 devrec->rx_addr_buf[0] = cmd >> 8 & 0xff;
737 devrec->rx_addr_buf[1] = cmd & 0xff;
738 devrec->rx_fifo_buf_trx.len = devrec->rx_buf[2];
739 ret = spi_async(devrec->spi, &devrec->rx_buf_msg);
740 if (ret) {
741 dev_err(printdev(devrec), "failed to read rx buffer\n");
742 mrf24j40_handle_rx_read_buf_unlock(devrec);
3731a334 743 }
c91a3011 744}
3731a334 745
c91a3011
AA		 746static void mrf24j40_handle_rx_read_len(void *context)
747{
748 struct mrf24j40 *devrec = context;
749 u16 cmd;
750 int ret;
3731a334 751
c91a3011
AA		 752 /* read the length of received frame */
753 devrec->rx_msg.complete = mrf24j40_handle_rx_read_buf;
754 devrec->rx_trx.len = 3;
755 cmd = MRF24J40_READLONG(REG_RX_FIFO);
756 devrec->rx_buf[0] = cmd >> 8 & 0xff;
757 devrec->rx_buf[1] = cmd & 0xff;
3731a334 758
c91a3011
AA		 759 ret = spi_async(devrec->spi, &devrec->rx_msg);
760 if (ret) {
761 dev_err(printdev(devrec), "failed to read rx buffer length\n");
762 mrf24j40_handle_rx_read_buf_unlock(devrec);
763 }
764}
3731a334 765
c91a3011
AA		 766static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
767{
768 /* Turn off reception of packets off the air. This prevents the
769 * device from overwriting the buffer while we're reading it.
770 */
771 devrec->rx_msg.complete = mrf24j40_handle_rx_read_len;
772 devrec->rx_trx.len = 2;
773 devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1);
774 devrec->rx_buf[1] = 0x04; /* SET RXDECINV */
775
776 return spi_async(devrec->spi, &devrec->rx_msg);
3731a334
AO		 777}
778
2323cf38
AA		 779static int
780mrf24j40_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
781 u8 retries)
782{
783 struct mrf24j40 *devrec = hw->priv;
784 u8 val;
785
786 /* min_be */
787 val = min_be << 3;
788 /* csma backoffs */
789 val |= retries;
790
791 return regmap_update_bits(devrec->regmap_short, REG_TXMCR, 0x1f, val);
792}
793
f1d78127
AA		 794static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw,
795 const struct wpan_phy_cca *cca)
796{
797 struct mrf24j40 *devrec = hw->priv;
798 u8 val;
799
800 /* mapping 802.15.4 to driver spec */
801 switch (cca->mode) {
802 case NL802154_CCA_ENERGY:
803 val = 2;
804 break;
805 case NL802154_CCA_CARRIER:
806 val = 1;
807 break;
808 case NL802154_CCA_ENERGY_CARRIER:
809 switch (cca->opt) {
810 case NL802154_CCA_OPT_ENERGY_CARRIER_AND:
811 val = 3;
812 break;
813 default:
814 return -EINVAL;
815 }
816 break;
817 default:
818 return -EINVAL;
819 }
820
821 return regmap_update_bits(devrec->regmap_short, REG_BBREG2, 0xc0,
822 val << 6);
823}
824
e33a0f96
AA		 825/* array for representing ed levels */
826static const s32 mrf24j40_ed_levels[] = {
827 -9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100,
828 -8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100,
829 -7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100,
830 -6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100,
831 -5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100,
832 -4000, -3900, -3800, -3700, -3600, -3500
833};
834
835/* map ed levels to register value */
836static const s32 mrf24j40_ed_levels_map[][2] = {
837 { -9000, 0 }, { -8900, 1 }, { -8800, 2 }, { -8700, 5 }, { -8600, 9 },
838 { -8500, 13 }, { -8400, 18 }, { -8300, 23 }, { -8200, 27 },
839 { -8100, 32 }, { -8000, 37 }, { -7900, 43 }, { -7800, 48 },
840 { -7700, 53 }, { -7600, 58 }, { -7500, 63 }, { -7400, 68 },
841 { -7300, 73 }, { -7200, 78 }, { -7100, 83 }, { -7000, 89 },
842 { -6900, 95 }, { -6800, 100 }, { -6700, 107 }, { -6600, 111 },
843 { -6500, 117 }, { -6400, 121 }, { -6300, 125 }, { -6200, 129 },
844 { -6100, 133 }, { -6000, 138 }, { -5900, 143 }, { -5800, 148 },
845 { -5700, 153 }, { -5600, 159 }, { -5500, 165 }, { -5400, 170 },
846 { -5300, 176 }, { -5200, 183 }, { -5100, 188 }, { -5000, 193 },
847 { -4900, 198 }, { -4800, 203 }, { -4700, 207 }, { -4600, 212 },
848 { -4500, 216 }, { -4400, 221 }, { -4300, 225 }, { -4200, 228 },
849 { -4100, 233 }, { -4000, 239 }, { -3900, 245 }, { -3800, 250 },
850 { -3700, 253 }, { -3600, 254 }, { -3500, 255 },
851};
852
853static int mrf24j40_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
854{
855 struct mrf24j40 *devrec = hw->priv;
856 int i;
857
858 for (i = 0; i < ARRAY_SIZE(mrf24j40_ed_levels_map); i++) {
859 if (mrf24j40_ed_levels_map[i][0] == mbm)
860 return regmap_write(devrec->regmap_short, REG_CCAEDTH,
861 mrf24j40_ed_levels_map[i][1]);
862 }
863
864 return -EINVAL;
865}
866
16301861 867static const struct ieee802154_ops mrf24j40_ops = {
3731a334 868 .owner = THIS_MODULE,
6844a0e4 869 .xmit_async = mrf24j40_tx,
3731a334
AO		 870 .ed = mrf24j40_ed,
871 .start = mrf24j40_start,
872 .stop = mrf24j40_stop,
873 .set_channel = mrf24j40_set_channel,
874 .set_hw_addr_filt = mrf24j40_filter,
2323cf38 875 .set_csma_params = mrf24j40_csma_params,
f1d78127 876 .set_cca_mode = mrf24j40_set_cca_mode,
e33a0f96 877 .set_cca_ed_level = mrf24j40_set_cca_ed_level,
3731a334
AO		 878};
879
37441611 880static void mrf24j40_intstat_complete(void *context)
3731a334 881{
37441611
AA		 882 struct mrf24j40 *devrec = context;
883 u8 intstat = devrec->irq_buf[1];
3731a334 884
37441611 885 enable_irq(devrec->spi->irq);
3731a334
AO		 886
887 /* Check for TX complete */
888 if (intstat & 0x1)
6844a0e4 889 ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false);
3731a334
AO		 890
891 /* Check for Rx */
892 if (intstat & 0x8)
893 mrf24j40_handle_rx(devrec);
37441611
AA		 894}
895
896static irqreturn_t mrf24j40_isr(int irq, void *data)
897{
898 struct mrf24j40 *devrec = data;
899 int ret;
900
901 disable_irq_nosync(irq);
902
903 devrec->irq_buf[0] = MRF24J40_READSHORT(REG_INTSTAT);
904 /* Read the interrupt status */
905 ret = spi_async(devrec->spi, &devrec->irq_msg);
906 if (ret) {
907 enable_irq(irq);
908 return IRQ_NONE;
909 }
3731a334 910
4a4e1da8 911 return IRQ_HANDLED;
3731a334
AO		 912}
913
3dac9a79
VB		 914static int mrf24j40_hw_init(struct mrf24j40 *devrec)
915{
916 int ret;
3dac9a79
VB		 917
918 /* Initialize the device.
919 From datasheet section 3.2: Initialization. */
42c7148e 920 ret = regmap_write(devrec->regmap_short, REG_SOFTRST, 0x07);
3dac9a79
VB		 921 if (ret)
922 goto err_ret;
923
42c7148e 924 ret = regmap_write(devrec->regmap_short, REG_PACON2, 0x98);
3dac9a79
VB		 925 if (ret)
926 goto err_ret;
927
42c7148e 928 ret = regmap_write(devrec->regmap_short, REG_TXSTBL, 0x95);
3dac9a79
VB		 929 if (ret)
930 goto err_ret;
931
42c7148e 932 ret = regmap_write(devrec->regmap_long, REG_RFCON0, 0x03);
3dac9a79
VB		 933 if (ret)
934 goto err_ret;
935
42c7148e 936 ret = regmap_write(devrec->regmap_long, REG_RFCON1, 0x01);
3dac9a79
VB		 937 if (ret)
938 goto err_ret;
939
42c7148e 940 ret = regmap_write(devrec->regmap_long, REG_RFCON2, 0x80);
3dac9a79
VB		 941 if (ret)
942 goto err_ret;
943
42c7148e 944 ret = regmap_write(devrec->regmap_long, REG_RFCON6, 0x90);
3dac9a79
VB		 945 if (ret)
946 goto err_ret;
947
42c7148e 948 ret = regmap_write(devrec->regmap_long, REG_RFCON7, 0x80);
3dac9a79
VB		 949 if (ret)
950 goto err_ret;
951
42c7148e 952 ret = regmap_write(devrec->regmap_long, REG_RFCON8, 0x10);
3dac9a79
VB		 953 if (ret)
954 goto err_ret;
955
42c7148e 956 ret = regmap_write(devrec->regmap_long, REG_SLPCON1, 0x21);
3dac9a79
VB		 957 if (ret)
958 goto err_ret;
959
42c7148e 960 ret = regmap_write(devrec->regmap_short, REG_BBREG2, 0x80);
3dac9a79
VB		 961 if (ret)
962 goto err_ret;
963
42c7148e 964 ret = regmap_write(devrec->regmap_short, REG_CCAEDTH, 0x60);
3dac9a79
VB		 965 if (ret)
966 goto err_ret;
967
42c7148e 968 ret = regmap_write(devrec->regmap_short, REG_BBREG6, 0x40);
3dac9a79
VB		 969 if (ret)
970 goto err_ret;
971
42c7148e 972 ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x04);
3dac9a79
VB		 973 if (ret)
974 goto err_ret;
975
42c7148e 976 ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x0);
3dac9a79
VB		 977 if (ret)
978 goto err_ret;
979
980 udelay(192);
981
982 /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
42c7148e 983 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x03, 0x00);
3dac9a79
VB		 984 if (ret)
985 goto err_ret;
986
db9e0ee8
SV		 987 if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) {
988 /* Enable external amplifier.
989 * From MRF24J40MC datasheet section 1.3: Operation.
990 */
42c7148e
AA		 991 regmap_update_bits(devrec->regmap_long, REG_TESTMODE, 0x07,
992 0x07);
db9e0ee8 993
42c7148e
AA		 994 /* Set GPIO3 as output. */
995 regmap_update_bits(devrec->regmap_short, REG_TRISGPIO, 0x08,
996 0x08);
db9e0ee8 997
42c7148e
AA		 998 /* Set GPIO3 HIGH to enable U5 voltage regulator */
999 regmap_update_bits(devrec->regmap_short, REG_GPIO, 0x08, 0x08);
db9e0ee8
SV		 1000
1001 /* Reduce TX pwr to meet FCC requirements.
1002 * From MRF24J40MC datasheet section 3.1.1
1003 */
42c7148e 1004 regmap_write(devrec->regmap_long, REG_RFCON3, 0x28);
db9e0ee8
SV		 1005 }
1006
3dac9a79
VB		 1007 return 0;
1008
1009err_ret:
1010 return ret;
1011}
1012
6844a0e4
AA		 1013static void
1014mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec)
1015{
1016 spi_message_init(&devrec->tx_msg);
1017 devrec->tx_msg.context = devrec;
1018 devrec->tx_msg.complete = write_tx_buf_complete;
1019 devrec->tx_hdr_trx.len = 2;
1020 devrec->tx_hdr_trx.tx_buf = devrec->tx_hdr_buf;
1021 spi_message_add_tail(&devrec->tx_hdr_trx, &devrec->tx_msg);
1022 devrec->tx_len_trx.len = 2;
1023 devrec->tx_len_trx.tx_buf = devrec->tx_len_buf;
1024 spi_message_add_tail(&devrec->tx_len_trx, &devrec->tx_msg);
1025 spi_message_add_tail(&devrec->tx_buf_trx, &devrec->tx_msg);
1026
1027 spi_message_init(&devrec->tx_post_msg);
1028 devrec->tx_post_msg.context = devrec;
1029 devrec->tx_post_trx.len = 2;
1030 devrec->tx_post_trx.tx_buf = devrec->tx_post_buf;
1031 spi_message_add_tail(&devrec->tx_post_trx, &devrec->tx_post_msg);
1032}
1033
c91a3011
AA		 1034static void
1035mrf24j40_setup_rx_spi_messages(struct mrf24j40 *devrec)
1036{
1037 spi_message_init(&devrec->rx_msg);
1038 devrec->rx_msg.context = devrec;
1039 devrec->rx_trx.len = 2;
1040 devrec->rx_trx.tx_buf = devrec->rx_buf;
1041 devrec->rx_trx.rx_buf = devrec->rx_buf;
1042 spi_message_add_tail(&devrec->rx_trx, &devrec->rx_msg);
1043
1044 spi_message_init(&devrec->rx_buf_msg);
1045 devrec->rx_buf_msg.context = devrec;
1046 devrec->rx_buf_msg.complete = mrf24j40_handle_rx_read_buf_complete;
1047 devrec->rx_addr_trx.len = 2;
1048 devrec->rx_addr_trx.tx_buf = devrec->rx_addr_buf;
1049 spi_message_add_tail(&devrec->rx_addr_trx, &devrec->rx_buf_msg);
1050 devrec->rx_fifo_buf_trx.rx_buf = devrec->rx_fifo_buf;
1051 spi_message_add_tail(&devrec->rx_fifo_buf_trx, &devrec->rx_buf_msg);
1052 devrec->rx_lqi_trx.len = 2;
1053 devrec->rx_lqi_trx.rx_buf = devrec->rx_lqi_buf;
1054 spi_message_add_tail(&devrec->rx_lqi_trx, &devrec->rx_buf_msg);
1055}
1056
37441611
AA		 1057static void
1058mrf24j40_setup_irq_spi_messages(struct mrf24j40 *devrec)
1059{
1060 spi_message_init(&devrec->irq_msg);
1061 devrec->irq_msg.context = devrec;
1062 devrec->irq_msg.complete = mrf24j40_intstat_complete;
1063 devrec->irq_trx.len = 2;
1064 devrec->irq_trx.tx_buf = devrec->irq_buf;
1065 devrec->irq_trx.rx_buf = devrec->irq_buf;
1066 spi_message_add_tail(&devrec->irq_trx, &devrec->irq_msg);
1067}
1068
766928fb
AA		 1069static void mrf24j40_phy_setup(struct mrf24j40 *devrec)
1070{
d344c912 1071 ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr);
766928fb 1072 devrec->hw->phy->current_channel = 11;
2323cf38
AA		 1073
1074 /* mrf24j40 supports max_minbe 0 - 3 */
1075 devrec->hw->phy->supported.max_minbe = 3;
1076 /* datasheet doesn't say anything about max_be, but we have min_be
1077 * So we assume the max_be default.
1078 */
1079 devrec->hw->phy->supported.min_maxbe = 5;
1080 devrec->hw->phy->supported.max_maxbe = 5;
f1d78127
AA		 1081
1082 devrec->hw->phy->cca.mode = NL802154_CCA_CARRIER;;
1083 devrec->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
1084 BIT(NL802154_CCA_CARRIER) |
1085 BIT(NL802154_CCA_ENERGY_CARRIER);
1086 devrec->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND);
e33a0f96
AA		 1087
1088 devrec->hw->phy->cca_ed_level = -6900;
1089 devrec->hw->phy->supported.cca_ed_levels = mrf24j40_ed_levels;
1090 devrec->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(mrf24j40_ed_levels);
766928fb
AA		 1091}
1092
bb1f4606 1093static int mrf24j40_probe(struct spi_device *spi)
3731a334
AO		 1094{
1095 int ret = -ENOMEM;
b2cfdf3c 1096 struct ieee802154_hw *hw;
3731a334
AO		 1097 struct mrf24j40 *devrec;
1098
ca079ad6 1099 dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq);
3731a334 1100
b2cfdf3c
AA		 1101 /* Register with the 802154 subsystem */
1102
1103 hw = ieee802154_alloc_hw(sizeof(*devrec), &mrf24j40_ops);
1104 if (!hw)
0aaf43f5 1105 goto err_ret;
b2cfdf3c
AA		 1106
1107 devrec = hw->priv;
1108 devrec->spi = spi;
1109 spi_set_drvdata(spi, devrec);
1110 devrec->hw = hw;
1111 devrec->hw->parent = &spi->dev;
1112 devrec->hw->phy->supported.channels[0] = CHANNEL_MASK;
2323cf38
AA		 1113 devrec->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT |
1114 IEEE802154_HW_CSMA_PARAMS;
b2cfdf3c 1115
e33a0f96
AA		 1116 devrec->hw->phy->flags = WPAN_PHY_FLAG_CCA_MODE |
1117 WPAN_PHY_FLAG_CCA_ED_LEVEL;
f1d78127 1118
6844a0e4 1119 mrf24j40_setup_tx_spi_messages(devrec);
c91a3011 1120 mrf24j40_setup_rx_spi_messages(devrec);
37441611 1121 mrf24j40_setup_irq_spi_messages(devrec);
6844a0e4 1122
b0156792
AA		 1123 devrec->regmap_short = devm_regmap_init_spi(spi,
1124 &mrf24j40_short_regmap);
1125 if (IS_ERR(devrec->regmap_short)) {
1126 ret = PTR_ERR(devrec->regmap_short);
1127 dev_err(&spi->dev, "Failed to allocate short register map: %d\n",
1128 ret);
1129 goto err_register_device;
1130 }
1131
1132 devrec->regmap_long = devm_regmap_init(&spi->dev,
1133 &mrf24j40_long_regmap_bus,
1134 spi, &mrf24j40_long_regmap);
1135 if (IS_ERR(devrec->regmap_long)) {
1136 ret = PTR_ERR(devrec->regmap_long);
1137 dev_err(&spi->dev, "Failed to allocate long register map: %d\n",
1138 ret);
1139 goto err_register_device;
1140 }
1141
78aedb6b
AA		 1142 if (spi->max_speed_hz > MAX_SPI_SPEED_HZ) {
1143 dev_warn(&spi->dev, "spi clock above possible maximum: %d",
1144 MAX_SPI_SPEED_HZ);
1145 return -EINVAL;
1146 }
3731a334 1147
3dac9a79 1148 ret = mrf24j40_hw_init(devrec);
3731a334 1149 if (ret)
a339e184 1150 goto err_register_device;
3731a334 1151
766928fb
AA		 1152 mrf24j40_phy_setup(devrec);
1153
37441611
AA		 1154 ret = devm_request_irq(&spi->dev, spi->irq, mrf24j40_isr,
1155 IRQF_TRIGGER_LOW, dev_name(&spi->dev),
1156 devrec);
3731a334
AO		 1157 if (ret) {
1158 dev_err(printdev(devrec), "Unable to get IRQ");
a339e184 1159 goto err_register_device;
3731a334
AO		 1160 }
1161
a339e184
AA		 1162 dev_dbg(printdev(devrec), "registered mrf24j40\n");
1163 ret = ieee802154_register_hw(devrec->hw);
1164 if (ret)
1165 goto err_register_device;
1166
3731a334
AO		 1167 return 0;
1168
3731a334 1169err_register_device:
5a504397 1170 ieee802154_free_hw(devrec->hw);
0aaf43f5 1171err_ret:
3731a334
AO		 1172 return ret;
1173}
1174
bb1f4606 1175static int mrf24j40_remove(struct spi_device *spi)
3731a334 1176{
4fa0a0ef 1177 struct mrf24j40 *devrec = spi_get_drvdata(spi);
3731a334
AO		 1178
1179 dev_dbg(printdev(devrec), "remove\n");
1180
5a504397
AA		 1181 ieee802154_unregister_hw(devrec->hw);
1182 ieee802154_free_hw(devrec->hw);
3731a334
AO		 1183 /* TODO: Will ieee802154_free_device() wait until ->xmit() is
1184 * complete? */
1185
3731a334
AO		 1186 return 0;
1187}
1188
2e6fd648
AA		 1189static const struct of_device_id mrf24j40_of_match[] = {
1190 { .compatible = "microchip,mrf24j40", .data = (void *)MRF24J40 },
1191 { .compatible = "microchip,mrf24j40ma", .data = (void *)MRF24J40MA },
1192 { .compatible = "microchip,mrf24j40mc", .data = (void *)MRF24J40MC },
1193 { },
1194};
1195MODULE_DEVICE_TABLE(of, mrf24j40_of_match);
1196
3731a334 1197static const struct spi_device_id mrf24j40_ids[] = {
db9e0ee8
SV		 1198 { "mrf24j40", MRF24J40 },
1199 { "mrf24j40ma", MRF24J40MA },
1200 { "mrf24j40mc", MRF24J40MC },
3731a334
AO		 1201 { },
1202};
1203MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
1204
1205static struct spi_driver mrf24j40_driver = {
1206 .driver = {
2e6fd648 1207 .of_match_table = of_match_ptr(mrf24j40_of_match),
3731a334 1208 .name = "mrf24j40",
3731a334
AO		 1209 .owner = THIS_MODULE,
1210 },
1211 .id_table = mrf24j40_ids,
1212 .probe = mrf24j40_probe,
bb1f4606 1213 .remove = mrf24j40_remove,
3731a334
AO		 1214};
1215
3d4a1316 1216module_spi_driver(mrf24j40_driver);
3731a334
AO		 1217
1218MODULE_LICENSE("GPL");
1219MODULE_AUTHOR("Alan Ott");
1220MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");
Linux 6.x block layer and io_uring tree(s)