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3731a334 AO |
1 | /* |
2 | * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller | |
3 | * | |
4 | * Copyright (C) 2012 Alan Ott <alan@signal11.us> | |
5 | * Signal 11 Software | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | #include <linux/spi/spi.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/module.h> | |
50861c7e | 25 | #include <linux/pinctrl/consumer.h> |
3731a334 AO |
26 | #include <net/wpan-phy.h> |
27 | #include <net/mac802154.h> | |
28 | ||
29 | /* MRF24J40 Short Address Registers */ | |
30 | #define REG_RXMCR 0x00 /* Receive MAC control */ | |
31 | #define REG_PANIDL 0x01 /* PAN ID (low) */ | |
32 | #define REG_PANIDH 0x02 /* PAN ID (high) */ | |
33 | #define REG_SADRL 0x03 /* Short address (low) */ | |
34 | #define REG_SADRH 0x04 /* Short address (high) */ | |
35 | #define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */ | |
36 | #define REG_TXMCR 0x11 /* Transmit MAC control */ | |
37 | #define REG_PACON0 0x16 /* Power Amplifier Control */ | |
38 | #define REG_PACON1 0x17 /* Power Amplifier Control */ | |
39 | #define REG_PACON2 0x18 /* Power Amplifier Control */ | |
40 | #define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */ | |
41 | #define REG_TXSTAT 0x24 /* TX MAC Status Register */ | |
42 | #define REG_SOFTRST 0x2A /* Soft Reset */ | |
43 | #define REG_TXSTBL 0x2E /* TX Stabilization */ | |
44 | #define REG_INTSTAT 0x31 /* Interrupt Status */ | |
45 | #define REG_INTCON 0x32 /* Interrupt Control */ | |
46 | #define REG_RFCTL 0x36 /* RF Control Mode Register */ | |
47 | #define REG_BBREG1 0x39 /* Baseband Registers */ | |
48 | #define REG_BBREG2 0x3A /* */ | |
49 | #define REG_BBREG6 0x3E /* */ | |
50 | #define REG_CCAEDTH 0x3F /* Energy Detection Threshold */ | |
51 | ||
52 | /* MRF24J40 Long Address Registers */ | |
53 | #define REG_RFCON0 0x200 /* RF Control Registers */ | |
54 | #define REG_RFCON1 0x201 | |
55 | #define REG_RFCON2 0x202 | |
56 | #define REG_RFCON3 0x203 | |
57 | #define REG_RFCON5 0x205 | |
58 | #define REG_RFCON6 0x206 | |
59 | #define REG_RFCON7 0x207 | |
60 | #define REG_RFCON8 0x208 | |
61 | #define REG_RSSI 0x210 | |
62 | #define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */ | |
63 | #define REG_SLPCON1 0x220 | |
64 | #define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */ | |
65 | #define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */ | |
66 | #define REG_RX_FIFO 0x300 /* Receive FIFO */ | |
67 | ||
68 | /* Device configuration: Only channels 11-26 on page 0 are supported. */ | |
69 | #define MRF24J40_CHAN_MIN 11 | |
70 | #define MRF24J40_CHAN_MAX 26 | |
71 | #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \ | |
72 | - ((u32)1 << MRF24J40_CHAN_MIN)) | |
73 | ||
74 | #define TX_FIFO_SIZE 128 /* From datasheet */ | |
75 | #define RX_FIFO_SIZE 144 /* From datasheet */ | |
76 | #define SET_CHANNEL_DELAY_US 192 /* From datasheet */ | |
77 | ||
78 | /* Device Private Data */ | |
79 | struct mrf24j40 { | |
80 | struct spi_device *spi; | |
81 | struct ieee802154_dev *dev; | |
82 | ||
83 | struct mutex buffer_mutex; /* only used to protect buf */ | |
84 | struct completion tx_complete; | |
85 | struct work_struct irqwork; | |
86 | u8 *buf; /* 3 bytes. Used for SPI single-register transfers. */ | |
87 | }; | |
88 | ||
89 | /* Read/Write SPI Commands for Short and Long Address registers. */ | |
90 | #define MRF24J40_READSHORT(reg) ((reg) << 1) | |
91 | #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1) | |
92 | #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5) | |
93 | #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4) | |
94 | ||
95 | /* Maximum speed to run the device at. TODO: Get the real max value from | |
96 | * someone at Microchip since it isn't in the datasheet. */ | |
97 | #define MAX_SPI_SPEED_HZ 1000000 | |
98 | ||
99 | #define printdev(X) (&X->spi->dev) | |
100 | ||
101 | static int write_short_reg(struct mrf24j40 *devrec, u8 reg, u8 value) | |
102 | { | |
103 | int ret; | |
104 | struct spi_message msg; | |
105 | struct spi_transfer xfer = { | |
106 | .len = 2, | |
107 | .tx_buf = devrec->buf, | |
108 | .rx_buf = devrec->buf, | |
109 | }; | |
110 | ||
111 | spi_message_init(&msg); | |
112 | spi_message_add_tail(&xfer, &msg); | |
113 | ||
114 | mutex_lock(&devrec->buffer_mutex); | |
115 | devrec->buf[0] = MRF24J40_WRITESHORT(reg); | |
116 | devrec->buf[1] = value; | |
117 | ||
118 | ret = spi_sync(devrec->spi, &msg); | |
119 | if (ret) | |
120 | dev_err(printdev(devrec), | |
121 | "SPI write Failed for short register 0x%hhx\n", reg); | |
122 | ||
123 | mutex_unlock(&devrec->buffer_mutex); | |
124 | return ret; | |
125 | } | |
126 | ||
127 | static int read_short_reg(struct mrf24j40 *devrec, u8 reg, u8 *val) | |
128 | { | |
129 | int ret = -1; | |
130 | struct spi_message msg; | |
131 | struct spi_transfer xfer = { | |
132 | .len = 2, | |
133 | .tx_buf = devrec->buf, | |
134 | .rx_buf = devrec->buf, | |
135 | }; | |
136 | ||
137 | spi_message_init(&msg); | |
138 | spi_message_add_tail(&xfer, &msg); | |
139 | ||
140 | mutex_lock(&devrec->buffer_mutex); | |
141 | devrec->buf[0] = MRF24J40_READSHORT(reg); | |
142 | devrec->buf[1] = 0; | |
143 | ||
144 | ret = spi_sync(devrec->spi, &msg); | |
145 | if (ret) | |
146 | dev_err(printdev(devrec), | |
147 | "SPI read Failed for short register 0x%hhx\n", reg); | |
148 | else | |
149 | *val = devrec->buf[1]; | |
150 | ||
151 | mutex_unlock(&devrec->buffer_mutex); | |
152 | return ret; | |
153 | } | |
154 | ||
155 | static int read_long_reg(struct mrf24j40 *devrec, u16 reg, u8 *value) | |
156 | { | |
157 | int ret; | |
158 | u16 cmd; | |
159 | struct spi_message msg; | |
160 | struct spi_transfer xfer = { | |
161 | .len = 3, | |
162 | .tx_buf = devrec->buf, | |
163 | .rx_buf = devrec->buf, | |
164 | }; | |
165 | ||
166 | spi_message_init(&msg); | |
167 | spi_message_add_tail(&xfer, &msg); | |
168 | ||
169 | cmd = MRF24J40_READLONG(reg); | |
170 | mutex_lock(&devrec->buffer_mutex); | |
171 | devrec->buf[0] = cmd >> 8 & 0xff; | |
172 | devrec->buf[1] = cmd & 0xff; | |
173 | devrec->buf[2] = 0; | |
174 | ||
175 | ret = spi_sync(devrec->spi, &msg); | |
176 | if (ret) | |
177 | dev_err(printdev(devrec), | |
178 | "SPI read Failed for long register 0x%hx\n", reg); | |
179 | else | |
180 | *value = devrec->buf[2]; | |
181 | ||
182 | mutex_unlock(&devrec->buffer_mutex); | |
183 | return ret; | |
184 | } | |
185 | ||
186 | static int write_long_reg(struct mrf24j40 *devrec, u16 reg, u8 val) | |
187 | { | |
188 | int ret; | |
189 | u16 cmd; | |
190 | struct spi_message msg; | |
191 | struct spi_transfer xfer = { | |
192 | .len = 3, | |
193 | .tx_buf = devrec->buf, | |
194 | .rx_buf = devrec->buf, | |
195 | }; | |
196 | ||
197 | spi_message_init(&msg); | |
198 | spi_message_add_tail(&xfer, &msg); | |
199 | ||
200 | cmd = MRF24J40_WRITELONG(reg); | |
201 | mutex_lock(&devrec->buffer_mutex); | |
202 | devrec->buf[0] = cmd >> 8 & 0xff; | |
203 | devrec->buf[1] = cmd & 0xff; | |
204 | devrec->buf[2] = val; | |
205 | ||
206 | ret = spi_sync(devrec->spi, &msg); | |
207 | if (ret) | |
208 | dev_err(printdev(devrec), | |
209 | "SPI write Failed for long register 0x%hx\n", reg); | |
210 | ||
211 | mutex_unlock(&devrec->buffer_mutex); | |
212 | return ret; | |
213 | } | |
214 | ||
215 | /* This function relies on an undocumented write method. Once a write command | |
216 | and address is set, as many bytes of data as desired can be clocked into | |
217 | the device. The datasheet only shows setting one byte at a time. */ | |
218 | static int write_tx_buf(struct mrf24j40 *devrec, u16 reg, | |
219 | const u8 *data, size_t length) | |
220 | { | |
221 | int ret; | |
222 | u16 cmd; | |
223 | u8 lengths[2]; | |
224 | struct spi_message msg; | |
225 | struct spi_transfer addr_xfer = { | |
226 | .len = 2, | |
227 | .tx_buf = devrec->buf, | |
228 | }; | |
229 | struct spi_transfer lengths_xfer = { | |
230 | .len = 2, | |
231 | .tx_buf = &lengths, /* TODO: Is DMA really required for SPI? */ | |
232 | }; | |
233 | struct spi_transfer data_xfer = { | |
234 | .len = length, | |
235 | .tx_buf = data, | |
236 | }; | |
237 | ||
238 | /* Range check the length. 2 bytes are used for the length fields.*/ | |
239 | if (length > TX_FIFO_SIZE-2) { | |
240 | dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n"); | |
241 | length = TX_FIFO_SIZE-2; | |
242 | } | |
243 | ||
244 | spi_message_init(&msg); | |
245 | spi_message_add_tail(&addr_xfer, &msg); | |
246 | spi_message_add_tail(&lengths_xfer, &msg); | |
247 | spi_message_add_tail(&data_xfer, &msg); | |
248 | ||
249 | cmd = MRF24J40_WRITELONG(reg); | |
250 | mutex_lock(&devrec->buffer_mutex); | |
251 | devrec->buf[0] = cmd >> 8 & 0xff; | |
252 | devrec->buf[1] = cmd & 0xff; | |
253 | lengths[0] = 0x0; /* Header Length. Set to 0 for now. TODO */ | |
254 | lengths[1] = length; /* Total length */ | |
255 | ||
256 | ret = spi_sync(devrec->spi, &msg); | |
257 | if (ret) | |
258 | dev_err(printdev(devrec), "SPI write Failed for TX buf\n"); | |
259 | ||
260 | mutex_unlock(&devrec->buffer_mutex); | |
261 | return ret; | |
262 | } | |
263 | ||
264 | static int mrf24j40_read_rx_buf(struct mrf24j40 *devrec, | |
265 | u8 *data, u8 *len, u8 *lqi) | |
266 | { | |
267 | u8 rx_len; | |
268 | u8 addr[2]; | |
269 | u8 lqi_rssi[2]; | |
270 | u16 cmd; | |
271 | int ret; | |
272 | struct spi_message msg; | |
273 | struct spi_transfer addr_xfer = { | |
274 | .len = 2, | |
275 | .tx_buf = &addr, | |
276 | }; | |
277 | struct spi_transfer data_xfer = { | |
278 | .len = 0x0, /* set below */ | |
279 | .rx_buf = data, | |
280 | }; | |
281 | struct spi_transfer status_xfer = { | |
282 | .len = 2, | |
283 | .rx_buf = &lqi_rssi, | |
284 | }; | |
285 | ||
286 | /* Get the length of the data in the RX FIFO. The length in this | |
287 | * register exclues the 1-byte length field at the beginning. */ | |
288 | ret = read_long_reg(devrec, REG_RX_FIFO, &rx_len); | |
289 | if (ret) | |
290 | goto out; | |
291 | ||
292 | /* Range check the RX FIFO length, accounting for the one-byte | |
293 | * length field at the begining. */ | |
294 | if (rx_len > RX_FIFO_SIZE-1) { | |
295 | dev_err(printdev(devrec), "Invalid length read from device. Performing short read.\n"); | |
296 | rx_len = RX_FIFO_SIZE-1; | |
297 | } | |
298 | ||
299 | if (rx_len > *len) { | |
300 | /* Passed in buffer wasn't big enough. Should never happen. */ | |
301 | dev_err(printdev(devrec), "Buffer not big enough. Performing short read\n"); | |
302 | rx_len = *len; | |
303 | } | |
304 | ||
305 | /* Set up the commands to read the data. */ | |
306 | cmd = MRF24J40_READLONG(REG_RX_FIFO+1); | |
307 | addr[0] = cmd >> 8 & 0xff; | |
308 | addr[1] = cmd & 0xff; | |
309 | data_xfer.len = rx_len; | |
310 | ||
311 | spi_message_init(&msg); | |
312 | spi_message_add_tail(&addr_xfer, &msg); | |
313 | spi_message_add_tail(&data_xfer, &msg); | |
314 | spi_message_add_tail(&status_xfer, &msg); | |
315 | ||
316 | ret = spi_sync(devrec->spi, &msg); | |
317 | if (ret) { | |
318 | dev_err(printdev(devrec), "SPI RX Buffer Read Failed.\n"); | |
319 | goto out; | |
320 | } | |
321 | ||
322 | *lqi = lqi_rssi[0]; | |
323 | *len = rx_len; | |
324 | ||
325 | #ifdef DEBUG | |
326 | print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ", | |
327 | DUMP_PREFIX_OFFSET, 16, 1, data, *len, 0); | |
328 | printk(KERN_DEBUG "mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n", | |
329 | lqi_rssi[0], lqi_rssi[1]); | |
330 | #endif | |
331 | ||
332 | out: | |
333 | return ret; | |
334 | } | |
335 | ||
336 | static int mrf24j40_tx(struct ieee802154_dev *dev, struct sk_buff *skb) | |
337 | { | |
338 | struct mrf24j40 *devrec = dev->priv; | |
339 | u8 val; | |
340 | int ret = 0; | |
341 | ||
342 | dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len); | |
343 | ||
344 | ret = write_tx_buf(devrec, 0x000, skb->data, skb->len); | |
345 | if (ret) | |
346 | goto err; | |
347 | ||
348 | /* Set TXNTRIG bit of TXNCON to send packet */ | |
349 | ret = read_short_reg(devrec, REG_TXNCON, &val); | |
350 | if (ret) | |
351 | goto err; | |
352 | val |= 0x1; | |
353 | val &= ~0x4; | |
354 | write_short_reg(devrec, REG_TXNCON, val); | |
355 | ||
356 | INIT_COMPLETION(devrec->tx_complete); | |
357 | ||
358 | /* Wait for the device to send the TX complete interrupt. */ | |
359 | ret = wait_for_completion_interruptible_timeout( | |
360 | &devrec->tx_complete, | |
361 | 5 * HZ); | |
362 | if (ret == -ERESTARTSYS) | |
363 | goto err; | |
364 | if (ret == 0) { | |
7a1c2318 | 365 | dev_warn(printdev(devrec), "Timeout waiting for TX interrupt\n"); |
3731a334 AO |
366 | ret = -ETIMEDOUT; |
367 | goto err; | |
368 | } | |
369 | ||
370 | /* Check for send error from the device. */ | |
371 | ret = read_short_reg(devrec, REG_TXSTAT, &val); | |
372 | if (ret) | |
373 | goto err; | |
374 | if (val & 0x1) { | |
375 | dev_err(printdev(devrec), "Error Sending. Retry count exceeded\n"); | |
376 | ret = -ECOMM; /* TODO: Better error code ? */ | |
377 | } else | |
378 | dev_dbg(printdev(devrec), "Packet Sent\n"); | |
379 | ||
380 | err: | |
381 | ||
382 | return ret; | |
383 | } | |
384 | ||
385 | static int mrf24j40_ed(struct ieee802154_dev *dev, u8 *level) | |
386 | { | |
387 | /* TODO: */ | |
388 | printk(KERN_WARNING "mrf24j40: ed not implemented\n"); | |
389 | *level = 0; | |
390 | return 0; | |
391 | } | |
392 | ||
393 | static int mrf24j40_start(struct ieee802154_dev *dev) | |
394 | { | |
395 | struct mrf24j40 *devrec = dev->priv; | |
396 | u8 val; | |
397 | int ret; | |
398 | ||
399 | dev_dbg(printdev(devrec), "start\n"); | |
400 | ||
401 | ret = read_short_reg(devrec, REG_INTCON, &val); | |
402 | if (ret) | |
403 | return ret; | |
404 | val &= ~(0x1|0x8); /* Clear TXNIE and RXIE. Enable interrupts */ | |
405 | write_short_reg(devrec, REG_INTCON, val); | |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
410 | static void mrf24j40_stop(struct ieee802154_dev *dev) | |
411 | { | |
412 | struct mrf24j40 *devrec = dev->priv; | |
413 | u8 val; | |
414 | int ret; | |
415 | dev_dbg(printdev(devrec), "stop\n"); | |
416 | ||
417 | ret = read_short_reg(devrec, REG_INTCON, &val); | |
418 | if (ret) | |
419 | return; | |
420 | val |= 0x1|0x8; /* Set TXNIE and RXIE. Disable Interrupts */ | |
421 | write_short_reg(devrec, REG_INTCON, val); | |
422 | ||
423 | return; | |
424 | } | |
425 | ||
426 | static int mrf24j40_set_channel(struct ieee802154_dev *dev, | |
427 | int page, int channel) | |
428 | { | |
429 | struct mrf24j40 *devrec = dev->priv; | |
430 | u8 val; | |
431 | int ret; | |
432 | ||
433 | dev_dbg(printdev(devrec), "Set Channel %d\n", channel); | |
434 | ||
435 | WARN_ON(page != 0); | |
436 | WARN_ON(channel < MRF24J40_CHAN_MIN); | |
437 | WARN_ON(channel > MRF24J40_CHAN_MAX); | |
438 | ||
439 | /* Set Channel TODO */ | |
440 | val = (channel-11) << 4 | 0x03; | |
441 | write_long_reg(devrec, REG_RFCON0, val); | |
442 | ||
443 | /* RF Reset */ | |
444 | ret = read_short_reg(devrec, REG_RFCTL, &val); | |
445 | if (ret) | |
446 | return ret; | |
447 | val |= 0x04; | |
448 | write_short_reg(devrec, REG_RFCTL, val); | |
449 | val &= ~0x04; | |
450 | write_short_reg(devrec, REG_RFCTL, val); | |
451 | ||
452 | udelay(SET_CHANNEL_DELAY_US); /* per datasheet */ | |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
457 | static int mrf24j40_filter(struct ieee802154_dev *dev, | |
458 | struct ieee802154_hw_addr_filt *filt, | |
459 | unsigned long changed) | |
460 | { | |
461 | struct mrf24j40 *devrec = dev->priv; | |
462 | ||
463 | dev_dbg(printdev(devrec), "filter\n"); | |
464 | ||
465 | if (changed & IEEE802515_AFILT_SADDR_CHANGED) { | |
466 | /* Short Addr */ | |
467 | u8 addrh, addrl; | |
468 | addrh = filt->short_addr >> 8 & 0xff; | |
469 | addrl = filt->short_addr & 0xff; | |
470 | ||
471 | write_short_reg(devrec, REG_SADRH, addrh); | |
472 | write_short_reg(devrec, REG_SADRL, addrl); | |
473 | dev_dbg(printdev(devrec), | |
474 | "Set short addr to %04hx\n", filt->short_addr); | |
475 | } | |
476 | ||
477 | if (changed & IEEE802515_AFILT_IEEEADDR_CHANGED) { | |
478 | /* Device Address */ | |
479 | int i; | |
480 | for (i = 0; i < 8; i++) | |
481 | write_short_reg(devrec, REG_EADR0+i, | |
482 | filt->ieee_addr[i]); | |
483 | ||
484 | #ifdef DEBUG | |
485 | printk(KERN_DEBUG "Set long addr to: "); | |
486 | for (i = 0; i < 8; i++) | |
487 | printk("%02hhx ", filt->ieee_addr[i]); | |
488 | printk(KERN_DEBUG "\n"); | |
489 | #endif | |
490 | } | |
491 | ||
492 | if (changed & IEEE802515_AFILT_PANID_CHANGED) { | |
493 | /* PAN ID */ | |
494 | u8 panidl, panidh; | |
495 | panidh = filt->pan_id >> 8 & 0xff; | |
496 | panidl = filt->pan_id & 0xff; | |
497 | write_short_reg(devrec, REG_PANIDH, panidh); | |
498 | write_short_reg(devrec, REG_PANIDL, panidl); | |
499 | ||
500 | dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id); | |
501 | } | |
502 | ||
503 | if (changed & IEEE802515_AFILT_PANC_CHANGED) { | |
504 | /* Pan Coordinator */ | |
505 | u8 val; | |
506 | int ret; | |
507 | ||
508 | ret = read_short_reg(devrec, REG_RXMCR, &val); | |
509 | if (ret) | |
510 | return ret; | |
511 | if (filt->pan_coord) | |
512 | val |= 0x8; | |
513 | else | |
514 | val &= ~0x8; | |
515 | write_short_reg(devrec, REG_RXMCR, val); | |
516 | ||
517 | /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA). | |
518 | * REG_ORDER is maintained as default (no beacon/superframe). | |
519 | */ | |
520 | ||
521 | dev_dbg(printdev(devrec), "Set Pan Coord to %s\n", | |
522 | filt->pan_coord ? "on" : "off"); | |
523 | } | |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
528 | static int mrf24j40_handle_rx(struct mrf24j40 *devrec) | |
529 | { | |
530 | u8 len = RX_FIFO_SIZE; | |
531 | u8 lqi = 0; | |
532 | u8 val; | |
533 | int ret = 0; | |
534 | struct sk_buff *skb; | |
535 | ||
536 | /* Turn off reception of packets off the air. This prevents the | |
537 | * device from overwriting the buffer while we're reading it. */ | |
538 | ret = read_short_reg(devrec, REG_BBREG1, &val); | |
539 | if (ret) | |
540 | goto out; | |
541 | val |= 4; /* SET RXDECINV */ | |
542 | write_short_reg(devrec, REG_BBREG1, val); | |
543 | ||
544 | skb = alloc_skb(len, GFP_KERNEL); | |
545 | if (!skb) { | |
546 | ret = -ENOMEM; | |
547 | goto out; | |
548 | } | |
549 | ||
550 | ret = mrf24j40_read_rx_buf(devrec, skb_put(skb, len), &len, &lqi); | |
551 | if (ret < 0) { | |
552 | dev_err(printdev(devrec), "Failure reading RX FIFO\n"); | |
553 | kfree_skb(skb); | |
554 | ret = -EINVAL; | |
555 | goto out; | |
556 | } | |
557 | ||
558 | /* Cut off the checksum */ | |
559 | skb_trim(skb, len-2); | |
560 | ||
561 | /* TODO: Other drivers call ieee20154_rx_irqsafe() here (eg: cc2040, | |
562 | * also from a workqueue). I think irqsafe is not necessary here. | |
563 | * Can someone confirm? */ | |
564 | ieee802154_rx_irqsafe(devrec->dev, skb, lqi); | |
565 | ||
566 | dev_dbg(printdev(devrec), "RX Handled\n"); | |
567 | ||
568 | out: | |
569 | /* Turn back on reception of packets off the air. */ | |
570 | ret = read_short_reg(devrec, REG_BBREG1, &val); | |
571 | if (ret) | |
572 | return ret; | |
573 | val &= ~0x4; /* Clear RXDECINV */ | |
574 | write_short_reg(devrec, REG_BBREG1, val); | |
575 | ||
576 | return ret; | |
577 | } | |
578 | ||
579 | static struct ieee802154_ops mrf24j40_ops = { | |
580 | .owner = THIS_MODULE, | |
581 | .xmit = mrf24j40_tx, | |
582 | .ed = mrf24j40_ed, | |
583 | .start = mrf24j40_start, | |
584 | .stop = mrf24j40_stop, | |
585 | .set_channel = mrf24j40_set_channel, | |
586 | .set_hw_addr_filt = mrf24j40_filter, | |
587 | }; | |
588 | ||
589 | static irqreturn_t mrf24j40_isr(int irq, void *data) | |
590 | { | |
591 | struct mrf24j40 *devrec = data; | |
592 | ||
593 | disable_irq_nosync(irq); | |
594 | ||
595 | schedule_work(&devrec->irqwork); | |
596 | ||
597 | return IRQ_HANDLED; | |
598 | } | |
599 | ||
600 | static void mrf24j40_isrwork(struct work_struct *work) | |
601 | { | |
602 | struct mrf24j40 *devrec = container_of(work, struct mrf24j40, irqwork); | |
603 | u8 intstat; | |
604 | int ret; | |
605 | ||
606 | /* Read the interrupt status */ | |
607 | ret = read_short_reg(devrec, REG_INTSTAT, &intstat); | |
608 | if (ret) | |
609 | goto out; | |
610 | ||
611 | /* Check for TX complete */ | |
612 | if (intstat & 0x1) | |
613 | complete(&devrec->tx_complete); | |
614 | ||
615 | /* Check for Rx */ | |
616 | if (intstat & 0x8) | |
617 | mrf24j40_handle_rx(devrec); | |
618 | ||
619 | out: | |
620 | enable_irq(devrec->spi->irq); | |
621 | } | |
622 | ||
bb1f4606 | 623 | static int mrf24j40_probe(struct spi_device *spi) |
3731a334 AO |
624 | { |
625 | int ret = -ENOMEM; | |
626 | u8 val; | |
627 | struct mrf24j40 *devrec; | |
50861c7e | 628 | struct pinctrl *pinctrl; |
3731a334 AO |
629 | |
630 | printk(KERN_INFO "mrf24j40: probe(). IRQ: %d\n", spi->irq); | |
631 | ||
632 | devrec = kzalloc(sizeof(struct mrf24j40), GFP_KERNEL); | |
633 | if (!devrec) | |
634 | goto err_devrec; | |
635 | devrec->buf = kzalloc(3, GFP_KERNEL); | |
636 | if (!devrec->buf) | |
637 | goto err_buf; | |
638 | ||
50861c7e AO |
639 | pinctrl = devm_pinctrl_get_select_default(&spi->dev); |
640 | if (IS_ERR(pinctrl)) | |
641 | dev_warn(&spi->dev, | |
642 | "pinctrl pins are not configured from the driver"); | |
643 | ||
3731a334 AO |
644 | spi->mode = SPI_MODE_0; /* TODO: Is this appropriate for right here? */ |
645 | if (spi->max_speed_hz > MAX_SPI_SPEED_HZ) | |
646 | spi->max_speed_hz = MAX_SPI_SPEED_HZ; | |
647 | ||
648 | mutex_init(&devrec->buffer_mutex); | |
649 | init_completion(&devrec->tx_complete); | |
650 | INIT_WORK(&devrec->irqwork, mrf24j40_isrwork); | |
651 | devrec->spi = spi; | |
652 | dev_set_drvdata(&spi->dev, devrec); | |
653 | ||
654 | /* Register with the 802154 subsystem */ | |
655 | ||
656 | devrec->dev = ieee802154_alloc_device(0, &mrf24j40_ops); | |
657 | if (!devrec->dev) | |
658 | goto err_alloc_dev; | |
659 | ||
660 | devrec->dev->priv = devrec; | |
661 | devrec->dev->parent = &devrec->spi->dev; | |
662 | devrec->dev->phy->channels_supported[0] = CHANNEL_MASK; | |
663 | devrec->dev->flags = IEEE802154_HW_OMIT_CKSUM|IEEE802154_HW_AACK; | |
664 | ||
665 | dev_dbg(printdev(devrec), "registered mrf24j40\n"); | |
666 | ret = ieee802154_register_device(devrec->dev); | |
667 | if (ret) | |
668 | goto err_register_device; | |
669 | ||
670 | /* Initialize the device. | |
671 | From datasheet section 3.2: Initialization. */ | |
672 | write_short_reg(devrec, REG_SOFTRST, 0x07); | |
673 | write_short_reg(devrec, REG_PACON2, 0x98); | |
674 | write_short_reg(devrec, REG_TXSTBL, 0x95); | |
675 | write_long_reg(devrec, REG_RFCON0, 0x03); | |
676 | write_long_reg(devrec, REG_RFCON1, 0x01); | |
677 | write_long_reg(devrec, REG_RFCON2, 0x80); | |
678 | write_long_reg(devrec, REG_RFCON6, 0x90); | |
679 | write_long_reg(devrec, REG_RFCON7, 0x80); | |
680 | write_long_reg(devrec, REG_RFCON8, 0x10); | |
681 | write_long_reg(devrec, REG_SLPCON1, 0x21); | |
682 | write_short_reg(devrec, REG_BBREG2, 0x80); | |
683 | write_short_reg(devrec, REG_CCAEDTH, 0x60); | |
684 | write_short_reg(devrec, REG_BBREG6, 0x40); | |
685 | write_short_reg(devrec, REG_RFCTL, 0x04); | |
686 | write_short_reg(devrec, REG_RFCTL, 0x0); | |
687 | udelay(192); | |
688 | ||
689 | /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */ | |
690 | ret = read_short_reg(devrec, REG_RXMCR, &val); | |
691 | if (ret) | |
692 | goto err_read_reg; | |
693 | val &= ~0x3; /* Clear RX mode (normal) */ | |
694 | write_short_reg(devrec, REG_RXMCR, val); | |
695 | ||
696 | ret = request_irq(spi->irq, | |
697 | mrf24j40_isr, | |
698 | IRQF_TRIGGER_FALLING, | |
699 | dev_name(&spi->dev), | |
700 | devrec); | |
701 | ||
702 | if (ret) { | |
703 | dev_err(printdev(devrec), "Unable to get IRQ"); | |
704 | goto err_irq; | |
705 | } | |
706 | ||
707 | return 0; | |
708 | ||
709 | err_irq: | |
710 | err_read_reg: | |
711 | ieee802154_unregister_device(devrec->dev); | |
712 | err_register_device: | |
713 | ieee802154_free_device(devrec->dev); | |
714 | err_alloc_dev: | |
715 | kfree(devrec->buf); | |
716 | err_buf: | |
717 | kfree(devrec); | |
718 | err_devrec: | |
719 | return ret; | |
720 | } | |
721 | ||
bb1f4606 | 722 | static int mrf24j40_remove(struct spi_device *spi) |
3731a334 AO |
723 | { |
724 | struct mrf24j40 *devrec = dev_get_drvdata(&spi->dev); | |
725 | ||
726 | dev_dbg(printdev(devrec), "remove\n"); | |
727 | ||
728 | free_irq(spi->irq, devrec); | |
916082b0 | 729 | flush_work(&devrec->irqwork); /* TODO: Is this the right call? */ |
3731a334 AO |
730 | ieee802154_unregister_device(devrec->dev); |
731 | ieee802154_free_device(devrec->dev); | |
732 | /* TODO: Will ieee802154_free_device() wait until ->xmit() is | |
733 | * complete? */ | |
734 | ||
735 | /* Clean up the SPI stuff. */ | |
736 | dev_set_drvdata(&spi->dev, NULL); | |
737 | kfree(devrec->buf); | |
738 | kfree(devrec); | |
739 | return 0; | |
740 | } | |
741 | ||
742 | static const struct spi_device_id mrf24j40_ids[] = { | |
743 | { "mrf24j40", 0 }, | |
744 | { "mrf24j40ma", 0 }, | |
745 | { }, | |
746 | }; | |
747 | MODULE_DEVICE_TABLE(spi, mrf24j40_ids); | |
748 | ||
749 | static struct spi_driver mrf24j40_driver = { | |
750 | .driver = { | |
751 | .name = "mrf24j40", | |
752 | .bus = &spi_bus_type, | |
753 | .owner = THIS_MODULE, | |
754 | }, | |
755 | .id_table = mrf24j40_ids, | |
756 | .probe = mrf24j40_probe, | |
bb1f4606 | 757 | .remove = mrf24j40_remove, |
3731a334 AO |
758 | }; |
759 | ||
760 | static int __init mrf24j40_init(void) | |
761 | { | |
762 | return spi_register_driver(&mrf24j40_driver); | |
763 | } | |
764 | ||
765 | static void __exit mrf24j40_exit(void) | |
766 | { | |
767 | spi_unregister_driver(&mrf24j40_driver); | |
768 | } | |
769 | ||
770 | module_init(mrf24j40_init); | |
771 | module_exit(mrf24j40_exit); | |
772 | ||
773 | MODULE_LICENSE("GPL"); | |
774 | MODULE_AUTHOR("Alan Ott"); | |
775 | MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver"); |