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mac802154: move wpan.c to iface.c
[linux-2.6-block.git] / drivers / net / ieee802154 / mrf24j40.c
CommitLineData
3731a334
AO		 1/*
2 * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
3 *
4 * Copyright (C) 2012 Alan Ott <alan@signal11.us>
5 * Signal 11 Software
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
3731a334
AO		 16 */
17
18#include <linux/spi/spi.h>
19#include <linux/interrupt.h>
20#include <linux/module.h>
21#include <net/wpan-phy.h>
22#include <net/mac802154.h>
cbde8123 23#include <net/ieee802154.h>
3731a334
AO		 24
25/* MRF24J40 Short Address Registers */
26#define REG_RXMCR 0x00 /* Receive MAC control */
27#define REG_PANIDL 0x01 /* PAN ID (low) */
28#define REG_PANIDH 0x02 /* PAN ID (high) */
29#define REG_SADRL 0x03 /* Short address (low) */
30#define REG_SADRH 0x04 /* Short address (high) */
31#define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */
32#define REG_TXMCR 0x11 /* Transmit MAC control */
33#define REG_PACON0 0x16 /* Power Amplifier Control */
34#define REG_PACON1 0x17 /* Power Amplifier Control */
35#define REG_PACON2 0x18 /* Power Amplifier Control */
36#define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
37#define REG_TXSTAT 0x24 /* TX MAC Status Register */
38#define REG_SOFTRST 0x2A /* Soft Reset */
39#define REG_TXSTBL 0x2E /* TX Stabilization */
40#define REG_INTSTAT 0x31 /* Interrupt Status */
41#define REG_INTCON 0x32 /* Interrupt Control */
db9e0ee8
SV		 42#define REG_GPIO 0x33 /* GPIO */
43#define REG_TRISGPIO 0x34 /* GPIO direction */
3731a334
AO		 44#define REG_RFCTL 0x36 /* RF Control Mode Register */
45#define REG_BBREG1 0x39 /* Baseband Registers */
46#define REG_BBREG2 0x3A /* */
47#define REG_BBREG6 0x3E /* */
48#define REG_CCAEDTH 0x3F /* Energy Detection Threshold */
49
50/* MRF24J40 Long Address Registers */
51#define REG_RFCON0 0x200 /* RF Control Registers */
52#define REG_RFCON1 0x201
53#define REG_RFCON2 0x202
54#define REG_RFCON3 0x203
55#define REG_RFCON5 0x205
56#define REG_RFCON6 0x206
57#define REG_RFCON7 0x207
58#define REG_RFCON8 0x208
59#define REG_RSSI 0x210
60#define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */
61#define REG_SLPCON1 0x220
62#define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
63#define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
db9e0ee8 64#define REG_TESTMODE 0x22F /* Test mode */
3731a334
AO		 65#define REG_RX_FIFO 0x300 /* Receive FIFO */
66
67/* Device configuration: Only channels 11-26 on page 0 are supported. */
68#define MRF24J40_CHAN_MIN 11
69#define MRF24J40_CHAN_MAX 26
70#define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
71 - ((u32)1 << MRF24J40_CHAN_MIN))
72
73#define TX_FIFO_SIZE 128 /* From datasheet */
74#define RX_FIFO_SIZE 144 /* From datasheet */
75#define SET_CHANNEL_DELAY_US 192 /* From datasheet */
76
db9e0ee8
SV		 77enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC };
78
3731a334
AO		 79/* Device Private Data */
80struct mrf24j40 {
81 struct spi_device *spi;
82 struct ieee802154_dev *dev;
83
84 struct mutex buffer_mutex; /* only used to protect buf */
85 struct completion tx_complete;
3731a334
AO		 86 u8 *buf; /* 3 bytes. Used for SPI single-register transfers. */
87};
88
89/* Read/Write SPI Commands for Short and Long Address registers. */
90#define MRF24J40_READSHORT(reg) ((reg) << 1)
91#define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
92#define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
93#define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
94
cf82dabd
AO		 95/* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
96#define MAX_SPI_SPEED_HZ 10000000
3731a334
AO		 97
98#define printdev(X) (&X->spi->dev)
99
100static int write_short_reg(struct mrf24j40 *devrec, u8 reg, u8 value)
101{
102 int ret;
103 struct spi_message msg;
104 struct spi_transfer xfer = {
105 .len = 2,
106 .tx_buf = devrec->buf,
107 .rx_buf = devrec->buf,
108 };
109
110 spi_message_init(&msg);
111 spi_message_add_tail(&xfer, &msg);
112
113 mutex_lock(&devrec->buffer_mutex);
114 devrec->buf[0] = MRF24J40_WRITESHORT(reg);
115 devrec->buf[1] = value;
116
117 ret = spi_sync(devrec->spi, &msg);
118 if (ret)
119 dev_err(printdev(devrec),
120 "SPI write Failed for short register 0x%hhx\n", reg);
121
122 mutex_unlock(&devrec->buffer_mutex);
123 return ret;
124}
125
126static int read_short_reg(struct mrf24j40 *devrec, u8 reg, u8 *val)
127{
128 int ret = -1;
129 struct spi_message msg;
130 struct spi_transfer xfer = {
131 .len = 2,
132 .tx_buf = devrec->buf,
133 .rx_buf = devrec->buf,
134 };
135
136 spi_message_init(&msg);
137 spi_message_add_tail(&xfer, &msg);
138
139 mutex_lock(&devrec->buffer_mutex);
140 devrec->buf[0] = MRF24J40_READSHORT(reg);
141 devrec->buf[1] = 0;
142
143 ret = spi_sync(devrec->spi, &msg);
144 if (ret)
145 dev_err(printdev(devrec),
146 "SPI read Failed for short register 0x%hhx\n", reg);
147 else
148 *val = devrec->buf[1];
149
150 mutex_unlock(&devrec->buffer_mutex);
151 return ret;
152}
153
154static int read_long_reg(struct mrf24j40 *devrec, u16 reg, u8 *value)
155{
156 int ret;
157 u16 cmd;
158 struct spi_message msg;
159 struct spi_transfer xfer = {
160 .len = 3,
161 .tx_buf = devrec->buf,
162 .rx_buf = devrec->buf,
163 };
164
165 spi_message_init(&msg);
166 spi_message_add_tail(&xfer, &msg);
167
168 cmd = MRF24J40_READLONG(reg);
169 mutex_lock(&devrec->buffer_mutex);
170 devrec->buf[0] = cmd >> 8 & 0xff;
171 devrec->buf[1] = cmd & 0xff;
172 devrec->buf[2] = 0;
173
174 ret = spi_sync(devrec->spi, &msg);
175 if (ret)
176 dev_err(printdev(devrec),
177 "SPI read Failed for long register 0x%hx\n", reg);
178 else
179 *value = devrec->buf[2];
180
181 mutex_unlock(&devrec->buffer_mutex);
182 return ret;
183}
184
185static int write_long_reg(struct mrf24j40 *devrec, u16 reg, u8 val)
186{
187 int ret;
188 u16 cmd;
189 struct spi_message msg;
190 struct spi_transfer xfer = {
191 .len = 3,
192 .tx_buf = devrec->buf,
193 .rx_buf = devrec->buf,
194 };
195
196 spi_message_init(&msg);
197 spi_message_add_tail(&xfer, &msg);
198
199 cmd = MRF24J40_WRITELONG(reg);
200 mutex_lock(&devrec->buffer_mutex);
201 devrec->buf[0] = cmd >> 8 & 0xff;
202 devrec->buf[1] = cmd & 0xff;
203 devrec->buf[2] = val;
204
205 ret = spi_sync(devrec->spi, &msg);
206 if (ret)
207 dev_err(printdev(devrec),
208 "SPI write Failed for long register 0x%hx\n", reg);
209
210 mutex_unlock(&devrec->buffer_mutex);
211 return ret;
212}
213
214/* This function relies on an undocumented write method. Once a write command
215 and address is set, as many bytes of data as desired can be clocked into
216 the device. The datasheet only shows setting one byte at a time. */
217static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
218 const u8 *data, size_t length)
219{
220 int ret;
221 u16 cmd;
222 u8 lengths[2];
223 struct spi_message msg;
224 struct spi_transfer addr_xfer = {
225 .len = 2,
226 .tx_buf = devrec->buf,
227 };
228 struct spi_transfer lengths_xfer = {
229 .len = 2,
230 .tx_buf = &lengths, /* TODO: Is DMA really required for SPI? */
231 };
232 struct spi_transfer data_xfer = {
233 .len = length,
234 .tx_buf = data,
235 };
236
237 /* Range check the length. 2 bytes are used for the length fields.*/
238 if (length > TX_FIFO_SIZE-2) {
239 dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
240 length = TX_FIFO_SIZE-2;
241 }
242
243 spi_message_init(&msg);
244 spi_message_add_tail(&addr_xfer, &msg);
245 spi_message_add_tail(&lengths_xfer, &msg);
246 spi_message_add_tail(&data_xfer, &msg);
247
248 cmd = MRF24J40_WRITELONG(reg);
249 mutex_lock(&devrec->buffer_mutex);
250 devrec->buf[0] = cmd >> 8 & 0xff;
251 devrec->buf[1] = cmd & 0xff;
252 lengths[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
253 lengths[1] = length; /* Total length */
254
255 ret = spi_sync(devrec->spi, &msg);
256 if (ret)
257 dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
258
259 mutex_unlock(&devrec->buffer_mutex);
260 return ret;
261}
262
263static int mrf24j40_read_rx_buf(struct mrf24j40 *devrec,
264 u8 *data, u8 *len, u8 *lqi)
265{
266 u8 rx_len;
267 u8 addr[2];
268 u8 lqi_rssi[2];
269 u16 cmd;
270 int ret;
271 struct spi_message msg;
272 struct spi_transfer addr_xfer = {
273 .len = 2,
274 .tx_buf = &addr,
275 };
276 struct spi_transfer data_xfer = {
277 .len = 0x0, /* set below */
278 .rx_buf = data,
279 };
280 struct spi_transfer status_xfer = {
281 .len = 2,
282 .rx_buf = &lqi_rssi,
283 };
284
285 /* Get the length of the data in the RX FIFO. The length in this
286 * register exclues the 1-byte length field at the beginning. */
287 ret = read_long_reg(devrec, REG_RX_FIFO, &rx_len);
288 if (ret)
289 goto out;
290
291 /* Range check the RX FIFO length, accounting for the one-byte
292 * length field at the begining. */
293 if (rx_len > RX_FIFO_SIZE-1) {
294 dev_err(printdev(devrec), "Invalid length read from device. Performing short read.\n");
295 rx_len = RX_FIFO_SIZE-1;
296 }
297
298 if (rx_len > *len) {
299 /* Passed in buffer wasn't big enough. Should never happen. */
300 dev_err(printdev(devrec), "Buffer not big enough. Performing short read\n");
301 rx_len = *len;
302 }
303
304 /* Set up the commands to read the data. */
305 cmd = MRF24J40_READLONG(REG_RX_FIFO+1);
306 addr[0] = cmd >> 8 & 0xff;
307 addr[1] = cmd & 0xff;
308 data_xfer.len = rx_len;
309
310 spi_message_init(&msg);
311 spi_message_add_tail(&addr_xfer, &msg);
312 spi_message_add_tail(&data_xfer, &msg);
313 spi_message_add_tail(&status_xfer, &msg);
314
315 ret = spi_sync(devrec->spi, &msg);
316 if (ret) {
317 dev_err(printdev(devrec), "SPI RX Buffer Read Failed.\n");
318 goto out;
319 }
320
321 *lqi = lqi_rssi[0];
322 *len = rx_len;
323
324#ifdef DEBUG
325 print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ",
326 DUMP_PREFIX_OFFSET, 16, 1, data, *len, 0);
ca079ad6
VB		 327 pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
328 lqi_rssi[0], lqi_rssi[1]);
3731a334
AO		 329#endif
330
331out:
332 return ret;
333}
334
335static int mrf24j40_tx(struct ieee802154_dev *dev, struct sk_buff *skb)
336{
337 struct mrf24j40 *devrec = dev->priv;
338 u8 val;
339 int ret = 0;
340
341 dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
342
343 ret = write_tx_buf(devrec, 0x000, skb->data, skb->len);
344 if (ret)
345 goto err;
346
16735d02 347 reinit_completion(&devrec->tx_complete);
9757f1d2 348
3731a334
AO		 349 /* Set TXNTRIG bit of TXNCON to send packet */
350 ret = read_short_reg(devrec, REG_TXNCON, &val);
351 if (ret)
352 goto err;
353 val |= 0x1;
cbde8123
AO		 354 /* Set TXNACKREQ if the ACK bit is set in the packet. */
355 if (skb->data[0] & IEEE802154_FC_ACK_REQ)
356 val |= 0x4;
3731a334
AO		 357 write_short_reg(devrec, REG_TXNCON, val);
358
3731a334
AO		 359 /* Wait for the device to send the TX complete interrupt. */
360 ret = wait_for_completion_interruptible_timeout(
361 &devrec->tx_complete,
362 5 * HZ);
363 if (ret == -ERESTARTSYS)
364 goto err;
365 if (ret == 0) {
7a1c2318 366 dev_warn(printdev(devrec), "Timeout waiting for TX interrupt\n");
3731a334
AO		 367 ret = -ETIMEDOUT;
368 goto err;
369 }
370
371 /* Check for send error from the device. */
372 ret = read_short_reg(devrec, REG_TXSTAT, &val);
373 if (ret)
374 goto err;
375 if (val & 0x1) {
cbde8123 376 dev_dbg(printdev(devrec), "Error Sending. Retry count exceeded\n");
3731a334
AO		 377 ret = -ECOMM; /* TODO: Better error code ? */
378 } else
379 dev_dbg(printdev(devrec), "Packet Sent\n");
380
381err:
382
383 return ret;
384}
385
386static int mrf24j40_ed(struct ieee802154_dev *dev, u8 *level)
387{
388 /* TODO: */
ca079ad6 389 pr_warn("mrf24j40: ed not implemented\n");
3731a334
AO		 390 *level = 0;
391 return 0;
392}
393
394static int mrf24j40_start(struct ieee802154_dev *dev)
395{
396 struct mrf24j40 *devrec = dev->priv;
397 u8 val;
398 int ret;
399
400 dev_dbg(printdev(devrec), "start\n");
401
402 ret = read_short_reg(devrec, REG_INTCON, &val);
403 if (ret)
404 return ret;
405 val &= ~(0x1|0x8); /* Clear TXNIE and RXIE. Enable interrupts */
406 write_short_reg(devrec, REG_INTCON, val);
407
408 return 0;
409}
410
411static void mrf24j40_stop(struct ieee802154_dev *dev)
412{
413 struct mrf24j40 *devrec = dev->priv;
414 u8 val;
415 int ret;
529160dc 416
3731a334
AO		 417 dev_dbg(printdev(devrec), "stop\n");
418
419 ret = read_short_reg(devrec, REG_INTCON, &val);
420 if (ret)
421 return;
422 val |= 0x1|0x8; /* Set TXNIE and RXIE. Disable Interrupts */
423 write_short_reg(devrec, REG_INTCON, val);
3731a334
AO		 424}
425
426static int mrf24j40_set_channel(struct ieee802154_dev *dev,
427 int page, int channel)
428{
429 struct mrf24j40 *devrec = dev->priv;
430 u8 val;
431 int ret;
432
433 dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
434
435 WARN_ON(page != 0);
436 WARN_ON(channel < MRF24J40_CHAN_MIN);
437 WARN_ON(channel > MRF24J40_CHAN_MAX);
438
439 /* Set Channel TODO */
440 val = (channel-11) << 4 | 0x03;
441 write_long_reg(devrec, REG_RFCON0, val);
442
443 /* RF Reset */
444 ret = read_short_reg(devrec, REG_RFCTL, &val);
445 if (ret)
446 return ret;
447 val |= 0x04;
448 write_short_reg(devrec, REG_RFCTL, val);
449 val &= ~0x04;
450 write_short_reg(devrec, REG_RFCTL, val);
451
452 udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
453
454 return 0;
455}
456
457static int mrf24j40_filter(struct ieee802154_dev *dev,
458 struct ieee802154_hw_addr_filt *filt,
459 unsigned long changed)
460{
461 struct mrf24j40 *devrec = dev->priv;
462
463 dev_dbg(printdev(devrec), "filter\n");
464
57205c14 465 if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
3731a334
AO		 466 /* Short Addr */
467 u8 addrh, addrl;
529160dc 468
b70ab2e8
PB		 469 addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff;
470 addrl = le16_to_cpu(filt->short_addr) & 0xff;
3731a334
AO		 471
472 write_short_reg(devrec, REG_SADRH, addrh);
473 write_short_reg(devrec, REG_SADRL, addrl);
474 dev_dbg(printdev(devrec),
475 "Set short addr to %04hx\n", filt->short_addr);
476 }
477
57205c14 478 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
3731a334 479 /* Device Address */
b70ab2e8
PB		 480 u8 i, addr[8];
481
482 memcpy(addr, &filt->ieee_addr, 8);
3731a334 483 for (i = 0; i < 8; i++)
b70ab2e8 484 write_short_reg(devrec, REG_EADR0 + i, addr[i]);
3731a334
AO		 485
486#ifdef DEBUG
ca079ad6 487 pr_debug("Set long addr to: ");
3731a334 488 for (i = 0; i < 8; i++)
ca079ad6
VB		 489 pr_debug("%02hhx ", addr[7 - i]);
490 pr_debug("\n");
3731a334
AO		 491#endif
492 }
493
57205c14 494 if (changed & IEEE802154_AFILT_PANID_CHANGED) {
3731a334
AO		 495 /* PAN ID */
496 u8 panidl, panidh;
529160dc 497
b70ab2e8
PB		 498 panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff;
499 panidl = le16_to_cpu(filt->pan_id) & 0xff;
3731a334
AO		 500 write_short_reg(devrec, REG_PANIDH, panidh);
501 write_short_reg(devrec, REG_PANIDL, panidl);
502
503 dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
504 }
505
57205c14 506 if (changed & IEEE802154_AFILT_PANC_CHANGED) {
3731a334
AO		 507 /* Pan Coordinator */
508 u8 val;
509 int ret;
510
511 ret = read_short_reg(devrec, REG_RXMCR, &val);
512 if (ret)
513 return ret;
514 if (filt->pan_coord)
515 val |= 0x8;
516 else
517 val &= ~0x8;
518 write_short_reg(devrec, REG_RXMCR, val);
519
520 /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
521 * REG_ORDER is maintained as default (no beacon/superframe).
522 */
523
524 dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
525 filt->pan_coord ? "on" : "off");
526 }
527
528 return 0;
529}
530
531static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
532{
533 u8 len = RX_FIFO_SIZE;
534 u8 lqi = 0;
535 u8 val;
536 int ret = 0;
537 struct sk_buff *skb;
538
539 /* Turn off reception of packets off the air. This prevents the
540 * device from overwriting the buffer while we're reading it. */
541 ret = read_short_reg(devrec, REG_BBREG1, &val);
542 if (ret)
543 goto out;
544 val |= 4; /* SET RXDECINV */
545 write_short_reg(devrec, REG_BBREG1, val);
546
547 skb = alloc_skb(len, GFP_KERNEL);
548 if (!skb) {
549 ret = -ENOMEM;
550 goto out;
551 }
552
553 ret = mrf24j40_read_rx_buf(devrec, skb_put(skb, len), &len, &lqi);
554 if (ret < 0) {
555 dev_err(printdev(devrec), "Failure reading RX FIFO\n");
556 kfree_skb(skb);
557 ret = -EINVAL;
558 goto out;
559 }
560
561 /* Cut off the checksum */
562 skb_trim(skb, len-2);
563
564 /* TODO: Other drivers call ieee20154_rx_irqsafe() here (eg: cc2040,
565 * also from a workqueue). I think irqsafe is not necessary here.
566 * Can someone confirm? */
567 ieee802154_rx_irqsafe(devrec->dev, skb, lqi);
568
569 dev_dbg(printdev(devrec), "RX Handled\n");
570
571out:
572 /* Turn back on reception of packets off the air. */
573 ret = read_short_reg(devrec, REG_BBREG1, &val);
574 if (ret)
575 return ret;
576 val &= ~0x4; /* Clear RXDECINV */
577 write_short_reg(devrec, REG_BBREG1, val);
578
579 return ret;
580}
581
582static struct ieee802154_ops mrf24j40_ops = {
583 .owner = THIS_MODULE,
584 .xmit = mrf24j40_tx,
585 .ed = mrf24j40_ed,
586 .start = mrf24j40_start,
587 .stop = mrf24j40_stop,
588 .set_channel = mrf24j40_set_channel,
589 .set_hw_addr_filt = mrf24j40_filter,
590};
591
592static irqreturn_t mrf24j40_isr(int irq, void *data)
593{
594 struct mrf24j40 *devrec = data;
3731a334
AO		 595 u8 intstat;
596 int ret;
597
598 /* Read the interrupt status */
599 ret = read_short_reg(devrec, REG_INTSTAT, &intstat);
600 if (ret)
601 goto out;
602
603 /* Check for TX complete */
604 if (intstat & 0x1)
605 complete(&devrec->tx_complete);
606
607 /* Check for Rx */
608 if (intstat & 0x8)
609 mrf24j40_handle_rx(devrec);
610
611out:
4a4e1da8 612 return IRQ_HANDLED;
3731a334
AO		 613}
614
3dac9a79
VB		 615static int mrf24j40_hw_init(struct mrf24j40 *devrec)
616{
617 int ret;
618 u8 val;
619
620 /* Initialize the device.
621 From datasheet section 3.2: Initialization. */
622 ret = write_short_reg(devrec, REG_SOFTRST, 0x07);
623 if (ret)
624 goto err_ret;
625
626 ret = write_short_reg(devrec, REG_PACON2, 0x98);
627 if (ret)
628 goto err_ret;
629
630 ret = write_short_reg(devrec, REG_TXSTBL, 0x95);
631 if (ret)
632 goto err_ret;
633
634 ret = write_long_reg(devrec, REG_RFCON0, 0x03);
635 if (ret)
636 goto err_ret;
637
638 ret = write_long_reg(devrec, REG_RFCON1, 0x01);
639 if (ret)
640 goto err_ret;
641
642 ret = write_long_reg(devrec, REG_RFCON2, 0x80);
643 if (ret)
644 goto err_ret;
645
646 ret = write_long_reg(devrec, REG_RFCON6, 0x90);
647 if (ret)
648 goto err_ret;
649
650 ret = write_long_reg(devrec, REG_RFCON7, 0x80);
651 if (ret)
652 goto err_ret;
653
654 ret = write_long_reg(devrec, REG_RFCON8, 0x10);
655 if (ret)
656 goto err_ret;
657
658 ret = write_long_reg(devrec, REG_SLPCON1, 0x21);
659 if (ret)
660 goto err_ret;
661
662 ret = write_short_reg(devrec, REG_BBREG2, 0x80);
663 if (ret)
664 goto err_ret;
665
666 ret = write_short_reg(devrec, REG_CCAEDTH, 0x60);
667 if (ret)
668 goto err_ret;
669
670 ret = write_short_reg(devrec, REG_BBREG6, 0x40);
671 if (ret)
672 goto err_ret;
673
674 ret = write_short_reg(devrec, REG_RFCTL, 0x04);
675 if (ret)
676 goto err_ret;
677
678 ret = write_short_reg(devrec, REG_RFCTL, 0x0);
679 if (ret)
680 goto err_ret;
681
682 udelay(192);
683
684 /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
685 ret = read_short_reg(devrec, REG_RXMCR, &val);
686 if (ret)
687 goto err_ret;
688
689 val &= ~0x3; /* Clear RX mode (normal) */
690
691 ret = write_short_reg(devrec, REG_RXMCR, val);
692 if (ret)
693 goto err_ret;
694
db9e0ee8
SV		 695 if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) {
696 /* Enable external amplifier.
697 * From MRF24J40MC datasheet section 1.3: Operation.
698 */
699 read_long_reg(devrec, REG_TESTMODE, &val);
700 val |= 0x7; /* Configure GPIO 0-2 to control amplifier */
701 write_long_reg(devrec, REG_TESTMODE, val);
702
703 read_short_reg(devrec, REG_TRISGPIO, &val);
704 val |= 0x8; /* Set GPIO3 as output. */
705 write_short_reg(devrec, REG_TRISGPIO, val);
706
707 read_short_reg(devrec, REG_GPIO, &val);
708 val |= 0x8; /* Set GPIO3 HIGH to enable U5 voltage regulator */
709 write_short_reg(devrec, REG_GPIO, val);
710
711 /* Reduce TX pwr to meet FCC requirements.
712 * From MRF24J40MC datasheet section 3.1.1
713 */
714 write_long_reg(devrec, REG_RFCON3, 0x28);
715 }
716
3dac9a79
VB		 717 return 0;
718
719err_ret:
720 return ret;
721}
722
bb1f4606 723static int mrf24j40_probe(struct spi_device *spi)
3731a334
AO		 724{
725 int ret = -ENOMEM;
3731a334
AO		 726 struct mrf24j40 *devrec;
727
ca079ad6 728 dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq);
3731a334 729
0aaf43f5 730 devrec = devm_kzalloc(&spi->dev, sizeof(struct mrf24j40), GFP_KERNEL);
3731a334 731 if (!devrec)
0aaf43f5
VB		 732 goto err_ret;
733 devrec->buf = devm_kzalloc(&spi->dev, 3, GFP_KERNEL);
3731a334 734 if (!devrec->buf)
0aaf43f5 735 goto err_ret;
3731a334
AO		 736
737 spi->mode = SPI_MODE_0; /* TODO: Is this appropriate for right here? */
738 if (spi->max_speed_hz > MAX_SPI_SPEED_HZ)
739 spi->max_speed_hz = MAX_SPI_SPEED_HZ;
740
741 mutex_init(&devrec->buffer_mutex);
742 init_completion(&devrec->tx_complete);
3731a334 743 devrec->spi = spi;
4fa0a0ef 744 spi_set_drvdata(spi, devrec);
3731a334
AO		 745
746 /* Register with the 802154 subsystem */
747
748 devrec->dev = ieee802154_alloc_device(0, &mrf24j40_ops);
749 if (!devrec->dev)
0aaf43f5 750 goto err_ret;
3731a334
AO		 751
752 devrec->dev->priv = devrec;
753 devrec->dev->parent = &devrec->spi->dev;
754 devrec->dev->phy->channels_supported[0] = CHANNEL_MASK;
755 devrec->dev->flags = IEEE802154_HW_OMIT_CKSUM|IEEE802154_HW_AACK;
756
757 dev_dbg(printdev(devrec), "registered mrf24j40\n");
758 ret = ieee802154_register_device(devrec->dev);
759 if (ret)
760 goto err_register_device;
761
3dac9a79 762 ret = mrf24j40_hw_init(devrec);
3731a334 763 if (ret)
3dac9a79 764 goto err_hw_init;
3731a334 765
0aaf43f5
VB		 766 ret = devm_request_threaded_irq(&spi->dev,
767 spi->irq,
768 NULL,
769 mrf24j40_isr,
770 IRQF_TRIGGER_LOW|IRQF_ONESHOT,
771 dev_name(&spi->dev),
772 devrec);
3731a334
AO		 773
774 if (ret) {
775 dev_err(printdev(devrec), "Unable to get IRQ");
776 goto err_irq;
777 }
778
779 return 0;
780
781err_irq:
3dac9a79 782err_hw_init:
3731a334
AO		 783 ieee802154_unregister_device(devrec->dev);
784err_register_device:
785 ieee802154_free_device(devrec->dev);
0aaf43f5 786err_ret:
3731a334
AO		 787 return ret;
788}
789
bb1f4606 790static int mrf24j40_remove(struct spi_device *spi)
3731a334 791{
4fa0a0ef 792 struct mrf24j40 *devrec = spi_get_drvdata(spi);
3731a334
AO		 793
794 dev_dbg(printdev(devrec), "remove\n");
795
3731a334
AO		 796 ieee802154_unregister_device(devrec->dev);
797 ieee802154_free_device(devrec->dev);
798 /* TODO: Will ieee802154_free_device() wait until ->xmit() is
799 * complete? */
800
3731a334
AO		 801 return 0;
802}
803
804static const struct spi_device_id mrf24j40_ids[] = {
db9e0ee8
SV		 805 { "mrf24j40", MRF24J40 },
806 { "mrf24j40ma", MRF24J40MA },
807 { "mrf24j40mc", MRF24J40MC },
3731a334
AO		 808 { },
809};
810MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
811
812static struct spi_driver mrf24j40_driver = {
813 .driver = {
814 .name = "mrf24j40",
815 .bus = &spi_bus_type,
816 .owner = THIS_MODULE,
817 },
818 .id_table = mrf24j40_ids,
819 .probe = mrf24j40_probe,
bb1f4606 820 .remove = mrf24j40_remove,
3731a334
AO		 821};
822
3d4a1316 823module_spi_driver(mrf24j40_driver);
3731a334
AO		 824
825MODULE_LICENSE("GPL");
826MODULE_AUTHOR("Alan Ott");
827MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");
Linux 6.x block layer and io_uring tree(s)