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7b8e19b6 | 1 | /* |
2 | * AT86RF230/RF231 driver | |
3 | * | |
4 | * Copyright (C) 2009-2012 Siemens AG | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 | |
8 | * as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
7b8e19b6 | 15 | * Written by: |
16 | * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> | |
17 | * Alexander Smirnov <alex.bluesman.smirnov@gmail.com> | |
01ebd60b | 18 | * Alexander Aring <aar@pengutronix.de> |
7b8e19b6 | 19 | */ |
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/interrupt.h> | |
4af619ae | 23 | #include <linux/irq.h> |
7b8e19b6 | 24 | #include <linux/gpio.h> |
25 | #include <linux/delay.h> | |
7b8e19b6 | 26 | #include <linux/spinlock.h> |
27 | #include <linux/spi/spi.h> | |
28 | #include <linux/spi/at86rf230.h> | |
f76014f7 | 29 | #include <linux/regmap.h> |
7b8e19b6 | 30 | #include <linux/skbuff.h> |
fa2d3e94 | 31 | #include <linux/of_gpio.h> |
4ca24aca | 32 | #include <linux/ieee802154.h> |
7b8e19b6 | 33 | |
34 | #include <net/mac802154.h> | |
5ad60d36 | 35 | #include <net/cfg802154.h> |
7b8e19b6 | 36 | |
a53d1f7c AA |
37 | struct at86rf230_local; |
38 | /* at86rf2xx chip depend data. | |
39 | * All timings are in us. | |
40 | */ | |
41 | struct at86rf2xx_chip_data { | |
7a4ef918 | 42 | u16 t_sleep_cycle; |
984e0c68 | 43 | u16 t_channel_switch; |
09e536cd | 44 | u16 t_reset_to_off; |
2e0571c0 AA |
45 | u16 t_off_to_aack; |
46 | u16 t_off_to_tx_on; | |
1d15d6b5 AA |
47 | u16 t_frame; |
48 | u16 t_p_ack; | |
a53d1f7c AA |
49 | int rssi_base_val; |
50 | ||
e37d2ec8 | 51 | int (*set_channel)(struct at86rf230_local *, u8, u8); |
a7d7eda9 | 52 | int (*get_desense_steps)(struct at86rf230_local *, s32); |
a53d1f7c AA |
53 | }; |
54 | ||
ba6d2239 AA |
55 | #define AT86RF2XX_MAX_BUF (127 + 3) |
56 | /* tx retries to access the TX_ON state | |
57 | * if it's above then force change will be started. | |
58 | * | |
59 | * We assume the max_frame_retries (7) value of 802.15.4 here. | |
60 | */ | |
61 | #define AT86RF2XX_MAX_TX_RETRIES 7 | |
7b8e19b6 | 62 | |
1d15d6b5 AA |
63 | struct at86rf230_state_change { |
64 | struct at86rf230_local *lp; | |
cca990c8 | 65 | int irq; |
7b8e19b6 | 66 | |
1d15d6b5 AA |
67 | struct spi_message msg; |
68 | struct spi_transfer trx; | |
69 | u8 buf[AT86RF2XX_MAX_BUF]; | |
70 | ||
71 | void (*complete)(void *context); | |
72 | u8 from_state; | |
73 | u8 to_state; | |
97fed795 AA |
74 | |
75 | bool irq_enable; | |
1d15d6b5 AA |
76 | }; |
77 | ||
78 | struct at86rf230_local { | |
79 | struct spi_device *spi; | |
7b8e19b6 | 80 | |
5a504397 | 81 | struct ieee802154_hw *hw; |
1d15d6b5 | 82 | struct at86rf2xx_chip_data *data; |
f76014f7 | 83 | struct regmap *regmap; |
7b8e19b6 | 84 | |
2e0571c0 AA |
85 | struct completion state_complete; |
86 | struct at86rf230_state_change state; | |
87 | ||
1d15d6b5 | 88 | struct at86rf230_state_change irq; |
6ca00197 | 89 | |
a53d1f7c | 90 | bool tx_aret; |
850f43ac | 91 | s8 max_frame_retries; |
1d15d6b5 AA |
92 | bool is_tx; |
93 | /* spinlock for is_tx protection */ | |
94 | spinlock_t lock; | |
ba6d2239 | 95 | u8 tx_retry; |
1d15d6b5 AA |
96 | struct sk_buff *tx_skb; |
97 | struct at86rf230_state_change tx; | |
7b8e19b6 | 98 | }; |
99 | ||
100 | #define RG_TRX_STATUS (0x01) | |
101 | #define SR_TRX_STATUS 0x01, 0x1f, 0 | |
102 | #define SR_RESERVED_01_3 0x01, 0x20, 5 | |
103 | #define SR_CCA_STATUS 0x01, 0x40, 6 | |
104 | #define SR_CCA_DONE 0x01, 0x80, 7 | |
105 | #define RG_TRX_STATE (0x02) | |
106 | #define SR_TRX_CMD 0x02, 0x1f, 0 | |
107 | #define SR_TRAC_STATUS 0x02, 0xe0, 5 | |
108 | #define RG_TRX_CTRL_0 (0x03) | |
109 | #define SR_CLKM_CTRL 0x03, 0x07, 0 | |
110 | #define SR_CLKM_SHA_SEL 0x03, 0x08, 3 | |
111 | #define SR_PAD_IO_CLKM 0x03, 0x30, 4 | |
112 | #define SR_PAD_IO 0x03, 0xc0, 6 | |
113 | #define RG_TRX_CTRL_1 (0x04) | |
114 | #define SR_IRQ_POLARITY 0x04, 0x01, 0 | |
115 | #define SR_IRQ_MASK_MODE 0x04, 0x02, 1 | |
116 | #define SR_SPI_CMD_MODE 0x04, 0x0c, 2 | |
117 | #define SR_RX_BL_CTRL 0x04, 0x10, 4 | |
118 | #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5 | |
119 | #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6 | |
120 | #define SR_PA_EXT_EN 0x04, 0x80, 7 | |
121 | #define RG_PHY_TX_PWR (0x05) | |
122 | #define SR_TX_PWR 0x05, 0x0f, 0 | |
123 | #define SR_PA_LT 0x05, 0x30, 4 | |
124 | #define SR_PA_BUF_LT 0x05, 0xc0, 6 | |
125 | #define RG_PHY_RSSI (0x06) | |
126 | #define SR_RSSI 0x06, 0x1f, 0 | |
127 | #define SR_RND_VALUE 0x06, 0x60, 5 | |
128 | #define SR_RX_CRC_VALID 0x06, 0x80, 7 | |
129 | #define RG_PHY_ED_LEVEL (0x07) | |
130 | #define SR_ED_LEVEL 0x07, 0xff, 0 | |
131 | #define RG_PHY_CC_CCA (0x08) | |
132 | #define SR_CHANNEL 0x08, 0x1f, 0 | |
133 | #define SR_CCA_MODE 0x08, 0x60, 5 | |
134 | #define SR_CCA_REQUEST 0x08, 0x80, 7 | |
135 | #define RG_CCA_THRES (0x09) | |
136 | #define SR_CCA_ED_THRES 0x09, 0x0f, 0 | |
137 | #define SR_RESERVED_09_1 0x09, 0xf0, 4 | |
138 | #define RG_RX_CTRL (0x0a) | |
139 | #define SR_PDT_THRES 0x0a, 0x0f, 0 | |
140 | #define SR_RESERVED_0a_1 0x0a, 0xf0, 4 | |
141 | #define RG_SFD_VALUE (0x0b) | |
142 | #define SR_SFD_VALUE 0x0b, 0xff, 0 | |
143 | #define RG_TRX_CTRL_2 (0x0c) | |
144 | #define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0 | |
8fad346f PB |
145 | #define SR_SUB_MODE 0x0c, 0x04, 2 |
146 | #define SR_BPSK_QPSK 0x0c, 0x08, 3 | |
643e53c2 PB |
147 | #define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4 |
148 | #define SR_RESERVED_0c_5 0x0c, 0x60, 5 | |
7b8e19b6 | 149 | #define SR_RX_SAFE_MODE 0x0c, 0x80, 7 |
150 | #define RG_ANT_DIV (0x0d) | |
151 | #define SR_ANT_CTRL 0x0d, 0x03, 0 | |
152 | #define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2 | |
153 | #define SR_ANT_DIV_EN 0x0d, 0x08, 3 | |
154 | #define SR_RESERVED_0d_2 0x0d, 0x70, 4 | |
155 | #define SR_ANT_SEL 0x0d, 0x80, 7 | |
156 | #define RG_IRQ_MASK (0x0e) | |
157 | #define SR_IRQ_MASK 0x0e, 0xff, 0 | |
158 | #define RG_IRQ_STATUS (0x0f) | |
159 | #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0 | |
160 | #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1 | |
161 | #define SR_IRQ_2_RX_START 0x0f, 0x04, 2 | |
162 | #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3 | |
163 | #define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4 | |
164 | #define SR_IRQ_5_AMI 0x0f, 0x20, 5 | |
165 | #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6 | |
166 | #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7 | |
167 | #define RG_VREG_CTRL (0x10) | |
168 | #define SR_RESERVED_10_6 0x10, 0x03, 0 | |
169 | #define SR_DVDD_OK 0x10, 0x04, 2 | |
170 | #define SR_DVREG_EXT 0x10, 0x08, 3 | |
171 | #define SR_RESERVED_10_3 0x10, 0x30, 4 | |
172 | #define SR_AVDD_OK 0x10, 0x40, 6 | |
173 | #define SR_AVREG_EXT 0x10, 0x80, 7 | |
174 | #define RG_BATMON (0x11) | |
175 | #define SR_BATMON_VTH 0x11, 0x0f, 0 | |
176 | #define SR_BATMON_HR 0x11, 0x10, 4 | |
177 | #define SR_BATMON_OK 0x11, 0x20, 5 | |
178 | #define SR_RESERVED_11_1 0x11, 0xc0, 6 | |
179 | #define RG_XOSC_CTRL (0x12) | |
180 | #define SR_XTAL_TRIM 0x12, 0x0f, 0 | |
181 | #define SR_XTAL_MODE 0x12, 0xf0, 4 | |
182 | #define RG_RX_SYN (0x15) | |
183 | #define SR_RX_PDT_LEVEL 0x15, 0x0f, 0 | |
184 | #define SR_RESERVED_15_2 0x15, 0x70, 4 | |
185 | #define SR_RX_PDT_DIS 0x15, 0x80, 7 | |
186 | #define RG_XAH_CTRL_1 (0x17) | |
187 | #define SR_RESERVED_17_8 0x17, 0x01, 0 | |
188 | #define SR_AACK_PROM_MODE 0x17, 0x02, 1 | |
189 | #define SR_AACK_ACK_TIME 0x17, 0x04, 2 | |
190 | #define SR_RESERVED_17_5 0x17, 0x08, 3 | |
191 | #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4 | |
192 | #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5 | |
84dda3c6 | 193 | #define SR_CSMA_LBT_MODE 0x17, 0x40, 6 |
7b8e19b6 | 194 | #define SR_RESERVED_17_1 0x17, 0x80, 7 |
195 | #define RG_FTN_CTRL (0x18) | |
196 | #define SR_RESERVED_18_2 0x18, 0x7f, 0 | |
197 | #define SR_FTN_START 0x18, 0x80, 7 | |
198 | #define RG_PLL_CF (0x1a) | |
199 | #define SR_RESERVED_1a_2 0x1a, 0x7f, 0 | |
200 | #define SR_PLL_CF_START 0x1a, 0x80, 7 | |
201 | #define RG_PLL_DCU (0x1b) | |
202 | #define SR_RESERVED_1b_3 0x1b, 0x3f, 0 | |
203 | #define SR_RESERVED_1b_2 0x1b, 0x40, 6 | |
204 | #define SR_PLL_DCU_START 0x1b, 0x80, 7 | |
205 | #define RG_PART_NUM (0x1c) | |
206 | #define SR_PART_NUM 0x1c, 0xff, 0 | |
207 | #define RG_VERSION_NUM (0x1d) | |
208 | #define SR_VERSION_NUM 0x1d, 0xff, 0 | |
209 | #define RG_MAN_ID_0 (0x1e) | |
210 | #define SR_MAN_ID_0 0x1e, 0xff, 0 | |
211 | #define RG_MAN_ID_1 (0x1f) | |
212 | #define SR_MAN_ID_1 0x1f, 0xff, 0 | |
213 | #define RG_SHORT_ADDR_0 (0x20) | |
214 | #define SR_SHORT_ADDR_0 0x20, 0xff, 0 | |
215 | #define RG_SHORT_ADDR_1 (0x21) | |
216 | #define SR_SHORT_ADDR_1 0x21, 0xff, 0 | |
217 | #define RG_PAN_ID_0 (0x22) | |
218 | #define SR_PAN_ID_0 0x22, 0xff, 0 | |
219 | #define RG_PAN_ID_1 (0x23) | |
220 | #define SR_PAN_ID_1 0x23, 0xff, 0 | |
221 | #define RG_IEEE_ADDR_0 (0x24) | |
222 | #define SR_IEEE_ADDR_0 0x24, 0xff, 0 | |
223 | #define RG_IEEE_ADDR_1 (0x25) | |
224 | #define SR_IEEE_ADDR_1 0x25, 0xff, 0 | |
225 | #define RG_IEEE_ADDR_2 (0x26) | |
226 | #define SR_IEEE_ADDR_2 0x26, 0xff, 0 | |
227 | #define RG_IEEE_ADDR_3 (0x27) | |
228 | #define SR_IEEE_ADDR_3 0x27, 0xff, 0 | |
229 | #define RG_IEEE_ADDR_4 (0x28) | |
230 | #define SR_IEEE_ADDR_4 0x28, 0xff, 0 | |
231 | #define RG_IEEE_ADDR_5 (0x29) | |
232 | #define SR_IEEE_ADDR_5 0x29, 0xff, 0 | |
233 | #define RG_IEEE_ADDR_6 (0x2a) | |
234 | #define SR_IEEE_ADDR_6 0x2a, 0xff, 0 | |
235 | #define RG_IEEE_ADDR_7 (0x2b) | |
236 | #define SR_IEEE_ADDR_7 0x2b, 0xff, 0 | |
237 | #define RG_XAH_CTRL_0 (0x2c) | |
238 | #define SR_SLOTTED_OPERATION 0x2c, 0x01, 0 | |
239 | #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1 | |
240 | #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4 | |
241 | #define RG_CSMA_SEED_0 (0x2d) | |
242 | #define SR_CSMA_SEED_0 0x2d, 0xff, 0 | |
243 | #define RG_CSMA_SEED_1 (0x2e) | |
244 | #define SR_CSMA_SEED_1 0x2e, 0x07, 0 | |
245 | #define SR_AACK_I_AM_COORD 0x2e, 0x08, 3 | |
246 | #define SR_AACK_DIS_ACK 0x2e, 0x10, 4 | |
247 | #define SR_AACK_SET_PD 0x2e, 0x20, 5 | |
248 | #define SR_AACK_FVN_MODE 0x2e, 0xc0, 6 | |
249 | #define RG_CSMA_BE (0x2f) | |
250 | #define SR_MIN_BE 0x2f, 0x0f, 0 | |
251 | #define SR_MAX_BE 0x2f, 0xf0, 4 | |
252 | ||
253 | #define CMD_REG 0x80 | |
254 | #define CMD_REG_MASK 0x3f | |
255 | #define CMD_WRITE 0x40 | |
256 | #define CMD_FB 0x20 | |
257 | ||
258 | #define IRQ_BAT_LOW (1 << 7) | |
259 | #define IRQ_TRX_UR (1 << 6) | |
260 | #define IRQ_AMI (1 << 5) | |
261 | #define IRQ_CCA_ED (1 << 4) | |
262 | #define IRQ_TRX_END (1 << 3) | |
263 | #define IRQ_RX_START (1 << 2) | |
264 | #define IRQ_PLL_UNL (1 << 1) | |
265 | #define IRQ_PLL_LOCK (1 << 0) | |
266 | ||
43b5abe0 SH |
267 | #define IRQ_ACTIVE_HIGH 0 |
268 | #define IRQ_ACTIVE_LOW 1 | |
269 | ||
7b8e19b6 | 270 | #define STATE_P_ON 0x00 /* BUSY */ |
271 | #define STATE_BUSY_RX 0x01 | |
272 | #define STATE_BUSY_TX 0x02 | |
273 | #define STATE_FORCE_TRX_OFF 0x03 | |
274 | #define STATE_FORCE_TX_ON 0x04 /* IDLE */ | |
275 | /* 0x05 */ /* INVALID_PARAMETER */ | |
276 | #define STATE_RX_ON 0x06 | |
277 | /* 0x07 */ /* SUCCESS */ | |
278 | #define STATE_TRX_OFF 0x08 | |
279 | #define STATE_TX_ON 0x09 | |
280 | /* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */ | |
281 | #define STATE_SLEEP 0x0F | |
48d5dbaf | 282 | #define STATE_PREP_DEEP_SLEEP 0x10 |
7b8e19b6 | 283 | #define STATE_BUSY_RX_AACK 0x11 |
284 | #define STATE_BUSY_TX_ARET 0x12 | |
028889b0 | 285 | #define STATE_RX_AACK_ON 0x16 |
286 | #define STATE_TX_ARET_ON 0x19 | |
7b8e19b6 | 287 | #define STATE_RX_ON_NOCLK 0x1C |
288 | #define STATE_RX_AACK_ON_NOCLK 0x1D | |
289 | #define STATE_BUSY_RX_AACK_NOCLK 0x1E | |
290 | #define STATE_TRANSITION_IN_PROGRESS 0x1F | |
291 | ||
f76014f7 AA |
292 | #define AT86RF2XX_NUMREGS 0x3F |
293 | ||
97fed795 | 294 | static void |
1d15d6b5 AA |
295 | at86rf230_async_state_change(struct at86rf230_local *lp, |
296 | struct at86rf230_state_change *ctx, | |
97fed795 AA |
297 | const u8 state, void (*complete)(void *context), |
298 | const bool irq_enable); | |
1d15d6b5 | 299 | |
f76014f7 AA |
300 | static inline int |
301 | __at86rf230_write(struct at86rf230_local *lp, | |
302 | unsigned int addr, unsigned int data) | |
303 | { | |
304 | return regmap_write(lp->regmap, addr, data); | |
305 | } | |
306 | ||
307 | static inline int | |
308 | __at86rf230_read(struct at86rf230_local *lp, | |
309 | unsigned int addr, unsigned int *data) | |
310 | { | |
311 | return regmap_read(lp->regmap, addr, data); | |
312 | } | |
313 | ||
314 | static inline int | |
315 | at86rf230_read_subreg(struct at86rf230_local *lp, | |
316 | unsigned int addr, unsigned int mask, | |
317 | unsigned int shift, unsigned int *data) | |
318 | { | |
319 | int rc; | |
320 | ||
321 | rc = __at86rf230_read(lp, addr, data); | |
322 | if (rc > 0) | |
323 | *data = (*data & mask) >> shift; | |
324 | ||
325 | return rc; | |
326 | } | |
327 | ||
328 | static inline int | |
329 | at86rf230_write_subreg(struct at86rf230_local *lp, | |
330 | unsigned int addr, unsigned int mask, | |
331 | unsigned int shift, unsigned int data) | |
332 | { | |
333 | return regmap_update_bits(lp->regmap, addr, mask, data << shift); | |
334 | } | |
335 | ||
336 | static bool | |
337 | at86rf230_reg_writeable(struct device *dev, unsigned int reg) | |
338 | { | |
339 | switch (reg) { | |
340 | case RG_TRX_STATE: | |
341 | case RG_TRX_CTRL_0: | |
342 | case RG_TRX_CTRL_1: | |
343 | case RG_PHY_TX_PWR: | |
344 | case RG_PHY_ED_LEVEL: | |
345 | case RG_PHY_CC_CCA: | |
346 | case RG_CCA_THRES: | |
347 | case RG_RX_CTRL: | |
348 | case RG_SFD_VALUE: | |
349 | case RG_TRX_CTRL_2: | |
350 | case RG_ANT_DIV: | |
351 | case RG_IRQ_MASK: | |
352 | case RG_VREG_CTRL: | |
353 | case RG_BATMON: | |
354 | case RG_XOSC_CTRL: | |
355 | case RG_RX_SYN: | |
356 | case RG_XAH_CTRL_1: | |
357 | case RG_FTN_CTRL: | |
358 | case RG_PLL_CF: | |
359 | case RG_PLL_DCU: | |
360 | case RG_SHORT_ADDR_0: | |
361 | case RG_SHORT_ADDR_1: | |
362 | case RG_PAN_ID_0: | |
363 | case RG_PAN_ID_1: | |
364 | case RG_IEEE_ADDR_0: | |
365 | case RG_IEEE_ADDR_1: | |
366 | case RG_IEEE_ADDR_2: | |
367 | case RG_IEEE_ADDR_3: | |
368 | case RG_IEEE_ADDR_4: | |
369 | case RG_IEEE_ADDR_5: | |
370 | case RG_IEEE_ADDR_6: | |
371 | case RG_IEEE_ADDR_7: | |
372 | case RG_XAH_CTRL_0: | |
373 | case RG_CSMA_SEED_0: | |
374 | case RG_CSMA_SEED_1: | |
375 | case RG_CSMA_BE: | |
376 | return true; | |
377 | default: | |
378 | return false; | |
379 | } | |
380 | } | |
381 | ||
382 | static bool | |
383 | at86rf230_reg_readable(struct device *dev, unsigned int reg) | |
384 | { | |
385 | bool rc; | |
386 | ||
387 | /* all writeable are also readable */ | |
388 | rc = at86rf230_reg_writeable(dev, reg); | |
389 | if (rc) | |
390 | return rc; | |
391 | ||
392 | /* readonly regs */ | |
393 | switch (reg) { | |
394 | case RG_TRX_STATUS: | |
395 | case RG_PHY_RSSI: | |
396 | case RG_IRQ_STATUS: | |
397 | case RG_PART_NUM: | |
398 | case RG_VERSION_NUM: | |
399 | case RG_MAN_ID_1: | |
400 | case RG_MAN_ID_0: | |
401 | return true; | |
402 | default: | |
403 | return false; | |
404 | } | |
405 | } | |
406 | ||
407 | static bool | |
408 | at86rf230_reg_volatile(struct device *dev, unsigned int reg) | |
409 | { | |
410 | /* can be changed during runtime */ | |
411 | switch (reg) { | |
412 | case RG_TRX_STATUS: | |
413 | case RG_TRX_STATE: | |
414 | case RG_PHY_RSSI: | |
415 | case RG_PHY_ED_LEVEL: | |
416 | case RG_IRQ_STATUS: | |
417 | case RG_VREG_CTRL: | |
418 | return true; | |
419 | default: | |
420 | return false; | |
421 | } | |
422 | } | |
423 | ||
424 | static bool | |
425 | at86rf230_reg_precious(struct device *dev, unsigned int reg) | |
426 | { | |
427 | /* don't clear irq line on read */ | |
428 | switch (reg) { | |
429 | case RG_IRQ_STATUS: | |
430 | return true; | |
431 | default: | |
432 | return false; | |
433 | } | |
434 | } | |
435 | ||
889ee2c7 | 436 | static const struct regmap_config at86rf230_regmap_spi_config = { |
f76014f7 AA |
437 | .reg_bits = 8, |
438 | .val_bits = 8, | |
439 | .write_flag_mask = CMD_REG | CMD_WRITE, | |
440 | .read_flag_mask = CMD_REG, | |
441 | .cache_type = REGCACHE_RBTREE, | |
442 | .max_register = AT86RF2XX_NUMREGS, | |
443 | .writeable_reg = at86rf230_reg_writeable, | |
444 | .readable_reg = at86rf230_reg_readable, | |
445 | .volatile_reg = at86rf230_reg_volatile, | |
446 | .precious_reg = at86rf230_reg_precious, | |
447 | }; | |
448 | ||
1d15d6b5 AA |
449 | static void |
450 | at86rf230_async_error_recover(void *context) | |
451 | { | |
452 | struct at86rf230_state_change *ctx = context; | |
453 | struct at86rf230_local *lp = ctx->lp; | |
454 | ||
97fed795 | 455 | at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON, NULL, false); |
955aee8b | 456 | ieee802154_wake_queue(lp->hw); |
1d15d6b5 AA |
457 | } |
458 | ||
fc50c6e3 | 459 | static inline void |
1d15d6b5 AA |
460 | at86rf230_async_error(struct at86rf230_local *lp, |
461 | struct at86rf230_state_change *ctx, int rc) | |
462 | { | |
463 | dev_err(&lp->spi->dev, "spi_async error %d\n", rc); | |
464 | ||
465 | at86rf230_async_state_change(lp, ctx, STATE_FORCE_TRX_OFF, | |
97fed795 | 466 | at86rf230_async_error_recover, false); |
1d15d6b5 AA |
467 | } |
468 | ||
469 | /* Generic function to get some register value in async mode */ | |
97fed795 | 470 | static void |
1d15d6b5 AA |
471 | at86rf230_async_read_reg(struct at86rf230_local *lp, const u8 reg, |
472 | struct at86rf230_state_change *ctx, | |
97fed795 AA |
473 | void (*complete)(void *context), |
474 | const bool irq_enable) | |
7b8e19b6 | 475 | { |
97fed795 AA |
476 | int rc; |
477 | ||
1d15d6b5 AA |
478 | u8 *tx_buf = ctx->buf; |
479 | ||
480 | tx_buf[0] = (reg & CMD_REG_MASK) | CMD_REG; | |
1d15d6b5 | 481 | ctx->msg.complete = complete; |
97fed795 AA |
482 | ctx->irq_enable = irq_enable; |
483 | rc = spi_async(lp->spi, &ctx->msg); | |
484 | if (rc) { | |
485 | if (irq_enable) | |
cca990c8 | 486 | enable_irq(ctx->irq); |
97fed795 AA |
487 | |
488 | at86rf230_async_error(lp, ctx, rc); | |
489 | } | |
1d15d6b5 AA |
490 | } |
491 | ||
492 | static void | |
493 | at86rf230_async_state_assert(void *context) | |
494 | { | |
495 | struct at86rf230_state_change *ctx = context; | |
496 | struct at86rf230_local *lp = ctx->lp; | |
497 | const u8 *buf = ctx->buf; | |
498 | const u8 trx_state = buf[1] & 0x1f; | |
499 | ||
500 | /* Assert state change */ | |
501 | if (trx_state != ctx->to_state) { | |
502 | /* Special handling if transceiver state is in | |
503 | * STATE_BUSY_RX_AACK and a SHR was detected. | |
504 | */ | |
505 | if (trx_state == STATE_BUSY_RX_AACK) { | |
506 | /* Undocumented race condition. If we send a state | |
507 | * change to STATE_RX_AACK_ON the transceiver could | |
508 | * change his state automatically to STATE_BUSY_RX_AACK | |
509 | * if a SHR was detected. This is not an error, but we | |
510 | * can't assert this. | |
511 | */ | |
512 | if (ctx->to_state == STATE_RX_AACK_ON) | |
513 | goto done; | |
514 | ||
515 | /* If we change to STATE_TX_ON without forcing and | |
516 | * transceiver state is STATE_BUSY_RX_AACK, we wait | |
517 | * 'tFrame + tPAck' receiving time. In this time the | |
518 | * PDU should be received. If the transceiver is still | |
519 | * in STATE_BUSY_RX_AACK, we run a force state change | |
520 | * to STATE_TX_ON. This is a timeout handling, if the | |
521 | * transceiver stucks in STATE_BUSY_RX_AACK. | |
ba6d2239 AA |
522 | * |
523 | * Additional we do several retries to try to get into | |
524 | * TX_ON state without forcing. If the retries are | |
525 | * higher or equal than AT86RF2XX_MAX_TX_RETRIES we | |
526 | * will do a force change. | |
1d15d6b5 AA |
527 | */ |
528 | if (ctx->to_state == STATE_TX_ON) { | |
ba6d2239 AA |
529 | u8 state = STATE_TX_ON; |
530 | ||
531 | if (lp->tx_retry >= AT86RF2XX_MAX_TX_RETRIES) | |
532 | state = STATE_FORCE_TX_ON; | |
533 | lp->tx_retry++; | |
534 | ||
535 | at86rf230_async_state_change(lp, ctx, state, | |
97fed795 AA |
536 | ctx->complete, |
537 | ctx->irq_enable); | |
1d15d6b5 AA |
538 | return; |
539 | } | |
540 | } | |
541 | ||
1d15d6b5 AA |
542 | dev_warn(&lp->spi->dev, "unexcept state change from 0x%02x to 0x%02x. Actual state: 0x%02x\n", |
543 | ctx->from_state, ctx->to_state, trx_state); | |
544 | } | |
545 | ||
546 | done: | |
547 | if (ctx->complete) | |
548 | ctx->complete(context); | |
549 | } | |
550 | ||
551 | /* Do state change timing delay. */ | |
552 | static void | |
553 | at86rf230_async_state_delay(void *context) | |
554 | { | |
555 | struct at86rf230_state_change *ctx = context; | |
556 | struct at86rf230_local *lp = ctx->lp; | |
557 | struct at86rf2xx_chip_data *c = lp->data; | |
558 | bool force = false; | |
1d15d6b5 AA |
559 | |
560 | /* The force state changes are will show as normal states in the | |
561 | * state status subregister. We change the to_state to the | |
562 | * corresponding one and remember if it was a force change, this | |
563 | * differs if we do a state change from STATE_BUSY_RX_AACK. | |
564 | */ | |
565 | switch (ctx->to_state) { | |
566 | case STATE_FORCE_TX_ON: | |
567 | ctx->to_state = STATE_TX_ON; | |
568 | force = true; | |
569 | break; | |
570 | case STATE_FORCE_TRX_OFF: | |
571 | ctx->to_state = STATE_TRX_OFF; | |
572 | force = true; | |
573 | break; | |
574 | default: | |
575 | break; | |
576 | } | |
577 | ||
578 | switch (ctx->from_state) { | |
2e0571c0 AA |
579 | case STATE_TRX_OFF: |
580 | switch (ctx->to_state) { | |
581 | case STATE_RX_AACK_ON: | |
582 | usleep_range(c->t_off_to_aack, c->t_off_to_aack + 10); | |
583 | goto change; | |
584 | case STATE_TX_ON: | |
585 | usleep_range(c->t_off_to_tx_on, | |
586 | c->t_off_to_tx_on + 10); | |
587 | goto change; | |
588 | default: | |
589 | break; | |
590 | } | |
591 | break; | |
1d15d6b5 AA |
592 | case STATE_BUSY_RX_AACK: |
593 | switch (ctx->to_state) { | |
594 | case STATE_TX_ON: | |
595 | /* Wait for worst case receiving time if we | |
596 | * didn't make a force change from BUSY_RX_AACK | |
597 | * to TX_ON. | |
598 | */ | |
599 | if (!force) { | |
600 | usleep_range(c->t_frame + c->t_p_ack, | |
601 | c->t_frame + c->t_p_ack + 1000); | |
602 | goto change; | |
603 | } | |
604 | break; | |
605 | default: | |
606 | break; | |
607 | } | |
608 | break; | |
09e536cd AA |
609 | /* Default value, means RESET state */ |
610 | case STATE_P_ON: | |
611 | switch (ctx->to_state) { | |
612 | case STATE_TRX_OFF: | |
613 | usleep_range(c->t_reset_to_off, c->t_reset_to_off + 10); | |
614 | goto change; | |
615 | default: | |
616 | break; | |
617 | } | |
618 | break; | |
1d15d6b5 AA |
619 | default: |
620 | break; | |
621 | } | |
622 | ||
623 | /* Default delay is 1us in the most cases */ | |
624 | udelay(1); | |
625 | ||
626 | change: | |
97fed795 AA |
627 | at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx, |
628 | at86rf230_async_state_assert, | |
629 | ctx->irq_enable); | |
1d15d6b5 AA |
630 | } |
631 | ||
632 | static void | |
633 | at86rf230_async_state_change_start(void *context) | |
634 | { | |
635 | struct at86rf230_state_change *ctx = context; | |
636 | struct at86rf230_local *lp = ctx->lp; | |
637 | u8 *buf = ctx->buf; | |
638 | const u8 trx_state = buf[1] & 0x1f; | |
639 | int rc; | |
640 | ||
641 | /* Check for "possible" STATE_TRANSITION_IN_PROGRESS */ | |
642 | if (trx_state == STATE_TRANSITION_IN_PROGRESS) { | |
643 | udelay(1); | |
97fed795 AA |
644 | at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx, |
645 | at86rf230_async_state_change_start, | |
646 | ctx->irq_enable); | |
1d15d6b5 AA |
647 | return; |
648 | } | |
649 | ||
650 | /* Check if we already are in the state which we change in */ | |
651 | if (trx_state == ctx->to_state) { | |
652 | if (ctx->complete) | |
653 | ctx->complete(context); | |
654 | return; | |
655 | } | |
656 | ||
657 | /* Set current state to the context of state change */ | |
658 | ctx->from_state = trx_state; | |
659 | ||
660 | /* Going into the next step for a state change which do a timing | |
661 | * relevant delay. | |
662 | */ | |
663 | buf[0] = (RG_TRX_STATE & CMD_REG_MASK) | CMD_REG | CMD_WRITE; | |
664 | buf[1] = ctx->to_state; | |
1d15d6b5 AA |
665 | ctx->msg.complete = at86rf230_async_state_delay; |
666 | rc = spi_async(lp->spi, &ctx->msg); | |
97fed795 AA |
667 | if (rc) { |
668 | if (ctx->irq_enable) | |
cca990c8 | 669 | enable_irq(ctx->irq); |
97fed795 | 670 | |
4fef7d3b | 671 | at86rf230_async_error(lp, ctx, rc); |
97fed795 | 672 | } |
7b8e19b6 | 673 | } |
674 | ||
97fed795 | 675 | static void |
1d15d6b5 AA |
676 | at86rf230_async_state_change(struct at86rf230_local *lp, |
677 | struct at86rf230_state_change *ctx, | |
97fed795 AA |
678 | const u8 state, void (*complete)(void *context), |
679 | const bool irq_enable) | |
7b8e19b6 | 680 | { |
1d15d6b5 AA |
681 | /* Initialization for the state change context */ |
682 | ctx->to_state = state; | |
683 | ctx->complete = complete; | |
97fed795 AA |
684 | ctx->irq_enable = irq_enable; |
685 | at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx, | |
686 | at86rf230_async_state_change_start, | |
687 | irq_enable); | |
1d15d6b5 | 688 | } |
7b8e19b6 | 689 | |
2e0571c0 AA |
690 | static void |
691 | at86rf230_sync_state_change_complete(void *context) | |
692 | { | |
693 | struct at86rf230_state_change *ctx = context; | |
694 | struct at86rf230_local *lp = ctx->lp; | |
695 | ||
696 | complete(&lp->state_complete); | |
697 | } | |
698 | ||
699 | /* This function do a sync framework above the async state change. | |
700 | * Some callbacks of the IEEE 802.15.4 driver interface need to be | |
701 | * handled synchronously. | |
702 | */ | |
703 | static int | |
704 | at86rf230_sync_state_change(struct at86rf230_local *lp, unsigned int state) | |
705 | { | |
3e544ef9 | 706 | unsigned long rc; |
2e0571c0 | 707 | |
97fed795 AA |
708 | at86rf230_async_state_change(lp, &lp->state, state, |
709 | at86rf230_sync_state_change_complete, | |
710 | false); | |
2e0571c0 AA |
711 | |
712 | rc = wait_for_completion_timeout(&lp->state_complete, | |
713 | msecs_to_jiffies(100)); | |
d06c2199 AA |
714 | if (!rc) { |
715 | at86rf230_async_error(lp, &lp->state, -ETIMEDOUT); | |
2e0571c0 | 716 | return -ETIMEDOUT; |
d06c2199 | 717 | } |
2e0571c0 AA |
718 | |
719 | return 0; | |
720 | } | |
721 | ||
1d15d6b5 AA |
722 | static void |
723 | at86rf230_tx_complete(void *context) | |
724 | { | |
725 | struct at86rf230_state_change *ctx = context; | |
726 | struct at86rf230_local *lp = ctx->lp; | |
727 | ||
cca990c8 | 728 | enable_irq(ctx->irq); |
955aee8b | 729 | |
ef5428a1 | 730 | ieee802154_xmit_complete(lp->hw, lp->tx_skb, !lp->tx_aret); |
1d15d6b5 AA |
731 | } |
732 | ||
733 | static void | |
734 | at86rf230_tx_on(void *context) | |
735 | { | |
736 | struct at86rf230_state_change *ctx = context; | |
737 | struct at86rf230_local *lp = ctx->lp; | |
1d15d6b5 | 738 | |
31fa7434 | 739 | at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON, |
97fed795 | 740 | at86rf230_tx_complete, true); |
1d15d6b5 AA |
741 | } |
742 | ||
743 | static void | |
744 | at86rf230_tx_trac_error(void *context) | |
745 | { | |
746 | struct at86rf230_state_change *ctx = context; | |
747 | struct at86rf230_local *lp = ctx->lp; | |
1d15d6b5 | 748 | |
97fed795 AA |
749 | at86rf230_async_state_change(lp, ctx, STATE_TX_ON, |
750 | at86rf230_tx_on, true); | |
1d15d6b5 AA |
751 | } |
752 | ||
753 | static void | |
754 | at86rf230_tx_trac_check(void *context) | |
755 | { | |
756 | struct at86rf230_state_change *ctx = context; | |
757 | struct at86rf230_local *lp = ctx->lp; | |
758 | const u8 *buf = ctx->buf; | |
759 | const u8 trac = (buf[1] & 0xe0) >> 5; | |
1d15d6b5 AA |
760 | |
761 | /* If trac status is different than zero we need to do a state change | |
762 | * to STATE_FORCE_TRX_OFF then STATE_TX_ON to recover the transceiver | |
763 | * state to TX_ON. | |
764 | */ | |
c8c7e3db | 765 | if (trac) |
97fed795 AA |
766 | at86rf230_async_state_change(lp, ctx, STATE_FORCE_TRX_OFF, |
767 | at86rf230_tx_trac_error, true); | |
c8c7e3db AA |
768 | else |
769 | at86rf230_tx_on(context); | |
1d15d6b5 AA |
770 | } |
771 | ||
1d15d6b5 AA |
772 | static void |
773 | at86rf230_tx_trac_status(void *context) | |
774 | { | |
775 | struct at86rf230_state_change *ctx = context; | |
776 | struct at86rf230_local *lp = ctx->lp; | |
1d15d6b5 | 777 | |
97fed795 AA |
778 | at86rf230_async_read_reg(lp, RG_TRX_STATE, ctx, |
779 | at86rf230_tx_trac_check, true); | |
1d15d6b5 AA |
780 | } |
781 | ||
782 | static void | |
74de4c80 | 783 | at86rf230_rx_read_frame_complete(void *context) |
1d15d6b5 | 784 | { |
74de4c80 AA |
785 | struct at86rf230_state_change *ctx = context; |
786 | struct at86rf230_local *lp = ctx->lp; | |
1d15d6b5 | 787 | u8 rx_local_buf[AT86RF2XX_MAX_BUF]; |
31fa7434 | 788 | const u8 *buf = ctx->buf; |
74de4c80 AA |
789 | struct sk_buff *skb; |
790 | u8 len, lqi; | |
1d15d6b5 | 791 | |
74de4c80 AA |
792 | len = buf[1]; |
793 | if (!ieee802154_is_valid_psdu_len(len)) { | |
794 | dev_vdbg(&lp->spi->dev, "corrupted frame received\n"); | |
795 | len = IEEE802154_MTU; | |
796 | } | |
797 | lqi = buf[2 + len]; | |
798 | ||
799 | memcpy(rx_local_buf, buf + 2, len); | |
263be332 | 800 | ctx->trx.len = 2; |
cca990c8 | 801 | enable_irq(ctx->irq); |
1d15d6b5 | 802 | |
61a22814 | 803 | skb = dev_alloc_skb(IEEE802154_MTU); |
1d15d6b5 AA |
804 | if (!skb) { |
805 | dev_vdbg(&lp->spi->dev, "failed to allocate sk_buff\n"); | |
806 | return; | |
807 | } | |
808 | ||
809 | memcpy(skb_put(skb, len), rx_local_buf, len); | |
b89c3341 | 810 | ieee802154_rx_irqsafe(lp->hw, skb, lqi); |
1d15d6b5 | 811 | } |
7b8e19b6 | 812 | |
97fed795 | 813 | static void |
cca990c8 | 814 | at86rf230_rx_read_frame(void *context) |
1d15d6b5 | 815 | { |
cca990c8 AA |
816 | struct at86rf230_state_change *ctx = context; |
817 | struct at86rf230_local *lp = ctx->lp; | |
31fa7434 | 818 | u8 *buf = ctx->buf; |
97fed795 AA |
819 | int rc; |
820 | ||
7b8e19b6 | 821 | buf[0] = CMD_FB; |
31fa7434 AA |
822 | ctx->trx.len = AT86RF2XX_MAX_BUF; |
823 | ctx->msg.complete = at86rf230_rx_read_frame_complete; | |
824 | rc = spi_async(lp->spi, &ctx->msg); | |
97fed795 | 825 | if (rc) { |
263be332 | 826 | ctx->trx.len = 2; |
cca990c8 | 827 | enable_irq(ctx->irq); |
31fa7434 | 828 | at86rf230_async_error(lp, ctx, rc); |
97fed795 | 829 | } |
1d15d6b5 AA |
830 | } |
831 | ||
832 | static void | |
833 | at86rf230_rx_trac_check(void *context) | |
834 | { | |
1d15d6b5 AA |
835 | /* Possible check on trac status here. This could be useful to make |
836 | * some stats why receive is failed. Not used at the moment, but it's | |
837 | * maybe timing relevant. Datasheet doesn't say anything about this. | |
838 | * The programming guide say do it so. | |
839 | */ | |
840 | ||
cca990c8 | 841 | at86rf230_rx_read_frame(context); |
1d15d6b5 AA |
842 | } |
843 | ||
97fed795 | 844 | static void |
1d15d6b5 AA |
845 | at86rf230_irq_trx_end(struct at86rf230_local *lp) |
846 | { | |
847 | spin_lock(&lp->lock); | |
848 | if (lp->is_tx) { | |
849 | lp->is_tx = 0; | |
850 | spin_unlock(&lp->lock); | |
1d15d6b5 AA |
851 | |
852 | if (lp->tx_aret) | |
97fed795 AA |
853 | at86rf230_async_state_change(lp, &lp->irq, |
854 | STATE_FORCE_TX_ON, | |
855 | at86rf230_tx_trac_status, | |
856 | true); | |
1d15d6b5 | 857 | else |
97fed795 AA |
858 | at86rf230_async_state_change(lp, &lp->irq, |
859 | STATE_RX_AACK_ON, | |
860 | at86rf230_tx_complete, | |
861 | true); | |
1d15d6b5 AA |
862 | } else { |
863 | spin_unlock(&lp->lock); | |
97fed795 AA |
864 | at86rf230_async_read_reg(lp, RG_TRX_STATE, &lp->irq, |
865 | at86rf230_rx_trac_check, true); | |
1d15d6b5 AA |
866 | } |
867 | } | |
868 | ||
869 | static void | |
870 | at86rf230_irq_status(void *context) | |
871 | { | |
872 | struct at86rf230_state_change *ctx = context; | |
873 | struct at86rf230_local *lp = ctx->lp; | |
31fa7434 | 874 | const u8 *buf = ctx->buf; |
1d15d6b5 | 875 | const u8 irq = buf[1]; |
1d15d6b5 AA |
876 | |
877 | if (irq & IRQ_TRX_END) { | |
97fed795 | 878 | at86rf230_irq_trx_end(lp); |
1d15d6b5 | 879 | } else { |
cca990c8 | 880 | enable_irq(ctx->irq); |
1d15d6b5 AA |
881 | dev_err(&lp->spi->dev, "not supported irq %02x received\n", |
882 | irq); | |
883 | } | |
884 | } | |
885 | ||
886 | static irqreturn_t at86rf230_isr(int irq, void *data) | |
887 | { | |
888 | struct at86rf230_local *lp = data; | |
889 | struct at86rf230_state_change *ctx = &lp->irq; | |
890 | u8 *buf = ctx->buf; | |
891 | int rc; | |
892 | ||
90566363 | 893 | disable_irq_nosync(irq); |
1d15d6b5 AA |
894 | |
895 | buf[0] = (RG_IRQ_STATUS & CMD_REG_MASK) | CMD_REG; | |
1d15d6b5 AA |
896 | ctx->msg.complete = at86rf230_irq_status; |
897 | rc = spi_async(lp->spi, &ctx->msg); | |
898 | if (rc) { | |
e9310211 | 899 | enable_irq(irq); |
1d15d6b5 AA |
900 | at86rf230_async_error(lp, ctx, rc); |
901 | return IRQ_NONE; | |
902 | } | |
903 | ||
904 | return IRQ_HANDLED; | |
905 | } | |
906 | ||
907 | static void | |
908 | at86rf230_write_frame_complete(void *context) | |
909 | { | |
910 | struct at86rf230_state_change *ctx = context; | |
911 | struct at86rf230_local *lp = ctx->lp; | |
912 | u8 *buf = ctx->buf; | |
913 | int rc; | |
914 | ||
915 | buf[0] = (RG_TRX_STATE & CMD_REG_MASK) | CMD_REG | CMD_WRITE; | |
916 | buf[1] = STATE_BUSY_TX; | |
917 | ctx->trx.len = 2; | |
918 | ctx->msg.complete = NULL; | |
919 | rc = spi_async(lp->spi, &ctx->msg); | |
920 | if (rc) | |
921 | at86rf230_async_error(lp, ctx, rc); | |
922 | } | |
923 | ||
924 | static void | |
925 | at86rf230_write_frame(void *context) | |
926 | { | |
927 | struct at86rf230_state_change *ctx = context; | |
928 | struct at86rf230_local *lp = ctx->lp; | |
929 | struct sk_buff *skb = lp->tx_skb; | |
31fa7434 | 930 | u8 *buf = ctx->buf; |
1d15d6b5 AA |
931 | int rc; |
932 | ||
933 | spin_lock(&lp->lock); | |
934 | lp->is_tx = 1; | |
935 | spin_unlock(&lp->lock); | |
936 | ||
937 | buf[0] = CMD_FB | CMD_WRITE; | |
938 | buf[1] = skb->len + 2; | |
939 | memcpy(buf + 2, skb->data, skb->len); | |
31fa7434 AA |
940 | ctx->trx.len = skb->len + 2; |
941 | ctx->msg.complete = at86rf230_write_frame_complete; | |
942 | rc = spi_async(lp->spi, &ctx->msg); | |
263be332 AA |
943 | if (rc) { |
944 | ctx->trx.len = 2; | |
1d15d6b5 | 945 | at86rf230_async_error(lp, ctx, rc); |
263be332 | 946 | } |
1d15d6b5 AA |
947 | } |
948 | ||
949 | static void | |
950 | at86rf230_xmit_tx_on(void *context) | |
951 | { | |
952 | struct at86rf230_state_change *ctx = context; | |
953 | struct at86rf230_local *lp = ctx->lp; | |
7b8e19b6 | 954 | |
97fed795 AA |
955 | at86rf230_async_state_change(lp, ctx, STATE_TX_ARET_ON, |
956 | at86rf230_write_frame, false); | |
1d15d6b5 AA |
957 | } |
958 | ||
959 | static int | |
5a504397 | 960 | at86rf230_xmit(struct ieee802154_hw *hw, struct sk_buff *skb) |
1d15d6b5 | 961 | { |
5a504397 | 962 | struct at86rf230_local *lp = hw->priv; |
1d15d6b5 | 963 | struct at86rf230_state_change *ctx = &lp->tx; |
7b8e19b6 | 964 | |
1d15d6b5 | 965 | void (*tx_complete)(void *context) = at86rf230_write_frame; |
7b8e19b6 | 966 | |
1d15d6b5 | 967 | lp->tx_skb = skb; |
7b8e19b6 | 968 | |
1d15d6b5 AA |
969 | /* In ARET mode we need to go into STATE_TX_ARET_ON after we |
970 | * are in STATE_TX_ON. The pfad differs here, so we change | |
971 | * the complete handler. | |
972 | */ | |
973 | if (lp->tx_aret) | |
974 | tx_complete = at86rf230_xmit_tx_on; | |
7b8e19b6 | 975 | |
ba6d2239 | 976 | lp->tx_retry = 0; |
97fed795 AA |
977 | at86rf230_async_state_change(lp, ctx, STATE_TX_ON, tx_complete, false); |
978 | ||
1d15d6b5 | 979 | return 0; |
7b8e19b6 | 980 | } |
981 | ||
982 | static int | |
5a504397 | 983 | at86rf230_ed(struct ieee802154_hw *hw, u8 *level) |
7b8e19b6 | 984 | { |
7b8e19b6 | 985 | BUG_ON(!level); |
986 | *level = 0xbe; | |
987 | return 0; | |
988 | } | |
989 | ||
7b8e19b6 | 990 | static int |
5a504397 | 991 | at86rf230_start(struct ieee802154_hw *hw) |
7b8e19b6 | 992 | { |
5a504397 | 993 | return at86rf230_sync_state_change(hw->priv, STATE_RX_AACK_ON); |
7b8e19b6 | 994 | } |
995 | ||
996 | static void | |
5a504397 | 997 | at86rf230_stop(struct ieee802154_hw *hw) |
7b8e19b6 | 998 | { |
5a504397 | 999 | at86rf230_sync_state_change(hw->priv, STATE_FORCE_TRX_OFF); |
7b8e19b6 | 1000 | } |
1001 | ||
8fad346f | 1002 | static int |
e37d2ec8 | 1003 | at86rf23x_set_channel(struct at86rf230_local *lp, u8 page, u8 channel) |
8fad346f PB |
1004 | { |
1005 | return at86rf230_write_subreg(lp, SR_CHANNEL, channel); | |
1006 | } | |
1007 | ||
1008 | static int | |
e37d2ec8 | 1009 | at86rf212_set_channel(struct at86rf230_local *lp, u8 page, u8 channel) |
8fad346f PB |
1010 | { |
1011 | int rc; | |
1012 | ||
1013 | if (channel == 0) | |
1014 | rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 0); | |
1015 | else | |
1016 | rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 1); | |
1017 | if (rc < 0) | |
1018 | return rc; | |
1019 | ||
6ca00197 | 1020 | if (page == 0) { |
643e53c2 | 1021 | rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 0); |
a53d1f7c | 1022 | lp->data->rssi_base_val = -100; |
6ca00197 | 1023 | } else { |
643e53c2 | 1024 | rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 1); |
a53d1f7c | 1025 | lp->data->rssi_base_val = -98; |
6ca00197 | 1026 | } |
643e53c2 PB |
1027 | if (rc < 0) |
1028 | return rc; | |
1029 | ||
24ccb9f4 AA |
1030 | /* This sets the symbol_duration according frequency on the 212. |
1031 | * TODO move this handling while set channel and page in cfg802154. | |
1032 | * We can do that, this timings are according 802.15.4 standard. | |
1033 | * If we do that in cfg802154, this is a more generic calculation. | |
1034 | * | |
1035 | * This should also protected from ifs_timer. Means cancel timer and | |
1036 | * init with a new value. For now, this is okay. | |
1037 | */ | |
1038 | if (channel == 0) { | |
1039 | if (page == 0) { | |
1040 | /* SUB:0 and BPSK:0 -> BPSK-20 */ | |
1041 | lp->hw->phy->symbol_duration = 50; | |
1042 | } else { | |
1043 | /* SUB:1 and BPSK:0 -> BPSK-40 */ | |
1044 | lp->hw->phy->symbol_duration = 25; | |
1045 | } | |
1046 | } else { | |
1047 | if (page == 0) | |
2d6dde29 | 1048 | /* SUB:0 and BPSK:1 -> OQPSK-100/200/400 */ |
24ccb9f4 AA |
1049 | lp->hw->phy->symbol_duration = 40; |
1050 | else | |
2d6dde29 | 1051 | /* SUB:1 and BPSK:1 -> OQPSK-250/500/1000 */ |
24ccb9f4 AA |
1052 | lp->hw->phy->symbol_duration = 16; |
1053 | } | |
1054 | ||
1055 | lp->hw->phy->lifs_period = IEEE802154_LIFS_PERIOD * | |
1056 | lp->hw->phy->symbol_duration; | |
1057 | lp->hw->phy->sifs_period = IEEE802154_SIFS_PERIOD * | |
1058 | lp->hw->phy->symbol_duration; | |
1059 | ||
8fad346f PB |
1060 | return at86rf230_write_subreg(lp, SR_CHANNEL, channel); |
1061 | } | |
1062 | ||
7b8e19b6 | 1063 | static int |
e37d2ec8 | 1064 | at86rf230_channel(struct ieee802154_hw *hw, u8 page, u8 channel) |
7b8e19b6 | 1065 | { |
5a504397 | 1066 | struct at86rf230_local *lp = hw->priv; |
7b8e19b6 | 1067 | int rc; |
1068 | ||
a53d1f7c | 1069 | rc = lp->data->set_channel(lp, page, channel); |
984e0c68 AA |
1070 | /* Wait for PLL */ |
1071 | usleep_range(lp->data->t_channel_switch, | |
1072 | lp->data->t_channel_switch + 10); | |
820bd66f | 1073 | return rc; |
7b8e19b6 | 1074 | } |
1075 | ||
1486774d | 1076 | static int |
5a504397 | 1077 | at86rf230_set_hw_addr_filt(struct ieee802154_hw *hw, |
1486774d | 1078 | struct ieee802154_hw_addr_filt *filt, |
1079 | unsigned long changed) | |
1080 | { | |
5a504397 | 1081 | struct at86rf230_local *lp = hw->priv; |
1486774d | 1082 | |
57205c14 | 1083 | if (changed & IEEE802154_AFILT_SADDR_CHANGED) { |
b70ab2e8 PB |
1084 | u16 addr = le16_to_cpu(filt->short_addr); |
1085 | ||
1486774d | 1086 | dev_vdbg(&lp->spi->dev, |
e80fb5ee | 1087 | "at86rf230_set_hw_addr_filt called for saddr\n"); |
b70ab2e8 PB |
1088 | __at86rf230_write(lp, RG_SHORT_ADDR_0, addr); |
1089 | __at86rf230_write(lp, RG_SHORT_ADDR_1, addr >> 8); | |
1486774d | 1090 | } |
1091 | ||
57205c14 | 1092 | if (changed & IEEE802154_AFILT_PANID_CHANGED) { |
b70ab2e8 PB |
1093 | u16 pan = le16_to_cpu(filt->pan_id); |
1094 | ||
1486774d | 1095 | dev_vdbg(&lp->spi->dev, |
e80fb5ee | 1096 | "at86rf230_set_hw_addr_filt called for pan id\n"); |
b70ab2e8 PB |
1097 | __at86rf230_write(lp, RG_PAN_ID_0, pan); |
1098 | __at86rf230_write(lp, RG_PAN_ID_1, pan >> 8); | |
1486774d | 1099 | } |
1100 | ||
57205c14 | 1101 | if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) { |
b70ab2e8 PB |
1102 | u8 i, addr[8]; |
1103 | ||
1104 | memcpy(addr, &filt->ieee_addr, 8); | |
1486774d | 1105 | dev_vdbg(&lp->spi->dev, |
e80fb5ee | 1106 | "at86rf230_set_hw_addr_filt called for IEEE addr\n"); |
b70ab2e8 PB |
1107 | for (i = 0; i < 8; i++) |
1108 | __at86rf230_write(lp, RG_IEEE_ADDR_0 + i, addr[i]); | |
1486774d | 1109 | } |
1110 | ||
57205c14 | 1111 | if (changed & IEEE802154_AFILT_PANC_CHANGED) { |
1486774d | 1112 | dev_vdbg(&lp->spi->dev, |
e80fb5ee | 1113 | "at86rf230_set_hw_addr_filt called for panc change\n"); |
1486774d | 1114 | if (filt->pan_coord) |
1115 | at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 1); | |
1116 | else | |
1117 | at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 0); | |
1118 | } | |
1119 | ||
1120 | return 0; | |
1121 | } | |
1122 | ||
9b2777d6 | 1123 | static int |
5a504397 | 1124 | at86rf230_set_txpower(struct ieee802154_hw *hw, int db) |
9b2777d6 | 1125 | { |
5a504397 | 1126 | struct at86rf230_local *lp = hw->priv; |
9b2777d6 PB |
1127 | |
1128 | /* typical maximum output is 5dBm with RG_PHY_TX_PWR 0x60, lower five | |
1129 | * bits decrease power in 1dB steps. 0x60 represents extra PA gain of | |
1130 | * 0dB. | |
1131 | * thus, supported values for db range from -26 to 5, for 31dB of | |
1132 | * reduction to 0dB of reduction. | |
1133 | */ | |
1134 | if (db > 5 || db < -26) | |
1135 | return -EINVAL; | |
1136 | ||
1137 | db = -(db - 5); | |
1138 | ||
677676cd | 1139 | return __at86rf230_write(lp, RG_PHY_TX_PWR, 0x60 | db); |
9b2777d6 PB |
1140 | } |
1141 | ||
84dda3c6 | 1142 | static int |
5a504397 | 1143 | at86rf230_set_lbt(struct ieee802154_hw *hw, bool on) |
84dda3c6 | 1144 | { |
5a504397 | 1145 | struct at86rf230_local *lp = hw->priv; |
84dda3c6 PB |
1146 | |
1147 | return at86rf230_write_subreg(lp, SR_CSMA_LBT_MODE, on); | |
1148 | } | |
1149 | ||
ba08fea5 | 1150 | static int |
7fe9a388 AA |
1151 | at86rf230_set_cca_mode(struct ieee802154_hw *hw, |
1152 | const struct wpan_phy_cca *cca) | |
ba08fea5 | 1153 | { |
5a504397 | 1154 | struct at86rf230_local *lp = hw->priv; |
7fe9a388 | 1155 | u8 val; |
ba08fea5 | 1156 | |
7fe9a388 AA |
1157 | /* mapping 802.15.4 to driver spec */ |
1158 | switch (cca->mode) { | |
1159 | case NL802154_CCA_ENERGY: | |
1160 | val = 1; | |
1161 | break; | |
1162 | case NL802154_CCA_CARRIER: | |
1163 | val = 2; | |
1164 | break; | |
1165 | case NL802154_CCA_ENERGY_CARRIER: | |
1166 | switch (cca->opt) { | |
1167 | case NL802154_CCA_OPT_ENERGY_CARRIER_AND: | |
1168 | val = 3; | |
1169 | break; | |
1170 | case NL802154_CCA_OPT_ENERGY_CARRIER_OR: | |
1171 | val = 0; | |
1172 | break; | |
1173 | default: | |
1174 | return -EINVAL; | |
1175 | } | |
1176 | break; | |
1177 | default: | |
1178 | return -EINVAL; | |
1179 | } | |
1180 | ||
1181 | return at86rf230_write_subreg(lp, SR_CCA_MODE, val); | |
ba08fea5 PB |
1182 | } |
1183 | ||
a7d7eda9 AA |
1184 | static int |
1185 | at86rf212_get_desens_steps(struct at86rf230_local *lp, s32 level) | |
1186 | { | |
1187 | return (level - lp->data->rssi_base_val) * 100 / 207; | |
1188 | } | |
1189 | ||
1190 | static int | |
1191 | at86rf23x_get_desens_steps(struct at86rf230_local *lp, s32 level) | |
1192 | { | |
1193 | return (level - lp->data->rssi_base_val) / 2; | |
1194 | } | |
1195 | ||
6ca00197 | 1196 | static int |
5a504397 | 1197 | at86rf230_set_cca_ed_level(struct ieee802154_hw *hw, s32 level) |
6ca00197 | 1198 | { |
5a504397 | 1199 | struct at86rf230_local *lp = hw->priv; |
6ca00197 | 1200 | |
a53d1f7c | 1201 | if (level < lp->data->rssi_base_val || level > 30) |
6ca00197 PB |
1202 | return -EINVAL; |
1203 | ||
a7d7eda9 AA |
1204 | return at86rf230_write_subreg(lp, SR_CCA_ED_THRES, |
1205 | lp->data->get_desense_steps(lp, level)); | |
6ca00197 PB |
1206 | } |
1207 | ||
f2fdd67c | 1208 | static int |
5a504397 | 1209 | at86rf230_set_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be, |
f2fdd67c PB |
1210 | u8 retries) |
1211 | { | |
5a504397 | 1212 | struct at86rf230_local *lp = hw->priv; |
f2fdd67c PB |
1213 | int rc; |
1214 | ||
f2fdd67c PB |
1215 | rc = at86rf230_write_subreg(lp, SR_MIN_BE, min_be); |
1216 | if (rc) | |
1217 | return rc; | |
1218 | ||
1219 | rc = at86rf230_write_subreg(lp, SR_MAX_BE, max_be); | |
1220 | if (rc) | |
1221 | return rc; | |
1222 | ||
39d7f320 | 1223 | return at86rf230_write_subreg(lp, SR_MAX_CSMA_RETRIES, retries); |
f2fdd67c PB |
1224 | } |
1225 | ||
1226 | static int | |
5a504397 | 1227 | at86rf230_set_frame_retries(struct ieee802154_hw *hw, s8 retries) |
f2fdd67c | 1228 | { |
5a504397 | 1229 | struct at86rf230_local *lp = hw->priv; |
f2fdd67c PB |
1230 | int rc = 0; |
1231 | ||
f2fdd67c | 1232 | lp->tx_aret = retries >= 0; |
850f43ac | 1233 | lp->max_frame_retries = retries; |
f2fdd67c PB |
1234 | |
1235 | if (retries >= 0) | |
1236 | rc = at86rf230_write_subreg(lp, SR_MAX_FRAME_RETRIES, retries); | |
1237 | ||
1238 | return rc; | |
1239 | } | |
1240 | ||
92f45f54 AA |
1241 | static int |
1242 | at86rf230_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on) | |
1243 | { | |
1244 | struct at86rf230_local *lp = hw->priv; | |
1245 | int rc; | |
1246 | ||
1247 | if (on) { | |
1248 | rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 1); | |
1249 | if (rc < 0) | |
1250 | return rc; | |
1251 | ||
1252 | rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 1); | |
1253 | if (rc < 0) | |
1254 | return rc; | |
1255 | } else { | |
1256 | rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 0); | |
1257 | if (rc < 0) | |
1258 | return rc; | |
1259 | ||
1260 | rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 0); | |
1261 | if (rc < 0) | |
1262 | return rc; | |
1263 | } | |
1264 | ||
1265 | return 0; | |
1266 | } | |
1267 | ||
16301861 | 1268 | static const struct ieee802154_ops at86rf230_ops = { |
7b8e19b6 | 1269 | .owner = THIS_MODULE, |
955aee8b | 1270 | .xmit_async = at86rf230_xmit, |
7b8e19b6 | 1271 | .ed = at86rf230_ed, |
1272 | .set_channel = at86rf230_channel, | |
1273 | .start = at86rf230_start, | |
1274 | .stop = at86rf230_stop, | |
1486774d | 1275 | .set_hw_addr_filt = at86rf230_set_hw_addr_filt, |
640985ec AA |
1276 | .set_txpower = at86rf230_set_txpower, |
1277 | .set_lbt = at86rf230_set_lbt, | |
1278 | .set_cca_mode = at86rf230_set_cca_mode, | |
1279 | .set_cca_ed_level = at86rf230_set_cca_ed_level, | |
1280 | .set_csma_params = at86rf230_set_csma_params, | |
1281 | .set_frame_retries = at86rf230_set_frame_retries, | |
92f45f54 | 1282 | .set_promiscuous_mode = at86rf230_set_promiscuous_mode, |
8fad346f PB |
1283 | }; |
1284 | ||
a53d1f7c | 1285 | static struct at86rf2xx_chip_data at86rf233_data = { |
7a4ef918 | 1286 | .t_sleep_cycle = 330, |
984e0c68 | 1287 | .t_channel_switch = 11, |
09e536cd | 1288 | .t_reset_to_off = 26, |
2e0571c0 AA |
1289 | .t_off_to_aack = 80, |
1290 | .t_off_to_tx_on = 80, | |
1d15d6b5 AA |
1291 | .t_frame = 4096, |
1292 | .t_p_ack = 545, | |
a53d1f7c AA |
1293 | .rssi_base_val = -91, |
1294 | .set_channel = at86rf23x_set_channel, | |
a7d7eda9 | 1295 | .get_desense_steps = at86rf23x_get_desens_steps |
a53d1f7c AA |
1296 | }; |
1297 | ||
1298 | static struct at86rf2xx_chip_data at86rf231_data = { | |
7a4ef918 | 1299 | .t_sleep_cycle = 330, |
984e0c68 | 1300 | .t_channel_switch = 24, |
09e536cd | 1301 | .t_reset_to_off = 37, |
2e0571c0 AA |
1302 | .t_off_to_aack = 110, |
1303 | .t_off_to_tx_on = 110, | |
1d15d6b5 AA |
1304 | .t_frame = 4096, |
1305 | .t_p_ack = 545, | |
a53d1f7c AA |
1306 | .rssi_base_val = -91, |
1307 | .set_channel = at86rf23x_set_channel, | |
a7d7eda9 | 1308 | .get_desense_steps = at86rf23x_get_desens_steps |
a53d1f7c AA |
1309 | }; |
1310 | ||
1311 | static struct at86rf2xx_chip_data at86rf212_data = { | |
7a4ef918 | 1312 | .t_sleep_cycle = 330, |
984e0c68 | 1313 | .t_channel_switch = 11, |
09e536cd | 1314 | .t_reset_to_off = 26, |
2e0571c0 AA |
1315 | .t_off_to_aack = 200, |
1316 | .t_off_to_tx_on = 200, | |
1d15d6b5 AA |
1317 | .t_frame = 4096, |
1318 | .t_p_ack = 545, | |
a53d1f7c AA |
1319 | .rssi_base_val = -100, |
1320 | .set_channel = at86rf212_set_channel, | |
a7d7eda9 | 1321 | .get_desense_steps = at86rf212_get_desens_steps |
a53d1f7c AA |
1322 | }; |
1323 | ||
ccdaeb2b | 1324 | static int at86rf230_hw_init(struct at86rf230_local *lp, u8 xtal_trim) |
7b8e19b6 | 1325 | { |
1db0558e | 1326 | int rc, irq_type, irq_pol = IRQ_ACTIVE_HIGH; |
f76014f7 | 1327 | unsigned int dvdd; |
f2fdd67c | 1328 | u8 csma_seed[2]; |
7b8e19b6 | 1329 | |
09e536cd | 1330 | rc = at86rf230_sync_state_change(lp, STATE_FORCE_TRX_OFF); |
7dcbd22a PB |
1331 | if (rc) |
1332 | return rc; | |
7b8e19b6 | 1333 | |
4af619ae | 1334 | irq_type = irq_get_trigger_type(lp->spi->irq); |
c91799c5 AA |
1335 | if (irq_type == IRQ_TYPE_EDGE_RISING || |
1336 | irq_type == IRQ_TYPE_EDGE_FALLING) | |
1337 | dev_warn(&lp->spi->dev, | |
1338 | "Using edge triggered irq's are not recommended!\n"); | |
702d211c AA |
1339 | if (irq_type == IRQ_TYPE_EDGE_FALLING || |
1340 | irq_type == IRQ_TYPE_LEVEL_LOW) | |
43b5abe0 | 1341 | irq_pol = IRQ_ACTIVE_LOW; |
43b5abe0 | 1342 | |
18c65049 | 1343 | rc = at86rf230_write_subreg(lp, SR_IRQ_POLARITY, irq_pol); |
43b5abe0 SH |
1344 | if (rc) |
1345 | return rc; | |
1346 | ||
6bd2b132 AA |
1347 | rc = at86rf230_write_subreg(lp, SR_RX_SAFE_MODE, 1); |
1348 | if (rc) | |
1349 | return rc; | |
1350 | ||
057dad6f | 1351 | rc = at86rf230_write_subreg(lp, SR_IRQ_MASK, IRQ_TRX_END); |
7b8e19b6 | 1352 | if (rc) |
1353 | return rc; | |
1354 | ||
be64f076 AA |
1355 | /* reset values differs in at86rf231 and at86rf233 */ |
1356 | rc = at86rf230_write_subreg(lp, SR_IRQ_MASK_MODE, 0); | |
1357 | if (rc) | |
1358 | return rc; | |
1359 | ||
f2fdd67c PB |
1360 | get_random_bytes(csma_seed, ARRAY_SIZE(csma_seed)); |
1361 | rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_0, csma_seed[0]); | |
1362 | if (rc) | |
1363 | return rc; | |
1364 | rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_1, csma_seed[1]); | |
1365 | if (rc) | |
1366 | return rc; | |
1367 | ||
7b8e19b6 | 1368 | /* CLKM changes are applied immediately */ |
1369 | rc = at86rf230_write_subreg(lp, SR_CLKM_SHA_SEL, 0x00); | |
1370 | if (rc) | |
1371 | return rc; | |
1372 | ||
1373 | /* Turn CLKM Off */ | |
1374 | rc = at86rf230_write_subreg(lp, SR_CLKM_CTRL, 0x00); | |
1375 | if (rc) | |
1376 | return rc; | |
1377 | /* Wait the next SLEEP cycle */ | |
7a4ef918 AA |
1378 | usleep_range(lp->data->t_sleep_cycle, |
1379 | lp->data->t_sleep_cycle + 100); | |
7b8e19b6 | 1380 | |
ccdaeb2b AA |
1381 | /* xtal_trim value is calculated by: |
1382 | * CL = 0.5 * (CX + CTRIM + CPAR) | |
1383 | * | |
1384 | * whereas: | |
1385 | * CL = capacitor of used crystal | |
1386 | * CX = connected capacitors at xtal pins | |
1387 | * CPAR = in all at86rf2xx datasheets this is a constant value 3 pF, | |
1388 | * but this is different on each board setup. You need to fine | |
1389 | * tuning this value via CTRIM. | |
1390 | * CTRIM = variable capacitor setting. Resolution is 0.3 pF range is | |
1391 | * 0 pF upto 4.5 pF. | |
1392 | * | |
1393 | * Examples: | |
1394 | * atben transceiver: | |
1395 | * | |
1396 | * CL = 8 pF | |
1397 | * CX = 12 pF | |
1398 | * CPAR = 3 pF (We assume the magic constant from datasheet) | |
1399 | * CTRIM = 0.9 pF | |
1400 | * | |
1401 | * (12+0.9+3)/2 = 7.95 which is nearly at 8 pF | |
1402 | * | |
1403 | * xtal_trim = 0x3 | |
1404 | * | |
1405 | * openlabs transceiver: | |
1406 | * | |
1407 | * CL = 16 pF | |
1408 | * CX = 22 pF | |
1409 | * CPAR = 3 pF (We assume the magic constant from datasheet) | |
1410 | * CTRIM = 4.5 pF | |
1411 | * | |
1412 | * (22+4.5+3)/2 = 14.75 which is the nearest value to 16 pF | |
1413 | * | |
1414 | * xtal_trim = 0xf | |
1415 | */ | |
1416 | rc = at86rf230_write_subreg(lp, SR_XTAL_TRIM, xtal_trim); | |
1417 | if (rc) | |
1418 | return rc; | |
1419 | ||
1cc9fc53 | 1420 | rc = at86rf230_read_subreg(lp, SR_DVDD_OK, &dvdd); |
7b8e19b6 | 1421 | if (rc) |
1422 | return rc; | |
1cc9fc53 | 1423 | if (!dvdd) { |
7b8e19b6 | 1424 | dev_err(&lp->spi->dev, "DVDD error\n"); |
1425 | return -EINVAL; | |
1426 | } | |
1427 | ||
05e3f2f3 AA |
1428 | /* Force setting slotted operation bit to 0. Sometimes the atben |
1429 | * sets this bit and I don't know why. We set this always force | |
1430 | * to zero while probing. | |
1431 | */ | |
6cc6399c | 1432 | return at86rf230_write_subreg(lp, SR_SLOTTED_OPERATION, 0); |
7b8e19b6 | 1433 | } |
1434 | ||
aaa1c4d2 | 1435 | static int |
ccdaeb2b AA |
1436 | at86rf230_get_pdata(struct spi_device *spi, int *rstn, int *slp_tr, |
1437 | u8 *xtal_trim) | |
fa2d3e94 | 1438 | { |
aaa1c4d2 | 1439 | struct at86rf230_platform_data *pdata = spi->dev.platform_data; |
ccdaeb2b | 1440 | int ret; |
fa2d3e94 | 1441 | |
aaa1c4d2 AA |
1442 | if (!IS_ENABLED(CONFIG_OF) || !spi->dev.of_node) { |
1443 | if (!pdata) | |
1444 | return -ENOENT; | |
fa2d3e94 | 1445 | |
aaa1c4d2 AA |
1446 | *rstn = pdata->rstn; |
1447 | *slp_tr = pdata->slp_tr; | |
ccdaeb2b | 1448 | *xtal_trim = pdata->xtal_trim; |
aaa1c4d2 AA |
1449 | return 0; |
1450 | } | |
fa2d3e94 | 1451 | |
aaa1c4d2 AA |
1452 | *rstn = of_get_named_gpio(spi->dev.of_node, "reset-gpio", 0); |
1453 | *slp_tr = of_get_named_gpio(spi->dev.of_node, "sleep-gpio", 0); | |
ccdaeb2b AA |
1454 | ret = of_property_read_u8(spi->dev.of_node, "xtal-trim", xtal_trim); |
1455 | if (ret < 0 && ret != -EINVAL) | |
1456 | return ret; | |
fa2d3e94 | 1457 | |
aaa1c4d2 | 1458 | return 0; |
fa2d3e94 AA |
1459 | } |
1460 | ||
c8ee0f56 AA |
1461 | static int |
1462 | at86rf230_detect_device(struct at86rf230_local *lp) | |
1463 | { | |
1464 | unsigned int part, version, val; | |
1465 | u16 man_id = 0; | |
1466 | const char *chip; | |
1467 | int rc; | |
1468 | ||
1469 | rc = __at86rf230_read(lp, RG_MAN_ID_0, &val); | |
1470 | if (rc) | |
1471 | return rc; | |
1472 | man_id |= val; | |
1473 | ||
1474 | rc = __at86rf230_read(lp, RG_MAN_ID_1, &val); | |
1475 | if (rc) | |
1476 | return rc; | |
1477 | man_id |= (val << 8); | |
1478 | ||
1479 | rc = __at86rf230_read(lp, RG_PART_NUM, &part); | |
1480 | if (rc) | |
1481 | return rc; | |
1482 | ||
7598968d | 1483 | rc = __at86rf230_read(lp, RG_VERSION_NUM, &version); |
c8ee0f56 AA |
1484 | if (rc) |
1485 | return rc; | |
1486 | ||
1487 | if (man_id != 0x001f) { | |
1488 | dev_err(&lp->spi->dev, "Non-Atmel dev found (MAN_ID %02x %02x)\n", | |
1489 | man_id >> 8, man_id & 0xFF); | |
1490 | return -EINVAL; | |
1491 | } | |
1492 | ||
2ac0f3a3 | 1493 | lp->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AACK | |
c8fc84ed | 1494 | IEEE802154_HW_TXPOWER | IEEE802154_HW_ARET | |
92f45f54 | 1495 | IEEE802154_HW_AFILT | IEEE802154_HW_PROMISCUOUS; |
c8ee0f56 | 1496 | |
b48a7c18 AA |
1497 | lp->hw->phy->cca.mode = NL802154_CCA_ENERGY; |
1498 | ||
c8ee0f56 AA |
1499 | switch (part) { |
1500 | case 2: | |
1501 | chip = "at86rf230"; | |
1502 | rc = -ENOTSUPP; | |
1503 | break; | |
1504 | case 3: | |
1505 | chip = "at86rf231"; | |
a53d1f7c | 1506 | lp->data = &at86rf231_data; |
5a504397 | 1507 | lp->hw->phy->channels_supported[0] = 0x7FFF800; |
fe58d016 | 1508 | lp->hw->phy->current_channel = 11; |
24ccb9f4 | 1509 | lp->hw->phy->symbol_duration = 16; |
c8ee0f56 AA |
1510 | break; |
1511 | case 7: | |
1512 | chip = "at86rf212"; | |
4ecc8a55 AY |
1513 | lp->data = &at86rf212_data; |
1514 | lp->hw->flags |= IEEE802154_HW_LBT; | |
1515 | lp->hw->phy->channels_supported[0] = 0x00007FF; | |
1516 | lp->hw->phy->channels_supported[2] = 0x00007FF; | |
1517 | lp->hw->phy->current_channel = 5; | |
1518 | lp->hw->phy->symbol_duration = 25; | |
c8ee0f56 AA |
1519 | break; |
1520 | case 11: | |
1521 | chip = "at86rf233"; | |
a53d1f7c | 1522 | lp->data = &at86rf233_data; |
5a504397 | 1523 | lp->hw->phy->channels_supported[0] = 0x7FFF800; |
fe58d016 | 1524 | lp->hw->phy->current_channel = 13; |
24ccb9f4 | 1525 | lp->hw->phy->symbol_duration = 16; |
c8ee0f56 AA |
1526 | break; |
1527 | default: | |
2b8b7e29 | 1528 | chip = "unknown"; |
c8ee0f56 AA |
1529 | rc = -ENOTSUPP; |
1530 | break; | |
1531 | } | |
1532 | ||
1533 | dev_info(&lp->spi->dev, "Detected %s chip version %d\n", chip, version); | |
1534 | ||
1535 | return rc; | |
1536 | } | |
1537 | ||
1d15d6b5 AA |
1538 | static void |
1539 | at86rf230_setup_spi_messages(struct at86rf230_local *lp) | |
1540 | { | |
2e0571c0 | 1541 | lp->state.lp = lp; |
cca990c8 | 1542 | lp->state.irq = lp->spi->irq; |
2e0571c0 AA |
1543 | spi_message_init(&lp->state.msg); |
1544 | lp->state.msg.context = &lp->state; | |
263be332 | 1545 | lp->state.trx.len = 2; |
2e0571c0 AA |
1546 | lp->state.trx.tx_buf = lp->state.buf; |
1547 | lp->state.trx.rx_buf = lp->state.buf; | |
1548 | spi_message_add_tail(&lp->state.trx, &lp->state.msg); | |
1549 | ||
1d15d6b5 | 1550 | lp->irq.lp = lp; |
cca990c8 | 1551 | lp->irq.irq = lp->spi->irq; |
1d15d6b5 AA |
1552 | spi_message_init(&lp->irq.msg); |
1553 | lp->irq.msg.context = &lp->irq; | |
263be332 | 1554 | lp->irq.trx.len = 2; |
1d15d6b5 AA |
1555 | lp->irq.trx.tx_buf = lp->irq.buf; |
1556 | lp->irq.trx.rx_buf = lp->irq.buf; | |
1557 | spi_message_add_tail(&lp->irq.trx, &lp->irq.msg); | |
1558 | ||
1559 | lp->tx.lp = lp; | |
cca990c8 | 1560 | lp->tx.irq = lp->spi->irq; |
1d15d6b5 AA |
1561 | spi_message_init(&lp->tx.msg); |
1562 | lp->tx.msg.context = &lp->tx; | |
263be332 | 1563 | lp->tx.trx.len = 2; |
1d15d6b5 AA |
1564 | lp->tx.trx.tx_buf = lp->tx.buf; |
1565 | lp->tx.trx.rx_buf = lp->tx.buf; | |
1566 | spi_message_add_tail(&lp->tx.trx, &lp->tx.msg); | |
1567 | } | |
1568 | ||
bb1f4606 | 1569 | static int at86rf230_probe(struct spi_device *spi) |
7b8e19b6 | 1570 | { |
5a504397 | 1571 | struct ieee802154_hw *hw; |
7b8e19b6 | 1572 | struct at86rf230_local *lp; |
f76014f7 | 1573 | unsigned int status; |
aaa1c4d2 | 1574 | int rc, irq_type, rstn, slp_tr; |
e3721749 | 1575 | u8 xtal_trim = 0; |
7b8e19b6 | 1576 | |
1577 | if (!spi->irq) { | |
1578 | dev_err(&spi->dev, "no IRQ specified\n"); | |
1579 | return -EINVAL; | |
1580 | } | |
1581 | ||
ccdaeb2b | 1582 | rc = at86rf230_get_pdata(spi, &rstn, &slp_tr, &xtal_trim); |
aaa1c4d2 AA |
1583 | if (rc < 0) { |
1584 | dev_err(&spi->dev, "failed to parse platform_data: %d\n", rc); | |
1585 | return rc; | |
43b5abe0 SH |
1586 | } |
1587 | ||
aaa1c4d2 AA |
1588 | if (gpio_is_valid(rstn)) { |
1589 | rc = devm_gpio_request_one(&spi->dev, rstn, | |
0679e29b | 1590 | GPIOF_OUT_INIT_HIGH, "rstn"); |
3fa27571 AA |
1591 | if (rc) |
1592 | return rc; | |
1593 | } | |
7b8e19b6 | 1594 | |
aaa1c4d2 AA |
1595 | if (gpio_is_valid(slp_tr)) { |
1596 | rc = devm_gpio_request_one(&spi->dev, slp_tr, | |
0679e29b | 1597 | GPIOF_OUT_INIT_LOW, "slp_tr"); |
7b8e19b6 | 1598 | if (rc) |
0679e29b | 1599 | return rc; |
7b8e19b6 | 1600 | } |
1601 | ||
1602 | /* Reset */ | |
aaa1c4d2 | 1603 | if (gpio_is_valid(rstn)) { |
3fa27571 | 1604 | udelay(1); |
aaa1c4d2 | 1605 | gpio_set_value(rstn, 0); |
3fa27571 | 1606 | udelay(1); |
aaa1c4d2 | 1607 | gpio_set_value(rstn, 1); |
3fa27571 AA |
1608 | usleep_range(120, 240); |
1609 | } | |
7b8e19b6 | 1610 | |
5a504397 AA |
1611 | hw = ieee802154_alloc_hw(sizeof(*lp), &at86rf230_ops); |
1612 | if (!hw) | |
640985ec AA |
1613 | return -ENOMEM; |
1614 | ||
5a504397 AA |
1615 | lp = hw->priv; |
1616 | lp->hw = hw; | |
640985ec | 1617 | lp->spi = spi; |
5a504397 | 1618 | hw->parent = &spi->dev; |
7c118c1a | 1619 | hw->vif_data_size = sizeof(*lp); |
f6f4e86a | 1620 | ieee802154_random_extended_addr(&hw->phy->perm_extended_addr); |
8fad346f | 1621 | |
f76014f7 AA |
1622 | lp->regmap = devm_regmap_init_spi(spi, &at86rf230_regmap_spi_config); |
1623 | if (IS_ERR(lp->regmap)) { | |
1624 | rc = PTR_ERR(lp->regmap); | |
1625 | dev_err(&spi->dev, "Failed to allocate register map: %d\n", | |
1626 | rc); | |
1627 | goto free_dev; | |
1628 | } | |
1629 | ||
1d15d6b5 AA |
1630 | at86rf230_setup_spi_messages(lp); |
1631 | ||
c8ee0f56 AA |
1632 | rc = at86rf230_detect_device(lp); |
1633 | if (rc < 0) | |
1634 | goto free_dev; | |
1635 | ||
8fad346f | 1636 | spin_lock_init(&lp->lock); |
2e0571c0 | 1637 | init_completion(&lp->state_complete); |
8fad346f PB |
1638 | |
1639 | spi_set_drvdata(spi, lp); | |
1640 | ||
ccdaeb2b | 1641 | rc = at86rf230_hw_init(lp, xtal_trim); |
7b8e19b6 | 1642 | if (rc) |
1d15d6b5 | 1643 | goto free_dev; |
7b8e19b6 | 1644 | |
19626946 AA |
1645 | /* Read irq status register to reset irq line */ |
1646 | rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &status); | |
7b8e19b6 | 1647 | if (rc) |
1d15d6b5 | 1648 | goto free_dev; |
7b8e19b6 | 1649 | |
1d15d6b5 AA |
1650 | irq_type = irq_get_trigger_type(spi->irq); |
1651 | if (!irq_type) | |
1652 | irq_type = IRQF_TRIGGER_RISING; | |
1653 | ||
1654 | rc = devm_request_irq(&spi->dev, spi->irq, at86rf230_isr, | |
1655 | IRQF_SHARED | irq_type, dev_name(&spi->dev), lp); | |
057dad6f | 1656 | if (rc) |
1d15d6b5 | 1657 | goto free_dev; |
057dad6f | 1658 | |
5a504397 | 1659 | rc = ieee802154_register_hw(lp->hw); |
7b8e19b6 | 1660 | if (rc) |
1d15d6b5 | 1661 | goto free_dev; |
7b8e19b6 | 1662 | |
1663 | return rc; | |
1664 | ||
640985ec | 1665 | free_dev: |
5a504397 | 1666 | ieee802154_free_hw(lp->hw); |
8fad346f | 1667 | |
7b8e19b6 | 1668 | return rc; |
1669 | } | |
1670 | ||
bb1f4606 | 1671 | static int at86rf230_remove(struct spi_device *spi) |
7b8e19b6 | 1672 | { |
1673 | struct at86rf230_local *lp = spi_get_drvdata(spi); | |
1674 | ||
17e84a92 AA |
1675 | /* mask all at86rf230 irq's */ |
1676 | at86rf230_write_subreg(lp, SR_IRQ_MASK, 0); | |
5a504397 AA |
1677 | ieee802154_unregister_hw(lp->hw); |
1678 | ieee802154_free_hw(lp->hw); | |
7b8e19b6 | 1679 | dev_dbg(&spi->dev, "unregistered at86rf230\n"); |
0679e29b | 1680 | |
7b8e19b6 | 1681 | return 0; |
1682 | } | |
1683 | ||
1086b4f6 | 1684 | static const struct of_device_id at86rf230_of_match[] = { |
fa2d3e94 AA |
1685 | { .compatible = "atmel,at86rf230", }, |
1686 | { .compatible = "atmel,at86rf231", }, | |
1687 | { .compatible = "atmel,at86rf233", }, | |
1688 | { .compatible = "atmel,at86rf212", }, | |
1689 | { }, | |
1690 | }; | |
835cb7d2 | 1691 | MODULE_DEVICE_TABLE(of, at86rf230_of_match); |
fa2d3e94 | 1692 | |
90b15520 AA |
1693 | static const struct spi_device_id at86rf230_device_id[] = { |
1694 | { .name = "at86rf230", }, | |
1695 | { .name = "at86rf231", }, | |
1696 | { .name = "at86rf233", }, | |
1697 | { .name = "at86rf212", }, | |
1698 | { }, | |
1699 | }; | |
1700 | MODULE_DEVICE_TABLE(spi, at86rf230_device_id); | |
1701 | ||
7b8e19b6 | 1702 | static struct spi_driver at86rf230_driver = { |
90b15520 | 1703 | .id_table = at86rf230_device_id, |
7b8e19b6 | 1704 | .driver = { |
fa2d3e94 | 1705 | .of_match_table = of_match_ptr(at86rf230_of_match), |
7b8e19b6 | 1706 | .name = "at86rf230", |
1707 | .owner = THIS_MODULE, | |
1708 | }, | |
1709 | .probe = at86rf230_probe, | |
bb1f4606 | 1710 | .remove = at86rf230_remove, |
7b8e19b6 | 1711 | }; |
1712 | ||
395a5738 | 1713 | module_spi_driver(at86rf230_driver); |
7b8e19b6 | 1714 | |
1715 | MODULE_DESCRIPTION("AT86RF230 Transceiver Driver"); | |
1716 | MODULE_LICENSE("GPL v2"); |